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CC3200寄存器详细手册 swru367b

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    CC3200 SimpleLink Wi-Fi and Internet-ofThings Solution, a Single Chip Wireless MCU Technical Reference Manual Literature Number: SWRU367B June 2014 – Revised October 2014 Contents 1 Architecture Overview......................................................................................................... 21 1.1 Introduction.................................................................................................................. 22 1.2 Architecture Overview ..................................................................................................... 23 1.3 Functional Overview ....................................................................................................... 24 1.3.1 Processor Core .................................................................................................... 24 1.3.2 Memory ............................................................................................................. 25 1.3.3 Micro Direct Memory Access Controller (uDMA).............................................................. 26 1.3.4 General Purpose Timer (GPT) .................................................................................. 26 1.3.5 Watch Dog Timer (WDT) ......................................................................................... 27 1.3.6 Multi-Channel Audio Serial Port (McASP) ..................................................................... 27 1.3.7 Serial Peripheral Interface (SPI)................................................................................. 27 1.3.8 Inter-Integrated Circuit Interface (I2C).......................................................................... 28 1.3.9 Universal Asynchronous Receiver/Transmitter (UART) ...................................................... 28 1.3.10 General Purpose Input / Output (GPIO)....................................................................... 29 1.3.11 Analog to Digital Converter (ADC) ............................................................................. 29 1.3.12 SD Card Host .................................................................................................... 29 1.3.13 Parallel Camera Interface ...................................................................................... 29 1.3.14 Debug Interface .................................................................................................. 29 1.3.15 Hardware Cryptography Accelerator........................................................................... 30 1.3.16 Clock, Reset and Power Management ........................................................................ 30 1.3.17 SimpleLink Subsystem .......................................................................................... 31 1.3.18 IO Pads and Pin Multiplexing................................................................................... 31 2 Cortex-M4 Processor .......................................................................................................... 32 2.1 Overview..................................................................................................................... 33 2.1.1 Block Diagram ..................................................................................................... 33 2.1.2 System-Level Interface ........................................................................................... 34 2.1.3 Integrated Configurable Debug.................................................................................. 34 2.1.4 Trace Port Interface Unit (TPIU) ................................................................................ 35 2.1.5 Cortex-M4 System Component Details......................................................................... 35 2.2 Functional Description ..................................................................................................... 35 2.2.1 Programming Model .............................................................................................. 35 2.2.2 Register Description .............................................................................................. 36 2.2.3 Memory Model ..................................................................................................... 40 2.2.4 Exception Model................................................................................................... 43 2.2.5 Fault Handling ..................................................................................................... 49 2.2.6 Power Management............................................................................................... 51 2.2.7 Instruction Set Summary ......................................................................................... 53 3 Cortex-M4 Peripherals......................................................................................................... 58 3.1 Overview..................................................................................................................... 59 3.2 Functional Description ..................................................................................................... 59 3.2.1 System Timer (SysTick) .......................................................................................... 59 3.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 60 3.2.3 System Control Block (SCB)..................................................................................... 61 3.3 Register Map................................................................................................................ 61 3.3.1 PERIPHERAL Registers ......................................................................................... 65 2 Contents SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4 Direct Memory Access (DMA) .............................................................................................. 96 4.1 Overview..................................................................................................................... 97 4.2 Functional Description ..................................................................................................... 97 4.2.1 Channel Assignment.............................................................................................. 98 4.2.2 Priority .............................................................................................................. 99 4.2.3 Arbitration Size .................................................................................................... 99 4.2.4 Channel Configuration ............................................................................................ 99 4.2.5 Transfer Mode.................................................................................................... 100 4.2.6 Transfer Size and Increment ................................................................................... 105 4.2.7 Peripheral Interface.............................................................................................. 106 4.2.8 Interrupts and Errors ............................................................................................ 106 4.3 Register Description ...................................................................................................... 107 4.3.1 DMA Register Map .............................................................................................. 107 4.3.2 µDMA Channel Control Structure.............................................................................. 108 4.3.3 DMA Registers ................................................................................................... 109 5 General-Purpose Input/Outputs (GPIOs) .............................................................................. 114 5.1 Overview ................................................................................................................... 115 5.2 Functional Description.................................................................................................... 115 5.2.1 Data Control ...................................................................................................... 116 5.3 Interrupt Control........................................................................................................... 117 5.3.1 μDMA Trigger Source ........................................................................................... 117 5.4 Initialization and Configuration .......................................................................................... 117 5.5 GPIO_REGISTER_MAP Registers..................................................................................... 119 5.5.1 GPIO Register Description ..................................................................................... 119 6 Universal Asynchronous Receivers/Transmitters (UARTs) .................................................... 131 6.1 Overview ................................................................................................................... 132 6.1.1 Block Diagram.................................................................................................... 133 6.2 Functional Description.................................................................................................... 133 6.2.1 Transmit/Receive Logic ......................................................................................... 133 6.2.2 Baud-Rate Generation .......................................................................................... 134 6.2.3 Data Transmission............................................................................................... 134 6.2.4 Initialization and Configuration ................................................................................. 137 6.3 Register Description ...................................................................................................... 138 6.3.1 UART Registers.................................................................................................. 139 7 Inter-Integrated Circuit (I2C) Interface ................................................................................. 161 7.1 Overview ................................................................................................................... 162 7.1.1 Block Diagram.................................................................................................... 163 7.1.2 Signal Description ............................................................................................... 163 7.2 Functional Description.................................................................................................... 164 7.2.1 I2C Bus Functional Overview .................................................................................. 164 7.2.2 Supported Speed Modes ....................................................................................... 168 7.2.3 Interrupts .......................................................................................................... 169 7.2.4 Loopback Operation ............................................................................................. 169 7.2.5 FIFO and µDMA Operation..................................................................................... 169 7.2.6 Command Sequence Flow Charts............................................................................. 171 7.2.7 Initialization and Configuration ................................................................................. 178 7.3 Register Map .............................................................................................................. 179 7.3.1 I2C Registers ..................................................................................................... 180 8 SPI (Serial Peripheral Interface) .......................................................................................... 219 8.1 Overview ................................................................................................................... 220 8.1.1 Features........................................................................................................... 221 8.2 Functional Description.................................................................................................... 221 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Contents 3 www.ti.com 8.2.1 SPI interface...................................................................................................... 221 8.2.2 SPI Transmission ................................................................................................ 221 8.2.3 Master Mode ..................................................................................................... 225 8.2.4 Slave Mode ....................................................................................................... 233 8.2.5 Interrupts .......................................................................................................... 235 8.2.6 DMA Requests ................................................................................................... 235 8.2.7 Reset .............................................................................................................. 236 8.3 Initialization and Configuration .......................................................................................... 236 8.3.1 Basic Initialization................................................................................................ 236 8.3.2 Master Mode Operation without Interrupt (Polling) .......................................................... 236 8.3.3 Slave Mode Operation with Interrupt .......................................................................... 237 8.3.4 Generic Interrupt Handler Implementation ................................................................... 237 8.4 Access to Data Registers................................................................................................ 238 8.5 Module Initialization....................................................................................................... 238 8.5.1 Common Transfer Sequence................................................................................... 238 8.5.2 End of Transfer Sequences .................................................................................... 239 8.5.3 FIFO Mode........................................................................................................ 240 8.6 SPI Registers.............................................................................................................. 244 8.6.1 SPI Register Description........................................................................................ 245 9 General-Purpose Timers .................................................................................................... 260 9.1 Overview ................................................................................................................... 261 9.2 Block Diagram............................................................................................................. 262 9.3 Functional Description.................................................................................................... 262 9.3.1 GPTM Reset Conditions ........................................................................................ 263 9.3.2 Timer Modes ..................................................................................................... 263 9.3.3 DMA Operation................................................................................................... 269 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................... 269 9.4 Initialization and Configuration .......................................................................................... 270 9.4.1 One-Shot/Periodic Timer Mode ................................................................................ 270 9.4.2 Input Edge-Count Mode......................................................................................... 270 9.4.3 Input Edge Time Mode.......................................................................................... 271 9.4.4 PWM Mode ....................................................................................................... 271 9.5 TIMER Registers.......................................................................................................... 273 9.5.1 GPT Register Description....................................................................................... 273 10 Watchdog Timer ............................................................................................................... 303 10.1 Overview ................................................................................................................... 304 10.1.1 Block Diagram................................................................................................... 304 10.2 Functional Description.................................................................................................... 305 10.2.1 Initialization and Configuration ................................................................................ 305 10.3 Register Map .............................................................................................................. 305 10.3.1 Register Description............................................................................................ 306 10.4 MCU Watch Dog Controller Usage Caveats .......................................................................... 314 10.4.1 System WatchDog.............................................................................................. 314 10.4.2 System WatchDog Recovery Sequence..................................................................... 315 11 SDHost Controller Interface ............................................................................................... 317 11.1 Overview ................................................................................................................... 318 11.2 1-Bit SD Interface......................................................................................................... 319 11.2.1 Clock and Reset Management................................................................................ 319 11.3 Initialization and configuration using Peripheral APIs................................................................ 320 11.3.1 Basic Initialization and Configuration......................................................................... 320 11.3.2 Sending Command ............................................................................................. 320 11.3.3 Card Detection and Initialization .............................................................................. 321 11.3.4 Block Read ...................................................................................................... 323 4 Contents SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.5 Block Write ...................................................................................................... 324 11.4 Performance and Testing................................................................................................ 325 11.5 Peripheral Library APIs .................................................................................................. 325 12 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port ................................................. 330 12.1 Overview ................................................................................................................... 331 12.1.1 I2S Format....................................................................................................... 331 12.2 Functional Description.................................................................................................... 332 12.3 Programming Model ...................................................................................................... 332 12.3.1 Clock and Reset Management................................................................................ 332 12.3.2 I2S Data Port Interface......................................................................................... 333 12.3.3 Initialization and Configuration ................................................................................ 333 12.4 Peripheral Library APIs for I2S Configuration......................................................................... 335 12.4.1 Basic APIs for Enabling and Configuring the Interface .................................................... 335 12.4.2 APIs for Data Access if DMA is Not Used................................................................... 338 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral....................... 340 12.4.4 APIs to Control FIFO Structures Associated with I2S Peripheral ........................................ 344 13 Analog-to-Digital Converter [ADC] ...................................................................................... 346 13.1 Overview ................................................................................................................... 347 13.2 Key Features .............................................................................................................. 347 13.3 ADC Register Mapping................................................................................................... 348 13.4 ADC_MODULE Registers ............................................................................................... 349 13.4.1 ADC Register Description ..................................................................................... 349 13.5 Initialization and Configuration ......................................................................................... 370 13.6 Peripheral Library APIs for ADC Operation ........................................................................... 371 13.6.1 Overview ......................................................................................................... 371 13.6.2 Configuring the ADC Channels ............................................................................... 371 13.6.3 Basic APIs for Enabling and Configuring the Interface .................................................... 371 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup] ........................................ 372 13.6.5 APIs for Interrupt Usage ....................................................................................... 374 13.6.6 APIs for Setting Up ADC Timer for Time Stamping the Samples ........................................ 376 14 Parallel Camera Interface Module ....................................................................................... 378 14.1 Overview ................................................................................................................... 379 14.2 Image Sensor Interface .................................................................................................. 379 14.3 Functional Description.................................................................................................... 380 14.3.1 Modes of Operation ............................................................................................ 380 14.3.2 FIFO Buffer ...................................................................................................... 382 14.3.3 Reset ............................................................................................................. 383 14.3.4 Clock Generation ............................................................................................... 383 14.3.5 Interrupt Generation ............................................................................................ 383 14.3.6 DMA Interface ................................................................................................... 384 14.4 Programming Model ...................................................................................................... 384 14.4.1 Camera Core Reset ............................................................................................ 384 14.4.2 Enable the Picture Acquisition ................................................................................ 384 14.4.3 Disable the Picture Acquisition................................................................................ 385 14.5 Interrupt Handling......................................................................................................... 385 14.5.1 FIFO_OF_IRQ (FIFO overflow) ............................................................................... 385 14.5.2 FIFO_UF_IRQ (FIFO underflow) ............................................................................. 385 14.6 Camera Interface Module Functional Registers ...................................................................... 386 14.6.1 Functional Register Description............................................................................... 386 14.6.2 Peripheral Library APIs ........................................................................................ 397 14.7 Developer’s Guide ........................................................................................................ 400 14.7.1 Using Peripheral Driver APIs for Capturing an Image ..................................................... 400 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Contents 5 www.ti.com 14.7.2 Using Peripheral Driver APIs for Communicating with Image Sensors.................................. 402 15 Power, Reset and Clock Management ................................................................................. 404 15.1 Overview ................................................................................................................... 405 15.1.1 VBAT Wide-Voltage Connection.............................................................................. 405 15.1.2 Pre-regulated 1.85 V ........................................................................................... 405 15.1.3 Supply Brownout and Blackout ............................................................................... 407 15.1.4 Application Processor Power Modes......................................................................... 407 15.2 Power Management Control Architecture ............................................................................. 409 15.2.1 Global Power-Reset-Clock Manager (GPRCM) ............................................................ 411 15.2.2 Application Reset-Clock Manager (ARCM) ................................................................. 412 15.3 PRCM APIs................................................................................................................ 412 15.3.1 MCU Initialization ............................................................................................... 412 15.3.2 Reset Control.................................................................................................... 412 15.3.3 Peripheral Reset ................................................................................................ 412 15.3.4 Reset Cause..................................................................................................... 413 15.3.5 Clock Control .................................................................................................... 413 15.3.6 Low Power Modes .............................................................................................. 413 15.3.7 Sleep (SLEEP) .................................................................................................. 414 15.3.8 Deep Sleep (DEEPSLEEP) ................................................................................... 414 15.3.9 Low Power Deep Sleep (LPDS) .............................................................................. 415 15.3.10 Hibernate (HIB) ................................................................................................ 416 15.3.11 Slow Clock Counter ........................................................................................... 418 15.4 Peripheral Macros ........................................................................................................ 418 15.5 Power Management Framework........................................................................................ 419 15.6 PRCM Registers .......................................................................................................... 420 15.6.1 PRCM Register Description ................................................................................... 421 16 IO Pads and Pin Multiplexing ............................................................................................. 472 16.1 Overview ................................................................................................................... 473 16.2 IO Pad Electrical Specifications:........................................................................................ 473 16.3 Analog-Digital Pin Multiplexing.......................................................................................... 475 16.4 Special Ana/DIG Pins .................................................................................................... 476 16.4.1 Pin 45 and 52:................................................................................................... 476 16.4.2 Pin 29 and 30:................................................................................................... 478 16.4.3 Pin 57, 58, 59, 60: .............................................................................................. 478 16.5 Analog Mux Control Registers .......................................................................................... 478 16.6 Pins Available for Applications .......................................................................................... 480 16.7 Functional Pin Mux Configurations ..................................................................................... 482 16.8 Pin Mapping Recommendations ........................................................................................ 496 16.8.1 Pad Configuration Registers for Application Pins .......................................................... 497 16.8.2 PAD Behavior During Reset and Hibernate................................................................. 499 16.8.3 Control Architecture ............................................................................................ 499 16.8.4 CC3200 Pin-mux Examples ................................................................................... 499 16.8.5 Wake on Pad .................................................................................................... 502 16.8.6 Sense on Power ................................................................................................ 502 A Software Development Kit Examples................................................................................... 505 B CC3200 Miscellaneous Registers........................................................................................ 506 B.1 Miscellaneous Register Summary ...................................................................................... 506 B.1.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] ......................................................... 507 B.1.2 DMA_IMS Register (offset = 90h) [reset = 0h]............................................................... 509 B.1.3 DMA_IMC Register (offset = 94h) [reset = 0h]............................................................... 511 B.1.4 DMA_ICR Register (offset = 9Ch) [reset = 0h] .............................................................. 513 B.1.5 DMA_MIS Register (offset = A0h) [reset = 0h] .............................................................. 515 6 Contents SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.6 DMA_RIS Register (offset = A4h) [reset = 0h]............................................................... 517 B.1.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h].......................................................... 519 Revision History B ..................................................................................................................... 520 Revision History A ..................................................................................................................... 520 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Contents 7 www.ti.com List of Figures 1-1. CC3200 MCU + WIFI System-On-Chip ................................................................................. 23 2-1. Application CPU Block Diagram.......................................................................................... 34 2-2. TPIU Block Diagram ....................................................................................................... 35 2-3. Cortex-M4 Register Set ................................................................................................... 37 2-4. Data Storage................................................................................................................ 42 2-5. Vector Table ................................................................................................................ 47 2-6. Exception Stack Frame.................................................................................................... 49 2-7. Power Management Architecture in CC3200 SoC..................................................................... 52 3-1. ACTLR Register ............................................................................................................ 66 3-2. STCTRL Register .......................................................................................................... 67 3-3. STRELOAD Register ...................................................................................................... 68 3-4. STCURRENT Register .................................................................................................... 69 3-5. EN_0 to EN_6 Register.................................................................................................... 70 3-6. DIS_0 to DIS_6 Register .................................................................................................. 71 3-7. PEND_0 to PEND_6 Register ............................................................................................ 72 3-8. UNPEND_0 to UNPEND_6 Register .................................................................................... 73 3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................ 74 3-10. PRI_0 to PRI_49 Register................................................................................................. 75 3-11. CPUID Register............................................................................................................. 76 3-12. INTCTRL Register.......................................................................................................... 77 3-13. VTABLE Register........................................................................................................... 79 3-14. APINT Register ............................................................................................................. 80 3-15. SYSCTRL Register ........................................................................................................ 81 3-16. CFGCTRL Register ........................................................................................................ 82 3-17. SYSPRI1 Register.......................................................................................................... 84 3-18. SYSPRI2 Register.......................................................................................................... 85 3-19. SYSPRI3 Register.......................................................................................................... 86 3-20. SYSHNDCTRL Register................................................................................................... 87 3-21. FAULTSTAT Register ..................................................................................................... 89 3-22. HFAULTSTAT Register.................................................................................................... 93 3-23. FAULTDDR Register....................................................................................................... 94 3-24. SWTRIG Register .......................................................................................................... 95 4-1. DMA Channel Assignment ................................................................................................ 98 4-2. Ping-Pong Mode .......................................................................................................... 102 4-3. Memory Scatter-Gather Mode .......................................................................................... 104 4-4. Peripheral Scatter-Gather Mode ........................................................................................ 105 4-5. DMA_SRCENDP Register............................................................................................... 110 4-6. DMA_DSTENDP Register ............................................................................................... 111 4-7. DMA_CHCTL Register ................................................................................................... 112 5-1. Digital I/O Pads ........................................................................................................... 115 5-2. GPIODATA Write Example .............................................................................................. 116 5-3. GPIODATA Read Example.............................................................................................. 116 5-4. GPIODATA Register ..................................................................................................... 120 5-5. GPIODIR Register ........................................................................................................ 121 5-6. GPIOIS Register .......................................................................................................... 122 5-7. GPIOIBE Register ........................................................................................................ 123 5-8. GPIOIEV Register ........................................................................................................ 124 8 List of Figures SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5-9. GPIOIM Register.......................................................................................................... 125 5-10. GPIORIS Register ........................................................................................................ 126 5-11. GPIOMIS Register ........................................................................................................ 127 5-12. GPIOICR Register ........................................................................................................ 128 6-1. UART Module Block Diagram........................................................................................... 133 6-2. UART Character Frame.................................................................................................. 134 6-3. UARTDR Register ........................................................................................................ 140 6-4. UARTRSR_UARTECR Register........................................................................................ 141 6-5. UARTFR Register ........................................................................................................ 143 6-6. UARTFBRD Register..................................................................................................... 146 6-7. UARTLCRH Register..................................................................................................... 147 6-8. UARTCTL Register ....................................................................................................... 149 6-9. UARTIFLS Register ...................................................................................................... 151 6-10. UARTIM Register ......................................................................................................... 152 6-11. UARTRIS Register........................................................................................................ 154 6-12. UARTMIS Register ....................................................................................................... 156 6-13. UARTICR Register ....................................................................................................... 158 6-14. UARTDMACTL Register ................................................................................................. 160 7-1. I2C Block Diagram........................................................................................................ 163 7-2. I2C Bus Configuration.................................................................................................... 164 7-3. START and STOP Conditions .......................................................................................... 165 7-4. Complete Data Transfer with a 7-Bit Address ........................................................................ 165 7-5. R/S Bit in First Byte....................................................................................................... 165 7-6. Data Validity During Bit Transfer on the I2C Bus..................................................................... 166 7-7. Master Single TRANSMIT ............................................................................................... 172 7-8. Master Single RECEIVE ................................................................................................. 173 7-9. Master TRANSMIT of Multiple Data Bytes ............................................................................ 174 7-10. Master RECEIVE of Multiple Data Bytes .............................................................................. 175 7-11. Master RECEIVE with Repeated START after Master TRANSMIT................................................ 176 7-12. Master TRANSMIT with Repeated START after Master RECEIVE................................................ 177 7-13. Slave Command Sequence ............................................................................................. 178 7-14. I2CMSA Register ......................................................................................................... 181 7-15. I2CMCS Register ......................................................................................................... 182 7-16. I2CMDR Register ......................................................................................................... 184 7-17. I2CMTPR Register........................................................................................................ 185 7-18. I2CMIMR Register ........................................................................................................ 186 7-19. I2CMRIS Register ........................................................................................................ 188 7-20. I2CMMIS Register ........................................................................................................ 190 7-21. I2CMICR Register ........................................................................................................ 192 7-22. I2CMCR Register ......................................................................................................... 194 7-23. I2CMCLKOCNT Register ................................................................................................ 195 7-24. I2CMBMON Register ..................................................................................................... 196 7-25. I2CMBLEN Register ...................................................................................................... 197 7-26. I2CMBCNT Register...................................................................................................... 198 7-27. I2CSOAR Register........................................................................................................ 199 7-28. I2CSCSR Register........................................................................................................ 200 7-29. I2CSDR Register.......................................................................................................... 202 7-30. I2CSIMR Register ........................................................................................................ 203 7-31. I2CSRIS Register ......................................................................................................... 205 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Figures 9 www.ti.com 7-32. I2CSMIS Register......................................................................................................... 207 7-33. I2CSICR Register......................................................................................................... 209 7-34. I2CSOAR2 Register ...................................................................................................... 211 7-35. I2CSACKCTL Register................................................................................................... 212 7-36. I2CFIFODATA Register .................................................................................................. 213 7-37. I2CFIFOCTL Register .................................................................................................... 214 7-38. I2CFIFOSTATUS Register .............................................................................................. 216 7-39. I2CPP Register............................................................................................................ 217 7-40. I2CPC Register ........................................................................................................... 218 8-1. SPI Block Diagram........................................................................................................ 220 8-2. SPI full duplex transmission (Example) ................................................................................ 222 8-3. Full duplex single transfer format with PHA = 0 ...................................................................... 224 8-4. Full duplex single transfer format with PHA = 1 ...................................................................... 225 8-5. Contiguous Transfers with SPIEN Kept Active (2 Data Pins Interface Mode) .................................... 227 8-6. Transmit/receive mode with no FIFO used............................................................................ 229 8-7. Transmit/receive mode with only receive FIFO enabled............................................................. 229 8-8. Transmit/receive mode with only transmit FIFO used ............................................................... 230 8-9. Transmit/receive mode with both FIFO direction used .............................................................. 230 8-10. Buffer Almost Full Level (AFL) .......................................................................................... 231 8-11. Buffer Almost Empty Level (AEL)....................................................................................... 231 8-12. 3-Pin Mode System Overview........................................................................................... 232 8-13. Flow Chart - Module Initialization ....................................................................................... 238 8-14. Flow Chart - Common Transfer Sequence ............................................................................ 239 8-15. Flow Chart - Transmit and Receive (Master and Slave)............................................................. 240 8-16. Flow Chart - FIFO Mode Common Sequence (Master) ............................................................. 242 8-17. Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master) ...................................... 243 8-18. Flow Chart - FIFO Mode Transmit and Receive without Word Count (Master) .................................. 244 8-19. SPI_SYSCONFIG Register.............................................................................................. 246 8-20. SPI_SYSSTATUS Register.............................................................................................. 247 8-21. SPI_IRQSTATUS Register .............................................................................................. 248 8-22. SPI_IRQENABLE Register .............................................................................................. 250 8-23. SPI_MODULCTRL Register............................................................................................. 251 8-24. SPI_CHCONF Register .................................................................................................. 252 8-25. SPI_CHSTAT Register................................................................................................... 255 8-26. SPI_CHCTRL Register................................................................................................... 256 8-27. SPI_TX Register .......................................................................................................... 257 8-28. SPI_RX Register.......................................................................................................... 258 8-29. SPI_XFERLEVEL Register .............................................................................................. 259 9-1. GPTM Module Block Diagram .......................................................................................... 262 9-2. Input Edge-Count Mode Example, Counting Down .................................................................. 266 9-3. 16-Bit Input Edge-Time Mode Example................................................................................ 267 9-4. 16-Bit PWM Mode Example ............................................................................................. 269 9-5. GPTMCFG Register ...................................................................................................... 274 9-6. GPTMTAMR Register .................................................................................................... 275 9-7. GPTMTBMR Register .................................................................................................... 277 9-8. GPTMCTL Register....................................................................................................... 279 9-9. GPTMIMR Register....................................................................................................... 281 9-10. GPTMRIS Register ....................................................................................................... 283 9-11. GPTMMIS Register....................................................................................................... 285 10 List of Figures SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9-12. GPTMICR Register ....................................................................................................... 287 9-13. GPTMTAILR Register .................................................................................................... 289 9-14. GPTMTBILR Register .................................................................................................... 290 9-15. GPTMTAMATCHR Register............................................................................................. 291 9-16. GPTMTBMATCHR Register............................................................................................. 292 9-17. GPTMTAPR Register .................................................................................................... 293 9-18. GPTMTBPR Register .................................................................................................... 294 9-19. GPTMTAPMR Register .................................................................................................. 295 9-20. GPTMTBPMR Register .................................................................................................. 296 9-21. GPTMTAR Register ...................................................................................................... 297 9-22. GPTMTBR Register ...................................................................................................... 298 9-23. GPTMTAV Register ...................................................................................................... 299 9-24. GPTMTBV Register ...................................................................................................... 300 9-25. GPTMDMAEV Register .................................................................................................. 301 10-1. WDT Module Block Diagram ............................................................................................ 304 10-2. WDTLOAD Register ...................................................................................................... 308 10-3. WDTVALUE Register .................................................................................................... 309 10-4. WDTCTL Register ........................................................................................................ 310 10-5. WDTICR Register......................................................................................................... 311 10-6. WDTRIS Register......................................................................................................... 312 10-7. WDTTEST Register ...................................................................................................... 313 10-8. WDTLOCK Register ...................................................................................................... 314 10-9. WatchDog Flow Chart.................................................................................................... 315 10-10. System WatchDog Recovery Sequence............................................................................... 316 12-1. I2S Protocol................................................................................................................ 331 12-2. MCASP Module ........................................................................................................... 332 12-3. Logical Clock Path........................................................................................................ 333 13-1. Architecture of the ADC Module in CC3200 .......................................................................... 347 13-2. Operation of the ADC .................................................................................................... 348 13-3. ADC_CTRL Register ..................................................................................................... 350 13-4. ADC_CH0_IRQ_EN Register ........................................................................................... 351 13-5. ADC_CH2_IRQ_EN Register ........................................................................................... 352 13-6. ADC_CH4_IRQ_EN Register ........................................................................................... 353 13-7. ADC_CH6_IRQ_EN Register ........................................................................................... 354 13-8. ADC_CH0_IRQ_STATUS Register .................................................................................... 355 13-9. ADC_CH2_IRQ_STATUS Register .................................................................................... 356 13-10. ADC_CH4_IRQ_STATUS Register .................................................................................... 357 13-11. ADC_CH6_IRQ_STATUS Register .................................................................................... 358 13-12. ADC_DMA_MODE_EN Register ....................................................................................... 359 13-13. ADC_TIMER_CONFIGURATION Register............................................................................ 360 13-14. ADC_TIMER_CURRENT_COUNT Register .......................................................................... 361 13-15. CHANNEL0FIFODATA Register........................................................................................ 362 13-16. CHANNEL2FIFODATA Register........................................................................................ 363 13-17. CHANNEL4FIFODATA Register........................................................................................ 364 13-18. CHANNEL6FIFODATA Register........................................................................................ 365 13-19. ADC_CH0_FIFO_LVL Register ......................................................................................... 366 13-20. ADC_CH2_FIFO_LVL Register ......................................................................................... 367 13-21. ADC_CH4_FIFO_LVL Register ......................................................................................... 368 13-22. ADC_CH6_FIFO_LVL Register ......................................................................................... 369 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Figures 11 www.ti.com 13-23. ADC_CH_ENABLE Register ............................................................................................ 370 14-1. The Camera Module Interfaces ......................................................................................... 379 14-2. Synchronization Signals and Frame Timing........................................................................... 380 14-3. Synchronization Signals and Data Timing............................................................................. 380 14-4. Different Scenarios of CAM_P_HS and CAM_P_VS ................................................................ 381 14-5. CAM_P_HS Toggles Between Pixels in Decimation................................................................. 381 14-6. Parallel Camera I/F State Machine..................................................................................... 381 14-7. FIFO Image Data Format ................................................................................................ 382 14-8. Assertion and De-assertion of the DMA Request Signal ............................................................ 384 14-9. CC_SYSCONFIG Register .............................................................................................. 387 14-10. CC_SYSSTATUS Register .............................................................................................. 388 14-11. CC_IRQSTATUS Register............................................................................................... 389 14-12. CC_IRQENABLE Register............................................................................................... 391 14-13. CC_CTRL Register ....................................................................................................... 393 14-14. CC_CTRL_DMA Register ............................................................................................... 395 14-15. CC_CTRL_XCLK Register .............................................................................................. 396 14-16. CC_FIFODATA Register................................................................................................. 397 15-1. Power Management Unit Supports Two Supply Configurations.................................................... 406 15-2. Sleep Modes .............................................................................................................. 409 15-3. Power Management Control Architecture in CC3200................................................................ 411 15-4. CAMCLKCFG Register .................................................................................................. 422 15-5. CAMCLKEN Register .................................................................................................... 423 15-6. CAMSWRST Register.................................................................................................... 424 15-7. MCASPCLKEN Register................................................................................................. 425 15-8. MCASPSWRST Register ................................................................................................ 426 15-9. SDIOMCLKCFG Register................................................................................................ 427 15-10. SDIOMCLKEN Register.................................................................................................. 428 15-11. SDIOMSWRST Register................................................................................................. 429 15-12. APSPICLKCFG Register................................................................................................. 430 15-13. APSPICLKEN Register .................................................................................................. 431 15-14. APSPISWRST Register.................................................................................................. 432 15-15. DMACLKEN Register .................................................................................................... 433 15-16. DMASWRST Register.................................................................................................... 434 15-17. GPIO0CLKEN Register .................................................................................................. 435 15-18. GPIO0SWRST Register ................................................................................................. 436 15-19. GPIO1CLKEN Register .................................................................................................. 437 15-20. GPIO1SWRST Register ................................................................................................. 438 15-21. GPIO2CLKEN Register .................................................................................................. 439 15-22. GPIO2SWRST Register ................................................................................................. 440 15-23. GPIO3CLKEN Register .................................................................................................. 441 15-24. GPIO3SWRST Register ................................................................................................. 442 15-25. GPIO4CLKEN Register .................................................................................................. 443 15-26. GPIO4SWRST Register ................................................................................................. 444 15-27. WDTCLKEN Register .................................................................................................... 445 15-28. WDTSWRST Register.................................................................................................... 446 15-29. UART0CLKEN Register.................................................................................................. 447 15-30. UART0SWRST Register................................................................................................. 448 15-31. UART1CLKEN Register.................................................................................................. 449 15-32. UART1SWRST Register................................................................................................. 450 12 List of Figures SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15-33. GPT0CLKCFG Register ................................................................................................. 451 15-34. GPT0SWRST Register................................................................................................... 452 15-35. GPT1CLKEN Register ................................................................................................... 453 15-36. GPT1SWRST Register................................................................................................... 454 15-37. GPT2CLKEN Register ................................................................................................... 455 15-38. GPT2SWRST Register................................................................................................... 456 15-39. GPT3CLKEN Register ................................................................................................... 457 15-40. GPT3SWRST Register................................................................................................... 458 15-41. MCASPCLKCFG0 Register ............................................................................................. 459 15-42. MCASPCLKCFG1 Register ............................................................................................. 460 15-43. I2CLCKEN Register ...................................................................................................... 461 15-44. I2CSWRST Register ..................................................................................................... 462 15-45. LPDSREQ Register....................................................................................................... 463 15-46. TURBOREQ Register .................................................................................................... 464 15-47. DSLPWAKECFG Register............................................................................................... 465 15-48. DSLPTIMRCFG Register ................................................................................................ 466 15-49. SLPWAKEEN Register................................................................................................... 467 15-50. SLPTMRCFG Register................................................................................................... 468 15-51. WAKENWP Register ..................................................................................................... 469 15-52. RCM_IS Register ......................................................................................................... 470 15-53. RCM_IEN Register ....................................................................................................... 471 16-1. Board Configuration to use Pins 45 and 52 as Digital Signals ..................................................... 476 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals ..................................................... 477 16-3. IO Pad Data and Control Path Architecture in CC3200 ............................................................. 499 16-4. Wake on Pad for Hibernate Mode ...................................................................................... 502 B-1. DMA_IMR Register ....................................................................................................... 507 B-2. DMA_IMS Register ....................................................................................................... 509 B-3. DMA_IMC Register ....................................................................................................... 511 B-4. DMA_ICR Register ....................................................................................................... 513 B-5. DMA_MIS Register ....................................................................................................... 515 B-6. DMA_RIS Register ....................................................................................................... 517 B-7. GPTTRIGSEL Register .................................................................................................. 519 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Figures 13 www.ti.com List of Tables 2-1. Summary of Processor Mode, Privilege level, and Stack Use ....................................................... 36 2-2. Processor Register Map................................................................................................... 37 2-3. PSR Register Combinations .............................................................................................. 39 2-4. Memory Map ................................................................................................................ 40 2-5. SRAM Memory Bit-banding Regions .................................................................................... 41 2-6. Exception Types............................................................................................................ 45 2-7. CC3200 Application Processor Interrupts............................................................................... 45 2-8. Faults ........................................................................................................................ 49 2-9. Fault Status and Fault Address Registers .............................................................................. 51 2-10. Cortex-M4 Instruction Summary.......................................................................................... 53 3-1. Core Peripheral Register Regions ....................................................................................... 59 3-2. Peripherals Register Map ................................................................................................. 61 3-3. PERIPHERAL REGISTERS .............................................................................................. 65 3-4. ACTLR Register Field Descriptions...................................................................................... 66 3-5. STCTRL Register Field Descriptions .................................................................................... 67 3-6. STRELOAD Register Field Descriptions ................................................................................ 68 3-7. STCURRENT Register Field Descriptions .............................................................................. 69 3-8. EN_0 to EN_6 Register Field Descriptions ............................................................................. 70 3-9. DIS_0 to DIS_6 Register Field Descriptions............................................................................ 71 3-10. PEND_0 to PEND_6 Register Field Descriptions...................................................................... 72 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions .............................................................. 73 3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions ................................................................. 74 3-13. PRI_0 to PRI_49 Register Field Descriptions .......................................................................... 75 3-14. CPUID Register Field Descriptions ...................................................................................... 76 3-15. INTCTRL Register Field Descriptions ................................................................................... 77 3-16. VTABLE Register Field Descriptions .................................................................................... 79 3-17. APINT Register Field Descriptions....................................................................................... 80 3-18. SYSCTRL Register Field Descriptions .................................................................................. 81 3-19. CFGCTRL Register Field Descriptions .................................................................................. 82 3-20. SYSPRI1 Register Field Descriptions ................................................................................... 84 3-21. SYSPRI2 Register Field Descriptions ................................................................................... 85 3-22. SYSPRI3 Register Field Descriptions ................................................................................... 86 3-23. SYSHNDCTRL Register Field Descriptions ............................................................................ 87 3-24. FAULTSTAT Register Field Descriptions ............................................................................... 89 3-25. HFAULTSTAT Register Field Descriptions ............................................................................. 93 3-26. FAULTDDR Register Field Descriptions ................................................................................ 94 3-27. SWTRIG Register Field Descriptions.................................................................................... 95 4-1. Channel Control Memory.................................................................................................. 99 4-2. Individual Control Structure.............................................................................................. 100 4-3. 8-bit Data Peripheral Configuration..................................................................................... 105 4-4. µDMA Register Map...................................................................................................... 107 4-5. DMA Registers ............................................................................................................ 109 4-6. DMA_SRCENDP Register Field Descriptions ........................................................................ 110 4-7. DMA_DSTENDP Register Field Descriptions......................................................................... 111 4-8. DMA_CHCTL Register Field Descriptions............................................................................. 112 5-1. GPIO Pad Configuration Examples .................................................................................... 117 5-2. GPIO Interrupt Configuration Example................................................................................. 118 14 List of Tables SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5-3. GPIO_REGISTER_MAP Registers..................................................................................... 119 5-4. GPIODATA Register Field Descriptions ............................................................................... 120 5-5. GPIODIR Register Field Descriptions.................................................................................. 121 5-6. GPIOIS Register Field Descriptions.................................................................................... 122 5-7. GPIOIBE Register Field Descriptions .................................................................................. 123 5-8. GPIOIEV Register Field Descriptions .................................................................................. 124 5-9. GPIOIM Register Field Descriptions ................................................................................... 125 5-10. GPIORIS Register Field Descriptions .................................................................................. 126 5-11. GPIOMIS Register Field Descriptions.................................................................................. 127 5-12. GPIOICR Register Field Descriptions.................................................................................. 128 5-13. GPIO_TRIG_EN Register Field Descriptions ......................................................................... 129 5-14. GPIO Mapping ............................................................................................................ 129 6-1. Flow Control Mode........................................................................................................ 135 6-2. UART Register Map ...................................................................................................... 138 6-3. UART REGISTERS....................................................................................................... 139 6-4. UARTDR Register Field Descriptions .................................................................................. 140 6-5. UARTRSR_UARTECR Register Field Descriptions.................................................................. 141 6-6. UARTFR Register Field Descriptions .................................................................................. 143 6-7. UARTIBRD Register Field Descriptions ............................................................................... 145 6-8. UARTFBRD Register Field Descriptions .............................................................................. 146 6-9. UARTLCRH Register Field Descriptions .............................................................................. 147 6-10. UARTCTL Register Field Descriptions................................................................................. 149 6-11. UARTIFLS Register Field Descriptions ................................................................................ 151 6-12. UARTIM Register Field Descriptions................................................................................... 152 6-13. UARTRIS Register Field Descriptions ................................................................................. 154 6-14. UARTMIS Register Field Descriptions ................................................................................. 156 6-15. UARTICR Register Field Descriptions ................................................................................. 158 6-16. UARTDMACTL Register Field Descriptions........................................................................... 160 7-1. I2C Signals (64QFN) ..................................................................................................... 164 7-2. Timer Periods ............................................................................................................. 168 7-3. I2C REGISTERS.......................................................................................................... 180 7-4. I2CMSA Register Field Descriptions ................................................................................... 181 7-5. I2CMCS Register Field Descriptions ................................................................................... 182 7-6. I2CMDR Register Field Descriptions................................................................................... 184 7-7. I2CMTPR Register Field Descriptions ................................................................................. 185 7-8. I2CMIMR Register Field Descriptions.................................................................................. 186 7-9. I2CMRIS Register Field Descriptions .................................................................................. 188 7-10. I2CMMIS Register Field Descriptions .................................................................................. 190 7-11. I2CMICR Register Field Descriptions .................................................................................. 192 7-12. I2CMCR Register Field Descriptions................................................................................... 194 7-13. I2CMCLKOCNT Register Field Descriptions.......................................................................... 195 7-14. I2CMBMON Register Field Descriptions............................................................................... 196 7-15. I2CMBLEN Register Field Descriptions................................................................................ 197 7-16. I2CMBCNT Register Field Descriptions ............................................................................... 198 7-17. I2CSOAR Register Field Descriptions ................................................................................. 199 7-18. I2CSCSR Register Field Descriptions ................................................................................. 200 7-19. I2CSDR Register Field Descriptions ................................................................................... 202 7-20. I2CSIMR Register Field Descriptions .................................................................................. 203 7-21. I2CSRIS Register Field Descriptions................................................................................... 205 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Tables 15 www.ti.com 7-22. I2CSMIS Register Field Descriptions .................................................................................. 207 7-23. I2CSICR Register Field Descriptions .................................................................................. 209 7-24. I2CSOAR2 Register Field Descriptions................................................................................ 211 7-25. I2CSACKCTL Register Field Descriptions ............................................................................ 212 7-26. I2CFIFODATA Register Field Descriptions............................................................................ 213 7-27. I2CFIFOCTL Register Field Descriptions.............................................................................. 214 7-28. I2CFIFOSTATUS Register Field Descriptions ........................................................................ 216 7-29. I2CPP Register Field Descriptions ..................................................................................... 217 7-30. I2CPC Register Field Descriptions ..................................................................................... 218 8-1. SPI Interface .............................................................................................................. 221 8-2. Phase and Polarity Combinations ...................................................................................... 223 8-3. Clock Ratio Granularity .................................................................................................. 228 8-4. Granularity Examples .................................................................................................... 228 8-5. SPI Word Length WL..................................................................................................... 228 8-6. SPI Registers.............................................................................................................. 245 8-7. SPI_SYSCONFIG Register Field Descriptions ....................................................................... 246 8-8. SPI_SYSSTATUS Register Field Descriptions ....................................................................... 247 8-9. SPI_IRQSTATUS Register Field Descriptions........................................................................ 248 8-10. SPI_IRQENABLE Register Field Descriptions........................................................................ 250 8-11. SPI_MODULCTRL Register Field Descriptions ...................................................................... 251 8-12. SPI_CHCONF Register Field Descriptions............................................................................ 252 8-13. SPI_CHSTAT Register Field Descriptions ............................................................................ 255 8-14. SPI_CHCTRL Register Field Descriptions ............................................................................ 256 8-15. SPI_TX Register Field Descriptions.................................................................................... 257 8-16. SPI_RX Register Field Descriptions.................................................................................... 258 8-17. SPI_XFERLEVEL Register Field Descriptions........................................................................ 259 9-1. Available CCP Pins and PWM Outputs/Signals Pins ................................................................ 262 9-2. General-Purpose Timer Capabilities ................................................................................... 263 9-3. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .................................... 264 9-4. 16-Bit Timer With Prescaler Configurations ........................................................................... 265 9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode.......................................... 265 9-6. Counter Values When the Timer is Enabled in Input Event-Count Mode ......................................... 267 9-7. Counter Values When the Timer is Enabled in PWM Mode ........................................................ 268 9-8. TIMER Registers.......................................................................................................... 273 9-9. GPTMCFG Register Field Descriptions................................................................................ 274 9-10. GPTMTAMR Register Field Descriptions.............................................................................. 275 9-11. GPTMTBMR Register Field Descriptions.............................................................................. 277 9-12. GPTMCTL Register Field Descriptions ................................................................................ 279 9-13. GPTMIMR Register Field Descriptions ................................................................................ 281 9-14. GPTMRIS Register Field Descriptions................................................................................. 283 9-15. GPTMMIS Register Field Descriptions................................................................................. 285 9-16. GPTMICR Register Field Descriptions................................................................................. 287 9-17. GPTMTAILR Register Field Descriptions.............................................................................. 289 9-18. GPTMTBILR Register Field Descriptions.............................................................................. 290 9-19. GPTMTAMATCHR Register Field Descriptions ...................................................................... 291 9-20. GPTMTBMATCHR Register Field Descriptions ...................................................................... 292 9-21. GPTMTAPR Register Field Descriptions .............................................................................. 293 9-22. GPTMTBPR Register Field Descriptions .............................................................................. 294 9-23. GPTMTAPMR Register Field Descriptions ............................................................................ 295 16 List of Tables SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9-24. GPTMTBPMR Register Field Descriptions ............................................................................ 296 9-25. GPTMTAR Register Field Descriptions ................................................................................ 297 9-26. GPTMTBR Register Field Descriptions ................................................................................ 298 9-27. GPTMTAV Register Field Descriptions ................................................................................ 299 9-28. GPTMTBV Register Field Descriptions ................................................................................ 300 9-29. GPTMDMAEV Register Field Descriptions............................................................................ 301 10-1. Watchdog Timers Register Map ........................................................................................ 306 10-2. WATCHDOG Registers .................................................................................................. 307 10-3. WDTLOAD Register Field Descriptions................................................................................ 308 10-4. WDTVALUE Register Field Descriptions .............................................................................. 309 10-5. WDTCTL Register Field Descriptions .................................................................................. 310 10-6. WDTICR Register Field Descriptions .................................................................................. 311 10-7. WDTRIS Register Field Descriptions .................................................................................. 312 10-8. WDTTEST Register Field Descriptions ................................................................................ 313 10-9. WDTLOCK Register Field Descriptions................................................................................ 314 11-1. Card Types ................................................................................................................ 325 11-2. Throughput Data .......................................................................................................... 325 12-1. ulIntFlags Parameter ..................................................................................................... 342 12-2. ulStatFlags Parameter ................................................................................................... 342 13-1. ADC Registers ............................................................................................................ 348 13-2. ADC_MODULE Registers ............................................................................................... 349 13-3. ADC_CTRL Register Field Descriptions ............................................................................... 350 13-4. ADC_CH0_IRQ_EN Register Field Descriptions ..................................................................... 351 13-5. ADC_CH2_IRQ_EN Register Field Descriptions ..................................................................... 352 13-6. ADC_CH4_IRQ_EN Register Field Descriptions ..................................................................... 353 13-7. ADC_CH6_IRQ_EN Register Field Descriptions ..................................................................... 354 13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions .............................................................. 355 13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions .............................................................. 356 13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions .............................................................. 357 13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions .............................................................. 358 13-12. ADC_DMA_MODE_EN Register Field Descriptions ................................................................. 359 13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions ..................................................... 360 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.................................................... 361 13-15. CHANNEL0FIFODATA Register Field Descriptions ................................................................. 362 13-16. CHANNEL2FIFODATA Register Field Descriptions ................................................................. 363 13-17. CHANNEL4FIFODATA Register Field Descriptions ................................................................. 364 13-18. CHANNEL6FIFODATA Register Field Descriptions ................................................................. 365 13-19. ADC_CH0_FIFO_LVL Register Field Descriptions................................................................... 366 13-20. ADC_CH2_FIFO_LVL Register Field Descriptions................................................................... 367 13-21. ADC_CH4_FIFO_LVL Register Field Descriptions................................................................... 368 13-22. ADC_CH6_FIFO_LVL Register Field Descriptions................................................................... 369 13-23. ADC_CH_ENABLE Register Field Descriptions ...................................................................... 370 13-24. ulChannel Tags ........................................................................................................... 371 13-25. ulIntFlags Tags............................................................................................................ 371 14-1. Image sensor interface signals.......................................................................................... 379 14-2. Ratio of the XCLK Frequency Generator .............................................................................. 383 14-3. CAMERA REGISTERS .................................................................................................. 386 14-4. CC_SYSCONFIG Register Field Descriptions........................................................................ 387 14-5. CC_SYSSTATUS Register Field Descriptions........................................................................ 388 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Tables 17 www.ti.com 14-6. CC_IRQSTATUS Register Field Descriptions ........................................................................ 389 14-7. CC_IRQENABLE Register Field Descriptions ........................................................................ 391 14-8. CC_CTRL Register Field Descriptions................................................................................. 393 14-9. CC_CTRL_DMA Register Field Descriptions ......................................................................... 395 14-10. CC_CTRL_XCLK Register Field Descriptions ........................................................................ 396 14-11. CC_FIFODATA Register Field Descriptions .......................................................................... 397 15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN) ........ 410 15-2. Peripheral Macro Table .................................................................................................. 419 15-3. PRCM Registers .......................................................................................................... 420 15-4. CAMCLKCFG Register Field Descriptions ............................................................................ 422 15-5. CAMCLKEN Register Field Descriptions .............................................................................. 423 15-6. CAMSWRST Register Field Descriptions ............................................................................. 424 15-7. MCASPCLKEN Register Field Descriptions........................................................................... 425 15-8. MCASPSWRST Register Field Descriptions.......................................................................... 426 15-9. SDIOMCLKCFG Register Field Descriptions ......................................................................... 427 15-10. SDIOMCLKEN Register Field Descriptions ........................................................................... 428 15-11. SDIOMSWRST Register Field Descriptions........................................................................... 429 15-12. APSPICLKCFG Register Field Descriptions .......................................................................... 430 15-13. APSPICLKEN Register Field Descriptions ............................................................................ 431 15-14. APSPISWRST Register Field Descriptions ........................................................................... 432 15-15. DMACLKEN Register Field Descriptions .............................................................................. 433 15-16. DMASWRST Register Field Descriptions ............................................................................. 434 15-17. GPIO0CLKEN Register Field Descriptions ............................................................................ 435 15-18. GPIO0SWRST Register Field Descriptions ........................................................................... 436 15-19. GPIO1CLKEN Register Field Descriptions ............................................................................ 437 15-20. GPIO1SWRST Register Field Descriptions ........................................................................... 438 15-21. GPIO2CLKEN Register Field Descriptions ............................................................................ 439 15-22. GPIO2SWRST Register Field Descriptions ........................................................................... 440 15-23. GPIO3CLKEN Register Field Descriptions ............................................................................ 441 15-24. GPIO3SWRST Register Field Descriptions ........................................................................... 442 15-25. GPIO4CLKEN Register Field Descriptions ............................................................................ 443 15-26. GPIO4SWRST Register Field Descriptions ........................................................................... 444 15-27. WDTCLKEN Register Field Descriptions .............................................................................. 445 15-28. WDTSWRST Register Field Descriptions ............................................................................. 446 15-29. UART0CLKEN Register Field Descriptions ........................................................................... 447 15-30. UART0SWRST Register Field Descriptions........................................................................... 448 15-31. UART1CLKEN Register Field Descriptions ........................................................................... 449 15-32. UART1SWRST Register Field Descriptions........................................................................... 450 15-33. GPT0CLKCFG Register Field Descriptions ........................................................................... 451 15-34. GPT0SWRST Register Field Descriptions ............................................................................ 452 15-35. GPT1CLKEN Register Field Descriptions ............................................................................. 453 15-36. GPT1SWRST Register Field Descriptions ............................................................................ 454 15-37. GPT2CLKEN Register Field Descriptions ............................................................................. 455 15-38. GPT2SWRST Register Field Descriptions ............................................................................ 456 15-39. GPT3CLKEN Register Field Descriptions ............................................................................. 457 15-40. GPT3SWRST Register Field Descriptions ............................................................................ 458 15-41. MCASPCLKCFG0 Register Field Descriptions ....................................................................... 459 15-42. MCASPCLKCFG1 Register Field Descriptions ....................................................................... 460 15-43. I2CLCKEN Register Field Descriptions ................................................................................ 461 18 List of Tables SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15-44. I2CSWRST Register Field Descriptions ............................................................................... 462 15-45. LPDSREQ Register Field Descriptions ................................................................................ 463 15-46. TURBOREQ Register Field Descriptions.............................................................................. 464 15-47. DSLPWAKECFG Register Field Descriptions ........................................................................ 465 15-48. DSLPTIMRCFG Register Field Descriptions.......................................................................... 466 15-49. SLPWAKEEN Register Field Descriptions ............................................................................ 467 15-50. SLPTMRCFG Register Field Descriptions ............................................................................ 468 15-51. WAKENWP Register Field Descriptions ............................................................................... 469 15-52. RCM_IS Register Field Descriptions ................................................................................... 470 15-53. RCM_IEN Register Field Descriptions ................................................................................. 471 16-1. GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) ................................... 473 16-2. GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53 ....................................... 474 16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25 C).................................................. 475 16-4. Analog Mux Control Registers and Bits................................................................................ 478 16-5. Board Level Behavior .................................................................................................... 479 16-6. GPIO/Pins Available for Application.................................................................................... 480 16-7. Pin Multiplexing ........................................................................................................... 483 16-8. Pin Groups for I2S ........................................................................................................ 497 16-9. Pin Groups for SPI........................................................................................................ 497 16-10. Pin Groups for SD-Card I/F ............................................................................................. 497 16-11. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description ...................................... 498 16-12. Recommended Pin Multiplexing Configurations ...................................................................... 500 16-13. Sense on Power Configurations ........................................................................................ 504 A-1. Peripheral Samples....................................................................................................... 505 B-1. Miscellaneous Register Summary ...................................................................................... 506 B-2. DMA_IMR Register Field Descriptions................................................................................. 507 B-3. DMA_IMS Register Field Descriptions................................................................................. 509 B-4. DMA_IMC Register Field Descriptions................................................................................. 511 B-5. DMA_ICR Register Field Descriptions ................................................................................. 513 B-6. DMA_MIS Register Field Descriptions................................................................................. 515 B-7. DMA_RIS Register Field Descriptions ................................................................................. 517 B-8. GPTTRIGSEL Register Field Descriptions ............................................................................ 519 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated List of Tables 19 20 List of Tables SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 1 SWRU367B – June 2014 – Revised October 2014 Architecture Overview Topic ........................................................................................................................... Page 1.1 Introduction....................................................................................................... 22 1.2 Architecture Overview ........................................................................................ 23 1.3 Functional Overview........................................................................................... 24 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 21 Introduction www.ti.com 1.1 Introduction Created for the Internet of Things (IoT), the SimpleLink CC3200 device is a wireless MCU that integrates a high-performance ARM Cortex-M4 MCU, allowing customers to develop an entire application with a single IC. With on-chip Wi-Fi, Internet, and robust security protocols, no prior Wi-Fi experience is required for faster development. The applications MCU subsystem contains an industry-standard ARM Cortex-M4 core running at 80 MHz. The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD/MMC, UART, SPI, I2C, and four-channel ADC. The CC3200 family includes flexible embedded RAM for code and data and ROM with external serial flash bootloader and peripheral drivers. The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-chip and contains an additional dedicated ARM MCU that completely offloads the applications MCU. This subsystem includes an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption. The CC3200 device supports Station, Access Point, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a-chip includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols. About This Manual This manual describes the modules and peripherals of the SimpeLink CC3200, Wireless MCU. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals may be present on all devices. Pin functions, internal signal connections, and operational parameters differ from device to device. The user should consult the device-specific data sheet for these details. Related Documentation Additional documentation about the device can be accessed from these links from Texas Instruments http://www.ti.com/simplelinkwifi and http://www.ti.com/simplelinkwifi-wiki Register Bit Conventions Each register is shown with a key indicating the accessibility of the individual bit, and the initial condition: Key Bit rw r r0 r1 w w0 w1 (w) h0 h1 -0, -1 -(0), -(1) -[0], -[1] -{0},-{1} Register Bit Accessibility and Initial Condition Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC Condition after POR Condition after BOR Condition after Brownout 22 Architecture Overview SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 1.2 Architecture Overview The building blocks of CC3200 system-on-chip are shown in Figure 1-1 Architecture Overview Figure 1-1. CC3200 MCU + WIFI System-On-Chip SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 23 Functional Overview www.ti.com 1.3 Functional Overview The following sections provide an overview of the main components of the CC3200 system on chip (SoC) from a microcontroller point of view. 1.3.1 Processor Core 1.3.1.1 ARM CortexTM M4 Processor Core CC3200 Application MCU subsystem is built around an ARM Cortex-M4 processor core which provides outstanding computational performance and exceptional system response to interrupts at low power consumption while optimizing memory footprint - making it an ideal fit for embedded applications. Key features of ARM Cortex-M4 processor core are: • Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size – enabling richer applications within a given device memory size. • Single-cycle multiply instruction and hardware divide • Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control • Unaligned data access, enabling data to be efficiently packed into memory • Fast code execution permits slower processor clock or increases sleep mode time. • Hardware division and fast multiplier • Deterministic, high-performance interrupt handling for time-critical applications • Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations • Configurable 4-pin JTAG and 2-pin (SWJ-DP) debug access • Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches • Ultra-low power sleep modes • Low active power consumption • 80-MHz operation 1.3.1.2 System Timer (SysTick) ARM Cortex-M4 processor core includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on- write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter is clocked on the system clock. SysTick makes OS porting between Cortex-M4 devices much easier because there is no need to change the OS system timer code. The SysTick timer integrates with the NVIC and can be used to generate a SysTick exception (exception type 15). In many OSs, a hardware timer generates interrupts so that the OS can perform task management (for example, to allow multiple tasks to run at different time slots and to ensure that no single task can lock up the entire system). To perform this function, the timer must be able to generate interrupts and, if possible, be protected from user tasks so that user applications cannot change the timer behavior. The counter can be used in several different ways; for example: • An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine • A high-speed alarm timer using the system clock • A simple counter used to measure time to completion and time used • An internal clock-source control based on missing or meeting durations 24 Architecture Overview SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Overview 1.3.1.3 Nested Vector Interrupt Controller (NVIC) CC3200 includes the ARM NVIC. The NVIC and Cortex-M3 prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to the state saving, thus enabling efficient interrupt entry. The processor supports tail- chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. The NVIC and Cortex-M4 processor prioritize and handle all exceptions in handler mode. The NVIC and the processor core interface are closely coupled to enable low-latency interrupt processing and efficient processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail chaining of interrupts. Key features are: • Exceptional interrupt handling through hardware implementation of required register manipulations • Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining • Programmable priority level for each interrupt • Low-latency interrupt and exception handling • Level and pulse detection of interrupt signals • Grouping of interrupts into group priority and sub-priority interrupts • Tail chaining of interrupts 1.3.1.4 System Control Block The system control block (SCB) provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.3.2 Memory 1.3.2.1 On Chip SRAM In order to enable low-cost applications, the CC3200 device family follows a flash-less approach. CC3200 has up to 256KB of zero wait state, on-chip SRAM to which application programs are downloaded and executed. The SRAM is used for both code and data and is connected to the Multi-Layer-AHB bus-matrix of the chip. There is no restriction on relative size or partitioning of code and data. The micro direct memory access (μDMA) controller can transfer data to and from SRAM and various peripherals. The SRAM banks implement an advanced 4-way interleaved architecture which almost eliminates performance penalty when DMA and processor simultaneously access the SRAM. Internal RAM has selective retention capability during low-power deep-sleep (LPDS) mode. Based on need, during LPDS mode the application can choose to retain 256KB, 192KB, 128KB or 64KB. Retaining the memory during low power mode provides a faster wakeup. TI provides an easy to use power management framework for processor and peripheral context save and restore mechanism based on SRAM retention. For more information, refer to the Power Management Framework User Guide in Section 15.5. 1.3.2.2 ROM CC3200 comes with factory programmed zero-wait-state ROM with the following firmware components: • Device Initialization • Bootloader • Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces When CC3200 powers up or chip reset is released or returns from hibernate mode, the device initialization procedure is executed first. After the chip hardware has been correctly configured, the boot loader is executed which loads the application code from non-volatile memory into on-chip SRAM and makes a jump to the application code entry point. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 25 Functional Overview www.ti.com The CC3200 DriverLib is a software library that controls on-chip peripherals. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt- driven peripheral support. The ROM DriverLib provides rich set of drivers for peripheral and chip. It is aimed at reducing application development time and improve solution robustness. TI recommends that applications should make extensive use of the DriverLib APIs to optimize memory and MIPS requirement of end applications. 1.3.3 Micro Direct Memory Access Controller (uDMA) The CC3200 microcontroller includes a multichannel DMA controller, or μDMA. The μDMA controller provides a way to offload data-transfer tasks from the Cortex-M4 processor, allowing more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals; it has dedicated channels for each supported on-chip module. The μDMA controller can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: • 32 configurable channels • 80-MHz operation • Support for memory to memory, memory to peripheral, and peripheral to memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-Pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request • Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable bus arbitration scheme – Software-initiated requests for any channel • Two levels of priority • Design optimizations for improved bus access performance between the µDMA controller and the processor core – µDMA controller access subordinate to core access – Simultaneous concurrent access • Data sizes of 8, 16, and 32 bits • Transfer size is programmable in binary steps from 1 to 1024 • Source and destination address increment size of byte, half-word, word, or no increment • Maskable peripheral requests • Interrupt on transfer completion, with a separate interrupt per channel 1.3.4 General Purpose Timer (GPT) CC3200 includes 4 instances of 32 bit user programmable general purpose timers. GPTs can be used to count or time external events that drive the timer input pins. Each GPT module (GPTM) block provides two 16-bit timers or counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer. The GPTM contains GPTM blocks with the following functional options: • Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer 26 Architecture Overview SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Overview – 16-bit general-purpose timer with an 8-bit prescaler – 16-bit input-edge count- or time-capture modes – 16-bit pulse-width modulation (PWM) mode with software-programmable output inversion of the PWM signal • Count up or down • Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the ISR • GPT can be used to trigger efficient transfers using the µDMA. – Dedicated channel for each timer – Burst request generated on timer interrupt 1.3.5 Watch Dog Timer (WDT) The watchdog timer in CC3200 is used to restart the system when it gets stuck due to an erroneous scenario and does not respond as expected. The watchdog timer be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out. Once the watchdog timer is configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The watchdog timer provides the following features: • 32-bit down-counter with a programmable load register • Programmable interrupt generation logic with interrupt masking • Lock register protection from runaway software • Reset generation logic 1.3.6 Multi-Channel Audio Serial Port (McASP) CC3200 includes a configurable multichannel audio serial port for glue-less interfacing to audio CODEC and DAC (speaker drivers). The audio port has two serializer / deserializers that can be individually enabled to either transmit or receive and operate synchronously. Key features are: • Two stereo I2S channels – One stereo receive and one stereo transmit lines – Two stereo transmit lines • Programmable Clock and frame-sync polarity (rising or falling edge) • Programmable Word length (bits per word): 16 and 24 bits • Programmable Fractional divider for bit-clock generation, up to 9MHz. 1.3.7 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a four-wire bidirectional communications interface that converts data between parallel and serial. The SPI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SPI allows a duplex serial communication between a local host and SPI-compliant external devices. CC3200 includes one SPI port that is dedicated to the application. Key features are • Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces Master and slave modes • 3-pin and 4-pin mode • Full duplex and half duplex • Serial clock with programmable frequency, polarity, and phase • Upto 20MHz operation • Programmable Chip Select polarity • Programmable delay before the first SPI word is transmitted. • Programmable timing control between chip select and external clock generation SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 27 Functional Overview • No dead cycle between two successive words in slave mode • SPI word lengths of 8, 16, and 32 bits • Efficient transfers using the μDMA controller • Programmable interface operation for Freescale SPI, MICROWIRE, or TI-SSI www.ti.com 1.3.8 Inter-Integrated Circuit Interface (I2C) The inter-integrated circuit (I2C) bus provides bidirectional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to wide variety of external I2C devices such as sensors, serial memory, control ports of image sensors and audio codecs etc. Multiple slave devices can be connected to the same I2C bus. CC3200 microcontroller includes one I2C module with the following features: • Master and Slave modes of operation • Master with arbitration and clock synchronization • Multi-master support • 7-bit addressing mode • Standard (100 Kbps) and Fast (400 Kbps) modes 1.3.9 Universal Asynchronous Receiver/Transmitter (UART) A universal asynchronous receivers/transmitter (UART) is an integrated circuit used for RS-232 serial communications. UARTS contain a transmitter (parallel-to-serial converter) and a receiver (serial-toparallel converter), each clocked separately. The CC3200 device includes two fully programmable UARTs. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and unmasked. The UARTs include the following features: • Programmable baud-rate generator allowing speeds up to 3 Mbps • Separate 16 x 8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading • Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface • FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 • Standard asynchronous communication bits for start, stop, and parity • Line-break generation and detection • Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop-bit generation • RTS and CTS modem handshake support • Standard FIFO-level and end-of-transmission interrupts • Efficient transfers using µDMA – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 28 Architecture Overview SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Overview 1.3.10 General Purpose Input / Output (GPIO) All digital pins of the CC3200 device and some of the analog pins can be used as a general-purpose input/output (GPIO). The GPIOs are grouped as 4 instances GPIO modules each of 8-bit. Supported features include: • Up to 24 GPIOs, depending on the functional pin configuration • Interrupt capability for all GPIO pins – Level or edge sensitive – Rising or falling edge – Selective interrupt masking • Can be used to trigger DMA operation • Selectable wakeup source (one out of 6 pins) • Programmable pad configuration – Internal 5 µA pull-up and pull-down – Configurable drive strength of 2, 4, 6, 8, 10, 12, and 14 mA – Open-drain mode • GPIO register readable through the high-speed internal bus matrix 1.3.11 Analog to Digital Converter (ADC) The ADC peripheral converts a continuous analog voltage to a discrete digital number. The CC3200 device includes ADC modules with four input channels. Each ADC module features 12-bit conversion resolution for the four input channels. Features include: • Number of bits: 12-bit • Effective nominal accuracy: 10 bits • Four analog input channels • Automatic round-robin sampling • Fixed sampling interval of 16 µs per channel • Automatic 16-bit time-stamping of every ADC samples based on system clock • Dedicated DMA channel to transfer ADC channel data to the application RAM. 1.3.12 SD Card Host CC3200 includes a SD-Host interface for applications that needs mass storage. The SD-Host interface support is limited to 1-bit mode due to chip pin constraints. 1.3.13 Parallel Camera Interface CC3200 includes an 8-bit parallel camera port to enable image sensor based applications. 1.3.14 Debug Interface CC3200 supports both IEEE Standard 1149.1 JTAG (4-wire) and the low-pin-count ARM SWD (2-wire) debug interfaces. Depending on the board level configuration of the sense-on-power pull resistors, the chip by default powers up with either the 4-wire JTAG or the 2-wire SWD interface. As shown in Fig-1, the 4-wire JTAG signals from the chip pins are routed via an IcePick module. TAPs other than the Application MCU are reserved for TI production test. A TAP select sequence is required to be sent to the device to connect to the ARM Cortex M4 JTAG TAP. The 2-wire mode however directly routes the ARM SWD-TMS and SWD-TCK pins directly to the respective chip pins. Further details about the debug interface will be addressed in the revision of this manual. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 29 Functional Overview www.ti.com 1.3.15 Hardware Cryptography Accelerator The secure variant of CC3200 includes a suite of high throughput state-of-the-art hardware accelerator for fast computation of ciphers (AES, DES, 3-DES), hashing (SHA, MD5) and CRC algorithms by the application. It is also referred as the Data Hashing and Transform Engine (DTHE). Further details about the hardware cryptography accelerator will be addressed in the revision of this manual. NOTE: Present production devices have the Crypto unlocked (Fuse Farm); a user application can use these. NOTE: Secure MCU ensures secure booting of the user application using the crypto engines. This feature will be available in future revisions of the device. 1.3.16 Clock, Reset and Power Management CC3200 system-on-chip includes the necessary clock and power management functionalities to build a standalone battery operated low power solution. Key features are: • Primary clocks – Slow Clock: 32.768KHz (+/-250ppm) • Used in RTC, Wi-Fi beacon listen timing in low power IDLE mode and some of the chip internal sequencing • On-chip low power 32KHz Xtal Oscillator • Support for externally fed 32.768KHz Clock • On-chip 32KHz RC Oscillator for initial wakeup – Fast Clock: 40MHz (+/-20ppm) • Used in Wi-Fi radio and MCU. • On-chip low phase-noise 40MHz Xtal Oscillator • Support for externally fed clean 40MHz Clock (eg: TCXO) • System and peripheral clocks are derived from internal PLL producing 240MHz • Flexible Reset Scheme – Following resets are supported in CC3200 • External chip reset pin: Entire chip, including power management is reset when nRESET pin is held low. • Reset on Hibernate: Entire core is reset when the chip goes through a hibernate cycle. • Reset on Watchdog: Application MCU is reset when the watchdog timer expires. • Soft-reset: Application MCU is reset by software – Complete system recovery from any stuck-at scenario can be achieved by using a combination of WDT reset and Hibernate sleep. • On-Chip Power Management – CC3200 supports two supply configurations: • Wide voltage mode: 2.1V to 3.6V • Powered by battery (2x1.5V) or a regulated 3.3V supply. • Regulated 1.85V • For applications with on-board DCDC regulator – A set of 3 on-chip high-efficiency DCDC converters are used to produce the internal module supply voltages as and when they are needed. These switching converters and their frequency plan are optimized to minimize interference to WLAN radio. • DIG-DCDC: Produces 0.9V to 1.2V for the core digital logic • ANA1-DCDC: Produces low ripple 1.8V supply for the analog and RF. This is bypassed in the 30 Architecture Overview SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Overview regulated 1.85V configuration. • PA-DCDC: Produces regulated 1.8V with extremely fast transient regulation for the WLAN RF Transmit Power Amplifier. This is bypassed in the regulated 1.85V configuration. – A set of Low Dropout Regulators (LDOs) are used in the Radio subsystem to further regulate and filter the ANA1-DCDC output before being fed to the analog circuits. – On chip factory-trimmed accurate band-gap voltage reference ensures the regulator outputs are stable across process and temperature. 1.3.17 SimpleLink Subsystem The SimpleLink subsystem provides a fast secured WLAN and Internet connections with 256-bit encryption. The CC3200 device supports station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi network processor includes an embedded IPv4 TCP/IP stack. This multi-processor subsystem consists of the following: • IPv4 Network Processor and Wi-Fi Driver • 802.11 b/g/n MAC • 802.11 b/g/n PHY • 802.11 b/g/n Radio The SimpleLink subsystem is accessible from the Application MCU over an asynchronous link and can be controlled through a complete set of SimpleLink Host Driver APIs – that are provided as part of the ROM driver library. The mode of usage is very similar to that of an external MCU using the CC3100 device. The co-location of the Wi-Fi subsystem on the same die imposes a few restrictions on the ApplicationMCU. These will be covered in detail in the chapter on power management (PRCM). 1.3.18 IO Pads and Pin Multiplexing The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and register control. The IO Pad and Pin Mux sections feature flexible wide-voltage IOs. Supported features include: • Programmable drive strength from 2mA to 14mA (nominal condition) in steps of 2mA. • Open drain mode • Output buffer isolation • Automatic output isolation during reset and hibernate • Configurable pull-up and pull-down (10uA nominal) • Software configurable pad state retention during LPDS • All digital I/Os are nonfail-safe. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Architecture Overview 31 Chapter 2 SWRU367B – June 2014 – Revised October 2014 Cortex-M4 Processor Topic ........................................................................................................................... Page 2.1 Overview ........................................................................................................... 33 2.2 Functional Description........................................................................................ 35 32 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 2.1 Overview CC3200 incorporates a dedicated instance of ARM® Cortex-M4 CPU core for executing application code with or without RTOS. This processor core is not used in any manner for running any networking or device management task. This dedicated ARM® Cortex™-M4 core along with large on-chip SRAM, rich set of peripherals, and advanced DCDC based power management, provides a very robust contention-free high-performance application platform at much lower power, at lower cost and smaller solution size when compared to solutions based on discrete MCUs. Features include: • 32-bit ARM® Cortex™-M4 architecture optimized for small-footprint embedded applications • 80-MHz operation • Fast interrupt handling • Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory • 16-bit SIMD vector processing unit • 3-stage pipeline Harvard architecture • Hardware division and fast digital-signal-processing orientated multiply accumulate • Saturating arithmetic for signal processing • Deterministic, high-performance interrupt handling for time-critical applications • Enhanced system debug with extensive breakpoints • Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing • Low power consumption with multiple sleep modes The ARM® Cortex™-M4 application processor core in CC3200 does not include the Floating Point Unit and Memory Protection Unit (FPU and MPU). This chapter provides information on the implementation of the Cortex-M4 application processor in CC3200, including the programming model, the memory model, the exception model, fault handling and power management. For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A). 2.1.1 Block Diagram The block diagram is shown in Figure 2-1. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 33 Overview Figure 2-1. Application CPU Block Diagram www.ti.com 2.1.2 System-Level Interface The Cortex-M4 application processor in CC3200 provides multiple interfaces using AMBA® technology in order to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. 2.1.3 Integrated Configurable Debug The Cortex-M4 application processor, in CC3200, implements an ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. The 4-bit trace interface from Embedded Trace Macrocell (ETM) is not supported in CC3200 due to pin limitations. Instead, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. A Serial Wire Viewer (SWV) can export a stream of software-generated messages (printf style debug), data trace, and profiling information through a single pin, in order to enable simple and cost-effective profiling of the system trace events. The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions for up to eight words of program code in the code memory region. FPB also provides code patching capability, yet since CC3200 application processor implements and executes from SRAM architecture, this type of patching is no longer required For more information on the Cortex-M4 debug capabilities, see the ARM® Debug Interface V5 Architecture Specification. 34 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 2.1.4 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M4 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2. Figure 2-2. TPIU Block Diagram Debug ATB Slave Port ARM® Trace Bus (ATB) Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) APB Sla ve Port Advance Peripheral Bus (APB) Interface 2.1.5 Cortex-M4 System Component Details The Cortex-M4 application processor core includes the following system components: • SysTck A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see Section 3.2.1). • Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” in Section 3.2.2). • System Control Block (SCB) The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” in Section 3.2.3). 2.2 Functional Description 2.2.1 Programming Model This section describes the Cortex-M4 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M4 has two modes of operation: • Thread Mode, which is used to execute application software. The processor enters thread mode when it comes out of reset. • Handler mode, which is used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M4 has two privilege levels: • Underprivileged In this mode, the software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 35 Functional Description www.ti.com – Possibly restricted access to memory or peripherals • Privileged In this mode, the software can use all the instructions and has access to all resources In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.2.1.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks: the main stack and the process stack, with a pointer for each held in independent registers (see the SP register). In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1. Table 2-1. Summary of Processor Mode, Privilege level, and Stack Use Processor Mode Use Thread Applications Handler Exception handlers (1) See CONTROL register in Section 2.2.2.1.2.1. Privilege level Privileged or unprivileged (1) Always privileged Stack Used (1)Main stack or process stack Main stack 2.2.2 Register Description 2.2.2.1 Registers 2.2.2.1.1 Register Map Figure 2-2 shows the Cortex-M4 register set. Table 2-2 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. 36 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 2-3. Cortex-M4 Register Set Offset - Table 2-2. Processor Register Map Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP LR PC PSR PRIMASK FAULTMASK BASEPRI CONTROL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - 0xFFFF.FFFF - 0x0100.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Cortex General-Purpose Register 0 Cortex General-Purpose Register 1 Cortex General-Purpose Register 2 Cortex General-Purpose Register 3 Cortex General-Purpose Register 4 Cortex General-Purpose Register 5 Cortex General-Purpose Register 6 Cortex General-Purpose Register 7 Cortex General-Purpose Register 8 Cortex General-Purpose Register 9 Cortex General-Purpose Register 10 Cortex General-Purpose Register 11 Cortex General-Purpose Register 12 Stack Pointer Link Register Program Counter Program Status Register Priority Mask Register Fault Mask Register Base Priority Mask Register Control Register SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 37 Functional Description Offset - www.ti.com Table 2-2. Processor Register Map (continued) Name FPSC Type R/W Reset - Description Floating-Point Status Control (N/A for CC3200) 2.2.2.1.2 Register Descriptions This section lists and describes the Cortex-M4 registers. The core registers are not memory mapped and are accessed by register name rather than offset. NOTE: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Stack Pointer (SP) In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Link Register (LR) The Link Register (LR) stores the return information for subroutines, function calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into the LR on exception entry. Program Counter (PC) The Program Counter (PC) contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Status Register (PSR) NOTE: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: • Application Program Status Register (APSR), bits 31:27, bits 19:16 • Execution Program Status Register (EPSR), bits 26:24, 15:10 • Interrupt Program Status Register (IPSR), bits 7:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the InterruptibleContinuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted. IPSR contains the exception type number of the current Interrupt Service Routine (ISR). 38 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. Table 2-3 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A) for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type PSR PSR R/W(1) (2) IEPSR RO IAPSR R/W (1) EAPSR R/W (2) (1) The processor ignores writes to the IPSR bits. (2) Reads of the EPSR bits return zero, and the processor ignores writes to these bits Combination APSR, EPSR, and IPSR EPSR and IPSR APSR and IPSR APSR and EPSR Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A) for more information on these instructions. Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A) for more information on these instructions. Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. 2.2.2.1.2.1 Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode. Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value. In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A), or perform an exception return to Thread mode with the appropriate EXC_RETURN value. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 39 Functional Description NOTE: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A). www.ti.com 2.2.2.1.3 Exceptions and Interrupts The Cortex-M4 application processor in CC3200 supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See Section 2.2.4.7 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more information. 2.2.2.1.4 Data Types The Cortex-M4 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64bit data transfer instructions. All instruction and data memory accesses are little endian. 2.2.3 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map of the CC3200 microcontroller subsystem is provided in Table 2-4. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see Section 2.2.3.1). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see the Cortex-M4 Peripherals, Chapter 3). Note:Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault. Start Address 0x0000.0000 0x2000.0000 0x2200.0000 0x4000.0000 0x4000.4000 0x4000.5000 0x4000.6000 0x4000.7000 0x4000.C000 0x4000.D000 0x4002.0000 0x4002.0800 0x04003.0000 0x04003.1000 0x04003.2000 0x04003.3000 End Address 0x0007.FFFF 0x2003.FFFF 0x23FF.FFFF 0x4000.0FFF 0x4000.4FFF 0x4000.5FFF 0x4000.6FFF 0x4000.7FFF 0x4000.CFFF 0x4000.DFFF 0x4002.07FF 0x4002.0FFF 0x4003.0FFF 0x4003.1FFF 0x4003.2FFF 0x4003.3FFF Table 2-4. Memory Map Description On-chip ROM (Bootloader + DriverLib) Bit-banded on-chip SRAM Bit-band alias of 0x2000.0000 through 0x200F.FFFF Watchdog timer A0 GPIO port A0 GPIO port A1 GPIO port A2 GPIO port A3 UART A0 UART A1 I 2C A0 (Master) I 2C A0 (Slave) General-purpose timer A0 General-purpose timer A1 General-purpose timer A2 General-purpose timer A3 Comment 40 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Start Address 0x400F.7000 0x400F.E000 0x400F.F000 0x4200.0000 0x4401.C000 0x4402.0000 0x4402.1000 0x4402.5000 0x4402.6000 0xE000.0000 0xE000.1000 0xE000.2000 0xE000.E000 0xE004.0000 0xE004.1000 Functional Description Table 2-4. Memory Map (continued) End Address 0x400F.7FFF 0x400F.EFFF 0x400F.FFFF 0x43FF.FFFF 0x4401.EFFF Description Configuration registers System control µDMA Bit band alias of 0x4000.0000 through 0x400F.FFFF McASP 0x4402.0FFF FlashSPI 0x4402.2FFF 0x4402.5FFF 0x4402.6FFF 0xE000.0FFF 0xE000.1FFF 0xE000.2FFF 0xE000.EFFF 0xE004.0FFF 0xE004.1FFF GSPI MCU reset clock manager MCU configuration space Instrumentation trace Macrocell TM Data watchpoint and trace (DWT) Flash patch and breakpoint (FPB) Cortex-M4 Peripherals (NVIC, SysTick,SCB) Trace port interface unit (TPIU) Reserved for embedded trace macrocell (ETM) Comment Used for external serial flash Used by application processor 2.2.3.1 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. In ARM Cortex-M4 architecture, the bit-band regions occupy the lowest 1 MB of the SRAM. Accesses to the 32MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-5. Note:A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. The CC3200 family of WiFi-Microcontrollers support up to 256Kbyte of on chip SRAM for code and data. The SRAM starts from address 0x2000.0000. Table 2-5. SRAM Memory Bit-banding Regions Address Range Start End 0x2000.0000 0x2003.FFFF 0x2200.0000 0x23FF.FFFF Memory Region SRAM bit-band region SRAM bit-band alias Instruction and Data Accesses Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. Data accesses to this region are remapped to bit band region. A write operation is performed as read-modifywrite. Instruction accesses are not remapped. Bit-banding for peripherals is not supported in CC3200. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 41 Functional Description www.ti.com 2.2.3.1.1 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.2.3.1.2 Directly Accessing a Bit-Band Region Behavior of Memory Accesses describes the behavior of direct byte, halfword, or word accesses to the bitband regions. 2.2.3.2 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-4 illustrates how data is stored. Figure 2-4. Data Storage Memory Register 7 0 Address A B0 lsbyte 31 24 23 16 15 87 0 B3 B2 B1 B0 A+1 B1 A+2 B2 A+3 B3 msbyte 2.2.3.3 Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: • A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. • A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: • The word instructions LDREX and STREX • The halfword instructions LDREXH and STREXH • The byte instructions LDREXB and STREXB 42 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M4 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: • It executes a CLREX instruction. • It executes a Store-Exclusive instruction, regardless of whether the write succeeds. • An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (ARM DUI 0553A). 2.2.4 Exception Model The ARM Cortex-M4 application processor in CC3200 and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-6 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 70 interrupts (listed in Table 2-6). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in Section 3.2.2. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, NonMaskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. NOTE: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC) (see Section 3.2.2) for more information on exceptions and interrupts. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 43 Functional Description www.ti.com 2.2.4.1 Exception States Each exception is in one of the following states: • Inactive.The exception is not active and not pending. • Pending.The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. • Active.An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. • Active and Pending.The exception is being serviced by the processor, and there is a pending exception from the same source. 2.2.4.2 Exception Types The exception types are: • Reset.Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. • NMI.A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. NMI in CC3200 is reserved for internal system and not available for application usage. • Hard Fault.A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. • Memory Management Fault.A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. • Bus Fault.A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. • Usage Fault.A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. • SVCall.A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. • Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. • PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. • SysTick.A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. 44 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description • Interrupt (IRQ).An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-5 lists the interrupts on the CC3200 application processor For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-6 shows as having configurable priority (see the SYSHNDCTRL register and the DIS0 register). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” (see Section 2.2.5). Table 2-6. Exception Types Exception Type - Reset Non-Maskable Interrupt (NMI) Hard Fault Memory Management Bus Fault Vector Number 0 1 2 3 4 5 Priority (1) - -3 (highest) -2 -1 programmable (3) programmable (3) Usage Fault 6 programmable (3) - 10-Jul - SVCall 11 programmable (3) Debug Monitor 12 programmable (3) - 13 - PendSV 14 programmable (3) SysTick 15 programmable (3) Interrupts 16 and above programmable (4) (1) a. 0 is the default priority for all the programmable priorities. (2) b. See Figure 2-5. (3) See SYSPRI1 on Table 3-3. (4) d. See PRIn registers. Vector Address or Offset (2) 0x0000.0000 0x0000.0004 0x0000.0008 Activation Stack top is loaded from the first entry of the vector table on reset. Asynchronous Asynchronous 0x0000.000C - 0x0000.0010 Synchronous 0x0000.0014 Synchronous when precise and asynchronous when imprecise 0x0000.0018 Synchronous - Reserved 0x0000.002C Synchronous 0x0000.0030 Synchronous - Reserved 0x0000.0038 Asynchronous 0x0000.003C Asynchronous 0x0000.0040 and above Asynchronous Interrupt Number (Bit in Interrupt Registers) 0 1 2 3 5 6 8 14 15 16 Table 2-7. CC3200 Application Processor Interrupts Vector Adderess or Offset 0x0000.0040 0x0000.0044 0x0000.0048 0x0000.004C 0x0000.0054 0x0000.0058 0x0000.0060 0x0000.0078 0x0000.007C 0x0000.0080 Description GPIO Port 0 (GPIO 0-7) GPIO Port A1 (GPIO 8-15) GPIO Port A2 (GPIO 16-23) GPIO Port A3 (GPIO 24-31) UART0 UART1 I2C ADC Channel-0 ADC Channel-1 ADC Channel-2 Type SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 45 Functional Description Interrupt Number (Bit in Interrupt Registers) 17 18 19 20 21 22 23 24 35 36 46 47 161 163 168 171 176 Table 2-7. CC3200 Application Processor Interrupts (continued) Vector Adderess or Offset 0x0000.0084 0x0000.0088 0x0000.008C 0x0000.0090 0x0000.0094 0x0000.0098 0x0000.009C 0x0000.00A0 0x0000.00CC 0x0000.00D0 0x0000.00F8 0x0000.00FC 0x0000.02C4 0x0000.02CC 0x0000.02E0 0x0000.02EC 0x0000.0300 Description ADC Channel-3 WDT 16/32-Bit Timer A0A 16/32-Bit Timer A0B 16/32-Bit Timer A1A 16/32-Bit Timer A1B 16/32-Bit Timer A2A 16/32-Bit Timer A2B 16/32-Bit Timer A3A 16/32-Bit Timer A3B uDMA Software Intr uDMA Error Intr I2S Camera RAM WR Error Network Intr SPI www.ti.com Type 2.2.4.3 Exception Handlers The processor handles exceptions using: • Interrupt Service Routines (ISRs).Interrupts (IRQx) are the exceptions handled by ISRs. • Fault Handlers.Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. • System Handlers.NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.2.4.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-6. Figure 2-5 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. 46 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 2-5. Vector Table Exception number IRQ number Offset (N+16) . . . 0x040 (N) + 0x(N*4) . . . 0x004C Vector IRQ N ... 18 2 0x0048 IRQ2 17 1 0x0044 IRQ1 16 0 0x0040 IRQ0 15 -1 0x003C Systick 14 -2 0x0038 PendSV 13 Reserve 12 d 11 -5 0x002C Reserved for Debug 10 SVCall 9 8 Reserved 7 6 -10 0x0018 5 -11 0x0014 Usage 4 -12 0x0010 fault Bus 3 -13 0x000C fault 2 -14 0x0008 Memory management 1 0x0004 fault Hard fault 0 0x0000 NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0400 to 0x3FFF.FC00. Note that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary. 2.2.4.5 Exception Priorities As Table 2-6 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. NOTE: Configurable priority values for the CC3200 implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions (NMI is reserved for use by the system), with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 47 Functional Description www.ti.com When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.2.4.6 Interrupt Priority Grouping .To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: • An upper field that defines the group priority • A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. 2.2.4.7 Exception Entry and Return Descriptions of exception handling use the following terms: • Preemption.When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See Section 2.2.4.6 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. • Return.Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a latearriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. • Tail-Chaining.This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. • Late-Arriving.This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.2.4.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK FAULTMASK, and BASEPRI registers). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tailchained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-6 shows the Cortex-M4 stack frame layout – which is similar to that of ARMv7-M implementations without an FPU. 48 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Figure 2-6. Exception Stack Frame Functional Description Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel with the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception 2.2.5 Fault Handling Faults are a subset of the exceptions (see Section 2.2.4). The following conditions generate a fault: • A bus error on an instruction fetch or vector table load or a data access. • An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. • Attempting to execute an instruction from a memory region marked as Non-Executable (XN). 2.2.5.1 Fault Types Table 2-8 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. Table 2-8. Faults Fault Bus error on a vector read Handler Hard fault Fault escalated to a hard fault Hard fault Default memory mismatch on instruction access Default memory mismatch on data access Default memory mismatch on exception stacking Memory management fault Memory management fault Memory management fault (1) Occurs on an access to an XN region. Fault Status Register Hard Fault Status (HFAULTSTAT) Hard Fault Status (HFAULTSTAT) Memory Management Fault Status (MFAULTSTAT) Memory Management Fault Status (MFAULTSTAT) Memory Management Fault Status (MFAULTSTAT) SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Bit Name VECT FORCED IERR (1) DERR MSTKE Cortex-M4 Processor 49 Functional Description www.ti.com Table 2-8. Faults (continued) Fault Handler Fault Status Register Bit Name Default memory mismatch on Memory management fault exception unstacking Memory Management Fault Status (MFAULTSTAT) MUSTKE Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction set state (2) Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 (2) Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation 2.2.5.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 in Section 3.3.1.17). Software can disable execution of the handlers for these faults (see SYSHNDCTRL). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in Section 2.2.4. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: • A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. • A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. • An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. • A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. 50 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 2.2.5.3 Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-9. Handler Hard fault Memory management fault Bus fault Usage fault Table 2-9. Fault Status and Fault Address Registers Status Register Name Hard Fault Status (HFAULTSTAT) Memory Management Fault Status (MFAULTSTAT) Bus Fault Status (BFAULTSTAT) Usage Fault Status (UFAULTSTAT) Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Register Description Section 3.3.1.22 Section 3.3.1.23 Section 3.3.1.23 Section 3.3.1.23 2.2.5.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. 2.2.6 Power Management CC3200 WiFi-Microcontroller is a multi-processor system-on-chip. An advanced power management scheme has been implemented at chip level that delivers the best in class energy efficiency across a wide class of application profiles, while handling the asynchronous sleep-wake requirements of multiple high performance processors and WiFi-radio subsystems. The Cortex-M4 application processor subsystem (consisting of the CM4 core and application peripherals) is a subset of this. The chip level power management scheme is such that the application program is unaware of the power state transitions of the other subsystems. This approach insulates the user from the complexities of a multi-processor system and simplifies the application development process. From the Cortex-M4 application processor standpoint, CC3200 supports the typical SLEEP and DEEPSLEEP modes similar to those in discrete microcontrollers. The following section describe these two modes. In addition to SLEEP and DEEPSLEEP, two additional sleep modes are offered. These two modes consume much lower power than the DEEPSLEEP mode in CC3200. • Low Power Deep Sleep Mode (LPDS) – Recommended for ultra-low power always connected cloud/WiFi applications – Up to 256Kbyte of SRAM retention and fast wakeup (<5mS) – When networking and WiFi subsystems are disabled, MCU draws less than 100uA with 256Kbyte of SRAM retained (code and data). Total system current (incl WiFi and network periodic wake-up) as low as 700uA – Processor and peripheral registers are not retained. Global always ON configurations at SoC level are retained • Hibernate Mode (HIB) – Recommended for ultra-low power in-frequently connected cloud/WiFi applications – Ultra low current of 4uA including RTC – Wake on RTC or selected GPIO – No SRAM or logic retention. 2 x 32 bit register retention. LPDS and HIB modes will be covered in more detail in the Power Clock and Reset Management chapter. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 51 Functional Description www.ti.com Figure 2-7 shows the architecture of the CC3200 SoC level power management, especially from the application point of view. Figure 2-7. Power Management Architecture in CC3200 SoC The Cortex-M4 processor implementation inside the CC3200 multiprocessor SoC has a few differences when compared to a discrete MCU. While typical SLEEP and DEEPSLEEP modes are supported, in the CC3200 these two modes achieve only limited saving in energy consumption. 52 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Ultra-low power applications should be architected such that time spent in LPDS or Hibernate mode is maximized. The Cortex-M4 application processor can be configured to be woken up on selected events, for example network events such as an incoming data packet, timer or IO pad toggle. The time spent in RUN (or ACTIVE) state should then be minimized. The dedicated Cortex-M4 application processor in CC3200 is particularly suited for this mode of operation due to its advanced power management, DMA, zero wait state multi-layer AHB interconnect, fast execution and retention over the entire range of zerowait state SRAM. • SLEEP: Sleep mode stops the processor clock (clock gating). • DEEPSLEEP: Deep-sleep mode stops the application process system clock and switches off the PLL. 2.2.7 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-10 lists the supported instructions. Note: In this table: • Angle brackets, < >, enclose alternative forms of the operand • Braces, {} enclose optional operands • The Operands column is n ot exhaustive • Op2 is a flexible second operand that can be either a register or a constant • Most instructions can use an optional cndition code suffix For more informationon the instructions and operands, see the instruction descriptions in the ARM® Cortex™-M4 Technical Reference Manual. Mnemonic ADC, ADCS ADD, ADDS ADD, ADDW ADR AND, ANDS ASR, ASRS B BFC BFI BIC, BICS BKPT BL BLX BX CBNZ CBZ CLREX CLZ CMN CMP CPSID CPSIE DMB DSB Table 2-10. Cortex-M4 Instruction Summary Operands {Rd,} Rn, Op2 {Rd,} Rn, Op2 {Rd,} Rn , #imm12 Rd, label {Rd,} Rn, Op2 Rd, Rm, label Rd, #lsb, #width Rd, Rn, #lsb, #width {Rd,} Rn, Op2 #imm label Rm Rm Rn, label Rn, label Rd, Rm Rn, Op2 Rn, Op2 i i - Brief Description Add with carry Add Add Load PC-relative address Logical AND Arithmetic shift right Branch Bit field clear Bit field insert Bit clear Breakpoint Branch with link Branch indirect with link Branch indirect Compare and branch if nonzero Compare and branch if zero Clear exclusive Count leading zeros Compare negative Compare Change processor state, disable interrupts Change processor state, enable interrupts Data memory barrier Data synchronization barrier Flags N,Z,C,V N,Z,C,V N,Z,C N,Z,C N,Z,C - N,Z,C,V N,Z,C,V - - - SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 53 Functional Description EOR, EORS ISB IT LDM LDMDB, LDMEA LDMFD, LDMIA LDR LDRB, LDRBT LDRD LDREX LDREXB LDREXH LDRH, LDRHT LDRSB, LDRSBT LDRSH, LDRSHT LDRT LSL, LSLS LSR, LSRS MLA MLS MOV, MOVS MOV, MOVW MOVT MRS MSR MUL, MULS MVN, MVNS NOP ORN, ORNS ORR, ORRS PKHTB, PKHBT POP PUSH QADD QADD16 QADD8 QASX QDADD QDSUB Table 2-10. Cortex-M4 Instruction Summary (continued) {Rd,} Rn, Op2 - Rn{!}, reglist Rn{!}, reglist Rn{!}, reglist Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, Rt2, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn] Rt, [Rn] Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn, #offset] Rd, Rm, Rd, Rm, Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra Rd, Op2 Rd, #imm16 Rd, #imm16 Rd, spec_reg spec_reg, Rm {Rd,} Rn, Rm Rd, Op2 {Rd,} Rn, Op2 {Rd,} Rn, Op2 {Rd,} Rn, Rm, Op2 reglist reglist {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Exclusive OR N,Z,C Instruction synchronization - barrier If-Then condition block - Load multiple registers, - increment after Load multiple registers, - decrement before Load multiple registers, - increment after Load register with word - Load register with byte - Load register with two bytes - Load register exclusive - Load register exclusive with byte Load register exclusive with halfword Load register with halfword - Load register with signed byte - Load register with signed - halfword Load register with word - Logical shift left N,Z,C Logical shift right N,Z,C Multiply with accumulate, 32-bit result Multiply and subtract, 32-bit result Move N,Z,C Move 16-bit constant N,Z,C Move top - Move from special register to general register Move from general register to N,Z,C,V special register Multiply, 32-bit result N,Z Move NOT N,Z,C No operation - Logical OR NOT N,Z,C Logical OR N,Z,C Pack halfword - Pop registers from stack - Push registers onto stack - Saturating add Q Saturating add 16 - Saturating add 8 - Saturating add and subtract with exchange Saturating double and add Q Saturating double and subtract Q www.ti.com 54 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Functional Description Table 2-10. Cortex-M4 Instruction Summary (continued) QSAX {Rd,} Rn, Rm QSUB QSUB16 QSUB8 RBIT REV REV16 {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, Rn Rd, Rn Rd, Rn REVSH Rd, Rn ROR, RORS RRX, RRXS RSB, RSBS SADD16 SADD8 SASX Rd, Rm, Rd, Rm {Rd,} Rn, Op2 {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm SBC, SBCS SBFX SDIV SEL SEV SHADD16 SHADD8 SHASX {Rd,} Rn, Op2 Rd, Rn, #lsb, #width {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm SHSAX {Rd,} Rn, Rm SHSUB16 SHSUB8 SMLABB, SMLABT, SMLATB, SMLATT SMLAD, SMLADX {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra SMLAL RdLo, RdHi, Rn, Rm SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALD, SMLALDX SMLAWB,SMLAWT SMLSD SMLSDX SMLSLD SMLSLDX SMMLA SMMLS, SMMLR SMMUL, SMMULR SMUAD SMUADX RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra RdLo, RdHi, Rn, Rm Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra {Rd,} Rn, Rm {Rd,} Rn, Rm Saturating subtract and add with exchange Saturating subtract Saturating subtract 16 Saturating subtract 8 Reverse bits Reverse byte order in a word Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend Rotate right Rotate right with extend Reverse subtract Signed add 16 Signed add 8 Signed add and subtract with exchange Subtract with carry Signed bit field extract Signed divide Select bytes Send event Signed halving add 16 Signed halving add 8 Signed halving add and subtract with exchange Signed halving add and subtract with exchange Signed halving subtract 16 Signed halving subtract 8 Signed multiply accumulate long (halfwords) Signed multiply accumulate dual Signed multiply with accumulate (32x32+64), 64-bit result Signed multiply accumulate long (halfwords) Signed multiply accumulate long dual Signed multiply accumulate, word by halfword Signed multiply subtract dual Signed multiply subtract long dual Signed most significant word multiply accumulate Signed most significant word multiply subtract Signed most significant word multiply Signed dual multiply add - Q - - N,Z,C N,Z,C N,Z,C,V GE GE GE N,Z,C,V - - Q Q - - - Q Q - - - Q SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 55 Functional Description Table 2-10. Cortex-M4 Instruction Summary (continued) SMULBB, SMULBT, SMULTB, {Rd,} Rn, Rm SMULTT SMULL RdLo, RdHi, Rn, Rm SMULWB, SMULWT SMUSD, SMUSDX SSAT SSAT16 SSAX {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, #n, Rm {,shift #s} Rd, #n, Rm {Rd,} Rn, Rm SSUB16 SSUB8 STM {Rd,} Rn, Rm {Rd,} Rn, Rm Rn{!}, reglist Mnemonic STMDB, STMEA Operands Rn{!}, reglist STMFD, STMIA Rn{!}, reglist STR STRB, STRBT STRD STREX STREXB STREXH Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, Rt2, [Rn {, #offset}] Rt, Rt, [Rn {, #offset}] Rd, Rt, [Rn] Rd, Rt, [Rn] STRH, STRHT STRSB, STRSBT STRSH, STRSHT STRT SUB, SUBS SUB, SUBW SVC SXTAB SXTAB16 Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] {Rd,} Rn, Op2 {Rd,} Rn, #imm12 #imm {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm,{,ROR #} SXTAH SXTB16 SXTB SXTH TBB TBH TEQ TST UADD16 UADD8 UASX {Rd,} Rn, Rm,{,ROR #} {Rd,} Rm {,ROR #n} {Rd,} Rm {,ROR #n} {Rd,} Rm {,ROR #n} [Rn, Rm] [Rn, Rm, LSL #1] Rn, Op2 Rn, Op2 {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm UHADD16 UHADD8 {Rd,} Rn, Rm {Rd,} Rn, Rm Signed multiply halfwords - Signed multiply (32x32), 64-bit result Signed multiply by halfword Signed dual multiply subtract Signed saturate Signed saturate 16 Saturating subtract and add with exchange Signed subtract 16 Signed subtract 8 Store multiple registers, increment after Brief Description Store multiple registers, decrement before Store multiple registers, increment after Store register word Store register byte Store register two words Store register exclusive Store register exclusive byte Store register exclusive halfword Store register halfword Store register signed byte Store register signed halfword Store register word Subtract Subtract 12-bit constant Supervisor call Extend 8 bits to 32 and add Dual extend 8 bits to 16 and add Extend 16 bits to 32 and add Signed extend byte 16 Sign extend a byte Sign extend a halfword Table branch byte Table branch halfword Test equivalence Test Unsigned add 16 Unsigned add 8 Unsigned add and subtract with exchange Unsigned halving add 16 Unsigned halving add 8 - Q Q GE - Flags - - - N,Z,C,V N,Z,C,V - N,Z,C N,Z,C GE GE GE - www.ti.com 56 Cortex-M4 Processor SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com UHASX UHSAX UHSUB16 UHSUB8 UBFX UDIV UMAAL UMLAL UMULL UQADD16 UQADD8 UQASX UQSAX UQSUB16 UQSUB8 USAD8 USADA8 USAT USAT16 USAX USUB16 USUB8 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI Functional Description Table 2-10. Cortex-M4 Instruction Summary (continued) {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, Rn, #lsb, #width {Rd,} Rn, Rm RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm, Ra Rd, #n, Rm {,shift #s} Rd, #n, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm, {,ROR #} {Rd,} Rm, {,ROR #n} {Rd,} Rm, {,ROR #n} {Rd,} Rm, {,ROR #n} - Unsigned halving add and - subtract with exchange Unsigned halving subtract and add with exchange Unsigned halving subtract 16 - Unsigned halving subtract 8 - Unsigned bit field extract - Unsigned divide - Unsigned multiply accumulate accumulate long (32x32+64), 64-bit result Unsigned multiply with - accumulate (32x32+32+32), 64-bit result Unsigned multiply (32x 2), 64- bit result Unsigned Saturating Add 16 - Unsigned Saturating Add 8 - Unsigned Saturating Add and Subtract with Exchange Unsigned Saturating Subtract and Add with Exchange Unsigned Saturating Subtract 16 Unsigned Saturating Subtract 8 - Unsigned Sum of Absolute - Differences Unsigned Sum of Absolute - Differences and Accumulate Unsigned Saturate Q Unsigned Saturate 16 Q Unsigned Subtract and add GE with Exchange Unsigned Subtract 16 GE Unsigned Subtract 8 GE Rotate, extend 8 bits to 32 and Add Rotate, dual extend 8 bits to 16 and Add Rotate, unsigned extend and Add Halfword Zero extend a Byte - Unsigned Extend Byte 16 - Zero extend a Halfword - Wait for event - Wait for interrupt - SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Processor 57 Chapter 3 SWRU367B – June 2014 – Revised October 2014 Cortex-M4 Peripherals Topic ........................................................................................................................... Page 3.1 Overview ........................................................................................................... 59 3.2 Functional Description........................................................................................ 59 3.3 Register Map ..................................................................................................... 61 58 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 3.1 Overview This chapter provides information on the CC3200 implementation of the Cortex-M4 application processor in CC3200 peripherals, including: • SysTick (see Section 3.2.1) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. • Nested Vectored Interrupt Controller (NVIC) (see Section 3.2.2) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers • System Control Block (SCB) (see Section 3.2.3) - Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. Table 3-1 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Address 0xE000.E010-0xE000.E01F 0xE000.E100-0xE000.E4EF 0xE000.EF00-0xE000.EF03 0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F Table 3-1. Core Peripheral Register Regions Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block 3.2 Functional Description This chapter provides information on the CC3200 implementation of the Cortex-M4 application processor in CC3200 peripherals: SysTick, NVIC and SCB. 3.2.1 System Timer (SysTick) Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: • An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. • A high-speed alarm timer using the system clock. • A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. • A simple counter used to measure time to completion and time used. • An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter is: 1. Program the value in the STRELOAD register. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 59 Functional Description 2. Clear the STCURRENT register by writing to it with any value. 3. Configure the STCTRL register for the required operation. Note:When the processor is halted for debugging, the counter does not decrement. www.ti.com 3.2.2 Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. • Low-latency exception and interrupt handling. • Level and pulse detection of interrupt signals. • Dynamic reprioritization of interrupts. • Grouping of priority values into group priority and subpriority fields. • Interrupt tail-chaining. • An external Non-maskable interrupt (NMI). The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.2.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see Section 3.2.2.2 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.2.2.2 Hardware and Software Control of Interrupts The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: • The NVIC detects that the interrupt signal is High and the interrupt is not active. • The NVIC detects a rising edge on the interrupt signal. • Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register or SWTRIG register. A pending interrupt remains pending until one of the following: • The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to 60 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. • Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.2.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.3 Register Map Table 3-2 lists the Cortex-M4 Peripheral SysTick, NVIC and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note:Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Offset Name System Timer (SysTick) Registers 0x010 STCTRL Table 3-2. Peripherals Register Map Type Reset R/W 0x0000.0000 0x014 STRELOAD R/W - 0x018 STCURRENT R/WC - Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 0x104 EN1 R/W 0x0000.0000 0x108 EN2 R/W 0x0000.0000 0x10C EN3 R/W 0x0000.0000 0x110 EN4 R/W 0x0000.0000 0x114 EN5 R/W 0x0000.0000 0x118 EN6 R/W 0x0000.0000 0x180 DIS0 R/W 0x0000.0000 0x184 DIS1 R/W 0x0000.0000 0x188 DIS2 R/W 0x0000.0000 0x18C DIS3 R/W 0x0000.0000 0x190 DIS4 R/W 0x0000.0000 Description SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register Interrupt 0-31 Set Enable Interrupt 32-63 Set Enable Interrupt 64-95 Set Enable Interrupt 96-127 Set Enable Interrupt 128-159 Set Enable Interrupt 160- 191 Set Enable Interrupt 192- 199 Set Enable Interrupt 0-31 Clear Enable Interrupt 32-63 Clear Enable Interrupt 64-95 Clear Enable Interrupt 96-127 Clear Enable Interrupt 128-159 Clear Enable SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 61 Register Map Offset 0x194 0x198 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x424 0x428 62 Cortex-M4 Peripherals www.ti.com Table 3-2. Peripherals Register Map (continued) Name DIS5 Type R/W Reset 0x0000.0000 DIS6 R/W 0x0000.0000 PEND0 R/W 0x0000.0000 PEND1 R/W 0x0000.0000 PEND2 R/W 0x0000.0000 PEND3 R/W 0x0000.0000 PEND4 R/W 0x0000.0000 PEND5 R/W 0x0000.0000 PEND6 R/W 0x0000.0000 UNPEND0 R/W 0x0000.0000 UNPEND1 R/W 0x0000.0000 UNPEND2 R/W 0x0000.0000 UNPEND3 R/W 0x0000.0000 UNPEND4 R/W 0x0000.0000 UNPEND5 R/W 0x0000.0000 UNPEND6 R/W 0x0000.0000 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 RO 0x0000.0000 RO 0x0000.0000 RO 0x0000.0000 RO 0x0000.0000 ACTIVE4 RO 0x0000.0000 ACTIVE5 RO 0x0000.0000 ACTIVE6 RO 0x0000.0000 PRI0 PRI1 PRI2 PRI3 PRI4 PRI5 PRI6 PRI7 PRI8 PRI9 PRI10 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 R/W 0x0000.0000 Description Interrupt 160-191 Clear Enable Interrupt 192 - 199 Clear Enable Interrupt 0-31 Set Pending Interrupt 32-63 Set Pending Interrupt 64-95 Set Pending Interrupt 96-127 Set Pending Interrupt 128-159 Set Pending Interrupt 160-191 Set Pending Interrupt 192-199 Set Pending Interrupt 0-31 Clear Pending Interrupt 32-63 Clear Pending Interrupt 64-95 Clear Pending Interrupt 96-127 Clear Pending Interrupt 128-159 Clear Pending Interrupt 160-191 Clear Pending Interrupt 192- 199 Clear Pending Interrupt 0-31 Active Bit Interrupt 32-63 Active Bit Interrupt 64-95 Active Bit Interrupt 96-127 Active Bit Interrupt 128-159 Active Bit Interrupt 160-191 Active Bit Interrupt 192-199 Active Bit Interrupt 0-3 Priority Interrupt 4-7 Priority Interrupt 8-11 Priority Interrupt 12-15 Priority Interrupt 16-19 Priority Interrupt 20-23 Priority Interrupt 24-27 Priority Interrupt 28-31 Priority Interrupt 32-35 Priority Interrupt 36-39 Priority Interrupt 40-43 Priority SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Offset 0x42C 0x430 0x434 0x438 0x43C 0x440 0x444 0x448 0x44C 0x450 0x454 0x458 0x45C 0x460 0x464 0x468 0x46C 0x470 0x474 0x478 0x47C 0x480 0x484 0x488 0x48C 0x490 0x494 0x498 0x49C 0x4A0 0x4A4 0x4A8 0x4AC 0x4B0 Table 3-2. Peripherals Register Map (continued) Name PRI11 PRI12 PRI13 PRI14 PRI15 PRI16 PRI17 PRI18 PRI19 PRI20 PRI21 PRI22 PRI23 PRI24 PRI25 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 PRI26 R/W 0x0000.0000 PRI27 R/W 0x0000.0000 PRI28 R/W 0x0000.0000 PRI29 R/W 0x0000.0000 PRI30 R/W 0x0000.0000 PRI31 R/W 0x0000.0000 PRI32 R/W 0x0000.0000 PRI33 R/W 0x0000.0000 PRI34 R/W 0x0000.0000 PRI35 R/W 0x0000.0000 PRI36 R/W 0x0000.0000 PRI37 R/W 0x0000.0000 PRI38 R/W 0x0000.0000 PRI39 R/W 0x0000.0000 PRI40 R/W 0x0000.0000 PRI41 R/W 0x0000.0000 PRI42 R/W 0x0000.0000 PRI43 R/W 0x0000.0000 PRI44 R/W 0x0000.0000 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map Description Interrupt 44-47 Priority Interrupt 48-51 Priority Interrupt 52-55 Priority Interrupt 56-59 Priority Interrupt 60-63 Priority Interrupt 64-67 Priority Interrupt 68-71 Priority Interrupt 72-75 Priority Interrupt 76-79 Priority Interrupt 80-83 Priority Interrupt 84-87 Priority Interrupt 88-91 Priority Interrupt 92-95 Priority Interrupt 96-99 Priority Interrupt 100-103 Priority Interrupt 104-107 Priority Interrupt 108-111 Priority Interrupt 112-115 Priority Interrupt 116-119 Priority Interrupt 120-123 Priority Interrupt 124-127 Priority Interrupt 128-131 Priority Interrupt 132-135 Priority Interrupt 136-139 Priority Interrupt 140-143 Priority Interrupt 144-147 Priority Interrupt 148-151 Priority Interrupt 152-155 Priority Interrupt 156-159 Priority Interrupt 160-163 Priority Interrupt 164-167 Priority Interrupt 168-171 Priority Interrupt 172-175 Priority Interrupt 176-179 Priority Cortex-M4 Peripherals 63 Register Map Offset 0x4B4 Table 3-2. Peripherals Register Map (continued) Name PRI45 Type R/W Reset 0x0000.0000 0x4B8 PRI46 R/W 0x0000.0000 0x4BC PRI47 R/W 0x0000.0000 0x4C0 PRI48 R/W 0x0000.0000 0x4C4 PRI49 R/W 0x0000.0000 0xF00 SWTRIG WO 0x0000.0000 System Control Block (SCB) Registers 0x008 ACTLR 0xD00 CPUID 0xD04 INTCTRL R/W 0x0000.0000 RO 0x410F.C241 R/W 0x0000.0000 0xD08 0xD0C VTABLE APINT R/W 0x0000.0000 R/W 0xFA05.0000 0xD10 0xD14 SYSCTRL CFGCTRL R/W 0x0000.0000 R/W 0x0000.0200 0xD18 SYSPRI1 R/W 0x0000.0000 0xD1C SYSPRI2 R/W 0x0000.0000 0xD20 SYSPRI3 R/W 0x0000.0000 0xD24 SYSHNDCTRL R/W 0x0000.0000 0xD28 FAULTSTAT R/W1C 0x0000.0000 0xD2C 0xD34 HFAULTSTAT MMADDR R/W1C R/W 0x0000.0000 - 0xD38 FAULTADDR R/W - www.ti.com Description Interrupt 180-183 Priority Interrupt 184-187 Priority Interrupt 188-191 Priority Interrupt 192-195 Priority Interrupt 196-199 Priority Software Trigger Interrupt Auxiliary Control CPU ID Base Interrupt Control and State Vector Table Offset Application Interrupt and Reset Control System Control Configuration and Control System Handler Priority 1 System Handler Priority 2 System Handler Priority 3 System Handler Control and State Configurable Fault Status Hard Fault Status Memory Management Fault Address Bus Fault Address 64 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1 PERIPHERAL Registers Table 3-3 lists the memory-mapped registers for the PERIPHERAL. All register offset addresses not listed in Table 3-3 should be considered as reserved locations and the register contents should not be modified. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Offset 8h 10h 14h 18h 100h to 118h 180h to 198h 200h to 218h 280h to 298h 300h to 318h 400h to 4C4h D00h D04h D08h D0Ch D10h D14h D18h D1Ch D20h D24h D28h D2Ch D38h F00h Acronym ACTLR STCTRL STRELOAD STCURRENT EN_0 to EN_6 Table 3-3. PERIPHERAL REGISTERS Register Name Auxiliary Control SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register Interrupt Set Enable DIS_0 to DIS_6 Interrupt Clear Enable PEND_0 to PEND_6 Interrupt Set Pending UNPEND_0 to UNPEND_6 Interrupt Clear Pending ACTIVE_0 to ACTIVE_6 Interrupt Active Bit PRI_0 to PRI_49 Interrupt Priority CPUID INTCTRL VTABLE APINT SYSCTRL CFGCTRL SYSPRI1 SYSPRI2 SYSPRI3 SYSHNDCTRL FAULTSTAT HFAULTSTAT FAULTDDR SWTRIG CPU ID Base Interrupt Control and State Vector Table Offset Application Interrupt and Reset Control System Control Configuration Control System Handler Priority 1 System Handler Priority 2 System Handler Priority 3 System Handler Control and State Configurable Fault Status Hard Fault Status Bus Fault Address Software Trigger Interrupt Section Section 3.3.1.1 Section 3.3.1.2 Section 3.3.1.3 Section 3.3.1.4 Section 3.3.1.5 Section 3.3.1.6 Section 3.3.1.7 Section 3.3.1.8 Section 3.3.1.9 Section 3.3.1.10 Section 3.3.1.11 Section 3.3.1.12 Section 3.3.1.13 Section 3.3.1.14 Section 3.3.1.15 Section 3.3.1.16 Section 3.3.1.17 Section 3.3.1.18 Section 3.3.1.19 Section 3.3.1.20 Section 3.3.1.21 Section 3.3.1.22 Section 3.3.1.23 Section 3.3.1.24 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 65 Register Map www.ti.com 3.3.1.1 ACTLR Register (offset = 8h) [reset = 0h] ACTLR is shown in Figure 3-1 and described in Table 3-4. NOTE: his register can only be accessed from privileged mode. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 application processor in CC3200 and does not normally require modification. Figure 3-1. ACTLR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED DISFOLD R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 DISOOFP R/W-0h 1 DISWBUF R/W-0h 24 16 8 DISFPCA R/W-0h 0 DISMCYC R/W-0h Bit 31-10 9 8 7-3 2 Field RESERVED DISOOFP DISFPCA RESERVED DISFOLD 1 DISWBUF 0 DISMCYC Table 3-4. ACTLR Register Field Descriptions Type R R/W R/W R R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description Disable Out-Of-Order Floating Point. N/A for CC3200. Disable IT Folding In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. 0h = No effect. 1h = Disables IT folding. Disable IT Folding In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. 0h = No effect. 1h = Disables IT folding. Disable Interrupts of Multiple Cycle Instructions In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. 0h = No effect. 1h = Disables interruption of load multiple and store multiple instructions. 66 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.2 STCTRL Register (offset = 10h) [reset = 0h] STCTRL is shown in Figure 3-2 and described in Table 3-5. NOTE: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. Figure 3-2. STCTRL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED CLK_SRC R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 INTEN R/W-0h 24 16 COUNT R-0h 8 0 ENABLE R/W-0h Bit 31-17 16 Field RESERVED COUNT 15-3 2 RESERVED CLK_SRC 1 INTEN 0 ENABLE Table 3-5. STCTRL Register Field Descriptions Type R R R R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h Description Count Flag This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM Debug Interface V5 Architecture Specification for more information on MasterType. 0h = The SysTick timer has not counted to 0 since the last time this bit was read. 1h = The SysTick timer has counted to 0 since the last time this bit was read. Clock Source 0h = Precision internal oscillator (PIOSC) divided by 4 1h = System clock Interrupt Enable 0h = Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1h = An interrupt is generated to the NVIC when SysTick counts to 0. Enable 0h = The counter is disabled. 1h = Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 67 Register Map www.ti.com 3.3.1.3 STRELOAD Register (offset = 14h) [reset = 0h] STRELOAD is shown in Figure 3-3 and described in Table 3-6. NOTE: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. Note that in order to access this register correctly, the system clock must be faster than 8 MHz. Figure 3-3. STRELOAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RELOAD R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-24 23-0 Field RESERVED RELOAD Table 3-6. STRELOAD Register Field Descriptions Type R R/W Reset 0h 0h Description Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. 68 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.4 STCURRENT Register (offset = 18h) [reset = 0h] STCURRENT is shown in Figure 3-4 and described in Table 3-7. NOTE: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. Figure 3-4. STCURRENT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CURRENT R-0h R/WC-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-24 23-0 Field RESERVED CURRENT Table 3-7. STCURRENT Register Field Descriptions Type R R/WC Reset 0h 0h Description Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 69 Register Map www.ti.com 3.3.1.5 EN_0 to EN_6 Register (offset = 100h to 118h) [reset = 0h] EN_0 to EN_6 is shown in Figure 3-5 and described in Table 3-8. NOTE: This register can only be accessed from privileged mode. The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of EN5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of EN6 corresponds to interrupt 192; bit 7 corresponds to interrupt 199. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Figure 3-5. EN_0 to EN_6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field INT Table 3-8. EN_0 to EN_6 Register Field Descriptions Type R/W Reset 0h Description Interrupt Enable A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, enables the interrupt. 1h (R) = On a read, indicates the interrupt is enabled. 70 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.6 DIS_0 to DIS_6 Register (offset = 180h to 198h) [reset = 0h] DIS_0 to DIS_6 is shown in Figure 3-6 and described in Table 3-9. NOTE: This register can only be accessed from privileged mode. The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of DIS5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of DIS6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199. Figure 3-6. DIS_0 to DIS_6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field INT Table 3-9. DIS_0 to DIS_6 Register Field Descriptions Type R/W Reset 0h Description Interrupt Disable EN5 (for DIS5) register EN6 (for DIS6) register 0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, no effect. 1h (R) = On a read, indicates the interrupt is enabled. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 71 Register Map www.ti.com 3.3.1.7 PEND_0 to PEND_6 Register (offset = 200h to 218h) [reset = 0h] PEND_0 to PEND_6 is shown in Figure 3-7 and described in Table 3-10. NOTE: This register can only be accessed from privileged mode. The PENDn registers force interrupts into the pending state and show which interrupts are pending. Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of PEND4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of PEND5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of PEND6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199. Figure 3-7. PEND_0 to PEND_6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field INT Table 3-10. PEND_0 to PEND_6 Register Field Descriptions Type R/W Reset 0h Description Interrupt Set Pending If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 (for PEND0 to PEND3) register UNPEND4 (for PEND4) register UNPEND5 (for PEND5) register UNPEND6 (for PEND6) register 0h (W) = On a write, no effect. 0h (R) = On a read, indicates that the interrupt is not pending. 1h (W) = On a write, the corresponding interrupt is set to pending even if it is disabled. 1h (R) = On a read, indicates that the interrupt is pending. 72 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.8 UNPEND_0 to UNPEND_6 Register (offset = 280h to 298h) [reset = 0h] UNPEND_0 to UNPEND_6 is shown in Figure 3-8 and described in Table 3-11. NOTE: This register can only be accessed from privileged mode. The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 159. Bit 0 of UNPEND5 corresponds to Interrupt 160; bit 31 corresponds to interrupt 191. Bit 0 of UNPEND6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199. Figure 3-8. UNPEND_0 to UNPEND_6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field INT Table 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions Type R/W Reset 0h Description Interrupt Clear Pending Setting a bit does not affect the active state of the corresponding interrupt. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates that the interrupt is not pending. 1h (W) = On a write, clears the corresponding INT[n] bit in the PEND0 (for UNPEND0 to UNPEND3) register PEND4 (for UNPEND4) register PEND5 (for UNPEND5) register PEND6 (for UNPEND6) register so that interrupt [n] is no longer pending. 1h (R) = On a read, indicates that the interrupt is pending. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 73 Register Map www.ti.com 3.3.1.9 ACTIVE_0 to ACTIVE_6 Register (offset = 300h to 318h) [reset = 0h] ACTIVE_0 to ACTIVE_6 is shown in Figure 3-9 and described in Table 3-12. The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of ACTIVE4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of ACTIVE5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of ACTIVE6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199. CAUTION: Do not manually set or clear the bits in this register. Figure 3-9. ACTIVE_0 to ACTIVE_6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field INT Table 3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions Type R Reset 0h Description Interrupt Active 0h = The corresponding interrupt is not active. 1h = The corresponding interrupt is active, or active and pending. 74 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.10 PRI_0 to PRI_49 Register (offset = 400h to 4C4h) [reset = 0h] PRI_0 to PRI_49 is shown in Figure 3-10 and described in Table 3-13. NOTE: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: bits 31 to 29 have interrupt [4n+3], bits 23 to 21 have interrupt [4n+2], bits 15 to 13 have interrupt [4n+1], and bits 7 to have interrupt [4n]. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. Figure 3-10. PRI_0 to PRI_49 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTD RESERVED INTC RESERVED R/W-0h R-0h R/W-0h R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTB RESERVED INTA RESERVED R/W-0h R-0h R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-29 Field INTD 28-24 23-21 RESERVED INTC 20-16 15-13 RESERVED INTB 12-8 7-5 RESERVED INTA 4-0 RESERVED Table 3-13. PRI_0 to PRI_49 Register Field Descriptions Type R/W R R/W R R/W R R/W R Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 75 Register Map www.ti.com 3.3.1.11 CPUID Register (offset = D00h) [reset = 410FC241h] CPUID is shown in Figure 3-11 and described in Table 3-14. NOTE: his register can only be accessed from privileged mode. The CPUID register contains the ARM Cortex -M4 processor part number, version, and implementation information. Figure 3-11. CPUID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMP VAR CON PARTNO REV R-41h R-0h R-Fh R-C24h R-1h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-24 Field IMP 23-20 VAR 19-16 CON 15-4 PARTNO 3-0 REV Table 3-14. CPUID Register Field Descriptions Type R R R R R Reset 41h 0h Fh C24h 1h Description Implementer Code 41h = ARM Variant Number 0h = The rn value in the rnpn product revision identifier, for example, the 0 in r0p0. Variant Number 0h = The rn value in the rnpn product revision identifier, for example, the 0 in r0p0. Part Number C24h = Cortex-M4 application processor in CC3200. Revision Number 1h = The pn value in the rnpn product revision identifier, for example, the 1 in r0p1. 76 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.1.12 INTCTRL Register (offset = D04h) [reset = 0h] INTCTRL is shown in Figure 3-12 and described in Table 3-15. 31 NMISET R/W-0h 30 29 RESERVED R-0h Figure 3-12. INTCTRL Register 28 27 26 PENDSV UNPENDSV PENDSTSET R/W-0h W-0h R/W-0h 25 PENDSTCLR W-0h 23 22 21 20 19 18 17 ISRPRE ISRPEND RESERVED VECPEND R-0h R-0h R-0h R-0h 15 14 13 12 11 10 9 VECPEND RETBASE RESERVED R-0h R-0h R-0h 7 6 5 4 3 2 1 VECACT R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Register Map 24 RESERVED R-0h 16 8 0 Bit Field 31 NMISET 30-29 28 RESERVED PENDSV 27 UNPENDSV 26 PENDSTSET Table 3-15. INTCTRL Register Field Descriptions Type R/W R R/W W R/W Reset 0h 0h 0h 0h 0h Description NMI Set Pending Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates an NMI exception is not pending. 1h (W) = On a write, changes the NMI exception state to pending. 1h (R) = On a read, indicates an NMI exception is pending. PendSV Set Pending Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates a PendSV exception is not pending. 1h (W) = On a write, changes the PendSV exception state to pending. 1h (R) = On a read, indicates a PendSV exception is pending. PendSV Clear Pending This bit is write only on a register read, its value is unknown. 0h = On a write, no effect. 1h = On a write, removes the pending state from the PendSV exception. SysTick Set Pending This bit is cleared by writing a 1 to the PENDSTCLR bit. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates a SysTick exception is not pending. 1h (W) = On a write, changes the SysTick exception state to pending. 1h (R) = On a read, indicates a SysTick exception is pending. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 77 Register Map www.ti.com Bit 25 24 23 22 21-20 19-12 11 10-8 7-0 Table 3-15. INTCTRL Register Field Descriptions (continued) Field PENDSTCLR RESERVED ISRPRE ISRPEND RESERVED VECPEND RETBASE RESERVED VECACT Type W R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description SysTick Clear Pending This bit is write only on a register read, its value is unknown. 0h = On a write, no effect. 1h = On a write, removes the pending state from the SysTick exception. Debug Interrupt Handling This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 0h = The release from halt does not take an interrupt. 1h = The release from halt takes an interrupt. Interrupt Pending This bit provides status for all interrupts excluding NMI and Faults. 0h = No interrupt is pending. 1h = An interrupt is pending. Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. 7h- Ah = Reserved ... 0h = No exceptions are pending 1h = Reserved 2h = NMI 3h = Hard fault 4h = Memory management fault 5h = Bus fault 6h = Usage fault Bh = SVCall Ch = Reserved for Debug Dh = Reserved Eh = PendSV Fh = SysTick 10h = Interrupt Vector 0 11h = Interrupt Vector 1 D9h = Interrupt Vector 199 Return to Base This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 0h = There are preempted active exceptions to execute. 1h = There are no active exceptions, or the currently executing exception is the only active exception. Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers. 78 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.13 VTABLE Register (offset = D08h) [reset = 0h] VTABLE is shown in Figure 3-13 and described in Table 3-16. NOTE: his register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Figure 3-13. VTABLE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET RESERVED R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-10 Field OFFSET 9-0 RESERVED Table 3-16. VTABLE Register Field Descriptions Type R/W R Reset 0h 0h Description Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 199 interrupts, the offset must be aligned on a 1024-byte boundary. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 79 Register Map www.ti.com 3.3.1.14 APINT Register (offset = D0Ch) [reset = FA050000h] APINT is shown in Figure 3-14 and described in Table 3-17. NOTE: his register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. NOTE: Determining preemption of an exception uses only the group priority field. PRIGROUP Bit Field = Binary Point = Group Priority Field = Subpriority Field = Group Priorities = Subpriorities 0h-4h = bxxx = [7:5] = None = 8 = 1 5h = bxx.y = [7:6] = [5] = 4 = 2 6h = bx.yy = [7] = [6:5] = 2 = 4 7h = b.yyy = None = [7:5] = 1 = 8 INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Figure 3-14. APINT Register 31 30 29 28 27 26 VECTKEY R/W-FA05h 23 22 21 20 19 18 VECTKEY R/W-FA05h 15 14 13 12 11 10 ENDIANESS RESERVED R-0h R-0h 7 6 5 4 3 2 RESERVED SYSRESREQ R-0h W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 PRIGROUP R/W-0h 1 VECTCLRACT W-0h 24 16 8 0 VECTRESET W-0h Bit 31-16 Field VECTKEY 15 14-11 10-8 7-3 2 ENDIANESS RESERVED PRIGROUP RESERVED SYSRESREQ 1 VECTCLRACT 0 VECTRESET Table 3-17. APINT Register Field Descriptions Type R/W R R R/W R W W W Reset FA05h 0h 0h 0h 0h 0h 0h 0h Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. Data Endianess The CC3200 implementation uses only little-endian mode so this is cleared to 0. Interrupt Priority Grouping This field determines the split of group priority from subpriority System Reset Request This bit is automatically cleared during the reset of the core and reads as 0. 0h = No effect. 1h = Resets the core and all on-chip peripherals except the Debug interface. Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 80 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.15 SYSCTRL Register (offset = D10h) [reset = 0h] SYSCTRL is shown in Figure 3-15 and described in Table 3-18. NOTE: his register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. Figure 3-15. SYSCTRL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED SEVONPEND RESERVED SLEEPDEEP R-0h R/W-0h R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 SLEEPEXIT R/W-0h 24 16 8 0 RESERVED R-0h Bit 31-5 4 Field RESERVED SEVONPEND 3 RESERVED 2 SLEEPDEEP 1 SLEEPEXIT 0 RESERVED Table 3-18. SYSCTRL Register Field Descriptions Type R R/W R R/W R/W R Reset 0h 0h 0h 0h 0h 0h Description Wake Up on Pending 0h = Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1h = Enabled events and all interrupts, including disabled interrupts, can wake up the processor. Deep Sleep Enable 0h = Use Sleep mode as the low power mode. 1h = Use Deep-sleep mode as the low power mode. Sleep on ISR Exit Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0h = When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1h = When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 81 Register Map www.ti.com 3.3.1.16 CFGCTRL Register (offset = D14h) [reset = 200h] CFGCTRL is shown in Figure 3-16 and described in Table 3-19. NOTE: his register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software. Figure 3-16. CFGCTRL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 RESERVED R-0h 4 DIV0 R/W-0h 3 UNALIGNED R/W-0h 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 STKALIGN R/W-1h 1 MANIPEND R/W-0h 24 16 8 BFHFMIGN R/W-0h 0 BASETHR R/W-0h Bit 31-10 9 Field RESERVED STKALIGN 8 BFHFMIGN 7-5 RESERVED 4 DIV0 3 UNALIGNED Table 3-19. CFGCTRL Register Field Descriptions Type R R/W R/W R R/W R/W Reset 0h 1h 0h 0h 0h 0h Description Stack Alignment on Exception Entry On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 0h = The stack is 4-byte aligned. 1h = The stack is 8-byte aligned. Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0h = Data bus faults caused by load and store instructions cause a lock-up. 1h = Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. 0h = Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1h = Trap on divide by 0. Trap on Unaligned Access Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 0h = Do not trap on unaligned halfword and word accesses. 1h = Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. 82 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 3-19. CFGCTRL Register Field Descriptions (continued) Bit Field 2 RESERVED 1 MANIPEND 0 BASETHR Type R R/W R/W Reset 0h 0h 0h Description Allow Main Interrupt Trigger 0h = Disables unprivileged software access to the SWTRIG register. 1h = Enables unprivileged software access to the SWTRIG register. Thread State Control 0h = The processor can enter Thread mode only when no exception is active. 1h = The processor can enter Thread mode from any level under the control of an EXC_RETURN value. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 83 Register Map www.ti.com 3.3.1.17 SYSPRI1 Register (offset = D18h) [reset = 0h] SYSPRI1 is shown in Figure 3-17 and described in Table 3-20. NOTE: his register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. Figure 3-17. SYSPRI1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED USAGE RESERVED R-0h R/W-0h R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS RESERVED MEM RESERVED R/W-0h R-0h R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-24 23-21 Field RESERVED USAGE 20-16 15-13 RESERVED BUS 12-8 7-5 RESERVED MEM 4-0 RESERVED Table 3-20. SYSPRI1 Register Field Descriptions Type R R/W R R/W R R/W R Reset 0h 0h 0h 0h 0h 0h 0h Description Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 84 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.18 SYSPRI2 Register (offset = D1Ch) [reset = 0h] SYSPRI2 is shown in Figure 3-18 and described in Table 3-21. NOTE: his register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. Figure 3-18. SYSPRI2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVC RESERVED R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-29 Field SVC 28-0 RESERVED Table 3-21. SYSPRI2 Register Field Descriptions Type R/W R Reset 0h 0h Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 85 Register Map www.ti.com 3.3.1.19 SYSPRI3 Register (offset = D20h) [reset = 0h] SYSPRI3 is shown in Figure 3-19 and described in Table 3-22. NOTE: his register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. Figure 3-19. SYSPRI3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TICK RESERVED PENDSV RESERVED R/W-0h R-0h R/W-0h R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DEBUG RESERVED R-0h R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-29 Field TICK 28-24 23-21 RESERVED PENDSV 20-8 7-5 RESERVED DEBUG 4-0 RESERVED Table 3-22. SYSPRI3 Register Field Descriptions Type R/W R R/W R R/W R Reset 0h 0h 0h 0h 0h 0h Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 86 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.20 SYSHNDCTRL Register (offset = D24h) [reset = 0h] SYSHNDCTRL is shown in Figure 3-20 and described in Table 3-23. NOTE: his register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. CAUTION: Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. Figure 3-20. SYSHNDCTRL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED USAGE R-0h R/W-0h 15 SVC R/W-0h 14 BUSP R/W-0h 13 MEMP R/W-0h 12 USAGEP R/W-0h 11 TICK R/W-0h 10 PNDSV R/W-0h 7 SVCA R/W-0h 6 5 4 RESERVED R-0h 3 USGA R/W-0h 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 BUS R/W-0h 9 RESERVED R-0h 1 BUSA R/W-0h 24 16 MEM R/W-0h 8 MON R/W-0h 0 MEMA R/W-0h Bit 31-19 18 Field RESERVED USAGE 17 BUS 16 MEM 15 SVC 14 BUSP Table 3-23. SYSHNDCTRL Register Field Descriptions Type R R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h Description Usage Fault Enable 0h = Disables the usage fault exception. 1h = Enables the usage fault exception. Bus Fault Enable 0h = Disables the bus fault exception. 1h = Enables the bus fault exception. Memory Management Fault Enable 0h = Disables the memory management fault exception. 1h = Enables the memory management fault exception. SVC Call Pending This bit can be modified to change the pending status of the SVC call exception. 0h = An SVC call exception is not pending. 1h = An SVC call exception is pending. Bus Fault Pending This bit can be modified to change the pending status of the bus fault exception. 0h = A bus fault exception is not pending. 1h = A bus fault exception is pending. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 87 Register Map www.ti.com Table 3-23. SYSHNDCTRL Register Field Descriptions (continued) Bit Field 13 MEMP 12 USAGEP 11 TICK 10 PNDSV 9 RESERVED 8 MON 7 SVCA 6-4 RESERVED 3 USGA 2 RESERVED 1 BUSA 0 MEMA Type R/W R/W R/W R/W R R/W R/W R R/W R R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Memory Management Fault Pending This bit can be modified to change the pending status of the memory management fault exception. 0 = A memory management fault exception is not pending. 1 = A memory management fault exception is pending. Usage Fault Pending This bit can be modified to change the pending status of the usage fault exception. 0h = A usage fault exception is not pending. 1h = A usage fault exception is pending. SysTick Exception Active This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 0h = A SysTick exception is not active. 1h = A SysTick exception is active. PendSV Exception Active This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 0h = A PendSV exception is not active. 1h = A PendSV exception is active. Debug Monitor Active 0h = The Debug monitor is not active. 1h = The Debug monitor is active. SVC Call Active This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 0h = SVC call is not active. 1h = SVC call is active. Usage Fault Active This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 0h = Usage fault is not active. 1h = Usage fault is active. Bus Fault Active This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 0h = Bus fault is not active. 1h = Bus fault is active. Memory Management Fault Active This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 0h = Memory management fault is not active. 1h = Memory management fault is active. 88 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.21 FAULTSTAT Register (offset = D28h) [reset = 0h] FAULTSTAT is shown in Figure 3-21 and described in Table 3-24. NOTE: his register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: Usage Fault Status (UFAULTSTAT), bits 31:16 Bus Fault Status (BFAULTSTAT), bits 15:8 Memory Management Fault Status (MFAULTSTAT), bits 7:0 (Not applicable for CC3200) FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: The complete FAULTSTAT register, with a word access to offset 0xD28 The MFAULTSTAT, with a byte access to offset 0xD28 The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 The BFAULTSTAT, with a byte access to offset 0xD29 The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Figure 3-21. FAULTSTAT Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED NOCP INVPC R-0h R/W1C-0h R/W1C-0h 15 BFARV R/W1C-0h 14 RESERVED R-0h 13 BLSPERR R/W1C-0h 12 BSTKE R/W1C-0h 11 BUSTKE R/W1C-0h 10 IMPRE R/W1C-0h 7 MMARV R/W1C-0h 6 RESERVED R-0h 5 MLSPERR R/W1C-0h 4 MSTKE R/W1C-0h 3 MUSTKE R/W1C-0h 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 DIV0 R/W1C-0h 17 INVSTAT R/W1C-0h 9 PRECISE R/W1C-0h 1 DERR R/W1C-0h 24 UNALIGN R/W1C-0h 16 UNDEF R/W1C-0h 8 IBUS R/W1C-0h 0 IERR R/W1C-0h Bit 31-26 25 Field RESERVED DIV0 24 UNALIGN 23-20 RESERVED Table 3-24. FAULTSTAT Register Field Descriptions Type R R/W1C Reset 0h 0h R/W1C 0h R 0h Description Divide-by-Zero Usage Fault When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register. This bit is cleared by writing a 1 to it. 0h = No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1h = The processor has executed an SDIV or UDIV instruction with a divisor of 0. Unaligned Access Usage Fault Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register. This bit is cleared by writing a 1 to it. 0h = No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1h = The processor has made an unaligned memory access. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 89 Register Map www.ti.com Table 3-24. FAULTSTAT Register Field Descriptions (continued) Bit Field 19 NOCP 18 INVPC 17 INVSTAT 16 UNDEF 15 BFARV 14 RESERVED 13 BLSPERR 12 BSTKE 11 BUSTKE Type R/W1C Reset 0h R/W1C 0h R/W1C 0h R/W1C 0h R/W1C 0h R 0h R/W1C 0h R/W1C 0h R/W1C 0h Description No Coprocessor Usage Fault This bit is cleared by writing a 1 to it. 0h = A usage fault has not been caused by attempting to access a coprocessor. 1h = The processor has attempted to access a coprocessor. Invalid PC Load Usage Fault When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. 0h = A usage fault has not been caused by attempting to load an invalid PC value. 1h = The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. Invalid State Usage Fault When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 0h = A usage fault has not been caused by an invalid state. 1h = The processor has attempted to execute an instruction that makes illegal use of the EPSR register. Undefined Instruction Usage Fault When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 0h = A usage fault has not been caused by an undefined instruction. 1h = The processor has attempted to execute an undefined instruction. Bus Fault Address Register Valid This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 0h = The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1h = The FAULTADDR register is holding a valid fault address. N/A Stack Bus Fault When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 0h = No bus fault has occurred on stacking for exception entry. 1h = Stacking for an exception entry has caused one or more bus faults. Unstack Bus Fault This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 0h = No bus fault has occurred on unstacking for a return from exception. 1h = Unstacking for a return from exception has caused one or more bus faults. 90 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 3-24. FAULTSTAT Register Field Descriptions (continued) Bit Field 10 IMPRE 9 PRECISE 8 IBUS 7 MMARV 6 RESERVED 5 MLSPERR 4 MSTKE 3 MUSTKE 2 RESERVED Type R/W1C Reset 0h R/W1C 0h R/W1C 0h R/W1C 0h R 0h R/W1C 0h R/W1C 0h R/W1C 0h R 0h Description Imprecise Data Bus Error When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 0h = An imprecise data bus error has not occurred. 1h = A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. Precise Data Bus Error When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 0h = A precise data bus error has not occurred. 1h = A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. Instruction Bus Error The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 0h = An instruction bus error has not occurred. 1h = An instruction bus error has occurred. Memory Management Fault Address Register Valid If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. 0h = The This bit is cleared by writing a 1 to it. value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1h = The MMADDR register is holding a valid fault address. N/A Stack Access Violation When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 0h = No memory management fault has occurred on stacking for exception entry. 1h = Stacking for an exception entry has caused one or more access violations. Unstack Access Violation This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 0h = No memory management fault has occurred on unstacking for a return from exception. 1h = Unstacking for a return from exception has caused one or more access violations. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 91 Register Map Bit Field 1 DERR 0 IERR www.ti.com Table 3-24. FAULTSTAT Register Field Descriptions (continued) Type R/W1C Reset 0h R/W1C 0h Description Data Access Violation When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 0h = A data access violation has not occurred. 1h = The processor attempted a load or store at a location that does not permit the operation. Instruction Access Violation This fault occurs on any access to an XN region. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 0h = An instruction access violation has not occurred. 1h = The processor attempted an instruction fetch from a location that does not permit execution. 92 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.22 HFAULTSTAT Register (offset = D2Ch) [reset = 0h] HFAULTSTAT is shown in Figure 3-22 and described in Table 3-25. NOTE: his register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. 31 DBG R/W1C-0h 30 FORCED R/W1C-0h Figure 3-22. HFAULTSTAT Register 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 1 VECT R/W1C-0h 0 RESERVED R-0h Bit Field 31 DBG 30 FORCED 29-2 1 RESERVED VECT 0 RESERVED Table 3-25. HFAULTSTAT Register Field Descriptions Type R/W1C R/W1C Reset 0h 0h R 0h R/W1C 0h R 0h Description Debug EventThis bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. Forced Hard Fault When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 0h = No forced hard fault has occurred. 1h = A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. Vector Table Read Fault This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0h = No bus fault has occurred on a vector table read. 1h = A bus fault occurred on a vector table read. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 93 Register Map www.ti.com 3.3.1.23 FAULTDDR Register (offset = D38h) [reset = 0h] FAULTDDR is shown in Figure 3-23 and described in Table 3-26. NOTE: his register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid. Figure 3-23. FAULTDDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field ADDR Table 3-26. FAULTDDR Register Field Descriptions Type R/W Reset 0h Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 94 Cortex-M4 Peripherals SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 3.3.1.24 SWTRIG Register (offset = F00h) [reset = 0h] SWTRIG is shown in Figure 3-24 and described in Table 3-27. NOTE: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). When the MAINPEND bit in the Configuration and Control (CFGCTRL) register is set, unprivileged software can access the SWTRIG register. Figure 3-24. SWTRIG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED INTID R-0h W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED INTID Table 3-27. SWTRIG Register Field Descriptions Type R W Reset 0h 0h Description Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Cortex-M4 Peripherals 95 Chapter 4 SWRU367B – June 2014 – Revised October 2014 Direct Memory Access (DMA) Topic ........................................................................................................................... Page 4.1 Overview ........................................................................................................... 97 4.2 Functional Description........................................................................................ 97 4.3 Register Description ......................................................................................... 107 96 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 4.1 Overview The CC3200 microcontroller includes a Direct Memory Access (DMA) controller, known as micro- DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex ™ -M4 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: • 32-channel configurable µDMA controller • Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request • Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Optional software-initiated requests for any channel • Two levels of priority • Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access • Data sizes of 8, 16, and 32 bits • Transfer size is programmable in binary steps from 1 to 1024 • Source and destination address increment size of byte, half-word, word, or no increment • Interrupt on transfer completion, with a separate interrupt per channel 4.2 Functional Description The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the microcontroller's Cortex-M4 processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the μDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include peripheral bus segmentation, which in many cases allow both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 97 Functional Description www.ti.com Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the μDMA controller re-arbitrates for channel priority. Using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request. 4.2.1 Channel Assignment The following table depicts μDMA channel allocation. There ae 32 DMA channels assigned to various peripherals. Peripheral are mapped at multiple places in order to address the application need where any combination of peripheral can be used in tandem. Figure 4-1. DMA Channel Assignment 98 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 4.2.2 Priority The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using the DMA Channel Priority Set (PRIOSET) register and cleared with the DMA Channel Priority Clear (PRIOCLR) register. 4.2.3 Arbitration Size When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making a request and services the μDMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before re-arbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels is increased because the μDMA controller completes the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer. 4.2.4 Channel Configuration The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each μDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. Table 4-1 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. The table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. The primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Offset 0x0 0x10 …. 0x1F0 0x200 0x210 …. Table 4-1. Channel Control Memory Channel Channel 0 – primary Channel 1 – primary Channel 31 – primary Channel 0 – Alternate Channel 1 – Alternate SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 99 Functional Description Table 4-1. Channel Control Memory (continued) Offset 0x3F0 Channel Channel 31 – Alternate www.ti.com Table 4-2 shows an individual control structure entry in the control table. Each entry is aligned on a 16byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The end pointers point to the ending address of the transfer and are inclusive. If the source or destination is non- incrementing (as for a peripheral register), then the pointer should point to the transfer address. Offset 0x000 0x004 0x008 0x00C Table 4-2. Individual Control Structure Description Source End pointer Destination End pointer Control Word Reserved Transfer size is part of control word. At the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMA Channel Enable Set (ENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (ENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel. 4.2.5 Transfer Mode The μDMA controller supports several transfer modes. Two of the modes support simple one- time transfers. Several complex modes support a continuous flow of data. 4.2.5.1 Stop Mode While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller does not perform any transfers and disables the channel if it is enabled. 4.2.5.2 Basic Mode In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer, and a transfer request is present. This mode is used with peripherals that assert a μDMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. For example, a software-initiated transfer creates a momentary request, and in Basic mode, only the number of transfers specified by the ARBSIZE field in the DMA Channel Control Word register is transferred on a software request, even if there is more data to transfer. When all of the items have been transferred using Basic mode, the μDMA controller sets the mode for that channel to Stop. 4.2.5.3 Auto Mode Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer runs to completion, even if the μDMA request is removed. This mode is suitable for software- triggered transfers. Generally, Auto mode is not used with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller sets the mode for that channel to Stop 100 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 4.2.5.4 Ping-Pong Mode Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping- Pong mode, both the primary and alternate data structures must be implemented. Both structures are set up by the processor for data transfer between memory and a peripheral. The transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller reads the alternate control structure for that channel to continue the transfer. Each time this happens, an interrupt is generated, and the processor can reload the control structure for the justcompleted transfer. Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 101 Functional Description Figure 4-2. Ping-Pong Mode www.ti.com 102 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 4.2.5.5 Memory Scatter-Gather Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. The end of the list is marked by programming the control word for the last entry to use Basic transfer mode. Once the last transfer is performed using Basic mode, the μDMA controller stops. A completion interrupt is generated only after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a μDMA request. By programming the μDMA controller using this method, a set of arbitrary transfers can be performed based on a single μDMA request. Figure 4-3 shows an example of operation in Memory Scatter-Gather mode. This example shows a gather operation, where data in three separate buffers in memory is copied together into one buffer. Figure 4-3 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 103 Functional Description Figure 4-3. Memory Scatter-Gather Mode www.ti.com (1) Application has a need to copy data items from three separate locations in memory into one combined buffer. (2) Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” (3) Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller 4.2.5.6 Peripheral Scatter-Gather Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. At the end of this transfer, the next transfer is started only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt is generated only after the last transfer. By using this method, the μDMA controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. 104 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Figure 4-4. Peripheral Scatter-Gather Mode Functional Description (1) Application has a need to copy data items from three separate locations in memory into a peripheral data register. (2) Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” (3) Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller 4.2.6 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). Table 4-3 shows the configuration to read from a peripheral that supplies 8-bit data. Field Source data size Destination data size Source address increment Destination address increment Source end pointer Destination end pointer Table 4-3. 8-bit Data Peripheral Configuration Configuration 8 bit 8 bit No Byte Peripheral FIFO register End of data buffer in memory SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 105 Functional Description 4.2.7 Peripheral Interface There are two main classes of uDMA-connected peripherals: • Peripherals with FIFOs serviced by the uDMA to transmit or receive data. • Peripherals that provide trigger inputs to the uDMA. www.ti.com 4.2.7.1 FIFO Peripherals FIFO peripherals contain a FIFO of data to be sent and a FIFO of data that has been received. The uDMA controller is used to transfer data between these FIFOs and system memory. For example, when a UART FIFO contains one or more entries, a single transfer request is sent to the uDMA for processing. If this request has not been processed and the UART FIFO reaches the interrupt FIFO level, another interrupt is sent to the uDMA which is higher priority than the single-transfer request. In this instance, an ARBSIZ transfer is performed as configured in the DMACHCTL register. After the transfer is complete, the DMA sends a receive or transmit complete interrupt to the UART register. If the FIFO peripheral's SETn bit is set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register, then the uDMA will only perform transfers defined by the ARBSIZ bit field in the DMACHCTL register for better bus utilization. For peripherals that tend to transmit and receive in bursts, such as the UART, we recommend against the use of this configuration since it could cause the tail end of transmissions to stick in the FIFO. 4.2.7.2 Trigger Peripherals Certain peripherals, such as the general purpose timer, trigger an interrupt to the uDMA controller when a programmed event occurs. When a trigger event occurs, the uDMA executes a transfer defined by the ARBSIZ bit field in the DMACHCTL register. If only a single transfer is needed for a uDMA trigger, then the ARBSIZ field is set to 0x1. If the trigger peripheral generates another uDMA request while the prior one is being serviced and that particular channel is the highest priority asserted channel, the second request will be processed as soon as the handling of the first is complete. If two additional trigger peripheral uDMA requests are generated prior to the completion of the first, the third request is lost. 4.2.7.3 Software Request Few μDMA channels are dedicated to software-initiated transfers. This channel also has a dedicated interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the DMA Channel Software Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be used. It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used for software requests as long as the corresponding peripheral is not using μDMA for data transfer. 4.2.8 Interrupts and Errors When a μDMA transfer is complete, a dma_done signal is sent to the peripheral that initiated the μDMA event. Interrupts can be enabled within the peripheral to trigger on μDMA transfer completion. If the transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt vector. If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit. 106 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3 Register Description Register Description 4.3.1 DMA Register Map Table below lists the μDMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, thus, the base address is n/a (not applicable) and noted as so above the register descriptions. In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See Table 4-1 for description of how the entries in the channel control table are located in memory. The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers can be programmed. There must be a delay of three system clocks after the μDMA module clock is enabled before any μDMA module registers are accessed. Offset 0x000 0x004 0x008 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x04C Table 4-4. µDMA Register Map Name Type Reset Description μDMA Channel Control Structure (Offset from Channel Control Table Base) DMA_SRCENDP R/W - DMA Channel Source Address End Pointer DMA_DSTENDP R/W - DMA Channel Destination Address End Pointer DMA_CHCTL R/W - DMA Channel Control Word μDMA Registers (Offset from μDMA Base Address) DMA_STAT RO 0x001F.0000 DMA_CFG WO - DMA Configuration DMA_CTLBASE R 0x0000.0000 DMA Channel Control Base Pointer DMA_ALTBASE RO 0x0000.0200 DMA Alternate Channel Control Base Pointer DMA_WAITSTAT RO 0x03C3.CF00 DMA Channel Wait-on- Request Status DMA_SWREQ WO - DMA Channel Software Request DMA_USEBURSTSET R/W 0x0000.0000 DMA Channel Useburst Set DMA_USEBURSTCLR WO - DMA Channel Useburst Clear DMA_REQMASKSET R/W 0x0000.0000 DMA Channel Request Mask Set DMA_REQMASKCLR WO - DMA Channel Request Mask Clear DMA_ENASET R/W 0x0000.0000 DMA Channel Enable Set DMA_ENACLR WO - DMA Channel Enable Clear DMA_ALTSET R/W 0x0000.0000 DMA Channel Primary Alternate Set DMA_ALTCLR WO - DMA Channel Primary Alternate Clear DMA_PRIOSET R/W 0x0000.0000 DMA Channel Priority Set DMA_PRIOCLR WO - DMA Channel Priority Clear DMA_ERRCLR R/W 0x0000.0000 DMA Bus Error Clear SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 107 Register Description Offset 0x500 0x510 0x514 0x518 0x51C 0xFB0 Table 4-4. µDMA Register Map (continued) Name DMA_CHASGN Type R/W Reset 0x0000.0000 DMA_CHMAP0 R/W 0x0000.0000 DMA_CHMAP1 R/W 0x0000.0000 DMA_CHMAP2 R/W 0x0000.0000 DMA_CHMAP3 R/W 0x0000.0000 DMA_PV RO 0x0000.0200 www.ti.com Description DMA Channel Assignment DMA Channel Map Select 0 DMA Channel Map Select 1 DMA Channel Map Select 2 DMA Channel Map Select 3 DMA peripheral Version 4.3.2 µDMA Channel Control Structure The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel has two control structures, which are located in a table in system memory. The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. 108 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 4.3.3 DMA Registers Table 4-5 lists the memory-mapped registers for the DMA_(OFFSET_FROM_CHANNEL_CONTROL_TABLE_BASE). All register offset addresses not listed in Table 4-5 should be considered as reserved locations and the register contents should not be modified. Table below lists the DMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, thus, the base address is n/a (not applicable) and noted as so above the register descriptions. In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See Channel Configuration table for description of how the entries in the channel control table are located in memory. The DMA register addresses are given as a hexadecimal increment, relative to the DMA base address of 0x400F.F000. Note that the DMA module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the DMA module clock is enabled before any DMA module registers are accessed. The DMA Channel Control Structure holds the transfer settings for a DMA channel. Each channel has two control structures, which are located in a table in system memory. The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. Offset 0h 4h 8h Acronym DMA_SRCENDP DMA_DSTENDP DMA_CHCTL Table 4-5. DMA Registers Register Name DMA Channel Source Address End Pointer DMA Channel Destination Address End Pointer DMA Channel Control Word Section Section 4.3.3.1 Section 4.3.3.2 Section 4.3.3.3 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 109 Register Description 4.3.3.1 DMA_SRCENDP Register (offset = 0h) [reset = 0h] DMA_SRCENDP is shown in Figure 4-5 and described in Table 4-6. www.ti.com Figure 4-5. DMA_SRCENDP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field ADDR Table 4-6. DMA_SRCENDP Register Field Descriptions Type R/W Reset 0h Description Source Address End Pointer. This field points to the last address of the DMA transfer source (inclusive). If the source address is not incrementing (the SRCINC field in the DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). 110 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.3.2 DMA_DSTENDP Register (offset = 4h) [reset = 0h] DMA_DSTENDP is shown in Figure 4-6 and described in Table 4-7. Register Description Figure 4-6. DMA_DSTENDP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field ADDR Table 4-7. DMA_DSTENDP Register Field Descriptions Type R/W Reset 0h Description Destination Address End Pointer. This field points to the last address of the DMA transfer destination (inclusive). If the destination address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 111 Register Description 4.3.3.3 DMA_CHCTL Register (offset = 8h) [reset = 0h] DMA_CHCTL is shown in Figure 4-7 and described in Table 4-8. 31 30 DSTINC R/W-0h Figure 4-7. DMA_CHCTL Register 29 28 27 26 DSTSIZE SRCINC R/W-0h R/W-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 ARBSIZE XFERSIZE R/W-0h R/W-0h 7 6 5 4 3 2 XFERSIZE NXTUSEBURS T R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset www.ti.com 25 24 SRCSIZE R/W-0h 17 16 ARBSIZE R/W-0h 9 8 1 0 XFERMODE R/W-0h Bit 31-30 Field DSTINC 29-28 DSTSIZE 27-26 SRCINC 25-24 SRCSIZE 23-18 RESERVED Table 4-8. DMA_CHCTL Register Field Descriptions Type R/W R/W R/W R/W R Reset 0h 0h 0h 0h 0h Description Destination Address Increment. This field configures the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE) 0h = Increment by 8-bit location 1h = Half word Increment by 16-bit location 2h = Word Increment by 32-bit location 3h = No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel Destination Data Size. This field configures the destination item data size. Note: DSTSIZE must be the same as SRCSIZE 0h = Increment by 8-bit location 1h = Half word Increment by 16-bit location 2h = Word Increment by 32-bit location 3h = No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel Source Address Increment. This field configures the destination address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE) 0h = Increment by 8-bit location 1h = Half word Increment by 16-bit location 2h = Word Increment by 32-bit location 3h = No increment Address remains set to the value of the source Address End Pointer (DMADSTENDP) for the channel Source Data Size. This field configures the source item data size. Note: DSTSIZE must be the same as SRCSIZE 0h = Increment by 8-bit location 1h = Half word Increment by 16-bit location 2h = Word Increment by 32-bit location 3h = No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 112 Direct Memory Access (DMA) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description Bit 17-14 13-4 3 2-0 Table 4-8. DMA_CHCTL Register Field Descriptions (continued) Field ARBSIZE XFERSIZE NXTUSEBURST XFERMODE Type R/W R/W R/W R/W Reset 0h 0h 0h 0h Description This field configures the number of transfers that can occur before the DMA controller re-arbitrates. The possible arbitration rate configurations represent powers of 2 and are shown below. 0xA-0xF = 1024 transfer 0h = 1 transfer 1h = 2 transfer 2h = 4 transfer 3h = 8 transfer 4h = 16 transfer 5h = 32 transfer 6h = 64 transfer 7h = 128 transfer 8h = 256 transfer Transfer Size (minus 1). This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The DMA controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the DMA cycle Next Useburst. This field controls whether the Useburst SET[n] bit is automatically set for the last transfer of a peripheral scatter gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the DMA controller uses single transfers to complete the transaction. If this bit is set, then the controller uses a burst transfer to complete the last transfer. DMA Transfer Mode. This field configures the operating mode of the DMA cycle. Because this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. 0h = Stop 1h = Basic 2h = Auto-request 3h = Ping-pong 4h = Memory Scatter-Gather 5h = Alternate memory scatter gather 6h = Peripheral scatter gather 7h = Alternate peripheral scatter gather SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Direct Memory Access (DMA) 113 Chapter 5 SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) Topic ........................................................................................................................... Page 5.1 Overview ......................................................................................................... 115 5.2 Functional Description ...................................................................................... 115 5.3 Interrupt Control............................................................................................... 117 5.4 Initialization and Configuration .......................................................................... 117 5.5 GPIO_REGISTER_MAP Registers ....................................................................... 119 114 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 5.1 Overview This chapter describes the general purpose input output module and the IO pad cells in CC3200. The GPIO module is composed of 4 physical GPIO blocks, each corresponding to an individual GPIO port (Port 0, Port A1, Port A2, Port A3). The GPIO module supports up to 32 programmable input/output pins when GPIO function is selected in IO pin muxing. The GPIO module has the following features: • Up to 26 GPIOs depending on pin mux configuration: – Excluding the two SWD pins (TMS, TCK) and the two pins dedicated for antenna switch control (diversity selection). 2-wire debug corresponds to the SOP Mode (Sense On Power). – If 4-wire JTAG mode is used instead (by pulling the Sense On Power pin 2:0 to “000” using board level pull-down resistors) – then the number of digital IOs excluding JTAG and antenna diversity controls is 24. • Programmable control for GPIO interrupts: – Interrupt generation masking. – Edge-triggered on rising, falling, or both. – Level-sensitive on High or Low values. 5.2 Functional Description Each GPIO port is a separate hardware instantiation of the same physical block. The CC3200 microcontroller contains four ports and thus four of these physical GPIO blocks. Each GPIO block has 8 bits. The available GPIOs are a subset of these 32 GPIO signals. For details on the usable GPIOs, refer to Table 16-6. Figure 5-1. Digital I/O Pads SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 115 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com 5.2.1 Data Control The data direction register GPIODIR configures the GPIO as an input or an output while the data register GPIODATA either captures incoming data or drives it out to the pads. 5.2.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. 5.2.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register by using bits [9:2] of the address bus as a mask. In this manner, software drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins. This method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set, the value of the GPIODATA Register is altered. If the address bit is cleared, the data bit is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in Figure 5-2, where u indicates that data is unchanged by the write. This example demonstrates how GPIODATA bits 5, 2, and 1 are written with a single operation by using GPIODATA address alias 0x098 (offset address with regards to the base of the respective GPIO instance A0 to A4). Figure 5-2. GPIODATA Write Example During a read, if the address bit associated with the data bit is set, the value is read. If the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 5-3. This example shows how to read GPIODATA bits 5, 4, and 0 with a single operation by using GPIODATA address alias 0x0C4 (offset address with regard to the base of the respective GPIO instance S0 to S4). Figure 5-3. GPIODATA Read Example 116 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupt Control 5.3 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers (refer to the register map). These registers are used to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. Three registers define the edge or sense that causes interrupts: • GPIO Interrupt Sense (GPIOIS) register. • GPIO Interrupt Both Edges (GPIOIBE) register. • GPIO Interrupt Event (GPIOIEV) register. Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register. When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers. As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until serviced. Once the input signal de-asserts from the interrupt generating logical sense, the corresponding RIS bit in the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS bit in the GPIORIS register is cleared by writing a ‘1’ to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. The corresponding GPIOMIS bit reflects the masked value of the RIS bit. When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled. 5.3.1 μDMA Trigger Source Any GPIO pin can be configured to be an external trigger for the μDMA using the apps gpio trigger enable (APPS_GPIO_TRIG_EN) register. If the μDMA is configured to start a transfer based on the GPIO signal, a transfer is initiated 5.4 Initialization and Configuration Follow these steps to configure the GPIO pins of a particular port: 1. Enable the clock to the port by setting the appropriate bits in the GPIO0CLKEN, GPIO1CLKEN, GPIO2CLKEN, GPIO3CLKEN, GPIO4CLKEN register. 2. Set the direction of the GPIO port pins by programming the GPIODIR register. A write of a 1 indicates output and a write of a 0 indicates input. 3. Configure the GPIO_PAD_CONFIG_# register to program each bit as a GPIO or other peripheral functions. The GPIODMACTL register can be used to program a GPIO pin as μDMA trigger. 4. 4. Program the GPIOIS, GPIOIBE, GPIOEV, and GPIOIM registers to configure the type, event, and mask of the interrupts for each port. Note: To prevent false interrupts, the following steps should be taken when re-configuring GPIO edge and interrupt sense registers: (a) Mask the corresponding port by clearing the IME field in the GPIOIM register. (b) Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE register. (c) Clear the GPIORIS register. (d) Unmask the port by setting the IME field in the GPIOIM register. Table 5-1. GPIO Pad Configuration Examples Configuration Digital Input (GPIO) Digital Output (GPIO) GPIO Register Bit Value DIR 0 1 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Input/Outputs (GPIOs) 117 Initialization and Configuration www.ti.com Use DATA register to drive required value on GPIO pin (When DIR = 1) or to read value on GPIO pin (when DIR = 0). Register GPIOIS GPIOIBE GPIOIEV GPIOIM Table 5-2. GPIO Interrupt Configuration Example Desired Interrupt Event Trigger 7 6 5 0=edge 1=level X X X 0=single edge 1=both edges X X X 0=Low level, or falling edge 1=High level, or rising X X X edge 0=masked 1=not masked 0 0 0 Pin 2 Bit Value 4 3 2 X X 0 X X 0 X X 1 0 0 1 1 0 X X X X X X 0 0 118 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5 GPIO_REGISTER_MAP Registers Table 5-3 lists the memory-mapped registers for the GPIO_REGISTER_MAP. Each GPIO port can be accessed through Advanced Peripheral Bus (APB). The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base address: • GPIO Port A0: 0x4000.4000 • GPIO Port A1: 0x4000.5000 • GPIO Port A2: 0x4000.6000 • GPIO Port A3: 0x4000.7000 Note that each GPIO module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Offset 0h 400h 404h 408h 40Ch 410h 414h 418h 41Ch Acronym GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Table 5-3. GPIO_REGISTER_MAP Registers Register Name GPIO Data GPIO Direction GPIO Interrupt Sense GPIO Interrupt Both Edges GPIO Interrupt Event GPIO Interrupt Mask GPIO Raw Interrupt Status GPIO Masked Interrupt Status GPIO Interrupt Clear Section Section 5.5.1.1 Section 5.5.1.2 Section 5.5.1.3 Section 5.5.1.4 Section 5.5.1.5 Section 5.5.1.6 Section 5.5.1.7 Section 5.5.1.8 Section 5.5.1.9 5.5.1 GPIO Register Description The remainder of this section lists and describes the GPIO registers. SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 119 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated GPIO_REGISTER_MAP Registers www.ti.com 5.5.1.1 GPIODATA Register (offset = 0h) [reset = 0h] GPIODATA is shown in Figure 5-4 and described in Table 5-4. The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register GPIODATA register has 256 aliased addresses from offset 0x000 to 0x3FF. A different address alias is used to directly read/write any combination of the 8 signal bits. This feature can be used to avoid time consuming read-modify-writes and bit-masking operation for read in software. In this scheme, in order to write to GPIODATA, the corresponding bits in the mask, represented by the address bus bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the alias address used to access the data register, bits [9:2]. Bits that are set in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. Figure 5-4. GPIODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R-0h R/W-0h Bit 31-8 Field RESERVED 7-0 DATA Table 5-4. GPIODATA Register Field Descriptions Type R R/W Reset 0h 0h Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. 120 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5.1.2 GPIODIR Register (offset = 400h) [reset = 0h] GPIODIR is shown in Figure 5-5 and described in Table 5-5. The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. Figure 5-5. GPIODIR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DIR R-0h R/W-0h Bit 31-8 7-0 Field RESERVED DIR Table 5-5. GPIODIR Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO Data Direction 0h = Corresponding pin is an input. 1h = Corresponding pins is an output. SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 121 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated GPIO_REGISTER_MAP Registers www.ti.com 5.5.1.3 GPIOIS Register (offset = 404h) [reset = 0h] GPIOIS is shown in Figure 5-6 and described in Table 5-6. The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. Note: To prevent false interrupts, the following steps should be taken when re-configuring GPIO edge and interrupt sense registers:Mask the corresponding port by clearing the IME field in the GPIOIM register.Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE register.Clear the GPIORIS register.Unmask the port by setting the IME field in the GPIOIM register. Figure 5-6. GPIOIS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IS R-0h R/W-0h Bit 31-8 7-0 Field RESERVED IS Table 5-6. GPIOIS Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO Interrupt Sense 0h = The edge on the corresponding pin is detected (edgesensitive). 1h = The level on the corresponding pin is detected (level-sensitive). 122 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5.1.4 GPIOIBE Register (offset = 408h) [reset = 0h] GPIOIBE is shown in Figure 5-7 and described in Table 5-7. The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register is set to detect edges, setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register. Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset. Note: To prevent false interrupts, the following steps should be taken when re-configuring GPIO edge and interrupt sense registers:Mask the corresponding port by clearing the IME field in the GPIOIM register.Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE register.Clear the GPIORIS register.Unmask the port by setting the IME field in the GPIOIM register. Figure 5-7. GPIOIBE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IBE R-0h R/W-0h Bit 31-8 7-0 Field RESERVED IBE Table 5-7. GPIOIBE Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO Interrupt Both Edges 0h = Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register. 1h = Both edges on the corresponding pin trigger an interrupt. SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 123 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated GPIO_REGISTER_MAP Registers www.ti.com 5.5.1.5 GPIOIEV Register (offset = 40Ch) [reset = 0h] GPIOIEV is shown in Figure 5-8 and described in Table 5-8. The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register. Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset. Figure 5-8. GPIOIEV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IEV R-0h R/W-0h Bit 31-8 7-0 Field RESERVED IEV Table 5-8. GPIOIEV Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO Interrupt Event 0h = A falling edge or a Low level on the corresponding pin triggers an interrupt. 1h = A rising edge or a High level on the corresponding pin triggers an interrupt. 124 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5.1.6 GPIOIM Register (offset = 410h) [reset = 0h] GPIOIM is shown in Figure 5-9 and described in Table 5-9. The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. Figure 5-9. GPIOIM Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IME R-0h R/W-0h Bit 31-8 7-0 Field RESERVED IME Table 5-9. GPIOIM Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO Interrupt Mask Enable 0h = The interrupt from the corresponding pin is masked. 1h = The interrupt from the corresponding pin is sent to the interrupt controller. SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 125 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated GPIO_REGISTER_MAP Registers www.ti.com 5.5.1.7 GPIORIS Register (offset = 414h) [reset = 0h] GPIORIS is shown in Figure 5-10 and described in Table 5-10. The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until serviced. Once the input signal de-asserts from the interrupt generating logical sense, the corresponding RIS bit in the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS bit in the GPIORIS register is cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. The corresponding GPIOMIS bit reflects the masked value of the RIS bit. Figure 5-10. GPIORIS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RIS R-0h R-0h Bit 31-8 7-0 Field RESERVED RIS Table 5-10. GPIORIS Register Field Descriptions Type R R Reset 0h 0h Description GPIO Interrupt Raw Status For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. For a GPIO level-detect interrupt, the bit is cleared when the level is deasserted. 0h = An interrupt condition has not occurred on the corresponding pin. 1h = An interrupt condition has occurred on the corresponding pin. 126 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5.1.8 GPIOMIS Register (offset = 418h) [reset = 0h] GPIOMIS is shown in Figure 5-11 and described in Table 5-11. The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking. Figure 5-11. GPIOMIS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MIS R-0h R-0h Bit 31-8 7-0 Field RESERVED MIS Table 5-11. GPIOMIS Register Field Descriptions Type R R Reset 0h 0h Description GPIO Masked Interrupt Status 0h = An interrupt condition on the corresponding pin is masked or has not occurred. 1h = An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. For a GPIO level-detect interrupt, the bit is cleared when the level is deasserted. SWRU367B – June 2014 – Revised October 2014 General-Purpose Input/Outputs (GPIOs) 127 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated GPIO_REGISTER_MAP Registers www.ti.com 5.5.1.9 GPIOICR Register (offset = 41Ch) [reset = 0h] GPIOICR is shown in Figure 5-12 and described in Table 5-12. The GPIOICR register is the interrupt clear register. For edge-detect interrupts, writing a 1 to the IC bit in the GPIOICR register clears the corresponding bit in the GPIORIS and GPIOMIS registers. If the interrupt is a level-detect, the IC bit in this register has no effect. In addition, writing a 0 to any of the bits in the GPIOICR register has no effect. Figure 5-12. GPIOICR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IC R-0h W1C-0h Bit 31-8 7-0 Field RESERVED IC Table 5-12. GPIOICR Register Field Descriptions Type R W1C Reset 0h 0h Description GPIO Interrupt Clear 0h = The corresponding interrupt is unaffected. 1h = The corresponding interrupt is cleared. 128 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com GPIO_REGISTER_MAP Registers 5.5.1.10 GPIO_TRIG_EN Register Register Outside GPIO Module : GPIO Trigger Enable (GPIO_TRIG_EN): This register is used to configure a GPIO pin as a source for the DMA trigger. Setting a bit in the GPIO_TRIG_EN register allows to trigger DMA upon any pin toggle correspond that GPIO module. Physical Address: 0x400F 70C8. Bit 31-4 3-0 Field RESERVED TRIG Table 5-13. GPIO_TRIG_EN Register Field Descriptions Type R R/W Reset 0h 0h Description GPIO DMA Trigger Enable. Bit 0: when '1' enable GPIO 0 trigger. This bit enables trigger for all GPIO 0 pins (GPIO 0 to GPIO7). Bit 1: when '1' enable GPIO 1 trigger. This bit enables trigger for all GPIO 1 pins ( GPIO8 to GPIO15). Bit 2: when '1' enable GPIO 2 trigger. This bit enables trigger for all GPIO 2 pins (GPIO16 to GPIO23). Bit 3: when '1' enable GPIO 3 trigger. This bit enables trigger for all GPIO 3 pins (GPIO24 to GPIO31). GPIO Module Instance GPIOA0 GPIOA0 GPIOA0 GPIOA0 GPIOA0 GPIOA0 GPIOA0 GPIOA0 GPIOA1 GPIOA1 GPIOA1 GPIOA1 GPIOA1 GPIOA1 GPIOA1 GPIOA1 GPIOA2 GPIOA2 GPIOA2 GPIOA2 GPIOA2 GPIOA2 GPIOA2 GPIOA2 GPIOA3 GPIOA3 GPIOA3 GPIOA3 GPIOA3 GPIOA3 Table 5-14. GPIO Mapping GPIO Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 GPIO # GPIO_00 (PM/Dig Mux) GPIO_01 GPIO_02 (Dig/ADC Mux) GPIO_03 (Dig/ADC Mux) GPIO_04 (Dig/ADC Mux) GPIO_05 (Dig/ADC Mux) GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 (Reserved) GPIO_19 (Reserved) GPIO_20 (Reserved) GPIO_21 (Reserved) GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 (Restricted Use; Antenna Selection 1 Only) GPIO_27 (Restricted Use; Antenna Selection 2 Only) GPIO_28 GPIO_29 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Input/Outputs (GPIOs) 129 GPIO_REGISTER_MAP Registers GPIO Module Instance GPIOA3 GPIOA3 Table 5-14. GPIO Mapping (continued) GPIO Bit 6 7 www.ti.com GPIO # GPIO_30 (PM/Dig Mux) GPIO_31 (PM/Dig Mux) 130 General-Purpose Input/Outputs (GPIOs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 6 SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) Topic ........................................................................................................................... Page 6.1 Overview ......................................................................................................... 132 6.2 Functional Description ...................................................................................... 133 6.3 Register Description ......................................................................................... 138 SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 131 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Overview www.ti.com 6.1 Overview The CC3200 includes two Universal Asynchronous Receiver/Transmitter (UART) with the following features: • Programmable baud-rate generator allowing speeds up to 3 Mbps. • Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading • Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface • FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 • Standard asynchronous communication bits for start, stop, and parity • Line-break generation and detection • Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation • RTS and CTS hardware flow support • Standard FIFO-level and End-of-Transmission interrupts • Efficient transfers using Micro Direct Memory Access Controller (μDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level • System clock is used to generate baud clock. 132 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.1.1 Block Diagram Overview Figure 6-1. UART Module Block Diagram 6.2 Functional Description Each CC3200 UART performs the functions of parallel-to-serial and serial-to-parallel conversions. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. 6.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 6-2 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 133 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Figure 6-2. UART Character Frame 6.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register . The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). By default, this is the main system clock described in “Clock Control” in Section 15.3.5. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: • UARTI BRD write, UARTF BRD write, and UARTLCRH write • UARTF BRD write, UARTI BRD write, and UARTLCRH write • UARTI BRD write and UARTLCRH write • UARTF BRD write and UARTLCRH write 6.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL. 134 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word. 6.2.3.1 Flow Control Flow control can be accomplished by either hardware or software. The following sections describe the different methods. 6.2.3.1.1 Hardware Flow Control (RTS/CTS) Hardware flow control between two devices is accomplished by connecting the U1RTS output to the Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving device to the U1RTS input. The U1RTS input controls the transmitter. The transmitter may only transmit data when the U1RTS input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has no space to store additional characters. The UARTCTL register bits 15 ( CTSEN) and 14 ( RTSEN) specify the flow control mode as shown in Table 6-1. CTSEN 1 1 0 0 Table 6-1. Flow Control Mode RTSEN 1 0 1 0 Description RTS and CTS flow control enabled Only CTS flow control enabled Only RTS Flow Control enabled Both RTS and CTS flow control disabled Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL register Request to Send ( RTS) bit, and the status of the RTS bit should be ignored. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts) Software flow control between two devices is accomplished by using interrupts to indicate the status of the UART. Interrupts may be generated for the U1CTS , and U1RI signals using bit 1 of the UARTIM register, respectively. The raw and masked interrupt status may be checked using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR register. 6.2.3.2 FIFO Operation The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register. Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 135 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com FIFO status can be monitored via the UART Flag (UARTFR) register and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and full flags are set according to the status of the 1-byte-deep holding registers. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register. Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include ⅛,¼, ½, ¾, and ⅞. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 6.2.3.3 Interrupts The UART can generate interrupts when the following conditions are observed: • Overrun Error • Break Error • Parity Error • Framing Error • Receive Timeout • Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer) • Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register. The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register. Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the corresponding bit in the UART Interrupt Clear (UARTICR) register. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period when the HSE bit is clear or over a 64-bit period when the HSE bit is set. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. The receive interrupt changes state when one of the following events occurs: • If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit. • If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit. The transmit interrupt changes state when one of the following events occurs: • If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore the FIFOmust be written past the programmed trigger level otherwise no further transmit interrupts will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit. • If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit. 136 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 6.2.3.4 LoopbackOperation The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the LBE bit in the UARTCTL register. In loopback mode, data transmitted on the UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is enabled. 6.2.3.5 DMA Operation The UART provides an interface to the μDMA controller with separate channels for transmit and receive. The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level configured in the UARTIFLS register. For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA controller depending on how the DMA channel is configured. To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control (UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive error occurs, the DMA receive requests are automatically disabled. This error condition can be cleared by clearing the appropriate UART error interrupt. If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion interrupt. 6.2.4 Initialization and Configuration To enable and initialize the UART, the following steps are necessary: 1. Enable the UART module using the UART0CLKEN/UART1CLKEN register. 2. Set the GPIO_PAD_CONFIG CONFMODE bits for the appropriate pins. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 80 MHz, and the desired UART configuration is: • 115200 baud rate • Data length of 8 bits • One stop bit • No parity • FIFOs disabled • No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), because the UARTI BRD and UARTF BRD registers must be written before the UARTLCRH register. Using the equation described in Section 6.2.2, the BRD can be calculated: BRD = 80,000,000 / (16 * 115,200) = 43.410590 which means that the DIVINT field of the UARTIBRD register should be set to 43 decimal or 0x2B. The value to be loaded into the UARTFBRD register is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.410590 * 64 + 0.5) = 26 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 137 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Optionally, configure the μDMA channel and enable the DMA options in the UARTDMACTL register. 6. Enable the UART by setting the UARTEN bit in the UARTCTL register. 6.3 Register Description Table 6-2 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: • UART0: 0x4000.C000 • UART1: 0x4000.D000 The UART module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. The UART must be disabled before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Offset 0x000 0x004 0x018 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 Table 6-2. UART Register Map Name UARTDR UARTRSR/UARTECR Type R/W R/W Reset 0x0000.0000 0x0000.0000 UARTFR RO UARTILPR R/W UARTIBRD R/W 0x0000.0090 0x0000.0000 0x0000.0000 UARTFBRD R/W 0x0000.0000 UARTLCRH R/W UARTCTL R/W UARTIFLS R/W 0x0000.0000 0x0000.0300 0x0000.0012 UARTIM R/W UARTRIS RO 0x0000.0000 0x0000.0000 UARTMIS RO 0x0000.0000 UARTICR UARTDMACTL W1C R/W 0x0000.0000 0x0000.0000 Description UART Data UART Receive Status/Error Clear UART Flag Reserved UART Integer BaudRate Divisor UART Fractional BaudRate Divisor UART Line Control UART Control UART Interrupt FIFO Level Select UART Interrupt Mask UART Raw Interrupt Status UART Masked Interrupt Status UART Interrupt Clear UART DMA Control 138 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1 UART Registers Table 6-3 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 6-3 should be considered as reserved locations and the register contents should not be modified. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: UART0: 0x4000.C000 UART1: 0x4000.D000 The UART module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. The UART must be disabled (see the UARTEN bit in the UARTCTL register) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Offset 0h 4h 18h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h Acronym UARTDR UARTRSR_UARTECR UARTFR UARTIBRD UARTFBRD UARTLCRH UARTCTL UARTIFLS UARTIM UARTRIS UARTMIS UARTICR UARTDMACTL Table 6-3. UART REGISTERS Register Name UART Data UART Receive Status/Error Clear UART Flag UART Integer Baud-Rate Divisor UART Fractional Baud-Rate Divisor UART Line Control UART Control UART Interrupt FIFO Level Select UART Interrupt Mask UART Raw Interrupt Status UART Masked Interrupt Status UART Interrupt Clear UART DMA Control Section Section 6.3.1.1 Section 6.3.1.2 Section 6.3.1.3 Section 6.3.1.4 Section 6.3.1.5 Section 6.3.1.6 Section 6.3.1.7 Section 6.3.1.8 Section 6.3.1.9 Section 6.3.1.10 Section 6.3.1.11 Section 6.3.1.12 Section 6.3.1.13 SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 139 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.1 UARTDR Register (offset = 0h) [reset = 0h] UARTDR is shown in Figure 6-3 and described in Table 6-4. NOTE: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. Figure 6-3. UARTDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OE BE PE FE DATA R-0h R-0h R-0h R-0h R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-12 11 Field RESERVED OE 10 BE 9 PE 8 FE 7-0 DATA Table 6-4. UARTDR Register Field Descriptions Type R R R R R R/W Reset 0h 0h 0h 0h 0h 0h Description UART Overrun Error 0h = No data has been lost due to a FIFO overrun. 1h = New data was received when the FIFO was full, resulting in data loss. UART Break Error 0h = No break condition has occurred 1h = A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received. UART Parity Error In FIFO mode, this error is associated with the character at the top of the FIFO. 0h = No parity error has occurred 1h = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. UART Framing Error 0h = No framing error has occurred 1h = The received character does not have a valid stop bit (a valid stop bit is 1). Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 140 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.2 UARTRSR_UARTECR Register (offset = 4h) [reset = 0h] UARTRSR_UARTECR is shown in Figure 6-4 and described in Table 6-5. The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared on reset. Figure 6-4. UARTRSR_UARTECR Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED OE_OR_DATA BE_OR_DATA PE_OR_DATA FE_OR_DATA R-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-5. UARTRSR_UARTECR Register Field Descriptions Bit Field 7-4 DATA 31-4 3 RESERVED OE_OR_DATA 2 BE_OR_DATA Type W R R/W R/W Reset 0h 0h 0h 0h Description Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. UART Overrun Error (R) or Error Clear (W) 0h (R) = No data has been lost due to a FIFO overrun. 1h (R) = New data was received when the FIFO was full, resulting in data loss. This bit is cleared by a write to UARTECR. The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. UART Break Error (R) or Error Clear (W) 0h (R) = No break condition has occurred 1h (R) = A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 141 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com Table 6-5. UARTRSR_UARTECR Register Field Descriptions (continued) Bit Field 1 PE_OR_DATA 0 FE_OR_DATA Type R/W R/W Reset 0h 0h Description UART Parity Error (R) or Error Clear (W) 0h (R) = No parity error has occurred 1h (R) = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. UART Framing Error (R) or Error Clear (W) 0h (R) = No framing error has occurred 1h (R) = The received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 142 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.3 UARTFR Register (offset = 18h) [reset = 90h] UARTFR is shown in Figure 6-5 and described in Table 6-6.The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. The RI and CTS bits indicate the modem flow control and status. Note that the modem bits are only implemented on UART1 and are reserved on UART0. Figure 6-5. UARTFR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 TXFE R-1h 6 RXFF R-0h 5 TXFF R-0h 4 EXFE R-1h 3 BUSY R-0h 2 DCD R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 DSR R-0h 24 16 8 RI R-0h 0 CTS R-0h Bit 31-9 8 7 Field RESERVED RI TXFE 6 RXFF 5 TXFF 4 EXFE Table 6-6. UARTFR Register Field Descriptions Type R R R R R R Reset 0h 0h 1h 0h 0h 1h Description Reserved UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 0h = The transmitter has data to transmit. 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 0h = The receiver can receive data. 1h = If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 0h = The transmitter is not full. 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 0h = The receiver is not empty. 1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 143 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description Bit Field 3 BUSY 2 DCD 1 DSR 0 CTS www.ti.com Table 6-6. UARTFR Register Field Descriptions (continued) Type R R R R Reset 0h 0h 0h 0h Description UART Busy 0h = The UART is not busy. 1h = The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). Reserved Reserved Clear To Send 0h = The U1CTS signal is not asserted. 1h = The U1CTS signal is asserted. This bit is implemented only on UART1 and is reserved for UART0 144 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.4 UARTIBRD Register (offset = 24h) [reset = 0h] The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. Bit 31-16 15-0 Field RESERVED DIVINT Table 6-7. UARTIBRD Register Field Descriptions Type R R/W Reset 0 0 Description Integer Baud-Rate Divisor SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 145 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.5 UARTFBRD Register (offset = 28h) [reset = 0h] UARTFBRD is shown in Figure 6-6 and described in Table 6-8. The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. Figure 6-6. UARTFBRD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DIVFRAC R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-6 5-0 Field RESERVED DIVFRAC Table 6-8. UARTFBRD Register Field Descriptions Type R R/W Reset 0h 0h Description Fractional Baud-Rate Divisor 146 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.6 UARTLCRH Register (offset = 2Ch) [reset = 0h] UARTLCRH is shown in Figure 6-7 and described in Table 6-9. The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. Figure 6-7. UARTLCRH Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 SPS R/W-0h 6 5 WLEN R/W-0h 4 FEN R/W-0h 3 STP2 R/W-0h 2 EPS R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 PEN R/W-0h 24 16 8 0 BRK R/W-0h Bit 31-8 7 Field RESERVED SPS 6-5 WLEN 4 FEN 3 STP2 Table 6-9. UARTLCRH Register Field Descriptions Type R R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h Description UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0h = 5 bits (default) 1h = 6 bits 2h = 7 bits 3h = 8 bits UART Enable FIFOs 0h = The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 1h = The transmit and receive FIFO buffers are enabled (FIFO mode). UART Two Stop Bits Select 0h = One stop bit is transmitted at the end of a frame. 1h = Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 147 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description Bit Field 2 EPS 1 PEN 0 BRK www.ti.com Table 6-9. UARTLCRH Register Field Descriptions (continued) Type R/W R/W R/W Reset 0h 0h 0h Description UART Even Parity Select 0h = Odd parity is performed, which checks for an odd number of 1s. 1h = Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. This bit has no effect when parity is disabled by the PEN bit. UART Parity Enable 0h = Parity is disabled and no parity bit is added to the data frame. 1h = Parity checking and generation is enabled. UART Parity Enable 0h = Parity is disabled and no parity bit is added to the data frame. 1h = Parity checking and generation is enabled. 148 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.7 UARTCTL Register (offset = 30h) [reset = 300h] UARTCTL is shown in Figure 6-8 and described in Table 6-10. The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. NOTE: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. Figure 6-8. UARTCTL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 CTSEN R/W-0h 14 RTSEN R/W-0h 13 12 RESERVED R-0h 11 RTS R/W-0h 10 DTR R/W-0h 7 LBE R/W-0h 6 RESERVED R-0h 5 HSE R/W-0h 4 EOT R/W-0h 3 RESERVED R-0h 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 RXE R/W-1h 1 SIREN R/W-0h 24 16 8 TXE R/W-1h 0 UARTEN R/W-0h Bit 31-16 15 Field RESERVED CTSEN 14 RTSEN 13-12 11 RESERVED RTS 10 DTR Table 6-10. UARTCTL Register Field Descriptions Type R R/W R/W R R/W R/W Reset 0h 0h 0h 0h 0h 0h Description Enable Clear To Send 0h = CTS hardware flow control is disabled. 1h = CTS hardware flow control is enabled. Data is only transmitted when the U1CTS signal is asserted. Enable Request to Send 0h = RTS hardware flow control is disabled. 1h = RTS hardware flow control is enabled. Data is only requested (by asserting U1RTS) when the receive FIFO has available entries. Request to Send When RTSEN is clear, the status of this bit is reflected on the U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read. Reserved SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 149 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com Table 6-10. UARTCTL Register Field Descriptions (continued) Bit Field 9 RXE 8 TXE 7 LBE 6 RESERVED 5 HSE 4 EOT 3 RESERVED 2 RESERVED 1 SIREN 0 UARTEN Type R/W R/W R/W R R/W R/W R R R/W R/W Reset 1h 1h 0h 0h 0h 0h 0h 0h 0h 0h Description UART Receive Enable 0h = The receive section of the UART is disabled. 1h = The receive section of the UART is enabled. If the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. UART Transmit Enable 0h = The transmit section of the UART is disabled. 1h = The transmit section of the UART is enabled. If the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. UART Loop Back Enable 0h = Normal operation. 1h = The UnTx path is fed through the UnRx path. High-Speed Enable 0h = The UART is clocked using the system clock divided by 16. 1h = The UART is clocked using the system clock divided by 8. Note: System clock used is also dependent on the baud-rate divisor configuration. The state of this bit has no effect on clock generation in ISO 7816 smart card mode (the SMART bit is set). End of Transmission This bit determines the behavior of the TXRIS bit in the UARTRIS register. 0h = The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met. 1h = The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer. RESERVED UART Enable 0h = The UART is disabled. 1h = The UART is enabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 150 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Description 6.3.1.8 UARTIFLS Register (offset = 34h) [reset = 12h] UARTIFLS is shown in Figure 6-9 and described in Table 6-11. The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. Figure 6-9. UARTIFLS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 RESERVED RXIFLSEL R-0h R/W-2h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 18 17 16 2 1 0 TXIFSEL R/W-2h Bit 31-6 5-3 Field RESERVED RXIFLSEL 2-0 TXIFSEL Table 6-11. UARTIFLS Register Field Descriptions Type R R/W R/W Reset 0h 2h 2h Description UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0h = Reserved 1h = RX FIFO full 2h = RX FIFO full (default) 3h = RX FIFO full 4h = RX FIFO full UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0h = Reserved 1h = TX FIFO empty 2h = TX FIFO empty (default) 3h = TX FIFO empty 4h = TX FIFO empty Note: If the EOT bit in UARTCTL is set, the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored. SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 151 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.9 UARTIM Register (offset = 38h) [reset = 0h] UARTIM is shown in Figure 6-10 and described in Table 6-12. The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. Figure 6-10. UARTIM Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 RESERVED R-0h 12 9BITIM R/W-0h 11 EOTIM R/W-0h 10 OEIM R/W-0h 7 FEIM R/W-0h 6 RTIM R/W-0h 5 TXIM R/W-0h 4 RXIM R/W-0h 3 DSRIM R/W-0h 2 DCDIM R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 DMATXIM R/W-0h 9 BEIM R/W-0h 1 CTSIM R/W-0h 16 DMARXIM R/W-0h 8 PEIM R/W-0h 0 RIIM R/W-0h Bit 31-18 17 Field RESERVED DMATXIM 16 DMARXIM 15-13 12 11 RESERVED 9BITIM EOTIM 10 OEIM 9 BEIM Table 6-12. UARTIM Register Field Descriptions Type R R/W R/W R R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Transmit DMA Interrupt Mask 0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the DMATXRIS bit in the UARTRIS register is set. Receive DMA Interrupt Mask 0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the DMARXRIS bit in the UARTRIS register is set. Reserved End of Transmission Interrupt Mask 0h = The EOTRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the EOTRIS bit in the UARTRIS register is set. UART Overrun Error Interrupt Mask 0h = The OERIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. UART Break Error Interrupt Mask 0h = The BERIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 152 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 8 PEIM 7 FEIM 6 RTIM 5 TXIM 4 RXIM 3 DSRIM 2 DCDIM 1 CTSIM 0 RIIM Register Description Table 6-12. UARTIM Register Field Descriptions (continued) Type R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description UART Parity Error Interrupt Mask 0h = The PERIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. UART Framing Error Interrupt Mask 0h = The FERIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. UART Receive Time-Out Interrupt Mask 0h = The RTRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. UART Transmit Interrupt Mask 0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. UART Receive Interrupt Mask 0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. Reserved Reserved UART Clear to Send Modem Interrupt Mask 0h = The CTSRIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set. Reserved SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 153 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.10 UARTRIS Register (offset = 3Ch) [reset = 0h] UARTRIS is shown in Figure 6-11 and described in Table 6-13. The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. Figure 6-11. UARTRIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RESERVED EOTRIS OERIS R-0h R-0h R-0h R-0h 7 FERIS R-0h 6 RTRIS R-0h 5 TXRIS R-0h 4 RXRIS R-0h 3 DSRRIS R-0h 2 DCDRIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 DMATXRIS R-0h 9 BERIS R-0h 1 CTSRIS R-0h 16 DMARXRIS R-0h 8 PERIS R-0h 0 RIRIS R-0h Bit 31-18 17 Field RESERVED DMATXRIS 16 DMARXRIS 15-13 12 11 RESERVED RESERVED EOTRIS 10 OERIS 9 BERIS Table 6-13. UARTRIS Register Field Descriptions Type R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Transmit DMA Raw Interrupt Status 0h = No interrupt 1h = The transmit DMA has completed. This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register. Receive DMA Raw Interrupt Status 0h = No interrupt 1h = The receive DMA has completed. This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register. End of Transmission Raw Interrupt Status 0h = No interrupt 1h = The last bit of all transmitted data and flags has left the serializer. This bit is cleared by writing a 1 to the EOTIC bit in the UARTICR register. UART Overrun Error Raw Interrupt Status 0h = No interrupt 1h = An overrun error has occurred. This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. UART Break Error Raw Interrupt Status 0h = No interrupt 1h = A break error has occurred. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 154 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 8 PERIS 7 FERIS 6 RTRIS 5 TXRIS 4 RXRIS 3 DSRRIS 2 DCDRIS 1 CTSRIS 0 RIRIS Register Description Table 6-13. UARTRIS Register Field Descriptions (continued) Type R R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description UART Parity Error Raw Interrupt Status 0h = No interrupt 1h = A parity error has occurred. This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. UART Framing Error Raw Interrupt Status 0h = No interrupt 1h = A framing error has occurred. This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. UART Receive Time-Out Raw Interrupt Status 0h = No interrupt 1h = A receive time out has occurred. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. UART Transmit Raw Interrupt Status 0h = No interrupt 1h = If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register. If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer. This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled. UART Receive Raw Interrupt Status Value Description 0 No interrupt 1 The receive FIFO level has passed through the condition defined in the UARTIFLS register. This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled. Reserved Reserved UART Clear to Send Modem Raw Interrupt Status 0h = No interrupt 1h = Clear to Send used for software flow control. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. Reserved SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 155 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.11 UARTMIS Register (offset = 40h) [reset = 0h] UARTMIS is shown in Figure 6-12 and described in Table 6-14. The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. Figure 6-12. UARTMIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RESERVED EOTMIS OEMIS R-0h R-0h R-0h R-0h 7 FEMIS R-0h 6 RTMIS R-0h 5 TXMIS R-0h 4 RXMIS R-0h 3 DSRMIS R-0h 2 DCDMIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 DMATXMIS R-0h 9 BEMIS R-0h 1 CTSMIS R-0h 16 DMARXMIS R-0h 8 PEMIS R-0h 0 RIMIS R-0h Bit 31-18 17 Field RESERVED DMATXMIS 16 DMARXMIS 15-13 12 11 RESERVED RESERVED EOTMIS 10 OEMIS 9 BEMIS Table 6-14. UARTMIS Register Field Descriptions Type R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Transmit DMA Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to the completion of the transmit DMA. This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register. Receive DMA Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to the completion of the receive DMA. This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register. End of Transmission Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to the transmission of the last data bit. This bit is cleared by writing a 1 to the EOTIC bit in the UARTICR register. UART Overrun Error Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to an overrun error. This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. UART Break Error Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to a break error. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 156 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 8 PEMIS 7 FEMIS 6 RTMIS 5 TXMIS 4 RXMIS 3 DSRMIS 2 DCDMIS 1 CTSMIS 0 RIMIS Register Description Table 6-14. UARTMIS Register Field Descriptions (continued) Type R R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description UART Parity Error Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to a parity error. This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. UART Framing Error Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to a framing error. This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. UART Receive Time-Out Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to a receive time out. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. UART Transmit Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set). This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled. UART Receive Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to passing through the specified receive FIFO level. This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled. Reserved Reserved UART Clear to Send Modem Masked Interrupt Status 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to Clear to Send. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. Reserved SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 157 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description www.ti.com 6.3.1.12 UARTICR Register (offset = 44h) [reset = 0h] UARTICR is shown in Figure 6-13 and described in Table 6-15. The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. Figure 6-13. UARTICR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RESERVED EOTIC OEIC R-0h R-0h W1C-0h W1C-0h 7 FEIC W1C-0h 6 RTIC W1C-0h 5 TXIC W1C-0h 4 RXIC W1C-0h 3 DSRMIC W1C-0h 2 DCDMIC W1C-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 DMATXIC W1C-0h 9 BEIC W1C-0h 1 CTSMIC W1C-0h 16 DMARXIC W1C-0h 8 PEIC W1C-0h 0 RIMIC W1C-0h Bit 31-18 17 Field RESERVED DMATXIC 16 DMARXIC 15-13 12 11 RESERVED RESERVED EOTIC 10 OEIC 9 BEIC 8 PEIC 7 FEIC 6 RTIC 5 TXIC Table 6-15. UARTICR Register Field Descriptions Type R W1C W1C R W1C W1C W1C W1C W1C W1C W1C W1C Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the UARTRIS register and the DMATXMIS bit in the UARTMIS register. Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the UARTRIS register and the DMARXMIS bit in the UARTMIS register. End of Transmission Interrupt Clear Writing a 1 to this bit clears the EOTRIS bit in the UARTRIS register and the EOTMIS bit in the UARTMIS register. Overrun Error Interrupt Clear Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the UARTMIS register. Break Error Interrupt Clear Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register. Parity Error Interrupt Clear Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register. Framing Error Interrupt Clear Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the UARTMIS register. Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register. Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register. 158 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 4 RXIC 3 DSRMIC 2 DCDMIC 1 CTSMIC 0 RIMIC Register Description Table 6-15. UARTICR Register Field Descriptions (continued) Type W1C W1C W1C W1C W1C Reset 0h 0h 0h 0h 0h Description Receive Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register. Reserved Reserved UART Clear to Send Modem Interrupt Clear Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register. Reserved SWRU367B – June 2014 – Revised October 2014 Universal Asynchronous Receivers/Transmitters (UARTs) 159 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Description 6.3.1.13 UARTDMACTL Register (offset = 48h) [reset = 0h] UARTDMACTL is shown in Figure 6-14 and described in Table 6-16. The UARTDMACTL register is the DMA control register. Figure 6-14. UARTDMACTL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED DMAERR R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 TXDMAE R/W-0h www.ti.com 24 16 8 0 RXDMAE R/W-0h Bit 31-3 2 Field RESERVED DMAERR 1 TXDMAE 0 RXDMAE Table 6-16. UARTDMACTL Register Field Descriptions Type R R/W R/W R/W Reset 0h 0h 0h 0h Description DMA on Error 0h = DMA receive requests are unaffected when a receive error occurs. 1h = DMA receive requests are automatically disabled when a receive error occurs. Transmit DMA Enable 0h = DMA for the receive FIFO is disabled. 1h = DMA for the receive FIFO is enabled. Receive DMA Enable 0h = DMA for the receive FIFO is disabled. 1h = DMA for the receive FIFO is enabled. 160 Universal Asynchronous Receivers/Transmitters (UARTs) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 7 SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface Topic ........................................................................................................................... Page 7.1 Overview ......................................................................................................... 162 7.2 Functional Description ...................................................................................... 164 7.3 Register Map.................................................................................................... 179 SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 161 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Overview www.ti.com 7.1 Overview The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (EEPROM), sensors, LCDs and so on. The 3200 chip includes one I2C module with the following features: • Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation • Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive • Supported transmission speeds: – Standard (100 Kbps) – Fast-mode (400 Kbps) • Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected • Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode • Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I2C 162 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.1.1 Block Diagram Overview Figure 7-1. I2C Block Diagram This section describes the details of the architecture of the peripheral and how it is structured. This information is the architecture and design details common to all of the operation modes. Information that is mode-specific to one of the supported modes can be put in the corresponding supported use case section. This section describes how the peripheral works. Block diagrams and other diagrams are included as needed. 7.1.2 Signal Description The following table lists the external signals of the I2C interface and describes the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the I2C signals. The CONFMODE bits in the GPIO_PAD_CONFIG register should be set to choose the I2C function. Set the I2CSDA and I2CSCL pins to open drain using the IODEN bits of the GPIO_PAD_CONFIG register. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 163 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description Pin Name Pin Number I2C1SCL I2C1SDA Pin 30 Pin Y Pin 29 Pin Q Pin R Table 7-1. I2C Signals (64QFN) www.ti.com Pin Mux / Pin Assignment Pin Type I/O Buffer Type OD Description I 2C module 1 clock. Note that this signal has an active pull-up. I/O OD I2C module 1 data 7.2 Functional Description CC3200 has one instance of I2C module comprised of both master and slave functions, identified by a unique address. A master-initiated communication generates the clock signal, SCL. For proper operation, the SDA and SCL pin must be configured as an open-drain signal. Both SDA and SCL signals must be connected to a positive supply voltage using a pull-up resistor. A typical I2C bus configuration is shown in Figure 7-2. The typical pull-ups needed for proper operation is approximately 2Kohms. See “Inter-Integrated Circuit (I2C) Interface” for I2C timing diagrams. • SCL SDA Rpullup Rpullup •• •• • • • I2C Bus I2CSCL I2CSDA Tiva™ Microcontroller SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface Figure 7-2. I2C Bus Configuration 7.2.1 I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on CC3200 microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in Section 7.2.1.1) is unrestricted, but each data byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, the receiver holds the clock line SCL Low and forces the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 7.2.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A Highto-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-toHigh transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition (see Figure 7-3). 164 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 7-3. START and STOP Conditions The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2C Master Data (I2CMDR) register. When the I2C module operates in Master receiver mode, the ACK bit is normally set causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. 7.2.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 7-4. After the START condition, a slave address is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). If the R/S bit is clear, the bit indicates a transmit operation (send), and if it is set, the bit indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/transmit formats are then possible within a single transfer. Figure 7-4. Complete Data Transfer with a 7-Bit Address The first seven bits of the first byte make up the slave address (see Figure 7-5). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. Figure 7-5. R/S Bit in First Byte 7.2.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 7-6). SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 165 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Figure 7-6. Data Validity During Bit Transfer on the I2C Bus 7.2.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the data validity requirements described in Section 7.2.1.3. When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. If the slave is required to provide a manual ACK or NACK, the I2C Slave ACK Control (I2CSACKCTL) register allows the slave to NACK for invalid data or command or ACK for valid data or command. When this operation is enabled, the MCU slave module I2C clock is pulled low after the last data bit until this register is written with the indicated response. 7.2.1.5 Repeated Start The I2C master module has the capability of executing a repeated START (transmit or receive) after an initial transfer has occurred. A repeated start sequence for a Master transmit is as follows: 1. When the device is in the idle state, the Master writes the slave address to the I2CMSA register and configures the R/S bit for the desired transfer type. 2. Data is written to the I2CMDR register. 3. When the BUSY bit in the I2CMCS register is '0' , the Master writes 0x3 to the I2CMCS register to initiate a transfer. 4. The Master does not generate a STOP condition but instead writes another slave address to the I2CMSA register and then writes 0x3 to initiate the repeated START. A repeated start sequence for a Master receive is similar: 1. When the device is in idle, the Master writes the slave address to the I2CMSA register and configures the R/S bit for the desired transfer type. 2. The master reads data from the I2CMDR register. 3. When the BUSY bit in the I2CMCS register is '0' , the Master writes 0x3 to the I2CMCS register to initiate a transfer. 4. The Master does not generate a STOP condition but instead writes another slave address to the I2CMSA register and then writes 0x3 to initiate the repeated START. 166 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 7.2.1.6 Clock Low Timeout (CLTO) The I2C slave can extend the transaction by pulling the clock low periodically to create a slow bit transfer rate. The I2C module has a 12-bit programmable counter that is used to track how long the clock has been held low. The upper 8 bits of the count value are software programmable through the I2C Master Clock Low Timeout Count (I2CMCLKOCNT) register. The lower four bits are not user visible and are 0x0. The CNTL value programmed in the I2CMCLKOCNT register must be greater than 0x01. The application can program the eight most significant bits of the counter to reflect the acceptable cumulative low period in transaction. The count is loaded at the START condition and counts down on each falling edge of the internal bus clock of the Master. The internal bus clock generated for this counter runs at the programmed I2C speed even if SCL is held low on the bus. Upon reaching terminal count, the master state machine forces ABORT on the bus by issuing a STOP condition at the instance of SCL and SDA release. For example, if an I2C module operates at 100 kHz speed, programming the I2CMCLKOCNT register to 0xDA translates the value 0xDA0 since the lower four bits are set to 0x0. This translates to a decimal value of 3488 clocks or a cumulative clock low period of 34.88 ms at 100 kHz. The CLKRIS bit in the I2C Master Raw Interrupt Status (I2CMRIS) register is set when the clock timeout period is reached, allowing the master to start corrective action to resolve the remote slave state. In addition, the CLKTO bit in the I2C Master Control/Status (I2CMCS) register is set; this bit is cleared when a STOP condition is sent or during the I2C master reset. The status of the raw SDA and SCL signals are readable by software through the SDA and SCL bits in the I2C Master Bus Monitor (I2CMBMON) register to help determine the state of the remote slave. In the event of a CLTO condition, application software must choose how it intends to attempt bus recovery. Most applications may attempt to manually toggle the I2C pins to force the slave to let go of the clock signal (a common solution is to attempt to force a STOP on the bus). If a CLTO is detected before the end of a burst transfer, and the bus is successfully recovered by the master, the master hardware attempts to finish the pending burst operation. Depending on the state of the slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where it can acknowledge the master (essentially, where it was before the bus hang), it continues where it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation and NAK the first data byte that the master sends or requests. Since the behavior of slaves cannot always be predicted, it is suggested that the application software always write the STOP bit in the I2C Master Configuration (I2CMCR) register during the CLTO interrupt service routine. This limits the amount of data the master attempts to send or receive upon bus recovery to a single byte, and after the single byte is on the wire, the master issues a STOP. An alternative solution is to have the application software reset the I2C peripheral before attempting to manually recover the bus. This solution allows the I2C master hardware to return to a known good (and idle) state before attempting to recover a stuck bus, and prevents any unwanted data from appearing on the wire. NOTE: The Master Clock Low Timeout counter counts for the entire time SCL is held Low continuously. If SCL is de-asserted at any point, the Master Clock Low Timeout Counter is reloaded with the value in the I2CMCLKOCNT register and begins counting down from this value. 7.2.1.7 Dual Address The I2C interface supports dual address capability for the slave. The additional programmable address is provided and can be matched if enabled. In legacy mode with dual address disabled, the I2C slave provides an ACK on the bus if the address matches the OAR field in the I2CSOAR register. In dual address mode, the I2C slave provides an ACK on the bus if either the OAR field in the I2CSOAR register or the OAR2 field in the I2CSOAR2 register is matched. The enable for dual address is programmable through the OAR2EN bit in the I2CSOAR2 register and there is no disable on the legacy address. The OAR2SEL bit in the I2CSCSR register indicates if the address that was ACKed is the alternate address or not. When this bit is clear, it indicates either legacy operation or no address match. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 167 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com 7.2.1.8 Arbitration A master may only start a transfer if the bus is idle. Two or more masters can generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA, while another master transmits a '0' (Low), switches off its data output stage and retires until the bus is idle again. Arbitration can take place over several bits. The first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. If arbitration is lost when the I2C master is initiating a BURST with the TX FIFO enabled, the application should execute the following steps to correctly handle the arbitration loss: 1. Flush and disable the TX FIFO 2. Clear and mask the TXFE interrupt by clearing the TXFEIM bit in the I2CMIMR register. Once the bus is IDLE, the TXFIFO can be filled and enabled, the TXFE bit can be unmasked and a new BURST transaction can be initiated. 7.2.2 Supported Speed Modes The I2C bus in CC3200 can run in Standard mode (100 kbps) or Fast mode (400 kbps). The selected mode should match the speed of the other I2C devices on the bus. 7.2.2.1 Standard and Fast Modes Standard, Fast modes are selected using a value in the I2C Master Timer Period (I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode and 400 kbps for Fast mode. The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2CMTPR register. This value is determined by replacing the known variables in the equation below and solving for TIMER_PRD. The I2C clock period is calculated as follows: SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD For example: CLK_PRD = 12.5 ns TIMER_PRD = 39 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/SCL_PERIOD = 100 Khz Table 7-2 gives examples of the timer periods that should be used to generate Standard and Fast mode SCL frequencies based on the fixed 80MHz system clock frequency. System clock 80 MHz Timer Period 0x27 Table 7-2. Timer Periods Standard Mode 100 Kbps Timer Period 0x09 Fast Mode 400 Kbps 168 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 7.2.3 Interrupts The I2C can generate interrupts when the following conditions are observed in the Master Module: • Master transaction completed (RIS bit) • Master arbitration lost (ARBLOSTRIS bit) • Master Address/Data NACK (NACKRIS bit) • Master bus timeout (CLKRIS bit) • Next byte request (RIS bit) • Stop condition on bus detected (STOPRIS bit) • Start condition on bus detected (STARTRIS bit) • RX DMA interrupt pending (DMARXRIS bit) • TX DMA interrupt pending (DMATXRIS bit) • Trigger value for FIFO has been reached and a TX FIFO request interrupt is pending (TXRIS bit) • Trigger value for FIFO has been reached and a RX FIFO request interrupt is pending (RXRIS bit) • Transmit FIFO is empty (TXFERIS bit) • Receive FIFO is full (RXFFRIS bit) Interrupts are generated when the following conditions are observed in the Slave Module: • Slave transaction received (DATARIS bit) • Slave transaction requested (DATARIS bit) • Slave next byte transfer request (DATARIS bit) • Stop condition on bus detected (STOPRIS bit) • Start condition on bus detected (STARTRIS bit) • RX DMA interrupt pending (DMARXRIS bit) • TX DMA interrupt pending (DMATXRIS bit) • Programmable trigger value for FIFO has been reached and a TX FIFO request interrupt is pending (TXRIS bit) • Programmable trigger value for FIFO has been reached and a RX FIFO request interrupt is pending (RXRIS bit) • Transmit FIFO is empty (TXFERIS bit) • Receive FIFO is full (RXFFRIS bit) The I2C master and I2C slave modules have separate interrupt registers. Interrupts can be masked by clearing the appropriate bit in the I2CMIMR or I2CSIMR register. Note that the RIS bit in the Master Raw Interrupt Status (I2CMRIS) register and the DATARIS bit in the Slave Raw Interrupt Status (I2CSRIS) register have multiple interrupt causes including a next byte transfer request interrupt. This interrupt is generated when both master and slave are requesting a receive or transmit transaction. 7.2.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting the LPBKbit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and are tied to the SDA and SCL signals of the slave module to allow internal testing of the device without having to go through I/O. 7.2.5 FIFO and µDMA Operation Both the master and the slave module have the capability to access two 8-byte FIFOs that can be used in conjunction with the µDMA for fast transfer of data. The transmit (TX) FIFO and receive (RX) FIFO can be independently assigned to either the I2C master or I2C slave. Thus, the following FIFO assignments are allowed: • The transmit and receive FIFOs can be assigned to the master • The transmit and receive FIFOs can be assigned to the slave SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 169 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com • The transmit FIFO can be assigned to the master, while the receive FIFO is assigned to the slave and vice versa. In most cases, both FIFOs will be assigned to either the master or the slave. The FIFO assignment is configured by programming the TXASGNMT and RXASGNMT bit in the I2C FIFO Control (I2CFIFOCTL) register. Each FIFO has a programmable threshold point which indicates when the FIFO service interrupt should be generated. Additionally, a FIFO receive full and transmit empty interrupt can be enabled in the Interrupt Mask (I2CxIMR) registers of both the master and slave. Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation. When a FIFO is not assigned to a master or a slave module, the FIFO interrupt and status signals to the module are forced to a state that indicates the FIFO is empty. For example, if the TX FIFO is assigned to the master module, the status signals to the slave transmit interface indicates that the FIFO is empty. NOTE: The FIFOs must be empty when reassigning the FIFOs for proper functionality 7.2.5.1 Master Module Burst Mode A BURST command is provided for the master module which allows a sequence of data transfers using the µDMA (or software, if desired) to handle the data in the FIFO. The BURST command is enabled by setting the BURST bit in the Master Control/Status (I2CMCS) register. The number of bytes transferred by a BURST request is programmed in the I2C Master Burst Length (I2CMBLEN) register and a copy of this value is automatically written to the I2C Master Burst Count (I2CMBCNT) register to be used as a down-counter during the BURST transfer. The bytes written to the I2C FIFO Data (I2CFIFODATA) register are transferred to the RX FIFO or TX FIFO depending on whether a transmit or receive is being executed. If data is NACKed during a BURST and the STOP bit is set in the I2CMCS register, the transfer terminates. If the STOP bit is not set, the software application must issue a repeated STOP or START when a NACK interrupt is asserted. In the case of a NACK, the I2CMBCNT register can be used to determine the amount of data that was transferred prior to the BURST termination. If the Address is NACKed during a transfer, then a STOP is issued. 7.2.5.1.1 Master Module µDMA Functionality When the Master Control/Status (I2CMCS) register is set to enable BURST and the master I2C µDMA channel is enabled in the DMA Channel Map Select n (DMACHMAPn) registers in the µDMA, the master control module will assert either the internal single µDMA request signal (dma_sreq) or multiple µDMA request signal (dma_req) to the µDMA. Note that there are separate dma_req and dma_sreq signals for transmit and receive. A single µDMA request (dma_sreq) will be asserted by the Master module when the Rx FIFO has at least one data byte present in the FIFO and/or when the Tx FIFO has at least one space available to fill. The dma_req (or Burst) signal will be asserted when Rx FIFO fill level is higher than trigger level and/or the Tx FIFO burst length remaining is less than 4 bytes and the FIFO fill level is less than trigger level. If a single transfer or BURST operation has completed, the µDMA sends a dma_done signal to the master module represented by the DMATX/DMARX interrupts in the I2CMIMR, I2CMRIS, I2CMMIS, and I2CMICR registers. If the µDMA I2C channel is disabled and software is used to handle the BURST command, software can read the FIFO Status (I2CFIFOSTAT) register and the Master Burst Count (I2CMBC) register to determine whether the FIFO needs servicing during the BURST transaction. A trigger value can be programmed in the I2CFIFOCTL register to allow for interrupts at various fill levels of the FIFOs. The NACK and ARBLOST bits in the interrupt status registers can be enabled to indicate no acknowledgment of data transfer or an arbitration loss on the bus. When the Master module is transmitting FIFO data, software can fill the Tx FIFO in advance of setting the BURST bit in the I2CMCS register. If the FIFO is empty when the µDMA is enabled for BURST mode, the dma_req and dma_sreq both assert (assuming the I2CMBLEN register is programmed to at least 4 bytes and the Tx FIFO fill level is less than the trigger set). If the I2CMBLEN register value is less than 4 and the Tx FIFO is not full but more than trigger level, only dma_sreq will assert. Single requests will be 170 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description generated as required to keep the FIFO full until the number of bytes specified in the I2CMBLEN register has been transferred to the FIFO (and the I2CMBCOUNT register reaches 0x0). At this point, no further requests are generated until the next BURST command is issued. If the µDMA is disabled, FIFOs will be serviced based on the interrupts active in the Master interrupt status registers, the FIFO trigger values shown in the I2CFIFOSTATUS register and completion of a BURST transfer. When the Master module is receiving FIFO data, the Rx FIFO is initially empty and no requests are asserted. If data is read from the slave and placed into the Rx FIFO, the dma_sreq signal to the µDMA is asserted to indicate there is data to be transferred. If the Rx FIFO contains at least 4 bytes, the dma_req signal is also asserted. The µDMA will continue to transfer data out of the Rx FIFO until it has reached the amount of bytes programmed in the I2CMBLEN register. NOTE: The TXFEIM interrupt mask bit in the I2CMIMR register should be clear (masking the TXFE interrupt) when the master is performing an RX Burst from the RXFIFO and should be unmasked before starting a TX FIFO transfers. 7.2.5.1.2 Slave Module The slave module also has the capability to use the µDMA in Rx and Tx FIFO data transfers. If the Tx FIFO is assigned to the slave module and the TXFIFO bit is set in the I2CSCSR register, the slave module will generate a single µDMA request, dma_sreq, if the master module requests the next byte transfer. If the FIFO fill level is less than the trigger level, a µDMA multiple transfer request, dma_req, will be asserted to continue data transfers from the µDMA. If the Rx FIFO is assigned to the slave module and the RXFIFO bit is set in the I2CSCSR register, then the slave module will generate a signal µDMA request, dma_sreq, if there is any data to be transferred. The dma_req signal will be asserted when the Rx FIFO has more data than the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register. NOTE: Best practice recommends that an application should not switch between the I2CSDR register and TX FIFO or vice versa for successive transactions. 7.2.6 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 7.2.6.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 171 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description Idle Write Slave Address to I2CMSA Write data to I2CMDR Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle Figure 7-7. Master Single TRANSMIT www.ti.com 172 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Idle Write Slave Address to I2CMSA Functional Description Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle Figure 7-8. Master Single RECEIVE SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 173 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Idle Write Slave Address to I2CMSA Write data to I2CMDR Sequence may be omitted in a Single Master system Read I2CMCS NO BUSY bit=0? Read I2CMCS NO BUSBSY bit=0? YES Write ---0-011 to I2CMCS YES NO ERROR bit=0? YES Write data to I2CMDR Write ---0-001 NO to I2CMCS Index=n? YES Write ---0-101 to I2CMCS NO ARBLST bit=1? YES Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle Figure 7-9. Master TRANSMIT of Multiple Data Bytes 174 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Functional Description Read I2CMCS NO BUSBSY bit=0? YES Write ---01011 to I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? Read data from I2CMDR Write ---01001 NO to I2CMCS Index=m-1? YES Write ---00101 to I2CMCS NO ARBLST bit=1? YES Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES NO ERROR bit=0? Error Service YES Read data from I2CMDR Idle Figure 7-10. Master RECEIVE of Multiple Data Bytes SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 175 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description Idle www.ti.com Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Repeated START condition is generated with changing data direction Idle Figure 7-11. Master RECEIVE with Repeated START after Master TRANSMIT 176 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Idle Functional Description Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle Figure 7-12. Master TRANSMIT with Repeated START after Master RECEIVE 7.2.6.2 I2C Slave Command Sequences The following figure presents the command sequence available for the I2C slave. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 177 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Idle Write OWN Slave Address to I2CSOAR Write ------ 1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Figure 7-13. Slave Command Sequence 7.2.7 Initialization and Configuration The following example shows how to configure the I2C module to transmit a single byte as a master. This assumes the system clock is 80 MHz. 1. Enable the I2C clock using the RCGCI2C register in the System Control module . 2. The CONFMODE bits in the GPIO_PAD_CONFIG register should be set to choose the I2C function. 3. Enable the I2CSCL pin for open-drain operation using the IODEN bits of GPIO_PAD_CONFIG register. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1; TPR = (80MHz/(2*(6+4)*100000))-1; TPR = 39 Write the I2CMTPR register with the value of 0x0000.0039. 6. Specify the slave address of the master and that the next operation is a Transmit by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 178 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 9. Wait until the transmission completes by polling the BUSBSY bit of the I2CMCS register until the bit has been cleared. 10. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged. 7.3 Register Map SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 179 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1 I2C Registers Table 7-3 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 73 should be considered as reserved locations and the register contents should not be modified. All addresses given are relative to the I2C base address: 0x4002.0000. Note that the I2C module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the I2C module clock is enabled before any I2C module registers are accessed. The hw_i2c.h file in the TivaWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare for E Series uses an offset between 0x000 and 0x018 with the slave base address. Offset 0h 4h 8h Ch 10h 14h 18h 1Ch 20h 24h 2Ch 30h 34h 800h 804h 808h 80Ch 810h 814h 818h 81Ch 820h F00h F04h F08h FC0h FC4h Acronym I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR I2CMCLKOCNT I2CMBMON I2CMBLEN I2CMBCNT I2CSOAR I2CSCSR I2CSDR I2CSIMR I2CSRIS I2CSMIS I2CSICR I2CSOAR2 I2CSACKCTL I2CFIFODATA I2CFIFOCTL I2CFIFOSTATUS I2CPP I2CPC Table 7-3. I2C REGISTERS Register Name I2C Master Slave Address I2C Master Control/Status I2C Master Data I2C Master Timer Period I2C Master Interrupt Mask I2C Master Control/Status I2C Master Masked Interrupt Status I2C Master Interrupt Clear I2C Master Configuration I2C Master Clock Low Timeout Count I2C Master Bus Monitor I2C Master Burst Length I2C Master Burst Count I2C Slave Own Address I2C Slave Control/Status I2C Slave Data I2C Slave Interrupt Mask I2C Slave Raw Interrupt Status I2C Slave Masked Interrupt Status I2C Slave Interrupt Clear I2C Slave Own Address 2 I2C Slave ACK Control I2C FIFO Data I2C FIFO Control I2C FIFO Status I2C Peripheral Properties I2C Peripheral Configuration Section Section 7.3.1.1 Section 7.3.1.2 Section 7.3.1.3 Section 7.3.1.4 Section 7.3.1.5 Section 7.3.1.6 Section 7.3.1.7 Section 7.3.1.8 Section 7.3.1.9 Section 7.3.1.10 Section 7.3.1.11 Section 7.3.1.12 Section 7.3.1.13 Section 7.3.1.14 Section 7.3.1.15 Section 7.3.1.16 Section 7.3.1.17 Section 7.3.1.18 Section 7.3.1.19 Section 7.3.1.20 Section 7.3.1.21 Section 7.3.1.22 Section 7.3.1.23 Section 7.3.1.24 Section 7.3.1.25 Section 7.3.1.26 Section 7.3.1.27 180 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.1 I2CMSA Register (offset = 0h) [reset = 0h] I2CMSA is shown in Figure 7-14 and described in Table 7-4. This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Transmit (Low). Figure 7-14. I2CMSA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SA R_S R-0h R/W-0h R/W0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-1 0 Field RESERVED SA R_S Table 7-4. I2CMSA Register Field Descriptions Type R R/W R/W Reset 0h 0h 0h Description I2C Slave Address This field specifies bits A6 through A0 of the slave address. Receive/Send 0h = Transmit 1h = Receive The R/S bit specifies if the next master operation is a Receive (High) or Transmit (Low). SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 181 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.2 I2CMCS Register (offset = 4h) [reset = 20h] I2CMCS is shown in Figure 7-15 and described in Table 7-5. www.ti.com Figure 7-15. I2CMCS Register 31 30 29 28 27 26 25 24 ACTDMARX ACTDMATX RESERVED R/W-0h R-0h R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 CLKTO R/W-0h 6 BUSBSY_OR_ BURST R/W-0h 5 IDLE_OR_QC MD R/W-1h 4 ARBLST_OR_ HS R/W-0h 3 DATACK_OR_ ACK R/W-0h 2 ADRACK_OR_ STOP R/W-0h 1 ERROR_OR_S TART R/W-0h 0 BUSY_OR_RU N R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 7-5. I2CMCS Register Field Descriptions Bit Field 31 ACTDMARX 30 ACTDMATX 29-8 7 RESERVED CLKTO Type R/W R R R/W 6 BUSBSY_OR_BURST R/W 5 IDLE_OR_QCMD R/W Reset 0h 0h 0h 0h 0h 1h Description DMA RX Active Status 0h (R) = DMA RX is not active 1h (R) = DMA RX is active DMA TX Active Status 0h (R) = DMA TX is not active 1h (R) = DMA TX is active. Clock Timeout Error This bit is cleared when the master sends a STOP condition or if the I2C master is reset. 0h (R) = No clock timeout error. 1h (R) = The clock timeout error has occurred. Bus Busy (R) or Burst Enable (W) Note that the BURST and RUN bits are mutually exclusive. The bit changes based on the START and STOP conditions. 0h (W) = Burst operation is disabled. 0h (R) = The I2C bus is idle. 1h (W) = The master is enabled to burst using the receive and transmit FIFOs. 1h (R) = The I2C bus is busy. I2C Idle (R) or Quick Command (W) To execute a quick command, the START, STOP and RUN bits also need to be set. After the quick command is issued, the master generates a STOP. 0h (W) = Bus transaction is not a quick command. 0h (R) = The I2C controller is not idle. 1h (W) = The bus transaction is a quick command. 1h (R) = The I2C controller is idle. 182 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-5. I2CMCS Register Field Descriptions (continued) Bit Field 4 ARBLST_OR_HS Type R/W 3 DATACK_OR_ACK R/W 2 ADRACK_OR_STOP R/W 1 ERROR_OR_START R/W 0 BUSY_OR_RUN R/W Reset 0h 0h 0h 0h 0h Description Arbitration Lost (R) or Reserved (High-Speed Enable Not Supported) (W) 0h (W) = The master operates in Standard or Fast mode as selected by using a value in the I2CMTPR register that results in an SCL frequency of 100 kbps for Standard mode or 400 kbps for Fast mode. 0h (R) = The I2C controller won arbitration. 1h (R) = The I2C controller lost arbitration. Acknowledge Data (R) or Data Acknowledge Enable (W) 0h (W) = The received data byte is not acknowledged automatically by the master. 0h (R) = The transmitted data was acknowledged 1h (W) = The received data byte is acknowledged automatically by the master. 1h (R) = The transmitted data was not acknowledged. Acknowledge Address (R) or Generate STOP (W) 0h (W) = The controller does not generate the STOP condition. 0h (R) = The transmitted address was acknowledged 1h (W) = The controller generates the STOP condition. 1h (R) = The transmitted address was not acknowledged. Error (R) or Generate START (W) The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0h (W) = The controller does not generate the START condition. 0h (R) = No error was detected on the last operation. 1h (W) = The controller generates the START or repeated START condition. 1h (R) = An error occurred on the last operation. I2C Busy (R) or I2C Master Enable (W) When the BUSY bit is set, the other status bits are not valid. Note that the BURST and RUN bits are mutually exclusive. 0h (W) = In standard mode, this encoding means the master is unable to transmit or receive data. In Burst mode, this bit is not used and must be set to 0. 0h (R) = The controller is idle. 1h (W) = The master is able to transmit or receive data. Note that this bit cannot be set in Burst mode. 1h (R) = The controller is busy. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 183 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.3 I2CMDR Register (offset = 8h) [reset = 0h] I2CMDR is shown in Figure 7-16 and described in Table 7-6. NOTE: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. If the BURST bit is enabled in the I2CMCS register, then the I2CFIFODATA register is used for the current data transmit or receive value and this register is ignored. Figure 7-16. I2CMDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED DATA Table 7-6. I2CMDR Register Field Descriptions Type R R/W Reset 0h 0h Description This byte contains the data transferred during a transaction. 184 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.4 I2CMTPR Register (offset = Ch) [reset = 1h] I2CMTPR is shown in Figure 7-17 and described in Table 7-7. This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard. Figure 7-17. I2CMTPR Register 31 30 29 28 27 26 25 24 23 22 21 20 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 RESERVED RESE RVED R-0h W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 19 3 TPR R/W-1h 18 17 16 PULSEL R/W-0h 2 1 0 Bit 31-19 18-16 Field RESERVED PULSEL 15-8 7 6-0 RESERVED RESERVED TPR Table 7-7. I2CMTPR Register Field Descriptions Type R R/W R R R/W Reset 0h 0h 0h 0h 1h Description Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of system clocks. 0h = Bypass 1h = 1 clock 2h = 2 clocks 3h = 3 clocks 4h = 4 clocks 5h = 8 clocks 6h = 16 clocks 7h = 31 clocks Timer Period This field is used in the equation to configure SCL_PERIOD: SCL_PERIOD = 2 -(1 + TPR) -(SCL_LP + SCL_HP) -CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the system clock period in ns. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 185 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.5 I2CMIMR Register (offset = 10h) [reset = 0h] I2CMIMR is shown in Figure 7-18 and described in Table 7-8. This register controls whether a raw interrupt is promoted to a controller interrupt. Figure 7-18. I2CMIMR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RXFFIM TXFEIM R-0h R/W-0h R/W-0h 7 ARBLOSTIM R/W-0h 6 STOPIM R/W-0h 5 STARTIM R/W-0h 4 NACKIM R/W-0h 3 DMATXIM R/W-0h 2 DAMRXIM R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 RXIM R/W-0h 1 CLKIM R/W-0h www.ti.com 24 16 8 TXIM R/W-0h 0 IM R/W-0h Bit 31-12 11 Field RESERVED RXFFIM 10 TXFEIM 9 RXIM 8 TXIM 7 ARBLOSTIM Table 7-8. I2CMIMR Register Field Descriptions Type R R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Mask 0h = The RXFFRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CMRIS register is set. Transmit FIFO Empty Interrupt Mask Note: The TXFEIM interrupt mask bit in the I2CMIMR register should be clear (masking the TXFE interrupt) when the master is performing an RX Burst from the RXFIFO and should be unmasked before starting a TX FIFO transfers. 0h = The TXFERIS interrupt is suppressed and not sent to the interrupt controller. 1h = The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CMRIS register is set. Receive FIFO Request Interrupt Mask 0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CMRIS register is set. Transmit FIFO Request Interrupt Mask 0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set. Transmit FIFO Request Interrupt Mask 0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set. 186 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 6 STOPIM 5 STARTIM 4 NACKIM 3 DMATXIM 2 DAMRXIM 1 CLKIM 0 IM Register Map Table 7-8. I2CMIMR Register Field Descriptions (continued) Type R/W R/W R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description STOP Detection Interrupt Mask 0h = The STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The STOP detection interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CMRIS register is set. START Detection Interrupt Mask 0h = The STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The START detection interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CMRIS register is set. Address/Data NACK Interrupt Mask 0h = The NACKRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The address/data NACK interrupt is sent to the interrupt controller when the NACKRIS bit in the I2CMRIS register is set. Transmit DMA Interrupt Mask 0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CMRIS register is set. Receive DMA Interrupt Mask 0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CMRIS register is set. Clock Timeout Interrupt Mask 0h = The CLKRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The clock timeout interrupt is sent to the interrupt controller when the CLKRIS bit in the I2CMRIS register is set. Master Interrupt Mask 0h = The RIS interrupt is suppressed and not sent to the interrupt controller. 1h = The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 187 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.6 I2CMRIS Register (offset = 14h) [reset = 0h] I2CMRIS is shown in Figure 7-19 and described in Table 7-9. This register specifies whether an interrupt is pending. Figure 7-19. I2CMRIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RXFFRIS TXFERIS R-0h R-0h R-0h 7 ARBLOSTRIS R-0h 6 STOPRIS R-0h 5 STARTRIS R-0h 4 NACKRIS R-0h 3 DMATXRIS R-0h 2 DMARXRIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 RXRIS R-0h 1 CLKRIS R-0h www.ti.com 24 16 8 TXRIS R-0h 0 RIS R-0h Bit 31-12 11 Field RESERVED RXFFRIS 10 TXFERIS 9 RXRIS 8 TXRIS 7 ARBLOSTRIS Table 7-9. I2CMRIS Register Field Descriptions Type R R R R R R Reset 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Raw Interrupt Status This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register. 0h = No interrupt 1h = The Receive FIFO Full interrupt is pending. Transmit FIFO Empty Raw Interrupt Status 0h = No interrupt 1h = The Transmit FIFO Empty interrupt is pending. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register. Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation. Receive FIFO Request Raw Interrupt Status This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register. 0h = No interrupt 1h = The trigger level for the RX FIFO has been reached or there is data in the FIFO and the burst count is zero. Thus, a RX FIFO request interrupt is pending. Transmit Request Raw Interrupt Status This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register. 0h = No interrupt 1h = The trigger level for the TX FIFO has been reached and more data is needed to complete the burst. Thus, a TX FIFO request interrupt is pending. Arbitration Lost Raw Interrupt Status This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. 0h = No interrupt 1h = The Arbitration Lost interrupt is pending. 188 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-9. I2CMRIS Register Field Descriptions (continued) Bit Field 6 STOPRIS 5 STARTRIS 4 NACKRIS 3 DMATXRIS 2 DMARXRIS 1 CLKRIS 0 RIS Type R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h Description STOP Detection Raw Interrupt Status This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register. 0h = No interrupt 1h = The STOP Detection interrupt is pending. START Detection Raw Interrupt Status This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register. 0h = No interrupt 1h = The START Detection interrupt is pending. Address/Data NACK Raw Interrupt Status This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register. 0h = No interrupt 1h = The address/data NACK interrupt is pending. Transmit DMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register. 0h = No interrupt. 1h = The transmit DMA complete interrupt is pending. Receive DMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register. 0h = No interrupt. 1h = The receive DMA complete interrupt is pending. Clock Timeout Raw Interrupt Status This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. 0h = No interrupt. 1h = The clock timeout interrupt is pending. Master Raw Interrupt Status This interrupt includes: Master transaction completed Next byte transfer request Value Description This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. 0h = No interrupt. 1h = A master interrupt is pending. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 189 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.7 I2CMMIS Register (offset = 18h) [reset = 0h] I2CMMIS is shown in Figure 7-20 and described in Table 7-10. This register specifies whether an interrupt was signaled. Figure 7-20. I2CMMIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RXFFMIS TXFEMIS R-0h R-0h R-0h 7 ARBLOSTMIS R-0h 6 STOPMIS R-0h 5 STARTMIS R-0h 4 NACKMIS R-0h 3 DMATXMIS R-0h 2 DMARXMIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 RXMIS R-0h 1 CLKMIS R-0h www.ti.com 24 16 8 TXMIS R-0h 0 MIS R-0h Bit 31-12 11 Field RESERVED RXFFMIS 10 TXFEMIS 9 RXMIS 8 TXMIS 7 ARBLOSTMIS Table 7-10. I2CMMIS Register Field Descriptions Type R R R R R R Reset 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Mask This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Receive FIFO Full interrupt was signaled and is pending. Transmit FIFO Empty Interrupt Mask This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Transmit FIFO Empty interrupt was signaled and is pending. Receive FIFO Request Interrupt Mask This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Receive FIFO Request interrupt was signaled and is pending. Transmit Request Interrupt Mask This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Transmit FIFO Request interrupt was signaled and is pending. Arbitration Lost Interrupt Mask This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Arbitration Lost interrupt was signaled and is pending. 190 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-10. I2CMMIS Register Field Descriptions (continued) Bit Field 6 STOPMIS 5 STARTMIS 4 NACKMIS 3 DMATXMIS 2 DMARXMIS 1 CLKMIS 0 MIS Type R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h Description STOP Detection Interrupt Mask This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked STOP Detection interrupt was signaled and is pending. START Detection Interrupt Mask This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked START Detection interrupt was signaled and is pending. Address/Data NACK Interrupt Mask This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Address/Data NACK interrupt was signaled and is pending. Transmit DMA Interrupt Status This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked transmit DMA complete interrupt was signaled and is pending. Receive DMA Interrupt Status This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked receive DMA complete interrupt was signaled and is pending. Clock Timeout Masked Interrupt Status This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked clock timeout interrupt was signaled and is pending. Clock Timeout Masked Interrupt Status This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked clock timeout interrupt was signaled and is pending. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 191 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.8 I2CMICR Register (offset = 1Ch) [reset = 0h] I2CMICR is shown in Figure 7-21 and described in Table 7-11. This register clears the raw and masked interrupts. Figure 7-21. I2CMICR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED RXFFIC TXFEIC R-0h W-0h W-0h 7 ARBLOSTIC W-0h 6 STOPIC W-0h 5 STARTIC W-0h 4 NACKIC W-0h 3 DMATXIC W-0h 2 DMARXIC W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 RXIC W-0h 1 CLKCIC W-0h www.ti.com 24 16 8 TXIC W-0h 0 IC W-0h Bit 31-12 11 Field RESERVED RXFFIC 10 TXFEIC 9 RXIC 8 TXIC 7 ARBLOSTIC 6 STOPIC 5 STARTIC 4 NACKIC Table 7-11. I2CMICR Register Field Descriptions Type R W W W W W W W W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Clear Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register and the RXFFMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Transmit FIFO Empty Interrupt Clear Writing a 1 to this bit clears the TXFERIS bit in the I2CMRIS register and the TXFEMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Receive FIFO Request Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the I2CMRIS register and the RXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Transmit FIFO Request Interrupt Clear Writing a 1 to this bit clears the TXRIS bit in the I2CMRIS register and the TXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Arbitration Lost Interrupt Clear Writing a 1 to this bit clears the ARBLOSTRIS bit in the I2CMRIS register and the ARBLOSTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. STOP Detection Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register and the STOPMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. START Detection Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Address/Data NACK Interrupt Clear Writing a 1 to this bit clears the NACKRIS bit in the I2CMRIS register and the NACKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. 192 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-11. I2CMICR Register Field Descriptions (continued) Bit Field 3 DMATXIC 2 DMARXIC 1 CLKCIC 0 IC Type W W W W Reset 0h 0h 0h 0h Description Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS register and the DMATXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CMRIS register and the DMARXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Clock Timeout Interrupt Clear Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and the CLKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Master Interrupt Clear Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 193 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.9 I2CMCR Register (offset = 20h) [reset = 0h] I2CMCR is shown in Figure 7-22 and described in Table 7-12. This register configures the mode (Master or Slave), and sets the interface for test mode loopback. Figure 7-22. I2CMCR Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 RESERVED R-0h 5 SFE R/W-0h 4 MFE R/W-0h 3 2 1 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 24 16 8 0 LPBK R/W-0h Bit 31-6 5 Field RESERVED SFE 4 MFE 3-1 RESERVED 0 LPBK Table 7-12. I2CMCR Register Field Descriptions Type R R/W R/W R R/W Reset 0h 0h 0h 0h 0h Description I2C Slave Function Enable 0h = Slave mode is disabled. 1h = Slave mode is enabled. I2C Master Function Enable 0h = Master mode is disabled. 1h = Master mode is enabled. I2C Loopback 0h = Normal operation. 1h = The controller in a test mode loopback configuration. 194 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.10 I2CMCLKOCNT Register (offset = 24h) [reset = 0h] I2CMCLKOCNT is shown in Figure 7-23 and described in Table 7-13. This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit for clock stretching by a remote slave. The lower four bits of the counter are not user visible and are always 0x0. NOTE: The Master Clock Low Timeout counter counts for the entire time SCL is held Low continuously. If SCL is de-asserted at any point, the Master Clock Low Timeout Counter is reloaded with the value in the I2CMCLKOCNT register and begins counting down from this value. Figure 7-23. I2CMCLKOCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CNTL R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED CNTL Table 7-13. I2CMCLKOCNT Register Field Descriptions Type R R/W Reset 0h 0h Description I2C Master Count This field contains the upper 8 bits of a 12-bit counter for the clock low timeout count. Note: The value of CNTL must be greater than 0x1. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 195 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.11 I2CMBMON Register (offset = 2Ch) [reset = 3h] I2CMBMON is shown in Figure 7-24 and described in Table 7-14. This register is used to determine the SCL and SDA signal status. Figure 7-24. I2CMBMON Register 31 30 29 28 27 26 25 24 23 22 21 20 19 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-2 1 Field RESERVED SDA 0 SCL Table 7-14. I2CMBMON Register Field Descriptions Type R R R Reset 0h 1h 1h Description I2C SDA Status 0h = The I2CSDA signal is low. 1h = The I2CSDA signal is high. I2C SCL Status 0h = The I2CSCL signal is low. 1h = The I2CSCL signal is high. www.ti.com 18 17 16 2 1 0 SDA SCL R-1h R-1h 196 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.12 I2CMBLEN Register (offset = 30h) [reset = 0h] I2CMBLEN is shown in Figure 7-25 and described in Table 7-15. This register contains the programmed length of bytes that are transferred during a Burst request. Figure 7-25. I2CMBLEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CNTL R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED CNTL Table 7-15. I2CMBLEN Register Field Descriptions Type R R/W Reset 0h 0h Description I2C Burst Length This field contains the programmed length of bytes of the Burst Transaction. If BURST is enabled this register must be set to a non-zero value otherwise an error will occur. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 197 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.13 I2CMBCNT Register (offset = 34h) [reset = 0h] I2CMBCNT is shown in Figure 7-26 and described in Table 7-16. When BURST is active, the value in the I2CMBLEN register is copied into this register and decremented during the BURST transaction. This register can be used to determine the number of transfers that occurred when a BURST terminates early (as a result of a data NACK). When a BURST completes successfully, this register will contain 0. Figure 7-26. I2CMBCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CNTL R-0h Ro-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED CNTL Table 7-16. I2CMBCNT Register Field Descriptions Type R Ro Reset 0h 0h Description I2C Master Burst Count This field contains the current count-down value of the BURST transaction. 198 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.14 I2CSOAR Register (offset = 800h) [reset = 0h] I2CSOAR is shown in Figure 7-27 and described in Table 7-17. This register consists of seven address bits that identify the TM4E111BE6ZRB I2C device on the I2C bus. Figure 7-27. I2CSOAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OAR R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-7 6-0 Field RESERVED OAR Table 7-17. I2CSOAR Register Field Descriptions Type R R/W Reset 0h 0h Description I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 199 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.15 I2CSCSR Register (offset = 804h) [reset = 0h] I2CSCSR is shown in Figure 7-28 and described in Table 7-18. This register functions as a control register when written, and a status register when read. www.ti.com Figure 7-28. I2CSCSR Register 31 30 29 28 27 26 25 24 ACTDMARX ACTDMATX RESERVED R-0h R-0h R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 RESERVED R-0h 5 QCMDRW RC-0h 4 QCMDST RC-0h 3 OAR2SEL RO-0h 2 FBR_OR_RXFI FO R/W-0h 1 TREQ_OR_TX FIFO R/W-0h 0 RREQ_OR_DA R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit Field 31 ACTDMARX 30 ACTDMATX 29-6 5 RESERVED QCMDRW 4 QCMDST 3 OAR2SEL 2 FBR_OR_RXFIFO Table 7-18. I2CSCSR Register Field Descriptions Type R R R RC RC RO R/W Reset 0h 0h 0h 0h 0h 0h 0h Description DMA RX Active Status 0h (R) = DMA RX is not active 1h (R) = DMA RX is active. DMA RX Active Status 0h (R) = DMA RX is not active 1h (R) = DMA RX is active. Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. 0h (R) = Quick command was a write 1h (R) = Quick command was a read Quick Command Status 0h (R) = The last transaction was a normal transaction or a transaction has not occurred. 1h (R) = The last transaction was a Quick Command transaction. OAR2 Address Matched This bit gets reevaluated after every address comparison. 0h (R) = Either the address is not matched or the match is in legacy mode. 1h (R) = OAR2 address matched and ACKed by the slave. First Byte Received (R) or RX FIFO Enable This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register. Note: This bit is not used for slave transmit operations. 0h (W) = Disables RX FIFO 0h (R) = The first byte has not been received. 1h (W) = Enables RX FIFO 1h (R) = The first byte following the slave s own address has been received. 200 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-18. I2CSCSR Register Field Descriptions (continued) Bit Field 1 TREQ_OR_TXFIFO Type R/W 0 RREQ_OR_DA R/W Reset 0h 0h Description Transmit Request (R) or TX FIFO Enable (W) 0h (W) = Disables TX FIFO 0h (R) = No outstanding transmit request. 1h (W) = Enables TX FIFO 1h (R) = The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register. Receive Request (R) or Device Active (W) Once this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0h (W) = Disables the I2C slave operation. 0h (R) = No outstanding receive data. 1h (W) = Enables the I2C slave operation. 1h (R) = The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 201 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.16 I2CSDR Register (offset = 808h) [reset = 0h] I2CSDR is shown in Figure 7-29 and described in Table 7-19. NOTE: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. If the RXFIFO bit or TXFIFO bit are enabled in the I2CSCSR register, then this register is ignored and the data value being transferred from the FIFO is contained in the I2CFIFODATA register. NOTE: Best practice recommends that an application should not switch between the I2CSDR register and TX FIFO or vice versa for successive transactions. Figure 7-29. I2CSDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED DATA Table 7-19. I2CSDR Register Field Descriptions Type R R/W Reset 0h 0h Description Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 202 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.1.17 I2CSIMR Register (offset = 80Ch) [reset = 0h] I2CSIMR is shown in Figure 7-30 and described in Table 7-20. This register controls whether a raw interrupt is promoted to a controller interrupt. Figure 7-30. I2CSIMR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 TXFEIM R/W-0h 6 RXIM R/W-0h 5 TXIM R/W-0h 4 DMATXIM R/W-0h 3 DMARXIM R/W-0h 2 STOPIM R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 STARTIM R/W-0h Register Map 24 16 8 RXFFIM R/W-0h 0 DATAIM R/W-0h Bit 31-9 8 Field RESERVED RXFFIM 7 TXFEIM 6 RXIM 5 TXIM 4 DMATXIM 3 DMARXIM Table 7-20. I2CSIMR Register Field Descriptions Type R R/W R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Mask 0h = The RXFFRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CSRIS register is set. Transmit FIFO Empty Interrupt Mask 0h = The TXFERIS interrupt is suppressed and not sent to the interrupt controller. 1h = The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CSRIS register is set. Receive FIFO Request Interrupt Mask 0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CSRIS register is set. Transmit FIFO Request Interrupt 0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CSRIS register is set. Transmit DMA Interrupt Mask 0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CSRIS register is set. Receive DMA Interrupt Mask 0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 203 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map Bit Field 2 STOPIM 1 STARTIM 0 DATAIM www.ti.com Table 7-20. I2CSIMR Register Field Descriptions (continued) Type R/W R/W R/W Reset 0h 0h 0h Description Stop Condition Interrupt Mask 0h = The STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CSRIS register is set. Start Condition Interrupt Mask 0h = The STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1h = The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CSRIS register is set. Data Interrupt Mask 0h = The DATARIS interrupt is suppressed and not sent to the interrupt controller. 1h = Data interrupt sent to interrupt controller when DATARIS bit in the I2CSRIS register is set. 204 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.1.18 I2CSRIS Register (offset = 810h) [reset = 0h] I2CSRIS is shown in Figure 7-31 and described in Table 7-21. This register specifies whether an interrupt is pending. Figure 7-31. I2CSRIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 TXFERIS R-0h 6 RXRIS R-0h 5 TXRIS R-0h 4 DMATXRIS R-0h 3 DMARXRIS R-0h 2 STOPRIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Register Map 25 24 17 16 9 1 STARTRIS R-0h 8 RXFFRIS R-0h 0 DATARIS R-0h Bit 31-9 8 Field RESERVED RXFFRIS 7 TXFERIS 6 RXRIS 5 TXRIS 4 DMATXRIS Table 7-21. I2CSRIS Register Field Descriptions Type R R R R R R Reset 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Raw Interrupt Status This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register. 0h = No interrupt 1h = The Receive FIFO Full interrupt is pending. Transmit FIFO Empty Raw Interrupt Status This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register. Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation. 0h = No interrupt 1h = The Transmit FIFO Empty interrupt is pending. Receive FIFO Request Raw Interrupt Status This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. 0h = No interrupt 1h = The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending. Receive FIFO Request Raw Interrupt Status This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. 0h = No interrupt 1h = The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending. Transmit DMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. 0h = No interrupt 1h = A transmit DMA complete interrupt is pending. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 205 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com Table 7-21. I2CSRIS Register Field Descriptions (continued) Bit Field 3 DMARXRIS 2 STOPRIS 1 STARTRIS 0 DATARIS Type R R R R Reset 0h 0h 0h 0h Description Receive DMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register. 0h = No interrupt 1h = A receive DMA complete interrupt is pending. Stop Condition Raw Interrupt Status This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 0h = No interrupt 1h = A STOP condition interrupt is pending. Start Condition Raw Interrupt Status This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0h = No interrupt. 1h = A START condition interrupt is pending. Data Raw Interrupt Status This interrupt encompasses the following: Slave transaction received Slave transaction requested Next byte transfer request This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 0h = No interrupt. 1h = Slave Interrupt is pending. 206 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.1.19 I2CSMIS Register (offset = 814h) [reset = 0h] I2CSMIS is shown in Figure 7-32 and described in Table 7-22. This register specifies whether an interrupt was signaled. Figure 7-32. I2CSMIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 TXFEMIS R-0h 6 RXMIS R-0h 5 TXMIS R-0h 4 DMATXMIS R-0h 3 DMARXMIS R-0h 2 STOPMIS R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Register Map 25 24 17 16 9 1 STARTMIS R-0h 8 RXFFMIS R-0h 0 DATAMIS R-0h Bit 31-9 8 Field RESERVED RXFFMIS 7 TXFEMIS 6 RXMIS 5 TXMIS 4 DMATXMIS Table 7-22. I2CSMIS Register Field Descriptions Type R R R R R R Reset 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Mask This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register. 0h = No interrupt. 1h = An unmasked Receive FIFO Full interrupt was signaled and is pending. Transmit FIFO Empty Interrupt Mask This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register. 0h = No interrupt. 1h = An unmasked Transmit FIFO Empty interrupt was signaled and is pending. Receive FIFO Request Interrupt Mask This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. 0h = No interrupt. 1h = An unmasked Receive FIFO Request interrupt was signaled and is pending. Transmit FIFO Request Interrupt Mask This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register. 0h = No interrupt. 1h = An unmasked Transmit FIFO Request interrupt was signaled and is pending. Transmit DMA Masked Interrupt Status This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. 0h = An interrupt has not occurred or is masked. 1h = An unmasked transmit DMA complete interrupt was signaled is pending. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 207 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com Table 7-22. I2CSMIS Register Field Descriptions (continued) Bit Field 3 DMARXMIS 2 STOPMIS 1 STARTMIS 0 DATAMIS Type R R R R Reset 0h 0h 0h 0h Description Receive DMA Masked Interrupt Status This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register. 0h = An interrupt has not occurred or is masked. 1h = An unmasked receive DMA complete interrupt was signaled is pending. Stop Condition Masked Interrupt Status This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 0h = An interrupt has not occurred or is masked. 1h = An unmasked STOP condition interrupt was signaled is pending. Start Condition Masked Interrupt Status This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0h = An interrupt has not occurred or is masked. 1h = An unmasked START condition interrupt was signaled is pending. Data Masked Interrupt Status This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 0h = An interrupt has not occurred or is masked. 1h = An unmasked slave data interrupt was signaled is pending. 208 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.1.20 I2CSICR Register (offset = 818h) [reset = 0h] I2CSICR is shown in Figure 7-33 and described in Table 7-23. This register clears the raw interrupt. A read of this register returns no meaningful data. Figure 7-33. I2CSICR Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 TXFEIC W-0h 6 RXIC W-0h 5 TXIC W-0h 4 DMATXIC W-0h 3 DMARXIC W-0h 2 STOPIC W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 STARTIC W-0h Register Map 24 16 8 RXFFIC W-0h 0 DATAIC W-0h Bit 31-9 8 Field RESERVED RXFFIC 7 TXFEIC 6 RXIC 5 TXIC 4 DMATXIC 3 DMARXIC 2 STOPIC 1 STARTIC Table 7-23. I2CSICR Register Field Descriptions Type R W W W W W W W W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Receive FIFO Full Interrupt Mask Writing a 1 to this bit clears the RXFFIS bit in the I2CSRIS register and the RXFFMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Transmit FIFO Empty Interrupt Mask Writing a 1 to this bit clears the TXFERIS bit in the I2CSRIS register and the TXFEMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Receive Request Interrupt Mask Writing a 1 to this bit clears the RXRIS bit in the I2CSRIS register and the RXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Transmit Request Interrupt Mask Writing a 1 to this bit clears the TXRIS bit in the I2CSRIS register and the TXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the I2CSRIS register and the DMATXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Start Condition Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 209 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map Bit Field 0 DATAIC www.ti.com Table 7-23. I2CSICR Register Field Descriptions (continued) Type W Reset 0h Description Start Condition Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 210 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.21 I2CSOAR2 Register (offset = 81Ch) [reset = 0h] I2CSOAR2 is shown in Figure 7-34 and described in Table 7-24. This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus. Figure 7-34. I2CSOAR2 Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 OAR2EN OAR2 R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7 Field RESERVED OAR2EN 6-0 OAR2 Table 7-24. I2CSOAR2 Register Field Descriptions Type R R/W R/W Reset 0h 0h 0h Description I2C Slave Own Address 2 Enable 0h = The alternate address is disabled. 1h = Enables the use of the alternate address in the OAR2 field. I2C Slave Own Address 2 This field specifies the alternate OAR2 address. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 211 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.22 I2CSACKCTL Register (offset = 820h) [reset = 0h] I2CSACKCTL is shown in Figure 7-35 and described in Table 7-25. This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or command. The I2C clock is pulled low after the last data bit until this register is written. Figure 7-35. I2CSACKCTL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 1 ACKOVAL R/W-0h 0 ACKOEN R/W-0h Bit 31-2 1 Field RESERVED ACKOVAL 0 ACKOEN Table 7-25. I2CSACKCTL Register Field Descriptions Type R R/W R/W Reset 0h 0h 0h Description I2C Slave ACK Override Value 0h = An ACK is sent indicating valid data or command. 1h = A NACK is sent indicating invalid data or command. I2C Slave ACK Override Enable 0h = A response in not provided. 1h = An ACK or NACK is sent according to the value written to the ACKOVAL bit. 212 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 7.3.1.23 I2CFIFODATA Register (offset = F00h) [reset = 0h] I2CFIFODATA is shown in Figure 7-36 and described in Table 7-26. The I2C FIFO Data (I2CFIFODATA) register contains the current value of the top of the RX or TX FIFO stack being used in the a transfer. Figure 7-36. I2CFIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-8 7-0 Field RESERVED DATA Table 7-26. I2CFIFODATA Register Field Descriptions Type R R/W Reset 0h 0h Description I2C RX FIFO Data Byte This field contains the current byte being read in the RX FIFO stack. This field contains the current byte written to the TX FIFO. For back to back transmit operations, the application should not switch between writing to the I2CSDR register and the I2CFIFODATA. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 213 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map www.ti.com 7.3.1.24 I2CFIFOCTL Register (offset = F04h) [reset = 40004h] I2CFIFOCTL is shown in Figure 7-37 and described in Table 7-27. The FIFO Control Register can be programmed to control various aspects of the FIFO transaction, such as RX and TX FIFO assignment, byte count value for FIFO triggers and flushing of the FIFOs. Figure 7-37. I2CFIFOCTL Register 31 30 29 28 27 26 25 24 RXASGNMT RXFLUSH DMARXENA RESERVED R/W-0h R/W-0h R/W-0h R-0h 23 22 21 20 19 18 17 16 RESERVED RXTRIG R-0h R/W-4h 15 14 13 12 11 10 9 8 TXASGNMT TXFLUSH DMATXENA RESERVED R/W-0h R/W-0h R/W-0h R-0h 7 6 5 4 3 2 1 0 RESERVED TXTRIG R-0h R/W-4h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit Field 31 RXASGNMT 30 RXFLUSH 29 DMARXENA 28-19 18-16 RESERVED RXTRIG 15 TXASGNMT 14 TXFLUSH 13 DMATXENA Table 7-27. I2CFIFOCTL Register Field Descriptions Type R/W R/W R/W R R/W R/W R/W R/W Reset 0h 0h 0h 0h 4h 0h 0h 0h Description RX Control Assignment 0h = RX FIFO is assigned to Master 1h = RX FIFO is assigned to Slave RX FIFO Flush Setting this bit will Flush the RX FIFO. This bit will self-clear when the flush has completed. DMA RX Channel Enable 0h = DMA RX channel disabled 1h = DMA RX channel enabled RX FIFO Trigger Indicates at what fill level the RX FIFO will generate a trigger. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0h = Trigger when RX FIFO contains no bytes 1h = Trigger when Rx FIFO contains 1 or more bytes 2h = Trigger when Rx FIFO contains 2 or more bytes 3h = Trigger when Rx FIFO contains 3 or more bytes 4h = Trigger when Rx FIFO contains 4 or more bytes 5h = Trigger when Rx FIFO contains 5 or more bytes 6h = Trigger when Rx FIFO contains 6 or more bytes 7h = Trigger when Rx FIFO contains 7 or more bytes. TX Control Assignment 0h = TX FIFO is assigned to Master 1h = TX FIFO is assigned to Slave TX FIFO Flush Setting this bit will Flush the TX FIFO. This bit will self-clear when the flush has completed. DMA TX Channel Enable 0h = DMA TX channel disabled 1h = DMA TX channel enabled 214 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map Table 7-27. I2CFIFOCTL Register Field Descriptions (continued) Bit 12-3 2-0 Field RESERVED TXTRIG Type R R/W Reset 0h 4h Description TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0h = Trigger when the TX FIFO is empty. 1h = Trigger when TX FIFO contains 1 byte 2h = Trigger when TX FIFO contains 2 bytes 3h = Trigger when TX FIFO 3 bytes 4h = Trigger when TX FIFO 4 bytes 5h = Trigger when TX FIFO 5 bytes 6h = Trigger when TX FIFO 6 bytes 7h = Trigger when TX FIFO 7 bytes SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 215 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.25 I2CFIFOSTATUS Register (offset = F08h) [reset = 10005h] I2CFIFOSTATUS is shown in Figure 7-38 and described in Table 7-28. This register contains the real-time status of the RX and TX FIFOs. Figure 7-38. I2CFIFOSTATUS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED RXABVTRIG R-0h R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED TXBLWTRIG R-0h R-1h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 RXFF R-0h 9 1 TXFF R-0h www.ti.com 24 16 RXFE R-1h 8 0 TXFE R-1h Bit 31-19 18 Field RESERVED RXABVTRIG 17 RXFF 16 RXFE 15-3 2 RESERVED TXBLWTRIG 1 TXFF 0 TXFE Table 7-28. I2CFIFOSTATUS Register Field Descriptions Type R R R R R R R R Reset 0h 0h 0h 1h 0h 1h 0h 1h Description RX FIFO Above Trigger Level 0h = The number of bytes in RX FIFO is below the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register 1h = The number of bytes in the RX FIFO is above the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register RX FIFO Full 0h = The RX FIFO is not full. 1h = The RX FIFO is full. RX FIFO Empty 0h = The RX FIFO is not empty. 1h = The RX FIFO is empty. TX FIFO Below Trigger Level 0h = The number of bytes in TX FIFO is above the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register 1h = The number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register TX FIFO Full 0h = The TX FIFO is not full. 1h = The TX FIFO is full. TX FIFO Empty 0h = The TX FIFO is not empty. 1h = The TX FIFO is empty. 216 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.1.26 I2CPP Register (offset = FC0h) [reset = 1h] I2CPP is shown in Figure 7-39 and described in Table 7-29. The I2CPP register provides information regarding the properties of the I2C module. Figure 7-39. I2CPP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Register Map 17 16 1 0 HS R-1h Bit 31-1 0 Field RESERVED HS Table 7-29. I2CPP Register Field Descriptions Type R R Reset 0h 1h Description High-Speed Capable 0h = The interface is capable of Standard or Fast mode operation. 1h = Reserved. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Circuit (I2C) Interface 217 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Register Map 7.3.1.27 I2CPC Register (offset = FC4h) [reset = 1h] I2CPC is shown in Figure 7-40 and described in Table 7-30. The I2CPC register allows software to enable features present in the I2C module. www.ti.com Figure 7-40. I2CPC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED HS R-0h R-1h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-1 0 Field RESERVED HS Table 7-30. I2CPC Register Field Descriptions Type R R Reset 0h 1h Description High-Speed Capable 0h = The interface is capable of Standard or Fast mode operation. 1h = Reserved. Must be set to 0 218 Inter-Integrated Circuit (I2C) Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 8 SWRU367B – June 2014 – Revised October 2014 SPI (Serial Peripheral Interface) Topic ........................................................................................................................... Page 8.1 Overview ......................................................................................................... 220 8.2 Functional Description ...................................................................................... 221 8.3 Initialization and Configuration .......................................................................... 236 8.4 Access to Data Registers .................................................................................. 238 8.5 Module Initialization.......................................................................................... 238 8.6 SPI Registers ................................................................................................... 244 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 219 Overview www.ti.com 8.1 Overview This document is intended to provide programmers with a functional presentation of the Master/Slave Serial Peripheral Interface module. It provides a module configuration example. In this specification, the Master/Slave Serial Peripheral Interface will be named SPI. The serial peripheral interface (SPI) is a four-wire bidirectional communications interface that converts data between parallel and serial. The CC3200 device has two SPI interfaces. • One SPI (master) interface is reserved for interfacing an external serial flash to CC3200. The serial flash is used to hold the application image and networking credentials, policies and software patches. This is referred to as the FLASH_SSPI; it has a fixed mapping to package pins. • The second SPI interface can be used by the application in either master or slave mode. Refer to on pin-mux for the supported pin mapping options for this interface and the state of the pins in various sleep and reset states. CLKSPIREF is clock input to the SPI module. It has a gating in PRCM module (please refer to on clock-reset-power management). The subdivision of this clock is inside the SPI module. CC3200 does not support waking up of the chip on SPI interface activity. This chapter focuses on the second SPI interface. The SPI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SPI module can be configured as either a master or slave device. As a slave device, the SPI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SPI module also includes a programmable bit rate clock divider to generate the output serial clock derived from the input clock of the SPI module. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The SPI allows full duplex between a local host and SPI-compliant external devices (slaves and masters). Figure 8-1 shows a high-level overview of the SPI system. 220 SPI (Serial Peripheral Interface) Figure 8-1. SPI Block Diagram SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 8.1.1 Features • Serial clock with programmable frequency, polarity, and phase • SPI enable – Generation programmable – Programmable polarity • Selection of SPI word lengths at 8, 16, and 32 bits • Support of both master and slave modes • Independent DMA requests for read and write • No dead cycle between two successive words in slave mode • Multiple SPI word access with a channel using an enabled FIFO The SPI allows a duplex serial communication between a local host and SPI-compliant external devices (slaves and masters). 8.2 Functional Description 8.2.1 SPI interface This section lists the name and description of the SPI interface used for connection to external SPI compliant devices. Name MISO/MOSI [1:0] SPICLK SPIEN Table 8-1. SPI Interface Type Reset Value In-Out Z In-Out Z In-Out Z Description Serial data lines for transmitting and receiving data. Transmits the serial clock when configured as a Master. Receives the serial clock when configured as a Slave. Indicates the beginning and the end of serialized data word. Selects the external slave SPI devices when configured as Master. Receives the slave select signal from external SPI masters when configured as a Slave 8.2.2 SPI Transmission This section describes the transmissions supported by SPI. The SPI protocol is a synchronous protocol that allows a master device to initiate serial communication with a slave device. Data is exchanged between these devices. A slave select line (SPIEN) can be use to allow selection of slave SPI device. The flexibility of SPI allows exchanging data with several formats through programmable parameters. 8.2.2.1 Two data pins interface mode The two data pins interface mode, allows a full duplex SPI transmission where data is transmitted (shifted out serially) and received (shifted in serially) simultaneously on separate data lines MISO and MOSI. • Data leaving the master exits on transmit serial data line also known as MOSI: MasterOutSlaveIn. • Data leaving the slave exits on the receive data line also known as MISO: MasterInSlaveOut. The serial clock (SPICLK) synchronizes shifting and sampling of the information on the two serial data lines. Each time a bit is transferred out from the Master; one bit is transferred in from Slave. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 221 Functional Description www.ti.com Figure 8-2 shows an example of a full duplex system with a Master device on the left and a Slave device on the right. After 8 cycles of the serial clock SPICLK, the WordA has been transferred from the master to the slave. At the same time, the WordB has been transferred from the slave to the master. Figure 8-2. SPI full duplex transmission (Example) When referring to the master device, the control block transmits the clock SPICLK and the enable signal SPIEN. 8.2.2.2 Transfer formats This section describes the transfer formats supported by SPI. The flexibility of SPI allows setting the parameters of the SPI transfer: • SPI word length • SPI enable generation programmable • SPI enable assertion • SPI enable polarity • SPI clock frequency • SPI clock phase • SPI clock polarity The consistency between SPI word length, clock phase and clock polarity of the master SPI device and the communicating slave device remains under software responsibility. 8.2.2.2.1 Programmable Word Length SPI supports word of 8, 16 and 32 bits long. 8.2.2.2.2 Programmable SPI Enable (SPIEN) The polarity of the SPIEN signals is programmable. SPIEN signals can be active high or low. The assertion of the SPIEN signals is programmable: SPIEN signals can be manually asserted or can be automatically asserted. 8.2.2.2.3 Programmable SPI Clock (SPICLK) The phase and the polarity of the SPI serial clock are programmable when SPI is a master device or a slave device. The baud rate of the SPI serial clock is programmable when SPI is a master. When SPI is operating as a slave, the serial clock SPICLK is an input from the external master. 222 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 8.2.2.2.4 Bit Rate In Master Mode, an internal reference clock CLKSPIREF is used as an input of a programmable divider to generate bit rate of the serial clock SPICLK. 8.2.2.2.5 Polarity and Phase SPI supports 4 sub-modes of the SPI format transfer that depend on the polarity (POL) and the phase (PHA) of the SPI serial clock (SPICLK). The details of each sub-mode are described in the following chapters. Table 8-2 shows a summary of the 4 sub-modes. Software selects one of four combinations of serial clock phase and polarity. Polarity (POL) 0 0 1 Table 8-2. Phase and Polarity Combinations Phase (PHA) 0 1 0 SPI Mode mode0 mode1 mode2 Comments SPICLK active high and sampling occurs on the rising edge. SPICLK active high and sampling occurs on the falling edge. SPICLK active low and campling occurs on the falling edge. SPICLK active low and 1 1 mode3 sampling occurs on the rising edge. 8.2.2.2.5.1 Transfer format with PHA = 0 This section describes the concept of a SPI transmission with the SPI mode0 and the SPI mode2. In the transfer format with PHA = 0, SPIEN is activated a half cycle of SPICLK ahead of the first SPICLK edge. In both master and slave modes, SPI drives the data lines at the time of SPIEN is asserted. Each data frame is transmitted starting with the MSB. At the extremity of both SPI data lines, the first bit of SPI word is valid a half cycle of SPICLK after the SPIEN assertion. Therefore the first edge of the SPICLK line is used by the master to sample the first data bit sent by the slave. On the same edge, the first data bit sent by the master is sampled by the slave. On the next SPICLK edge, the received data bit is shifted into the shift register, and a new data bit is transmitted on the serial data line. This process continues for a total of pulses on the SPICLK line defined by the SPI word length programmed in the master device, with data being latched on odd numbered edges and shifted on even numbered edges. Figure 8-3 is a timing diagram of a SPI transfer for the SPI mode0 and the SPI mode2, when SPI is master or slave, with the frequency of SPICLK equals to the frequency of CLKSPIREF. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 223 Functional Description www.ti.com Figure 8-3. Full duplex single transfer format with PHA = 0 t Lead— Minimum leading time required for slave mode (guaranteed in master mode) before the first SPICLK edge. t Lag— Minimum trailing time required for slave mode (guaranteed in master mode) after the last SPICLK edge. In 3-pin mode without using the SPIEN signal, the controller provides the same waveform but with SPIEN forced to low state. In 3 pin slave mode SPIEN is useless. 8.2.2.2.5.2 Transfer format with PHA = 1 This section describes SPI full duplex transmission with the SPI mode1 and the SPI mode3. In the transfer format with PHA = 1, SPIEN is activated a delay (tLead) ahead of the first SPICLK edge. In both master and slave modes, SPI drives the data lines on the first SPICLK edge. Each data frame is transmitted starting with the MSB. At the extremity of both SPI data lines, the first bit of SPI word is valid on the next SPICLK edge, a half cycle of SPICLK later. It is the sampling edge for both the master and slave. When the third edge occurs, the received data bit is shifted into the shift register. The next data bit of the master is provided to the serial input pin of the slave. This process continues for a total of pulses on the SPICLK line defined by the word length programmed in the master device, with data being latched on even numbered edges and shifted on odd numbered edges. Figure 8-4 is a timing diagram of a SPI transfer for the SPI mode1 and the SPI mode3, when SPI is master or slave, with the frequency of SPICLK equals to the frequency of CLKSPIREF. 224 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 8-4. Full duplex single transfer format with PHA = 1 t Lead— Minimum leading time required for slave mode (guaranteed in master mode) before the first SPICLK edge. t Lag— Minimum trailing time required for slave mode (guaranteed in master mode) after the last SPICLK edge. In 3-pin mode without using the SPIEN signal, the controller provides the same waveform but with SPIEN forced to low state. In 3 pin slave mode SPIEN is useless. 8.2.3 Master Mode SPI is in master mode when the bit MS of the register SPI_MODULCTRL is cleared. 8.2.3.1 Interrupt events in master mode In master mode, the interrupt events related to the transmitter register state are TX_empty and TX_underflow. The interrupt event related to the receiver register state is RX_full. 8.2.3.1.1 TX_empty The event TX_empty is activated when a channel is enabled and its transmitter register becomes empty (transient event). Enabling channel automatically raises this event. When FIFO buffer is enabled (MCSPI_CHCONF[FFEW] set to 1), the TX_empty is asserted as soon as there is enough space in buffer to write a number of byte defined by MCSPI_XFERLEVEL[AEL]. Transmitter register must be loaded to remove the source of the interrupt and the TX_empty interrupt status bit must be cleared for interrupt line de-assertion (if event enabled as interrupt source). When FIFO is enabled, no new TX_empty event is asserted as soon as the local host has not performed the number of write into transmitter register defined by MCSPI_XFERLEVEL[AEL]. The local host must perform the right number of writes. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 225 Functional Description www.ti.com 8.2.3.1.2 TX_underflow The event, TX_underflow is activated when the channel is enabled and if the transmitter register or FIFO is empty (not updated with new data) at the time of shift register assignment. The TX_underflow is a harmless warning in master mode. To avoid having TX_underflow event at the beginning of a transmission, the event TX_underflow is not activated when no data has been loaded into the transmitter register since the channel has been enabled. To avoid having TX_underflow event the Transmitter register must be loaded seldom. TX_underflow interrupt status bit must be cleared for interrupt line de-assertion (if event enable as interrupt source). 8.2.3.1.3 RX_ full The event RX_full is activated when channel is enabled and receiver register becomes filled. When FIFO buffer is enabled (MCSPI_CHCONF[FFER] set to 1), the RX_full is asserted as soon as there is a number of bytes holds in buffer to read defined by MCSPI_XFERLEVEL[AFL]. Receiver register must be read to remove source of interrupt and RX_full interrupt status bit must be cleared for interrupt line de-assertion (if event enabled as interrupt source). When FIFO is enabled, no new RX_full event will be asserted till Local Host has not performed the number of read into receive register defined by MCSPI_XFERLEVEL[AFL]. It is the responsibility of Local Host to perform the right number of reads. 8.2.3.1.4 End of Word Count The event EOW (End of Word Count) is activated when channel is enabled and configured to use the built-in FIFO. This interrupt is raised when the controller has performed the number of transfers defined in MCSPI_XFERLEVEL[WCNT] register. If the value was programmed to 0x0000, the counter is not enabled and this interrupt is not generated. The End of Word Count interrupt also indicates that the SPI transfer is halt on channel (using the FIFO buffer) until MCSPI_XFERLEVEL[WCNT] is not reloaded and channel is re-enabled. End of Word interrupt status bit must be cleared for interrupt line de-assertion (if event enable as interrupt source). 8.2.3.2 Master Transmit and Receive Mode This mode is programmable by bit TRM of the register SPI_CHCONF. The channel access to the shift registers is based on its transmitter and receiver register state. Rule 1: Only if channel is enabled (bit EN of the register SPI_CHCTRL), can be scheduled for transmission and/or reception. Rule 2: An enabled channel can be scheduled if its transmitter register is not empty (bit TXS of the register SPI_CHSTAT) or its FIFO is not empty in case of buffer is used (bit FFE of the register MCSPI_CHSTAT), that is updated with new data; at the time of shift register assignment. If the transmitter register or FIFO is empty, at the time of shift register assignment, the event TX_underflow is activated. Rule 3: An enabled channel can be scheduled if its receive register is not full (bit RXS of the register SPI_CHSTAT) or its FIFO is not full in case of buffer used (bit FFF of the register MCSPI_CHSTAT) at the time of shift register assignment. Therefore the receiver register of FIFO cannot be overwritten. The RX_overflow bit, in the SPI_IRQSTATUS register is never set in this mode. The built-in FIFO is available in this mode and can be configured in one or both data direction for Transmit or Receive. The FIFO is seen as a unique 64 bytes buffer if it is configured for one data direction. If it is configured in both data direction (Transmit and Receive) then the FIFO is split into two separate 32 byte buffers with their own address space management. In this case the definition of AEL and AFL levels is based on32 bytes and is under local host responsibility. 8.2.3.3 SPI enable control in Master mode When SPI is configured as a master device, the assertion of the SPIEN is optional depending on device connected to the controller. The following is a description of each configuration: In 3-Pin Mode: MCSPI_MODULCTRL[1] PIN34 and MCSPI_MODULCTRL[0] SINGLE bit are set to 1, the controller transmit spi word as soon as transmit register or FIFO is not empty. 226 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description In 4-Pin Mode: MCSPI_MODULCTRL[1] PIN34 bit is set to 0 and MCSPI_MODULCTRL[0] SINGLE bit is set to 1, SPIEN assertion/deassertion controlled by Software. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN) Continuous transfers are manually allowed by keeping the SPIEN signal active for successive SPI words. Several sequences (configuration - enable – disable of the channel) can be run without deactivating the SPIEN line. This ‘keep SPIEN active’ mode is authorized when: • The parameters of the transfer are loaded in the configuration register (MCSPI_CHCONF) • The state of the SPIEN signal is programmable: – Writing 1 into the bit FORCE of the register MCSPI_CHCONF drives high the SPIEN line when MCSPI_CHCONF[EPOL] is set to zero, and drives it low when MCSPI_CHCONF[EPOL] is set. – Writing 0 into the bit FORCE of the register MCSPI_CHCONF drives low the SPIEN line when MCSPI_CHCONF[EPOL] is set to zero, and drives it high when MCSPI_CHCONF[EPOL] is set. Once the channel is enabled, the SPIEN signal is activated with the programmed polarity. The start of the transfer depends on the status of the transmitter register, the status of the receiver register. The status of the serialization completion of each SPI word is given by the bit EOT of the SPI_CHSTAT register is set when a received data is loaded from the shift register to the receiver register. A change in the configuration parameters is directly propagated on the SPI interface. If the SPIEN signal is activated the user must insure that the configuration is changed only between SPI words, in order to avoid corrupting the current transfer. Note that SPIEN polarity, the SPICLK phase and SPICLK polarity must not be modified when the SPIEN signal is activated. The channel can be disabled and enabled while the SPIEN signal is activated. At the end of the last SPI word, the channel must be deactivated (MCSPI_CHCTRL[En] set to 0) and the SPIEN can be forced to its inactive state (MCSPI_CHCONF[Force]). Figure 8-5. Contiguous Transfers with SPIEN Kept Active (2 Data Pins Interface Mode) Figure 8-5 shows successive transfers with SPIEN kept active low with a different configuration for each SPI word in respectively single data pin interface mode and two data pins interface mode. The arrows indicate when the channel is disabled before a change in the configuration parameters and enabled again. 8.2.3.4 Clock Ratio Granularity The clock division ratio is defined by the register MCSPI_CHCONF[CLKD] with power of two granularity leading to a clock division in range 1 to 32768, in this case the duty cycle is always 50%. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 227 Functional Description Clock Ratio F ratio 1 Even ≥ 2 Table 8-3. Clock Ratio Granularity CLKSPIO High Time T high_ref T_ref × (F ratio/2) Granularity examples with a clock source frequency of 48 Mhz: MCSPI _CHC ONF [CLKD ] 0 1 2 3 F ratio 1 2 4 8 Table 8-4. Granularity Examples MCSPI _CHC ONF [PHA] MCSPI_CHCO NF [POL] X X X X X X X X T high (ns) 10.4 20.8 41.6 83.2 T low (ns) 10.4 20.8 41.6 83.2 T period (ns) 20.8 41.6 83.2 166.4 www.ti.com CLKSPIO Low Time T low_ref T_ref × (F ratio/2) Duty Cycle F out (Mhz) 50-50 48 50-50 24 50-50 12 50-50 6 8.2.3.4.1 FIFO Buffer Management The Spi controller has a built-in 64 bytes buffer in order to unload DMA or interrupt handler and improve data throughput. This buffer can be used by setting MCSPI_CHCONF[FFER] or MCSPI_CHCONF[FFEW] to 1. The buffer can be used in the modes defined below: • Master or Slave mode • Every word length MCSPI_CHCONF[WL] are supported. Two levels AEL and AFL located in the MCSPI_XFERLEVEL register rule the buffer management. The driver must set these values as a multiple of SPI word length defined in MCSPI_CHCONF[WL]. The number of byte written in the FIFO depends on word length (see Table 8-5). The FIFO buffer pointers are reset when the channel is enabled or FIFO configuration changes. Number of bytes written in the FIFO Table 8-5. SPI Word Length WL SPI Word Length 8 2 Bytes 16 and 32 4 Bytes 8.2.3.4.1.1 Splitted FIFO The FIFO can be split into two parts when the module is configured in Transmit/receive mode, MCSPI_CHCONF[TRM] set to 0 and MCSPI_CHCONF[FFER] and MCSPI_CHCONF[FFEW] asserted. Then system can access a 32 byte depth FIFO per direction. 228 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 8-6. Transmit/receive mode with no FIFO used Figure 8-7. Transmit/receive mode with only receive FIFO enabled SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 229 Functional Description www.ti.com Figure 8-8. Transmit/receive mode with only transmit FIFO used Figure 8-9. Transmit/receive mode with both FIFO direction used 8.2.3.4.1.2 Buffer Almost Full The bitfield MCSPI_XFERLEVEL[AFL] is needed when the buffer is used to receive Spi word from a slave (MCSPI_CHCONF[FFER] must be set to 1). It defines the Almost Full buffer status. When FIFO pointer reaches this level an interrupt or a DMA request is sent to the Local Host to enable system to read AFL+1 bytes from Receive register. Be careful AFL+1 must correspond to a multiple value of MCSPI_CHCONF[WL]. When DMA is used, the request is de-asserted after the first Receive register read. No new request will be asserted till has not performed the right number of read accesses. 230 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 8-10. Buffer Almost Full Level (AFL) 8.2.3.4.1.3 Buffer Almost Empty The bitfield MCSPI_XFERLEVEL[AEL] is needed when the buffer is used to transmit Spi word to a slave (MCSPI_CHCONF[FFEW] must be set to 1). It defines the Almost Empty buffer status. When FIFO pointer has reached this level an interrupt or a DMA request is sent to the Local Host to enable system to write AEL+1 bytes to Transmit register. Be careful AEL+1 must correspond to a multiple value of MCSPI_CHCONF[WL]. When DMA is used, the request is de-asserted after the first Transmit register write. No new request will be asserted again till system has not performed the right number of write accesses. Figure 8-11. Buffer Almost Empty Level (AEL) 8.2.3.4.1.4 End of Transfer Management When the FIFO buffer is enabled for a channel, the user configures the MCSPI_XFERLEVEL register, the AEL and AFL levels, and the WCNT bit field to define the number of SPI word to be transferred using the FIFO before enabling the channel. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 231 Functional Description www.ti.com This counter allows the controller to stop the transfer after a defined number of SPI word transfer. If WCNT is set to 0x0000, the counter is not used and the user must stop the transfer manually by disabling the channel, in case the user does not know how many SPI transfers have been done. For a receive transfer, the software polls the corresponding FFE bit field and read the Receive register to empty the FIFO buffer. When the End Of Word count interrupt is generated, the user can disable the channel and poll on MCSPI_CHSTAT[FFE] register to know if there is SPI word in FIFO buffer, and read the last words. 8.2.3.4.1.5 3- or 4-Pin Mode. The external SPI bus interface can be configured to use a restricted set of pin using the bit field MCSPI_MODULCTRL[1] PIN34 and depending on targeted application: • If MCSPI_MODULECTRL[1] is set to 0 (default value) the controller is in 4-pin mode using the SPI pins CLKSPI, SOMI, SIMO and chip enable CS. • If MCSPI_MODULECTRL[1] is set to 1 the controller is in 3-pin mode using the SPI pins CLKSPI, SOMI and SIMO. In this mode it is mandatory to have only one SPI device on the bus. Figure 8-12. 3-Pin Mode System Overview In 3-pin mode all options related to chip select management are not used: • MCSPI_CHxCONF[EPOL] • MCSPI_CHxCONF[TCS0] • MCSPI_CHxCONF[FORCE] 232 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com The chip select pin SPIEN is force to ‘0’ in this mode. Functional Description 8.2.4 Slave Mode SPI is in slave mode when the MS bit of the SPI_MODULCTRL register is set. In slave mode, SPI should be connected to only one external master device. In slave mode, SPI initiates data transfer on the data lines (MISO/MOSI) when it receives an SPI clock (SPICLK) from the external SPI master device. The controller is able to work with or without a chip select SPIEN depending on the MCSPI_MODULCTRL[1] PIN34 bit setting. It also support transfers without a dead cycle between two successive words. The following configurations are available for the slave channel: • A channel enable, programmable with the EN bit of the SPI_CHCTRL register. This channel should be enabled before transmission and reception. Disabling the channel, outside data word transmission, is the user's responsibility. • A transmitter register SPI_TX on top of the common shift register. If the transmitter register is empty, the status bit TXS of the SPI_CHSTAT register is set. When SPI is selected by an external master (active signal on the SPIEN port), the transmitter register content of channel is always loaded in shift register whether it has been updated or not. The transmitter register should be loaded before SPI is selected by a master. • A receiver register SPI_RX on top of the common shift register. If the receiver register is full, the status bit RXS of the SPI_CHSTAT register is set. • A communication configuration with the following parameters via the MCSPI_CHCONF register: – Transmit/Receive modes, programmable with the bit TRM. – SPI word length, programmable with the bits WL. – SPIEN polarity, programmable with the bit EPOL. – SPICLK polarity, programmable with the bit POL. – SPICLK phase, programmable with the bit PHA. – Use a FIFO buffer or not, programmable with FFER and FFEW, depending on transfer mode TRM. – The SPICLK frequency of a transfer is controlled by the external SPI master. – Two DMA requests events, read and write, to synchronize read/write accesses of the DMA controller with the activity of SPI. The DMA requests are enabled with the bits DMAR and DMAW of the MCSPI_CHCONF register. 8.2.4.1 Interrupts events in slave mode The interrupt events related to the transmitter register state are TX_empty and TX_underflow. The interrupt events related to the receiver register state are RX_full and RX_overflow. 8.2.4.1.1 TX_empty The TX_empty event activates when the channel is enabled and its transmitter register becomes empty. Enabling channel automatically raises this event. When the FIFO buffer is enabled (MCSPI_CHCONF[FFEW] set to 1), the TX_empty is asserted as soon as there is enough space in buffer to write a number of byte defined by MCSPI_XFERLEVEL[AEL]. The transmitter register must be loaded to remove the source of the interrupt and the TX_empty interrupt status bit must be cleared for the interrupt line de-assertion (if event enable is the interrupt source). When FIFO is enabled, no new TX_empty event is asserted if the local host has not performed the number of writes into the transmitter register defined by MCSPI_XFERLEVEL[AEL]. The local host must perform the correct number of writes. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 233 Functional Description www.ti.com 8.2.4.1.2 TX_underflow The TX_underflow event activates when the channel is enabled and the transmitter register or FIFO (if buffer is enabled) is empty (not updated with new data), when an external master device starts a data transfer with SPI (transmit and receive). When FIFO is enabled, the data emitted while the underflow event is raised is not the last data written in the FIFO. The TX_underflow indicates an error (data loss) in slave mode. To avoid having a TX_underflow event at the beginning of a transmission, the event TX_underflow is not activated when no data has been loaded into the transmitter register, because the channel has been enabled. TX_underflow interrupt status bit must be cleared for an interrupt line de-assertion (if event is enabled as the interrupt source). 8.2.4.1.3 RX_ full The RX_full event activates when the channel is enabled and the receiver is filled (transient event). When the FIFO buffer is enabled (MCSPI_CHCONF[FFER] set to 1), the RX_full is asserted once there is a number of bytes held in the buffer to read defined by MCSPI_XFERLEVEL[AFL]. The receiver register must be read to remove the source of the interrupt and the RX_full interrupt status bit must be cleared for an interrupt line de-assertion (if event is enabled as an interrupt source). When FIFO is enabled, no new RX_full event is asserted if the local host has not performed the number of reads into the receive register defined by MCSPI_XFERLEVEL[AFL]. The local host must perform the correct number of reads. 8.2.4.1.4 RX_overflow The RX_overflow event activates when the channel is enabled and the receiver register or FIFO (if the buffer is enabled) is full at the time of a new SPI word reception. The receiver register is always overwritten with the new SPI word. If FIFO is enabled and the data within the FIFO is overwritten, it must be corrupted. The RX_overflow event should not appear in slave mode using the FIFO. The RX_overflow indicates an error (data loss) in slave mode. The RX_overflow interrupt status bit must be cleared for an interrupt line de-assertion (if event is enabled as an interrupt source). 8.2.4.1.5 End Of Word count The EOW (End of Word Count) event activates when the channel is enabled and configured to use the build-in FIFO. This interrupt is raised when the controller performs the number of transfers defined in the MCSPI_XFERLEVEL[WCNT] register. If the value is programmed to 0x0000, the counter is not enabled and this interrupt is not generated. The End of Word count interrupt also indicates that the SPI transfer is stopped on the channel using the FIFO buffer as soon as MCSPI_XFERLEVEL[WCNT] is not reloaded and the channel re-enabled. The End of Word interrupt status bit must be cleared for the interrupt line de-assertion (if event is enabled as an interrupt source). 8.2.4.2 Slave Transmit and Receive mode The slave transmit and receive mode is programmable (bits TRM set to 00 in the register SPI_CHCONF). After the channel is enabled, transmission and reception proceed with interrupt and DMA request events. In slave transmit and receive mode, the transmitter register should be loaded before SPI is selected by an external SPI master device. The transmitter register or FIFO (if the use of a buffer is enabled) content is always loaded in the shift register whether updated or not. The TX_underflow event activates, and does not prevent transmission. Upon completion of SPI word transfer (bit EOT of the SPI_CHSTAT register is set), the received data is transferred to the channel receive register. This bit is meaningless when using the Buffer for this channel. 234 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description The built-in FIFO is available in this mode and can be configured in one data direction Transmit or Receive to ensure that the FIFO is seen as a unique 64 byte buffer. The FIFO can also be configured in both data directions Transmit and Receive, to ensure the FIFO is split into two separate 32 byte buffers with individual address space management. In this last case, the definition of the AEL and AFL levels is based on 64 bytes and is the responsibility of the local host. 8.2.5 Interrupts According to the transmitter register state and the receiver register state, the channel can issue interrupt events if enabled. Each interrupt event has a status bit in the SPI_IRQSTATUS register which indicates service is required, and an interrupt enable bit in the SPI_IRQENABLE register which enables the status to generate hardware interrupt requests. When an interrupt occurs and a mask is then applied on it (IRQENABLE), the interrupt line is not asserted again even if the interrupt source has not been serviced. SPI supports interrupt-driven operation and polling. 8.2.5.1 Interrupt-Driven Operation Alternatively, an interrupt enable bit in the SPI_IRQENABLE register can be set to enable each of the events to generate interrupt requests when the corresponding event occurs. Status bits are automatically set by hardware logic conditions. When an event occurs (the single interrupt line is asserted), the local host must: • Read the SPI_IRQSTATUS register to identify which event occurred. • Interrupt handling: – Read the receiver register that corresponds to the event, to remove the source of an RX_full event, or – Write into the transmitter register that corresponds to the event, to remove the source of a TX_empty event. – No action is needed to remove the source of the events TX_underflow and RX_overflow. • Write a 1 into the corresponding bit of the SPI_IRQSTATUS register to clear the interrupt status, and release the interrupt line. The interrupt status bit should always be reset after channel enabling and before events are enabled as interrupt source. 8.2.5.2 Polling When the interrupt capability of an event is disabled in the SPI_IRQENABLE register, the interrupt line is not asserted and: • The status bits in the SPI_IRQSTATUS register is polled by software to detect when the corresponding event occurs. • Once the expected event occurs, local host must read the receiver register that corresponds to the event to remove the source of an RX_full event, or write into the transmitter register that corresponds to the event to remove the source of a TX_empty event. No action is needed to remove the source of the events TX_underflow and RX_overflow. • Writing a 1 into the corresponding bit of the SPI_IRQSTATUS register clears the interrupt status and does not affect the interrupt line state. 8.2.6 DMA Requests SPI can be interfaced with a DMA controller. At the system level, the advantage is to discharge the local host of the data transfers. According to FIFO level (if use of buffer for the channel) the channel can issue DMA requests if enabled. The DMA requests must be disabled to get TX and RX interrupts. There are 2 DMA request lines for the channel. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 235 Functional Description www.ti.com 8.2.6.1 FIFO Buffer Enabled The DMA Read request line asserts when the channel is enabled and a number of bytes defined in SPI_XFERLEVEL[AFL] bit field is held in the FIFO buffer for the receive register of the channel. A DMA Read request can be individually masked with the DMAR bit of the SPI_CHCONF register. The DMA Read request line is de-asserted on the first SPI word read completion of the receive register of the channel. No new DMA request is asserted if user has not performed the right number of read accesses as defined by SPI_XFERLEVEL[AFL]. The DMA Write request line asserts when the channel is enabled and the number of bytes held in the FIFO buffer is below the level defined by the SPI_XFERLEVEL[AEL] bit field. A DMA Write request can be individually masked with the DMAW bit of the SPI_CHCONF register. The DMA Write request line asserts when the channel is enabled and the number of bytes held in the FIFO buffer is below the level defined by the SPI_XFERLEVEL[AEL] bit field. 8.2.7 Reset The module can be reset by software through the SoftReset bit of the SPI_SYSCONFIG register. The SPI_SYSCONFIG register is not sensitive to software reset. The SoftReset control bit is active high. The bit is automatically reset to 0 by the hardware. A global ResetDone status bit is provided in the SPI_SYSCONFIG status register. The global ResetDone status bit can be monitored by the software to check if the module is ready to use following a reset. 8.3 Initialization and Configuration This section describes a GSPI module initialization and configuration example for each of the two basic modes supported to transmit and receive at 100000 KHz. 8.3.1 Basic Initialization (a) Enable the SPI module clock by invoking following API: PRCMPeripheralClkEnable(PRCM_GSPI,PRCM_RUN_MODE_CLK) (b) Set the pinmux to bring out the SPI signals to the chip boundary at desired location using: PinTypeSPI(, ). (c) Soft reset the module: SPIReset(GSPI_BASE) 8.3.2 Master Mode Operation without Interrupt (Polling) (a) Configure the SPI with following parameters: • Mode: 4-Pin/Master • Sub mode: 0 • Bit Rate: 100000 Hz • Chip Select: Software controlled/Active High • Word Length: 8 bits SPIConfigSetExpClk(GSPI_BASE,PRCMPeripheralClockGet(PRCM_GSPI), 100000, SPI_MODE_MASTER, SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE|SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_8)) (b) Enable SPI channel for communication: SPIEnable(GSPI_BASE) (c) Enable Chip Select: SPICSEnable(GSPI_BASE) (d) Write new data into TX FIFO to transmit it over the interface: 236 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPIDataPut(GSPI_BASE,); (e) Read received data from the RX FIFO: SPIDataGet(GSPI_BASE,&) (f) Disable Chip Select: SPICSDisable(GSPI_BASE) Initialization and Configuration 8.3.3 Slave Mode Operation with Interrupt (a) Set the Interrupt vector table base and enable master interrupt for NVIC: IntVTableBaseSet( )IntMasterEnable() (b) Configure the SPI with following parameters: • Mode: 4-Pin/Slave • Word Length: 8 bits SPIConfigSetExpClk(GSPI_BASE,PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE, SPI_MODE_SLAVE, SPI_SUB_MODE_0, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_8)) (c) Register the interrupt handler: SPIIntRegister(GSPI_BASE, ) (d) Enable the transmit empty and receive full interrupts: SPIIntEnable(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY) (e) Enable SPI channel for communication: SPIEnable(GSPI_BASE) 8.3.4 Generic Interrupt Handler Implementation void SlaveIntHandler() { unsigned long ulDummy; unsigned long ulStatus; // Read the interrupt status ulStatus = SPIIntStatus(GSPI_BASE,true); // Acknowledge the interrupts SPIIntClear(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY); // If TX empty, write a new data into SPI register if(ulStatus & SPI_INT_TX_EMPTY) { SPIDataPut(GSPI_BASE, ) } // if RX is full, readout the data from SPI if(ulStatus & SPI_INT_RX_FULL) { SPIDataGetNonBlocking(GSPI_BASE, &ulDummy); } } SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 237 Access to Data Registers www.ti.com 8.4 Access to Data Registers This section describes the supported data accesses (read or write) from/to the data receiver registers SPI_RX and data transmitter registers SPI_TX. SPI supports only one SPI word per register (receiver or transmitter) and does not support successive 8bit or 16-bit accesses for a single SPI word. The SPI word received is always right justified on the LSbit of the 32bit SPI_RX register, and the SPI word to transmit is always right justified on the LSbit of the 32bit SPI_TX register. The bits above SPI word length are ignored and the content of the data registers is not reset between the SPI data transfers. The coherence between the number of bits of the SPI Word, the number of bits of the access, and the enabled byte is the responsibility of the user. Only aligned accesses are supported. In Master mode, data should not be written in the transmit register when the channel is disabled. 8.5 Module Initialization Figure 8-13. Flow Chart - Module Initialization Before the ResetDone bit is set, the clocks CLK and CLKSPIREF must be provided to the module. To avoid hazardous behavior, reset the module before changing from MASTER mode to SLAVE mode or from SLAVE mode to MASTER mode. 8.5.1 Common Transfer Sequence SPI module allows the transfer of one or several words, according to different modes: • MASTER Normal, MASTER Turbo, SLAVE 238 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Module Initialization • TRANSMIT – RECEIVE • Write and read requests: Interrupts, DMA • SPIEN lines assertion/deassertion: automatic, manual For all these flows, the host process contains the main process and the interrupt routines. The interrupt routines are called on the interrupt signals or by an internal call if the module is used in polling mode. Figure 8-14 represents the main sequence common to all transfers. Figure 8-14. Flow Chart - Common Transfer Sequence 8.5.2 End of Transfer Sequences In these sequences, some soft variables are used: • write_count = 0 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 239 Module Initialization www.ti.com • read_count. = 0 • channel_enable = FALSE • last_transfer = FALSE • last_request = FALSE These variables are initialized before starting the channel. The executed transfer has size of ‘N’. If the requests are configured in DMA, write_count and read_count are assigned with ‘N’. Figure 8-15 highlights the interrupt routine executed for N times till write_count and read_count reached value ‘N’, after which the transfer is over and ‘main process’ disables the channel. Figure 8-15. Flow Chart - Transmit and Receive (Master and Slave) 8.5.3 FIFO Mode These flows describe the transfer with FIFO. The SPI module allows the transfer of one or several words, according to different modes: • MASTER Normal, MASTER Turbo, SLAVE • TRANSMIT – RECEIVE • Write and read requests: IRQ, DMA 240 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Module Initialization For each flow, the host process contains the main process and the interrupt routine. This routine is called on the IRQ signals or by an internal call if the module is used in polling mode. 8.5.3.1 Common Transfer Sequence In TRANSMIT/RECEIVE mode, the FIFO can be enabled for write or read request only. The SPI module starts the transfer only when the first write request is released by writing the SPI_TX register. See Figure 8-16. This first write request is managed by the IRQ routine or DMA handler. The sequence varies according to whether word count is used or not (SPI_XFERLEVEL : WCNT ≠ 0 or not). The AEL and/or AFL values can be different, but they must be a multiple of the word size in the FIFO: 1, 2 or 4 bytes according to word length. In these sequences, the transfer to execute has a size of N words. In these sequences, the numbers of word written or read for each write or read FIFO request are: • write_request_size • read_request_size. If they are not submultiples of N, the last request sizes are: • ast_write_request_size ( < write_request_size ) • last_read_request_size. ( < read_request_size) SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 241 Module Initialization www.ti.com Figure 8-16. Flow Chart - FIFO Mode Common Sequence (Master) In these sequences, some soft variables are used: • write_count = N • read_count = N • last_request = FALSE These variables are initialized before starting the channel. 8.5.3.2 Transmit Receive with Word Count Flow of a transfer in TRANSMIT – RECEIVE mode, with word count. 242 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Module Initialization Figure 8-17. Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master) 8.5.3.3 Transmit Receive without Word Count Flow of a transfer in TRANSMIT – RECEIVE mode, without word count. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 243 SPI Registers www.ti.com Figure 8-18. Flow Chart - FIFO Mode Transmit and Receive without Word Count (Master) 8.6 SPI Registers Table 8-6 lists the memory-mapped registers for the SPI. All register offset addresses not listed in Table 86 should be considered as reserved locations and the register contents should not be modified. 244 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Offset 10h 114h 118h 11Ch 128h 12Ch 130h 134h 138h 13Ch 17Ch Acronym SPI_SYSCONFIG SPI_SYSSTATUS SPI_IRQSTATUS SPI_IRQENABLE SPI_MODULCTRL SPI_CHCONF SPI_CHSTAT SPI_CHCTRL SPI_TX SPI_RX SPI_XFERLEVEL Table 8-6. SPI Registers Register Name System Configuration System Status Register Interrupt Status Register Interrupt Enable Register Module Control Register Channel Configuration Register Channel Status Register Channel Control Register Channel Transmitter Register Channel Receiver Register Transfer Levels Register 8.6.1 SPI Register Description The remainder of this section lists and describes the SPI registers. SPI Registers Section Section 8.6.1.1 Section 8.6.1.2 Section 8.6.1.3 Section 8.6.1.4 Section 8.6.1.5 Section 8.6.1.6 Section 8.6.1.7 Section 8.6.1.8 Section 8.6.1.9 Section 8.6.1.10 Section 8.6.1.11 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 245 SPI Registers 8.6.1.1 SPI_SYSCONFIG Register (offset = 10h) [reset = 0h] SPI_SYSCONFIG is shown in Figure 8-19 and described in Table 8-7. Clock management configuration. Figure 8-19. SPI_SYSCONFIG Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-1 0 Field RESERVED SOFTRESET Table 8-7. SPI_SYSCONFIG Register Field Descriptions Type R R/W Reset 0h 0h Description Software reset. (Optional) 0h (W) = No action 0h (R) = Reset done, no pending action 1h (W) = Initiate software reset 1h (R) = Reset (software or other) ongoing www.ti.com 24 16 8 0 SOFTRESET R/W-0h 246 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPI Registers 8.6.1.2 SPI_SYSSTATUS Register (offset = 114h) [reset = 0h] SPI_SYSSTATUS is shown in Figure 8-20 and described in Table 8-8. This register provides status information about the module excluding the interrupt status information. Figure 8-20. SPI_SYSSTATUS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 1 0 RESETDONE R-0h Bit 31-1 0 Field RESERVED RESETDONE Table 8-8. SPI_SYSSTATUS Register Field Descriptions Type R R Reset 0h 0h Description Internal Reset Monitoring 0h (R) = Internal module reset is on-going 1h (R) = Reset completed SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 247 SPI Registers www.ti.com 8.6.1.3 SPI_IRQSTATUS Register (offset = 118h) [reset = 0h] SPI_IRQSTATUS is shown in Figure 8-21 and described in Table 8-9. The interrupt status regroups all the status of the module internal events that can generate an interrupt. Figure 8-21. SPI_IRQSTATUS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED RX_OVERFLO W RX_FULL R-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 EOW R/W-0h 9 16 WKS R/W-0h 8 1 TX_UNDERFL OW R/W-0h 0 TX_EMPTY R/W-0h Bit 31-18 17 Field RESERVED EOW 16 WKS 15-4 3 RESERVED RX_OVERFLOW 2 RX_FULL Table 8-9. SPI_IRQSTATUS Register Field Descriptions Type R R/W R/W R R/W R/W Reset 0h 0h 0h 0h 0h 0h Description End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by SPI_XFERLEVEL[WCNT]. 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field SPI_CHCONF[SPIENSLV]. 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending Receiver register overflow (slave mode only). 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending Receiver register full or almost full. This bit indicate FIFO almost full status when built-in FIFO is use for receive register (SPI_CHCONF[FFER] is set). 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending 248 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPI Registers Table 8-9. SPI_IRQSTATUS Register Field Descriptions (continued) Bit Field 1 TX_UNDERFLOW 0 TX_EMPTY Type R/W R/W Reset 0h 0h Description Transmitter register underflow. 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending Transmitter register empty or almost empty. This bit indicate FIFO almost full status when built-in FIFO is use for transmit register (SPI_CHCONF[FFEW] is set). 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 249 SPI Registers www.ti.com 8.6.1.4 SPI_IRQENABLE Register (offset = 11Ch) [reset = 0h] SPI_IRQENABLE is shown in Figure 8-22 and described in Table 8-10. This register allows to enable/disable the module internal sources of interrupt, on an event-byevent basis. Figure 8-22. SPI_IRQENABLE Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED EOWE WKE R-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED RX_OVERFLO RX_FULL_ENA TX_UNDERFL TX_EMPTY_E W_ENABLE BLE OW_ENABLE NABLE R-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-18 17 16 15-4 3 2 1 0 Table 8-10. SPI_IRQENABLE Register Field Descriptions Field RESERVED EOWE WKE Type R R/W R/W RESERVED R RX_OVERFLOW_ENABL R/W E RX_FULL_ENABLE R/W TX_UNDERFLOW_ENAB R/W LE TX_EMPTY_ENABLE R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h Description End of Word count Interrupt Enable. 0h = Interrupt disabled 1h = Interrupt enabled Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field SPI_CHCONF[SPIENSLV] 0h = Interrupt disabled 1h = Interrupt enabled Receiver register Overflow Interrupt Enable. 0h = Interrupt disabled 1h = Interrupt enabled Receiver register Full or almost full Interrupt Enable. 0h = Interrupt disabled 1h = Interrupt enabled Transmitter register Underflow Interrupt Enable. 0h = Interrupt disabled 1h = Interrupt enabled Transmitter register Empty or almost empty Interrupt Enable. 0h = Interrupt disabled 1h = Interrupt enabled 250 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 8.6.1.5 SPI_MODULCTRL Register (offset = 128h) [reset = 4h] SPI_MODULCTRL is shown in Figure 8-23 and described in Table 8-11. This register is dedicated to the configuration of the serial port interface. Figure 8-23. SPI_MODULCTRL Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 RESERVED R-0h 5 4 RESERVED R-0h 3 2 MS R/W-1h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset SPI Registers 25 17 9 1 PIN34 R/W-0h 24 16 8 0 SINGLE R/W-0h Bit 31-8 7-3 2 Field RESERVED RESERVED MS 1 PIN34 0 SINGLE Table 8-11. SPI_MODULCTRL Register Field Descriptions Type R R R/W R/W R/W Reset 0h 0h 1h 0h 0h Description Master/ Slave 0h = Master - The module generates the SPICLK and SPIEN 1h = Slave - The module receives the SPICLK and SPIEN Pin mode selection: 3 wire vs 4 wire. This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO,SOMI and SPICLK clock pin for spi transfers. 0h = SPIEN is used as a chip select. 1h = SPIEN is not used. In this mode all related option to chip select have no meaning. Channel enable (master mode only) 1h = Channel will be used in master mode. This bit must be set in Force SPIEN mode. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 251 SPI Registers www.ti.com 8.6.1.6 SPI_CHCONF Register (offset = 12Ch) [reset = 60000h] SPI_CHCONF is shown in Figure 8-24 and described in Table 8-12. This register is dedicated to the configuration of the channel. The table below lists the allowed data lines configurations per channel. The user has the responsibility to program which data line to use and in which direction (receive or transmit), according to the single data pin or two pins interface mode shared with the external slave/master device. IS DPE1 DPE0 TRM (Transmit and Receive) 0 0 0 supported 0 0 1 supported 0 1 0 supported 0 1 1 NOT supported (unpredictable result) 1 0 0 supported 1 0 1 supported 1 1 0 supported 1 1 1 NOT supported (unpredictable result) 31 30 RESERVED R-0h 29 CLKG R/W-0h Figure 8-24. SPI_CHCONF Register 28 27 26 FFER FFEW R/W-0h R/W-0h 25 RESERVED R-0h 23 22 21 RESERVED R-0h 20 FORCE R/W-0h 19 TURBO R/W-0h 18 IS R/W-1h 17 DPE1 R/W-1h 15 14 13 12 11 10 9 DMAR DMARW TRM WL R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 WL EPOL R/W-0h R/W-0h 4 3 CLKD R/W-0h 2 1 POL R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 24 16 DPE0 R/W-0h 8 0 PHA R/W-0h Bit 31-30 29 Field RESERVED CLKG 28 FFER 27 FFEW 26-21 RESERVED Table 8-12. SPI_CHCONF Register Field Descriptions Type R R/W R/W R/W R Reset 0h 0h 0h 0h 0h Description Clock divider granularity. This register defines the granularity of channel clock divider: power of two or one clock cycle granularity. When this bit is set the register SPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then The clock divider ratio is a concatenation of SPI_CHCONF[CLKD] and SPI_CHCTRL[EXTCLK] values 0h = Clock granularity of power of two 1h = One clock cycle granularity FIFO enabled for receive: Only one channel can have this bit field set. 0h = The buffer is not used to receive data. 1h = The buffer is used to receive data. FIFO enabled for Transmit: Only one channel can have this bit field set. 0h = The buffer is not used to transmit data. 1h = The buffer is used to transmit data. 252 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPI Registers Bit 20 19 18 17 16 15 14 13-12 11-7 6 Field FORCE TURBO IS DPE1 DPE0 DMAR DMARW TRM WL EPOL Table 8-12. SPI_CHCONF Register Field Descriptions (continued) Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0h 0h 1h 1h 0h 0h 0h 0h 0h 0h Description Manual SPIEN assertion to keep SPIEN active between SPI words. (single channel master mode only) 0h = Writing 0 into this bit drives low the SPIEN line when SPI_CHCONF[EPOL] = 0, and drives it high when SPI_CHCONF[EPOL] = 1. 1h = Writing 1 into this bit drives high the SPIEN line when SPI_CHCONF[EPOL] = 0, and drives it low when SPI_CHCONF[EPOL] = 1 Turbo mode 0h = Turbo is deactivated (recommended for single SPI word transfer) 1h = Turbo is activated to maximize the throughput for multi SPI words transfer. Input Select 0h = Data Line0 (SPIDAT[0]) selected for reception. 1h = Data Line1 (SPIDAT[1]) selected for reception Transmission Enable for data line 1 0h = Data Line1 (SPIDAT[1]) selected for transmission 1h = No transmission on Data Line1 (SPIDAT[1]) Transmission Enable for data line 0 0h = Data Line0 (SPIDAT[0]) selected for transmission 1h = No transmission on Data Line0 (SPIDAT[0]) DMA Read request. The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA Read request line is deasserted on read completion of the receive register of the channel. 0h = DMA Read Request disabled 1h = DMA Read Request enabled DMA Write request. The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA Write request line is deasserted on load completion of the transmitter register of the channel. 0h = DMA Write Request disabled 1h = DMA Write Request enabled Transmit Receive modes 0h = Transmit and Receive mode SPI word length 7h = The SPI word is 8-bits long Fh = The SPI word is 16-bits long 1Fh = The SPI word is 32-bits long SPIEN polarity 0h = SPIEN is held high during the active state. 1h = SPIEN is held low during the active state. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 253 SPI Registers Bit Field 5-2 CLKD 1 POL 0 PHA www.ti.com Table 8-12. SPI_CHCONF Register Field Descriptions (continued) Type R/W R/W R/W Reset 0h 0h 0h Description Frequency divider for SPICLK. (Only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shiftout data. 0h = 1 1h = 2 2h = 4 3h = 8 4h = 16 5h = 32 6h = 64 7h = 128 8h = 256 9h = 512 Ah = 1024 Bh = 2048 Ch = 4096 Dh = 8192 Eh = 16384 Fh = 32768 SPICLK polarity 0h = SPICLK is held high during the active state 1h = SPICLK is held low during the active state SPICLK phase 0h = Data are latched on odd numbered edges of SPICLK. 1h = Data are latched on even numbered edges of SPICLK. 254 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPI Registers 8.6.1.7 SPI_CHSTAT Register (offset = 130h) [reset = 0h] SPI_CHSTAT is shown in Figure 8-25 and described in Table 8-13. This register provides status information about transmitter and receiver registers of channel. Figure 8-25. SPI_CHSTAT Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 RESERVED R-0h 6 RXFFF R-0h 5 RXFFE R-0h 4 TXFFF R-0h 3 TXFFE R-0h 2 EOT R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 TXS R-0h 24 16 8 0 RXS R-0h Bit 31-7 6 Field RESERVED RXFFF 5 RXFFE 4 TXFFF 3 TXFFE 2 EOT 1 TXS 0 RXS Table 8-13. SPI_CHSTAT Register Field Descriptions Type R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Channel FIFO Receive Buffer Full Status 0h (R) = FIFO Receive Buffer is not full 1h (R) = FIFO Receive Buffer is full Channel FIFO Receive Buffer Empty Status 0h (R) = FIFO Receive Buffer is not empty 1h (R) = FIFO Receive Buffer is empty Channel FIFO Transmit Buffer Full Status 0h (R) = FIFO Transmit Buffer is not full 1h (R) = FIFO Transmit Buffer is full Channel FIFO Transmit Buffer Empty Status 0h (R) = FIFO Transmit Buffer is not empty 1h (R) = FIFO Transmit Buffer is empty Channel End of transfer Status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (Turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an SPI transfer. Channel Transmitter Register Status 0h (R) = Register is full 1h (R) = Register is empty Channel Receiver Register Status 0h (R) = Register is empty 1h (R) = Register is full SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 255 SPI Registers www.ti.com 8.6.1.8 SPI_CHCTRL Register (offset = 134h) [reset = 0h] SPI_CHCTRL is shown in Figure 8-26 and described in Table 8-14. This register is dedicated to enable the channel and defines the extended clock ratio with one clock cycle granularity. Figure 8-26. SPI_CHCTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EXTCLK RESERVED R/W-0h R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 17 16 1 0 EN R/W0h Bit 31-16 15-8 Field RESERVED EXTCLK 7-1 RESERVED 0 EN Table 8-14. SPI_CHCTRL Register Field Descriptions Type R R/W R R/W Reset 0h 0h 0h 0h Description Clock Ratio Extension This register is used to concatenate with the SPI_CHCONF[CLKD] register for the clock ratio only when the granularity is one clock cycle (SPI_CHCONF[CLKG] set to 1). Then, the max value reached is 4096 clock divider ratio. 0h = Clock ratio is CLKD + 1 1h = Clock ratio is CLKD + 1 + 16 FFh = Clock ratio is CLKD + 1 + 4080 Channel Enable 0h = Channel is not active 1h = Channel is active 256 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SPI Registers 8.6.1.9 SPI_TX Register (offset = 138h) [reset = 0h] SPI_TX is shown in Figure 8-27 and described in Table 8-15. This register contains a single SPI word to transmit on the serial link, what ever SPI word length is. Note: see Chapter Access to data registers for the list of supported accesses; little endian host access SPI 8bit word on 0x00 while big endian host accesses it on 0x03. Figure 8-27. SPI_TX Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDATA R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field TDATA Table 8-15. SPI_TX Register Field Descriptions Type R/W Reset 0h Description Channel Data to transmit SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 257 SPI Registers www.ti.com 8.6.1.10 SPI_RX Register (offset = 13Ch) [reset = 0h] SPI_RX is shown in Figure 8-28 and described in Table 8-16. This register contains a single SPI word received through the serial link, what ever SPI word length is. Note: see Chapter Access to data registers for the list of supported accesses; little endian host access SPI 8bit word on 0x00 while big endian host accesses it on 0x03. Figure 8-28. SPI_RX Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field RDATA Table 8-16. SPI_RX Register Field Descriptions Type R Reset 0h Description Channel Received Data 258 SPI (Serial Peripheral Interface) SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 8.6.1.11 SPI_XFERLEVEL Register (offset = 17Ch) [reset = 0h] SPI_XFERLEVEL is shown in Figure 8-29 and described in Table 8-17. This register provides transfer levels needed while using FIFO buffer during transfer. SPI Registers Figure 8-29. SPI_XFERLEVEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WCNT AFL AEL R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-16 Field WCNT 15-8 AFL 7-0 AEL Table 8-17. SPI_XFERLEVEL Register Field Descriptions Type R/W R/W R/W Reset 0h 0h 0h Description Spi word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word transfer index. 0h = Counter not used 1h = One spi word FFFEh = 65534 spi word FFFFh = 65535 spi word Buffer Almost Full. This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer SPI_XFERLEVEL[AFL] must be set with n-1. 0h = One byte 1h = 2 bytes Fh = 16 bytes Buffer Almost Empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the buffer SPI_XFERLEVEL[AEL] must be set with n-1. 0h = One byte 1h = 2 bytes Fh = 16 bytes SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SPI (Serial Peripheral Interface) 259 Chapter 9 SWRU367B – June 2014 – Revised October 2014 General-Purpose Timers Topic ........................................................................................................................... Page 9.1 Overview ......................................................................................................... 261 9.2 Block Diagram.................................................................................................. 262 9.3 Functional Description ...................................................................................... 262 9.4 Initialization and Configuration .......................................................................... 270 9.5 TIMER Registers............................................................................................... 273 260 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 9.1 Overview Programmable timers can be used to count or time external events that drive the Timer input pins. The CC3200 General-Purpose Timer Module (GPTM) contains 16/32-bit GPTM blocks. Each 16/32-bit GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer. Timers can also be used to trigger μDMA transfers. The General-Purpose Timer Module (GPTM) contains four 16/32-bit GPTM blocks with the following functional options: ■ Operating modes: • 16- or 32-bit programmable one-shot timer. • 16- or 32-bit programmable periodic timer. • 16-bit general-purpose timer with an 8-bit prescaler. • 16-bit input-edge count- or time-capture modes with an 8-bit prescaler. • 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal. ■ Count up or down. ■ Sixteen 16/32-bit Capture Compare PWM pins (CCP). ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug. ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA): • Dedicated channel for each timer. • Burst request generated on timer interrupt. ■ Runs from System Clock (80MHz). SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 261 Block Diagram 9.2 Block Diagram Timer A Free-Running Output Value Configuration / Interrupt Timer A Interrupt Timer B Interrupt GPTMCFG GPTMCTL GPTMSYNC GPTMIMR GPTMRIS GPTMMIS GPTMICR GPTMDMAEV GPTMPP GPTMCC Timer B Free-Running Output Value www.ti.com Timer A Control GPTMTAPS GPTMTAPMR GPTMTAPR GPTMTAMATCHR GPTMTAILR GPTMTAMR 0xFFFF.FFFF (Up Counter Modes, 32-bit) 0x0000.0000 (Down Counter Modes, 32--bit) 0xFFFF (Up Counter Modes, 16--bit) 0x0000 (Down Counter Modes, 16-bit) TA Comparator GPTMTAR GPTMTAV Timer A Clk/Edge Detect Even CCP Pin GPTTRIGSEL Timer B GPTMTBMR GPTMTBILR GPTMTBMATCHR GPTMTBPR GPTMTBPMR GPTMTBPS Timer B Control GPTMTBV GPTMTBR TB Comparator Clk/Edge Detect Odd CCP Pin 0xFFFF.FFFF (Up Counter Modes, 32--bit) 0x0000.0000 (Down Counter Modes, 32-bit) 0xFFFF (Up Counter Modes, 16-bit) 0x0000 (Down Counter Modes, 16-bit) Figure 9-1. GPTM Module Block Diagram Timer 16/32-Bit Timer 0 16/32-Bit Timer 1 16/32-Bit Timer 2 16/32-Bit Timer 3 Table 9-1. Available CCP Pins and PWM Outputs/Signals Pins Up/Down Counter Timer A Timer B Timer A Timer B Timer A Timer B Timer A Timer B Even CCP Pin GT_CCP00 GT_CCP02 GT_CCP04 GT_CCP06 - Odd CCP Pin - GT_CCP01 - GT_CCP03 - GT_CCP05 - GT_CCP07 PWM Outputs/Signals PWM_OUT0 PWM_OUT1 PWM_OUT2 PWM_OUT3 PWM_OUT5 PWM_OUT6 PWM_OUT7 The GP Timer signals pin muxed and CONFMODE bits in the GPIO PAD CONFIG register should be set to choose the GP Timer function. 9.3 Functional Description The main components of each GPTM block are two free-running up/down counters (referred to as Timer A and Timer B), two prescaler registers, two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Timer A and Timer B can be used individually, in which case they have a 16-bit counting range for the 16/32-bit GPTM blocks. In addition, Timer A and Timer B can be concatenated to provide a 32-bit counting range for the 16/32-bit GPTM blocks. NOTE: The prescaler can only be used when the timers are used individually. 262 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description The available modes for each GPTM block are shown in Table 9-2. Note that when counting down in oneshot or periodic modes, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up in one-shot or periodic modes, the prescaler acts as a timer extension and holds the most-significant bits of the count. In input edge count, input edge time and PWM mode, the prescaler always acts as a timer extension, regardless of the count direction. Mode One-shot Periodic Edge Count Edge Time PWM Table 9-2. General-Purpose Timer Capabilities Timer Use Individual Concatenated Individual Concatenated Individual Individual Individual Count Direction Up or Down Up or Down Up or Down Up or Down Up or Down Up or Down Down Counter Size 16-bit 32-bit 16-bit 32-bit 16-bit 16-bit 16-bit Prescaler Sizea 8-bit 8-bit 8-bit 8-bit 8-bit a. The prescaler is only available when the timers are used individually Software configures the GPTM using the GPTM Configuration (GPTMCFG) register, the GPTM Timer A Mode (GPTMTAMR) register, and the GPTM Timer B Mode (GPTMTBMR) register. When in one of the concatenated modes, Timer A and Timer B can only operate in one mode. However, when configured in an individual mode, Timer A and Timer B can be independently configured in any combination of the individual modes. 9.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all 1s, along with their corresponding registers: ■ Load Registers: • GPTM Timer A Interval Load (GPTMTAILR) register • GPTM Timer B Interval Load (GPTMTBILR) register ■ Shadow Registers: • GPTM Timer A Value (GPTMTAV) register • GPTM Timer B Value (GPTMTBV) register The following prescale counters are initialized to all 0s: • GPTM Timer A Prescale (GPTMTAPR) register • GPTM Timer B Prescale (GPTMTBPR) register • GPTM Timer A Prescale Snapshot (GPTMTAPS) register • GPTM Timer B Prescale Snapshot (GPTMTBPS) register 9.3.2 Timer Modes This section describes the operation of the various timer modes. When using Timer A and Timer B in concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register. In the following sections, the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer n Prescale (GPTMTnPR) registers. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 263 Functional Description www.ti.com 9.3.2.1 One-Shot/Periodic Timer Mode The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTM Timer n Mode (GPTMTnMR) register. The timer is configured to count up or down using the TnCDIR bit in the GPTMTnMR register. When software sets the TnEN bit in the GPTM Control (GPTMCTL) register, the timer begins counting up from 0x0 or down from its preloaded value Table 9-3 on shows the values that are loaded into the timer registers when the timer is enabled. Table 9-3. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes Register GPTMTnR GPTMTnV GPTMTnPS Count Down Mode GPTMTnILR GPTMTnILR in concatenated mode; GPTMTnPR in combination with GPTMTnILR in individual mode. GPTMTnPR in individual mode; not available in concatenated mode. Count Up Mode 0x0 0x0 0x0 in individual mode; not available in concatenated mode. When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, the timer starts counting again on the next cycle. In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR register, the value of the timer at the time-out event is loaded into the GPTMTnR register and the value of the prescaler is loaded into the GPTMTnPS register. The free-running counter value is shown in the GPTMTnV register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR entry by examining the snapshot values and the current value of the free-running timer. Snapshot mode is not available when the timer is configured in one-shot mode. In addition to reloading the count value, the GPTM can generate interrupts, CCP outputs and triggers when it reaches the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the TnTOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. The time-out interrupt can be disabled entirely by setting the TACINTD bit in the GPTM Timer n Mode (GPTMTnMR) register. In this case, the TnTORIS bit does not even set in the GPTMRIS register. By setting the TnMIE bit in the GPTMTnMR register, an interrupt condition can also be generated when the Timer value equals the value loaded into the GPTM Timer n Match (GPTMTnMATCHR) and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the time-out interrupt, but uses the match interrupt bits instead (for example, the raw interrupt status is monitored via TnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register. Note that the interrupt status bits are not updated by the hardware unless the TnMIE bit in the GPTMTnMR register is set, which is different than the behavior for the time-out interruptThe μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel as well as the type of trigger enable in the GPTM DMA Event (GPTMDMAEV) register. If software updates the GPTMTnILR or the GPTMTnPR register while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting from the new value if the TnILD bit in the GPTMTnMR register is clear. If the TnILD bit is set, the counter loads the new value after the next timeout. If software updates the GPTMTnILR or the GPTMTnPR register while the counter is counting up, the timeout event is changed on the next cycle to the new value. If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value. If software updates the GPTMTnMATCHR or the GPTMTnPMR registers, the new values are reflected on the next clock cycle if the TnMRSU bit in the GPTMTnMR register is clear. If the TnMRSU bit is set, the new value will not take effect until the next timeout. 264 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description If the TnSTALL bit in the GPTMCTL register is set the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. All values assume a 80-MHz clock with Tc=12.5 ns (clock period). The prescaler can only be used when a 16/32-bit timer is configured in 16-bit mode. Table 9-4. 16-Bit Timer With Prescaler Configurations Prescale (8-bit value) 00000000 00000001 00000010 -----------11111101 11111110 11111111 # of Timer Clocks (Tc)a 1 2 3 -- 254 255 256 Max Time 0.8192 1.6384 2.4576 -- 208.0768 208.896 209.7152 Units ms ms ms -ms ms ms a. Tc is the clock period. 9.3.2.2 Input Edge-Count Mode NOTE: For rising-edge detection, the input signal must be High for at least two clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the frequency. In Edge-Count mode, the timer is configured as a 24-bit up- or down-counter including the optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR. Table 9-5 shows the values that are loaded into the timer registers when the timer is enabled. Table 9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode Register GPTMTnR GPTMTnV Count Down Mode GPTMTnPR in combination with GPTMTnILR GPTMTnPR in combination with GPTMTnILR Count Up Mode 0x0 0x0 When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements or increments the counter by 1 until the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match interrupt is enabled in SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 265 Functional Description www.ti.com the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnMMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In up-count mode, the current count of the input events is held in both the GPTMTnR and GPTMTnV registers. In down-count mode, the current count of the input events can be obtained by subtracting the GPTMTnR or GPTMTnV from the value made up of the GPTMTnPR and GPTMTnILR register combination. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel as well as the type of trigger enable in the GPTM DMA Event (GPTMDMAEV) register. After the match value is reached in down-count mode, the counter is then reloaded using the value in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0 and continues counting. Figure 9-2 shows how Input Edge-Count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted because the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. Figure 9-2. Input Edge-Count Mode Example, Counting Down 9.3.2.3 Input Edge-Time Mode NOTE: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. In Edge-Time mode, the timer is configured as a 24-bit up- or down-counter including the optional prescaler with the upper timer value stored in the GPTMTnPR register and the lower bits in the GPTMTnILR register. In this mode, the timer is initialized to the value loaded in the GPTMTnILR and GPTMTnPR registers when counting down and 0x0 when counting up. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. Table 9-6 shows the values that are loaded into the timer registers when the timer is enabled. One also needs to set TRIGSEL bits of the register GPTTRIGSEL to detect GPIO triggers. 266 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Table 9-6. Counter Values When the Timer is Enabled in Input Event-Count Mode Register TnR TnV Count Down Mode GPTMTnILR GPTMTnILR Count Up Mode 0x0 0x0 When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnR and GPTMTnPS register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR and GPTMTnPS registers hold the time at which the selected input event occurred while the GPTMTnV register holds the freerunning timer value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, a μDMA trigger can be generated.. The μDMA trigger is enabled by configuring the appropriate μDMA channel as well as the type of trigger selected in the GPTM DMA Event (GPTMDMAEV) register. After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count mode and the value from the GPTMTnILR and GPTMTnPR registers in down-count mode. Figure 9-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR and GPTMTnPS registers, and is held there until another rising edge is detected (at which point the new count value is loaded into the GPTMTnR and GPTMTnPS registers). Figure 9-3. 16-Bit Input Edge-Time Mode Example Note: When operating in Edge-time mode, the counter uses a modulo 224 count if prescaler is enabled or 216, if not. If there is a possibility the edge could take longer than the count, then another timer configured in periodic-timer mode can be implemented to ensure detection of the missed edge. The periodic timer should be configured in such a way that: • The periodic timer cycles at the same rate as the edge-time timer. • The periodic timer interrupt has a higher interrupt priority than the edge-time timeout interrupt. • If the periodic timer interrupt service routine is entered, software must check if an edge-time interrupt is pending and if it is, the value of the counter must be subtracted by 1 before being used to calculate the snapshot time of the event. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 267 Functional Description www.ti.com 9.3.2.4 PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 24-bit down-counter with a start value (and thus period) defined by the GPTMTnILR and GPTMTnPR registers. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. Table 9-7 shows the values that are loaded into the timer registers when the timer is enabled. Table 9-7. Counter Values When the Timer is Enabled in PWM Mode Register GPTMTnR GPTMTnV Count Down Mode GPTMTnILR GPTMTnILR Count Up Mode Not available Not available When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its start value from the GPTMTnILR and GPTMTnPR registers and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. The timer is capable of generating interrupts based on three types of events: rising edge, falling edge, or both. The event is configured by the TnEVENT field of the GPTMCTL register, and the interrupt is enabled by setting the TnPWMIE bit in the GPTMTnMR register. When the event occurs, the CnERIS bit is set in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. Note that the interrupt status bits are not updated unless the TnPWMIE bit is set. In addition, when the TnPWMIE bit is set and a capture event occurs, the Timer automatically generates triggers to the DMA if the trigger capability is enabled by setting the TnOTE bit in the GPTMCTL register and the CnEDMAEN bit in the GPTMDMAEV register, respectively. In this mode, the GPTMTnR and GPTMTnV registers always have the same value. The output PWM signal asserts when the counter is at the value of the GPTMTnILR and GPTMTnPR registers (its start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR and GPTMTnPMR registers. Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. NOTE: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is GPTMTnMATCHR=0x411A. 268 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 9-4. 16-Bit PWM Mode Example 9.3.3 DMA Operation The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA controller. Pulse requests are generated by a timer via its own dma_req signal. A dma_done signal is provided from the µDMA to each timer to indicate transfer completion and trigger a µDMA done interrupt (DMAnRIS) in the GPTM Raw Interrupt Status Register (GPTMRIS) register. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. The arbitration size of the μDMA transfer should be set to the amount of data that should be transferred whenever a timer event occurs. For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of 8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items have been transferred. A GPTM DMA Event (GPTMDMAEV) register is provided to enable the types of events that can cause a dma_req signal assertion by the timer module. Application software can enable a dma_req trigger for a match, capture or time-out event for each timer using the GPTMDMAEV register. For an individual timer, all active timer trigger events that have been enabled through the GPTMDMAEV register are ORed together to create a single dma_req pulse that is sent to the µDMA. When the µDMA transfer has completed, a dma_done signal is sent to the timer resulting in a DMAnRIS bit set in the GPTMRIS register. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values The GPTM is placed into concatenated mode by writing a 0x0 to the GPTMCFG bit field in the GPTM Configuration (GPTMCFG) register. In this configuration, certain 16/32-bit GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: • GPTM Timer A Interval Load (GPTMTAILR) register [15:0] • GPTM Timer B Interval Load (GPTMTBILR) register [15:0] • GPTM Timer A (GPTMTAR) register [15:0] • GPTM Timer B (GPTMTBR) register [15:0] • GPTM Timer A Value (GPTMTAV) register [15:0] • GPTM Timer B Value (GPTMTBV) register [15:0] • GPTM Timer A Match (GPTMTAMATCHR) register [15:0] • GPTM Timer B Match (GPTMTBMATCHR) register [15:0] SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 269 Initialization and Configuration www.ti.com In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] A 32-bit read access to GPTMTAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0] 9.4 Initialization and Configuration To use a GPTM, the appropriate CLKEN bit must be set in the GPTnCLKCFG/GPTnCLKEN register. Configure the CONFMODE fields in the GPIO_PAD_CONFIG register to assign the CCP signals to the appropriate pins. The user should set GPTTRIGSEL bits appropriately before using CCP mode. One can also reset GPTM blocks using register GPTnSWRST. This section shows module initialization and configuration examples for each of the supported timer modes. 9.4.1 One-Shot/Periodic Timer Mode The GPTM is configured for One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000. 3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR): (a) Write a value of 0x1 for One-Shot mode. (b) Write a value of 0x2 for Periodic mode. 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting. 8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register (GPTMICR). If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To reenable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event. 9.4.2 Input Edge-Count Mode A timer is configured to Input Edge-Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Program registers according to count direction: • In down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the 270 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Initialization and Configuration GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. • In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note that when executing an up-count, the value of GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR. 6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 8. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat Step #4 through #9. 9.4.3 Input Edge Time Mode A timer is configured to Input Edge Time mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3 and select a count direction by programming the TnCDIR bit. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register (GPTMTnPR). 6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 9. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timer n (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register and clearing the TnILD bit in the GPTMTnMR register. The change takes effect at the next cycle after the write. 9.4.4 PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register (GPTMTnPR). 6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted. 7. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 271 Initialization and Configuration www.ti.com 9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. 272 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5 TIMER Registers Table 9-8 lists the memory-mapped registers for the TIMER. All register offset addresses not listed in Table 9-8 should be considered as reserved locations and the register contents should not be modified. Offset 0h 4h 8h Ch 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 6Ch Acronym GPTMCFG GPTMTAMR GPTMTBMR GPTMCTL GPTMIMR GPTMRIS GPTMMIS GPTMICR GPTMTAILR GPTMTBILR GPTMTAMATCHR GPTMTBMATCHR GPTMTAPR GPTMTBPR GPTMTAPMR GPTMTBPMR GPTMTAR GPTMTBR GPTMTAV GPTMTBV GPTMDMAEV Table 9-8. TIMER Registers Register Name GPTM Configuration GPTM Timer A Mode GPTM Timer B Mode GPTM Control GPTM Interrupt Mask GPTM Raw Interrupt Status GPTM Masked Interrupt Status GPTM Interrupt Clear GPTM Timer A Interval Load GPTM Timer B Interval Load GPTM Timer A Match GPTM Timer B Match GPTM Timer A Prescale GPTM Timer B Prescale GPTM TimerA Prescale Match GPTM TimerB Prescale Match GPTM Timer A GPTM Timer B GPTM Timer A Value GPTM Timer B Value GPTM DMA Event Section Section 9.5.1.1 Section 9.5.1.2 Section 9.5.1.3 Section 9.5.1.4 Section 9.5.1.5 Section 9.5.1.6 Section 9.5.1.7 Section 9.5.1.8 Section 9.5.1.9 Section 9.5.1.10 Section 9.5.1.11 Section 9.5.1.12 Section 9.5.1.13 Section 9.5.1.14 Section 9.5.1.15 Section 9.5.1.16 Section 9.5.1.17 Section 9.5.1.18 Section 9.5.1.19 Section 9.5.1.20 Section 9.5.1.21 9.5.1 GPT Register Description The remainder of this section lists and describes the GPT registers, in numerical order by address offset. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 273 TIMER Registers www.ti.com 9.5.1.1 GPTMCFG Register (offset = 0h) [reset = 0h] GPTMCFG is shown in Figure 9-5 and described in Table 9-9. This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. Important: Bits in this register should only be changed when the TAEN and TBEN bits in the GPTMCTL register are cleared. Figure 9-5. GPTMCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GPTMCFG R-0h R/W-0h Bit 31-3 2-0 Field RESERVED GPTMCFG Table 9-9. GPTMCFG Register Field Descriptions Type R R/W Reset 0h 0h Description GPTM Configuration The GPTMCFG values are defined as follows: 1h-3h = Reserved 5h - 7h = Reserved 0h = For a 16/32-bit timer, this value selects the 32-bit timer configuration. 4h = For a 16/32-bit timer, this value selects the 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 274 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.2 GPTMTAMR Register (offset = 4h) [reset = 0h] GPTMTAMR is shown in Figure 9-6 and described in Table 9-10. This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2. 31 30 29 23 22 21 15 14 13 RESERVED R-0h 7 6 RESERVED R-0h 5 TAMIE R/W-0h Figure 9-6. GPTMTAMR Register 28 27 26 RESERVED R-0h 20 19 18 RESERVED R-0h 12 11 10 TAPLO TAMRSU R/W-0h R/W-0h 4 TACDIR R/W-0h 3 TAAMS R/W-0h 2 TACMIR R/W-0h 25 24 17 16 9 TAPWMIE R/W-0h 8 TAILD R/W-0h 1 0 TAMR R/W-0h Bit 31-12 11 Field RESERVED TAPLO 10 TAMRSU 9 TAPWMIE Table 9-10. GPTMTAMR Register Field Descriptions Type R R/W R/W R/W Reset 0h 0h 0h 0h Description GPTM Timer A PWM Legacy Operation 0h = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0. 1h = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0. GPTM Timer A Match Register Update If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit. 0h = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next cycle. 1h = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next timeout. GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the TAEVENT field in the GPTMCTL register. In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the TAOTE bit in the GPTMCTL register and the CAEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event interrupt is enabled. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 275 TIMER Registers www.ti.com Table 9-10. GPTMTAMR Register Field Descriptions (continued) Bit Field 8 TAILD 7-6 RESERVED 5 TAMIE 4 TACDIR 3 TAAMS 2 TACMIR 1-0 TAMR Type R/W R R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description GPTM Timer A Interval Load Write Note the state of this bit has no effect when counting up. The bit descriptions above apply if the timer is enabled and running. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR GPTMTAV and GPTMTAPs, are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAR and GPTMTAPS are updated according to the configuration of this bit. 0h = Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next cycle. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1h = Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next timeout. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next timeout. GPTM Timer A Match Interrupt Enable 0h = The match interrupt is disabled for match events. Additionally, triggers to the DMA on match events are prevented. 1h = An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes. GPTM Timer A Count Direction When in PWM mode, the status of this bit is ignored. PWM mode always counts down. 0h = The timer counts down. 1h = The timer counts up. When counting up, the timer starts from a value of 0x0. GPTM Timer A Alternate Mode Select The TAAMS values are defined as follows: Note: To enable PWM mode, clear the TACMR bit and configure the TAMR field to 0x1 or 0x2. 0h = Capture or compare mode is enabled. 1h = PWM mode is enabled. GPTM Timer A Capture Mode The TACMR values are defined as follows: 0h = Edge-Count mode 1h = Edge-Time mode GPTM Timer A Mode The TAMR values are defined as follows: The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-Shot Timer mode 2h = Periodic Timer mode 3h = Capture mode 276 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.3 GPTMTBMR Register (offset = 8h) [reset = 0h] GPTMTBMR is shown in Figure 9-7 and described in Table 9-11. This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored and GPTMTAMR controls the modes for both Timer A and Timer B. Note: Except for the TCACT bit field, all other bits in this register should only be changed when the TBEN bit in the GPTMCTL register is cleared. 31 30 29 23 22 21 15 14 13 RESERVED R-0h 7 6 RESERVED R-0h 5 TBMIE R/W-0h Figure 9-7. GPTMTBMR Register 28 27 26 RESERVED R-0h 20 19 18 RESERVED R-0h 12 11 10 TBPLO TBMRSU R/W-0h R/W-0h 4 TBCDIR R/W-0h 3 TBAMS R/W-0h 2 TBCMR R/W-0h 25 24 17 16 9 TBPWMIE R/W-0h 8 TBILD R/W-0h 1 0 TBMR R/W-0h Bit 31-12 11 Field RESERVED TBPLO 10 TBMRSU 9 TBPWMIE Table 9-11. GPTMTBMR Register Field Descriptions Type R R/W R/W R/W Reset 0h 0h 0h 0h Description Timer B PWM Legacy Operation This bit is only valid in PWM mode. 0h = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0. 1h = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0. GPTM Timer B Match Register Update If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBMATCHR and GPTMTBPR are updated when the timer is enabled. If the timer is stalled (TBSTALL is set), GPTMTBMATCHR and GPTMTBPR are updated according to the configuration of this bit. 0h = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next cycle. 1h = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next timeout. GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output as defined by the TBEVENT field in the GPTMCTL register. In addition, when this bit is set and a capture event occurs, Timer B automatically generates triggers to the ADC and DMA if the trigger capability is enabled by setting the TBOTE bit in the GPTMCTL register and the CBEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event is enabled. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 277 TIMER Registers www.ti.com Table 9-11. GPTMTBMR Register Field Descriptions (continued) Bit Field 8 TBILD 7-6 RESERVED 5 TBMIE 4 TBCDIR 3 TBAMS 2 TBCMR 1-0 TBMR Type R/W R R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description GPTM Timer B Interval Load Write Note the state of this bit has no effect when counting up. The bit descriptions above apply if the timer is enabled and running. If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR, GPTMTBV and are updated when the timer is enabled. If the timer is stalled (TBSTALL is set), GPTMTBR and GPTMTBPS are updated according to the configuration of this bit. 0h = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next cycle. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next cycle. 1h = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next timeout. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next timeout. GPTM Timer B Match Interrupt Enable 0h = The match interrupt is disabled for match events. Additionally, triggers to the DMA on match events are prevented. 1h = An interrupt is generated when the match value in the GPTMTBMATCHR register is reached in the one-shot and periodic modes. GPTM Timer B Count Direction 0h = The timer counts down.1h = The timer counts up. When counting up, the timer starts from a value of 0x0.When in PWM mode, the status of this bit is ignored. PWM mode always counts down GPTM Timer B Alternate Mode Select The TBAMS values are defined as follows: Note: To enable PWM mode, clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2. 0h = Capture or compare mode is enabled. 1h = PWM mode is enabled. GPTM Timer B Capture Mode The TBCMR values are defined as follows: 0h = Edge-Count mode 1h = Edge-Time mode GPTM Timer B Mode The TBMR values are defined as follows: The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-Shot Timer mode 2h = Periodic Timer mode 3h = Capture mode 278 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.5.1.4 GPTMCTL Register (offset = Ch) [reset = 0h] GPTMCTL is shown in Figure 9-8 and described in Table 9-12. 31 30 23 22 15 RESERVED R-0h 7 RESERVED R-0h 14 TBPWML R/W-0h 6 TAPWML R/W-0h Figure 9-8. GPTMCTL Register 29 28 27 26 RESERVED R-0h 21 20 19 18 RESERVED R-0h 13 12 RESERVED R-0h 11 10 TBEVENT R/W-0h 5 4 RESERVED R-0h 3 2 TAEVENT R/W-0h TIMER Registers 25 24 17 16 9 TBSTALL R/W-0h 1 TASTALL R/W-0h 8 TBEN R/W-0h 0 TAEN R/W-0h Bit 31-15 14 Field RESERVED TBPWML 13-12 11-10 RESERVED TBEVENT 9 TBSTALL 8 TBEN 7 RESERVED 6 TAPWML 5-4 RESERVED Table 9-12. GPTMCTL Register Field Descriptions Type R R/W R R/W R/W R/W R R/W R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description GPTM Timer B PWM Output Level The TBPWML values are defined as follows: 0h = Output is unaffected. 1h = Output is inverted. GPTM Timer B Event Mode The TBEVENT values are defined as follows: Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 0h = Positive edge 1h = Negative edge 2h = Reserved 3h = Both edges GPTM Timer B Stall Enable The TBSTALL values are defined as follows: If the processor is executing normally, the TBSTALL bit is ignored. 0h = Timer B continues counting while the processor is halted by the debugger. 1h = Timer B freezes counting while the processor is halted by the debugger. GPTM Timer B Enable The TBEN values are defined as follows: 0h = Timer B is disabled. 1h = Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. GPTM Timer A PWM Output Level The TAPWML values are defined as follows: 0h = Output is unaffected. 1h = Output is inverted. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 279 TIMER Registers www.ti.com Table 9-12. GPTMCTL Register Field Descriptions (continued) Bit Field 3-2 TAEVENT 1 TASTALL 0 TAEN Type R/W R/W R/W Reset 0h 0h 0h Description GPTM Timer A Event Mode The TAEVENT values are defined as follows: Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 0h = Positive edge 1h = Negative edge 2h = Reserved 3h = Both edges GPTM Timer A Stall Enable The TASTALL values are defined as follows: If the processor is executing normally, the TASTALL bit is ignored. 0h = Timer A continues counting while the processor is halted by the debugger. 1h = Timer A freezes counting while the processor is halted by the debugger. GPTM Timer A Enable The TAEN values are defined as follows: 0h = Timer A is disabled. 1h = Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 280 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.5 GPTMIMR Register (offset = 18h) [reset = 0h] Register mask: 0h GPTMIMR is shown in Figure 9-9 and described in Table 9-13. This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. 31 30 23 22 15 14 RESERVED R-X 7 6 RESERVED R-X 29 21 13 DMABIM R/W-X 5 DMAAIM R/W-X Figure 9-9. GPTMIMR Register 28 27 26 RESERVED R-X 20 19 18 RESERVED R-X 12 RESERVED R-X 11 TBMIM R/W-X 10 CBEIM R/W-X 4 TAMIM R/W-X 3 RESERVED R-X 2 CAEIM R/W-X 25 17 9 CBMIM R/W-X 1 CAMIM R/W-X 24 16 8 TBTOIM R/W-X 0 TATOIM R/W-X Bit 31-14 13 Field RESERVED DMABIM 12 RESERVED 11 TBMIM 10 CBEIM 9 CBMIM 8 TBTOIM 7-6 RESERVED 5 DMAAIM Table 9-13. GPTMIMR Register Field Descriptions Type R R/W R R/W R/W R/W R/W R R/W Reset X X X X X X X X X Description GPTM Timer B DMA Done Interrupt Mask The DMABIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer B Match Interrupt Mask The TBMIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer B Capture Mode Event Interrupt Mask The CBEIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer B Capture Mode Match Interrupt Mask The CBMIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer B Time-Out Interrupt Mask The TBTOIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer A DMA Done Interrupt Mask The DMAAIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 281 TIMER Registers www.ti.com Table 9-13. GPTMIMR Register Field Descriptions (continued) Bit Field 4 TAMIM 3 RESERVED 2 CAEIM 1 CAMIM 0 TATOIM Type R/W R R/W R/W R/W Reset X X X X X Description GPTM Timer A Match Interrupt Mask The TAMIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer A Capture Mode Event Interrupt Mask The CAEIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer A Capture Mode Match Interrupt Mask The CAMIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. 282 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.5.1.6 GPTMRIS Register (offset = 1Ch) [reset = 0h] Register mask: 0h GPTMRIS is shown in Figure 9-10 and described in Table 9-14. 31 30 23 22 15 14 RESERVED R-X 7 6 RESERVED R-X 29 21 13 DMABRIS R-X 5 DMAARIS R-X Figure 9-10. GPTMRIS Register 28 27 26 RESERVED R-X 20 19 18 RESERVED R-X 12 RESERVED R-X 11 TBMRIS R-X 10 CBERIS R-X 4 TAMRIS R-X 3 RESERVED R-X 2 CAERIS R-X TIMER Registers 25 24 17 16 9 CBMRIS R-X 1 CAMRIS R-X 8 TBTORIS R-X 0 TATORIS R-X Bit 31-14 13 Field RESERVED DMABRIS 12 RESERVED 11 TBMRIS 10 CBERIS 9 CBMRIS 8 TBTORIS 7-6 RESERVED 5 DMAARIS Table 9-14. GPTMRIS Register Field Descriptions Type R R R R R R R R R Reset X X X X X X X X X Description GPTM Timer B DMA Done Raw Interrupt Status 0h = The Timer B DMA transfer has not completed. 1h = The Timer B DMA transfer has completed. GPTM Timer B Match Raw Interrupt This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 0h = The match value has not been reached. 1h = The TBMIE bit is set in the GPTMTBMR register, and the match values in the GPTMTBMATCHR and (optionally) GPTMTBPMR registers have been reached when configured in oneshot or periodic mode. GPTM Timer B Capture Mode Event Raw Interrupt This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 0h = The capture mode event for Timer B has not occurred. 1h = A capture mode event has occurred for Timer B. This interrupt asserts when the subtimer is configured in Input Edge-Time mode. GPTM Timer B Capture Mode Match Raw Interrupt This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. 0h = The capture mode match for Timer B has not occurred. 1h = The capture mode match has occurred for Timer B. This interrupt asserts when the values in the GPTMTBR and GPTMTBPR match the values in the GPTMTBMATCHR and GPTMTBPMR when configured in Input Edge-Time mode. GPTM Timer B Time-Out Raw Interrupt This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 0h = Timer B has not timed out. 1h = Timer B has timed out. This interrupt is asserted when a oneshot or periodic mode timer reaches it's count limit (0 or the value loaded into GPTMTBILR, depending on the count direction). GPTM Timer A DMA Done Raw Interrupt Status 0h = The Timer A DMA transfer has not completed. 1h = The Timer A DMA transfer has completed. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 283 TIMER Registers www.ti.com Table 9-14. GPTMRIS Register Field Descriptions (continued) Bit Field 4 TAMRIS 3 RESERVED 2 CAERIS 1 CAMRIS 0 TATORIS Type R R R R R Reset X X X X X Description GPTM Timer A Match Raw Interrupt This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 0h = The match value has not been reached. 1h = The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR and (optionally) GPTMTAPMR registers have been reached when configured in oneshot or periodic mode. GPTM Timer A Capture Mode Event Raw Interrupt This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. 0h = The capture mode event for Timer A has not occurred. 1h = A capture mode event has occurred for Timer A. This interrupt asserts when the subtimer is configured in Input Edge-Time mode. GPTM Timer A Capture Mode Match Raw Interrupt This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 0h = The capture mode match for Timer A has not occurred. 1h = A capture mode match has occurred for Timer A. This interrupt asserts when the values in the GPTMTAR and GPTMTAPR match the values in the GPTMTAMATCHR and GPTMTAPMR when configured in Input Edge-Time mode. GPTM Timer A Time-Out Raw Interrupt This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. 0h = Timer A has not timed out. 1h = Timer A has timed out. This interrupt is asserted when a oneshot or periodic mode timer reaches it's count limit (0 or the value loaded into GPTMTAILR, depending on the count direction). 284 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.5.1.7 GPTMMIS Register (offset = 20h) [reset = 0h] Register mask: 0h GPTMMIS is shown in Figure 9-11 and described in Table 9-15. 31 30 23 22 15 14 RESERVED R-X 7 6 RESERVED R-X 29 21 13 DMABMIS R-X 5 DMAAMIS R-X Figure 9-11. GPTMMIS Register 28 27 26 RESERVED R-X 20 19 18 RESERVED R-X 12 RESERVED R-X 11 TBMMIS R-X 10 CBEMIS R-X 4 TAMMIS R-X 3 RESERVED R-X 2 CAEMIS R-X TIMER Registers 25 24 17 16 9 CBMMIS R-X 1 CAMMIS R-X 8 TBTOMIS R-X 0 TATOMIS R-X Bit 31-14 13 Field RESERVED DMABMIS 12 RESERVED 11 TBMMIS 10 CBEMIS 9 CBMMIS 8 TBTOMIS 7-6 RESERVED 5 DMAAMIS 4 TAMMIS 3 RESERVED Table 9-15. GPTMMIS Register Field Descriptions Type R R R R R R R R R R R Reset X X X X X X X X X X X Description GPTM Timer B DMA Done Masked Interrupt This bit is cleared by writing a 1 to the DMABINT bit in the GPTMICR register. 0h = A Timer B DMA done interrupt has not occurred or is masked. 1h = An unmasked Timer B DMA done interrupt has occurred. GPTM Timer B Match Masked Interrupt This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 0h = A Timer B Mode Match interrupt has not occurred or is masked. 1h = An unmasked Timer B Mode Match interrupt has occurred. GPTM Timer B Capture Mode Event Masked Interrupt This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 0h = A Capture B event interrupt has not occurred or is masked. 1h = An unmasked Capture B event interrupt has occurred. GPTM Timer B Capture Mode Match Masked Interrupt This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. 0h = A Capture B Mode Match interrupt has not occurred or is masked. 1h = An unmasked Capture B Match interrupt has occurred. GPTM Timer B Time-Out Masked Interrupt This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 0h = A Timer B Time-Out interrupt has not occurred or is masked. 1h = An unmasked Timer B Time-Out interrupt has occurred. GPTM Timer A DMA Done Masked Interrupt This bit is cleared by writing a 1 to the DMAAINT bit in the GPTMICR register. 0h = A Timer A DMA done interrupt has not occurred or is masked. 1h = An unmasked Timer A DMA done interrupt has occurred. GPTM Timer A Match Masked Interrupt This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 0h = A Timer A Mode Match interrupt has not occurred or is masked. 1h = An unmasked Timer A Mode Match interrupt has occurred. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 285 TIMER Registers www.ti.com Table 9-15. GPTMMIS Register Field Descriptions (continued) Bit Field 2 CAEMIS 1 CAMMIS 0 TATOMIS Type R R R Reset X X X Description GPTM Timer A Capture Mode Event Masked Interrupt This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. 0h = A Capture A event interrupt has not occurred or is masked. 1h = An unmasked Capture A event interrupt has occurred. GPTM Timer A Capture Mode Match Masked Interrupt This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 0h = A Capture A Mode Match interrupt has not occurred or is masked. 1h = An unmasked Capture A Match interrupt has occurred. GPTM Timer A Time-Out Masked Interrupt This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. 0h = A Timer A Time-Out interrupt has not occurred or is masked. 1h = An unmasked Timer A Time-Out interrupt has occurred. 286 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.8 GPTMICR Register (offset = 24h) [reset = 0h] Register mask: 0h GPTMICR is shown in Figure 9-12 and described in Table 9-16. This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. 31 30 23 22 15 14 RESERVED R-X 7 6 RESERVED R-X 29 21 13 DMABINT W1C-X 5 DMAAINT W1C-X Figure 9-12. GPTMICR Register 28 27 26 RESERVED R-X 20 19 18 RESERVED R-X 12 RESERVED R-X 11 TBMCINT W1C-X 10 CBECINT W1C-X 4 TAMCINT W1C-X 3 RESERVED R-X 2 CAECINT W1C-X 25 24 17 16 9 CBMCINT W1C-X 1 CAMCINT W1C-X 8 TBTOCINT W1C-X 0 TATOCINT W1C-X Bit 31-14 13 Field RESERVED DMABINT 12 RESERVED 11 TBMCINT 10 CBECINT 9 CBMCINT 8 TBTOCINT 7-6 RESERVED 5 DMAAINT 4 TAMCINT 3 RESERVED 2 CAECINT 1 CAMCINT Table 9-16. GPTMICR Register Field Descriptions Type R W1C R W1C W1C W1C W1C R W1C W1C R W1C W1C Reset X X X X X X X X X X X X X Description GPTM Timer B DMA Done Interrupt Clear Writing a 1 to this bit clears the DMABRIS bit in the GPTMRIS register and the DMABMIS bit in the GPTMMIS register. GPTM Timer B Match Interrupt Clear Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the GPTMMIS register. GPTM Timer B Capture Mode Event Interrupt Clear Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS bit in the GPTMMIS register. GPTM Timer B Capture Mode Match Interrupt Clear Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS bit in the GPTMMIS register. GPTM Timer B Time-Out Interrupt Clear Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in the GPTMMIS register. GPTM Timer A DMA Done Interrupt Clear Writing a 1 to this bit clears the DMAARIS bit in the GPTMRIS register and the DMAAMIS bit in the GPTMMIS register. GPTM Timer A Match Interrupt Clear Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the GPTMMIS register. GPTM Timer A Capture Mode Event Interrupt Clear Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in the GPTMMIS register. GPTM Timer A Capture Mode Match Interrupt Clear Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 287 TIMER Registers www.ti.com Table 9-16. GPTMICR Register Field Descriptions (continued) Bit Field 0 TATOCINT Type W1C Reset X Description GPTM Timer A Time-Out Raw Interrupt Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register. 288 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.9 GPTMTAILR Register (offset = 28h) [reset = FFFFFFFFh] GPTMTAILR is shown in Figure 9-13 and described in Table 9-17. When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. Figure 9-13. GPTMTAILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILR R/W-FFFFFFFFh Bit 31-0 Field TAILR Table 9-17. GPTMTAILR Register Field Descriptions Type R/W Reset Description FFFFFFFFh GPTM Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 289 TIMER Registers www.ti.com 9.5.1.10 GPTMTBILR Register (offset = 2Ch) [reset = FFFFh] GPTMTBILR is shown in Figure 9-14 and described in Table 9-18. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are reserved in both cases. Figure 9-14. GPTMTBILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILR R/W-FFFFh Bit 31-0 Field TBILR Table 9-18. GPTMTBILR Register Field Descriptions Type R/W Reset FFFFh Description GPTM Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of GPTMTBILR. When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 290 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.11 GPTMTAMATCHR Register (offset = 30h) [reset = FFFFFFFFh] GPTMTAMATCHR is shown in Figure 9-15 and described in Table 9-19. When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR. Figure 9-15. GPTMTAMATCHR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMR R/W-FFFFFFFFh Bit 31-0 Field TAMR Table 9-19. GPTMTAMATCHR Register Field Descriptions Type R/W Reset Description FFFFFFFFh GPTM Timer A Match Register This value is compared to the GPTMTAR register to determine match events. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 291 TIMER Registers www.ti.com 9.5.1.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh] GPTMTBMATCHR is shown in Figure 9-16 and described in Table 9-20. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Figure 9-16. GPTMTBMATCHR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBMR R/W-FFFFh Bit 31-0 Field TBMR Table 9-20. GPTMTBMATCHR Register Field Descriptions Type R/W Reset FFFFh Description GPTM Timer B Match Register This value is compared to the GPTMTBR register to determine match events. 292 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.13 GPTMTAPR Register (offset = 38h) [reset = 0h] GPTMTAPR is shown in Figure 9-17 and described in Table 9-21. This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTAR and GPTMTAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. Figure 9-17. GPTMTAPR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TAPSR R-X R/W-0h Bit 31-8 7-0 Field RESERVED TAPSR Table 9-21. GPTMTAPR Register Field Descriptions Type R R/W Reset X 0h Description GPTM Timer A Prescale The register loads this value on a write. A read returns the current value of the register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 293 TIMER Registers www.ti.com 9.5.1.14 GPTMTBPR Register (offset = 3Ch) [reset = 0h] GPTMTBPR is shown in Figure 9-18 and described in Table 9-22. This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTBR and b registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. Figure 9-18. GPTMTBPR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TBPSR R-X R/W-0h Bit 31-8 7-0 Field RESERVED TBPSR Table 9-22. GPTMTBPR Register Field Descriptions Type R R/W Reset X 0h Description GPTM Timer B Prescale The register loads this value on a write. A read returns the current value of this register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. 294 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.15 GPTMTAPMR Register (offset = 40h) [reset = 0h] GPTMTAPMR is shown in Figure 9-19 and described in Table 9-23. This register allows software to extend the range of the GPTMTAMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. Figure 9-19. GPTMTAPMR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TAPSMR R-X R/W-0h Bit 31-8 7-0 Field RESERVED TAPSMR Table 9-23. GPTMTAPMR Register Field Descriptions Type R R/W Reset X 0h Description GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler match value. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 295 TIMER Registers www.ti.com 9.5.1.16 GPTMTBPMR Register (offset = 44h) [reset = 0h] GPTMTBPMR is shown in Figure 9-20 and described in Table 9-24. This register allows software to extend the range of the GPTMTBMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. Figure 9-20. GPTMTBPMR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TBPSMR R-X R/W-0h Bit 31-8 7-0 Field RESERVED TBPSMR Table 9-24. GPTMTBPMR Register Field Descriptions Type R R/W Reset X 0h Description GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 296 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.17 GPTMTAR Register (offset = 48h) [reset = FFFFFFFFh] GPTMTAR is shown in Figure 9-21 and described in Table 9-25. When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (GPTMTAPS) register. Figure 9-21. GPTMTAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAR R-FFFFFFFFh Bit 31-0 Field TAR Table 9-25. GPTMTAR Register Field Descriptions Type R Reset Description FFFFFFFFh GPTM Timer A Register A read returns the current value of the GPTM Timer A Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 297 TIMER Registers www.ti.com 9.5.1.18 GPTMTBR Register (offset = 4Ch) [reset = FFFFh] GPTMTBR is shown in Figure 9-22 and described in Table 9-26. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (GPTMTBPS) register. Figure 9-22. GPTMTBR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBR R-FFFFh Bit 31-0 Field TBR Table 9-26. GPTMTBR Register Field Descriptions Type R Reset FFFFh Description GPTM Timer B Register A read returns the current value of the GPTM Timer B Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 298 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.19 GPTMTAV Register (offset = 50h) [reset = FFFFFFFFh] GPTMTAV is shown in Figure 9-23 and described in Table 9-27. When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (GPTMTBV) register). In a 16bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. Figure 9-23. GPTMTAV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAV R/W-FFFFFFFFh Bit 31-0 Field TAV Table 9-27. GPTMTAV Register Field Descriptions Type R/W Reset Description FFFFFFFFh GPTM Timer A Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of the GPTMTAV register can be written with a new value. Writes to the prescaler bits have no effect. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 299 TIMER Registers www.ti.com 9.5.1.20 GPTMTBV Register (offset = 54h) [reset = FFFFh] GPTMTBV is shown in Figure 9-24 and described in Table 9-28. When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0. Figure 9-24. GPTMTBV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBV R/W-FFFFh Bit 31-0 Field TBV Table 9-28. GPTMTBV Register Field Descriptions Type R/W Reset FFFFh Description GPTM Timer B Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of the GPTMTBV register can be written with a new value. Writes to the prescaler bits have no effect. 300 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com TIMER Registers 9.5.1.21 GPTMDMAEV Register (offset = 6Ch) [reset = 0h] GPTMDMAEV is shown in Figure 9-25 and described in Table 9-29. This register allows software to enable and disable GPTM DMA trigger events. Setting a bit enables the corresponding DMA trigger, while clearing a bit disables it. Figure 9-25. GPTMDMAEV Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED TBMDMAEN CBEDMAEN CBMDMAEN TBTODMAEN R-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED TAMDMAEN RTCDMAEN CAEDMAEN CAMDMAEN TATODMAEN R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-12 11 Field RESERVED TBMDMAEN 10 CBEDMAEN 9 CBMDMAEN 8 TBTODMAEN 7-5 RESERVED 4 TAMDMAEN 3 RTCDMAEN Table 9-29. GPTMDMAEV Register Field Descriptions Type R R/W R/W R/W R/W R R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h Description GPTM B Mode Match Event DMA Trigger Enable When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a mode match has occurred. 0h = Timer B Mode Match DMA trigger is disabled. 1h = Timer B DMA Mode Match trigger is enabled GPTM B Capture Event DMA Trigger Enable When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a capture event has occurred. 0h = Timer B Capture Event DMA trigger is disabled. 1h = Timer B Capture Event DMA trigger is enabled. GPTM B Capture Match Event DMA Trigger Enable When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a capture match event has occurred. 0h = Timer B Capture Match DMA trigger is disabled. 1h = Timer B Capture Match DMA trigger is enabled GPTM B Time-Out Event DMA Trigger Enable When this bit is enabled, a Timer B dma_req signal is sent to the DMA on a time-out event. 0h = Timer B Time-Out DMA trigger is disabled. 1h = Timer B Time-Out DMA trigger is enabled. GPTM A Mode Match Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a mode match has occurred. 0h = Timer A Mode Match DMA trigger is disabled. 1h = Timer A DMA Mode Match trigger is enabled. GPTM A RTC Match Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a RTC match has occurred. 0h = Timer A RTC Match DMA trigger is disabled. 1h = Timer A RTC Match DMA trigger is enabled. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated General-Purpose Timers 301 TIMER Registers www.ti.com Table 9-29. GPTMDMAEV Register Field Descriptions (continued) Bit Field 2 CAEDMAEN 1 CAMDMAEN 0 TATODMAEN Type R/W R/W R/W Reset 0h 0h 0h Description GPTM A Capture Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a capture event has occurred. 0h = Timer A Capture Event DMA trigger is disabled. 1h = Timer A Capture Event DMA trigger is enabled. GPTM A Capture Match Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a capture match event has occurred. 0h = Timer A Capture Match DMA trigger is disabled. 1h = Timer A Capture Match DMA trigger is enabled. GPTM A Time-Out Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the DMA on a time-out event. 0h = Timer A Time-Out DMA trigger is disabled. 1h = Timer A Time-Out DMA trigger is enabled. 302 General-Purpose Timers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 10 SWRU367B – June 2014 – Revised October 2014 Watchdog Timer Topic ........................................................................................................................... Page 10.1 Overview ......................................................................................................... 304 10.2 Functional Description ...................................................................................... 305 10.3 Register Map.................................................................................................... 305 10.4 MCU Watch Dog Controller Usage Caveats.......................................................... 314 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 303 Overview www.ti.com 10.1 Overview A watchdog timer in CC3200 can generate a regular interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. CC3200 has one Watchdog Timer Module, clocked by the system clock. The Watchdog Timer module supports the following features: • 32-bit down counter with a programmable load register • Lock register protection from runaway software • Reset generation cannot be disabled • User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The Watchdog Timer Module, supports the following clock sources: • System clock (80MHz in RUN mode) The clock used for WDT is selected by the configuration register APRCM:WDTCLKEN. 10.1.1 Block Diagram Interrupt System Clock Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD 32-Bit Down Counter 0x0000.0000 Comparator WDTVALUE Identification Registers WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 Figure 10-1. WDT Module Block Diagram 304 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 10.2 Functional Description The Watchdog Timer module generates the first time-out signal (interrupt) when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. The WDT can be configured to reset on the second overflow. The WDT interrupt is maskable. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The watchdog timer is disabled by default out of reset. To achieve maximum watchdog protection of the device, the watchdog timer can be enabled at the start of the reset vector. NOTE: In CC3200 R1 device, it is highly recommended that the application software, when rebooting after a WDT reset, requests the PRCM for Hibernation (see Section 15.3.10) for 10mS of and resume its full functionality only after returning from this hibernation. This is effective for full recovery from any complex stuck-at scenario that involves the WiFi subsystem. Application can determine if the reset cause is WDT, by reading the GPRCM:APPS_RESET_CAUSE[7:0] register (Physical address 0x4402 D00C). On wakeup following a WDT reset, this would read the value "0101". Please refer to the chapter on Power, Reset, and Clock Management for more details. 10.2.1 Initialization and Configuration The Watchdog Timer is configured using the following sequence: 1. To use the WDT, its peripheral clock must be enabled by setting the , RUNCLKEN bit in Watchdog Timer Clock Enable (WDTCLKEN) register. 2. Watchdog module is reset using watch dog timer software reset (WDTSWRST) register 3. Load the WDTLOADregister with the desired timer load value. 4. Set the INTEN bit in the WDTCTLregister to enable the Watchdog, enable interrupts, and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCKregister. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. To service the watchdog, periodically reload the count value into the WDTLOADregister to restart the count. The interrupt can be enabled using the INTEN bit in the WDTCTLregister to allow the processor to attempt corrective action if the watchdog is not serviced often enough. The RESEN bit in WDTCTL can be set so that the system resets if the failure is not recoverable using the ISR. 10.3 Register Map Table 10-1on lists the Watchdog registers. The offset listed is a hexadecimal increment to the register's address, relative to the Watchdog Timer base address: 0x4000.0000. Note that the Watchdog Timer module clock must be enabled before the registers can be programmed. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 305 Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x418 0xC00 Table 10-1. Watchdog Timers Register Map www.ti.com Name WDTLOAD WDTVALUE WDTCTL WDTICR WDTRIS WDTTEST WDTLOCK Type R/W RO R/W WO RO R/W R/W Reset 0xFFFF.FFFF 0xFFFF.FFFF 0x0000.0000 (WDT0) 0x8000.0000 (WDT1) - 0x0000.0000 0x0000.0000 0x0000.0000 Description Watchdog Load Watchdog Value Watchdog Control Watchdog Interrupt Clear Watchdog Raw Interrupt Status Watchdog Test Watchdog Lock 10.3.1 Register Description The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 306 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 10.3.1.1 WATCHDOG Registers Table 10-2 lists the memory-mapped registers for the WATCHDOG. All register offset addresses not listed in Table 10-2 should be considered as reserved locations and the register contents should not be modified. lists the Watchdog registers. The offset listed is a hexadecimal increment to the register's address, relative to the Watchdog Timer base address: 0x4000.0000. Note that the Watchdog Timer module clock must be enabled before the registers can be programmed. Offset 0h 4h 8h Ch 10h 418h C00h Acronym WDTLOAD WDTVALUE WDTCTL WDTICR WDTRIS WDTTEST WDTLOCK Table 10-2. WATCHDOG Registers Register Name Watchdog Load Watchdog Value Watchdog Control Watchdog Interrupt Clear Watchdog Raw Interrupt Status Watchdog Test Watchdog Lock Section Section 10.3.1.1.1 Section 10.3.1.1.2 Section 10.3.1.1.3 Section 10.3.1.1.4 Section 10.3.1.1.5 Section 10.3.1.1.6 Section 10.3.1.1.7 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 307 Register Map www.ti.com 10.3.1.1.1 WDTLOAD Register (offset = 0h) [reset = FFFFFFFFh] WDTLOAD is shown in Figure 10-2 and described in Table 10-3. This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Figure 10-2. WDTLOAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLOAD R/W-FFFFFFFFh LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field WDTLOAD Table 10-3. WDTLOAD Register Field Descriptions Type R/W Reset Description FFFFFFFFh Watchdog Load Value 308 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 10.3.1.1.2 WDTVALUE Register (offset = 4h) [reset = FFFFFFFFh] WDTVALUE is shown in Figure 10-3 and described in Table 10-4. This register contains the current count value of the timer. Register Map Figure 10-3. WDTVALUE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTVALUE R-FFFFFFFFh LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field WDTVALUE Table 10-4. WDTVALUE Register Field Descriptions Type R Reset Description FFFFFFFFh Watchdog Value Current value of the 32-bit down counter. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 309 Register Map www.ti.com 10.3.1.1.3 WDTCTL Register (offset = 8h) [reset = 80000000h] WDTCTL is shown in Figure 10-4 and described in Table 10-5. This register is the watchdog control register. The watchdog timer can be used to generate a reset signal (on second time-out) or an interrupt on time-out. 31 30 WRC R-1h Figure 10-4. WDTCTL Register 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED INTTYPE R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 RESERVED R/W-0h 24 16 8 0 INTEN R/W-0h Bit Field 31 WRC 30-3 2 RESERVED INTTYPE 1 RESERVED 0 INTEN Table 10-5. WDTCTL Register Field Descriptions Type R R R/W R/W R/W Reset 1h 0h 0h 0h 0h Description Write Complete The WRC values are defined as follows: Note: This bit is reserved for WDT0 and has a reset value of 0. 0h = A write access to one of the WDT1 registers is in progress. 1h = A write access is not in progress, and WDT1 registers can be read or written. Watchdog Interrupt Type The INTTYPE values are defined as follows: 0h = Watchdog interrupt is a standard interrupt. 1h = Not Valid Value Watchdog Interrupt Enable The INTEN values are defined as follows: 0h = Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1h = Interrupt event enabled. Once enabled, all writes are ignored. Setting this bit enables the Watchdog Timer. 310 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 10.3.1.1.4 WDTICR Register (offset = Ch) [reset = 0h] Register mask: 0h WDTICR is shown in Figure 10-5 and described in Table 10-6. This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Write to this register when a watchdog time-out interrupt has occurred to properly service the Watchdog. Value for a read or reset is indeterminate. Figure 10-5. WDTICR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTINTCLR W-X LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field WDTINTCLR Table 10-6. WDTICR Register Field Descriptions Type W Reset X Description Watchdog Interrupt Clear SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 311 Register Map www.ti.com 10.3.1.1.5 WDTRIS Register (offset = 10h) [reset = 0h] WDTRIS is shown in Figure 10-6 and described in Table 10-7. This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Figure 10-6. WDTRIS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 1 0 WDTRIS R-0h Bit 31-1 0 Field RESERVED WDTRIS Table 10-7. WDTRIS Register Field Descriptions Type R R Reset 0h 0h Description Watchdog Raw Interrupt Status 0h = The watchdog has not timed out. 1h = A watchdog time-out event has occurred. 312 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Register Map 10.3.1.1.6 WDTTEST Register (offset = 418h) [reset = 0h] WDTTEST is shown in Figure 10-7 and described in Table 10-8. This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Figure 10-7. WDTTEST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 STALL R/W-0h 1 0 Bit 31-9 8 Field RESERVED STALL 7-0 RESERVED Table 10-8. WDTTEST Register Field Descriptions Type R R/W R Reset 0h 0h 0h Description Watchdog Stall Enable 0h = The watchdog timer continues counting if the microcontroller is stopped with a debugger. 1h = If the microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 313 MCU Watch Dog Controller Usage Caveats www.ti.com 10.3.1.1.7 WDTLOCK Register (offset = C00h) [reset = 0h] WDTLOCK is shown in Figure 10-8 and described in Table 10-9. Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers, except for the Watchdog Test (WDTTEST) register. The locked state will be enabled after 2 clock cycles. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Figure 10-8. WDTLOCK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLOCK R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field WDTLOCK Table 10-9. WDTLOCK Register Field Descriptions Type R/W Reset 0h Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates, except for the WDTTEST register. Avoid writes to the WDTTEST register when the watchdog registers are locked. A read of this register returns the following values: 0h = Unlocked 1h = Locked 10.4 MCU Watch Dog Controller Usage Caveats 10.4.1 System WatchDog Behavior: • The system WDOG timer expiry forces the MCU and network processor through a reset cycle, but the WLAN domain (MAC and Baseband) is not reset. • Subsequent recovery takes MCU and NWP out of reset at the same time. Issue: • The above behavior does not allow a WLAN domain clean reset. • The recovery flow order is not congruent to the software flow (NWP start-up is always initiated by the MCU once the MCU boot loading is completed). Resolution: The MCU application must detect a recovery from the WDOG trigger and force the device into complete hibernation with a wake-up associated with an internal RTC timer. This ensures a complete system cleanup. 314 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MCU Watch Dog Controller Usage Caveats Figure 10-9. WatchDog Flow Chart 10.4.2 System WatchDog Recovery Sequence The following sequence should be integrated in the user application for a reliable recovery from the WDOG trigger: SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Watchdog Timer 315 MCU Watch Dog Controller Usage Caveats www.ti.com Figure 10-10. System WatchDog Recovery Sequence 316 Watchdog Timer SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Chapter 11 SWRU367B – June 2014 – Revised October 2014 SDHost Controller Interface Topic ........................................................................................................................... Page 11.1 Overview ......................................................................................................... 318 11.2 1-Bit SD Interface ............................................................................................. 319 11.3 Initialization and configuration using Peripheral APIs ........................................... 320 11.4 Performance and Testing .................................................................................. 325 11.5 Peripheral Library APIs ..................................................................................... 325 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 317 Overview www.ti.com 11.1 Overview The Secure Digital Host (SD Host) controller on CC3200 provides an interface between a local host (LH) such as a microprocessor controller (MCU) and a SD memory card and handles SD transactions with minimal LH intervention. The SD host provides SD Card access in 1-bit mode and deals with SD protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness. The application interface can send every SD command and either poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation. The controller can be configured to generate DMA requests and work with minimum CPU intervention. Given the nature of integration of this peripheral on the CC3200 platform, it is recommended that developers use Peripheral Library APIs to control and operate the block. This section of the TRM emphasizes understanding the SD Host APIs provided in the CC3200 Software Development Kit [Peripheral Library]. After introducing of the APIs, this document would lean on a reference application to illustrate the usage of the APIs. SD Host Features • Full compliance with SD command/response sets as defined in the SD Memory Card. Specifications, v2.0. Including high-capacity (size >2GB) cards HC SD. • Flexible architecture allowing support for new command structure. • 1-bit transfer mode specifications for SD cards. • Built-in 1024-byte buffer for read or write – 512-Byte each for Transmit and Receive – Each 32-bit wide by 128 words deep • 32-bit-wide access bus to maximize bus throughput • Single interrupt line for multiple interrupt source events • Two slave DMA channels (1 for TX, 1 for RX) • Programmable clock generation • Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver. • Supports configurable busy and response timeout. • Support for a wide range of card clock frequency with odd and even clock ratio. Max frequency supported is 24 MHz 318 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.2 1-Bit SD Interface 1-Bit SD Interface SDHost Controller Interface Block Diagram The interface uses three signal lines to communicate with SD Card: 1. CLK: Generated internally by SDHost controller and provided to external SD Card. 2. CMD: Bidirectional; Used to send commands and receive responses. 3. DATA: Bidirectional; Used to send and receive data to/from the attached SD Card. The bus protocol between the SD host controller and the card is message-based. Each message is represented by one of the following parts: • Command: A command starts an operation. The command is transferred serially from the SD host controller to the card on the CMD line. • Response: A response is an answer to a command. The response is sent from the card to the SD host controller, and is transferred serially on the CMD line. • Data: Data is transferred from the SD host controller to the card or from a card to the SD host controller using the DATA line. • Busy: The Data signal is maintained low by the card as it programs the data received. 11.2.1 Clock and Reset Management The Power, Reset and Clock Module (PRCM) manages the clock and reset functions. The on-chip SDHost controller is sourced by a 120 MHz fixed clock that can be divided down to the required card clock frequency using the internal 10-bit divider of the module. The user can reset the module to bring all the internal registers to their default state by calling the PRCM reset API with the appropriate parameters. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 319 Initialization and configuration using Peripheral APIs www.ti.com 11.3 Initialization and configuration using Peripheral APIs This section discusses the host initialization and configuration example, followed by showing how the peripheral APs can implement the standard SD card detection and initialization sequence. 11.3.1 Basic Initialization and Configuration 1. Enable SD Host Clock using PRCMPeripheralClkEnable(PRCM_SDHOST, PRCM_RUN_MODE_CLK). 2. In Pinmux module, enable the appropriate pins for SD Host functionality. 3. For a pin configured as CLK, configure the pin as an output by calling: PinDirModeSet(,PIN_DIR_MODE_OUT) 4. Soft reset and initialize the host controller: PRCMPeripheralReset(PRCM_SDHOST) SDHostInit(SDHOST_BASE) 5. Soft reset and initialize the host controller for 15 MHz card clocks: SDHostSetExpClk(SDHOST_BASE, PRCMPeripheralClockGet(PRCM_SDHOST), 15000000) 11.3.2 Sending Command The following code shows how to send a command to an attached SD card using peripheral APIs. SendCmd(unsigned long ulCmd, unsigned long ulArg) { unsigned long ulStatus; // // Clear interrupt status // SDHostIntClear(SDHOST_BASE,0xFFFFFFFF); // // Send command // SDHostCmdSend(SDHOST_BASE,ulCmd,ulArg); // // Wait for command complete or error // do { ulStatus = SDHostIntStatus(SDHOST_BASE); ulStatus = (ulStatus & (SDHOST_INT_CC|SDHOST_INT_ERRI)); } while( !ulStatus ); // // Check error status // if(ulStatus &SDHOST_INT_ERRI) { // // Reset the command line // SDHostCmdReset(SDHOST_BASE); return 1; } else 320 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com { } } return 0; Initialization and configuration using Peripheral APIs The ulCmd parameter is logical OR of the SD Command, expected response length, or flags indicating if the command is followed by a block read or write, a multi-block read or write, and whether the host controller will generate a DMA request for data to and from the internal FIFO. For example, the SD card command 0 (or GO_IDLE command) has neither a response associated with it nor any block read or write that follows it. The command also doesn’t take any argument. For this the SendCmd() will be invoked as: #define CMD_GO_IDLE_STATE SDHOST_CMD_0 SendCmd(CMD_GO_IDLE_STATE, 0) Another command example is the SD card command 18, used to read multiple blocks from the SD Card. The command takes the block number or linear address of the first byte to be read based on the version and capacity of the attached card: #define CMD_READ_MULTI_BLK SendCmd(CMD_READ_MULTI_BLK, ) SDHOST_CMD_18| SDHOST_RD_CMD| SDHOST_RESP_LEN_48| SDHOST_MULTI_BLK 11.3.3 Card Detection and Initialization The following code shows a card detection and initialization using peripheral APIs: CardInit(CardAttrib_t *CardAttrib) { unsigned long ulRet; unsigned long ulResp[4]; // // Initialize the attributes. // CardAttrib->ulCardType = CARD_TYPE_UNKNOWN; CardAttrib->ulCapClass = CARD_CAP_CLASS_SDSC; CardAttrib->ulRCA = 0; CardAttrib->ulVersion = CARD_VERSION_1; // // Send std GO IDLE command // if( SendCmd(CMD_GO_IDLE_STATE, 0) == 0) { ulRet = SendCmd(CMD_SEND_IF_COND,0x00000100); // // It's a SD ver 2.0 or higher card // if(ulRet == 0) { CardAttrib->ulVersion = CARD_VERSION_2; CardAttrib->ulCardType = CARD_TYPE_SDCARD; // // Wait for card to become ready. // do { // SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 321 Initialization and configuration using Peripheral APIs // Send ACMD41 // SendCmd(CMD_APP_CMD,0); ulRet = SendCmd(CMD_SD_SEND_OP_COND,0x40E00000); // // Response contains 32-bit OCR register // SDHostRespGet(SDHOST_BASE,ulResp); }while(((ulResp[0] >> 31) == 0)); if(ulResp[0] & (1UL<<30)) { CardAttrib->ulCapClass = CARD_CAP_CLASS_SDHC; } } else //It's a MMC or SD 1.x card { // // Wait for card to become ready. // do { if( (ulRet = SendCmd(CMD_APP_CMD,0)) == 0 ) { ulRet = SendCmd(CMD_SD_SEND_OP_COND,0x00E00000); // // Response contains 32-bit OCR register // SDHostRespGet(SDHOST_BASE,ulResp); } }while((ulRet == 0) &&((ulResp[0] >>31) == 0)); // // Check the response // if(ulRet == 0) { CardAttrib->ulCardType = CARD_TYPE_SDCARD; } else // CMD 55 is not recognised by SDHost cards. { // // Confirm if its a SDHost card // ulRet = SendCmd(CMD_SEND_OP_COND,0); if( ulRet == 0) { CardAttrib->ulCardType = CARD_TYPE_MMC; } } } } // // Get the RCA of the attached card // if(ulRet == 0) { ulRet = SendCmd(CMD_ALL_SEND_CID,0); if( ulRet == 0) { SendCmd(CMD_SEND_REL_ADDR,0); www.ti.com 322 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SDHostRespGet(SDHOST_BASE,ulResp); Initialization and configuration using Peripheral APIs // // Fill in the RCA // CardAttrib->ulRCA = (ulResp[0] >> 16); // // Get tha card capacity // CardAttrib->ullCapacity = CardCapacityGet(CardAttrib->ulRCA); } } // // return status. // return ulRet; } The structure used in the API has following format: typedef struct { unsigned long ulCardType; unsigned long long ullCapacity; unsigned long ulVersion; unsigned long ulCapClass; unsigned short ulRCA; }CardAttrib_t; 11.3.4 Block Read The following code shows a block read using peripheral APIs: unsigned long CardReadBlock(CardAttrib_t *Card, unsigned char *pBuffer, unsigned long ulBlockNo, unsigned long ulBlockCount) { unsigned long ulSize; unsigned long ulBlkIndx; ulBlockCount = ulBlockCount + ulBlockNo; for(ulBlkIndx = ulBlockNo; ulBlkIndx ulCapClass == CARD_CAP_CLASS_SDSC) { ulBlockNo = ulBlkIndx * 512; } if( SendCmd(CMD_READ_SINGLE_BLK, ulBlockNo) == 0 ) { // Read out the data. while(ulSize--) SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 323 Initialization and configuration using Peripheral APIs { MAP_SDHostDataRead(SDHOST_BASE,((unsigned long *)pBuffer); pBuffer+=4; } } else { // Retutn error return 1; } } // Return success return 0; } www.ti.com 11.3.5 Block Write The following code shows a block write using peripheral APIs: Unsigned long CardWriteBlock(CardAttrib_t *Card, unsigned char *pBuffer, unsigned long ulBlockNo, unsigned long ulBlockCount) { unsigned long ulSize; unsigned long ulBlkIndx; ulBlockCount = ulBlockCount + ulBlockNo; for(ulBlkIndx = ulBlockNo; ulBlkIndx ulCapClass == CARD_CAP_CLASS_SDSC) { ulBlockNo = ulBlkIndx * 512; } if( SendCmd(CMD_WRITE_SINGLE_BLK, ulBlockNo) == 0 ) { // Write the data while(ulSize--) { SDHostDataWrite(SDHOST_BASE,*((unsigned long *)pBuffer)); pBuffer+=4; } // Wait for transfer completion. while( !(SDHostIntStatus(SDHOST_BASE) &SDHOST_INT_TC) ); } else { return 1; } } // Return error return 0; } 324 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.4 Performance and Testing The APIs discussed above were tested with following cards types: Performance and Testing Vendor Transcend Transcend Strontium SanDisk SanDisk Kingston Size 2 GB 16 GB 2 GB 2 GB 64 GB 16 GB Table 11-1. Card Types Capacity Class SDSC SDHC SDSC SDSC SDXC SDHC Block Read/Write Comments Passed Passed Passed Passed This card required some additional delay after the card select command is sent to the card, and before sending a read or write command, or the command will never complete. Passed This card required some additional delay after the card select command is sent to the card, and before sending a read or write command, or the command will never complete. Failed. Didn’t responded to Block Read/Write commands This card requires a special SW sequence to work properly. The initialization sequence was different from other cards. Example of throughput data using the CPU. These values were measured with 1MB and 10MB block read or write on a Class-4 Transcend 16GB SDHC Card: Vendor & Type Class 4 Transcend Operation Read Read Write Write Write Write Table 11-2. Throughput Data Card Freq 24 24 12 12 24 24 80 MHz Cycles 67959516 680884716 236784547 2442413554 2151815366 2152352658 Data (bytes) 1048576 10485760 1048576 10485760 10485760 10485760 Baud (bytes/sec) 1234354 1232016 354272 343456 389839 389741 Throughput (Mbps) 9.4 9.4 2.70 2.62 2.97 2.97 11.5 Peripheral Library APIs This section lists the APIs, hosted in CC3200 SDK (Peripheral Library) necessary for I2S configuration. void SDHostInit(unsigned long ulBase) • Description: This function configures the SDHost module, enabling internal sub-modules. • Parameters: ulBase – Base address of the SDHost module. • Return: None void SDHostCmdReset(unsigned long ulBase) • Description: This function resets SDHost command line. • Parameters: ulBase – Base address of the SDHost module. • Return: None SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 325 Peripheral Library APIs www.ti.com long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd, unsigned ulArg) • Description: This function sends a command to the attached card over the SDHost interface. • Parameters: – ulBase – Base address of the SDHost module. – ulCmd – Command to be send to the card. – ulArg – Argument for the command. The ulCmd parameter can be one of SDHOST_CMD_0 to SDHOST_CMD_63. It can be logically ORed with one or more of the following: – SDHOST_MULTI_BLK For multi block transfer. – SDHOST_WR_CMD If command is followed by write data. – SDHOST_RD_CMD If command is followed by read data. – SDHOST_DMA_EN If data transfer needs to generate a DMA request. • Return: Returns 0 on success, -1 otherwise void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) • Description: This function registers the interrupt handler. This enables the global interrupt in the interrupt controller; specific interrupts must be enabled via SDHostIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source. • Parameters: – ulBase – Base address of the SDHost module. – pfnHandler – Pointer to the SDHost interrupt handler function. • Return: None void SDHostIntUnregister(unsigned long ulBase) • Description: This function unregisters the interrupt handler. It clears the handler to be called when a SDHost interrupt occurs. This also masks off the interrupt in the interrupt controller so that interrupt handler no longer is called. • Parameters: ulBase – Base address of the SDHost module. • Return: None void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags) • Description: This function enables the indicated SDHost interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor. • Parameters: – ulBase – Base address of the SDHost module. – ulIntFlags – Bit mask of the interrupt sources to be enabled The ulIntFlags parameter is the logical OR of any of the following: – SDHOST_INT_CC: Command Complete interrupt. – SDHOST_INT_TC: Transfer Complete interrupt. – SDHOST_INT_BWR: Buffer Write Ready interrupt. – SDHOST_INT_BWR: Buffer Read Ready interrupt. – SDHOST_INT_ERRI: Error interrupt. • Note that SDHOST_INT_ERRI can only be used with SDHostIntStatus() and is internally logical OR of all error status bits. Setting this bit alone as ulIntFlags doesn't generate any interrupt. – SDHOST_INT_CTO: Command Timeout error interrupt. – SDHOST_INT_CEB: Command End Bit error interrupt. – SDHOST_INT_DTO: Data Timeout error interrupt. – SDHOST_INT_DCRC: Data CRC error interrupt. – SDHOST_INT_DEB: Data End Bit error. – SDHOST_INT_CERR: Cart Status Error interrupt. 326 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Peripheral Library APIs – SDHOST_INT_BADA: Bad Data error interrupt. – SDHOST_INT_DMARD: Read DMA done interrupt. – SDHOST_INT_DMAWR: Write DMA done interrupt. • Return: None void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags) • Description: This function disables the indicated SDHost interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. • Parameters: – ulBase – Base address of the SDHost module. – ulIntFlags – Bit mask of the interrupt sources to be disabled. The ulIntFlags parameter has the same definition as the ulIntFlags parameter to SDHostIntEnable(). • Return: None unsigned long SDHostIntStatus(unsigned long ulBase) • Description: This function returns the interrupt status for the specified SDHost. • Parameters: ulBase – Base address of the SDHost module. • Return: Returns the current interrupt status, enumerated as a bit field of values described in SDHostIntEnable(). void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags) • Description: The specified SDHost interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being recognized again immediately upon exit. • Parameters: – ulBase – Base address of the SDHost module. – ulIntFlags – Bit mask of the interrupt sources to be cleared. The ulIntFlags parameter has the same definition as the ulIntFlags parameter to SDHostIntEnable(). • Return: None Void SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask) • Description: This function sets the card status error mask for response type R1, R1b, R5, R5b and R6 response. The parameter ulErrMask is the bit mask of card status errors to be enabled, if the corresponding bits in the 'card status' field of a response are set then the host controller indicates a card error interrupt status. Only bits referenced as type E (error) in the status field in the response can set a card status error. • Parameters: – ulBase – Base address of the SDHost module. – ulErrMask – Bit mask of card status errors to be enabled • Return: None unsigned long SDHostCardErrorMaskGet(unsigned long ulBase) • Description: This function gets the card status error mask for response type R1, R1b, R5, R5b and R6 response. • Parameters: ulBase – Base address of the SDHost module. • Return: Returns the current card status error. void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, unsigned long ulCardClk) • Description: This function configures the SDHost interface to supply the specified clock to the connected card. • Parameters: – ulBase – Base address of the SDHost module. – ulSDHostClk – The rate of clock supplied to SDHost module. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 327 Peripheral Library APIs www.ti.com – ulCardClk – Required SD interface clock. • Return: None void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]) • Description: This function gets the response from the SD card for the last command send. • Parameters: – ulBase – Base address of the SDHost module. – ulRespnse – 128-bit response • Return: None void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize) • Description: This function sets the block size the data transfer. • Parameters: – ulBase – Base address of the SDHost module. – ulBlkSize – Transfer block size in bytes. The parameter ulBlkSize is size of each data block in bytes. This should be in range 0 -2^10. • Return: None void SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount) • Description: This function sets block count for the data transfer. This needs to be set for each block transfer. • Parameters: – ulBase – Base address of the SDHost module. – ulBlkCount – Number of blocks. • Return: None tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData) • Description: This function writes a single data word into the SDHost write buffer. The function returns true if there was a space available in the buffer else returns false. • Parameters: – ulBase – Base address of the SDHost module. – ulData – Data word to be transferred. • Return: Return true on success, false otherwise. tBoolean SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData) • Description: This function reads a data word from the SDHost read buffer. The function returns true if there was data available in to buffer else returns false. • Parameters: – ulBase – Base address of the SDHost module. – pulData – Pointer to data word to be transferred. • Return: Return true on success, false otherwise. void SDHostDataWrite(unsigned long ulBase, unsigned long ulData) • Description: This function writes \e ulData into the SDHost write buffer. If there is no space in the write buffer this function waits until there is a space available before returning. • Parameters: – ulBase – Base address of the SDHost module. – ulData – Data word to be transferred. • Return: None void SDHostDataRead(unsigned long ulBase, unsigned long *ulData) • Description: This function reads a single data word from the SDHost read buffer. If there is no data available in the buffer the function will wait until a data word is received before returning. 328 SDHost Controller Interface SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com • Parameters: – ulBase – Base address of the SDHost module. – pulData – Pointer to data word to be transferred. • Return: None Peripheral Library APIs SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated SDHost Controller Interface 329 Chapter 12 SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port Topic ........................................................................................................................... Page 12.1 Overview ......................................................................................................... 331 12.2 Functional Description ...................................................................................... 332 12.3 Programming Model.......................................................................................... 332 12.4 Peripheral Library APIs for I2S Configuration ...................................................... 335 330 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 12.1 Overview CC3200 hosts a multi-channel audio serial port (MCASP). In this version of the device, only the InterIntegrated Sound (I2S) bit stream format is supported. Given the nature of integration of this peripheral on the CC3200 platform, developers should use Peripheral Library APIs to control and operate the I2S block. These APIs are tested to ensure I2S operation in master mode [CC3200 sources the I2S bit clock and frame synchronization signals], while interfacing with external audio codecs. This section of the TRM describes the I2S APIs provided in the CC3200 Software Development Kit [Peripheral Library]. This document uses a reference audio application to illustrate the usage of the I2S APIs. 12.1.1 I2S Format The I2S format is used in audio interfaces. I2S format is realized by configuring the internal TDM transfer mode to 2 slots per frame. I2S format is designed to transfer a stereo channel (left and right) over a single data pin. "Slots" are also commonly referred to as "channels". The frame width duration in the I2S format is the same as the slot size. The frame signal is also referred to as "word select" in the I2S format. Figure 12-1 shows the I2S protocol. Figure 12-1. I2S Protocol Figure 12-2 is a functional diagram of the MCASP module. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 331 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Functional Description Local host System clock unit System interrupt System DMA 32 32 Transmit format unit 32 32 Receive format unit Serializer 0 Serializer 1 Control Transmit state machine Transmit TDM sequencer Receive state machine Receive TDM sequencer AUXCLK Transmit Clock generator Frame-sync generator Receive Clock generator Frame-sync generator Error check Pin function control www.ti.com McAXR0 McAXR1 McACLKX McACLKR McAFSX McAFSR Clock check circuit Figure 12-2. MCASP Module SWAS032-013 12.2 Functional Description The following lists the configuration options: • Interface – Bit clock configuration (generated internally in the device) – speed, polarity, and so forth – Frame sync configuration – speed, polarity, width, and so forth. • Data Format – Alignment (left or right) – Order (MSB first or LSB first) – Pad – Slot Size • Data Transfer (CPU or DMA) For details on the APIs used for I2S configuration, see Section 12.4. 12.3 Programming Model 12.3.1 Clock and Reset Management The Power, Reset and Clock Module (PRCM) manages the clock and reset. The I2S master module is sourced by a 240MHz clock through a fractional clock divider. By default, this divider is set to output 24 MHz clock to the I2S module. The minimum frequency obtained by configuring this divider is (240000KHz/1023.99) = 234.377 KHz. 332 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Programming Model This divider can be configured using the PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq) API from the PRCM module driver. The module also has two internal dividers supporting a wide range of bit clock frequency. The following block diagram shows the logical clock path. Figure 12-3. Logical Clock Path The user resets the module to return the internal registers to their default state by calling the PRCM reset API with the appropriate parameters. 12.3.2 I2S Data Port Interface The I2S module has two data interfaces, CPU port and DMA port. Either can be used to feed transmit data into the I2S transmit buffer or read received data from the receive buffer. CPU Port: This port exposes the I2S buffers as 32-bit registers with one register per serializer (or data line) and can be written or read using the following APIs: • I2SDataPutNonBlocking(unsigned long ulBase, unsigned long ulDataLine, long ulData) • I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, long ulData) • I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine, long &ulData) • I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, long &ulData) DMA Port: This port exposes the I2S buffers as two 32 bit registers, one each for transmit and receive. The transmit port will service each serializer configured as transmit in a cyclic order if multiple serializers are configured as a transmitter. Similarly, the receive port services each serializer configured as receiver in a cyclic order if multiple serializers are configured as a transmitter. The ports can be assessed using following macros: • I2S_TX_DMA_PORT 0x4401E200 • I2S_RX_DMA_PORT 0x4401E280 12.3.3 Initialization and Configuration I2S on CC3200 acts as master providing frame sync and bit clock to slave and can operate in two modes – Transmit Only Mode and Synchronous Transmit - Receive Mode. In Transmit Only Mode, the device is only configured to transmit data. In Synchronous Transmit - Receive Mode, the device is configured to transmit and receive in a synchronous manner. In both cases the data transmitted and received is in sync with the frame sync and bit clock signals generated internally by the I2S module. This section shows a module initialization and configuration example for each mode supported to transmit and receive 16-bit, 44.1 KHz audio. 1. Computing bit clock from sampling frequency and bits/sample: BitClock = (Sampling_Frequency * 2 * bits/sample) BitClock = (44100 * 2 * 16) = 1411200 Hz 2. Basic Initialization SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 333 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Programming Model www.ti.com (a) Enable the I2S module clock by invoking PRCMPeripheralClkEnable(PRCM_I2S,PRCM_RUN_MODE_CLK). (b) Reset the module using PRCMPeripheralReset(PRCM_I2S). (c) Set fractional clock divider to generate module input clock of BitRate * 10: PRCMI2SClockFreqSet(14112000) (d) Configure the internal divider of the module to generate the required bit clock frequency: I2SConfigSetExpClk(I2S_BASE, 14112000, 1411200, I2S_SLOT_SIZE_16|I2S_PORT_CPU). • The second parameter “I2S_SLOT_SIZE_16|I2S_PORT_CPU” sets the slot size and chooses the port interface on which the I2C module should expect the data. (e) Register the interrupt handler and enable the transmit data interrupt: I2SIntRegister(I2S_BASE, I2SIntHandler) I2SIntEnable(I2S_BASE,I2S_INT_XDATA) 3. Transmit Only Mode with interrupts (a) Configure the serializer 0 for transmit: I2SSerializerConfig(I2S_BASE, I2S_DATA_LINE_0,I2S_SER_MODE_TX, I2S_INACT_LOW_LEVEL) (b) Enable I2S module in transmit only mode: I2SEnable(I2S_BASE, I2S_MODE_TX_ONLY) 4. Synchronous Transmit - Receive with interrupts (a) Enable receive data Interrupt: I2SIntEnable(I2S_BASE,I2S_INT_XDATA) (b) Configure the serializer 0 for transmit and serializer 1 for receive: I2SSerializerConfig(I2S_BASE, I2S_DATA_LINE_0, I2S_SER_MODE_TX, I2S_INACT_LOW_LEVEL) I2SSerializerConfig(I2S_BASE, I2S_DATA_LINE_1, I2S_SER_MODE_RX, I2S_INACT_LOW_LEVEL) (c) Enable I2S module in Synchronous Transmit-Receive mode: I2SEnable(I2S_BASE, I2S_MODE_TX_RX_SYNC) 5. Generic I2S Interrupt handler void I2SIntHandler() { unsigned long ulStatus; unsigned long ulDummy; // Get the interrupt status ulStatus = I2SIntStatus(I2S_BASE); // Check if there was a Transmit interrupt; if so write next data into the tx buffer and acknowledge // the interrupt if(ulStatus &I2S_STS_XDATA) { I2SDataPutNonBlocking(I2S_BASE,I2S_DATA_LINE_0,0xA5) I2SIntClear(I2S_BASE,I2S_STS_XDATA); } // Check if there was a receive interrupt; if so read the data from the rx buffer and acknowledge // the interrupt if(ulStatus &I2S_STS_RDATA) { I2SDataGetNonBlocking( I2S_BASE, I2S_DATA_LINE_1, 334 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com &ulDummy); } } Peripheral Library APIs for I2S Configuration I2SIntClear(I2S_BASE,I2S_STS_RDATA); 12.4 Peripheral Library APIs for I2S Configuration This section describes the APIs hosted in the CC3200 SDK (Peripheral Library) necessary for I2S configuration. 12.4.1 Basic APIs for Enabling and Configuring the Interface void I2SDisable (unsigned long ulBase) Disables transmit and/or receive. Parameters: ulBase — the base address of the I2S module. This function disables transmit, receive, or both from the I2S module. Returns: None. void I2SEnable (unsigned long ulBase, unsigned long ulMode) Enables transmit and/or receive. Parameters: ulBase — is the base address of the I2S module. ulMode — is one of the valid modes. This function enables the I2S module in specified mode. The parameter ulMode should be one of the following: -I2S_MODE_TX_ONLY -I2S_MODE_TX_RX_SYNC Returns: None. Reference: ulModeparameter #define I2S_MODE_TX_ONLY 0x00000001 #define I2S_MODE_TX_RX_SYNC 0x00000003 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState) Configure the serializer in a specified mode. Parameters: ulBase — is the base address of the I2S module. ulDataLine — is the data line (serilizer) to be configured. ulSerMode — is the required serializer mode. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 335 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Peripheral Library APIs for I2S Configuration ulInActState — sets the inactive state of the data line. www.ti.com This function configures and enables the serializer associated with the given data line in specified mode. The paramenter ulDataLine selects to data line to be configured and can be one of the following: -I2S_DATA_LINE_0 -I2S_DATA_LINE_1 The parameter ulSerMode can be one of the following: -I2S_SER_MODE_TX -I2S_SER_MODE_RX -I2S_SER_MODE_DISABLE The parameter ulInActState can be one of the following: -I2S_INACT_TRI_STATE -I2S_INACT_LOW_LEVEL -I2S_INACT_LOW_HIGH Returns: Returns receive FIFO status. References: ulDataLine parameter #define I2S_DATA_LINE_0 0x00000001 #define I2S_DATA_LINE_1 0x00000002 ulSerMode parameter #define I2S_SER_MODE_TX 0x00000001 #define I2S_SER_MODE_RX 0x00000002 #define I2S_SER_MODE_DISABLE 0x00000000 ulInActState parameter #define I2S_INACT_TRI_STATE 0x00000000 #define I2S_INACT_LOW_LEVEL 0x00000008 #define I2S_INACT_HIGH_LEVEL 0x0000000C void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig) Sets the configuration of the I2S module. Parameters: ulBase — is the base address of the I2S module. ulI2SClk — is the rate of the clock supplied to the I2S module. ulBitClk — is the desired bit rate. ulConfig — is the data format. This function configures the I2S for operation in the specified data format. The bit rate is provided in the ulBitClk parameter and the data format in the ulConfig parameter. The ulConfig parameter is the logical OR of two values: the slot size and the data read/write port select. The following parameters select the slot size: -I2S_SLOT_SIZE_24 -I2S_SLOT_SIZE_16 336 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com The following parameters select the data read/write port: -I2S_PORT_DMA -I2S_PORT_CPU Peripheral Library APIs for I2S Configuration Returns: None. Reference: #define I2S_SLOT_SIZE_24 0x00B200B4 #define I2S_SLOT_SIZE_16 0x00700074 #define I2S_PORT_CPU 0x00000008 #define I2S_PORT_DMA 0x00000000 SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 337 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Peripheral Library APIs for I2S Configuration 12.4.2 APIs for Data Access if DMA is Not Used void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData) Waits for data from the specified data line. Parameters: ulBase — is the base address of the I2S module. ulDataLine — is one of the valid data lines. pulData — is a pointer to the receive data variable. www.ti.com This function gets data from the receive register for the specified data line. If there is no data available, this function waits until a receive before returning. Returns: None. long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData) Receives data from the specified data line. Parameters: ulBase — is the base address of the I2S module. ulDataLine — is one of the valid data lines. pulData — is a pointer to the receive data variable. This function gets data from the receive register for the specified data line. Returns: Returns 0 on success, -1 otherwise. void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData) Waits to send data over the specified data line. Parameters: ulBase — is the base address of the I2S module. ulDataLine — is one of the valid data lines. ulData — is the data to be transmitted. This function sends the ucData to the transmit register for the specified data line. If there is no space available, this function waits until there is space available before returning. Returns: None. void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData) Waits to send data over the specified data line. Parameters: ulBase — is the base address of the I2S module. 338 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ulDataLine — is one of the valid data lines. ulData — is the data to be transmitted. Peripheral Library APIs for I2S Configuration This function writes the ucData to the transmit register for the specified data line. This function does not block, so if there is no space available, then -1 is returned, and the application must retry the function later. Returns: Returns 0 on success, -1 otherwise. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 339 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Peripheral Library APIs for I2S Configuration www.ti.com 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler) Registers an interrupt handler for an I2S interrupt. Parameters: ulBase — is the base address of the I2S module. pfnHandler — is a pointer to the function to be called when the I2S interrupt occurs. This function registers the interrupt handler. This function enables the global interrupt in the interrupt controller; specific I2S interrupts must be enabled via I2SIntEnable(). The interrupt handler must clear the interrupt source. See IntRegister() for information about registering interrupt handlers. Returns: None. void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags) Enables individual I2S interrupt sources. Parameters: ulBase — is the base address of the I2S module. ulIntFlags — is the bit mask of the interrupt sources to be enabled. This function enables the indicated I2S interrupt sources. Only enabled sources can be reflected to the processor interrupt; disabled sources have no effect on the processor. The ulIntFlags parameter is the logical OR for any of the following: -I2S_INT_XUNDRN -I2S_INT_XSYNCERR -I2S_INT_XLAST -I2S_INT_XDATA -I2S_INT_XSTAFRM -I2S_INT_XDMA -I2S_INT_ROVRN -I2S_INT_RSYNCERR -I2S_INT_RLAST -I2S_INT_RDATA -I2S_INT_RSTAFRM -I2S_INT_RDMA Returns: None. void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags) Disables individual I2S interrupt sources. Parameters: ulBase — is the base address of the I2S module. ulIntFlags — is the bit mask of the interrupt sources to be disabled. This function disables the indicated I2S interrupt sources. Only enabled sources can be reflected to the processor interrupt; disabled sources have no effect on the processor. The ulIntFlags parameter has the same definition as the ulIntFlags parameter to I2SIntEnable(). Returns: None. 340 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com unsigned long I2SIntStatus (unsigned long ulBase) Gets the current interrupt status. Parameters: ulBase — is the base address of the I2S module. Peripheral Library APIs for I2S Configuration This function returns the raw interrupt status for I2S enumerated as a bit field of values: -I2S_STS_XERR -I2S_STS_XDMAERR -I2S_STS_XSTAFRM -I2S_STS_XDATA -I2S_STS_XLAST -I2S_STS_XSYNCERR -I2S_STS_XUNDRN -I2S_STS_XDMA -I2S_STS_RERR -I2S_STS_RDMAERR -I2S_STS_RSTAFRM -I2S_STS_RDATA -I2S_STS_RLAST -I2S_STS_RSYNCERR -I2S_STS_ROVERN -I2S_STS_RDMA Returns: Returns the current interrupt status, enumerated as a bit field of the values described above. void I2SIntUnregister (unsigned long ulBase) Unregisters an interrupt handler for a I2S interrupt. Parameters: ulBase — is the base address of the I2S module. This function unregisters the interrupt handler. The function clears the handler to be called when a I2S interrupt occurs. This function also masks off the interrupt in the interrupt controller so that the interrupt handler no longer is called. See IntRegister() for information about registering interrupt handlers. Returns: None. void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags) Clears I2S interrupt sources. Parameters: ulBase — is the base address of the I2S module. ulStatFlags — is a bit mask of the interrupt sources to be cleared. The specified I2S interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being recognized again immediately upon exit. The ulIntFlags parameter is the logical OR of any of the value describe in I2SIntStatus(). Returns: None. Values that can be passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags parameter Table 12-1 lists the values that can be passed to I2SIntEnable()and I2SIntDisable()as the ulIntFlagsparameter. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 341 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Peripheral Library APIs for I2S Configuration Table 12-1. ulIntFlags Parameter Tag I2S_INT_XUNDR I2S_INT_XSYNCERR I2S_INT_XLAST I2S_INT_XDATA I2S_INT_XSTAFRM I2S_INT_XDMA I2S_INT_ROVRN I2S_INT_RSYNCERR I2S_INT_RLAST I2S_INT_RDATA I2S_INT_RSTAFRM I2S_INT_RDMA Value 0x00000001 0x00000002 0x00000010 0x00000020 0x00000080 0x80000000 0x00010000 0x00020000 0x00100000 0x00200000 0x00800000 0x40000000 Description Transmit underrun interrupt enable bit. Unexpected transmit frame sync interrupt enable bit. Transmit last slot interrupt enable bit. Transmit data ready interrupt enable bit. Transmit start of frame interrupt enable bit. Receiver overrun interrupt enable bit. Unexpected receive frame sync interrupt enable bit. Receive start of frame interrupt enable bit. Receive data ready interrupt enable bit. Receive start of frame interrupt enable bit. www.ti.com Values that can be passed to I2SIntClear() as the ulStatFlags parameter and returned from I2SIntStatus() Table 12-2 lists the values that can be passed to I2SIntClear()as the ulStatFlagsparameter and returned from I2SIntStatus(). Tag I2S_STS_XERR I2S_STS_XDMAERR I2S_STS_XSTAFRM I2S_STS_XDATA I2S_STS_XLAST I2S_STS_XSYNCERR I2S_STS_XUNDRN I2S_STS_XDMA I2S_STS_RERR I2S_STS_RDMAERR I2S_STS_RSTAFRM I2S_STS_RDATA I2S_STS_RLAST Table 12-2. ulStatFlags Parameter Value 0x00000100 0x00000080 0x00000040 0x00000020 0x00000010 0x00000002 0x00000001 0x80000000 0x01000000 0x00800000 0x00400000 0x00200000 0x00100000 Description XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters Transmit start of frame flag Transmit data ready flag. '1' indicates that data is copied from Tx Buffer to shift register. Tx Buffer is EMPTY and ready to be written '0' indicates Tx Buffer is FULL Transmit last slot flag. XLAST is set along with XDATA, if the current slot is the last slot in a frame. Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from Tx Buffer, but Tx Buffer has not yet been serviced with new data since the last transfer. RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error interrupt has occurred. Receive DMA error Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers Receive start of frame flag - Indicates A new receive frame sync is detected Receive data ready flag. Indicates data is transferred from shift Register to Rx Buffer and ready to be serviced by the CPU or DMA. When RDATA is set, it always causes a DMA event. Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. 342 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Peripheral Library APIs for I2S Configuration Table 12-2. ulStatFlags Parameter (continued) Tag I2S_STS_RSYNCERR Value 0x00020000 I2S_STS_ROVERN 0x00010000 I2S_STS_RDMA 0x40000000 Description Unexpected receive frame sync Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync occurs before it is expected Receive clock failure Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 343 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Peripheral Library APIs for I2S Configuration 12.4.4 APIs to Control FIFO Structures Associated with I2S Peripheral void I2SRxFIFODisable (unsigned long ulBase) Disables receive FIFO. Parameters: ulBase — is the base address of the I2S module. This function disables the I2S receive FIFO. Returns: None. www.ti.com void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer) Configure and enable receive FIFO. Parameters: ulBase — is the base address of the I2S module. ulRxLevel — is the receive FIFO DMA request level. FIFO. ulWordsPerTransfer — is the nuber of words transferred from the This function configures and enable I2S receive FIFO. The parameter ulRxLevel sets the level at which receive DMA requests are generated. This should be non-zero integer multiple of number of serializers enabled as receivers. The parameter ulWordsPerTransfer sets the number of words that are transferred to the receive FIFO from the data line(s). This value must equal the number of serializers used as receivers. Returns: None. unsigned long I2SRxFIFOStatusGet (unsigned long ulBase) Get the receive FIFO status. Parameters: ulBase — is the base address of the I2S module. This function gets the number of 32-bit words currently in the receive FIFO. Returns: Returns receive FIFO status. void I2STxFIFODisable (unsigned long ulBase) Disables transmit FIFO. Parameters: ulBase — is the base address of the I2S module. This function disables the I2S transmit FIFO. 344 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Returns: None. Peripheral Library APIs for I2S Configuration void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer) Configure and enable transmit FIFO. Parameters: ulBase — is the base address of the I2S module. ulTxLevel — is the transmit FIFO DMA request level. FIFO. ulWordsPerTransfer — is the nuber of words transferred from the This function configures and enables I2S transmit FIFO. The parameter ulTxLevel sets the level at which transmit DMA requests are generated. This should be non-zero integer multiple of number of serializers enabled as transmitters The parameter ulWordsPerTransfer sets the number of words that are transferred from the transmit FIFO to the data lines. This value must equal the number of serializers used as transmitters. Returns: None. unsigned long I2STxFIFOStatusGet (unsigned long ulBase) Get the transmit FIFO status. Parameters: ulBase — is the base address of the I2S module. This function gets the number of 32-bit words currently in the transmit FIFO. Returns: Returns transmit FIFO status. SWRU367B – June 2014 – Revised October 2014 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port 345 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Chapter 13 SWRU367B – June 2014 – Revised October 2014 Analog-to-Digital Converter [ADC] Topic ........................................................................................................................... Page 13.1 Overview ......................................................................................................... 347 13.2 Key Features.................................................................................................... 347 13.3 ADC Register Mapping ...................................................................................... 348 13.4 ADC_MODULE Registers ................................................................................... 349 13.5 Initialization and Configuration .......................................................................... 370 13.6 Peripheral Library APIs for ADC Operation .......................................................... 371 346 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 13.1 Overview CC3200 provides a general purpose multi-channel Analog to Digital Converter (ADC). Each of the ADC channels supports 12-bit conversion resolution with sampling periodicity of 16uS (62.5Ksps/channel). Each channel has associated FIFO and DMA. For detailed electrical characteristics of the ADC, refer to the CC3200 Datasheet. 13.2 Key Features • Total 8 channels – 4 external analog input channels for user applications – 4 internal channels reserved for SimpleLink subsystem (Network and WiFi). • 12-bit Resolution • Fixed sampling rate of 16 μs per channel. Equivalent to 62.5 K Samples/sec per channel • Fixed round-robin sampling across all channels • Samples are uniformly spaced and interleaved. Multiple user channels can be combined together to realize higher sampling rate. For example, all four channels can be shorted together to get an aggregate sampling rate of 250KSamples/sec. • DMA interface to transfer data to the application RAM; dedicated DMA channel for each channel • Capability to timestamp ADC samples using 17 bit timer running on 40MHz clock. The user can read the timestamp along with the sample from the FIFO registers. Each sample in the FIFO contains actual data and a timestamp. Figure 13-1 shows the architecture of the ADC module in CC3200. Figure 13-1. Architecture of the ADC Module in CC3200 Figure 13-2shows the round-robin operation of the ADC. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 347 ADC Register Mapping www.ti.com Figure 13-2. Operation of the ADC 13.3 ADC Register Mapping Naming convention for ADC registers: The CC3200 ADC module supports a total of 8 analog input channels: CH0 to CH7. Each of these channels are sampled at a fixed rate of 16uS in a fixed round-robin fashion. See ADC timing diagram. Out of these, the four channels (even) are available for application processor: CH0, CH2, CH4, CH6. In the chip pin-mux description these are referred to as ADC_CH0 to ADC_CH3. Table 13-1 shows the name aliasing and the convention followed in register description in the following section of this chapter. Pin Number 57 58 59 60 N/A N/A N/A N/A Table 13-1. ADC Registers ADC Channel Name Alias in Pin Mux ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 N/A (Used internal to SoC) N/A (Used internal to SoC) N/A (Used internal to SoC) N/A (Used internal to SoC) Channel Name Used In ADC Module Register Description CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 The remaining channels (odd) are used for monitoring various internal levels by the SimpleLink subsystem in CC3200 SoC. Register bits and functions related to these internal channels are marked as reserved in the register description. These bits must not be modified by application code to ensure proper functioning of the system. 348 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC_MODULE Registers 13.4 ADC_MODULE Registers Table 13-2 lists the memory-mapped registers for the ADC_MODULE. All register offset addresses not listed in Table 13-2 should be considered as reserved locations and the register contents should not be modified. Offset 0h 24h 2Ch 34h 3Ch 44h 4Ch 54h 5Ch 64h 68h 70h 74h 7Ch 84h 8Ch 94h 9Ch A4h ACh B8h Table 13-2. ADC_MODULE Registers Acronym ADC_CTRL ADC_CH0_IRQ_EN ADC_CH2_IRQ_EN ADC_CH4_IRQ_EN ADC_CH6_IRQ_EN ADC_CH0_IRQ_STATUS ADC_CH2_IRQ_STATUS ADC_CH4_IRQ_STATUS ADC_CH6_IRQ_STATUS ADC_DMA_MODE_EN ADC_TIMER_CONFIGURATION ADC_TIMER_CURRENT_COUNT CHANNEL0FIFODATA CHANNEL2FIFODATA CHANNEL4FIFODATA CHANNEL6FIFODATA ADC_CH0_FIFO_LVL ADC_CH2_FIFO_LVL ADC_CH4_FIFO_LVL ADC_CH6_FIFO_LVL ADC_CH_ENABLE Register Name ADC control register Channel 0 interrupt enable register Channel 2 interrupt enable register Channel 4 interrupt enable register Channel 6 interrupt enable register Channel 0 interrupt status register Channel 2 interrupt status register Channel 4 interrupt status register Channel 6 interrupt status register DMA mode enable register ADC timer configuration register ADC timer current count register CH0 FIFO DATA register CH2 FIFO DATA register CH4 FIFO DATA register CH6 FIFO DATA register Channel 0 interrupt status register Channel 2 interrupt status register Channel 4 interrupt status register Channel 6 interrupt status register ADC Enable Register for Application Channels Section Section 13.4.1.1 Section 13.4.1.2 Section 13.4.1.3 Section 13.4.1.4 Section 13.4.1.5 Section 13.4.1.6 Section 13.4.1.7 Section 13.4.1.8 Section 13.4.1.9 Section 13.4.1.10 Section 13.4.1.11 Section 13.4.1.12 Section 13.4.1.13 Section 13.4.1.14 Section 13.4.1.15 Section 13.4.1.16 Section 13.4.1.17 Section 13.4.1.18 Section 13.4.1.19 Section 13.4.1.20 Section 13.4.1.21 13.4.1 ADC Register Description The remainder of this section lists and describes the ADC registers, in numerical order by address offset. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 349 ADC_MODULE Registers 13.4.1.1 ADC_CTRL Register (offset = 0h) [reset = 0h] ADC_CTRL is shown in Figure 13-3 and described in Table 13-3. Figure 13-3. ADC_CTRL Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED R-0h Bit 31-1 0 Field RESERVED ADC_EN_APPS Table 13-3. ADC_CTRL Register Field Descriptions Type R R/W Reset 0h 0h Description ADC enable for application processor www.ti.com 24 16 8 0 ADC_EN_APP S R/W-0h 350 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.2 ADC_CH0_IRQ_EN Register (offset = 24h) [reset = 0h] ADC_CH0_IRQ_EN is shown in Figure 13-4 and described in Table 13-4. ADC_MODULE Registers Figure 13-4. ADC_CH0_IRQ_EN Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL0_IRQ_EN R-0h R/W-0h Table 13-4. ADC_CH0_IRQ_EN Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL0_IRQ_E R/W N Reset 0h 0h Description Interrupt enable register for per ADC channel Bit 3: when '1' -> enable FIFO overflow interrupt Bit 2: when '1' -> enable FIFO underflow interrupt Bit 1: when "1' -> enable FIFO empty interrupt Bit 0: when "1" -> enable FIFO full interrupt SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 351 ADC_MODULE Registers 13.4.1.3 ADC_CH2_IRQ_EN Register (offset = 2Ch) [reset = 0h] ADC_CH2_IRQ_EN is shown in Figure 13-5 and described in Table 13-5. Figure 13-5. ADC_CH2_IRQ_EN Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED ADC_CHANNEL2_IRQ_EN R-0h R/W-0h www.ti.com 24 16 8 0 Table 13-5. ADC_CH2_IRQ_EN Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL2_IRQ_E R/W N Reset 0h 0h Description Interrupt enable register for per ADC channel Bit 3: when '1' -> enable FIFO overflow interrupt Bit 2: when '1' -> enable FIFO underflow interrupt Bit 1: when "1' -> enable FIFO empty interrupt Bit 0: when "1" -> enable FIFO full interrupt 352 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.4 ADC_CH4_IRQ_EN Register (offset = 34h) [reset = 0h] ADC_CH4_IRQ_EN is shown in Figure 13-6 and described in Table 13-6. ADC_MODULE Registers Figure 13-6. ADC_CH4_IRQ_EN Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL4_IRQ_EN R-0h R/W-0h Table 13-6. ADC_CH4_IRQ_EN Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL4_IRQ_E R/W N Reset 0h 0h Description Interrupt enable register for per ADC channel Bit 3: when '1' -> enable FIFO overflow interrupt Bit 2: when '1' -> enable FIFO underflow interrupt Bit 1: when "1' -> enable FIFO empty interrupt Bit 0: when "1" -> enable FIFO full interrupt SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 353 ADC_MODULE Registers 13.4.1.5 ADC_CH6_IRQ_EN Register (offset = 3Ch) [reset = 0h] ADC_CH6_IRQ_EN is shown in Figure 13-7 and described in Table 13-7. Figure 13-7. ADC_CH6_IRQ_EN Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED ADC_CHANNEL6_IRQ_EN R-0h R/W-0h www.ti.com 24 16 8 0 Table 13-7. ADC_CH6_IRQ_EN Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL6_IRQ_E R/W N Reset 0h 0h Description Interrupt enable register for per ADC channel Bit 3: when '1' -> enable FIFO overflow interrupt Bit 2: when '1' -> enable FIFO underflow interrupt Bit 1: when "1' -> enable FIFO empty interrupt Bit 0: when "1" -> enable FIFO full interrupt 354 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.6 ADC_CH0_IRQ_STATUS Register (offset = 44h) [reset = 0h] ADC_CH0_IRQ_STATUS is shown in Figure 13-8 and described in Table 13-8. ADC_MODULE Registers Figure 13-8. ADC_CH0_IRQ_STATUS Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL0_IRQ_STATUS R-0h R/W-0h Table 13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL0_IRQ_S R/W TATUS Reset 0h 0h Description Interrupt status register for per ADC channel. Interrupt status can be cleared on write. Bit 3: when value '1' is written -> would clear FIFO overflow interrupt status in the next cycle. If same interrupt is set in the same cycle then interrupt would be set and clear command will be ignored. Bit 2: when value '1' is written -> would clear FIFO underflow interrupt status in the next cycle. Bit 1: when value '1' is written -> would clear FIFO empty interrupt status in the next cycle. Bit 0: when value '1' is written -> would clear FIFO full interrupt status in the next cycle. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 355 ADC_MODULE Registers 13.4.1.7 ADC_CH2_IRQ_STATUS Register (offset = 4Ch) [reset = 0h] ADC_CH2_IRQ_STATUS is shown in Figure 13-9 and described in Table 13-9. Figure 13-9. ADC_CH2_IRQ_STATUS Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED ADC_CHANNEL2_IRQ_STATUS R-0h R/W-0h www.ti.com 24 16 8 0 Table 13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL2_IRQ_S R/W TATUS Reset 0h 0h Description Interrupt status register for per ADC channel. Interrupt status can be cleared on write. Bit 3: when value '1' is written -> would clear FIFO overflow interrupt status in the next cycle. If same interrupt is set in the same cycle then interrupt would be set and clear command will be ignored. Bit 2: when value '1' is written -> would clear FIFO underflow interrupt status in the next cycle. Bit 1: when value '1' is written -> would clear FIFO empty interrupt status in the next cycle. Bit 0: when value '1' is written -> would clear FIFO full interrupt status in the next cycle. 356 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC_MODULE Registers 13.4.1.8 ADC_CH4_IRQ_STATUS Register (offset = 54h) [reset = 0h] ADC_CH4_IRQ_STATUS is shown in Figure 13-10 and described in Table 13-10. Figure 13-10. ADC_CH4_IRQ_STATUS Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL4_IRQ_STATUS R-0h R/W-0h Table 13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL4_IRQ_S R/W TATUS Reset 0h 0h Description Interrupt status register for per ADC channel. Interrupt status can be cleared on write. Bit 3: when value '1' is written -> would clear FIFO overflow interrupt status in the next cycle. If same interrupt is set in the same cycle then interrupt would be set and clear command will be ignored. Bit 2: when value '1' is written -> would clear FIFO underflow interrupt status in the next cycle. Bit 1: when value '1' is written -> would clear FIFO empty interrupt status in the next cycle. Bit 0: when value '1' is written -> would clear FIFO full interrupt status in the next cycle. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 357 ADC_MODULE Registers 13.4.1.9 ADC_CH6_IRQ_STATUS Register (offset = 5Ch) [reset = 0h] ADC_CH6_IRQ_STATUS is shown in Figure 13-11 and described in Table 13-11. Figure 13-11. ADC_CH6_IRQ_STATUS Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED ADC_CHANNEL6_IRQ_STATUS R-0h R/W-0h www.ti.com 24 16 8 0 Table 13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions Bit 31-4 3-0 Field Type RESERVED R ADC_CHANNEL6_IRQ_S R/W TATUS Reset 0h 0h Description Interrupt status register for per ADC channel. Interrupt status can be cleared on write. Bit 3: when value '1' is written -> would clear FIFO overflow interrupt status in the next cycle. If same interrupt is set in the same cycle then interrupt would be set and clear command will be ignored. Bit 2: when value '1' is written -> would clear FIFO underflow interrupt status in the next cycle. Bit 1: when value '1' is written -> would clear FIFO empty interrupt status in the next cycle. Bit 0: when value '1' is written -> would clear FIFO full interrupt status in the next cycle. 358 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.10 ADC_DMA_MODE_EN Register (offset = 64h) [reset = 0h] ADC_DMA_MODE_EN is shown in Figure 13-12 and described in Table 13-12. ADC_MODULE Registers Figure 13-12. ADC_DMA_MODE_EN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DMA_MODEENABLE R-0h R/W-0h Table 13-12. ADC_DMA_MODE_EN Register Field Descriptions Bit 31-8 7-0 Field RESERVED DMA_MODEENABLE Type R R/W Reset 0h 0h Description This register enables DMA mode. Bit 0: channel 0 DMA mode enable. Bit 1: Reserved for internal channel Bit 2: channel 2 DMA mode enable. Bit 3: Reserved for internal channel. Bit 4: channel 4 DMA mode enable. Bit 5: Reserved for internal channel Bit 6: channel 6 DMA mode enable. Bit 7: Reserved for internal channel. 0h = Only the interrupt mode is enabled. 1h = Respective ADC channel is enabled for DMA. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 359 ADC_MODULE Registers 13.4.1.11 ADC_TIMER_CONFIGURATION Register (offset = 68h) [reset = 111111h] ADC_TIMER_CONFIGURATION is shown in Figure 13-13 and described in Table 13-13. Figure 13-13. ADC_TIMER_CONFIGURATION Register 31 30 29 28 27 26 25 RESERVED TIMEREN R-0h R/W-0h 23 22 21 20 19 18 17 TIMERCOUNT R/W-111111h 15 14 13 12 11 10 9 TIMERCOUNT R/W-111111h 7 6 5 4 3 2 1 TIMERCOUNT R/W-111111h www.ti.com 24 TIMERRESET R/W-0h 16 8 0 Bit 31-26 25 24 23-0 Table 13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions Field RESERVED TIMEREN TIMERRESET TIMERCOUNT Type R R/W R/W R/W Reset 0h 0h 0h 111111h Description 1h = Timer is enabled 1h = Reset timer Timer count configuration. 17 bit counter is supported. Other MSB's are redundant. 360 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC_MODULE Registers 13.4.1.12 ADC_TIMER_CURRENT_COUNT Register (offset = 70h) [reset = 0h] ADC_TIMER_CURRENT_COUNT is shown in Figure 13-14 and described in Table 13-14. Figure 13-14. ADC_TIMER_CURRENT_COUNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TIMERCURRENTCOUNT R-0h R-0h Bit 31-17 16-0 Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions Field Type RESERVED R TIMERCURRENTCOUNT R Reset 0h 0h Description Timer count configuration SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 361 ADC_MODULE Registers 13.4.1.13 CHANNEL0FIFODATA Register (offset = 74h) [reset = 0h] CHANNEL0FIFODATA is shown in Figure 13-15 and described in Table 13-15. www.ti.com Figure 13-15. CHANNEL0FIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_RD_DATA R-0h Table 13-15. CHANNEL0FIFODATA Register Field Descriptions Bit 31-0 Field FIFO_RD_DATA Type R Reset 0h Description Read to this register returns ADC data along with time stamp information in following format: [1:0] : Reserved [13:2] : ADC sample Bits [30:14]: time stamp per ADC sample [31] : Reserved 362 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.14 CHANNEL2FIFODATA Register (offset = 7Ch) [reset = 0h] CHANNEL2FIFODATA is shown in Figure 13-16 and described in Table 13-16. ADC_MODULE Registers Figure 13-16. CHANNEL2FIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_RD_DATA R-0h Table 13-16. CHANNEL2FIFODATA Register Field Descriptions Bit 31-0 Field FIFO_RD_DATA Type R Reset 0h Description Read to this register returns ADC data along with time stamp information in following format: [1:0] : Reserved [13:2] : ADC sample Bits [30:14]: time stamp per ADC sample [31] : Reserved SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 363 ADC_MODULE Registers 13.4.1.15 CHANNEL4FIFODATA Register (offset = 84h) [reset = 0h] CHANNEL4FIFODATA is shown in Figure 13-17 and described in Table 13-17. www.ti.com Figure 13-17. CHANNEL4FIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_RD_DATA R-0h Table 13-17. CHANNEL4FIFODATA Register Field Descriptions Bit 31-0 Field FIFO_RD_DATA Type R Reset 0h Description Read to this register returns ADC data along with time stamp information in following format: [1:0] : Reserved [13:2] : ADC sample Bits [30:14]: time stamp per ADC sample [31] : Reserved 364 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.16 CHANNEL6FIFODATA Register (offset = 8Ch) [reset = 0h] CHANNEL6FIFODATA is shown in Figure 13-18 and described in Table 13-18. ADC_MODULE Registers Figure 13-18. CHANNEL6FIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_RD_DATA R-0h Table 13-18. CHANNEL6FIFODATA Register Field Descriptions Bit 31-0 Field FIFO_RD_DATA Type R Reset 0h Description Read to this register returns ADC data along with time stamp information in following format: [1:0] : Reserved [13:2] : ADC sample Bits [30:14]: time stamp per ADC sample [31] : Reserved SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 365 ADC_MODULE Registers 13.4.1.17 ADC_CH0_FIFO_LVL Register (offset = 94h) [reset = 0h] ADC_CH0_FIFO_LVL is shown in Figure 13-19 and described in Table 13-19. www.ti.com Figure 13-19. ADC_CH0_FIFO_LVL Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL0_FIFO_LVL R-0h R-0h Table 13-19. ADC_CH0_FIFO_LVL Register Field Descriptions Bit 31-3 2-0 Field RESERVED ADC_CHANNEL0_FIFO_ LVL Type R R Reset 0h 0h Description This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4 366 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.18 ADC_CH2_FIFO_LVL Register (offset = 9Ch) [reset = 0h] ADC_CH2_FIFO_LVL is shown in Figure 13-20 and described in Table 13-20. ADC_MODULE Registers Figure 13-20. ADC_CH2_FIFO_LVL Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL2_FIFO_LVL R-0h R-0h Table 13-20. ADC_CH2_FIFO_LVL Register Field Descriptions Bit 31-3 2-0 Field RESERVED ADC_CHANNEL2_FIFO_ LVL Type R R Reset 0h 0h Description This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 367 ADC_MODULE Registers 13.4.1.19 ADC_CH4_FIFO_LVL Register (offset = A4h) [reset = 0h] ADC_CH4_FIFO_LVL is shown in Figure 13-21 and described in Table 13-21. www.ti.com Figure 13-21. ADC_CH4_FIFO_LVL Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL4_FIFO_LVL R-0h R-0h Table 13-21. ADC_CH4_FIFO_LVL Register Field Descriptions Bit 31-3 2-0 Field RESERVED ADC_CHANNEL4_FIFO_ LVL Type R R Reset 0h 0h Description This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4 368 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.4.1.20 ADC_CH6_FIFO_LVL Register (offset = ACh) [reset = 0h] ADC_CH6_FIFO_LVL is shown in Figure 13-22 and described in Table 13-22. ADC_MODULE Registers Figure 13-22. ADC_CH6_FIFO_LVL Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED ADC_CHANNEL6_FIFO_LVL R-0h R-0h Table 13-22. ADC_CH6_FIFO_LVL Register Field Descriptions Bit 31-3 2-0 Field RESERVED ADC_CHANNEL6_FIFO_ LVL Type R R Reset 0h 0h Description This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are : 0x0 to 0x4 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 369 Initialization and Configuration 13.4.1.21 ADC_CH_ENABLE Register (offset = B8h) [reset = 0h] ADC_CH_ENABLE is shown in Figure 13-23 and described in Table 13-23. Figure 13-23. ADC_CH_ENABLE Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 RESERVED R-0h 4 3 2 EXTERNAL_CH_GATE R/W-0h www.ti.com 25 24 17 16 9 8 1 0 RESERVED R-0h Table 13-23. ADC_CH_ENABLE Register Field Descriptions Bit 31-5 4-1 Field RESERVED EXTERNAL_CH_GATE Type R R/W 0 RESERVED R Reset 0h 0h 0h Description Bits[4:1] : to control ADC channel isolation switches. By default all channel analog inputs are isolated (value: 0 ). Bit1: 1 connects Channel '0' to Pin-57 (ADC_CH0) Bit2: 1 connects Channel '2' to Pin-58 (ADC_CH1) Bit3: 1 connects Channel '4' to Pin-59 (ADC_CH2) Bit4: 1 connects Channel '6' to Pin-60 (ADC_CH3) 13.5 Initialization and Configuration This section provides a pseudo code for the host initialization and configuration example, of the analog to digital converter channels. 1. Set the pin type as ADC for required pin PinTypeADC(PIN_58, 0xFF) 2. Enable the ADC channel ADCChannel Enable(ADC_BASE, ADC_CH_1) 3. Optionally configure internal timer for time stamping ADCTimerConfig(ADC_BASE, 2^17) ADCTimerEnable(ADC_BASE) 4. Enable the ADC module ADCEnable(ADC_BASE) 5. Read out the ADC samples using following code if( ADCFIFOLvlGet(ADC_BASE, ADC_CH_1) ) { ulSample = ADCFIFORead(ADC_BASE, ADC_CH_1) } 370 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.6 Peripheral Library APIs for ADC Operation Peripheral Library APIs for ADC Operation 13.6.1 Overview Four out of the eight channels of the ADC in CC3200 are used internally for the SimpleLink subsystem (NWP and WiFi). TI encourages applications to access the four external ADC channels via the Peripheral Library APIs. These APIs have been designed for optimal ADC operation of the four ADC channels available to the user, along with the internal ADC channels used for internal functionality of the device. In this section of the TRM, the emphasis is on understanding the ADC APIs provided in the CC3200 Software Development Kit (Peripheral Library). This section lists the software APIs, hosted in CC3200 SDK (Peripheral Library) that can be used by the user for easy access to ADC operation. 13.6.2 Configuring the ADC Channels Some configuration options that the application developer might need to choose from: • Enable the channel of interest (it is assumed that the user has programmed the appropriate pins as mentioned in the device data sheet). Most importantly the device pin is configured as an analog pin. • Data Transfer – CPU (FIFO Level Check and FIFO Read) or DMA • Setup interrupts • Setup timer for time stamping samples The following tables serve as a reference for values used for ulChannel and ulIntFlags: Tag ADC_CH_0 ADC_CH_1 ADC_CH_2 ADC_CH_3 Table 13-24. ulChannel Tags Value 0x00000000 0x00000008 0x00000010 0x00000018 Tag ADC_DMA_DONE ADC_FIFO_OVERFLOW ADC_FIFO_UNDERFLOW ADC_FIFO_EMPTY ADC_FIFO_FULL Table 13-25. ulIntFlags Tags Value 0x00000010 0x00000008 0x00000004 0x00000002 0x00000001 13.6.3 Basic APIs for Enabling and Configuring the Interface 13.6.3.1 void ADCEnable (unsigned long ulBase) Enables the ADC. Parameters: ulBase Base address of the ADC SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 371 Peripheral Library APIs for ADC Operation This function sets the ADC global enable. Returns: • None 13.6.3.2 void ADCDisable (unsigned long ulBase) Disable the ADC. Parameters: ulBase Base address of the ADC This function clears the ADC global enable. Returns: • None 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel) Enables specified ADC channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels This function enables specified ADC channel and configures the pin as analog pin. Returns: • None 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel) Disables specified ADC channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels This function disables specified ADC channel. Returns: • None 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup] 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel) Gets the current FIFO level for specified ADC channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels www.ti.com 372 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Peripheral Library APIs for ADC Operation This function returns the current FIFO level for specified ADC channel. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • Return the current FIFO level for specified channel 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel) Reads FIFO for specified ADC channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels This function returns one data sample from the channel fifo as specified by ulChannel parameter. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • Return one data sample from the channel FIFO. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel) Enables the ADC DMA operation for specified channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels This function enables the DMA operation for specified ADC channel. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • None. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel) Disables the ADC DMA operation for specified channel. Parameters: SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 373 Peripheral Library APIs for ADC Operation www.ti.com ulBase ulChannel Base address of the ADC One of the valid ADC channels This function disables the DMA operation for specified ADC channel. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • None. 13.6.5 APIs for Interrupt Usage 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags) Enables individual interrupt sources for specified channel. Parameters: ulBase ulChannel ulIntFlags Base address of the ADC One of the valid ADC channels the bit mask of the interrupt sources to be enabled This function enables the indicated ADC interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 The ulIntFlags parameter is the logical OR of any of: • ADC_DMA_DONE for DMA done • ADC_FIFO_OVERFLOW for FIFO over flow • ADC_FIFO_UNDERFLOW for FIFO under flow • ADC_FIFO_EMPTY for FIFO empty • ADC_FIFO_FULL for FIFO full Returns: • None 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags) Disables individual interrupt sources for specified channel. Parameters: ulBase ulChannel ulIntFlags Base address of the ADC One of the valid ADC channels the bit mask of the interrupt sources to be enabled 374 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Peripheral Library APIs for ADC Operation This function disables the indicated ADC interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor. The parametersulIntFlags and ulChannel should be as explained in ADCIntEnable(). Returns: • None 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler) Enables and registers ADC interrupt handler for specified channel. Parameters: ulBase ulChannel pfnHandler Base address of the ADC One of the valid ADC channels a pointer to the function to be called when the ADC channel interrupt occurs This function enables and registers ADC interrupt handler for specified channel. Individual interrupt for each channel should be enabled using ADCIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • None 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel) Disables and unregisters ADC interrupt handler for specified channel. Parameters: ulBase ulChannel Base address of the ADC One of the valid ADC channels This function disables and unregisters ADC interrupt handler for specified channel. This function also masks off the interrupt in the interrupt controller so that the interrupt handler no longer is called. The parameter ulChannel should be one of: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • None 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel) Gets the current channel interrupt status. Parameters: SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 375 Peripheral Library APIs for ADC Operation www.ti.com ulBase ulChannel Base address of the ADC One of the valid ADC channels This function returns the interrupt status of the specified ADC channel. See Table 13-25 The parameter ulChannel should be as explained in ADCIntEnable(). Returns: • Return the ADC channel interrupt status, enumerated as a bit field of values described in ADCIntEnable() 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags) Clears the current channel interrupt sources. Parameters: ulBase ulChannel ulIntFlags Base address of the ADC One of the valid ADC channels Bit mask of the interrupt sources to be cleared This function clears individual interrupt source for the specified ADC channel. The parameter ulChannel should be as explained in ADCIntEnable(). Returns: • None 13.6.6 APIs for Setting Up ADC Timer for Time Stamping the Samples 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue) Configures the ADC internal timer. Parameters: ulBase ulValue Base address of the ADC Wrap around value of the timer This function Configures the ADC internal timer. The ADC timer is 17-bit timer used to timestamp the ADC data samples internally. You can read the timestamp along with the sample from the FIFO registers. Each sample in the FIFO contains 14-bit actual data and an 18-bit timestamp. The parameter ulValue can take any value between 0 and 2^17. Returns: • None 13.6.6.2 void ADCTimerDisable (unsigned long ulBase) Disables ADC internal timer. Parameters: ulBase Base address of the ADC 376 Analog-to-Digital Converter [ADC] SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com This function disables 17-bit ADC internal timer. Returns: • None Peripheral Library APIs for ADC Operation 13.6.6.3 void ADCTimerEnable (unsigned long ulBase) Enables ADC internal timer. Parameters: ulBase Base address of the ADC This function enables the 17-bit ADC internal timer. Returns: • None 13.6.6.4 void ADCTimerReset (unsigned long ulBase) Resets ADC internal timer. Parameters: ulBase Base address of the ADC This function resets the 17-bit ADC internal timer. Returns: • None 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase) Gets the current value of ADC internal timer. Parameters: ulBase Base address of the ADC This function the current value of the 17-bit ADC internal timer. Returns: • Returns the current value of the ADC internal timer. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Analog-to-Digital Converter [ADC] 377 Chapter 14 SWRU367B – June 2014 – Revised October 2014 Parallel Camera Interface Module Topic ........................................................................................................................... Page 14.1 Overview ......................................................................................................... 379 14.2 Image Sensor Interface ..................................................................................... 379 14.3 Functional Description ...................................................................................... 380 14.4 Programming Model.......................................................................................... 384 14.5 Interrupt Handling............................................................................................. 385 14.6 Camera Interface Module Functional Registers .................................................... 386 14.7 Developer’s Guide ............................................................................................ 400 378 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 14.1 Overview The CC3200 camera core module can be used to interface an external image sensor. It supports an 8 bit parallel image sensor interface (Non-BT) interface with vertical and horizontal synchronization signals. BT mode is not supported. Recommended maximum pixel clock is 1 MHz. The module stores the image data in a FIFO and can generate DMA requests. Figure 14-1 shows how the camera core is connected to the rest of the system in CC3200. Figure 14-1. The Camera Module Interfaces 14.2 Image Sensor Interface Table below lists the image-sensor interface signals. Interface Name CAM_P_HS CAM_P_VS CAM_MCLK CAM_XCLK CAM_P_DATA [11:4] Table 14-1. Image sensor interface signals I/O Description I Row trigger input signal. The polarity of CAM_P_HS can be reversed. I Frame trigger input signal. The polarity of CAM_P_VS can be reversed. I Input clock used to derive the external clock for the image sensor clock (see paragraph 4.4). O External clock for the image sensor module. This clock is derived from the functional clock (see paragraph 4.4). I Parallel input data bits. Upper 8 bits of the interface are connected to 8-bits from image sensor. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 379 Functional Description www.ti.com Table 14-1. Image sensor interface signals (continued) Interface Name CAM_P_CLK I/O Description Latch clock for the parallel input data. The data on the parallel interface I are presented on CAM_P_DATA, one pixel for every CAM_P_CLK rising or falling edge. 14.3 Functional Description The camera core is used to transfer data from the image sensor into the buffer (FIFO) and to generate DMA requests (one working on the threshold, the other on the remaining data in the FIFO to complete the frame acquisition. The camera interface can provide a clock to the external image sensor module (CAM_XCLK). This clock is derived from the functional clock CAM_MCLK. 14.3.1 Modes of Operation The camera interface uses the CAM_P_HS and CAM_P_VS signal to be able to detect when the data is valid. This configuration can work with 8-bit data. No assumptions are made on the data format. The pixel data is presented on CAM_P_DATA one pixel for every CAM_P_CLK rising edge (or falling depending on the configuration of CAM_P_CLK polarity, defined in CC_CTRL.PAR_CLK_POL). There are additional pixel times between rows that represent a blanking period. The active pixels are identified by a combination of two additional timing signals: horizontal synchronization (CAM_P_HS) and vertical synchronization (CAM_P_VS). During the image sensor readout, these signals define when a row of valid data begins and ends and when a frame starts and ends. A bit field sets the CAM_P_HS polarity (NOBT_HS_POL) and CAM_P_VS polarity (NOBT_VS_POL). Figure 14-2. Synchronization Signals and Frame Timing Note that the clock CAM_P_CLK is running during blanking periods (CAM_P_HS and CAM_P_VS inactive) and a minimum of 10 clock cycles are required between two consecutive CAM_P_VS active for proper operations when the line is not a multiple of 12 bytes, otherwise 1 clock cycle is enough to detect CAM_P_VS and work properly. Figure 14-3. Synchronization Signals and Data Timing The acquisition can start either on a beginning of a new frame (CAM_P_VS inactive and then active) or immediately in function of the CC_CTRL.NOBT_SYNCHRO register bit. Please set CC_CTRL.NOBT_SYNCHRO to ‘1’ to ensure a clean acquisition of the frame. The following scenarios are also allowed, in other words data is accepted as long as CAM_P_HS, CAM_P_VS are both active (when CC_CTRL.NOBT_SYNCHRO is cleared 0): 380 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description Figure 14-4. Different Scenarios of CAM_P_HS and CAM_P_VS The camera core module supports decimation from the image sensor where CAM_P_HS toggles between pixels. Figure 14-5. CAM_P_HS Toggles Between Pixels in Decimation Figure 14-6. Parallel Camera I/F State Machine SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 381 Functional Description www.ti.com Image data is stored differently in the FIFO depending on the setting of the bit PAR_ORDERCAM as shown in Figure 14-7. Figure 14-7. FIFO Image Data Format NOTE: Blanking period is removed automatically by the module. 14.3.2 FIFO Buffer The internal data FIFO buffer is a 32 bit wide, 64 locations deep. Received data from the 8-bit parallel interface is stored in the buffer until read out by the CPU, which accesses the buffer by reading locations starting at CC_FIFO_DATA register. When enabled, the buffer can generate DMA request based on FIFO_CTRL_DMA.THRESHOLD value. The FIFO goes into overflow when a write is attempted to a full FIFO, this is due to the software being too slow or the throughput being too high. The content of the full FIFO is not corrupted by any further writes. During FIFO overflow, it is still possible to read data from the FIFO. Once the FIFO is not full anymore, more writes are also possible. The FIFO goes into overflow when a write is attempted to a full FIFO, this is due to the software being too slow or the throughput being too high. The content of the full FIFO is not corrupted by any further writes. During FIFO overflow, it is still possible to read data from the FIFO. Once the FIFO is not full anymore, more writes are also possible. The FIFO goes into underflow when a read is attempted from an empty FIFO, this is due to software (too many read accesses). After an underflow, it’s still possible to write and once the FIFO is no longer empty, it’s possible to read from FIFO. The FIFO is reset by writing a “1” into CC_CTRL.CC_RST. If FIFO_OF_IRQ is enabled, (or FIFO_UF_IRQ) an overflow (or an underflow) will generate an interrupt. The interrupt is cleared by writing a “1” to the bit FIFO_OF_IRQ (or FIFO_UF_IRQ) – no need to apply CC_RST beforehand. 382 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Functional Description 14.3.3 Reset The camera core has three types of reset: 1. Reset of the Camera Core – Reset the camera core module globally by setting to “1’ the bit CC_SYSCONFIG.SoftReset. 2. Reset of the FIFOs and DMA control – The internal state machines of the FIFO and the DMA control circuitry are reset by setting to “1” the bit CC_CTRL.CC_RST. This bit is mainly used after an underflow or an overflow to avoid re-configuring the entire module. 14.3.4 Clock Generation The module divides down CAM_MCLK and generates CAM_XCLK clock to the external camera sensor. The configuration of the CAM_XCLK divider is programmable by setting the configuration register CC_CTRL_XCLK CAM_XCLK is not used by the camera core module itself. It is routed to the chip pin. Table 14-2. Ratio of the XCLK Frequency Generator Ratio 0 (default) 1 2 3 4 5 6 7 8 9 10 11 12 ... 30 31 XCLK Based on CAM_MCLK ( CAM_MCLK = 120MHz) Stable Low level, Divider not enabled Stable High level, Divider not enabled 60 MHz (division by 2) 40 MHz (division by 3) 30 MHz 24 MHz 20 MHz 17.14 MHz 15 MHz 13.3 MHz 12 MHz 10.91 MHz 10 MHz ... 4 MHz (division by 30) Bypass (CAM_XCLK = CAM_MCLK) 14.3.5 Interrupt Generation The interrupt line is asserted (active low) when one the following events, takes place: • FIFO_UF – FIFO underflow • FIFO_OF – FIFO overflow • FIFO_THR – FIFO threshold • FIFO_FULL – FIFO full • FIFO_NOEMPTY – FIFO not empty (can be used to detect that a first data is written) • FE – Frame End When the read of the register CC_IRQSTATUS occurs, the register is not automatically reset. In order to reset the interrupt a ‘1’ must be written to the correspondent bit. Each event that generates an interrupt can be individually enabled using the CC_IRQENABLE. When a particular event is not enabled (for example CC_IRQENABLE[5] = 0), the correspondent status (CC_IRQSTATUS[5] = 1) bit will be flagged if the correspondent event occurs. Clearly this has no effect on the interrupt line but can be used by any software to poll the status. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 383 Functional Description www.ti.com 14.3.6 DMA Interface The camera core module interfaces with a DMA controller. At system level, the advantage is to discharge the CPU of the data transfers. The module is able to generate DMA request when the FIFO reaches the threshold programmed into CC_CTRL_DMA.FIFO_THRESHOLD The de-assertion of the DMA request takes place when a number of 32-bit words equal to the FIFO threshold have been read by the DMA controller. The DMA assertion and de-assertion is illustrated in the following figure where it is assumed a FIFO threshold of 8 plus some remaining data to end the frame acquisition. Figure 14-8. Assertion and De-assertion of the DMA Request Signal 14.4 Programming Model This section deals with the programming model of the Camera Core module. 14.4.1 Camera Core Reset The camera core module is able to accept a general software reset, propagated through all the hierarchy. This reset can be done to initialize the module and has the same effect as the hardware reset. 1. Set CC_SYSCONFIG.SOFTRESET to “1” 2. Read CC_SYSSTATUS.RESETDONE to check if it is “1”, meaning the reset took place. If after 5 reads, CC_SYSSTATUS.RESETDONE still returns 0, it can be assumed that an error occurred during the reset stage. The programmer should not set the bit CC_SYSCONFIG.SOFTRESET to “1” if the camera core module is integrated in a subsystem, it is safer to use the software reset at subsystem level. 14.4.2 Enable the Picture Acquisition The camera core module must be set using the following programming model provided below: 384 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Programming Model 1. Configure the interrupt generation as required using the CC_IRQSTATUS and CC_IRQENABLE registers (most common are overflow and underflow interrupts). 2. CC_CTRL_DMA.FIFO_THRESHOLD must be set to a specific value (depends on the DMA module) and CC_CTRL_DMA.DMA_EN must be set to ‘1’ for normal usage of the module. 3. Configure the CC_CTRL_XCLK. 4. Enable the picture acquisition using the CC_CTRL. We recommend people to set CC_FRAME_TRIG and NOBT_SYNCHRO to ‘1’when CC_EN is set to ‘1’ to start the acquisition. If software wants to acquire only one frame acquisition, please use the CC_ONE_SHOT register bit (In that case, the module will be automatically disabled by itself at the end of the frame). 14.4.3 Disable the Picture Acquisition In order to end the picture acquisition, use the CC_CTRL.CC_EN to ‘0’ in conjunction with CC_CTRL.CC_FRAME_TRIG to ‘1’ to disable properly the frame acquisition. In that case, the camera core will end the current frame at the end or stop immediately if there is no frame on going. 14.5 Interrupt Handling 14.5.1 FIFO_OF_IRQ (FIFO overflow) 1. Set CC_CTRL.CC_EN to 0 and CC_CTRL.CC_FRAME_TRIG to 0, thus stopping the data flow from the image sensor. 2. Clear the interrupt, by writing “1” to the CC_IRQSTATUS.FIFO_OF_IRQ bit. 3. If the CC_CTRL_DMA.DMA_EN bit is set to 0, the CPU may want to keep reading the FIFO_DATA register or decide to just stop reading. If the CC_CTRL_DMA.EN bit is set to 1, the CPU may want to stop immediately the DMA or to let it run until there are no more DMA requests. 4. Reset FIFO pointers and internal camera core state machines, by writing “1” to the CC_CTRL.CC_RST bit. 5. Set the CC_CTRL.CC_EN bit to 1, to re-enable the data flow from the image sensor. If an overflow occurs, the entire dataflow path must be reset in order to restart in a clean way (for example, the DMA controller). 14.5.2 FIFO_UF_IRQ (FIFO underflow) 1. Set the CC_CTRL.CC_EN bit to 0 and the CC_CTRL.CC_FRAME_TRIG bit to 0, thus stopping the data flow from the image sensor. 2. Clear the interrupt, by writing “1” to the CC_IRQSTATUS.FIFO_UF_IRQ bit. 3. Reset FIFO pointers and internal camera core state machines, by writing “1” to the CC_CTRL.CC_RST bit. 4. Set the CC_CTRL.CC_EN bit to 1, to re-enable the data flow from the image sensor. If an underflow occurs, the entire dataflow path must be reset in order to restart in a clean way (for example, the DMA controller). SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 385 Camera Interface Module Functional Registers www.ti.com 14.6 Camera Interface Module Functional Registers Table 14-3 lists the memory-mapped registers for the camera interface. All register offset addresses not listed in Table 14-3 should be considered as reserved locations and the register contents should not be modified. It is highly recommended to use the API's instead of directly accessing the register bits in this module. Offset Acronym 10h CC_SYSCONFIG 14h CC_SYSSTATUS 18h CC_IRQSTATUS 1Ch CC_IRQENABLE 40h CC_CTRL 44h CC_CTRL_DMA 48h CC_CTRL_XCLK 100h to CC_FIFODATA 1FCh Table 14-3. CAMERA REGISTERS Register Name System Configuration Register Type R/W System Status Register R Interrupt Status Register R/W Interrupt Enable Register R/W Control Register R/W Control DMA Register R/W External Clock Control Register R/W FIFO Data Register R Reset 0h 0h 0h 0h 1001h 16Fh 0h 0h Section Section 14.6.1.1 Section 14.6.1.2 Section 14.6.1.3 Section 14.6.1.4 Section 14.6.1.5 Section 14.6.1.6 Section 14.6.1.7 Section 14.6.1.8 14.6.1 Functional Register Description The remainder of this section lists and describes the camera interface module functional registers, in numerical order by address offset. 386 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.1 CC_SYSCONFIG Register (offset = 10h) [reset = 0h] CC_SYSCONFIG is shown in Figure 14-9 and described in Table 14-4. This register controls the various parameters of the OCP interface (CCP and Parallel Mode) Figure 14-9. CC_SYSCONFIG Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 RESERVED R-0h 4 3 SIdleMode R/W-0h 2 RESERVED R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 17 9 1 SoftReset R/W-0h 24 16 8 0 AutoIdle R/W-0h Bit 31-5 4-3 Field RESERVED SIdleMode 2 RESERVED 1 SoftReset 0 AutoIdle Table 14-4. CC_SYSCONFIG Register Field Descriptions Type R R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h Description Slave interface power management, req/ack control 00h = Force-idle. An idle request is acknowledged unconditionally 01h = No-idle. An idle request is never acknowledged 10h = reserved (Smart-idle not implemented) 11h = Reserved - do not use Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reset it always returns 0. 0h = Normal mode 1h = The module is reset Internal OCP clock gating strategy 0h = OCP clock is free-running 1h = Automatic OCP clock gating strategy is applied, based on the OCP interface activity SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 387 Camera Interface Module Functional Registers www.ti.com 14.6.1.2 CC_SYSSTATUS Register (offset = 14h) [reset = 0h] Register mask: FFFFFFFEh CC_SYSSTATUS is shown in Figure 14-10 and described in Table 14-5. This register provides status information about the module excluding the interrupt status information (CCP and Parallel Mode) Figure 14-10. CC_SYSSTATUS Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 1 0 ResetDone R-X Bit 31-1 0 Field RESERVED ResetDone Table 14-5. CC_SYSSTATUS Register Field Descriptions Type R R Reset 0h X Description Internal Reset Monitoring 0h = Internal module reset is on-going 1h = Reset completed 388 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.3 CC_IRQSTATUS Register (offset = 18h) [reset = 0h] CC_IRQSTATUS is shown in Figure 14-11 and described in Table 14-6. The interrupt status regroups all the status of the module internal events that can generate an interrupt (CCP and Parallel Mode) Figure 14-11. CC_IRQSTATUS Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED FS_IRQ LE_IRQ LS_IRQ FE_IRQ R-0h R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 RESERVED FSP_ERR-IRQ FW_ERR_IRQ FSC_ERR_IRQ SSC_ERR_IRQ R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED FIFO_NOEMPT FIFO_FULL_IR FIFO_THR_IR FIFO_OF_IRQ FIFO_UF_IRQ Y_IRQ Q Q R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-20 19 Field RESERVED FS_IRQ 18 LE_IRQ 17 LS_IRQ 16 FE_IRQ 15-12 11 RESERVED FSP_ERR-IRQ Table 14-6. CC_IRQSTATUS Register Field Descriptions Type R R/W R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description Frame Start has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Line End has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Line Start has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Frame End has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FSP code error 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 389 Camera Interface Module Functional Registers Table 14-6. CC_IRQSTATUS Register Field Descriptions (continued) Bit Field 10 FW_ERR_IRQ Type R/W 9 FSC_ERR_IRQ R/W 8 SSC_ERR_IRQ R/W 7-5 RESERVED R/W 4 FIFO_NOEMPTY_IRQ R/W 3 FIFO_FULL_IRQ R/W 2 FIFO_THR_IRQ R/W 1 FIFO_OF_IRQ R/W 0 FIFO_UF_IRQ R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Frame Height Error 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") False Synchronization Code 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Shifted Synchronization Code 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FIFO is not empty 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FIFO is full 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FIFO threshold has been reached 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FIFO overflow has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") FIFO underflow has occurred 0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") www.ti.com 390 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.4 CC_IRQENABLE Register (offset = 1Ch) [reset = 0h] CC_IRQENABLE is shown in Figure 14-12 and described in Table 14-7. The interrupt enable register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis (CCP and Parallel Mode) Figure 14-12. CC_IRQENABLE Register 31 30 29 28 27 26 25 24 RESERVED R/W-0h 23 22 21 20 19 18 17 16 RESERVED FS_IRQ_EN LE_IRQ_EN LS_IRQ_EN FE_IRQ_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 RESERVED FSP_ERR_IRQ FW_ERR_IRQ_ FSC_ERR_IRQ SSC_ERR_IRQ _EN EN _EN _EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED FIFO_NOEMPT FIFO_FULL_IR FIFO_THR_IR FIFO_OF_IRQ_ FIFO_UF_IRQ_ Y_IRQ_EN Q_EN Q_EN EN EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-20 19 18 17 16 15-12 11 10 9 8 7-5 Table 14-7. CC_IRQENABLE Register Field Descriptions Field RESERVED FS_IRQ_EN Type R/W R/W LE_IRQ_EN R/W LS_IRQ_EN R/W FE_IRQ_EN R/W RESERVED R/W FSP_ERR_IRQ_EN R/W FW_ERR_IRQ_EN R/W FSC_ERR_IRQ_EN R/W SSC_ERR_IRQ_EN R/W RESERVED R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Frame Start Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Line End Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Line Start Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Frame End Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs FSP code Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Frame Height Error Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs False Synchronization Code Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs False Synchronization Code Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 391 Camera Interface Module Functional Registers Table 14-7. CC_IRQENABLE Register Field Descriptions (continued) Bit Field Type 4 FIFO_NOEMPTY_IRQ_E R/W N 3 FIFO_FULL_IRQ_EN R/W 2 FIFO_THR_IRQ_EN R/W 1 FIFO_OF_IRQ_EN R/W 0 FIFO_UF_IRQ_EN R/W Reset 0h 0h 0h 0h 0h Description FIFO Not Empty Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs FIFO Full Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs FIFO Threshold Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs FIFO Overflow Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs FIFO Underflow Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs www.ti.com 392 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.5 CC_CTRL Register (offset = 40h) [reset = 1001h] CC_CTRL is shown in Figure 14-13 and described in Table 14-8. This register controls the various parameters of the Camera Core block (CCP and Parallel Mode). In CCP_MODE, you must configure PAR_MODE to 0x0. Figure 14-13. CC_CTRL Register 31 30 29 28 27 26 25 24 RESERVED R/W-0h 23 22 21 20 19 18 17 16 RESERVED CC_ONE_SHO CC_IF_SYNCH T RO CC_RST CC_FRAME_T RIG CC_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 15 14 RESERVED R/W-0h 13 NOBT_SYNCH RO R/W-0h 12 BT_CORRECT R/W-1h 11 10 9 PAR_ORDERC PAR_CLK_POL NOBT_HS_PO AM L R/W-0h R/W-0h R/W-0h 8 NOBT_VS_PO L R/W-0h 7 6 5 4 3 2 1 0 RESERVED PORT_SELEC T PAR_MODE R/W-0h R/W-0h R/W-1h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-21 20 Field RESERVED CC_ONE_SHOT 19 CC_IF_SYNCHRO 18 CC_RST 17 CC_FRAME_TRIG 16 CC_EN 15-14 RESERVED Table 14-8. CC_CTRL Register Field Descriptions Type R/W R/W R/W R/W R/W R/W R/W Reset 0h 0h 0h 0h 0h 0h 0h Description One shot capability (One frame captured) This must be set in the same time ass CC_EN is set to '1'. One frame acquisition will start/stop automatically Reads returns 0 0h = No synchro (most of applications) 1h = Synchro enabled (should never be required) Synchronize all camera sensor inputs This must be set during the configuration phase before CC_EN set to '1'. This can be used in very high frequency to avoid dependancy to the IO timings. 0h = No synchro (most of applications) 1h = Synchro enabled (should never be required) Resets all the internal finite states machines of the camera core module - by writing a 1 to this bit. Must be applied when CC_EN = 0 Reads returns 0 Set the modality in which CC_EN works when a disabling of the sensor camera core is wanted. If CC_FRAME_TRIG = 1, by writing "0" to CC_EN the module is disabled at the end of the frame If CC_FRAME_TRIG = 0, by writing "0" to CC_EN the module is disabled immediately Enables the sensor interface of the camera core module By writing "1" to this field, the module is enabled By writing "0" to this field, the module is disabled at the end of the frame if CC_FRAME_TRIG = 1 and is disabled immediately if CC_FRAME_TRIG = 0 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 393 Camera Interface Module Functional Registers www.ti.com Table 14-8. CC_CTRL Register Field Descriptions (continued) Bit Field 13 NOBT_SYNCHRO 12 BT_CORRECT 11 PAR_ORDERCAM 10 PAR_CLK_POL 9 NOBT_HS_POL 8 NOBT_VS_POL 7-5 RESERVED 4 PORT_SELECT 3-0 PAR_MODE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0h 1h 0h 0h 0h 0h 0h 0h 1h Description Enables to start at the beginning of the frame or not in NoBT 0h = Acquisition starts when Vertical synchro is high 1h = Acquisition starts when Vertical synchro goes from low to high (beginning of the frame) - Recommended Enables the correct within the sync codes in BT mode 0h = correction is not enabled 1h = correction is enabled Enables swap between image-data in parallel mode 0h = swap is not enabled 1h = swap is enabled Inverts the clock coming from the sensor in parallel mode 0h = clock not inverted - data sampled on rising edge 1h = clock inverted - data sampled on falling edge Sets the polarity of the synchronization signals in NOBT parallel mode 0h = CAM_P_HS is active high 1h = CAM_P_HS is active low Sets the polarity of the synchronization signals in NOBT parallel mode 0h = CAM_P_VS is active high 1h = CAM_P_VS is active low Determines which OCP port can perform read access from internal FIFO when DMA_EN bit is set to 1 0h = OCP 2 1h = OCP 1 Sets the Protocol Mode of the Camera Core module in parallel mode (when CCP_MODE = 0) 000h = Parallel NOBT 8-bit 001h = Parallel NOBT 10-bit 010h = Parallel NOBT 12-bit 011h = reserved 100h = Parallel BT 8-bit 101h = Parallel BT 10-bit 110h = reserved 111h = FIFO test mode. Refer to Table 12 - FIFO Write and Read access 394 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.6 CC_CTRL_DMA Register (offset = 44h) [reset = 16Fh] CC_CTRL_DMA is shown in Figure 14-14 and described in Table 14-9. This register controls the DMA interface of the Camera Core block (CCP and Parallel Mode) Figure 14-14. CC_CTRL_DMA Register 31 30 29 28 27 26 RESERVED R/W-0h 23 22 21 20 19 18 RESERVED R/W-0h 15 14 13 12 11 10 RESERVED R/W-0h 7 6 5 4 3 2 RESERVED FIFO_THRESHOLD R/W-0h R/W-7h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset 25 24 17 16 9 8 DMA_EN R/W-1h 1 0 Table 14-9. CC_CTRL_DMA Register Field Descriptions Bit 31-9 8 Field RESERVED DMA1_DISABLE Type R/W R/W 8 DMA_EN R/W 7 RESERVED R/W 6-0 FIFO_THRESHOLD R/W Reset 0h 1h 1h 0h 7h Description DMA1 disable capability. Only use DMA0 (threshold based) 0h = DMA1 line can be activated 1h = DMA1 line can not be activated Sets the number of dma request lines 0h = DMA interface disabled. The DMA request line stays inactive 1h = DMA interface enabled. The DMA request line is operational Sets the threshold of the FIFO The assertion of the dma request line takes place when the threshold is reached 0000000h = threshold set to 1 0000001h = threshold set to 2 ... 1111111h = threshold set to 128 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 395 Camera Interface Module Functional Registers www.ti.com 14.6.1.7 CC_CTRL_XCLK Register (offset = 48h) [reset = 0h] CC_CTRL_XCLK is shown in Figure 14-15 and described in Table 14-10. This register controls the value of the clock divisor used to generate the external clock (Parallel Mode). Please refer to the table given in section "clock generation" for details about the ratio of XCLK frequency. Figure 14-15. CC_CTRL_XCLK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R/W-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XCLK_DIV R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-5 4-0 Field RESERVED XCLK_DIV Table 14-10. CC_CTRL_XCLK Register Field Descriptions Type R/W R/W Reset 0h 0h Description Sets the clock divisor value for CAM_XCLK generation. Based on CAM_MCLK (value of CAM_MCLK IS 96MHz). Divider not enabled Divider not enabled 00000h = CAM_XCLK Stable Low Level 00001h = CAM_XCLK Stable High Level from 2 to 30 = CAM_XCLK = CAM_MCLK / XCLK DIV 11111h = Bypass - CAM_XCLK = CAM_MCLK 396 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers 14.6.1.8 CC_FIFODATA Register (offset = 4Ch) [reset = 0h] Register mask: 0h CC_FIFODATA is shown in Figure 14-16 and described in Table 14-11. This register allows to write to the FIFO and read from the FIFO (CCP and Parallel Mode). Please refer to the table provided in section FIFO for details about FIFO write and read accesses into this register bank. Figure 14-16. CC_FIFODATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_DATA R/W-X LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Bit 31-0 Field FIFO_DATA Table 14-11. CC_FIFODATA Register Field Descriptions Type R/W Reset X Description Reads/writes the 32-bit word from/into the FIFO 14.6.2 Peripheral Library APIs This section lists the software APIs, hosted in CC3200 SDK (Peripheral Library) for configuring and using the camera interface module. void CameraReset(unsigned long ulBase) • Description: This function resets the camera core • Parameters: – ulBase Base address of the camera module. • Return: None void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, unsigned long ulXClk) • Description: This function sets the internal clock divider based on ulCamClkIn to generate XCLK as specified be ulXClk. Maximum supported division is 30 • Parameters: – ulBase Base address of the camera module. – ulCamClkIn Input clock frequency to camera module – ulXClk Required XCLK frequency • Return: None void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, unsigned long ulVSPol, unsigned long ulFlags) • Description: This function sets different camera parameters. • Parameters: – ulBase Base address of the camera module. – ulHSPol sets the HSync polarity – ulVSPol Sets the VSync polarity – ulFlags Configuration flags The parameter ulHSPol should be on the following: – CAM_HS_POL_HI HSYNC Polarity is active high – CAM_HS_POL_LO HSYNC Polarity is active low The parameter ulVSPol should be on the following: – CAM_VS_POL_HI VSYNC Polarity is active high – CAM_VS_POL_LO VSYNC Polarity is active low SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 397 Camera Interface Module Functional Registers www.ti.com The parameter ulFlags can be logical OR of one or more of the following or 0: – CAM_PCLK_RISE_EDGE PCLK Polarity is active high – CAM_PCLK_FALL_EDGE PCLK Polarity is active low – CAM_ORDERCAM_SWAP Swap the byte order – CAM_NOBT_SYNCHRO Enable to start capture at start of frame – CAM_IF_SYNCHRO Synchronize all sensor inputs • Return: None void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags) • Description: This function sets the internal divide in specified mode. • Parameters: – ulBase Base address of the camera module. – bXClkFlags Sets the divider mode The parameter bXClkFlags should be one of the following: – CAM_XCLK_STABLE_LO XCLK line will be pulled low – CAM_XCLK_STABLE_HI XCLK line will be pulled high – CAM_XCLK_DIV_BYPASS XCLK divider is in bypass mode • Return: None void CameraDMAEnable(unsigned long ulBase) • Description: This function enables transfer request to DMA from camera. DMA specific configuration has to be done separately. • Parameters: – ulBase Base address of the camera module. • Return: None void CameraDMADisable(unsigned long ulBase) • Description: This function masks transfer request to DMA from camera • Parameters: – ulBase Base address of the camera module. • Return: None void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold) • Description: This function sets the FIFO threshold for DMA transfer request. • Parameters: – ulBase Base address of the camera module – ulThreshold Specifies FIFO level at which DMA request is generated. This can be in range 1 to 64. • Return: None void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) • Description: This function registers and enables global camera interrupt from the interrupt controller. Individual camera interrupts source should be enabled using CameraIntEnable(). • Parameters: – ulBase Base address of the camera module. • Return: None void CameraIntUnregister(unsigned long ulBase) • Description: This function unregisters and disables global camera interrupt from the interrupt controller. • Parameters: – ulBase Base address of the camera module. 398 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Camera Interface Module Functional Registers • Return: None. void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags) • Description: This function enables individual camera interrupt sources. • Parameters: – ulBase Base address of the camera module. – ulIntFlags Bit mask of the interrupt sources to be enabled The parameter ulIntFlags should be logical OR of one or more of the following: – CAM_INT_DMA DMA done interrupt – CAM_INT_FE Frame end interrupt – CAM_INT_FSC_ERR Frame sync error interrupt – CAM_INT_FIFO_NOEMPTY FIFO empty interrupt – CAM_INT_FIFO_FULL FIFO full interrupt – CAM_INT_FIFO_THR FIFO reached threshold interrupt – CAM_INT_FIFO_OF FIFO overflow interrupt – CAN_INT_FIFO_UR FIFO underflow interrupt • Return: None void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags) • Description: This function disables individual camera interrupt sources • Parameters: – ulBase Base address of the camera module. – ulIntFlags Bit mask of the interrupt sources to be disabled • Return: None unsigned long CameraIntStatus(unsigned long ulBase) • Description: This functions returns the current interrupt status for the camera. • Parameters: – ulBase Base address of the camera module. • Return: Returns the current interrupt status, enumerated as a bit field of values described in CameraIntEnable(). void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags) • Description: This function Clears individual camera interrupt sources. • Parameters: – ulBase Base address of the camera module. – ulIntFlags Bit mask of the interrupt sources to be Cleared • Return: None void CameraCaptureStart(unsigned long ulBase) • Description: This function starts the image capture over the configured camera interface. This function should be called after configuring the camera module completely • Parameters: – ulBase Base address of the camera module. • Return: None void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate) • Description: This function stops the image capture over the camera interface. The capture is stopped either immediately or at the end of current frame based on bImmediate parameter. • Parameters: – ulBase Base address of the camera module. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 399 Developer’s Guide www.ti.com – bImmediate True to stop capture immediately, False to stop at end of frame • Return: None void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer, unsigned char ucSize) • Description: This function reads the camera buffer (FIFO). • Parameters: – ulBase Base address of the camera module. – pBuffer Pointer to the read buffer – ucSize Size to data to be read • Return: None 14.7 Developer’s Guide 14.7.1 Using Peripheral Driver APIs for Capturing an Image First, the clock for camera peripheral needs to be configured and enabled. Peripherals are clock gated by default and will generate a bus fault if accessed without enabling the clock. The peripheral will be ready to use after the software reset: MAP_PRCMPeripheralClkEnable(PRCM_CAMERA, PRCM_RUN_MODE_CLK); MAP_PRCMPeripheralReset(PRCM_CAMERA); The camera parameters must be set next using the peripheral driver API ‘CameraParamsConfig.' This function sets the appropriate bits in register CAMERA_O_CC_CTRL for controlling the various parameters of the camera control block. The parameters are: • ulHSPol: Sets the horizontal synchronization signal’s (‘CAM_P_HS’) polarity. It can be either ‘CAM_HS_POL_HI’ or ‘CAM_HS_POL_LO.’ • ulHSPol: Sets the vertical synchronization signal’s (‘CAM_P_VS’) polarity. It can be either ‘CAM_VS_POL_HI’ or ‘CAM_VS_POL_LO’ • ulFlags: – Should be set to (CAM_ORDERCAM_SWAP | CAM_NOBT_SYNCHRO) for starting acquisition/capture when ‘CAM_P_VS’ goes from low to high and swapping image data in FIFO. See Section 14.3.1 for more details. – Should be set to CAM_NOBT_SYNCHRO for starting acquisition/capture when ‘CAM_P_VS’ goes from low to high without swapping the image-data in FIFO. For high frequency operations, set ‘CAM_IF_SYNCHRO’ to avoid dependency on the IO timings. The interrupt-handler must be registered next using the peripheral driver API ‘CameraIntRegister.' This function registers and enables global camera interrupts from the interrupt controller. The external-clock must be derived next by programming the clock-divider values. Peripheral driver API ‘CameraXClkConfig’ sets the appropriate bits in this register for setting the internal clock divider. MCLK is by-default set to 120MHz, and cannot be modified. Hence, an XCLK of: • 5MHz can be derived by calling: CameraXClkConfig(CAMERA_BASE, 120000000, 5000000) • 10MHz can be derived by calling: CameraXClkConfig(CAMERA_BASE, 120000000, 10000000) Note: The maximum supported division is 30; a 2MHz XCLK cannot be derived using a 120MHz MCLK. The FIFO threshold must be set next using the peripheral driver API ‘CameraThresholdSet.' This function sets the threshold at which to generate a DMA request. CameraThresholdSet(CAMERA_BASE, 8); For handling the image data that’s not a multiple of FIFO threshold, the Frame-End interrupt needs to be registered using the peripheral API ‘CameraIntEnable.' This will generate an interrupt at the end of every frame: CameraIntEnable(CAMERA_BASE, CAM_INT_FE) 400 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Developer’s Guide The DMA interface of the camera control block must be enabled next by using the peripheral driver API ‘CameraDMAEnable.’ CameraDMAEnable(CAMERA_BASE) The DMA interface of the camera control block must be configured next. As an exmaple, configure the DMA in Ping-Pong mode: • First initialize the DMA interface using the peripheral driver API ‘UDMAInit.’ • The Ping-Pong transfer can be setup next using the peripheral driver API ‘DMASetupTransfer’. The code below code shows how this API could be used: DMASetupTransfer(UDMA_CH22_CAMERA, UDMA_MODE_PINGPONG, >, UDMA_SIZE_32, UDMA_ARB_8, (void *)CAM_BUFFER_ADDR, UDMA_SRC_INC_32, (void *),UDMA_DST_INC_32); +=;/* Setup the buffer for pong */ DMASetupTransfer(UDMA_CH22_CAMERA|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, ,UDMA_SIZE_32, UDMA_ARB_8, (void *)CAM_BUFFER_ADDR, UDMA_SRC_INC_32, (void *),UDMA_DST_INC_32); += ;/* Setup buffer for next ping */ The interrupts must be cleared and unmasked next by setting BIT-8 of ‘DMA_DONE_INT_ACK’ and ‘DMA_DONE_INT_MASK_CLR’ respectively. The image can now be captured using the peripheral driver API ‘CameraCaptureStart.' This function enables the sensor interface of the camera core module. • An interrupt will be continuously generated until the capture is stopped and the interrupt-handler registered above should handler the interrupts appropriately. • Since the DMA is configured for Ping-Pong transfer, the has to be adjusted for the next ping/pong transaction. • Depending on the value set for , a DMA-Done interrupt will be generated every time after elements are copied to memory. Code snippet for handling the camera interrupts: void () { /* Stop capture on receiving a frame-end */ if(CameraIntStatus(CAMERA_BASE) &CAM_INT_FE) { CameraIntClear(CAMERA_BASE, CAM_INT_FE); CameraCaptureStop(CAMERA_BASE, true); } /* Check if ‘CAM_THRESHHOLD_DMA_DONE’ is active */ if((DMA_DONE_INT_STS_RAW) & (1<<8)) { /* Clear the interrupt */ (DMA_DONE_INT_ACK) |= 1 << 8; += * <32- bits>; /* For every iteration, set either the ping or pong transactions */ if() { DMASetupTransfer(UDMA_CH22_CAMERA, UDMA_MODE_PINGPONG,, UDMA_SIZE_32, UDMA_ARB_8, (void *)CAM_BUFFER_ADDR, UDMA_SRC_INC_32, (void *), UDMA_DST_INC_32); } else() { DMASetupTransfer(UDMA_CH22_CAMERA|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, , UDMA_SIZE_32, UDMA_ARB_8, (void *)CAM_BUFFER_ADDR, UDMA_SRC_INC_32, (void *), UDMA_DST_INC_32); } SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 401 Developer’s Guide www.ti.com /* Setup the buffer for the next ping/pong */ += ; if () { /* Disable DMA and mask ‘CAM_THRESHHOLD_DMA_DONE’ */ UDMAStopTransfer(UDMA_CH22_CAMERA);(0x44026090) |= 1 << 8; } } The capture can be stopped using the peripheral driver API ‘CameraCaptureStop.' This function disables the sensor interface of the camera core module. The sensor interface can be disabled immediately or at the end of current frame. For stopping the image capture after a frame, disable the sensor interface immediately after the ‘CAM_INT_FE’ interrupt. 14.7.2 Using Peripheral Driver APIs for Communicating with Image Sensors Most image sensors provide a two-wire serial interface for external-MCUs to control them. This section shows how to use CC3200’s I2C interface to communicate with these image-sensors. CC3200 includes one I2C module operating with standard (100 Kbps) or fast (400 Kbps) transmission speeds. First configure and enable the clock for I2C peripheral. Peripherals are clock gated by default and will generate a bus fault if accessed without enabling the clock. The peripheral should be ready to use after the software reset. MAP_PRCMPeripheralClkEnable(PRCM_I2CA0, PRCM_RUN_MODE_CLK); MAP_PRCMPeripheralReset(PRCM_I2CA0); The I2C master block must be configured and enabled next in either standard or fast mode, using peripheral driver API ‘MAP_I2CMasterInitExpClk.' The function internally computes the clock divider to achieve the fastest speed less than or equal to the desired speed. MAP_I2CMasterInitExpClk (I2C_BASE, SYS_CLK, true); /* SYS_CLK is set to 80MHz */ The commands to the image-sensor can then be written and responses be read. Normally a standard communication consists of: • Generating a START condition. • Setting I2C slave address. • Transferring data. • Generating a STOP condition. The master sends the slave address followed by the START condition. A slave with an address that matches this address will respond by returning an acknowledgment bit. Once the slave addressing is achieved, data transfer can proceed byte-by-byte. Peripheral driver APIs for writing and reading to and from an I2C slave: I2CMasterSlaveAddrSet • Description: Sets the address that the I2C Master places on the bus. • Parameters: – ui32Base is the base address of the I2C Master module. – ui8SlaveAddr is an 7-bit slave address. – bReceive is the flag indicating the type of communication with the slave. I2CMasterDataPut • Description: Transmits a byte from the I2C Master. • Parameters: – ui32Base is the base address of the I2C Master module. – ui8Data is data to be transmitted from the I2C Master. I2CMasterDataGet • Description: Receives a byte that has been sent to the I2C Master. 402 Parallel Camera Interface Module SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Developer’s Guide • Parameters: – ui32Base is the base address of the I2C Master module I2CMasterIntClearEx • Description: Clears I2C Master interrupt sources. • Parameters: – ui32Base is the base address of the I2C Master module. – ui32IntFlags is a bit mask of the interrupt sources to be cleared. I2CMasterTimeoutSet • Description: Sets the Master clock timeout value. • Parameters: – ui32Base is the base address of the I2C Master module. – ui32Value is the number of I2C clocks before the timeout is asserted. I2CMasterControl • Description: Controls the state of the I2C Master module. • Parameters: – ui32Base is the base address of the I2C Master module. – ui32Cmd is the command to be issued to the I2C Master module. I2CMasterIntStatusEx • Description: Gets the current I2C Master interrupt status. • Parameters: – ui32Base is the base address of the I2C Master module. – bMasked is false if the raw interrupt status is requested andtrue if the masked interrupt status is requested. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Parallel Camera Interface Module 403 Chapter 15 SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management Topic ........................................................................................................................... Page 15.1 Overview ......................................................................................................... 405 15.2 Power Management Control Architecture ............................................................ 409 15.3 PRCM APIs ...................................................................................................... 412 15.4 Peripheral Macros............................................................................................. 418 15.5 Power Management Framework ......................................................................... 419 15.6 PRCM Registers ............................................................................................... 420 404 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 15.1 Overview The CC3200 SoC incorporates a highly optimized on-chip power management unit that is capable of operating directly from battery without any external regulator. The on-chip PMU includes a set of high-efficiency fast transient response DC-DC converters, LDOs and reference voltage generators. The on-chip PMU is connected to the input supply directly and generates the internal voltages required by the different sections of the chip across power modes. The PMU is tightly synchronized with WLAN radio and avoids interference during radio receive and transmit operations. The chip supports two supply configurations, which provide flexibility to system designers. In one configuration the input supply voltage at chip pin supports a range of 2.1V to 3.6V for active operation. In the other configuration, the chip can be supplied a pre-regulated 1.85V that meets the ripple, loadtransient and peak current requirements. Refer to the CC3200 Datasheet for electrical details. 15.1.1 VBAT Wide-Voltage Connection In the wide-voltage battery connection, the device is powered directly by the battery or pre-regulated 3.3-V supply. All other voltages required to operate the device are generated internally by the DC-DC converters. This is the most common usage for the device, as it supports wide-voltage operation from 2.1 to 3.6 V. 15.1.2 Pre-regulated 1.85 V The pre-regulated 1.85-V mode of operation applies an external regulated 1.85 V directly to the pins 10, 25, 33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. The ANA1 DC-DC and PA DC-DC converters are bypassed. This mode provides the lowest BOM count version. Note: The chip auto-detects which of the two configurations is being used, based on the state of the DCDC pins. The chip will then enable the DCDCs accordingly. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 405 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Overview www.ti.com Figure 15-1. Power Management Unit Supports Two Supply Configurations The PMU includes the following key modules: • Dig-DCDC: Generates 0.9V to 1.2V regulated output for digital core logic. • ANA1-DCDC: Generates 1.8V – 1.9V regulated output for analog and RF. • PA-DCDC: Generates 1.8V – 1.9V regulated output for WLAN transmit power-amplifier. • Precision Voltage Reference • Supply brown-out monitor: – Brownout level for Wide-Voltage mode: 2.1V. – Brownout level for Pre-regulated 1.85V mode: 1.74V. • 32.768KHz crystal oscillator: – Generates precision 32.768KHz for RTC and WLAN power-save protocol timing. – Supports feeding an external square wave 32.768KHz clock in lieu of XTAL . • 32KHz RC oscillator for chip startup: The 32.768KHz XTAL oscillator requires 1.1 sec to become stable after first time power-up or chip reset (ie. nRESET). Until the slow xtal clock is stable, the alternate RC slow-clock is used by the system. • Hibernate Controller: Implements the lowest current sleep mode of the chip called Hibernate mode, and consists of the following functions: – Chip wakeup controller. – RTC counter and RTC based wakeup. 406 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com – GPIO monitor and GPIO based wakeup. – 2x 32bit general purpose direct-battery powered retention register. – Accessible from application processor via SoC level interconnect. – Manages the PMU and IOs when core digital is powered off. • PMU Controller: – Controls all the low-level real-time sequencing of the DCDCs, LDOs and references. – Implements the low-level sequences associated with sleep mode transitions. – Not directly accessible from application processor. – PMU state transitions are initiated by control signals from PRCM. Refer to the CC3200 Datasheet for the chip wakeup sequence and timing parameters. Overview 15.1.3 Supply Brownout and Blackout BROWNOUT: BROWNOUT is the state where the supply voltage falls below the chip brownout threshold. For Wide Voltage mode, Vbrownout=2.1V. For Pre-regulated 1.85V mode, Vbrownout=1.74V. All DCDCs are disabled and all digital logic is power gated, as long as the chip is in BROWNOUT state. The Hibernate controller, 2x32 bit general purpose retention register inside the hibernate controller, and the 32.768KHz XOSC and the RTC counter are not impacted by BROWNOUT and continue to function. Once the supply voltage rises again above Vbrownout, the chip reboots. BLACKOUT: The CC3x PMU incorporates a continuous time coarse analog supply voltage monitor that forces the PMU, including the hibernate controller into a reset state where Vsupply < Vblackout. This condition is referred to as BLACKOUT. Vblackout is typically 1.4V and varies with temperature. The main purpose of BLACKOUT is to ensure that there is a deterministic reset of the control registers and flags inside the hibernate module just before the supply falls, to ensure that the system operations are terminated reliably. In this way, when proper supply level is restored, the PMU starts from a clean reset state without any corrupt control bits carried over from last session. The Hibernate controller, 2x32 bit general purpose retention register inside the hibernate controller, the 32.768KHz XOSC and the RTC counter are all reset during BLACKOUT. For a functional perspective, the effect of BLACKOUT is similar to that of pulling down the chip reset pin (nRESET). 15.1.4 Application Processor Power Modes From the application processor (Cortex M4 and its peripherals) standpoint, the following power modes are supported: • ACTIVE Mode – The processor is clocked at 80MHz. – The required set of peripherals are running at configured clock rates. • SLEEP Mode – The processor is clock gated until an interrupt event. – Reduces consumption by 3mA with respect to ACTIVE. – Immediate wakeup. – The required set of peripherals is running at pre-configured clock rates. – By default the sleep clock to the peripherals is disabled. If the application chooses to enter sleep anytime and requires certain peripherals to be active, the sleep clock to the peripheral has to be enabled in advance (see ARCM register mapping as well as the PRCM APIs). • DEEPSLEEP Mode – The processor is clock gated and PLL is disabled until an interrupt event. – Reduces consumption by 5mA with respect to ACTIVE. – Using peripherals in conjunction with DEEPSLEEP is not recommended in CC3200. • Low Power Deep Sleep Mode (LPDS) – Up to 256Kbyte of SRAM retention. No logic retention. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 407 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Overview www.ti.com • TI SW API and framework provided for transparent save and restore of processor context, peripheral and pin configurations. – Total system current (incl WiFi and network periodic wake-up) as low as 700uA. – When networking and WiFi subsystems are disabled, chip draws around 120uA. • 40MHz XTAL and PLL are turned off. 32.768 KHz XTAL is kept alive. • Most of digital logic is turned off. Digital supply voltage is reduced to 0.9V. • SRAM can be retained in multiples of 64KB. – Processor and peripheral registers are not retained. Global always ON configurations at SoC level are retained. – Configurable wake-on-pad (one out of six pads). – Less that 5mS wakeup latency. – Recommended for ultra-low power always connected cloud/WiFi applications. • Hibernate Mode (HIB) – 32.768KHz XTAL is kept alive . – Wake on RTC (for example, the 32KHz Slow Clock Counter) or selected GPIO. – No SRAM or logic retention. – 2 x 32bit general purpose retention register. • These registers are powered by the input supply directly and retain their content as long as the chip is not reset (nRESET=1) and the supply stays above the Blackout level (1.4V). – Ultra low current of 4uA including RTC. – Less that 10mS wakeup latency. – Recommended for ultra-low power infrequently connected cloud/WiFi applications. – A brief hibernation may also be used by software to implement a full system reboot as part of an Over the Air software upgrade (OTA) or to restore the system to a guaranteed clean state following a watchdog reset. – Once a brownout condition is detected, the application software may choose to enter Hibernate mode to prevent further oscillatory brownouts that may otherwise cause unpredictable system behavior and possible damage to the end equipment. The system can subsequently be made to restart on a RTC timer, on a chip reset, or on plugging of new batteries. For CC3200 applications where battery life is critical, maximize the fraction of time spent in LPDS or Hibernate modes compared to Active and other sleep modes (SLEEP, DEEPSLEEP). 408 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Power Management Control Architecture Figure 15-2. Sleep Modes 15.2 Power Management Control Architecture The CC3200 WiFi-Microcontroller is a multi-processor system-on-chip with several subsystems independently cycling between active and sleep states (Application processor, Network processor, WLANMAC and WLAN-PHY) for optimal energy usage. The activities of various subsystems are tied to the data and management traffic. In absence of events and traffic, all the systems are typically in sleep state (LPDS). The timing of sleep and wakeup do not need to be synchronized across subsystems. For example, in Idle connected case, when the association to the AP is maintained most of the time, the WLAN subsystem is in LPDS and wakes up periodically for short intervals, only to listen for any incoming beacon packets and delivery pending messages from the AP (apart from occasional keep alive packet transmissions). While this repeats in multiples of the beacon period (104mS), the application processor may implement its own sleep strategy with a different periodicity. An advanced power management scheme has been implemented at the CC3200 chip level. This scheme handles the asynchronous sleep-wake requirements of multiple processors and Wi-Fi radio subsystems in a way that is transparent to the software and yet energy efficient. The chip level power management scheme is such that the application program is unaware of the power state transitions of the other subsystems. This approach insulates the user from the real-time complexities of a multi-processor system; it improves robustness by eliminating race conditions and simplifies the application development process. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 409 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Power Management Control Architecture www.ti.com As a result, the power-mode of the chip can be different from the sleep state of the application software code. For example, when the application code requests for LPDS mode it is granted immediately; however, if the Network processor or WLAN is active at that time then the chip does not enter LPDS until they are done. In that case, the application processor is held under reset, which produces a safe result for the software, regardless of when the digital logic gets power gated and when exactly voltage drops to 0.9V. Similarly, on wake-event for a particular subsystem, the chip as a whole transitions into active state (VDD_DIG=1.2V, 40MHz XOSC and PLL enabled) and then only that subsystem is awakened from LPDS. The other subsystems are held in reset until their respective wake-events. Table 15-1 shows the feasible combinations of power states between Application processor and the network (including WLAN) subsystems. Refer to the CC3200 Datasheet for details of current consumption for these combinations. Table 15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN) Application Processor (MCU) Software State ACTIVE ACTIVE ACTIVE SLEEP SLEEP SLEEP LPDS (Fake-LPDS) LPDS (Fake-LPDS) LPDS (Fake-LPDS) Request For HIBERNATE Network Processor & WLAN Software State ACTIVE SLEEP LPDS (Fake-LPDS) ACTIVE SLEEP LPDS (Fake-LPDS) ACTIVE SLEEP LPDS (Fake-LPDS) Don't Care Resulting Power State of Chip, Core Logic Voltage and Clock ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) ACTIVE (1.2V, 80MHz, 32KHz) LPDS (True-LPDS) (0.9V, 32KHz) HIBERNATE (0V, 32KHz) 410 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Power Management Control Architecture Figure 15-3 shows the high-level architecture of the CC3200 SoC level power management. Figure 15-3. Power Management Control Architecture in CC3200 15.2.1 Global Power-Reset-Clock Manager (GPRCM) The Global Power-Reset-Clock Manager module (GPRCM) receives the sleep requests from the subsystems and the wake events from associated sources. Based on sleep requests and wake events, GPRCM controls the clock sources, PLL, power switches and the PMU to change or gate/un-gate the supply, clocks and resets to the following subsystems: • Application Processor (APPS) • Networking Processor (NWP) SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 411 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Power Management Control Architecture www.ti.com • WLAN MAC and PHY Processors (WLAN) Programmable system clock frequency (via PLL) is not supported in CC3200 due to co-existence reasons. For ease of programming and system robustness, application code has limited access to the chip power and clock management infrastructure in CC3200. The software interface to power management is limited to a subset of GPRCM registers, which are accessed via a set of easy-to-use API functions described in Section 15.3. 15.2.2 Application Reset-Clock Manager (ARCM) The application processor subsystem uses a local reset and clock control module called ARCM. The ARCM controls the reset, clock muxing and clock gating to the application specific peripheral modules. ARCM has no power control functionality. The application processor subsystem is a single power domain managed by GPRCM at SoC level. Power gating at individual peripheral level does not lead to significant savings in a high performance multi-processor system and is not supported in CC3200. The ARCM registers can be accessed either directly or via a set of easy-to-use API functions described in Section 15.3. The ARCM register map is described in Section 15.6. 15.3 PRCM APIs This section gives an overview of the PRCM APIs provided in the CC3200 Software Development Kit Peripheral Library. For more details refer to the SDK Documentation. 15.3.1 MCU Initialization Booting from Power-Off or exiting Hibernate Low Power Mode, the user application is expected to configure mandatory MCU parameters by calling void PRCMCC3200MCUInit() API. void PRCMCC3200MCUInit(void) Description: This function sets mandatory configuration for MCU. Parameter: None Return: None 15.3.2 Reset Control MCU Reset (Software Reset) MCU subsystem can be reset to its default state using the following API function call. void PRCMMCUReset(tBoolean bIncludeSubsystem) Description: This function performs a software reset of a MCU and associated peripherals. The core resumes execution in the ROM boot loader which will re-load the user application from sFlash. Parameter: bIncludeSubsystem – If true, MCU along its associated peripherals are reset, MCU only otherwise. Return: None 15.3.3 Peripheral Reset Individual peripherals can be reset to their default register state using the following API call. void PRCMPeripheralReset(unsigned long ulPeripheral) Description: This function performs a software reset of the specified peripheral. Parameter: ulPeripheral – A valid peripheral macro (see Peripheral Macro section) Return: None 412 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PRCM APIs 15.3.4 Reset Cause The application's processor restarts its execution from reset vector after a reset. User application can determine the cause of reset using the following API. unsigned long PRCMSysResetCauseGet(void) Description: This function acquires the reason for an MCU reset. This is a sticky status. Parameter: None Return: Returns MCU reset cause as one of the following: • PRCM_POWER_ON: Power On Reset • PRCM_LPDS_EXIT: Exiting from LPDS • PRCM_CORE_RESET: Software reset (core only) • PRCM_MCU_RESET: Software reset (core and associated peripherals) • PRCM_WDT_RESET: Watchdog Reset • PRCM_SOC_RESET: Software SOC reset • PRCM_HIB_EXIT: Exiting from Hibernate 15.3.5 Clock Control Individual peripherals can be kept clock gated or un-gated across different power modes. Any access to a peripheral with clock gated will result in a bus fault. The following APIs can be used to control the peripheral clock gating. void PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags) Description: This function un-gates the specified peripheral clock and makes the peripheral accessible. Parameters: • ulPeripheral: One of the valid peripheral macro (see Peripheral Macro section) • ulClkFlag: Power mode during which the clock will be kept enabled and is bitwise or one or more of the following: – PRCM_RUN_MODE_CLK: Un-gates clock to the peripheral during run mode. – PRCM_SLP_MODE_CLK: Keeps the clock un-gated during Sleep. – PRCM_DSLP_MODE_CLK: Keeps the clock un-gated during deep sleep . Return: None void PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags) Description: This function gates a specified peripheral clock. Parameter: • ulPeripheral: One of the valid peripheral macros (see Peripheral Macro section). • ulClkFlag: Power mode during which the clock will be kept disabled and is bitwise or one or more of the following: – PRCM_RUN_MODE_CLK: Gates clock to the peripheral during run mode. – PRCM_SLP_MODE_CLK: Keeps the clock gated during Sleep. – PRCM_DSLP_MODE_CLK: Keeps the clock gated during deep sleep . Return: None 15.3.6 Low Power Modes SRAM Retention – CC3200 SRAM is organized in 4 x 64 KB columns. By default all SRAM columns are configured to be retained across LPDS and Deep Sleep power modes. The user's application can enable or disable retention per column by calling the following API with appropriate parameters: void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulFlags) SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 413 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM APIs www.ti.com Description: This function reads from a specified OCR register. Parameter: • ulSramColSel: Bit-packed representation of SRAM columns. ulSramColSel is logical or one or more of the following: – PRCM_SRAM_COL_1: SRAM column 1 – PRCM_SRAM_COL_2: SRAM column 2 – PRCM_SRAM_COL_3: SRAM column 3 – PRCM_SRAM_COL_4: SRAM column 4 • ulFlags: Bit-packed representation of power modes. ulFlags is logical or one or more of the following: – PRCM_SRAM_DSLP_RET: Configuration for DSLP – PRCM_SRAM_LPDS_RET: Configuration for LPDS Return: None void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags) Description: This function reads from a specified OCR register. Parameter: • ulSramColSel: Bit-packed representation of SRAM columns. ulSramColSel is logical or one or more of the following: – PRCM_SRAM_COL_1: SRAM column 1 – PRCM_SRAM_COL_2: SRAM column 2 – PRCM_SRAM_COL_3: SRAM column 3 – PRCM_SRAM_COL_4: SRAM column 4 • ulFlags: Bit-packed representation of power modes. ulFlags is logical or one or more of the following: – PRCM_SRAM_DSLP_RET: Configuration for DSLP – PRCM_SRAM_LPDS_RET: Configuration for LPDS Return: None 15.3.7 Sleep (SLEEP) This mode can be entered by calling following API. During this mode the core is halted at the point of invocation on this API with selective peripheral clock gating. Core resumes execution from the same location when it receives an interrupt. void PRCMSleepEnter() Description: Enter Sleep power mode by invoking “WFI” instruction. Parameter: None Return: None 15.3.8 Deep Sleep (DEEPSLEEP) During this mode the core is halted at the point of invocation on this API, with selective peripheral clock gating and SRAM retention. Core resumes execution from the same location when it receives an interrupt. This mode can be entered by calling following API. void PRCMDeepSleepEnter () Description: Enter Deep Sleep power mode by executing “WFI” instruction. Parameter: None Return: None 414 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PRCM APIs By default, entire application SRAM is retained during DSLP. User can enable/disable SRAM retention using the APIs PRCMSRAMRetentionEnable() and PRCMSRAMRetentionDisable(). See Section 15.3.6 for more details. 15.3.9 Low Power Deep Sleep (LPDS) During this mode the MCU core and its associated peripheral are reset with selective SRAM column retention. By default, the entire application's SRAM is retained during DSLP. The user can enable or disable SRAM retention using the APIs PRCMSRAMRetentionEnable() and PRCMSRAMRetentionDisable(). See “Section 15.3.6 for more details. Core resumes its execution either in ROM boot loader or pre-configured location in SRAM (in case user sets restore info before entering LPDS) upon wakeup due to configured wake sources which includes the following: • Host IRQ – An Interrupt from NWP • LPDS Timer – Dedicated LPDS Timer • LPDS wakeup GPIOs – Six selected GPIOs LPDS restore info can be set using the following API: void PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr) Description: This function sets the PC and Stack pointer info that will be restored by the bootloader on exit from LPDS. Parameter: • ulStackPtr: Stack Pointer restored on exit from LPDS. • ulProgCntr: Program counter restored on exit from LPDS. Return: None LPDS wakeup sources can be configured using following APIs: ● void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc) Description: This function enables the specified LPDS wakeup sources. Parameter: ulLpdsWakeupSrc: Bit-packed representation of valid wakeup sources. ulLpdsWakeupSrc is bitwise or one or more of the following: • PRCM_LPDS_HOST_IRQ: Interrupt from NWP • PRCM_LPDS_GPIO: LPDS wakeup GPIOs • PRCM_LPDS_TIMER: Dedicated LPDS timer Return: None ● void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc) Description: This function disables the specified LPDS wakeup sources. Parameter: ulLpdsWakeupSrc: Bit-packed representation of valid wakeup sources. ulLpdsWakeupSrc is bitwise or one or more of the following: • PRCM_LPDS_HOST_IRQ: Interrupt from NWP • PRCM_LPDS_GPIO: LPDS wakeup GPIOs • PRCM_LPDS_TIMER: Dedicated LPDS timer Return: None ● void PRCMLPDSIntervalSet(unsigned long ulTicks) Description: This function sets the LPDS wakeup timer interval. The 32-bit timer is clocked at 32.768 KHz and triggers a wakeup on expiry. The timer is started only when system enters LPDS Parameter: ulTicks: Wakeup interval in 32.768 KHz ticks. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 415 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM APIs www.ti.com Return: None ● unsigned long PRCMLPDSWakeupCauseGet(void) Description: This function gets the LPDS wakeup cause. Parameter: None Return: Returns the LPDS wakeup cause enumerated as one of the following: • PRCM_LPDS_HOST_IRQ: Interrupt from NWP • PRCM_LPDS_GPIO: LPDS wakeup GPIOs • PRCM_LPDS_TIMER: Dedicated LPDS timer ● void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType) Description: Sets the specified GPIO as the wakeup source and configures that GPIO to sense specified. Parameter: • ulGPIOPin: One of the valid LPDS wakeup GPIOs. ulGPIOPin can be one of the following: – PRCM_LPDS_GPIO2: GPIO 2 – PRCM_LPDS_GPIO4: GPIO 4 – PRCM_LPDS_GPIO13: GPIO 13 – PRCM_LPDS_GPIO17: GPIO 17 – PRCM_LPDS_GPIO11: GPIO 11 – PRCM_LPDS_GPIO24: GPIO 24 • ulType: Event Type. ulType can be one of the following: – PRCM_LPDS_LOW_LEVEL: GPIO is held low (0) – PRCM_LPDS_HIGH_LEVEL: GPIO is held high (1) – PRCM_LPDS_FALL_EDGE: GPIO changes from High to Low – PRCM_LPDS_RISE_EDGE: GPIO changes from Low to High Return: None ● The user application can put the system in LPDS by invoking following the API function: void PRCMLPDSEnter(void) Description: This function puts the system into Low Power Deep Sleep (LPDS) power mode, and should be invoked after configuring the wake source, SRAM retention configuration and system restore configuration. Parameter: None Return: None 15.3.10 Hibernate (HIB) During this mode the entire SOC loses its state, including the MCU subsystem, the NWP subsystem and SRAM except 2 x 32 bit OCR registers and the free running slow clock counter. Core resumes its execution in ROM boot loader upon wakeup due to configured wake sources which include the following: • Slow clock Counter – Always on 32.768 KHz Counter • HIB wakeup GPIOs – Six selected GPIOs Hibernate wakeup sources are configured using following APIs: ● void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc) Description: This function enables the specified HIB wakeup sources. Parameter: ulHIBWakupSrc: Bit-packed representation of valid wakeup sources. ulHIBWakupSrc is bitwise or one or more of the following: • PRCM_HIB_SLOW_CLK_CTR: Slow Clock Counter 416 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PRCM APIs • PRCM_HIB_GPIO2: GPIO 2 • PRCM_HIB_GPIO4: GPIO 4 • PRCM_HIB_GPIO13: GPIO 13 • PRCM_HIB_GPIO17: GPIO 17 • PRCM_HIB_GPIO11: GPIO 11 • PRCM_HIB_GPIO24: GPIO 24 Return: None ● void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc) Description: This function disables the specified HIB wakeup sources. Parameter: ulHIBWakupSrc: Bit-packed representation of valid wakeup sources. ulHIBWakupSrc is bitwise or one or more of the following: • PRCM_HIB_SLOW_CLK_CTR: Slow Clock Counter • PRCM_HIB_GPIO2: GPIO 2 • PRCM_HIB_GPIO4: GPIO 4 • PRCM_HIB_GPIO13: GPIO 13 • PRCM_HIB_GPIO17: GPIO 17 • PRCM_HIB_GPIO11: GPIO 11 • PRCM_HIB_GPIO24: GPIO 24 Return: None ● unsigned long PRCMHibernateWakeupCauseGet(void) Description: This function gets the HIB wakeup cause. Parameter: None Return: Returns the HIB wakeup cause enumerated as one of the following: • PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK: Slow Clock Counter • PRCM_HIB_WAKEUP_CAUSE_GPIO: HIB wakeup GPIOs ● void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap, unsigned long ulType) Description: Sets the specified GPIOs as wakeup source and configures them to sense the specified event. Parameter: • ulMultiGPIOBitMap: One of the valid HIB wakeup GPIOs. ulMultiGPIOBitMap is logical OR of one or more of the following: – PRCM_LPDS_GPIO2: GPIO 2 – PRCM_LPDS_GPIO4: GPIO 4 – PRCM_LPDS_GPIO13: GPIO 13 – PRCM_LPDS_GPIO17: GPIO 17 – PRCM_LPDS_GPIO11: GPIO 11 – PRCM_LPDS_GPIO24: GPIO 24 • ulType: Event Type. ulType can be one of the following: – PRCM_HIB_LOW_LEVEL: GPIO is held low (0) – PRCM_HIB_HIGH_LEVEL: GPIO is held high (1) – PRCM_HIB_FALL_EDGE: GPIO changes from High to Low – PRCM_HIB_RISE_EDGE: GPIO changes from Low to High Return: None ● void PRCMHibernateIntervalSet(unsigned long long ullTicks) SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 417 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM APIs www.ti.com Description: This function sets the HIB wakeup interval based on the current slow clock count. The 48-bit timer is clocked at 32.768 KHz and triggers a wakeup when the counter reaches a particular value. The function computes the wakeup count value by adding a specified interval to the current value of the slow clock counter. Parameter: ullTicks: Wakeup interval in 32.768 KHz ticks Return: None ● User application can put the system in HIB by invoking following API: void PRCMHibernateEnter (void) Description: This function puts the system into Hibernate power mode. Parameter: None Return: None Two 32-bit On-Chip Retention registers (OCR) retained during the Hibernate power mode can be accessed using the following APIs: ● void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue) Description: This function writes into a specified OCR register. Parameter: • ucIndex: Selects one out of two available registers, 0 or 1 • ulRegValue: 32-bit value Return: None ● unsigned long PRCMOCRRegisterRead(unsigned char ucIndex) Description: This function reads from a specified OCR register. Parameter: ucIndex: Selects one out of two available registers, 0 or 1 Return: Returns a 32-bit value read from a specified OCR register. 15.3.11 Slow Clock Counter The CC3200 has a 48-bit on chip always on slow counter running at 32.768 KHz, which can wake up the device from Hibernate low power mode, or generate an interrupt to the core on counting a particular match value. The following API returns the current value of the counter: unsigned long PRCMSlowClkCtrGet(void) Description: This function reads from specified OCR register. Parameter: None Return: None To set the match value to receive an interrupt call use following API with the appropriate value: void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks) Description: This function sets the match value of the slow clock triggered interrupt. Parameter: ullTicks 48-bit match value Return: None 15.4 Peripheral Macros 418 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Table 15-2. Peripheral Macro Table Power Management Framework Macro PRCM_CAMERA PRCM_I2S PRCM_SDHOST PRCM_GSPI PRCM_UDMA PRCM_GPIOA0 PRCM_GPIOA1 PRCM_GPIOA2 PRCM_GPIOA3 PRCM_WDT PRCM_UARTA0 PRCM_UARTA1 PRCM_TIMERA0 PRCM_TIMERA1 PRCM_TIMERA2 PRCM_TIMERA3 PRCM_I2CA0 Description Camera interface I2S interface SDHost interface General purpose SPI interface uDMA module General Purpose IO port A0 General Purpose IO port A1 General Purpose IO port A2 General Purpose IO port A3 Watchdog module UART interface A0 UART interface A1 PRCM_TIMERA0 General purpose Timer A0 PRCM_TIMERA0 General purpose Timer A1 PRCM_TIMERA0 General purpose Timer A2 PRCM_TIMERA0 General purpose Timer A3 I2C interface 15.5 Power Management Framework The CC3200 SDK comes with a power management software framework. This framework provides simple services that can be invoked by the application, and callback functions that can be overridden by the application code. For details refer to the Power Management framework software documentation. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 419 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers www.ti.com 15.6 PRCM Registers Table 15-3 lists the memory-mapped registers for the ARCM. All register offset addresses not listed in Table 15-3 should be considered as reserved locations and the register contents should not be modified. Offset 0h 4h 8h 14h 18h 20h 24h 28h 2Ch 30h 34h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h D8h DCh E4h ECh 108h Acronym CAMCLKCFG CAMCLKEN CAMSWRST MCASPCLKEN MCASPSWRST SDIOMCLKCFG SDIOMCLKEN SDIOMSWRST APSPICLKCFG APSPICLKEN APSPISWRST DMACLKEN DMASWRST GPIO0CLKEN GPIO0SWRST GPIO1CLKEN GPIO1SWRST GPIO2CLKEN GPIO2SWRST GPIO3CLKEN GPIO3SWRST GPIO4CLKEN GPIO4SWRST WDTCLKEN WDTSWRST UART0CLKEN UART0SWRST UART1CLKEN UART1SWRST GPT0CLKCFG GPT0SWRST GPT1CLKEN GPT1SWRST GPT2CLKEN GPT2SWRST GPT3CLKEN GPT3SWRST MCASPCLKCFG0 MCASPCLKCFG1 I2CLCKEN I2CSWRST LPDSREQ TURBOREQ DSLPWAKECFG Table 15-3. PRCM Registers Register Name Section Section 15.6.1.1 Section 15.6.1.2 Section 15.6.1.3 Section 15.6.1.4 Section 15.6.1.5 Section 15.6.1.6 Section 15.6.1.7 Section 15.6.1.8 Section 15.6.1.9 Section 15.6.1.10 Section 15.6.1.11 Section 15.6.1.12 Section 15.6.1.13 Section 15.6.1.14 Section 15.6.1.15 Section 15.6.1.16 Section 15.6.1.17 Section 15.6.1.18 Section 15.6.1.19 Section 15.6.1.20 Section 15.6.1.21 Section 15.6.1.22 Section 15.6.1.23 Section 15.6.1.24 Section 15.6.1.25 Section 15.6.1.26 Section 15.6.1.27 Section 15.6.1.28 Section 15.6.1.29 Section 15.6.1.30 Section 15.6.1.31 Section 15.6.1.32 Section 15.6.1.33 Section 15.6.1.34 Section 15.6.1.35 Section 15.6.1.36 Section 15.6.1.37 Section 15.6.1.38 Section 15.6.1.39 Section 15.6.1.40 Section 15.6.1.41 Section 15.6.1.42 Section 15.6.1.43 Section 15.6.1.44 420 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Offset 10Ch 110h 114h 118h 120h 124h Acronym DSLPTIMRCFG SLPWAKEEN SLPTMRCFG WAKENWP RCM_IS RCM_IEN Table 15-3. PRCM Registers (continued) Register Name PRCM Registers Section Section 15.6.1.45 Section 15.6.1.46 Section 15.6.1.47 Section 15.6.1.48 Section 15.6.1.49 Section 15.6.1.50 15.6.1 PRCM Register Description The remainder of this section lists and describes the PRCM registers, in numerical order by address offset. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 421 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.1 CAMCLKCFG Register (offset = 0h) [reset = 0h] CAMCLKCFG is shown in Figure 15-4 and described in Table 15-4. www.ti.com Figure 15-4. CAMCLKCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DIVOFFTIM NU1 DIVONTIM R-0h R/W-0h R-0h R/W-0h Bit 31-11 10-8 Field RESERVED DIVOFFTIM 7-3 NU1 2-0 DIVONTIM Table 15-4. CAMCLKCFG Register Field Descriptions Type R R/W R R/W Reset 0h 0h 0h 0h Description CAMERA_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clk (240 MHz) in generation of Camera func-clk: "000" 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 CAMERA_PLLCKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clk (240 MHz) in generation of Camera func-clk: "000" 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 422 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.2 CAMCLKEN Register (offset = 4h) [reset = 0h] CAMCLKEN is shown in Figure 15-5 and described in Table 15-5. Figure 15-5. CAMCLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 NU1 R-0h 15 14 13 12 11 10 NU2 R-0h 7 6 5 4 3 2 NU3 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-24 23-17 16 Field RESERVED NU1 DSLPCLKEN 15-9 8 NU2 SLPCLKEN 7-1 NU3 0 RUNCLKEN Table 15-5. CAMCLKEN Register Field Descriptions Type R R R R R/W R R/W Reset 0h 0h 0h 0h 0h 0h 0h Description CAMERA_DSLP_CLK_ENABLE 0h = Disable camera clk during deep-sleep mode CAMERA_SLP_CLK_ENABLE 0h = Disable camera clk during sleep mode 1h = Enable camera clk during sleep mode CAMERA_RUN_CLK_ENABLE 0h = Disable camera clk during run mode 1h = Enable camera clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 423 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.3 CAMSWRST Register (offset = 8h) [reset = 0h] CAMSWRST is shown in Figure 15-6 and described in Table 15-6. Figure 15-6. CAMSWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-6. CAMSWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description CAMERA_ENABLED_STATUS 0h = Camera clocks/resets are disabled 1h = Camera clocks/resets are enabled CAMERA_SOFT_RESET 0h = De-assert reset for Camera-core 1h = Assert reset for Camera-core www.ti.com 24 16 8 0 SWRST R/W-0h 424 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.4 MCASPCLKEN Register (offset = 14h) [reset = 0h] MCASPCLKEN is shown in Figure 15-7 and described in Table 15-7. Figure 15-7. MCASPCLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 NU1 R-0h 15 14 13 12 11 10 NU2 R-0h 7 6 5 4 3 2 NU3 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-24 23-17 16 Field RESERVED NU1 DSLPCLKEN 15-9 8 NU2 SLPCLKEN 7-1 NU3 0 RUNCLKEN Table 15-7. MCASPCLKEN Register Field Descriptions Type R R R R R/W R R/W Reset 0h 0h 0h 0h 0h 0h 0h Description MCASP_DSLP_CLK_ENABLE 0h = Disable MCASP clk during deep-sleep mode MCASP_SLP_CLK_ENABLE 0h = Disable MCASP clk during sleep mode 1h = Enable MCASP clk during sleep mode MCASP_RUN_CLK_ENABLE 0h = Disable MCASP clk during run mode 1h = Enable MCASP clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 425 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.5 MCASPSWRST Register (offset = 18h) [reset = 0h] MCASPSWRST is shown in Figure 15-8 and described in Table 15-8. Figure 15-8. MCASPSWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-8. MCASPSWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description MCASP_ENABLED_STATUS 0h = MCASP Clocks/resets are disabled 1h = MCASP Clocks/resets are enabled MCASP_SOFT_RESET 0h = De-assert reset for MCASP-core 1h = Assert reset for MCASP-core www.ti.com 24 16 8 0 SWRST R/W-0h 426 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.6 SDIOMCLKCFG Register (offset = 20h) [reset = 0h] SDIOMCLKCFG is shown in Figure 15-9 and described in Table 15-9. PRCM Registers Figure 15-9. SDIOMCLKCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DIVOFFTIM NU1 DIVONTIM R-0h R/W-0h R-0h R/W-0h Bit 31-11 10-8 Field RESERVED DIVOFFTIM 7-3 NU1 2-0 DIVONTIM Table 15-9. SDIOMCLKCFG Register Field Descriptions Type R R/W R R/W Reset 0h 0h 0h 0h Description MMCHS_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clk (240 MHz) in generation of MMCHS func-clk: "000" 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 MMCHS_PLLCKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clk (240 MHz) in generation of MMCHS func-clk "000" 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 427 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.7 SDIOMCLKEN Register (offset = 24h) [reset = 0h] SDIOMCLKEN is shown in Figure 15-10 and described in Table 15-10. Figure 15-10. SDIOMCLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 NU1 R-0h 15 14 13 12 11 10 NU2 R-0h 7 6 5 4 3 2 NU3 R-0h www.ti.com 25 24 17 16 DSLPCLKEN R-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-24 23-17 16 Field RESERVED NU1 DSLPCLKEN 15-9 8 NU2 SLPCLKEN 7-1 NU3 0 RUNCLKEN Table 15-10. SDIOMCLKEN Register Field Descriptions Type R R R R R/W R R/W Reset 0h 0h 0h 0h 0h 0h 0h Description MMCHS_DSLP_CLK_ENABLE 0h = Disable MMCHS clk during deep-sleep mode MMCHS_SLP_CLK_ENABLE 0h = Disable MMCHS clk during sleep mode 1h = Enable MMCHS clk during sleep mode MMCHS_RUN_CLK_ENABLE 0h = Disable MMCHS clk during run mode 1h = Enable MMCHS clk during run mode 428 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.8 SDIOMSWRST Register (offset = 28h) [reset = 0h] SDIOMSWRST is shown in Figure 15-11 and described in Table 15-11. Figure 15-11. SDIOMSWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h PRCM Registers 25 17 9 1 ENSTS R-0h 24 16 8 0 SWRST R/W-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-11. SDIOMSWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description MMCHS_ENABLED_STATUS 0h = MMCHS Clocks/resets are disabled 1h = MMCHS Clocks/resets are enabled MMCHS_SOFT_RESET 0h = De-assert reset for MMCHS-core 1h = Assert reset for MMCHS-core SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 429 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.9 APSPICLKCFG Register (offset = 2Ch) [reset = 0h] APSPICLKCFG is shown in Figure 15-12 and described in Table 15-12. Figure 15-12. APSPICLKCFG Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h www.ti.com 25 24 17 9 DIVOFFTIM R/W-0h 1 DIVONTIM R/W-0h 16 BAUDSEL R/W-0h 8 0 Bit 31-17 16 Field RESERVED BAUDSEL 15-11 10-8 NU1 DIVOFFTIM 7-3 NU2 2-0 DIVONTIM Table 15-12. APSPICLKCFG Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description MCSPI_A1_BAUD_CLK_SEL 0h = XTAL clk is used as baud clk for MCSPI_A1 1h = PLL divclk is used as baud clk for MCSPI_A1. MCSPI_A1_PLLCLKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clk (240 MHz) in generation of MCSPI_A1 func-clk: "000" - 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 MCSPI_A1_PLLCLKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clk (240 MHz) in generation of MCSPI_A1 func-clk: "000" - 1 "001" - 2 "010" - 3 "011" - 4 "100" - 5 "101" - 6 "110" - 7 "111" - 8 430 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.10 APSPICLKEN Register (offset = 30h) [reset = 0h] APSPICLKEN is shown in Figure 15-13 and described in Table 15-13. Figure 15-13. APSPICLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 NU1 R-0h 15 14 13 12 11 10 NU2 R-0h 7 6 5 4 3 2 NU3 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-24 23-17 16 Field RESERVED NU1 DSLPCLKEN 15-9 8 NU2 SLPCLKEN 7-1 NU3 0 RUNCLKEN Table 15-13. APSPICLKEN Register Field Descriptions Type R R R R R/W R R/W Reset 0h 0h 0h 0h 0h 0h 0h Description MCSPI_A1_DSLP_CLK_ENABLE 0h = Disable MCSPI_A1 clk during deep-sleep mode MCSPI_A1_SLP_CLK_ENABLE 0h = Disable MCSPI_A1 clk during sleep mode 1h = Enable MCSPI_A1 clk during sleep mode MCSPI_A1_RUN_CLK_ENABLE 0h = Disable MCSPI_A1 clk during run mode 1h = Enable MCSPI_A1 clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 431 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.11 APSPISWRST Register (offset = 34h) [reset = 0h] APSPISWRST is shown in Figure 15-14 and described in Table 15-14. Figure 15-14. APSPISWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-14. APSPISWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description MCSPI_A1_ENABLED_STATUS 0h = MCSPI_A1 Clocks/Resets are disabled 1h = MCSPI_A1 Clocks/Resets are enabled MCSPI_A1_SOFT_RESET 0h = De-assert reset for MCSPI_A1-core 1h = Assert reset for MCSPI_A1-core www.ti.com 24 16 8 0 SWRST R/W-0h 432 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.12 DMACLKEN Register (offset = 48h) [reset = 0h] DMACLKEN is shown in Figure 15-15 and described in Table 15-15. Figure 15-15. DMACLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-15. DMACLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description UDMA_A_DSLP_CLK_ENABLE 0h = Disable UDMA_A clk during deep-sleep mode 1h = Enable UDMA_A clk during deep-sleep mode UDMA_A_SLP_CLK_ENABLE 0h = Disable UDMA_A clk during sleep mode 1h = Enable UDMA_A clk during sleep mode UDMA_A_RUN_CLK_ENABLE 0h = Disable UDMA_A clk during run mode 1h = Enable UDMA_A clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 433 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.13 DMASWRST Register (offset = 4Ch) [reset = 0h] DMASWRST is shown in Figure 15-16 and described in Table 15-16. Figure 15-16. DMASWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-16. DMASWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description UDMA_A_ENABLED_STATUS 0h = UDMA_A Clocks/Resets are disabled 1h = UDMA_A Clocks/Resets are enabled UDMA_A_SOFT_RESET 0h = De-assert reset for DMA_A 1h = Assert reset for DMA_A www.ti.com 24 16 8 0 SWRST R/W-0h 434 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.14 GPIO0CLKEN Register (offset = 50h) [reset = 0h] GPIO0CLKEN is shown in Figure 15-17 and described in Table 15-17. Figure 15-17. GPIO0CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-17. GPIO0CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPIO_A_DSLP_CLK_ENABLE 0h = Disable GPIO_A clk during deep-sleep mode 1h = Enable GPIO_A clk during deep-sleep mode GPIO_A_SLP_CLK_ENABLE 0h = Disable GPIO_A clk during sleep mode 1h = Enable GPIO_A clk during sleep mode GPIO_A_RUN_CLK_ENABLE 0h = Disable GPIO_A clk during run mode 1h = Enable GPIO_A clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 435 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.15 GPIO0SWRST Register (offset = 54h) [reset = 0h] GPIO0SWRST is shown in Figure 15-18 and described in Table 15-18. Figure 15-18. GPIO0SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-18. GPIO0SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPIO_A_ENABLED_STATUS 0h = GPIO_A Clocks/Resets are disabled 1h = GPIO_A Clocks/Resets are enabled GPIO_A_SOFT_RESET 0h = De-assert reset for GPIO_A 1h = Assert reset for GPIO_A www.ti.com 24 16 8 0 SWRST R/W-0h 436 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.16 GPIO1CLKEN Register (offset = 58h) [reset = 0h] GPIO1CLKEN is shown in Figure 15-19 and described in Table 15-19. Figure 15-19. GPIO1CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-19. GPIO1CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPIO_B_DSLP_CLK_ENABLE 0h = Disable GPIO_B clk during deep-sleep mode 1h = Enable GPIO_B clk during deep-sleep mode GPIO_B_SLP_CLK_ENABLE 0h = Disable GPIO_B clk during sleep mode 1h = Enable GPIO_B clk during sleep mode GPIO_B_RUN_CLK_ENABLE 0h = Disable GPIO_B clk during run mode 1h = Enable GPIO_B clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 437 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.17 GPIO1SWRST Register (offset = 5Ch) [reset = 0h] GPIO1SWRST is shown in Figure 15-20 and described in Table 15-20. Figure 15-20. GPIO1SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-20. GPIO1SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPIO_B_ENABLED_STATUS 0h = GPIO_B Clocks/Resets are disabled 1h = GPIO_B Clocks/Resets are enabled GPIO_B_SOFT_RESET 0h = De-assert reset for GPIO_B 1h = Assert reset for GPIO_B www.ti.com 24 16 8 0 SWRST R/W-0h 438 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.18 GPIO2CLKEN Register (offset = 60h) [reset = 0h] GPIO2CLKEN is shown in Figure 15-21 and described in Table 15-21. Figure 15-21. GPIO2CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-21. GPIO2CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPIO_C_DSLP_CLK_ENABLE 0h = Disable GPIO_C clk during deep-sleep mode 1h = Enable GPIO_C clk during deep-sleep mode GPIO_C_SLP_CLK_ENABLE 0h = Disable GPIO_C clk during sleep mode 1h = Enable GPIO_C clk during sleep mode GPIO_C_RUN_CLK_ENABLE 0h = Disable GPIO_C clk during run mode 1h = Enable GPIO_C clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 439 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.19 GPIO2SWRST Register (offset = 64h) [reset = 0h] GPIO2SWRST is shown in Figure 15-22 and described in Table 15-22. Figure 15-22. GPIO2SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-22. GPIO2SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPIO_C_ENABLED_STATUS 0h = GPIO_C Clocks/Resets are disabled 1h = GPIO_C Clocks/Resets are enabled GPIO_C_SOFT_RESET 0h = De-assert reset for GPIO_C 1h = Assert reset for GPIO_C www.ti.com 24 16 8 0 SWRST R/W-0h 440 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.20 GPIO3CLKEN Register (offset = 68h) [reset = 0h] GPIO3CLKEN is shown in Figure 15-23 and described in Table 15-23. Figure 15-23. GPIO3CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-23. GPIO3CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPIO_D_DSLP_CLK_ENABLE 0h = Disable GPIO_D clk during deep-sleep mode 1h = Enable GPIO_D clk during deep-sleep mode GPIO_D_SLP_CLK_ENABLE 0h = Disable GPIO_D clk during sleep mode 1h = Enable GPIO_D clk during sleep mode GPIO_D_RUN_CLK_ENABLE 0h = Disable GPIO_D clk during run mode 1h = Enable GPIO_D clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 441 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.21 GPIO3SWRST Register (offset = 6Ch) [reset = 0h] GPIO3SWRST is shown in Figure 15-24 and described in Table 15-24. Figure 15-24. GPIO3SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-24. GPIO3SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPIO_D_ENABLED_STATUS 0h = GPIO_D Clocks/Resets are disabled 1h = GPIO_D Clocks/Resets are enabled GPIO_D_SOFT_RESET 0h = De-assert reset for GPIO_D 1h = Assert reset for GPIO_D www.ti.com 24 16 8 0 SWRST R/W-0h 442 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.22 GPIO4CLKEN Register (offset = 70h) [reset = 0h] GPIO4CLKEN is shown in Figure 15-25 and described in Table 15-25. Figure 15-25. GPIO4CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-25. GPIO4CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPIO_E_DSLP_CLK_ENABLE 0h = Disable GPIO_E clk during deep-sleep mode 1h = Enable GPIO_E clk during deep-sleep mode GPIO_E_SLP_CLK_ENABLE 0h = Disable GPIO_E clk during sleep mode 1h = Enable GPIO_E clk during sleep mode GPIO_E_RUN_CLK_ENABLE 0h = Disable GPIO_E clk during run mode 1h = Enable GPIO_E clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 443 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.23 GPIO4SWRST Register (offset = 74h) [reset = 0h] GPIO4SWRST is shown in Figure 15-26 and described in Table 15-26. Figure 15-26. GPIO4SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-26. GPIO4SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPIO_E_ENABLED_STATUS 0h = GPIO_E Clocks/Resets are disabled 1h = GPIO_E Clocks/Resets are enabled GPIO_E_SOFT_RESET 0h = De-assert reset for GPIO_E 1h = Assert reset for GPIO_E www.ti.com 24 16 8 0 SWRST R/W-0h 444 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.24 WDTCLKEN Register (offset = 78h) [reset = 0h] WDTCLKEN is shown in Figure 15-27 and described in Table 15-27. Figure 15-27. WDTCLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 BAUDCLKSEL R/W-0h 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-26 25-24 Field RESERVED BAUDCLKSEL 23-17 16 RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-27. WDTCLKEN Register Field Descriptions Type R R/W R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h 0h 0h Description WDOG_A_BAUD_CLK_SEL "00" - Sysclk "01" - REF_CLK (38.4 MHz) "10/11" - Slow_clk WDOG_A_DSLP_CLK_ENABLE 0h = Disable WDOG_A clk during deep-sleep mode 1h = Enable WDOG_A clk during deep-sleep mode WDOG_A_SLP_CLK_ENABLE 0h = Disable WDOG_A clk during sleep mode 1h = Enable WDOG_A clk during sleep mode WDOG_A_RUN_CLK_ENABLE 0h = Disable WDOG_A clk during run mode 1h = Enable WDOG_A clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 445 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.25 WDTSWRST Register (offset = 7Ch) [reset = 0h] WDTSWRST is shown in Figure 15-28 and described in Table 15-28. Figure 15-28. WDTSWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-28. WDTSWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description WDOG_A_ENABLED_STATUS 0h = WDOG_A Clocks/Resets are disabled 1h = WDOG_A Clocks/Resets are enabled WDOG_A_SOFT_RESET 0h = De-assert reset for WDOG_A 1h = Assert reset for WDOG_A www.ti.com 24 16 8 0 SWRST R/W-0h 446 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.26 UART0CLKEN Register (offset = 80h) [reset = 0h] UART0CLKEN is shown in Figure 15-29 and described in Table 15-29. Figure 15-29. UART0CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 UART0DSLPC LKEN R/W-0h 9 8 UART0SLPCLK EN R/W-0h 1 0 UART0RCLKE N R/W-0h Bit 31-17 16 15-9 8 7-1 0 Table 15-29. UART0CLKEN Register Field Descriptions Field RESERVED UART0DSLPCLKEN Type R R/W NU1 R UART0SLPCLKEN R/W NU2 R UART0RCLKEN R/W Reset 0h 0h 0h 0h 0h 0h Description UART_A0_DSLP_CLK_ENABLE 0h = Disable UART_A0 clk during deep-sleep mode 1h = Enable UART_A0 clk during deep-sleep mode UART_A0_SLP_CLK_ENABLE 0h = Disable UART_A0 clk during sleep mode 1h = Enable UART_A0 clk during sleep mode UART_A0_RUN_CLK_ENABLE 0h = Disable UART_A0 clk during run mode 1h = Enable UART_A0 clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 447 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.27 UART0SWRST Register (offset = 84h) [reset = 0h] UART0SWRST is shown in Figure 15-30 and described in Table 15-30. Figure 15-30. UART0SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-30. UART0SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description UART_A0_ENABLED_STATUS 0h = UART_A0 Clocks/Resets are disabled 1h = UART_A0 Clocks/Resets are enabled UART_A0_SOFT_RESET 0h = De-assert reset for UART_A0 1h = Assert reset for UART_A0 www.ti.com 24 16 8 0 SWRST R/W-0h 448 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.28 UART1CLKEN Register (offset = 88h) [reset = 0h] UART1CLKEN is shown in Figure 15-31 and described in Table 15-31. Figure 15-31. UART1CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-31. UART1CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description UART_A1_DSLP_CLK_ENABLE 0h = Disable UART_A1 clk during deep-sleep mode 1h = Enable UART_A1 clk during deep-sleep mode UART_A1_SLP_CLK_ENABLE 0h = Disable UART_A1 clk during sleep mode 1h = Enable UART_A1 clk during sleep mode UART_A1_RUN_CLK_ENABLE 0h = Disable UART_A1 clk during run mode 1h = Enable UART_A1 clk during run mode SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 449 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.29 UART1SWRST Register (offset = 8Ch) [reset = 0h] UART1SWRST is shown in Figure 15-32 and described in Table 15-32. Figure 15-32. UART1SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-32. UART1SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description UART_A1_ENABLED_STATUS 0h = UART_A1 Clocks/Resets are disabled 1h = UART_A1 Clocks/Resets are enabled UART_A1_SOFT_RESET 0h = De-assert the soft reset for UART_A1 1h = Assert the soft reset for UART_A1 www.ti.com 24 16 8 0 SWRST R/W-0h 450 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.30 GPT0CLKCFG Register (offset = 90h) [reset = 0h] GPT0CLKCFG is shown in Figure 15-33 and described in Table 15-33. Figure 15-33. GPT0CLKCFG Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-33. GPT0CLKCFG Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPT_A0_DSLP_CLK_ENABLE 0h = Disable the GPT_A0 clock during deep-sleep 1h = Enable the GPT_A0 clock during deep-sleep GPT_A0_SLP_CLK_ENABLE 0h = Disable the GPT_A0 clock during sleep 1h = Enable the GPT_A0 clock during sleep GPT_A0_RUN_CLK_ENABLE 0h = Disable the GPT_A0 clock during run 1h = Enable the GPT_A0 clock during run SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 451 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.31 GPT0SWRST Register (offset = 94h) [reset = 0h] GPT0SWRST is shown in Figure 15-34 and described in Table 15-34. Figure 15-34. GPT0SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-34. GPT0SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPT_A0_ENABLED_STATUS 0h = GPT_A0 clocks/resets are disabled 1h = GPT_A0 clocks/resets are enabled GPT_A0_SOFT_RESET 0h = De-assert the soft reset for GPT_A0 1h = Assert the soft reset for GPT_A0 www.ti.com 24 16 8 0 SWRST R/W-0h 452 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.32 GPT1CLKEN Register (offset = 98h) [reset = 0h] GPT1CLKEN is shown in Figure 15-35 and described in Table 15-35. Figure 15-35. GPT1CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-35. GPT1CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPT_A1_DSLP_CLK_ENABLE 0h = Disable the GPT_A1 clock during deep-sleep 1h = Enable the GPT_A1 clock during deep-sleep GPT_A1_SLP_CLK_ENABLE 0h = Disable the GPT_A1 clock during sleep 1h = Enable the GPT_A1 clock during sleep GPT_A1_RUN_CLK_ENABLE 0h = Disable the GPT_A1 clock during run 1h = Enable the GPT_A1 clock during run SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 453 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.33 GPT1SWRST Register (offset = 9Ch) [reset = 0h] GPT1SWRST is shown in Figure 15-36 and described in Table 15-36. Figure 15-36. GPT1SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-36. GPT1SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPT_A1_ENABLED_STATUS 0h = GPT_A1 clocks/resets are disabled 1h = GPT_A1 clocks/resets are enabled GPT_A1_SOFT_RESET 0h = De-assert the soft reset for GPT_A1 1h = Assert the soft reset for GPT_A1 www.ti.com 24 16 8 0 SWRST R/W-0h 454 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.34 GPT2CLKEN Register (offset = A0h) [reset = 0h] GPT2CLKEN is shown in Figure 15-37 and described in Table 15-37. Figure 15-37. GPT2CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-37. GPT2CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPT_A2_DSLP_CLK_ENABLE 0h = Disable the GPT_A2 clock during deep-sleep 1h = Enable the GPT_A2 clock during deep-sleep GPT_A2_SLP_CLK_ENABLE 0h = Disable the GPT_A2 clock during sleep 1h = Enable the GPT_A2 clock during sleep GPT_A2_RUN_CLK_ENABLE 0h = Disable the GPT_A2 clock during run 1h = Enable the GPT_A2 clock during run SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 455 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.35 GPT2SWRST Register (offset = A4h) [reset = 0h] GPT2SWRST is shown in Figure 15-38 and described in Table 15-38. Figure 15-38. GPT2SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-38. GPT2SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPT_A2_ENABLED_STATUS 0h = GPT_A2 clocks/resets are disabled 1h = GPT_A2 clocks/resets are enabled GPT_A2_SOFT_RESET 0h = De-assert the soft reset for GPT_A2 1h = Assert the soft reset for GPT_A2 www.ti.com 24 16 8 0 SWRST R/W-0h 456 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.36 GPT3CLKEN Register (offset = A8h) [reset = 0h] GPT3CLKEN is shown in Figure 15-39 and described in Table 15-39. Figure 15-39. GPT3CLKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-39. GPT3CLKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description GPT_A3_DSLP_CLK_ENABLE 0h = Disable the GPT_A3 clock during deep-sleep 1h = Enable the GPT_A3 clock during deep-sleep GPT_A3_SLP_CLK_ENABLE 0h = Disable the GPT_A3 clock during sleep 1h = Enable the GPT_A3 clock during sleep GPT_A3_RUN_CLK_ENABLE 0h = Disable the GPT_A3 clock during run 1h = Enable the GPT_A3 clock during run SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 457 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.37 GPT3SWRST Register (offset = ACh) [reset = 0h] GPT3SWRST is shown in Figure 15-40 and described in Table 15-40. Figure 15-40. GPT3SWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-40. GPT3SWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description GPT_A3_ENABLED_STATUS 0h = GPT_A3 Clocks/resets are disabled 1h = GPT_A3 Clocks/resets are enabled GPT_A3_SOFT_RESET 0h = De-assert the soft reset for GPT_A3 1h = Assert the soft reset for GPT_A3 www.ti.com 24 16 8 0 SWRST R/W-0h 458 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.38 MCASPCLKCFG0 Register (offset = B0h) [reset = A0000h] MCASPCLKCFG0 is shown in Figure 15-41 and described in Table 15-41. PRCM Registers Figure 15-41. MCASPCLKCFG0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED DIVISR R-0h R/W-Ah 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRACTN R/W-0h Bit 31-26 25-16 Field RESERVED DIVISR 15-0 FRACTN Table 15-41. MCASPCLKCFG0 Register Field Descriptions Type R R/W R/W Reset 0h Ah 0h Description MCASP_FRAC_DIV_DIVISOR If the root clock frequency is Fref and the required output clock frequency is Freq., the ratio of these two frequencies (Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio. MCASP_FRAC_DIV_FRACTION If the root clock frequency is Fref and the required output clock frequency is Freq., the ratio of these two frequencies (Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio. SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 459 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.39 MCASPCLKCFG1 Register (offset = B4h) [reset = 0h] MCASPCLKCFG1 is shown in Figure 15-42 and described in Table 15-42. Figure 15-42. MCASPCLKCFG1 Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 SPARE R/W-0h www.ti.com 25 24 17 16 DIVIDRSWRST R/W-0h 9 8 SPARE R/W-0h 1 0 Bit 31-17 16 15-10 9-0 Field RESERVED DIVIDRSWRST RESERVED SPARE Table 15-42. MCASPCLKCFG1 Register Field Descriptions Type R R/W R R/W Reset 0h 0h 0h 0h Description MCASP_FRAC_DIV_SOFT_RESET 0h = Donot assert the reset for MCASP frac clk-div 1h = Assert the reset for MCASP Frac-clk div MCASP_FRAC_DIV_PERIOD This bitfield is not used in HW. Can be used as a spare RW register. 460 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.40 I2CLCKEN Register (offset = D8h) [reset = 0h] I2CLCKEN is shown in Figure 15-43 and described in Table 15-43. Figure 15-43. I2CLCKEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 NU1 R-0h 7 6 5 4 3 2 NU2 R-0h PRCM Registers 25 24 17 16 DSLPCLKEN R/W-0h 9 8 SLPCLKEN R/W-0h 1 0 RUNCLKEN R/W-0h Bit 31-17 16 Field RESERVED DSLPCLKEN 15-9 8 NU1 SLPCLKEN 7-1 NU2 0 RUNCLKEN Table 15-43. I2CLCKEN Register Field Descriptions Type R R/W R R/W R R/W Reset 0h 0h 0h 0h 0h 0h Description I2C_DSLP_CLK_ENABLE 0h = Disable the I2C clock during deep-sleep 1h = Enable the I2C Clock during deep-sleep I2C_SLP_CLK_ENABLE 0h = Disable the I2C clock during sleep 1h = Enable the I2C clock during sleep I2C_RUN_CLK_ENABLE 0h = Disable the I2C clock during run 1h = Enable the I2C clock during run SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 461 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.41 I2CSWRST Register (offset = DCh) [reset = 0h] I2CSWRST is shown in Figure 15-44 and described in Table 15-44. Figure 15-44. I2CSWRST Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h 25 17 9 1 ENSTS R-0h Bit 31-2 1 Field RESERVED ENSTS 0 SWRST Table 15-44. I2CSWRST Register Field Descriptions Type R R R/W Reset 0h 0h 0h Description I2C_ENABLED_STATUS 0h = I2C clocks/resets are disabled 1h = I2C Clocks/Resets are enabled I2C_SOFT_RESET 0h = De-assert the soft reset for Shared-I2C 1h = Assert the soft reset for Shared-I2C www.ti.com 24 16 8 0 SWRST R/W-0h 462 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.42 LPDSREQ Register (offset = E4h) [reset = 0h] LPDSREQ is shown in Figure 15-45 and described in Table 15-45. Figure 15-45. LPDSREQ Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h PRCM Registers 25 24 17 16 9 8 1 0 LPDSREQ R/W-0h Bit 31-1 0 Field RESERVED LPDSREQ Table 15-45. LPDSREQ Register Field Descriptions Type R R/W Reset 0h 0h Description APPS_LPDS_REQ 1h = Request for LPDS SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 463 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.43 TURBOREQ Register (offset = ECh) [reset = 0h] TURBOREQ is shown in Figure 15-46 and described in Table 15-46. Figure 15-46. TURBOREQ Register 31 30 29 28 27 26 25 RESERVED R-0h 23 22 21 20 19 18 17 RESERVED R-0h 15 14 13 12 11 10 9 RESERVED R-0h 7 6 5 4 3 2 1 RESERVED R-0h Bit 31-1 0 Field RESERVED TURBOREQ Table 15-46. TURBOREQ Register Field Descriptions Type R R/W Reset 0h 0h Description APPS_TURBO_REQ 1h = Request for TURBO www.ti.com 24 16 8 0 TURBOREQ R/W-0h 464 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.44 DSLPWAKECFG Register (offset = 108h) [reset = 0h] DSLPWAKECFG is shown in Figure 15-47 and described in Table 15-47. Figure 15-47. DSLPWAKECFG Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h PRCM Registers 25 24 17 16 9 8 1 EXITDSLPBYN WPEN R/W-0h 0 EXITDSLPBYT MREN R/W-0h Table 15-47. DSLPWAKECFG Register Field Descriptions Bit 31-2 1 Field RESERVED EXITDSLPBYNWPEN Type R R/W 0 EXITDSLPBYTMREN R/W Reset 0h 0h 0h Description DSLP_WAKE_FROM_NWP_ENABLE 0h = Disable NWP to wake APPS from deep-sleep 1h = Enable the NWP to wake APPS from deep-sleep DSLP_WAKE_TIMER_ENABLE 0h = Disable deep-sleep wake timer in APPS RCM 1h = Enable deep-sleep wake timer in APPS RCM for deep-sleep SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 465 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.45 DSLPTIMRCFG Register (offset = 10Ch) [reset = 0h] DSLPTIMRCFG is shown in Figure 15-48 and described in Table 15-48. www.ti.com Figure 15-48. DSLPTIMRCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMROPPCFG TIMRCFG R/W-0h R/W-0h Bit 31-16 Field TIMROPPCFG 15-0 TIMRCFG Table 15-48. DSLPTIMRCFG Register Field Descriptions Type R/W R/W Reset 0h 0h Description DSLP_WAKE_TIMER_OPP_CFG Configuration (in slow_clks) which indicates when to request for OPP during deep-sleep exit. DSLP_WAKE_TIMER_WAKE_CFG Configuration (in slow_clks) which indicates when to request for WAKE during deep-sleep exit. 466 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.46 SLPWAKEEN Register (offset = 110h) [reset = 0h] SLPWAKEEN is shown in Figure 15-49 and described in Table 15-49. Figure 15-49. SLPWAKEEN Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h PRCM Registers 25 24 17 16 9 8 1 EITBYNWP R/W-0h 0 EXITBYTIMR R/W-0h Bit 31-2 1 Field RESERVED EITBYNWP 0 EXITBYTIMR Table 15-49. SLPWAKEEN Register Field Descriptions Type R R/W R/W Reset 0h 0h 0h Description SLP_WAKE_FROM_NWP_ENABLE 0h = Disable the sleep wakeup due to NWP request 1h = Enable the sleep wakeup due to NWP request. SLP_WAKE_TIMER_ENABLE 0h = Disable the sleep wakeup due to sleep-timer 1h = Enable the sleep wakeup due to sleep-timer SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 467 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.47 SLPTMRCFG Register (offset = 114h) [reset = 0h] SLPTMRCFG is shown in Figure 15-50 and described in Table 15-50. www.ti.com Figure 15-50. SLPTMRCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRCFG R/W-0h Bit 31-0 Field TMRCFG Table 15-50. SLPTMRCFG Register Field Descriptions Type R/W Reset 0h Description SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz) for the Sleep wakeup timer. 468 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.48 WAKENWP Register (offset = 118h) [reset = 0h] WAKENWP is shown in Figure 15-51 and described in Table 15-51. Figure 15-51. WAKENWP Register 31 30 29 28 27 26 RESERVED R-0h 23 22 21 20 19 18 RESERVED R-0h 15 14 13 12 11 10 RESERVED R-0h 7 6 5 4 3 2 RESERVED R-0h PRCM Registers 25 24 17 16 9 8 1 0 WAKENWP R/W-0h Bit 31-1 0 Field RESERVED WAKENWP Table 15-51. WAKENWP Register Field Descriptions Type R R/W Reset 0h 0h Description APPS_TO_NWP_WAKEUP_REQUEST When 1 => APPS generated a wake request to NWP (When NWP is in any of its lowpower modes : SLP/DSLP/LPDS) SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 469 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PRCM Registers 15.6.1.49 RCM_IS Register (offset = 120h) [reset = 0h] RCM_IS is shown in Figure 15-52 and described in Table 15-52. www.ti.com 31 23 15 RESERVED R-0h 7 30 29 22 21 14 WAKETIMRIR Q R-0h 13 RESERVED R-0h 6 5 RESERVED R-0h Figure 15-52. RCM_IS Register 28 27 26 25 24 RESERVED R-0h 20 19 18 17 16 RESERVED R-0h 12 11 10 9 8 PLLLOCK RESERVED R-0h 4 R-0h 3 EXITDSLPBYT MR R-0h 2 EXITSLPBYTM R R-0h 1 EXITDSLPBYN WP R-0h 0 EXITSLPBYNW P R-0h Bit 31-15 14 Field RESERVED WAKETIMRIRQ 13 RESERVED 12 PLLLOCK 11-4 3 RESERVED EXITDSLPBYTMR 2 EXITSLPBYTMR 1 EXITDSLPBYNWP 0 EXITSLPBYNWP Table 15-52. RCM_IS Register Field Descriptions Type R R R R R R R R R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description To enable the RTC timer interrupt, set 0th bit of HIB3P3:MEM_HIB_RTC_IRQ_ENABLE(0x4402 F854) and 2nd bit of RCM_IEN(0x124) to '1', 1h = indicates interrupt to the Apps processor due to the RTC timer reaching the programmed value. Enable this interrupt by setting 0th bit of RCM_IEN(0x124). 1h = indicates that an interrupt was received by the processor because of PLL lock. apps_deep_sleep_timer_wake 1h = Indicates that deep-sleep timer expiry had caused the wakeup from deep-sleep. apps_sleep_timer_wake 1h = Indicates that sleep timer expiry had caused the wakeup from sleep. apps_deep_sleep_wake_from_nwp 1h = Indicates that NWP had caused the wakeup from deep-sleep. apps_sleep_wake_from_nwp 1h = Indicates that NWP had caused the wakeup from Sleep 470 Power, Reset and Clock Management SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.6.1.50 RCM_IEN Register (offset = 124h) [reset = 0h] RCM_IEN is shown in Figure 15-53 and described in Table 15-53. PRCM Registers Figure 15-53. RCM_IEN Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED WAKETIMERIR RESERVED PLLLOCKIRQ Q R-0h R/W-0h R-0h R/W-0h Bit 31-3 2 Field RESERVED WAKETIMERIRQ 1 RESERVED 0 PLLLOCKIRQ Table 15-53. RCM_IEN Register Field Descriptions Type R R/W R R/W Reset 0h 0h 0h 0h Description To enable RTC timer interrupt set 0th bit of HIB3P3:MEM_HIB_RTC_IRQ_ENABLE(0x4402 F854) to '1' 0h = Unmask this interrupt. 1h = Unmask interrupt to the Apps processor when RTC timer reaches the programmed value. 0h = Mask this interrupt 1h = Unmask Interrupt to Apps processor when PLL is locked SWRU367B – June 2014 – Revised October 2014 Power, Reset and Clock Management 471 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Chapter 16 SWRU367B – June 2014 – Revised October 2014 IO Pads and Pin Multiplexing Topic ........................................................................................................................... Page 16.1 Overview ......................................................................................................... 473 16.2 IO Pad Electrical Specifications:......................................................................... 473 16.3 Analog-Digital Pin Multiplexing .......................................................................... 475 16.4 Special Ana/DIG Pins ........................................................................................ 476 16.5 Analog Mux Control Registers ........................................................................... 478 16.6 Pins Available for Applications .......................................................................... 480 16.7 Functional Pin Mux Configurations..................................................................... 482 16.8 Pin Mapping Recommendations ......................................................................... 496 472 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Overview 16.1 Overview CC3200 features flexible wide-voltage IOs. Supported features are: • Programmable drive strength from 2mA to 14mA (nominal condition) in steps of 2mA. • Open drain mode. • Output buffer isolation • Automatic output isolation during reset and hibernate. • Configurable pull-up and pull-down (10uA nominal) • Software configurable pad state retention during LPDS Each IO pad cell in CC3200 has the following ports: • PAD: I/O pad connected to package pin and external components. • ODI: Level shifted data from from PAD to core logic • IDO: Input to IO-cell from core. ioden: When level '1' this disables the PMOS xtors of the output stages making them open-drain type. For example I2C may use a open-drain config. Value gets latched at rising edge of RET33. • ioe_n: If level '0' enables the IDO to PAD path. Else PAD is tristated (except for the PU/PD which are independent). • ioen33: This control signal is driven by hibernate controller. Level '1' enables the IDO to PAD path. Else PAD is made HiZ (except for the PU/PD which are independent). This is automatically controlled by hardware to HiZ the main o/p drivers during chip reset (nRESET=0). At first time power-up the chip performs a "Sense on Power"M detection of board level pull up/dn resistors on three specific device pins (SOP0,SOP1,SOP2) and after this is done, this control signal is made high. Note that the user defined IO pads will still remain in HiZ state until the user program configures them. • 3 bit drive strength control (Value gets latched at rising edge of RET33): – i2maen: Level ‘1’ enables the approx 2mA output stage (in parallel with 4mA and 8mA drivers – if they are enabled) – i4maen: Level ‘1’ enables the approx 4mA output stage (in parallel with 2mA and 8mA drivers – if they are enabled) – i8maen: Level ‘1’ enables the approx 8mA output stage (in parallel with 4mA and 2mA drivers – if they are enabled) NOTE: Any drive strength between 2mA and 14mA can be realized by enabling one or more of above drivers together. So treat these 3 pins as 3 bit binary coded strength control. • Pullup/dn controls (Value gets latched at rising edge of RET33. Works independent of these: ioe_n, ioen33, i2maen/i4maen/i8maen) – iwkpuen: 10uA pull up (NOM_25C_3.3V) – iwkpden: 10uA pull down (NOM_25C_3.3V) • RET33: Control signal from hibernate controller module. Puts the IO in low power retention mode. The control and data signals are latched on rising edge (except ioen33). The internal bias for high-speed level-shifter is automatically disabled when RET33 is '1'. By default this signal is controlled by power management state-machine in hibernate controller. By default this signal goes high on entry to hibernate mode. On exit from hibernate, RET33 returns to level 0, to allow device firmware and application software to access the IO pads. 16.2 IO Pad Electrical Specifications: Table 16-1. GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) Parameter Parameter Name Min Nom Max Unit CIN Pin capacitance 4 pF SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 473 IO Pad Electrical Specifications: www.ti.com Table 16-1. GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) (continued) GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) VIH High-level input voltage 0.65*VDD VDD + 0.5V V VIL Low-level input voltage -0.5 0.35*VDD V IIH High-level input current 5 nA IIL Low-level input current 5 nA VOH High-level output voltage (VDD= 3.0V) 2.4 V VOL Low-level output voltage (VDD= 3.0V) 0.4 V High-level source current, VOH=2.4 2-mA Drive 2 mA 4-mA Drive 4 mA 6-mA Drive 6 mA IOH 8-mA Drive 8 mA 10-mA Drive 10 mA 12-mA Drive 12 mA 14-mA Drive 14 mA Low-level sink current, VOH=0.4 2-mA Drive 2 mA 4-mA Drive 4 mA 6-mA Drive 6 mA IOL 8-mA Drive 8 mA 10-mA Drive 10 mA 12-mA Drive 12 mA 14-mA Drive 14 mA Table 16-2. GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53 GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53 Parameter Parameter Name Min Nom Max Unit CIN Pin capacitance VIH High-level input voltage 0.65*VDD 7 pF VDD + 0.5V V VIL Low-level input voltage -0.5 0.35*VDD V IIH High-level input current 50 nA IIL Low-level input current 50 nA VOH High-level output voltage (VDD = 3.0V) 2.4 V High-level source current, VOH = 2.4 2-mA Drive 1.5 mA 4-mA Drive 2.5 mA 6-mA Drive 3.5 mA IOH 8-mA Drive 4.0 mA 10-mA Drive 4.5 mA 12-mA Drive 5.0 mA 14-mA Drive 5.0 mA 474 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Analog-Digital Pin Multiplexing Table 16-2. GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53 (continued) GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53 Low-level sink current, VOH = 0.4 2-mA Drive 1.5 mA 4-mA Drive 2.5 mA 6-mA Drive 3.5 mA IOL 8-mA Drive 4.0 mA 10-mA Drive 4.5 mA 12-mA Drive 5.0 mA 14-mA Drive 5.0 mA Table 16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25 C) Parameter Parameter Name Min Nom Max Unit IOH Pull-Up current, VOH = 2.4 (VDD = 3.0V) 5 uA IOL Pull-Down current, VOL = 0.4 (VDD = 3.0V) 5 uA NOTE: It is recommended that lowest possible drive-strength should be used that is just adequate for the applications. This would minimize the risk of interference to WLAN radio and mitigate any potential degradation of RF sensitivity and performance. The default drive-strength setting is 6mA. 16.3 Analog-Digital Pin Multiplexing CC3200 device implements an advanced analog digital pin multiplexing scheme to maximize the number of functional signals in a compact 64-pin QFN package. Pins are multiplexed with analog-test, RF-test, clock and power-management functionalities. This is shown in the following diagram. The control registers for the analog signal mux and switches (S1 through S10 in Figure 16-1) are described in later section. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 475 Special Ana/DIG Pins www.ti.com Figure 16-1. Board Configuration to use Pins 45 and 52 as Digital Signals 16.4 Special Ana/DIG Pins 16.4.1 Pin 45 and 52: Pin 45 and pin 52 are used by an internal DCDC (ANA2_DCDC) and the RTC XTAL oscillator respectively. These modules use automatic configuration sensing. Hence some board level configuration is required to use pin 45 and pin 52 as digital pads. This is shown below. 476 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Special Ana/DIG Pins NOTE: In CC3200R device, ANA2 DCDC is not required, which allows pin to be always used for digital functions. However pin 47 must be shorted to the supply input. Typically pin 52 will be used up for RTC XTAL in most applications. In some applications however, a 32.768KHz square wave clock may always be available on board. In that such cases the XTAL may be removed freeing up pin 52 for digital functions. The external clock must then be applied at pin 51. For chip to automatically detect this configuration, a 100K pull-up resistor must be connected between pin 52 and the supply line. To prevent false detection, it is recommended that pin 52 be used for output only functionalities. Figure 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 477 Special Ana/DIG Pins www.ti.com 16.4.2 Pin 29 and 30: Pin 29 and pin 30 are reserved for WLAN antenna diversity – where these pins control an external RF switch which multiplexes the RF pin of CC3200 between two antennas. These pins should not be used for other functionalities in general. 16.4.3 Pin 57, 58, 59, 60: These pins are shared by the ADC inputs and digital IO pad cells. Important: The ADC inputs are tolerant upto 1.8 V. The digital pads on the other hand can swing upto 3.63V. Hence care must be taken to prevent accidental damage to the ADC inputs. It is recommended that the output buffer(s) of the digital IOs corresponding to the desired ADC channel should be disabled first (ie. make them HiZ) and thereafter the respective pass switches (S7,S8,S9,S10) should be enabled. 16.5 Analog Mux Control Registers The internal analog switches and muxes for the ana-dig pins must be configured correctly for proper device operation and avoid device damage. Once a digital IO pad cell is routed correctly to the package pin via these analog switches, the functional pin-mux must be configured to select the desired digital interface pin to be brought out of the chip. In other words, these pins require two levels of mux configuration. CC3200 ROM firmware automatically configures the analog switches/mux-es for pins 29, 30, 45, 50, 52, 53 as part of chip initialization sequence which happens after exit from global reset (nRESET pulled high from low) or exit from Hibernate or exit from LPDS. User application code can directly use these six pins like other digital pins. The ADC inputs, on the other hand, can tolerate levels only up to 1.8 V. Application code must therefore enable the analog switches for one or more ADC inputs, after making sure there are no other internal or external driver on these pins that can go above 1.8 V. The output buffer, pull-up and pull-down should be disabled while ADC inputs are connected to the pins to avoid device damage. The following table describes the register bits used to configure the internal analog switches and muxes for the ana-dig pins. Table 16-4. Analog Mux Control Registers and Bits Analog Mux Control Registers and Bits Pin Analog Mux Control Register and Bit Write Values Reset Value Notes 29 Register: MEM_TOPMUXCTRL_IFORCE Address: 0x4402 E178 Bit [0] 0: GPIO26 Digital path not enabled 1: GPIO26 Digital path enabled ANTSEL1 (GPIO26) Device init FW enables the digital 0 path. No user configuration required for the analog mux. 30 Register: MEM_TOPMUXCTRL_IFORCE Address: 0x4402 E178 Bit [1] 0: GPIO27 Digital path not enabled 1: GPIO27 Digital path enabled ANTSEL2 (GPIO27) Device init FW enables the digital 0 path. No user configuration required for the analog mux. Register: MEM_HIB_CONFIG 45 Address: 0x4402 F850 Bit [19] 0: Digital path not enabled 1: Digital path enabled Device init FW enables the digital 0 path. No user configuration required for the analog mux. Register: MEM_HIB_CONFIG 50 Address: 0x4402 F850 Bit [17] 0: Digital path not enabled 1: Digital path enabled Device init FW enables the digital 0 path. No user configuration required for the analog mux. Register: MEM_HIB_CONFIG 52 Address: 0x4402 F850 Bit [16] 0: Digital path not enabled 1: Digital path enabled Device init FW enables the digital 0 path. No user configuration required for the analog mux. 478 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Analog Mux Control Registers Table 16-4. Analog Mux Control Registers and Bits (continued) Register: MEM_HIB_CONFIG 53 Address: 0x4402 F850 Bit [18] Register: ADCSPARE1 57 Address: 0x4402 E8B8 Bit [1] Register: ADCSPARE1 58 Address: 0x4402 E8B8 Bit [2] Register: ADCSPARE1 59 Address: 0x4402 E8B8 Bit [3] Register: ADCSPARE1 60 Address: 0x4402 E8B8 Bit [4] Analog Mux Control Registers and Bits 0: Digital path not enabled 1: Digital path enabled 0 0: ADC channel 0 path is not enabled 1: ADC channel 0 path is 0 enabled 0: ADC channel 1 path is not enabled 1: ADC channel 1 path is 0 enabled 0: ADC channel 2 path is not enabled 1: ADC channel 2 path is 0 enabled 0: ADC channel 3 path is not enabled 1: ADC channel 3 path is 0 enabled Device init FW enables the digital path. No user configuration required for the analog mux. Digital IO cell is always connected to this pin and application software must be make the digital IO HiZ before enabling analog mux to prevent device damage. Digital IO cell is always connected to this pin and application software must be make the digital IO HiZ before enabling analog mux to prevent device damage. Digital IO cell is always connected to this pin and application software must be make the digital IO HiZ before enabling analog mux to prevent device damage. Digital IO cell is always connected to this pin and application software must be make the digital IO HiZ before enabling analog mux to prevent device damage. The following table describes the default behavior and configurations required for some of the ana-dig multiplexed IOs to be used for digital signals. Table 16-5. Board Level Behavior Pin Board Level Configuration and Usage Connected to enable pin of RF switch 29 (ANTSEL1). Other usage not recommended. Connected to enable pin of RF switch 30 (ANTSEL2). Other usage not recommended. VDD_ANA2 (pin 47) must be shorted to 45 input supply rail. Otherwise this pin will be driven by the ANA2 DCDC 50 Generic Input/Output This pin must have an external pullup of 52 100K to supply rail. This pin must be used for output only signals. 53 Generic Input/Output 57 Analog signal (1.8V absolute max. 1.46V full scale) 58 Analog signal (1.8V absolute max. 1.46V full scale) 59 Analog signal (1.8V absolute max. 1.46V full scale) Board Level Behavior Default State At First Powerup or Forced Reset State After Disabling Analog Path(in ACTIVE, LPDS, HIB power modes) Analog is isolated. Digital IO cell is also isolated. Determined by the IO cell state, like other digital IO s. Analog is isolated. Digital IO cell is also isolated. Determined by the IO cell state, like other digital IO s. Analog is isolated. Digital IO cell is also isolated. Analog is isolated. Digital IO cell is also isolated. Analog is isolated. Digital IO cell is also isolated. Analog is isolated. Digital IO cell is also isolated. ADC is isolated. Digital IO cell is directly connected but HiZ. ADC is isolated. Digital IO cell is directly connected but HiZ. ADC is isolated. Digital IO cell is directly connected but HiZ. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. Determined by the IO cell state, like other digital IO s. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 479 Pins Available for Applications www.ti.com Table 16-5. Board Level Behavior (continued) 60 Analog signal (1.8V absolute max. 1.46V full scale) Board Level Behavior ADC is isolated. Digital IO cell is directly connected but HiZ. Determined by the IO cell state, like other digital IO s. 16.6 Pins Available for Applications Table 16-6 shows the pins available for application signals under various board level configurations. Table 16-6. GPIO/Pins Available for Application Pkg Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pins That Can be Used by Application Using 40MHz XTAL Yes = 1 Pins That Can be Used by APplication Using 40MHz TCXO (For Full Industrial Temp Range) Yes = 1 Name 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz XTAL GPIO10 1 1 1 1 1 1 1 1 GPIO11 1 1 1 1 1 1 1 1 GPIO12 1 1 1 1 1 1 1 1 GPIO13 1 1 1 1 1 1 1 1 GPIO14 1 1 1 1 1 1 1 1 GPIO15 1 1 1 1 1 1 1 1 GPIO16 1 1 1 1 1 1 1 1 GPIO17 1 1 1 1 1 1 1 1 VDD_DIG1 VIN_IO1 FLASH_SP I_CLK FLASH_SP I_DOUT FLASH_SP I_DIN FLASH_SP I_CS GPIO22 1 1 1 1 1 1 1 1 TDI 1 1 1 1 TDO 1 1 1 1 GPIO28 1 1 1 1 1 1 1 1 TCK TMS 0 0 0 0 SOP2 1 1 1 1 (TCXO_EN (TCXO_EN (TCXO_EN (TCXO_EN ) ) ) ) WLAN_XT AL_N 0 0 1 1 WLAN_XT AL_P VDD_PLL LDO_IN2 480 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Pins Available for Applications Pkg Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Table 16-6. GPIO/Pins Available for Application (continued) Pins That Can be Used by Application Using 40MHz XTAL Yes = 1 Pins That Can be Used by APplication Using 40MHz TCXO (For Full Industrial Temp Range) Yes = 1 Name 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz XTAL NC NC NC ANTSEL1 ANTSEL2 RF_BG nRESET VDD_PA_I N SOP1 SOP0 LDO_IN1 VIN_DCDC _ANA DCDC_AN A_SW VIN_DCDC _PA DCDC_PA _SW_P DCDC_PA _SW_N DCDC_PA _OUT DCDC_DI G_SW VIN_DCDC _DIG DCDC_AN A2_SW_P DCDC_AN A2_SW_N VDD_ANA 2 VDD_ANA 1 VDD_RAM GPIO0 1 1 1 1 1 1 1 1 RTC_XTAL _P RTC_XTAL _N 0 0 1 1 1 1 1 1 GPIO30 1 1 1 1 1 1 1 1 VIN_IO2 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 481 Functional Pin Mux Configurations www.ti.com Table 16-6. GPIO/Pins Available for Application (continued) Pins That Can be Used by Application Using 40MHz XTAL Yes = 1 Pins That Can be Used by APplication Using 40MHz TCXO (For Full Industrial Temp Range) Yes = 1 Pkg Pin Name 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz 4-Wire JTAG SOP[2:0] = "000" w/ 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ 32KHz XTAL 4-Wire JTAG SOP[2:0] = "000" w/ external 32KHz XTAL 2-Wire JTAG SOP[2:0] = "001" w/ external 32KHz XTAL 55 GPIO1 1 1 1 1 1 1 1 1 56 VDD_DIG2 57 GPIO2 1 1 1 1 1 1 1 1 58 GPIO3 1 1 1 1 1 1 1 1 59 GPIO4 1 1 1 1 1 1 1 1 60 GPIO5 1 1 1 1 1 1 1 1 61 GPIO6 1 1 1 1 1 1 1 1 62 GPIO7 1 1 1 1 1 1 1 1 63 GPIO8 1 1 1 1 1 1 1 1 64 GPIO9 1 1 1 1 1 1 1 1 GND 65 (THERMAL PAD) Total Available for Application 22 24 23 25 22 24 23 25 16.7 Functional Pin Mux Configurations Pin mux configurations supported in CC3200 are listed in Table 16-7. 482 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Table 16-7. Pin Multiplexing Functional Pin Mux Configurations Pkg Pin 1 2 General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO10 I/O No GPIO11 I/O Yes Config Addl Analog Mux No No Muxed Dig. Pin Mux Config with Reg JTAG GPIO_PAD_CONFIG_ No 10 (0x4402 E0C8) GPIO_PAD_CONFIG_ No 11 (0x4402 E0CC) Dig. Pin Mux Config Mode Value 0 1 3 7 6 12 0 1 3 4 6 7 12 13 Function Signal Name Signal Description GPIO10 I2C_SCL General-Purpose I/O I2C Clock GT_PWM06 Pulse-Width Modulated O/P UART1_TX UART TX Data SDCARD_CLK SD Card Clock GT_CCP01 Timer Capture Port GPIO11 General-Purpose I/O I2C_SDA I2C Data GT_PWM07 pXCLK (XVCLK) SDCARD_CM D UART1_RX GT_CCP02 McAFSX Pulse-Width Modulated O/P Free Clock To Parallel Camera SD Card Command Line UART RX Data Timer Capture Port I2S Audio Port Frame Sync Signal Direction I/O O (Open Drain) O O O I I/O I/O (Open Drain) O O I/O I I O LPDS (1) Hi-Z Hi-Z Hi-Z 1 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z (1) LPDS mode: The state of unused GPIOs in LPDS is input with 500 k Ω pulldown. For all used GPIOs , the user can enable internal pulls, which would hold them in a valid state. (2) Hibernate mode: The CC3200 device leaves the digital pins in a Hi-Z state without any internal pulls when the device enters hibernate state. This can cause glitches on output lines unless held at valid levels by external resistors. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 483 Functional Pin Mux Configurations www.ti.com Pkg Pin 3 4 5 General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO12 I/O No GPIO13 I/O Yes GPIO14 I/O Config Addl Analog Mux No No No Table 16-7. Pin Multiplexing (continued) Muxed Dig. Pin Mux Config with Reg JTAG GPIO_PAD_CONFIG_ No 12 (0x4402 E0D0) GPIO_PAD_CONFIG_ No 13 (0x4402 E0D4) GPIO_PAD_CONFIG_ No 14 (0x4402 E0D8) Dig. Pin Mux Config Mode Value 0 3 4 5 7 12 0 5 4 7 12 0 5 7 4 12 Function Signal Name Signal Signal Description Direction GPIO12 McACLK pVS (VSYNC) I2C_SCL General Purpose I/O I2S Audio Port Clock O Parallel Camera Vertical Sync I2C Clock UART0_TX GT_CCP03 GPIO13 I2C_SDA UART0 TX Data Timer Capture Port General-Purpose I/O I2C Data pHS (HSYNC) Parallel Camera Horizontal Sync UART0_RX UART0 RX Data GT_CCP04 Timer Capture Port GPIO14 General-Purpose I/O I2C_SCL I2C Clock GSPI_CLK pDATA8 (CAM_D4) GT_CCP05 General SPI Clock Parallel Camera Data Bit 4 Timer Capture Port I/O O I I/O (Open Drain) O I I/O I/O (Open Drain) I I I I/O I/O (Open Drain) I/O I I LPDS (1) Hi-Z Hi-Z Hi-Z Hi-Z 1 Hi-Z Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 484 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Pkg Pin 6 7 8 9 General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO15 I/O GPIO16 I/O GPIO17 I/O Wake-Up Source VDD_DIG1 Int pwr N/A Config Addl Analog Mux No No No N/A Table 16-7. Pin Multiplexing (continued) Muxed Dig. Pin Mux Config with Reg JTAG GPIO_PAD_CONFIG_ No 15 (0x4402 E0DC) Dig. Pin Mux Config Mode Value 0 5 7 4 8 13 Function Signal Name Signal Signal Description Direction GPIO15 I2C_SDA General-Purpose I/O I2C Data GSPI_MISO General SPI MISO pDATA9 Parallel Camera (CAM_D5) Data Bit 5 SDCARD_DAT SD Card Data A GT_CCP06 Timer Capture Port I/O I/O (Open Drain) I/O I I/O I 0 GPIO16 General-Purpose I/O I/O 7 GPIO_PAD_CONFIG_ No 16 4 (0x4402 E0E0) GSPI_MOSI General SPI I/O MOSI pDATA10 Parallel Camera I (CAM_D6) Data Bit 6 5 UART1_TX UART1 TX Data O 8 SDCARD_CLK SD Card Clock O 13 GT_CCP07 Timer Capture I Port 0 GPIO17 General-Purpose I/O I/O 5 UART1_RX UART1 RX Data I GPIO_PAD_CONFIG_ 7 GSPI_CS General SPI Chip I/O No 17 Select (0x4402 E0E4) 8 SDCARD_CM SD Card I/O D Command Line 4 pDATA11 Parallel Camera I (CAM_D7) Data Bit 7 N/A N/A N/A VDD_DIG1 Internal Digital Core Voltage LPDS (1) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 0 Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 485 Functional Pin Mux Configurations www.ti.com Table 16-7. Pin Multiplexing (continued) Pkg Pin 10 11 12 13 14 15 16 General Pin Attributes Pin Alias Use Select as Wakeup Source VIN_IO1 Sup. input N/A FLASH_SPI_ CLK O N/A FLASH_SPI_ DOUT O N/A FLASH_SPI_ DIN I N/A FLASH_SPI_ CS O N/A GPIO22 I/O No TDI I/O No Config Addl Analog Mux N/A N/A N/A N/A N/A No No Muxed Dig. Pin Mux Config with Reg JTAG N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A GPIO_PAD_CONFIG_ No 22 (0x4402 E0F8) MUXed with JTAG TDI GPIO_PAD_CONFIG_ 23 (0x4402 E0FC) Dig. Pin Mux Config Mode Value N/A N/A N/A N/A N/A 0 7 5 1 0 2 9 Function Signal Name VIN_IO1 FLASH_SPI_ CLK FLASH_SPI_ DOUT FLASH_SPI_ DIN FLASH_SPI_ CS GPIO22 McAFSX GT_CCP04 TDI GPIO23 UART1_TX I2C_SCL Signal Signal Description Direction Chip Supply Voltage (VBAT) Clock To SPI Serial Flash (Fixed Default) Data To SPI Serial Flash (Fixed Default) Data From SPI Serial Flash (Fixed Default) Chip Select To SPI Serial Flash (Fixed Default) General-Purpose I/O I2S Audio Port Frame Sync Timer Capture Port JTAG TDI. Reset Default Pinout. General-Purpose I/O UART1 TX Data I2C Clock O O I O I/O O I I I/O O I/O (Open Drain) LPDS (1) Hi-Z Hi-Z 1 Hi-Z Hi-Z Hi-Z 1 Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 486 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Pkg Pin 17 18 19 20 Table 16-7. Pin Multiplexing (continued) General Pin Attributes Pin Alias Use Select as Wakeup Source TDO I/O Wake-Up Source GPIO28 I/O TCK I/O No TMS I/O No Config Addl Analog Mux No No No No Muxed Dig. Pin Mux Config with Reg JTAG MUXed with JTAG TDO GPIO_PAD_CONFIG_ 24 (0x4402 E100) GPIO_PAD_CONFIG_ 28 (0x4402 E110) MUXed with JTAG/S WDTCK MUXed with JTAG/S WDTMSC GPIO_PAD_CONFIG_ 29 (0x4402 E114) Dig. Pin Mux Config Mode Value 1 0 5 2 9 4 6 0 1 8 1 0 Function Signal Name TDO GPIO24 PWM0 UART1_RX I2C_SDA GT_CCP06 McAFSX GPIO28 TCK GT_PWM03 TMS GPIO29 Signal Signal Description Direction JTAG TDO. Reset Default Pinout. General-Purpose I/O Pulse Width Modulated O/P UART1 RX Data I2C Data Timer Capture Port I2S Audio Port Frame Sync General-Purpose I/O JTAG/SWD TCK Reset Default Pinout Pulse Width Modulated O/P JATG/SWD TMS Reset Default Pinout General-Purpose I/O O I/O O I I/O (Open Drain) I O I/O I O I/O LPDS (1) Hi-Z Hi-Z Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 487 Functional Pin Mux Configurations www.ti.com Table 16-7. Pin Multiplexing (continued) Pkg Pin 21 22 23 24 25 26 27 28 29 30 General Pin Attributes Pin Alias Use Select as Wakeup Source Config Addl Analog Mux Muxed with JTAG SOP2 O Only No No No WLAN_XTAL WLAN _N Ana. N/A WLAN_XTAL WLAN _P Ana. N/A VDD_PLL Int. Pwr N/A N/A N/A N/A N/A N/A N/A LDO_IN2 Int. Pwr N/A N/A N/A NC WLAN Ana. N/A N/A N/A NC WLAN Ana. N/A N/A N/A NC WLAN Ana. N/A N/A N/A User ANTSEL1 O Only No config not No required User ANTSEL2 O Only No config not No required Dig. Pin Mux Config Reg GPIO_PAD_CONFIG_ 25 (0x4402 E104) N/A N/A N/A N/A N/A N/A N/A GPIO_PAD_CONFIG_ 26 (0x4402 E108) GPIO_PAD_CONFIG_ 27 (0x4402 E10C) Dig. Pin Mux Config Mode Value 0 9 2 See (3) See (4) See (3) 0 0 Function Signal Name Signal Signal Description Direction GPIO25 General-Purpose I/O O GT_PWM02 Pulse Width O Modulated O/P McAFSX I2S Audio Port O Frame Sync TCXO_EN Enable to O Optional External 40-MHz TCXO SOP2 Sense-On-Power I 2 WLAN_XTAL_ N 40-MHz XTAL Pulldown if ext TCXO is used. WLAN_XTAL_ 40-MHz XTAL or P TCXO clock input VDD_PLL Internal analog voltage LDO_IN2 Analog RF supply from ANA DC-DC output NC Reserved NC Reserved NC Reserved ANTSEL1 Antenna Selection Control O ANTSEL2 Antenna Selection Control O LPDS (1) Hi-Z Hi-Z Hi-Z O Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (3) For details on proper use, see Section 3.2 of the CC3200 Datasheet (SWAS032), Drive Strength and Reset States for Analog-Digital Multiplexed Pins. (4) This pin is one of three that must have a passive pullup or pulldown resistor on board to configure the chip hardware power-up mode. Because of this reason, if this pin is used for digital functions, it must be output only. 488 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Pkg Pin General Pin Attributes Pin Alias Use Select as Wakeup Source 31 RF_BG WLAN Ana. N/A 32 nRESET Glob. Rst N/A 33 VDD_PA_IN Int. Pwr N/A 34 SOP1 Config Sense N/A 35 SOP0 Config Sense N/A 36 LDO_IN1 Internal Power N/A 37 VIN_DCDC_ Supply ANA Input N/A 38 DCDC_ANA_ Internal SW Power N/A 39 VIN_DCDC_ Supply PA Input N/A 40 DCDC_PA_S Internal W_P Power N/A 41 DCDC_PA_S Internal W_N Power N/A 42 DCDC_PA_O Internal UT Power N/A 43 DCDC_DIG_ Internal SW Power N/A 44 VIN_DCDC_ Supply DIG Input N/A Config Addl Analog Mux N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Table 16-7. Pin Multiplexing (continued) Muxed Dig. Pin Mux Config with Reg JTAG Dig. Pin Mux Config Mode Value Function Signal Name Signal Signal Description Direction N/A N/A RF_BG RF BG band N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A nRESET Master chip reset. Active low. VDD_PA_IN PA supply voltage from PA DC-DC output. SOP1 Sense On Power 1 SOP0 Sense On Power 0 LDO_IN1 Analog RF supply from ana DC-DC output VIN_DCDC_A NA Analog DC-DC input (connected to chip input supply [VBAT]) DCDC_ANA_S Analog DC-DC W switching node. PA DC-DC input VIN_DCDC_PA (connected to chip input supply [VBAT]) DCDC_PA_SW PA DCDC _P switching node DCDC_PA_SW PA DCDC _N switching node DCDC_PA_OU PA buck T converter output DCDC_DIG_S DIG DC-DC W switching node DIG DC-DC input VIN_DCDC_DI (connected to G chip input supply [VBAT]) LPDS (1) Pad States Hib(2) nRESET = 0 SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 489 Functional Pin Mux Configurations www.ti.com Table 16-7. Pin Multiplexing (continued) Pkg Pin 45 (5) 46 47 48 49 General Pin Attributes Pin Alias Use Select as Wakeup Source Config Addl Analog Mux Muxed with JTAG DCDC_ANA2 _SW_P I/O User No config not required No (6) (7) DCDC_ANA2 Internal _SW_N Power N/A VDD_ANA2 Internal Power N/A VDD_ANA1 Internal Power N/A VDD_RAM Internal Power N/A N/A N/A N/A N/A N/A N/A N/A N/A Dig. Pin Mux Config Reg GPIO_PAD_CONFIG_ 31 (0x4402 E11C) N/A N/A N/A N/A Dig. Pin Mux Config Mode Value 0 9 12 2 6 7 See (8) N/A N/A N/A N/A Function Signal Name Signal Description GPIO31 General-Purpose I/O UART0_RX UART0 RX Data McAFSX I2S Audio Port Frame Sync UART1_RX UART1 RX Data McAXR0 I2S Audio Port Data 0 (RX/TX) GSPI_CLK General SPI Clock DCDC_ANA2_ ANA2 DCDC SW_P Converter +ve Switching Node. DCDC_ANA2_ SW_N ANA2 DCDC Converter -ve Switching Node. VDD_ANA2 ANA2 DCDC O VDD_ANA1 VDD_RAM Analog supply fed by ANA2 DCDC output SRAM LDO output Signal Direction I/O I O I I/O I/O LPDS (1) Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z (5) Pin 45 is used by an internal DC-DC (ANA2_DCDC) and pin 52 is used by the RTC XTAL oscillator. These modules use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 45 and pin 52 as digital pads (see Figure 16-2 ). Because the CC3200R device does not require ANA2_DCDC, the pin can always be used for digital functions. However, pin 47 must be shorted to the supply input. Typically, pin 52 is used for RTC XTAL in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. In such cases, the XTAL can be removed to free up pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100K pull-up resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for outputonly functions. (6) Device firmware automatically enables the digital path during ROM boot. (7) VDD_FLASH must be shorted to V supply. (8) For details on proper use, see Section 3.2 of the CC3200 Datasheet (SWAS032), Drive Strength and Reset States for Analog-Digital Multiplexed Pins. 490 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Table 16-7. Pin Multiplexing (continued) Pkg Pin 50 51 General Pin Attributes Pin Alias Use Select as Wakeup Source Config Addl Analog Mux Muxed with JTAG Dig. Pin Mux Config Reg User GPIO_PAD_CONFIG_ GPIO0 I/O No config not No 0 required (0x4402 E0A0) RTC_XTAL_ RTC P Clock N/A N/A N/A N/A Dig. Pin Mux Config Mode Value 0 12 6 7 9 10 3 4 Function Signal Name Signal Signal Description Direction GPIO0 General-Purpose I/O I/O UART0_CTS UART0 Clear To I Send Input (Active Low) McAXR1 I2S Audio Port I/O Data 1 (RX/TX) GT_CCP00 Timer Capture I Port GSPI_CS General SPI Chip I/O Select UART1_RTS UART1 Request O To Send O (Active Low) UART0_RTS UART0 Request O To Send O (Active Low) McAXR0 I2S Audio Port I/O Data 0 (RX/TX) RTC_XTAL_P Connect 32.768kHz XTAL or Froce external CMOS level clock LPDS (1) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 491 Functional Pin Mux Configurations www.ti.com Table 16-7. Pin Multiplexing (continued) General Pin Attributes Function Pad States Pkg Pin Pin Alias Use Select as Config Muxed Dig. Pin Mux Config Dig. Pin Signal Name Wakeup Addl with Reg Mux Source Analog JTAG Config Mux Mode Value Signal Description Signal LPDS(1) Direction Hib(2) nRESET = 0 RTC_XTAL_N Connect 32.768kHz XTAL or connect a 100 kΩ to Vsupply. 0 GPIO32 General-Purpose I/O I/O Hi-Z 52 (9) RTC_XTAL_ N O Only 2 User config not required (10) (11) No GPIO_PAD_CONFIG_ 32 (0x4402 E120) 4 McACLK I2S Audio Port O Hi-Z Clock O McAXR0 I2S Audio Port O Hi-Z Hi-Z Hi-Z Data (Only O Mode Supported On Pin 52) 6 UART0_RTS UART0 Request O 1 To Send O (Active Low) 8 GSPI_MOSI General SPI MOSI I/O Hi-Z 0 GPIO30 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z 9 UART0_TX UART0 TX Data O 1 2 53 GPIO30 I/O No User config not required (10) No GPIO_PAD_CONFIG_ 30 (0x4402 E118) 3 McACLK I2S Audio Port O Hi-Z Clock O McAFSX I2S Audio Port O Hi-Z Frame Sync 4 GT_CCP05 Timer Capture Port I Hi-Z 7 GSPI_MISO General SPI MISO I/O Hi-Z 54 VIN_IO2 Supply Input N/A N/A N/A N/A VIN_IO2 Chip Supply Voltage (VBAT) (9) Pin 45 is used by an internal DC-DC (ANA2_DCDC) and pin 52 is used by the RTC XTAL oscillator. These modules use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 45 and pin 52 as digital pads (see Figure 16-2 ). Because the CC3200R device does not require ANA2_DCDC, the pin can always be used for digital functions. However, pin 47 must be shorted to the supply input. Typically, pin 52 is used for RTC XTAL in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. In such cases, the XTAL can be removed to free up pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100K pull-up resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for outputonly functions. (10) Device firmware automatically enables the digital path during ROM boot. (11) To use the digital functions, RTC_XTAL_N must be pulled high to V supply using 100-K Ω resistor 492 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Pkg Pin 55 56 57 (12) General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO1 I/O No VDD_DIG2 Internal Power N/A GPIO2 Analog Input (up to 1.5 V)/ Digital I/O Wake-Up Source Config Addl Analog Mux No N/A See (13) (14) Table 16-7. Pin Multiplexing (continued) Muxed with JTAG No N/A No Dig. Pin Mux Config Reg GPIO_PAD_CONFIG_ 1 (0x4402 E0A4) N/A GPIO_PAD_CONFIG_ 2 (0x4402 E0A8) Dig. Pin Mux Config Mode Value 0 3 4 6 7 See (15) 0 3 6 7 Function Signal Name GPIO1 UART0_TX pCLK (PIXCLK) UART1_TX GT_CCP01 VDD_DIG2 ADC_CH0 GPIO2 UART0_RX UART1_RX GT_CCP02 Signal Signal Description Direction General-Purpose I/O I/O UART0 TX Data O Pixel Clock From I Parallel Camera Sensor UART1 TX Data O Timer Capture I Port Internal Digital Core Voltage ADC Channel 0 Input (1.5V max) I General-Purpose I/O I/O UART0 RX Data I UART1 RXt Data I Timer Capture I Port LPDS (1) Hi-Z 1 Hi-Z 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z (12) This pin is shared by the ADC inputs and digital I/O pad cells. Important: The ADC inputs are tolerant up to 1.8 V. On the other hand, the digital pads can tolerate up to 3.6 V. Hence, care must be taken to prevent accidental damage to the ADC inputs. TI recommends that the output buffer(s) of the digital I/Os corresponding to the desired ADC channel be disabled first (that is, converted to high-impedance state), and thereafter the respective pass switches (S7, S8, S9, S10) should be enabled (see Section 3.2 of SWAS032, Drive Strength and Reset States for Analog-Digital Multiplexed Pins). (13) Pin 45 is used by an internal DC-DC (ANA2_DCDC) and pin 52 is used by the RTC XTAL oscillator. These modules use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 45 and pin 52 as digital pads (see Figure 16-2 ). Because the CC3200R device does not require ANA2_DCDC, the pin can always be used for digital functions. However, pin 47 must be shorted to the supply input. Typically, pin 52 is used for RTC XTAL in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. In such cases, the XTAL can be removed to free up pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100K pull-up resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for outputonly functions. (14) Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch. (15) For details on proper use, see Section 3.2 of the CC3200 Datasheet (SWAS032), Drive Strength and Reset States for Analog-Digital Multiplexed Pins. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 493 Functional Pin Mux Configurations www.ti.com Pkg Pin 58 (16) 59 (16) 60 (16) General Pin Attributes Pin Alias Use Select as Wakeup Source Analog Input GPIO3 (up to 1.5V)/D No igital I/O. GPIO4 Analog Input (up to 1.5V)/D igital I/O. Wake-up Source Analog Input GPIO5 (up to 1.5V)/D No igital I/O. Config Addl Analog Mux See (17) (18) See (17) (18) See (17) (18) Table 16-7. Pin Multiplexing (continued) Muxed with JTAG No No No Dig. Pin Mux Config Reg GPIO_PAD_CONFIG_ 3 (0x4402 E0AC) GPIO_PAD_CONFIG_ 4 (0x4402 E0B0) GPIO_PAD_CONFIG_ 5 (0x4402 E0B4) Dig. Pin Mux Config Mode Value See (19) 0 6 4 See (19) 0 6 4 See (19) 0 4 6 7 Function Signal Name ADC_CH1 GPIO3 UART1_TX pDATA7 (CAM_D3) ADC_CH2 GPIO4 UART1_RX pDATA6 (CAM_D2) ADC_CH3 GPIO5 pDATA5 (CAM_D1) McAXR1 GT_CCP05 Signal Description ADC Channel 1 Input (1.5V max) General-Purpose I/O UART1 TX Data Parallel Camera Data Bit 3 ADC Channel 2 Input (1.4V max) General-Purpose I/O UART1 RX Data Parallel Camera Data Bit 2 ADC Channel 3 Input (1.4V max) General-Purpose I/O Parallel Camera Data Bit 1 I2S Audio Port Data 1 (RX/TX) Timer Capture Port Signal Direction I I/O O I I I/O I I I I/O I I/O I LPDS (1) Hi-Z 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (16) This pin is shared by the ADC inputs and digital I/O pad cells. Important: The ADC inputs are tolerant up to 1.8 V. On the other hand, the digital pads can tolerate up to 3.6 V. Hence, care must be taken to prevent accidental damage to the ADC inputs. TI recommends that the output buffer(s) of the digital I/Os corresponding to the desired ADC channel be disabled first (that is, converted to high-impedance state), and thereafter the respective pass switches (S7, S8, S9, S10) should be enabled (see Section 3.2 of SWAS032, Drive Strength and Reset States for Analog-Digital Multiplexed Pins). (17) Pin 45 is used by an internal DC-DC (ANA2_DCDC) and pin 52 is used by the RTC XTAL oscillator. These modules use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 45 and pin 52 as digital pads (see Figure 16-2 ). Because the CC3200R device does not require ANA2_DCDC, the pin can always be used for digital functions. However, pin 47 must be shorted to the supply input. Typically, pin 52 is used for RTC XTAL in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. In such cases, the XTAL can be removed to free up pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100K pull-up resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for outputonly functions. (18) Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch. (19) For details on proper use, see Section 3.2 of the CC3200 Datasheet (SWAS032), Drive Strength and Reset States for Analog-Digital Multiplexed Pins. 494 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Functional Pin Mux Configurations Pkg Pin 61 62 63 General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO6 No No GPIO7 I/O No GPIO8 I/O No Config Addl Analog Mux No No No Table 16-7. Pin Multiplexing (continued) Muxed Dig. Pin Mux Config with Reg JTAG GPIO_PAD_CONFIG_ No 6 (0x4402 E0B8) GPIO_PAD_CONFIG_ No 7 (0x4402 E0BC) GPIO_PAD_CONFIG_ No 8 (0x4402 E0C0) Dig. Pin Mux Config Mode Value 0 5 4 3 6 7 0 13 3 10 11 0 6 7 12 Function Signal Name Signal Signal Description Direction GPIO6 General-Purpose I/O I/O UART0_RTS UART0 Request O To Send O (Active Low) pDATA4 Parallel Camera I (CAM_D0) Data Bit 0 UART1_CTS UART1 Clear To I Send Input (Active Low) UART0_CTS UART0 Clear To I Send Input (Active Low) GT_CCP06 Timer Capture I Port GPIO7 General-Purpose I/O I/O McACLKX I2S Audio Port O Clock O UART1_RTS UART1 Request O To Send O (Active Low) UART0_RTS UART0 Request O To Send O (Active Low) UART0_TX UART0 TX Data O GPIO8 General-Purpose I/O I/O SDCARD_IRQ Interrupt from SD I Card (Future support) McAFSX I2S Audio Port O Frame Sync GT_CCP06 Timer Capture I Port LPDS (1) Hi-Z 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 1 Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 495 Pin Mapping Recommendations www.ti.com Pkg Pin 64 65 General Pin Attributes Pin Alias Use Select as Wakeup Source GPIO9 I/O No GND_TAB Config Addl Analog Mux No Table 16-7. Pin Multiplexing (continued) Muxed Dig. Pin Mux Config with Reg JTAG GPIO_PAD_CONFIG_ No 9 (0x4402 E0C4) Dig. Pin Mux Config Mode Value 0 3 6 7 12 Function Signal Name Signal Signal Description Direction GPIO9 General-Purpose I/O I/O GT_PWM05 Pulse Width O Modulated O/P SDCARD_DAT SD Cad Data I/O A McAXR0 I2S Audio Port I/O Data (Rx/Tx) GT_CCP00 Timer Capture I Port Thermal pad and electrical ground LPDS (1) Hi-Z Pad States Hib(2) nRESET = 0 Hi-Z Hi-Z 16.8 Pin Mapping Recommendations For certain high speed interfaces, TI recommends using the following pin groups. Recommended pin groups for I2S: 496 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Signal Data 0 Data 1 Clock Frame Sync Table 16-8. Pin Groups for I2S Audio Interface (I2S) Pin Group #1 Pin Group #2 45 64 50 50 53 62 63 63 Pin Mapping Recommendations Pin Group #3 52 (Tx Only) 50 53 45 Recommended pin groups for SPI: Signal MOSI MISO CLK CS Table 16-9. Pin Groups for SPI SPI Interface (GSPI) Supported Pin Group #1 7 6 5 8 Supported Pin Group #2 52 53 45 50 Recommended pin groups for SD-Card I/F: Signal CLK CMD DATA IRQ (Future Support) Table 16-10. Pin Groups for SD-Card I/F SD Card Master (1 bit Mode) Interface Pin Group #1 1 (GPIO_10) 2 (GPIO_11) 64 (GPIO_09) 63 (GPIO_8) Pin Group #2 7 (GPIO_16) 8 (GPIO_17) 6 (GPIO_15) 63 (GPIO_8) 16.8.1 Pad Configuration Registers for Application Pins The following table lists the configuration registers associated with the device pins. Package Pin # GPIO #(1) Digital Pad Config Register Physical Address 50 GPIO0 / (ANA) GPIO_PAD_CONFIG_0 0x4402 E0A0 55 GPIO1 GPIO_PAD_CONFIG_1 0x4402 E0A4 57 GPIO2 GPIO_PAD_CONFIG_2 0x4402 E0A8 58 GPIO3 GPIO_PAD_CONFIG_3 0x4402 E0AC 59 GPIO4 GPIO_PAD_CONFIG_4 0x4402 E0B0 60 GPIO5 GPIO_PAD_CONFIG_5 0x4402 E0B4 61 GPIO6 GPIO_PAD_CONFIG_6 0x4402 E0B8 62 GPIO7 GPIO_PAD_CONFIG_7 0x4402 E0BC 63 GPIO8 GPIO_PAD_CONFIG_8 0x4402 E0C0 64 GPIO9 GPIO_PAD_CONFIG_9 0x4402 E0C4 1 GPIO10 GPIO_PAD_CONFIG_10 0x4402 E0C8 2 GPIO11 GPIO_PAD_CONFIG_11 0x4402 E0CC 3 GPIO12 GPIO_PAD_CONFIG_12 0x4402 E0D0 4 GPIO13 GPIO_PAD_CONFIG_13 0x4402 E0D4 5 GPIO14 GPIO_PAD_CONFIG_14 0x4402 E0D8 (1) Pins are referred either by number or sometimes more conveniently by the GPIO mapped to that pin. Functionalities available on a pin are not limited to that name. Please refer to the pin-mux table for all possible functional mapping. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 497 Pin Mapping Recommendations www.ti.com Package Pin # GPIO #(1) Digital Pad Config Register Physical Address 6 GPIO15 GPIO_PAD_CONFIG_15 0x4402 E0DC 7 GPIO16 GPIO_PAD_CONFIG_16 0x4402 E0E0 8 GPIO17 GPIO_PAD_CONFIG_17 0x4402 E0E4 11 GPIO18 (SPI_FLASH_CLK)(2) GPIO_PAD_CONFIG_18 0x4402 E0E8 12 GPIO19 (SPI_FLASH_DOUT(2) GPIO_PAD_CONFIG_19 0x4402 E0EC 13 GPIO20 (SPI_FLASH_DIN)(2) GPIO_PAD_CONFIG_20 0x4402 E0F0 14 GPIO21 (SPI_FLASH_CS)(2) GPIO_PAD_CONFIG_21 0x4402 E0F4 15 GPIO22 GPIO_PAD_CONFIG_22 0x4402 E0F8 16 GPIO23 (TDI) GPIO_PAD_CONFIG_23 0x4402 E0FC 17 GPIO24 (TDO) GPIO_PAD_CONFIG_24 0x4402 E100 18 GPIO28 GPIO_PAD_CONFIG_40 0x4402 E140 19 GPIO28 (TCK) GPIO_PAD_CONFIG_28 0x4402 E110 21 GPIO25 (SOP2) GPIO_PAD_CONFIG_25 0x4402 E104 29 GPIO26 (ANTSEL1) GPIO_PAD_CONFIG_26 0x4402 E108 30 GPIO27 (ANTSEL2) GPIO_PAD_CONFIG_27 0x4402 E10C 20 GPIO29 (TMS) GPIO_PAD_CONFIG_29 0x4402 E114 53 GPIO30 (ANA) GPIO_PAD_CONFIG_30 0x4402 E118 45 GPIO31 (DCDC_ANA2_SW_P) GPIO_PAD_CONFIG_31 0x4402 E11C 52 GPIO32 (RTC_XTAL_N) GPIO_PAD_CONFIG_32 0x4402 E120 (2) These four pins are dedicated for the external SPI serial flash. These cannot be used or shared in any way for other functions. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions: 16.8.1.1.1 GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Bit 31-12 11-0 Table 16-11. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description Field Type Reserved R MEM_GPIO_ RW PAD_CONFI G Reset 0 0xC61 Description [3:0] CONFMODE. Determines which functional signal will be routed to the pad. Please refer to the Pin Mux Table. [4] Enable Open Drain mode (eg: when used as I2C). [7:5] DRIVESTRENGTH 111 = 14mA 110 = 12mA 101 = 10mA 100 = 8mA 011 = 6mA 010 = 4mA 001 = 2mA 000 = Output Driver Not Enabled [8] Enable internal weak pull up [9] Enable internal weak pull down [10] Pad output enable override value. level ‘0’ enables the pad output buffer. Else output buffer is TriStated. This does not affect the internal pullup/pull-down which are controlled independently by bit 8 and bit 9 above. [11] This enables over-riding of the pad output buffer enable. When this bit is set to logic '1', then the value in bit 4 above will control the state of the pad output buffer. When this bit is set to logic '0', then the state of the pad output buffer is directly controlled by the peripheral module to which the pad is functionally mux-ed. 498 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Pin Mapping Recommendations 16.8.2 PAD Behavior During Reset and Hibernate By default, all digital pads are HiZ during forced reset (nRESET=0) and hibernate. This includes the serialflash and JTAG pins. On exit from chip reset or hibernate, the SPI-Flash pads and JTAG pads are configured automatically by resident ROM firmware during device initialization. The ROM boot-loader then reads from the external SPI flash the application image, loads it into SRAM and makes a jump. At this point all other digital IOs are in the reset default state (which is HiZ). The application code must configure the IOs. The application code must also configure any associated analog muxes for pins that are shared by both digital and analog or PM functions. 16.8.3 Control Architecture The IO pad data and control path architecture in CC3200 is shown in Figure 16-3. Figure 16-3. IO Pad Data and Control Path Architecture in CC3200 16.8.4 CC3200 Pin-mux Examples Table 16-12 shows recommended pin-out for several application classes. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 499 Pin Mapping Recommendations Table 16-12. Recommended Pin Multiplexing Configurations www.ti.com Pin Number 52 53 45 50 55 57 58 59 60 61 CC3200 Recommended Pinout Grouping Use – Examples (1) Home Wifi Audio ++ Sensor-Tag Security High- Industrial end Toys Home Security Toys Wifi Audio ++ Industrial WiFi Remote w/ 7x7 keypad and audio Sensor DoorLock FireAlarm Toys w/o Cam Industrial Home Appliances Industrial Home Appliances Smart-Plug Industrial Home Appliances" GPIOs External 32 External 32 kHz (2) kHz (2) External TCXO 40 MHZ (-40 to +85°C) Cam + I2S (Tx or Rx) + I2C + SPI + SWD + UART-Tx + (App Logger) 2 GPIO + 1PWM + *4 overlaid wakeup from Hib I2S (Tx & Rx) I2S (Tx & Rx) Cam + I2S + 1 Ch ADC + + 2 Ch ADC + (Tx or Rx) + 1x 4wire 2wire UART + I2C + SWD + UART + 1x SPI + I2C + UART-Tx + 2wire UART + SWD + 2 (App Logger) 1bit SD Card PMW + 6 4 GPIO + + SPI + I2C + GPIO + 3 1PWM + *4 SWD + 3 GPIO with overlaid GPIO + 1 Wake-From- wakeup from PWM + 1 Hib HIB GPIO with Wake-From- Hib I2S (Tx & Rx) I2S (Tx & Rx) I2S (Tx or Rx) 4 Ch ADC + 3 Ch ADC + 2 Ch ADC + + 1 Ch ADC + + 1 Ch ADC + + 2 Ch ADC + 1x 4wire 2wire UART + 2wire UART + 2x 2wire UART (Tx 2 wire UART UART + 1x SPI + I2C + I2C + SWD + UART + 1bit Only) I2C + + SPI + I2C + 2wire UART + SWD + 3 3 PWM + 11 SD Card + SWD + 15 3 PMW + 3 SPI + I2C + PWM + 9 GPIO + 5 SPI + I2C + GPIO + 1 GPIO with SWD + 1 GPIO + 2 GPIO with SWD + 4 PWM + 1 Wake-From- PWM + 6 GPIO with Wake-From- GPIO + 1 GPIO with Hib + 5 GPIO GPIO + 1 Wake-From- Hib PWM + 1 Wake-From- SWD + GPIO with Hib GPIO with Hib Wake-From- Wake-From- Hib Enable Hib for Ext 40 MHz TCXO Pinout #11 Pinout #10 Pinout #9 Pinout #8 Pinout #7 Pinout #6 Pinout #5 Pinout #4 Pinout #3 Pinout #2 Pinout #1 GSPI-MOSI McASP-D0 (Tx) GPIO_32 output only GSPI-MISO MCASPACLKX MCASPACLKX GPIO_30 GPIO_30 GPIO_30 GPIO_30 UART0-TX GPIO_30 UART0-TX GPIO_30 GSPI-CLK McASP-AFSX McASP-D0 GPIO_31 McASP-AFSX McASP-AFSX McASP-AFSX UART0-RX GPIO_31 UART0-RX GPIO_31 GSPI-CS McASP-D1 (Rx) McASP-D1 McASP-D1 McASP-D1 McASP-D1 McASP-D1 UART0-CTS GPIO_0 GPIO_0 GPIO_0 pCLK (PIXCLK) UART0-TX UART0-TX PIXCLK UART0-TX UART0-TX UART0-TX GPIO-1 UART0-TX GPIO_1 GPIO_1 (wake) GPIO2 UART0-RX UART0-RX (wake) GPIO2 UART0-RX GPIO_2 UART0-RX ADC-0 UART0-RX (wake) GPIO_2 (wake) GPIO_2 pDATA7 (D3) UART1-TX ADC-CH1 pDATA7 (D3) UART1-TX GPIO_3 ADC-1 ADC-1 ADC-1 ADC-1 GPIO_3 pDATA6 (D2) UART1-RX (wake) GPIO_4 pDATA6 (D2) UART1-RX GPIO_4 (wake) GPIO_4 ADC-2 ADC-2 (wake) GPIO_4 (wake) GPIO_4 pDATA5 (D1) ADC-3 ADC-3 pDATA5 (D1) ADC-3 ADC-3 ADC-3 ADC-3 ADC-3 ADC-3 GPIO_5 pDATA4 (D0) UART1-CTS GPIO_6 pDATA4 (D0) GPIO_6 GPIO_6 GPIO_6 UART0-RTS GPIO_6 GPIO_6 GPIO_6 (1) Pins marked "wake" can be configured to wake up the chip from HIBERNATE or LPDS state. In the current silicon revision, any wake pin can trigger wake up from HIBERNATE. The wakeup monitor in the hibernate control module logically ORs these pins applying a selection mask. However, wakeup from LPDS state can be triggered only by one of the wakeup pins that can be configured before entering LPDS. The core digital wakeup monitor use a mux to select one of these pins to monitor. (2) The device supports the feeding of an external 32.768-kHz clock. This configuration frees one pin (32K_XTAL_N) to use in output-only mode with a 100K pullup. 500 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Pin Mapping Recommendations Table 16-12. Recommended Pin Multiplexing Configurations (continued) CC3200 Recommended Pinout Grouping Use – Examples (1) 62 McASP- UART1-RTS GPIO_7 McASP- McASP- McASP- McASP- GPIO_7 GPIO_7 GPIO_7 GPIO_7 ACLKX ACLKX ACLKX ACLKX ACLKX 63 McASP-AFSX SDCARD-IRQ McASP-AFSX McASP-AFSX SDCARD-IRQ GPIO_8 GPIO_8 GPIO_8 GPIO_8 GPIO_8 GPIO_8 64 McASP-D0 SDCARD- GT_PWM5 McASP-D0 SDCARD- GPIO_9 GT_PWM5 GT_PWM5 GT_PWM5 GT_PWM5 GPIO_9 DATA DATA 1 UART1-TX SDCARD- GPIO_10 UART1-TX SDCARD- GPIO_10 GT_PWM6 UART1-TX GT_PWM6 GPIO_10 GPIO_10 CLK CLK 2 (wake) SDCARD- (wake) (wake) SDCARD- GPIO_11 (wake) UART1-RX (wake) (wake) (wake) pXCLK CMD GPIO_11 pXCLK CMD GPIO_11 GPIO_11 GPIO_11 GPIO_11 (XVCLK) (XVCLK) 3 pVS (VSYNC) I2C-SCL I2C-SCL pVS (VSYNC) I2C-SCL GPIO_12 I2C-SCL I2C-SCL I2C-SCL GPIO_12 GPIO_12 4 (wake) pHS I2C-SDA I2C-SDA (wake) pHS I2C-SDA GPIO_13 I2C-SDA I2C-SDA I2C-SDA (wake) (wake) (HSYNC) (HSYNC) GPIO_13 GPIO_13 5 pDATA8 (D4) GSPI-CLK GSPI-CLK pDATA8 (D4) GSPI-CLK I2C-SCL GSPI-CLK GSPI-CLK GSPI-CLK I2C-SCL GPIO_14 6 pDATA9 (D5) GSPI-MISO GSPI-MISO pDATA9 (D5) GSPI-MISO I2C-SDA GSPI-MISO GSPI-MISO GSPI-MISO I2C-SDA GPIO_15 7 pDATA10 GSPI-MOSI GSPI-MOSI pDATA10 GSPI-MOSI GPIO_16 GSPI-MOSI GSPI-MOSI GSPI-MOSI GPIO_16 GPIO_16 (D6) (D6) 8 (wake) GSPI-CS GSPI-CS (wake) GSPI-CS GPIO_17 GSPI-CS GSPI-CS GSPI-CS (wake) (wake) pDATA11 pDATA11 GPIO_17 GPIO_17 (D7) (D7) 11 SPI- SPI- SPI- SPI- SPI- SPI- SPI- SPI- SPI- SPI- SPI- FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK FLASH_CLK 12 SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT 13 SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN 14 SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- SPI-FLASH- CS CS CS CS CS CS CS CS CS CS CS 15 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 GPIO_22 16 I2C-SCL GPIO_23 GPIO_23 I2C-SCL GPIO_23 GPIO_23 GPIO_23 GPIO_23 GPIO_23 GPIO_23 GPIO_23 17 I2C-SDA (wake) (wake) I2C-SDA (wake) (wake) (wake) (wake) (wake) GT-PWM0 (wake) GPIO_24 GPIO_24 GPIO_24 GPIO_24 GPIO_24 GPIO_24 GPIO_24 GPIO_24 19 SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK SWD-TCK 20 SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS SWD-TMS 18 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 21 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 TCXO_EN GT_PWM2 GT_PWM2 GPIO_25 out only SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 501 Pin Mapping Recommendations 16.8.5 Wake on Pad CC3200 supports wake from hibernate and LPDS on pad events for up to six pins. The implementation for Hibernate is shown below. www.ti.com Figure 16-4. Wake on Pad for Hibernate Mode Similar capability is available in LPDS mode as well. However, in case of LPDS only one pin can be selected as wake up source at a time. Wakeup sources are covered in detail in the power management section of this document. 16.8.6 Sense on Power CC3200 implements a sense on power scheme. By using a few board level pull resistors CC3200 can be configured by the user to power up in one of the three following modes: 502 IO Pads and Pin Multiplexing Copyright © 2014, Texas Instruments Incorporated SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback www.ti.com Pin Mapping Recommendations 1. Fn4WJ: Functional Mode with 4-wire JTAG mapped to fixed pins 2. Fn2WJ: Functional Mode with 2-wire SWD mapped to fixed pins 3. LDfrUART : UART Load Mode for flashing the system during development and in OEM assembly line (eg: serial flash connected to CC3200R) Sense on Power (SoP) values are sensed from the device pin during power up. This encoding determines the boot flow as well as the default mapping for some of the pins (JTAG, SWD, UART0). Three SoP pins are used for this purpose. Before the device is taken out of reset, the SoP values are made available on a register and determine the device character while powering up. Table 16-13 shows the pull configurations. SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated IO Pads and Pin Multiplexing 503 Pin Mapping Recommendations Table 16-13. Sense on Power Configurations www.ti.com SoP Mode LDfrUART SoP[2] Pullup Fn2WJ Pulldown Fn4WJ Pulldown SoP[1] Pulldown Pulldown Pulldown SoP[0] Pulldown Pullup Pulldown Name Comment UARTLOAD (4-wire JTAG) Factory/Lab Flash/SRAM load through UART Functional development mode. In this mode, twopin JTAG is FUNCTIONAL_2WJ available to the developer. TMS and TCK are available for debugger conecction. Functional development mode. In this mode, four pin JTAG is FUNCTIONAL_4WJ available to developer. TDI, TMS, TCK, and TDO are available for debugger connection. Recommended value of pull resistor for SOP0, SOP1 is 100Kohm. Recommended value of pull resistor for SOP2 is 10Kohm. Note that SOP2 may be used by the application after chip power-up is complete. To avoid spurious SOP value being sensed at power-up, it is strongly recommended that SOP2 pin should be used only for output signals. SOP0 and SOP1, on the other hand, are multiplexed with WLAN analog test pins and not available for application. 504 IO Pads and Pin Multiplexing SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Appendix A SWRU367B – June 2014 – Revised October 2014 Software Development Kit Examples The CC3200 SDK kit contains several examples of sample code for most of the peripherals covered in this document. Table A-1 provides links to examples for each of the peripherals. Also refer to the CC3200 SDK Sample Applications wiki page. Peripheral DMA GPIO UART I2C SPI GPT WDT SD Host I2S ADC Parallel camera interface Table A-1. Peripheral Samples Chapter Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Sample Examples with URLs 1. uDMA Application 2. UART DMA Application 1. Blinky Application 2. Timer Demo Application 1. UART Demo Application 2. UART DMA Application 1. I2C Application 1. SPI Reference Application 1. PWM Application 1. Watchdog Demo Application 1. SDHost Application 2. SDHost FatFS Application 1. Wi-Fi Audio Application 1. ADC Reference 1. Camera Application SWRU367B – June 2014 – Revised October 2014 Software Development Kit Examples 505 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Appendix B SWRU367B – June 2014 – Revised October 2014 CC3200 Miscellaneous Registers This chapter lists miscellaneous registers which do not belong to any one module, but hold information corresponding to multiple modules and peripherals. B.1 Miscellaneous Register Summary Table B-1 lists the memory-mapped registers for the REGISTER_SUMMARY. All register offset addresses not listed in Table B-1 should be considered as reserved locations and the register contents should not be modified. Offset 8Ch 90h 94h 9Ch A0h A4h B0h Acronym DMA_IMR DMA_IMS DMA_IMC DMA_ICR DMA_MIS DMA_RIS GPTTRIGSEL Table B-1. Miscellaneous Register Summary Register Name DMA_IMR Register DMA_IMS Register DMA_IMC Register DMA_ICR Register DMA_MIS Register DMA_RIS Register GPTTRIGSEL Register Section Section B.1.1 Section B.1.2 Section B.1.3 Section B.1.4 Section B.1.5 Section B.1.6 Section B.1.7 506 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] Register mask: FF0Fh DMA_IMR is shown in Figure B-1 and described in Table B-2. Miscellaneous Register Summary Figure B-1. DMA_IMR Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-Fh R/W-1h R/W-1h R/W-1h R/W-1h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-1h R/W-1h R/W-1h R/W-1h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED 3 APSPIWR 2 APSPIRD 1 SDIOMWR Table B-2. DMA_IMR Register Field Descriptions Type R R/W R/W R/W R/W R/W R R/W R/W R/W Reset X Fh 1h 1h 1h 1h X 1h 1h 1h Description ADC_WR_DMA_DONE_INT_MASK bit 15: ADC channel 6 interrupt enable/disable bit 14: ADC channel 4 interrupt enable/disable bit 13: ADC channel 2 interrupt enable/disable bit 12: ADC channel 0 interrupt enable/disable 0h = interrupt enabled 1h = disable corresponding interrupt MCASP_WR_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt MCASP_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt CAM_FIFO_EMPTY_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt CAM_THRESHHOLD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt APPS_SPI_WR_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt APPS_SPI_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt SDIOM_WR_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 507 Miscellaneous Register Summary Table B-2. DMA_IMR Register Field Descriptions (continued) Bit Field 0 SDIOMRD Type R/W Reset 1h Description SDIOM_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt www.ti.com 508 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.2 DMA_IMS Register (offset = 90h) [reset = 0h] Register mask: FF0Fh DMA_IMS is shown in Figure B-2 and described in Table B-3. Miscellaneous Register Summary Figure B-2. DMA_IMS Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED 3 APSPIWR 2 APSPIRD 1 SDIOMWR Table B-3. DMA_IMS Register Field Descriptions Type R R/W R/W R/W R/W R/W R R/W R/W R/W Reset X 0h 0h 0h 0h 0h X 0h 0h 0h Description ADC_WR_DMA_DONE_INT_MASK_SET bit 15: ADC channel 6 DMA Done IRQ bit 14: ADC channel 4 DMA Done IRQ bit 13: ADC channel 2 DMA Done IRQ bit 12: ADC channel 0 DMA Done IRQ 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ MCASP_WR_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ MCASP_RD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ APPS_SPI_WR_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ APPS_SPI_RD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ SDIOM_WR_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 509 Miscellaneous Register Summary www.ti.com Table B-3. DMA_IMS Register Field Descriptions (continued) Bit Field 0 SDIOMRD Type R/W Reset 0h Description SDIOM_RD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ 510 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.3 DMA_IMC Register (offset = 94h) [reset = 0h] Register mask: FF0Fh DMA_IMC is shown in Figure B-3 and described in Table B-4. Miscellaneous Register Summary Figure B-3. DMA_IMC Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED 3 APSPIWR 2 APSPIRD 1 SDIOMWR Table B-4. DMA_IMC Register Field Descriptions Type R R/W R/W R/W R/W R/W R R/W R/W R/W Reset X 0h 0h 0h 0h 0h X 0h 0h 0h Description ADC_WR_DMA_DONE_INT_MASK_CLR bit 15: ADC channel 6 DMA Done IRQ mask bit 14: ADC channel 4 DMA Done IRQ mask bit 13: ADC channel 2 DMA Done IRQ mask bit 12: ADC channel 0 DMA Done IRQ mask 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ MCASP_WR_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ MCASP_RD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ APPS_SPI_WR_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ APPS_SPI_RD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ SDIOM_WR_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 511 Miscellaneous Register Summary www.ti.com Table B-4. DMA_IMC Register Field Descriptions (continued) Bit Field 0 SDIOMRD Type R/W Reset 0h Description SDIOM_RD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ 512 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.4 DMA_ICR Register (offset = 9Ch) [reset = 0h] Register mask: FF0Fh DMA_ICR is shown in Figure B-4 and described in Table B-5. Miscellaneous Register Summary Figure B-4. DMA_ICR Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED 3 APSPIWR 2 APSPIRD 1 SDIOMWR Table B-5. DMA_ICR Register Field Descriptions Type R R/W R/W R/W R/W R/W R R/W R/W R/W Reset X 0h 0h 0h 0h 0h X 0h 0h 0h Description ADC_WR_DMA_DONE_INT_ACK bit 15: ADC channel 6 DMA Done IRQ bit 14: ADC channel 4 DMA Done IRQ bit 13: ADC channel 2 DMA Done IRQ bit 12: ADC channel 0 DMA Done IRQ 0h = No effect 1h = Clear corresponding interrupt MCASP_WR_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt MCASP_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt CAM_FIFO_EMPTY_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt CAM_THRESHHOLD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt APPS_SPI_WR_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt APPS_SPI_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt SDIOM_WR_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 513 Miscellaneous Register Summary Table B-5. DMA_ICR Register Field Descriptions (continued) Bit Field 0 SDIOMRD Type R/W Reset 0h Description SDIOM_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt www.ti.com 514 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.5 DMA_MIS Register (offset = A0h) [reset = 0h] Register mask: FF0Fh DMA_MIS is shown in Figure B-5 and described in Table B-6. Miscellaneous Register Summary Figure B-5. DMA_MIS Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED Table B-6. DMA_MIS Register Field Descriptions Type R R/W R/W R/W R/W R/W R Reset X 0h 0h 0h 0h 0h X Description ADC_WR_DMA_DONE_INT_STS_MASKED bit 15: ADC channel 6 DMA Done IRQ bit 14: ADC channel 4 DMA Done IRQ bit 13: ADC channel 2 DMA Done IRQ bit 12: ADC channel 0 DMA Done IRQ 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive MCASP_WR_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive MCASP_RD_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 515 Miscellaneous Register Summary www.ti.com Table B-6. DMA_MIS Register Field Descriptions (continued) Bit Field 3 APSPIWR 2 APSPIRD 1 SDIOMWR 0 SDIOMRD Type R/W R/W R/W R/W Reset 0h 0h 0h 0h Description APPS_SPI_WR_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive APPS_SPI_RD_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive SDIOM_WR_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive SDIOM_RD_DMA_DONE_INT_STS_MASKED 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask 1h = Corresponding interrupt is active and not masked. Read is nondestructive 516 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.6 DMA_RIS Register (offset = A4h) [reset = 0h] Register mask: FF0Fh DMA_RIS is shown in Figure B-6 and described in Table B-7. Miscellaneous Register Summary Figure B-6. DMA_RIS Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 17 16 RESERVED R-X 15 14 13 12 11 10 9 8 ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD R-X R/W-0h R/W-0h R/W-0h R/W-0h Bit 31-16 15-12 Field RESERVED ADCWR 11 MCASPWR 10 MCASPRD 9 CAMEMPT 8 CAMFULL 7-4 RESERVED 3 APSPIWR 2 APSPIRD 1 SDIOMWR Table B-7. DMA_RIS Register Field Descriptions Type R R/W R/W R/W R/W R/W R R/W R/W R/W Reset X 0h 0h 0h 0h 0h X 0h 0h 0h Description ADC_WR_DMA_DONE_INT_STS_RAW bit 15: ADC channel 6 DMA Done IRQ bit 14: ADC channel 4 DMA Done IRQ bit 13: ADC channel 2 DMA Done IRQ bit 12: ADC channel 0 DMA Done IRQ 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive MCASP_WR_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive MCASP_RD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive CAM_FIFO_EMPTY_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive APPS_SPI_WR_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive APPS_SPI_RD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive SDIOM_WR_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 517 Miscellaneous Register Summary www.ti.com Table B-7. DMA_RIS Register Field Descriptions (continued) Bit Field 0 SDIOMRD Type R/W Reset 0h Description SDIOM_RD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive 1h = Corresponding interrupt is active. Read is non-destructive 518 CC3200 Miscellaneous Registers SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com B.1.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h] GPTTRIGSEL is shown in Figure B-7 and described in Table B-8. Miscellaneous Register Summary Figure B-7. GPTTRIGSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TRIGSEL R-X R/W-0h Bit 31-8 7-0 Field RESERVED TRIGSEL Table B-8. GPTTRIGSEL Register Field Descriptions Type R R/W Reset X 0h Description GPT_TRIG_SEL When this bit is set to logic '1': enable external trigger mode for APPS GPT CP0 and CP1 pin. bit 0: when set '1' enable external GPT trigger 0 on GPTA0 CP0 pin bit 1: when set '1' enable external GPT trigger 1 on GPTA0 CP1 pin bit 2: when set '1' enable external GPT trigger 2 on GPTA1 CP0 pin bit 3: when set '1' enable external GPT trigger 3 on GPTA1 CP1 pin bit 4: when set '1' enable external GPT trigger 4 on GPTA2 CP0 pin bit 5: when set '1' enable external GPT trigger 5 on GPTA2 CP1 pin bit 6: when set '1' enable external GPT trigger 6 on GPTA3 CP0 pin bit 7: when set '1' enable external GPT trigger 7 on GPTA3 CP1 pin SWRU367B – June 2014 – Revised October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CC3200 Miscellaneous Registers 519 Revision History B www.ti.com Revision History B Changes from A Revision (September 2014) to B Revision .......................................................................................... Page • Updated UARTFR Register description. ............................................................................................ 143 • Added Appendix B: CC3200 Miscellaneous Registers. .......................................................................... 507 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision History A Changes from Original (June 2014) to A Revision ......................................................................................................... Page • Added Section 10.4 ....................................................................................................................... 4 • Removed SPI_WAKEUPENABLE register.......................................................................................... 245 • Added EXTCLK bit to SPI_CHCTRL Register ..................................................................................... 256 • Changed to SPI_XFERLEVEL ....................................................................................................... 259 • Removed WDTMIS register. .......................................................................................................... 306 • Removed WDTMIS register. ......................................................................................................... 307 • Added Section 10.4 .................................................................................................................... 314 • Updated image.......................................................................................................................... 332 • Changed Time Stamp Counter from 18-bit to 17-bit. .............................................................................. 347 • Changed CHANNEL0FIFODATA register description. ............................................................................ 362 • Changed CHANNEL2FIFODATA register description. ............................................................................ 363 • Changed CHANNEL4FIFODATA register description. ............................................................................ 364 • Changed CHANNEL6FIFODATA register description. ............................................................................ 365 • Changed possible supported levels from 0x3 to 0x4. ............................................................................. 366 • Changed possible supported levels from 0x3 to 0x4. ............................................................................. 367 • Changed possible supported levels from 0x3 to 0x4. ............................................................................. 368 • Changed possible supported levels from 0x3 to 0x4. ............................................................................. 369 • Fixed Pin totals. ........................................................................................................................ 482 • Added SDCARD_DATA, SDCARD_CLK and SDCARD_CMD values to table. ............................................... 485 • Changed from 1.5V to 1.4V........................................................................................................... 494 520 Revision History SWRU367B – June 2014 – Revised October 2014 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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