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STM8内核编程手册

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STM8内核编程手册,对编程有帮助

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PM0044 Programming manual STM8 CPU programming manual Introduction The STM8 family of HCMOS microcontrollers is designed and built around an enhanced industry standard 8-bit core and a library of peripheral blocks, which include ROM, Flash, RAM, EEPROM, I/O, Serial Interfaces (SPI, USART, I2C,...), 16-bit Timers, A/D converters, comparators, power supervisors etc. These blocks may be assembled in various combinations in order to provide cost-effective solutions for application-specific products. The STM8 family forms a part of the STMicroelectronics 8-bit MCU product line, which finds its place in a wide variety of applications such as automotive systems, remote controls, video monitors, car radio and numerous other consumer, industrial, telecom, and multimedia products. June 2008 Rev 2 1/148 www.st.com Contents Contents PM0044 1 STM8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 STM8 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Enhanced STM8 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 STM8 core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 STM8 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Memory interface architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 STM8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 Direct addressing mode (Short, Long, Extended) . . . . . . . . . . . . . . . . . . 23 5.3.1 Short Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.2 Long Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.3 Extended Direct addressing mode (only for CALLF and JPF) . . . . . . . . 26 5.4 Indexed addressing mode (No Offset, Short, SP, Long, Extended) . . . . . 27 5.4.1 No Offset Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.2 Short Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4.3 SP Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.4 Long Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.5 Extended Indexed (only LDF instruction) . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 Indirect (Short Pointer Long, Long Pointer Long) . . . . . . . . . . . . . . . . . . . 33 5.6 Short Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . 34 5.7 Long Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . . 35 5.8 Indirect Indexed (Short Pointer Long, Long Pointer Long, Long Pointer Extended) addressing mode 36 2/148 PM0044 Contents 5.9 Short Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . 37 5.10 Long Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . . 39 5.11 Long Pointer Indirect Extended Indexed addressing mode . . . . . . . . . . . 41 5.12 Relative Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.13 Bit Direct (Long) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.14 Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . 47 6 STM8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.1 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.3 Code condition bit value notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.4 Memory and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.5 Operation code notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 BCCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 BCPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 BRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 BTJF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 BTJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CALLF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 CALLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 CCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 CLR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CLRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3/148 Contents PM0044 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 CPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CPLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DECW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DIVW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EXG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EXGW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 HALT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 INCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 JPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 JRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 JRxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NEGW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 POPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PUSHW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 RET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4/148 PM0044 Contents RETF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 RLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 RLCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 RLWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 RRCW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 RRWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 RVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SLAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SLLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SRLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SWAPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 TNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 TNZW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5/148 STM8 architecture 1 STM8 architecture PM0044 The 8-bit STM8 Core is designed for high code efficiency. It contains 6 internal registers, 20 addressing modes and 80 instructions. The 6 internal registers include two 16-bit Index registers, an 8-bit Accumulator, a 24-bit Program Counter, a 16-bit Stack Pointer and an 8bit Condition Code register. The two Index registers X and Y enable Indexed Addressing modes with or without offset, along with read-modify-write type data manipulation. These registers simplify branching routines and data/arrays modifications. The 24-bit Program Counter is able to address up to 16-Mbyte of RAM, ROM or Flash memory. The 16-bit Stack Pointer provides access to a 64K-level Stack. The Core also includes a Condition Code register providing 7 Condition flags that indicate the result of the last instruction executed. The 20 Addressing modes, including Indirect Relative and Indexed addressing, allow sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing mode, for instance, permits look-up tables to be located anywhere in the address space, thus enabling very flexible programming and compact C-based code. The stack pointer relative addressing mode permits optimized C compiler stack model for local variables and parameter passing. The Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction Set offers, in addition to standard data movement and logic/arithmetic functions, 8-bit by 8bit multiplication, 16-bit by 8-bit and 16-bit by 16-bit division, bit manipulation, data transfer between Stack and Accumulator (Push / Pop) with direct stack access, as well as data transfer using the X and Y registers or direct memory-to-memory transfers. The number of Interrupt vectors can vary up to 32, and the interrupt priority level may be managed by software providing hardware controlled nested capability. Some peripherals include Direct Memory Access (DMA) between serial interfaces and memory. Support for slow memories allows easy external code execution through serial or parallel interface (ROMLESS products for instance). The STM8 has a high energy-efficient architecture, based on a Harvard architecture and pipelined execution. A 32-bit wide program memory bus allows most of the instructions to be fetched in 1 CPU cycle. Moreover, as the average instruction length is 2 bytes, this allows for a reduction in the power consumption by only accessing the program memory half of the time, on average. The pipelined execution allowed the execution time to be minimized, ensuring high system performance, when needed, together with the possibility to reduce the overall energy consumption, by using different power saving operating modes. Power-saving can be managed under program control by placing the device in SLOW, WAIT, SLOW-WAIT, ACTIVE-HALT or HALT mode (see product datasheet for more details). 6/148 PM0044 STM8 architecture Additional blocks The additional blocks take the form of integrated hardware peripherals arranged around the central processor core. The following (non-exhaustive) list details the features of some of the currently available blocks: ROM Flash RAM Data EEPROM Timers A/D converter I2C SPI USART Watchdog I/O ports User ROM Flash-based devices Sizes up to several Kbytes Sizes up to several Kbytes. Erase/programming operations do not require additional external power sources. Different versions based on 8/16-bit free running or autoreload timer/counter are available. They can be coupled with either input captures, output compares or PWM facilities. PWM functions can have software programmable duty cycle between 0% to 100% in up to 256/65536 steps. The outputs can be filtered to provide D/A conversion. The Analog to Digital Converter uses a sample and hold technique. It has 12-bit resolution. Multi/master, single master, single slave modes, DMA or 1byte transfer, standard and fast I2C modes, 7 and 10-bit addressing. The Serial peripheral Interface is a fully synchronous 3/4 wire interface ideal for Master and Slave applications such as driving devices with input shift register (LCD driver, external memory,...). The USART is a fast synchronous/asynchronous interface which features both duplex transmission, NRZ format, programmable baud rates and standard error detection. The USART can also emulate RS232 protocol. It has the ability to induce a full reset of the MCU if its counter counts down to zero prior to being reset by the software. This feature is especially useful in noisy applications. They are programmable by software to act in several input or output configurations on an individual line basis, including high current and interrupt generation. The basic block has eight bit lines. 1.1 STM8 development support The STM8 family of MCUs is supported by a comprehensive range of development tools. This family presently comprises hardware tools (emulators, programmers), a software package (assembler-linker, debugger, archiver) and a C-compiler development tool. STM8 and ST7 CPUs are supported by a single toolchain allowing easy reuse and portability of the applications between product lines. 7/148 STM8 architecture PM0044 1.2 Enhanced STM8 features ● 16-Mbyte linear program memory space with 3 FAR instructions (CALLF, RETF, JPF) ● 16-Mbyte linear data memory space with 1 FAR instruction (LDF) ● Up to 32 24-bit interrupt vectors with optimized context save management ● 16-bit Stack Pointer (SP=SH:S) with stack manipulation instructions and addressing modes ● New register and memory access instructions (EXG, MOV) ● New arithmetic instructions: DIV 16/8 and DIVW 16/16 ● New bit handling instructions (CCF, BCPL, BCCM) ● 2 x 16-bit index registers (X=XH:XL, Y=YH:YL). 8-bit data transfers address the low byte. The high-byte is not affected, with a reset value of 0. This allows the use of X/Y as 8-bit values. ● Fast interrupt handling through alternate register files (up to 4 contexts) with standard stack compatible mode (for real time OS kernels) ● 16-bit/8-bit stack operations (X, Y, A, CC stacking) ● 16-bit pointer direct update with 16-bit relative offset (ADDW/SUBW for X/Y/SP) ● 8-bit & 16-bit arithmetic and signed arithmetic support 8/148 PM0044 2 Glossary Glossary mnem mnemonic src source dst destination cy duration of the instruction in CPU clock cycles (internal clock) lgth length of the instruction in byte(s) op-code instruction byte(s) implementation (1..4 bytes), operation code. mem memory location imm immediate value off offset ptr pointer pos position byte a byte word 16-bit value short represent a short 8-bit addressing mode long represent a long 16-bit addressing mode EA Effective Address: The final computed data byte address Page Zero all data located at [00..FF] addressing space (single byte address) (XX) content of a memory location XX XX a byte value ExtB Extended Byte MS Most Significant byte of a 16-bit value (MSB) LS Least Significant byte of a 16-bit value (LSB) A Accumulator register X 16-bit X Index register Y 16-bit Y Index register reg A, XL or YL register (1-byte LS part of X/Y), XH or YH (1-byte MS part of X/Y) ndx index register, either X or Y PC 24-bit Program Counter register SP 16-bit Stack Pointer S Stack Pointer LSB CC Condition Code register 9/148 STM8 core description 3 STM8 core description PM0044 3.1 Introduction The CPU has a full 8-bit architecture, with 16-bit operations on index registers (for address computation). Six internal registers allow efficient 8-bit data manipulation. The CPU is able to execute 80 basic instructions. It features 20 addressing modes and can address 6 internal registers and 16 MBytes of memory/peripheral registers. 3.2 CPU registers The 6 CPU registers are shown in the programming model in Figure 1. Following an interrupt, the register context is saved. The context may be saved in two ways: register context switch or pushed onto the stack (please check product datasheet for actual implementation). In the case of a register context switch, all the internal registers (except SP) are replaced by a new set. There are up to 4 register sets - each set being dedicated to one interrupt level (1-3) and one set for the main execution level. When a register context is not available for the interrupt level or the stack compatible mode is chosen, all the registers are pushed onto the stack in the order shown in Figure 2. They are popped from stack in the reverse order. Accumulator (A). The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. Index registers (X and Y). These 16-bit registers are used to create effective addresses or as temporary storage area for data manipulations. In most of the cases, the cross assembler generates a PRECODE instruction (PRE) to indicate that the following instruction refers to the Y register. Both X and Y are automatically saved on interrupt routine branch. Program Counter (PC). The program counter is a 24-bit register used to store the address of the next instruction to be executed by the CPU. It is automatically refreshed after each processed instruction. As a result, the STM8 core can access up to 16-Mbytes of memory. 10/148 PM0044 STM8 core description Figure 1. Programming model 15 XH 15 YH 15 23 16 15 PCE PCH 7 0 A ACCUMULATOR 87 XL 0 X INDEX 87 YL 0 Y INDEX 0 SP STACK POINTER 87 0 PCL PC PROGRAM COUNTER 7 0 V - I1 H I0 N Z C CC CODE CONDITION 11/148 STM8 core description PM0044 Note: Stack Pointer (SP): The stack pointer is a 16-bit register. It contains the address of the next free location of the stack. Depending on the product, the most significant bits can be forced to a preset value. The stack is used to save the CPU context on subroutines calls or interrupts. The user can also directly use it through the POP and PUSH instructions. After an MCU reset the Stack Pointer is set to its upper limit value. It is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit. The previously stored information is then overwritten, and therefore lost. A subroutine call occupies two or three locations. When an interrupt occurs, the CPU registers (CC, X, Y, A, PC) are pushed onto the stack. This operation takes 9 CPU cycles and uses 9 bytes in RAM. The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU is in one of these modes, the latency is reduced. 12/148 PM0044 STM8 core description Figure 2. Context save/restore for interrupts INTERRUPT GENERATION (execute pipeline) Complete instruction in execute stage (1-6 cycles latency) PUSH PCL PUSH PCH PUSH PCE PUSH Y PUSH X PUSH A PUSH CC 9 CPU CYCLES JUMP TO INTERRUPT ROUTINE GIVEN BY THE INTERRUPT VECTOR INTERRUPT RETURN UNSTACK (POP) PCL PCH PCE YL YH XL XH A CC IRET INSTRUCTION STACK (PUSH) POP CC POP A POP X POP Y POP PCE POP PCH POP PCL 9 CPU CYCLES JUMP TO THE ADDRESS GIVEN BY PROGRAM COUNTER (Reload Pipeline) 13/148 STM8 core description PM0044 Global configuration register (CFG_GCR): The global configuration register is a memory mapped register. It controls the configuration of the processor. It contains the AL control bit: ● AL: Activation level If the AL bit is 0 (main), the IRET will cause the context to be retrieved from stack and the main program will continue after the WFI instruction. If the AL bit is 1 (interrupt only active), the IRET will cause the CPU to go back to WFI/HALT mode without restoring the context. This bit is used to control the low power modes of the MCU. In a very low power application, the MCU spends most of the time in WFI/HALT mode and is woken up (through interrupts) at specific moments in order to execute a specific task. Some of these recurring tasks are short enough to be treated directly in an ISR, rather than going back to the main program. In this case, by programming the AL bit to 1 before going to low power (by executing WFI/HALT instruction), the run time/ISR execution is reduced due to the fact that the register context is not saved/restored each time. Condition Code register (CC): The Condition Code register is a 8-bit register which indicates the result of the instruction just executed as well as the state of the processor. These bits can be individually tested by a program and specified action taken as a result of their state. The following paragraphs describe each bit. ● V: Overflow When set, V indicates that an overflow occurred during the last signed arithmetic operation, on the MSB operation result bit. See INC, INCW, DEC, DECW, NEG, NEGW, ADD, ADC, SUB, SUBW, SBC, CP, CPW instructions. ● I1: Interrupt mask level 1 The I1 flag works in conjunction with the I0 flag to define the current interruptability level as shown in the following table. These flags can be set and cleared by software through the RIM, SIM, HALT, WFI, IRET, TRAP and POP instructions and are automatically set by hardware when entering an interrupt service routine. Table 1. Interruptability levels Interruptability Priority I1 I0 Interruptable Main 1 0 Interruptable Level 1 Interruptable Level 2 Non Interruptable Lowest 0 1 ↕ Highest 0 0 1 1 ● H: Half carry bit The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines. For ADDW, SUBW it is set when a carry occurs from bit 7 to 8, allowing to implement byte arithmetic on 16-bit index registers. 14/148 PM0044 STM8 core description ● I0: Interrupt mask level 0 See Flag I1 ● N: Negative When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1). ● Z: Zero When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. ● C: Carry When set, C indicates that a carry or borrow out of the ALU occurred during the last arithmetic operation on the MSB operation result bit (bit 7 for 8-bit result/destination or bit 15 for 16-bit result). This bit is also affected during bit test, branch, shift, rotate and load instructions. See ADD, ADC, SUB, SBC instructions. In bit test operations, C is the copy of the tested bit. See BTJF, BTJT instructions. In shift and rotates operations, the carry is updated. See RRC, RLC, SRL, SLL, SRA instructions. This bit can be set, reset or complemented by software using SCF, RCF, CCF instructions. Example: Addition $B5 + $94 = "C" + $49 = $149 C 7 0 0 10110101 C +0 C =1 7 0 10010100 7 0 01001001 The results of each instruction on the Condition Code register are shown by tables in Section 6: STM8 instruction set. The following table is an example: V I1 H I0 N Z C V 0 0 N Z 1 where: Nothing = Flag not affected Flag name = Flag affected 0= Flag cleared 1= Flag set 15/148 STM8 memory interface 4 STM8 memory interface PM0044 4.1 Note: Program space The program space is 16-Mbyte and linear. To distinguish the 1, 2 and 3 byte wide addressing modes, naming has been defined as shown in Figure 3: ● "Page" [xxxx00h to xxxxFFh]: 256-byte wide memory space with the same two most significant address bytes (xxxx defines the page number). ● "Section" [xx0000h to xxFFFFh]: 64-Kbyte wide memory space with the same most significant address byte (xx defines the section number). The reset and interrupt vector table are placed at address 8000h for the STM8 family. (Note: the base address may be different for later implementations.) The table has 32 4-byte entries: RESET, Trap, NMI and up to 29 normal user interrupts. Each entry consists of the reserved op-code 82h, followed by a 24-bit value: PCE, PCH, PCL address of the respective Interrupt Service Routine. The main program and ISRs can be mapped anywhere in the 16 Mbyte memory space. CALL/CALLR and RET must be used only in the same section. The effective address for the CALL/RET is used as an offset to the current PCE register value. For the JP, the effective address 16 or 17-bit (for indexed addressing) long, is added to the current PCE value. In order to reach any address in the program space, the JPF jump and CALLF call instructions are provided with a three byte extended addressing mode while the RETF pops also three bytes from the stack. As the memory space is linear, sections can be crossed by two CPU actions: next instruction byte fetch (PC+1), relative jumps and, in some cases, by JP (for indexed addressing mode). For safe memory usage, a function which crosses sections MUST: - be called by a CALLF - include only far instructions for code operation (CALLF & JPF) All label pointers are located in section 0 (JP [ptr.w] example: ptr.w is located in section 0 and the jump address in current section) Any illegal op-code read from the program space triggers a MCU reset. 4.2 Data space The data space is 16-Mbyte and linear. As the stack must be located in section 0 and as data access outside section 0/1 can be managed only with LDF instructions, frequently used data should be located in section 0 to get the optimum code efficiency. All data pointers are located in section 0 only. Indexed addressing (with 16-bit index registers and long offset) allows data access over section 0 and 1. All the peripherals are memory mapped in the data space. 16/148 PM0044 Figure 3. Address spaces PROGRAM SPACE FFFFFFh 82h INT28E INT28H INT28L 00807Ch SECTION 256 FF0000h 82h INT1E INT1H INT1L 82h INT0E INT0H INT0L 82h NMIE NMIH NMIL 01FFFFh 82h TRAPE TRAPH TRAPL 82h RESETE RESETH RESETL 008000h 010000h 00FFFFh SECTION 1 00807Fh VECTORS 008000h 0000FFh 000000h PAGE 0 SECTION 0 STM8 memory interface DATA SPACE 3-BYTE ADDRESSING MODE ACCESSIBLE DATA 2-BYTE ADDRESSING MODE BIT HANDLING CAPABILITY POWERFUL DATA MANAGEMENT STACK AREA POINTERS 1-BYTE ADDRESSING MODE BIT HANDLING CAPABILITY FAST DATA ACCESS WITH SHORT GENERATED CODE 17/148 STM8 memory interface PM0044 4.3 Memory interface architecture The STM8 uses a Harvard architecture, with separate program and data memory buses. However, the logical address space is unified, all memories sharing the same 16-Mbytes space, non-overlapped. The memory interfaces are shown in Figure 4. It consists of two buses: address, data, read/write control signal (R/W) and memory acknowledge signal (STALL). The STALL acknowledge signal makes the CPU compatible with slow serial or parallel memory interfaces. When the memory interface is slow the CPU waits the memory acknowledge before executing the instruction. So in such a case, the instruction CPU cycle time is prolonged compare to the value given in this manual. The program memory bus is 32-bit wide, allowing the fetch of most of the instructions in one cycle. As the address space is unified, the architecture allows data to be stored also in the Flash memory and program to be fetched also from RAM (data bus). In this later case the performance is impacted, besides the fact that data and fetch operation share the same bus, the instructions will be fetched one byte at a time, thus taking longer (1 cycle /byte). Figure 4. Memory Interface Architecture Memory Interface (Flash) DATABUS (FETCH) @BUS STALL "LDF" INSTRUCTION D31..0 00h Data@E Data@E0:H:L A23..0 24 CPU N Y 7 @DATABUS 24 @DATABUS 24 17 PROGRAM COUNTER PCE PCH PCL 24 RAM FETCH INSTRUCTION N Y @BUS DATABUS STALL D7..0 A15..0 R/W Memory Interface (RAM) 18/148 PM0044 5 STM8 addressing modes STM8 addressing modes The STM8 core features 18 different addressing modes which can be classified in 8 main groups: Addressing mode groups Inherent Immediate Direct Indexed SP Indexed Indirect Relative Bit operation Example NOP LD A,#$55 LD A,$55 LD A,($55,X) LD A,($55,SP) LD A,([$55],X) JRNE loop BSET byte,#5 The STM8 Instruction set is designed to minimize the number of required bytes per instruction. To do so, most of the addressing modes can be split in three sub-modes called extended, long and short: ● The extended addressing mode ("e") can reach any byte in the 16-Mbyte addressing space, but the instruction size is bigger than the short and long addressing mode. Moreover, the number of instructions with this addressing mode (far) is limited (CALLF, RETF, JPF and LDF) ● The long addressing mode ("w") is the most powerful for program management, when the program is executed in the same section (same PCE value). The long addressing mode is optimized for data management in the first 64-Kbyte addressing space (from 000000h to 00FFFFh) with a complete set of instructions, but the instruction size is bigger than the short addressing mode. ● The short addressing mode ("b") is less powerful because it can only access the page zero (from 000000h to 0000FFh), but the instruction size is more compact. Table 2. STM8 addressing mode overview Mode Syntax Inherent Immediate Short Long Extended No Offset Short Short Long Extended Direct Direct Direct Direct Direct Direct Direct Direct Indexed Indexed SP Indexed Indexed Indexed NOP LD A,#$55 LD A,$10 LD A,$1000 LDF A,$100000 LD A,(X) LD A,($10,X) LD A,($10,SP) LD A,($1000,X) LDF A,($100000,X) Destination address 000000..0000FF 000000..00FFFF 000000..FFFFFF 000000..00FFFF 000000..0100FE 00..(FF+Stacktop) 000000..01FFFE 000000..FFFFFF Pointer address Pointer size 19/148 STM8 addressing modes PM0044 Pointer size Table 2. STM8 addressing mode overview Mode Syntax Destination address Pointer address Short Pointer Long Indirect LD A,[$10.w] 000000..00FFFF 000000..0000FF 2 Long Pointer Long indirect LD A,[$1000.w] 000000..00FFFF 000000..00FFFF 2 Long Pointer Extended indirect LDF A,[$1000.e] 000000..FFFFFF 000000..00FFFF 3 Short Pointer Long Indirect Indexed LD A,([$10.w],X) 000000..01FFFE 000000..0000FF 2 Long Pointer Long Indirect Indexed (X only) LD A,([$1000.w],X) 000000..01FFFE 000000..00FFFF 2 Long Pointer Extended Indirect Indexed LDF A,([$1000.e],X) 000000..FFFFFF 000000..00FFFF 3 Relative Direct JRNE loop PC+127/-128 Bit Long Direct BSET $1000,#7 000000..00FFFF Bit Long Direct Relative BTJT $1000,#7,skip 000000..00FFFF PC+127/-128 20/148 PM0044 STM8 addressing modes 5.1 Inherent addressing mode All related instructions are 1 or 2 byte. The op-code fully specifies all required information for the CPU to process the operation. Instruction Function NOP No operation TRAP WFI, WFE HALT RET RETF IRET SIM RIM SCF S/W Interrupt Wait For Interrupt / Event (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Far Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag RCF RVF CCF LD, LDW CLR, CLRW PUSH, POP, PUSHW, POPW INC, DEC, INCW, DECW TNZ, TNZW Reset Carry Flag Reset Overflow Flag Complement Carry Flag Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero CPL, NEG, CPLW, NEGW MUL DIV, DIVW EXG, EXGW SLA, SLL, SRL, SRA, RLC, RRC, SLAW, SLLW, SRLW, SRAW, RLCW, RRCW SWAP, SWAPW 1’s or 2’s Complement Byte Multiplication Division Exchange Shift and Rotate Operations Swap Nibbles/Bytes Example: 1000 98 RCF ; Reset carry flag 1001 9D NOP ; No operation 1002 9F LD A,X; Transfer X register content into accumulator 1004 88 PUSH A; Push accumulator content onto the stack 21/148 STM8 addressing modes PM0044 5.2 Immediate addressing mode The data byte required for the operation, follows the op-code. Immediate instruction LD, MOV, LDW CP, CPW BCP AND, OR, XOR ADC, ADD, SUB, SBC, ADDW, SUBW PUSH Function Load and move operation Compare Bit Compare Logical Operations Arithmetic Operations Stack Operations These are two byte instructions, one for the op-code and the other one for the immediate data byte. Example: 05BA AEFF LD 05BC A355 CP 05BE A6F8 LD Action: X,#$FF X,#$55 A,#$F8 Load X = $FF Compare (X, $55) A = $F8 Figure 5. Immediate addressing mode example Before Completion LD A, #0F8h A6 05BE F8 05BF 05C0 A Previous Value PC 05BE Steps to Determine Effective Address PC = 05BE PC = PC + 1 = 05BF EA = PC = 05BF New PC = PC + 1 = 05C0 After Completion A6 05BE F8 05BF 05C0 A F8 New PC 05C0 Instruction Complete A = (EA) = F8 New PC = 05C0 VR02059A 22/148 PM0044 STM8 addressing modes 5.3 Direct addressing mode (Short, Long, Extended) Addressing mode Short Long Extended Direct Direct Direct Syntax shortmem longmem extmem EA formula (shortmem) (longmem) (extmem) Ptr Adr op + 1 op + 1..2 op + 1..3 Ptr Size Byte Word Ext word Dest adr 00..FF 0000..FFFF 000000..FFFFFF The data byte required for the operation is found by its memory address, which follows the op-code. Direct addressing mode is made of three sub-modes: Available Long and Short Direct instructions Function LD, LDW Load CP AND, OR, XOR ADC, ADD, SUB, SBC, ADDW, SUBW BCP MOV CLR INC, DEC TNZ Compare Logical Operations Arithmetic Addition/Subtraction operations Bit Compare Move Clear Increment/Decrement Test Negative or Zero CPL, NEG SLA, SLL, SRL, SRA, RLC, RRC SWAP CALL, JP 1’s or 2’s Complement Shift and Rotate Operations Swap Nibbles Call or Jump subroutine Available Extended Direct instructions only Function CALLF, JPF Call or Jump FAR subroutine Available Long Direct instructions only EXG PUSH, POP Exchange Stack operation Function 23/148 STM8 addressing modes PM0044 5.3.1 Short Direct addressing mode The address is a byte, thus require only one byte after the op-code, but only allow 00..FF addressing space. Example: 004B 052D 20 coeff B64B dc.b LD Action: A = (coeff) = ($4B) = $20 $20 A,coeff Figure 6. Short Direct addressing mode example Before Completion Coeff .byte 20h LD A,Coeff 20 004B B6 052D 4B 052E 052F A Previous Value PC 052D EA 004B Steps to Determine Effective Address PC = 052D PC = PC + 1 = 052E EA = (PC) = (4B + 0000) = 004B Coeff .byte 20h LD A,Coeff After Completion A 20 004B 20 B6 052D 4B 052E 052F New PC 052F Instruction Complete A = (EA) = 20 New PC = PC +1 =052F VR02059L 24/148 PM0044 STM8 addressing modes 5.3.2 Long Direct addressing mode The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes after the op-code. Example: 0409 C606E5 06E5 40 coeff LD dc.b A,coeff $ 40 Action: A = (coeff) = ($06E5) = $40 Figure 7. Long Direct addressing mode example Before Completion LD A,Coeff A Previous Value PC Steps to Determine Effective Address C6 0409 0409 06 040A 06E5 E5 040B PC = 0409 PC = PC + 1 = 040A EA = (PC) : (PC+1) = 06E5 040C Coeff .byte 040h 40 06E5 EA 06E5 After Completion LD A,Coeff C6 0409 06 040A E5 040B 040C Coeff .byte 040h 40 06E5 New PC 040C A 40 Instruction Complete A = (EA) = 40 New PC = PC + 2 = 040C VR02059B 25/148 STM8 addressing modes PM0044 5.3.3 Extended Direct addressing mode (only for CALLF and JPF) The address is an extended word, thus allowing 000000 to FFFFFF addressing space, but requires 3 bytes after the op-code. Example: 000409 0106E5 8D0106E5 4C sw_routine CALLF sw_routine INC A Action: PC = $0106E5 Figure 8. Far Direct addressing mode example Before Completion CALLF sw_routine A Previous Value PC Steps to Determine Effective Address 8D 0409 0409 01 040A 0106E5 06 040B E5 040C PC = 0409 PC=PC+1 EA=(PC):(PC+1):(PC+2) =0106E5 New PC = EA INC A EA 0106E5 4C 0106E5 After Completion CALLF sw_routine INC A 8D 0409 01 040A 06 040B E5 040C 4C 0106E5 Instruction Complete New PC = 0106E5 New PC 0106E5 VR02059U 26/148 PM0044 STM8 addressing modes 5.4 Indexed addressing mode (No Offset, Short, SP, Long, Extended) Addressing mode No offset Short Stack Pointer Long Direct Indexed Direct Indexed Direct Indexed Direct Indexed Extended Direct Indexed Syntax EA formula Ptr Adr Ptr Size Dest adr (ndx) (ndx) --- --- (shortoff,ndx) (ptr + ndx) op + 1 Byte 00..FFFF 00..100FE (shortoff,SP) (ptr + SP) op + 1 Byte 00..(FF+stacktop) (longoff,ndx) (ptr.w + ndx) op + 1..2 Word 000000..01FFFE (extoff,ndx) (ptr.e + ndx) op + 1..3 Ext Word 000000..FFFFFF The data byte required for operation is found by its memory address, which is defined by the unsigned addition of an index register (X or Y or SP) with an offset which follows the opcode. The indexed addressing mode is made of five sub-modes: No Offset, Long, Short and SP Indexed instructions LD, LDW CLR CP AND, OR, XOR ADC, ADD, SUB, SBC, ADDW, SUBW INC, DEC TNZ CPL, NEG SLA, SLL, SRL, SRA, RLC, RRC SWAP Function Load Clear Compare Logical Operations Arithmetic Addition/Subtraction operations Increment/Decrement Test Negative or Zero 1’s or 2’s Complement Shift and Rotate Operations Swap Nibbles No Offset, Long, Short Indexed Instructions Function CALL, JP Call or Jump subroutine Extended Indexed Instructions only LDF Far Load Function 27/148 STM8 addressing modes PM0044 5.4.1 No Offset Indexed addressing mode There is no offset, (no extra byte after the op-code), but only allows 00..FF addressing space. Example: 00B8 05F2 05F4 11223344 table AEB8 F6 dc.w $1122, $3344 LD X,#table LD A,(X) Action: X = table A = (X) = (table) = ($B8) = $11 Figure 9. No Offset Indexed addressing mode example Before completion Table .word 1122 11 22 33 44 LD A,(X) F6 00B8 00B9 00BA 00BB 05F4 A Previous Value X B8 Steps to determine Effective Address PC = 05F4 EA = X + 0000 = 00B8 PC 05F4 EA 00B8 After completion A Table .word 1122 11 00B8 11 22 X 33 B8 44 Instruction Complete A = (EA) = 11 New PC = PC +1 = 05F5 LD A,(X) F6 05F4 05F5 New PC 05F5 VR02059C 28/148 PM0044 STM8 addressing modes 5.4.2 Short Indexed addressing mode The offset is a byte, thus requires only one byte after the op-code, but only allows 00..1FE addressing space. Example: 0089 11223344 0759 AE03 075B E689 table dc.l LD LD $11223344 X,#3 A,(table,X) Action: X=3 A = (table, X) = ($89, X) = ($89, 3) = ($8C) = $44 Figure 10. Short Indexed - 8-bit offset - addressing mode example Before completion Table .long 11223344 11 0089 22 008A 33 008B 44 008C LD A, (table,X) E6 075B 89 075C 075D A Previous Value X 03 PC 075B Steps to determine Effective Address PC = 075B PC = PC + 1 = 075C EA = (PC) + X = 89 + 03 = 008C 89 03 Adder EA 008C After Completion Table .long 11223344 11 0089 22 008A 33 008B 44 008C LD A, (table,X) E6 075B 89 075C 075D A 44 X 03 New PC 075D Instruction Complete A = (EA) = 44 New PC = PC + 1 = 075D VR02059D 29/148 STM8 addressing modes PM0044 5.4.3 SP Indexed addressing mode The offset is a byte, thus require only one byte after the op-code, but only allow 00..(FF + stack top) addressing space. Example: 0086 4B11 0087 4B22 0088 4B33 0089 7B03 PUSH #$11 PUSH #$22 PUSH #$33 LD A,($03,SP) Action: A = ($03, SP) = ($03, $1FFC) = ($1FFF) = $11 Figure 11. SP Indexed - 8-bit offset - addressing mode example Before completion LD A, ($03,SP) 7B 0089 03 008A 008B 1FFC 33 1FFD 22 1FFE 11 1FFF PC 0089 A Previous Value SP 1FFC Steps to determine effective address PC = 0089 PC = PC + 1 = 008A EA = (PC) + SP=03+1FFC= 1FFF 1FFC 03 Adder EA 1FFF After completion LD A, ($03,SP) 7B 0089 03 008A 008B 1FFC 33 1FFD 22 1FFE 11 1FFF New PC 008B SP 1FFC A 11 Instruction Complete A = (EA) = 11 New PC = PC+1 = 008B VR02059D 30/148 PM0044 STM8 addressing modes 5.4.4 Long Indexed addressing mode The offset is a word, thus allowing up to 128 KB addressing space, but requires 2 bytes after the op-code. Example: 0690 AE02 LD X,#2 0692 D6077E LD A,(table,X) 077E BF table dc.b $BF 86 dc.b $86 DBCF dc.w $DBCF Action: X=2 A = (table, X) = ($077E, X) = ($077E, 2) = ($0780) = $DB Figure 12. Long Indexed - 16-bit offset - addressing mode example Before completion LD A, (table, X) table . byte BF D6 0692 07 0693 7E 0694 BF 077E 86 077F DB 0780 CF 0781 PC 0692 X 02 A Previous Value Steps to Determine Effective Address PC = 0692 PC = PC + 1 = 0693 EA = (PC):(PC+1) + X = 077E + 02 = 0780 077E 02 Adder LD A, (table, X) table . byte BF EA 0780 After Completion D6 0692 07 0693 7E 0694 0695 X 02 New PC 0695 BF 077E 86 077F A DB 0780 DB CF 0781 Instruction Complete A = (EA) = DB New PC = PC + 2 = 0695 VR02059E 31/148 STM8 addressing modes PM0044 5.4.5 Extended Indexed (only LDF instruction) The offset is an extended word, thus allowing 16Mbyte addressing space (from 000000 to FFFFFF), but requires 3 bytes after the op-code. Example: 0690 AE02 0692 AF010780 010780 BF table 86 DDFE LD X,#2 LDF A,(table,X) dc.b $BF dc.b $86 dc.w $DDFE Action: X = 2, A = (table, X) = ($010780,X) = ($010780+2)) = ($010782) = $DD Figure 13. Far Indexed - 16-bit offset - addressing mode example Before Completion PC Steps to determine LDF A, (table, X) AF 0692 0692 Effective Address 01 0693 07 0694 80 0695 PC = 0692 X PC = PC + 1 = 0693 02 EA= (PC):(PC+1):(PC+2)+X A = 010780+02 = 010782 table . byte BF BF 010780 Previous Value 86 010781 010780 02 DD 010782 Adder FE 010783 LD A, (table, X) EA 010782 After Completion X AF 0692 02 01 0693 07 0694 80 0695 0696 New PC 0696 Instruction Complete A = (EA) = DD New PC = PC+3 = 0696 table . byte BF BF 010780 86 010781 A DD 010782 DD FE 010783 VR02059R 32/148 PM0044 STM8 addressing modes 5.5 Indirect (Short Pointer Long, Long Pointer Long) Addressing mode Short Pointer Long Indirect Long Pointer Long Indirect Syntax EA formula Ptr Adr Ptr Size ((shortptr.w)) ((shortptr.w)) 00..FF Word ((longptr.w)) ((longptr.w)) 0000..FFFF Word Dest adr 0000..FFFF 0000..FFFF The data byte required for the operation is found by its memory address, located in memory (pointer). The pointer address follows the op-code. The indirect addressing mode is made of three sub-modes: Available Long Pointer Long and Short Pointer Long Indirect Instructions LD, LDW CP AND, OR, XOR ADC, ADD, SUB, SBC BCP CALL, JP Function Load Compare Logical Operations Arithmetic Addition/Subtraction operations Bit Compare Call or Jump subroutine Available Long Pointer Long Indirect Instructions CLR TNZ CPL, NEG SLA, SLL, SRL, SRA, RLC, RRC SWAP INC, DEC Function Clear Test Negative or Zero 1’s or 2’s Complement Shift and Rotate Operations Swap Nibbles Increment/Decrement 33/148 STM8 addressing modes PM0044 5.6 Short Pointer Indirect Long addressing mode The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 1 byte after the op-code. Example: 0040 42E5 ptr dc.w var 0409 92C640 LD A,[shortptr.w] 42E5 11 Action: var dc.b $11 A = [shortptr.w] = ((shortptr.w)) = (($40.w)) = ($42E5) = $11 Figure 14. Short Pointer Indirect Long addressing mode example Before Completion ptr .word var LD A, [shortptr.w] 42 0040 E5 0041 92 0409 C6 040A 40 040B 040C A Previous Value PC 0409 Steps to determine Effective Address PC = 0409 PC = PC + 2 = 40B EA = ((PC)) :((PC)+1) = 42E5 var.byte 011h 11 42E5 EA 42E5 ptr .word var LD A, [shortptr.w] var .byte 011h After Completion 42 0040 E5 0041 92 0409 C6 040A 40 040B 040C 11 42E5 New PC 040C A 11h Instruction Complete A = (EA) = 11h New PC = PC +1 = 040C 34/148 PM0044 STM8 addressing modes 5.7 Long Pointer Indirect Long addressing mode The pointer address is a word, the pointer size is a word, thus allowing 64 KB addressing space, and requires 2 bytes after the op-code. Example: 1040 1409 42E5 42E5 72C61040 11 ptr dc.w var LD A,[longptr.w] var dc.b $11 Action: A = [longptr.w] = ((longptr.w)) = (($1040.w)) = ($42E5) = $11 Figure 15. Long Pointer Indirect Long addressing mode example Before Completion Steps to determine Effective Address ptr .word var LD A, [longptr.w] 42 1040 E5 1041 72 1409 C6 140A 10 140B 40 140C 140D A Previous Value PC 1409 PC = 1409 PC = PC + 2 = 140B EA =((PC):(PC+1)): ((PC):(PC+1)+1) = 42E5 EA 42E5 var.byte 011h 11 42E5 ptr .word var LD A, [longptr.w] var .byte 11h After Completion 42 1040 E5 1041 72 1409 C6 140A 10 140B 40 140C 140D 11 42E5 New PC 040D A 11h Instruction complete A = (EA) = 11h New PC = PC + 2 = 140D VR02059G 35/148 STM8 addressing modes PM0044 5.8 Indirect Indexed (Short Pointer Long, Long Pointer Long, Long Pointer Extended) addressing mode Addressing mode Syntax EA formula Ptr Adr Short Pointer Long Long Pointer Long Long Pointer Extended Indirect Indirect Indirect Indexed ([shortptr.w],ndx) ((shortptr.w) + ndx) 00..FF Indexed ([longptr.w],ndx) ([longptr.w] +ndx) 00..FFFF Indexed ([longptr.e],ndx) ([longptr.e] +ndx) 00..FFFF Ptr Size Dest adr Word 000000.01FFFE Word 000000.01FFFE Extword 000000.FFFFFE This is a combination of indirect and indexed addressing mode. The data byte required for the operation is found by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the op-code. The indirect indexed addressing mode is made of four sub-modes: Available Long Pointer Long and Short Pointer Long Indirect Indexed instructions LD, LDW CP AND, OR, XOR ADC, ADD, SUB, SBC BCP CALL, JP Function Load Compare Logical Operations Arithmetic Addition/Subtraction operations Bit Compare Call or Jump subroutine Available Long Pointer Long Indirect Indexed instructions Function CLR TNZ CPL, NEG SLA,SLL, SRL, SRA, RLC, RRC SWAP INC, DEC Clear Test Negative or Zero 1’s or 2’s Complement Shift and Rotate Operations Swap Nibbles Increment/Decrement Long Pointer Extended Indirect Indexed instructions only LDF Far load Function 36/148 PM0044 STM8 addressing modes 5.9 Short Pointer Indirect Long Indexed addressing mode The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 1 byte after the op-code. Example: 0089 0800 ptr dc.w table 0800 10203040 table dc.b $10,$20,$30,$40 0690 AE03 0692 92D689 LD X,#3 LD A,([shortptr.w],X) X=3 A = ([shortptr.w],X) = ((shortptr.w), X) = (($89.w), 3) = ($0800,3) = ($0803) = $40 37/148 STM8 addressing modes PM0044 Figure 16. Short Pointer Indirect Long Indexed addressing mode example Before completion ptr .word table 08 0089 00 008A LD A,([shortptr.w],X) 92 0692 D6 0693 89 0694 table .byte 10h,20h,30h,40h 10 800 20 801 30 802 40 803 PC 0692 X 03 A Previous value Steps to determine Effective Address PC = 0692 PC = PC + 2 = 0694 EA = ((PC)) : ((PC)+1) + X EA = 0803 800 03 Adder EA 0803 After completion ptr .word table 08 0089 00 008A LD A,([shortptr.w],X) 92 0692 D6 0693 89 0694 0695 X 03 New PC 0695 table .byte 10h,20h,30h,40h 10 0800 20 0801 30 0802 A 40 0803 40 Instruction Complete A = (EA) = 40 New PC = PC + 1 = 0695 38/148 PM0044 STM8 addressing modes 5.10 Long Pointer Indirect Long Indexed addressing mode The pointer address is a word, the pointer size is a word, thus allowing up to 128 KB addressing space, and requires 2 bytes after the op-code. Example: 1089 1800 ptr dc.w table 1800 10203040 table dc.b $10,$20,$30,$40 1690 AE03 1692 72D61089 LD X,#3 LD A,([longptr.w],X) X=3 A = ([longptr.w],X) = ((longptr.w), X) = (($1089.w), 3) = ($1800,3) = ($1803) = $40 39/148 STM8 addressing modes PM0044 Figure 17. Long Pointer Indirect Long Indexed addressing mode example Before completion ptr .word table 18 1089 00 108A LD A,([longptr.w],X) 72 1692 D6 1693 10 1694 89 1695 table .byte 10h,20h,30h,40h 10 20 30 40 1800 1801 1802 1803 PC 1692 X 03 A Previous value Steps to determine Effective Address PC = 1692 PC = PC + 2 = 1694 EA = (((PC) : (PC+1)) : ((PC) : (PC+1) +1)) + X EA = 1803 1800 03 Adder EA 1803 After completion ptr .word table 18 1089 00 108A X LD A,([longptr.w],X) 92 1692 03 D6 1693 10 1694 89 1695 1696 New PC 1696 Instruction Complete A = (EA) = 40 New PC = PC + 2 = 1696 table .byte 10h,20h,30h,40h 10 1800 20 1801 30 1802 A 40 1803 40 40/148 PM0044 STM8 addressing modes 5.11 Long Pointer Indirect Extended Indexed addressing mode The pointer address is a word, the pointer size is an extended word, thus allowing 16-Mbyte addressing space, and requires 2 bytes after the op-code. Example: 1089 180000 ptr dc.b page(table), high(table), low(table) 180000 10203040 table dc.b $10,$20,$30,$40 1690 AE03 1692 72A71089 LD X,#3 LDF A,([longptr.e],X) X=3 A = ([longptr.e],X) = ((longptr.e), X) = (($1089.e), 3) = ($180000,3) = ($180003) = $40 41/148 STM8 addressing modes PM0044 Figure 18. Long Pointer Indirect Extended Indexed addressing mode example Before completion 18 1089 ptr .word table 00 108A 00 LDF A,([longptr.w],X) 72 A7 10 89 table .byte 10h,20h,30h,40h 10 108B 1692 1693 1694 1695 180000 PC 1692 X 03 A Previous value Steps to Determine Effective Address PC = 1692 PC = PC + 2 = 1694 EA = (((PC) : (PC+1)) : ((PC) : (PC+1) +1) : ((PC) : (PC+1) +2)) + X EA = 180003 20 180001 30 180002 40 180003 180000 03 Adder EA 180003 After completion 18 1089 ptr .word table 00 108A 00 108B LDF A,([longptr.w],X) 72 1692 A7 1693 10 1694 89 1695 1696 Instruction Complete X A = (EA) = 40 New PC = PC + 2 = 1696 03 New PC 1696 table .byte 10h,20h,30h,40h 10 20 30 40 180000 180001 180002 180003 A VR02059I 40 42/148 PM0044 5.12 Relative Direct addressing mode STM8 addressing modes Addressing mode Direct Relative Syntax off EA formula PC = PC + off Ptr Adr Ptr Size Dest adr op + 1 --- PC +127/-128 This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. Available Relative Direct instructions JRxx JRA CALLR Function Conditional Jump Jump Relative Always Call Relative The offset follows the op-code. Example: 04A7 04A9 04AA 2717 9D 9D jreq nop nop skip 04C0 20FE skip jra* ; Infinite loop Action: if (Z == 1)thenPC = PC + $17 = $04A9 + $17 = $04C0 elsePC = PC= $04A9 43/148 STM8 addressing modes PM0044 Figure 19. Relative Direct addressing mode example JREQ SKIP JREQ SKIP SKIP : JREQ SKIP 27 17 27 17 27 17 04A7 04A8 04A9 04A7 04A8 04A9 Before completion CC Z PC 04A7 02 04A7 Adder 04A9 EA After completion (Branch taken) CC Z=1 PC 04A9 Steps to Determine Effective Address PC = 04A7 PC = PC + 1 = 04A8 TEMP = (PC) = 17 PC = PC +1 = 04A9 Stop here if there is no Branch; i.e., Z = 0 EA = PC + TEMP = 04A9 + 17 = 04C0 New PC = EA if Branch is taken Instruction Complete New PC = EA = 04C0 17 04A9 04C0 04C0 New PC Adder 04C0 EA After completion (No branch taken) CC Z=0 Instruction Complete 04A7 04A8 04A9 New PC 04A9 New PC = EA = 04A9 44/148 PM0044 5.13 Bit Direct (Long) addressing mode STM8 addressing modes Addressing mode Syntax EA formula Ptr Adr Ptr Size Dest adr Bit Long Direct longmem, #pos (longmem) op + 1..2 Word 0000..FFFF The data byte required for the operation is found by its memory address, which follows the op-code. The bit used for the operation is selected by the bit selector which is encoded in the instruction op-code. Available Bit Direct instructions BRES BSET BCPL BCCM Function Bit Reset Bit Set Bit Complement Copy Carry Bit to Memory The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes after the op-code. The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to by the address. Example: 0408 721006E5 BCPL coeff, #0 06E5 40 coeff dc.b $ 40 Action: (coeff) = ($06E5) XOR 2**0 = $40 XOR $01 = $41 45/148 STM8 addressing modes Figure 20. Bit Long Direct addressing mode example Before c ompletion PM0044 PC BCPL Coeff,#0 90 0408 0408 10 0409 06 040A 06E5 E5 040B 040C Coeff .byte 040h 40 06E5 EA 06E5 After c ompletion Steps to d etermine e ffective a ddress PC = 0408 PC = PC + 2 = 040A EA = (PC ) :(PC+1) = 06E5 EA = (PC ): (PC+1) = 06E5 BCPL Coeff,#0 90 0408 10 0409 06 040A E5 040B 040C Coeff .byte 040h 41 06E5 New PC 040C Instruction c omplete (EA) = (EA) | 2**0 = 40 | 01 = 41 New PC = PC + 2 = 040C 40 XOR 01 46/148 PM0044 STM8 addressing modes 5.14 Bit Direct (Long) Relative addressing mode Addressing mode Syntax EA formula Ptr Adr Ptr Size Dest adr Long (longmem) op + 1..2 Word 0000..FFFF Bit Relative longmem, #pos, off Direct PC = PC + off op + 3 Byte PC +127/-128 This addressing mode is a combination between the Bit Direct addressing mode (for data addressing) and Relative Direct mode (for PC computation). The data byte required for the operation is found by its memory address, which follows the op-code. The bit used for the test operation is selected by the bit selector which is encoded in the instruction op-code. Following the logical test operation, the PC register value can be modified, by adding an 8-bit signed offset to it. Available Bit Direct Relative instructions Function BTJT, BTJF Bit Test and Jump The data address is a word, thus allowing 0000 to FFFF addressing space (requires 2 bytes after the op-code). The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to by the address. The offset follows the op-code and data address. Example: 104B 00 DRA dc.b $00 ; Port A data register (input value) bit0 equ $0 ; data bit 0 04A7 7201104BFB wait_1 BTJF DRA, bit0, wait_1 04AC .... cont_0 Action: Test = select_bit(0, ($4B)) = select_bit(0, DRA) if (Test /= 1) then PC = PC + $FB = $0004AC - $05 = $0004A7 else PC = PC = $0004AC 47/148 STM8 addressing modes PM0044 Figure 21. Bit Long Direct Relative addressing mode example DRA .byte wait_1 BTJF DRA, #0, wait_1 wait_1 BTJF DRA, #0, wait_1 DRA b0 104B 104C 72 04A7 01 04A8 10 04A9 4B 04AA FB 04AB 72 04A7 01 04A8 10 04A9 4B 04AA FB 04AB DRA.b0 =? 0 PC 04A7 05 04A7 Adder 04AC EA After completion (Branch taken) (EA) b0 = 0 04A7 New PC PC 04AC Steps to Determine Effective Address PC = 04A7 PC = PC + 2 = 04A9 EA = (PC):(PC+1) = 104B Test = (EA).b0 PC = PC + 2 = 04AB TEMP = (PC) = FC PC = PC +1 = 04AC Stop here if there is no Branch; i.e., Test = TRUE (1) EA = PC + TEMP = 04AA + FD = 04A7 New PC = EA if Branch is taken Instruction Complete New PC = EA = 04A7 FB 04AC Adder wait_1 BTJF DRA, #0, wait_1 72 04A7 01 04A8 10 04A9 4B 04AA FB 04AB 04AC 04A7 After completion (No branch taken) (EA) b0 = 1 New PC 04AC EA Instruction Complete New PC = EA = 04AC 48/148 PM0044 6 STM8 instruction set STM8 instruction set 6.1 Introduction This chapter describes all the STM8 instructions. There are 96 and they are described in alphabetical order. However, they can be classified in 13 main groups as follows: Table 3. Instruction groups Load and Transfer LD LDF CLR MOV EXG LDW CLRW EXGW Stack operation PUSH POP PUSH W POPW Increment/ Decrement INC DEC INCW DECW Compare and Tests CP TNZ BCP CPW TNZW Logical operations AND OR XOR CPL CPLW Bit Operation BSET BRES BCPL BCCM Conditional Bit Test and Branch BTJT BTJF Arithmetic operations NEG ADC ADD SUB SBC MUL DIV DIVW NEGW ADDW SUBW Shift and Rotates SLL SRL SRA SWAP RLWA RRWA RLC RRC SWAP SLLW SRLW SRAW RLCW RRCW Unconditional Jump or Call JRA JRT JRF JP JPF CALL CALLR CALLF RET RETF NOP Conditional Branch/ Execution JRxx WFE Interrupt management TRAP WFI HALT IRET Condition Code Flag SIM RIM SCF RCF CCF RVF modification The instructions are described with one to five bytes. PC-1 End of previous instruction PC Op-code PC+1..4 Additional word (0 to 4) according to the number of bytes required to compute the effective address(es) 49/148 STM8 instruction set PM0044 Using a pre-code (two-byte op-codes) In order to extend the number of available op-codes for an 8-bit CPU (256 op-codes), four different pre-code bytes are defined. These pre-codes modify the meaning of the instruction they precede. The whole instruction becomes: PC-1 End of previous instruction PC Pre-code PC+1 Op-code PC+2 Additional word (0 to 3) according to the number of bytes required to compute the effective address These pre-bytes are: 90h = PDY Replaces an X based instruction using immediate, direct, indexed or inherent addressing mode by a Y one. It also provides read/modify/write instructions using Y indexed addressing mode with long offset and two bit handling instructions (BCPL and BCCM) 92h = PIX Replaces an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. 91h = PIY Replace an instruction using indirect X indexed addressing mode by a Y one. 72h = PWSP Provide long addressing mode for bit handling and read/modify/write instructions. It also provides indirect addressing mode with two byte pointer for read/modify/write and register/memory instructions. Finally it provides stack pointer indexed addressing mode on register/memory instructions. 50/148 PM0044 STM8 instruction set 6.2 6.2.1 6.2.2 6.2.3 6.2.4 Nomenclature Operators ← is loaded with ... ↔ has its value exchanged with ... CPU registers A X XL XH Y YL YH PC PCL PCH PCE SP CC CC.V CC.I0 CC.H CC.I1 CC.N CC.Z CC.C accumulator X index register (2 bytes) least significant byte of the X index register (1 byte) most significant byte of the X index register (1 byte) Y index register (2 bytes) least significant byte of the Y index register (1 byte) most significant byte of the Y index register (1 byte) program counter register (3 bytes) low significant byte of the program counter register (1 byte) high significant byte of the program counter register (1 byte) extended significant byte of the program counter register (1 byte) stack pointer register (2 bytes) Condition code register (1 byte) overflow flag of the code condition register (1 bit) interrupt mask bit 0 of the code condition register (1 bit) half carry flag of the code condition register (1 bit) interrupt mask bit 1 of the code condition register (1 bit) negative flag of the code condition register (1 bit) zero flag of the code condition register (1 bit) carry flag of the code condition register (1 bit) Code condition bit value notation - bit not affected by the instruction 1 bit forced to 1 by the instruction 0 bit forced to 0 by the instruction X bit modified by the instruction Memory and addressing M(...) R R(...) Rn XX.B content of a memory location 8-bit operation result value 8-bit operation result value stored into the register or memory shown inside parentheses bit n of the operation result value (0≤n≤7) bit B of the XX register or memory location imm.b byte immediate value imm.w 16-bit immediate value shortmem memory location with short addressing mode (1 byte) longmem memory location with long addressing mode (2 bytes) extmem memory location with extended addressing mode (3 bytes) shortoff longoff extoff short offset (1 byte) long offset (2 bytes) extended offset (3 bytes) [shortptr.w] short pointer (1 byte) on long memory location (2 bytes). Assembler notation = [$12.w]. [longptr.w] long pointer (2 bytes) on lo ng memory location (2 bytes). Assembler notation = [$1234.w] [longptr.e] long pointer (2 bytes) on extended memory location (3 bytes). Assembler notation = [$1234.e] 51/148 STM8 instruction set PM0044 6.2.5 Operation code notation ee extended order byte of 24-bit extended address ww high order byte of 16-bit long address or middle order byte of 24-bit extended address bb short address or low order byte of 16-bit long address or 24-bit extended address ii immediate data byte or low order byte of 16-bit immediate data iw high order byte of 16-bit immediate data rr relative offset byte in a range of [-128..+127] 6.3 Instruction set summary Table 4. Instruction set summary Effect on CC register Description Syntax example V I1 H I0 N Z C Operation Opcode(s) Cycles Pipe Mnemo ADC Add with carry - - ADC A,($12,SP) A ← A + M(SP+shortoff) + CC.C 19 bb 1 Set if R7 is set cleared otherwise Set if R=$00 cleared otherwise Set if there is a carry from R7 cleared otherwise cleared otherwise Set if there is a carry from bit 3 to 4 Set if there is a carry from bit 3 to 4 different from the carry bit C Set if the carry from R6 is Set if R7 is set cleared otherwise Set if R=$00 cleared otherwise Set if there is a carry from R7 cleared otherwise cleared otherwise different from the carry bit C Set if the carry from R6 is ADD Add without carry - - ADD A,($12,SP) A ← A + M(SP+shortoff) 1B bb 1 - - - - - - - ADD SP,#$12 SP ← SP + imm.b 5B ii 2 ADDW Add word without carry - - ADDW X,($12,SP) A ← A + M(SP+shortoff) 72 FB bb 2 Set if R15 is set cleared otherwise Set if R=$0000 cleared otherwise Set if there is a carry from R15 cleared otherwise Set if there is a carry from bit 7 to 8 cleared otherwise different from the carry bit C Set if the carry from R14 is Set if R7 is set cleared otherwise Set if R=$00 cleared otherwise AND Logical AND - --- - AND A,($12,SP) A ← A AND M(SP+shortoff) 14 bb 1 BCCM Copy carry in memory bit -- --- - - BCCM $1234,#1 M(longmem).bit ← CC.C 90 1n ww bb n=11 + 2*bit 1 52/148 PM0044 STM8 instruction set Cycles Pipe Mnemo Table 4. Instruction set summary (continued) Effect on CC register Description Syntax example V I1 H I0 N Z C Operation Opcode(s) Set if R7 is set cleared otherwise Set if R=$00 cleared otherwise BCP Logical bit compare --- test { A AND - BCP A,($12,SP) M(SP+shortoff) } N and Z are updated 15 bb 1 accordingly BCPL Complement bit in memory - - --- - - BCPL $1234,#1 M(longmem).bit ← M(longmem).bit 90 1n ww bb n=10 + 2*bit 1 BRES Bit reset - - - - - - - BRES $1234,#1 M(longmem).bit ← 0 72 1n ww bb n=11 + 2*bit 1 BSET Bit set - - - - - - - BSET $1234,#1 M(longmem).bit ← 1 72 1n ww bb n=10 + 2*bit 1 BTJF Bit test and relative jump if condition is false ----- - tested bit BTJF $1234,#1,label if M(longmem).bit=0 then PC ← PC + 4 + rr else PC ← PC + 4 72 0n ww bb n=01 + 2*bit 2/3 Flush Bit test and BTJT relative jump if ----- - condition is true tested bit BTJT $1234,#1,label if M(longmem).bit=1 then PC ← PC + 4 + rr else PC ← PC + 4 72 0n ww bb n=00 + 2*bit 2/3 Flush Call to CALL Subroutine with address in - - --- - - CALL [$1234.w] same section PC ← PC + 4 M(SP--) ← PCL M(SP--) ← PCH PCH ← M(longmem) PCL← M(longmem + 1) 72 CD ww bb 6 Flush Call to CALLF subroutine with extended - - --- - - CALLF $123456 address PC ← PC+4 M(SP--) ← PCL M(SP--) ← PCH M(SP--) ← PCE PC ← extmem 8D ee ww bb 5 Flush CALLR Call Subroutine relative - - --- - - CALLR label PC ← PC + 4 M(SP--) ← PCL M(SP--) ← PCH PC ← PC + rr 92 AD bb 4 Flush CCF Complement carry flag ----- - C CCF CC.C ← CC.C 8C 1 CLR Clears the destination byte - - - -0 1 - CLR ([$1234.w],X) M( M(longmem).w + X ) ← 00h 72 6F ww bb 4 Clears the CLRW destination - - - - 0 1 - CLRW X index register X ← 0000h 5F 1 CP Compare --- CP A,($12,SP) test { A - M(SP+shortoff) } 11 bb 1 Set if A-mem (signed values) overflows, cleared otherwise Set if R7 is set cleared otherwise Set if R=$00 cleared otherwise Set if A 0 Description Read the destination byte, test the corresponding bit (bit position), and jump to 'rel' label if the bit is true (1), else continue the program to the next instruction. The tested bit is saved in the C flag. The destination is a memory byte. The bit position is a constant. The jump label represents a signed offset to be added to the current PC/instruction address (relative jump). This instruction is used for boolean variable manipulation, hardware register flag tests, or I/O polling. Instruction overview Affected condition flags mnem dst bit position jump label V I1 H I0 N Z C BTJT Mem #pos rel - - - - - -C C⇒ Tested bit is saved in the C flag. Detailed description dst longmem pos = 0..7 n= 00+2.pos Asm BTJT $1000,#1,loop cy lgth Op-code(s) ST7 2/3 5 72 0n MS LS XX See also: BTJF 73/148 STM8 instruction set PM0044 CALL CALL Subroutine (Absolute) CALL Operation PC = PC+lgth (SP--) = PCL (SP--) = PCH PC = dst Description The current PC register value is pushed onto the stack, then PC is loaded with the destination address in same section of memory. The CALL destination and the instruction following the CALL should be in the same section as PCE is not stacked. The corresponding RET instruction should be executed in the same section. This instruction should be used versus CALLR when developing a program. Instruction overview mnem dst CALL Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst Asm cy lgth Op-code(s) ST7 longmem CALL $1000 4 3 CD MS LS ✗ (X) (shortoff,X) (longoff,X) (Y) CALL(X) CALL($10,X) CALL($1000,X) CALL(Y) 4 1 FD ✗ 4 2 ED XX ✗ 4 3 DD MS LS ✗ 4 2 90 FD ✗ (shortoff,Y) (longoff,Y) [shortptr.w] CALL($10,Y) CALL($1000,Y) CALL[$10.w] 4 3 90 ED XX ✗ 4 4 90 DD MS LS ✗ 6 3 92 CD XX ✗ [longptr.w] CALL[$1000.w] ([shortptr.w],X) CALL([$10.w],X) 6 4 72 CD MS LS 6 3 92 DD XX ✗ ([longptr.w],X) CALL([$1000.w],X) 6 4 72 DD MS LS ([shortptr.w],Y) CALL([$10.w],Y) 6 3 91 DD XX ✗ See also:RET, CALLR, CALLF 74/148 PM0044 STM8 instruction set CALLF CALL Far Subroutine CALLF Syntax CALLF dst e.g. CALLF label Operation PC = PC+lgth (SP--) = PCL (SP--) = PCH (SP--) = PCE PC = dst Description The current PC register value is pushed onto the stack, then PC is loaded with the destination address.This instruction is used with extended memory addresses. For safe memory usage, a function which crosses sections must be called by CALLF. Instruction overview mnem dst CALLF Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst extmem [longptr.e] Asm CALLF $35AA00 CALLF [$2FFC.e] cy lgth Op-code(s) ST7 5 4 8D ExtB MS LS 8 4 92 8D MS LS See also: RETF, CALL, JPF 75/148 STM8 instruction set PM0044 CALLR CALL Subroutine Relative CALLR Syntax CALLR dst e.g. CALLR chk_pol Operation PC = PC+lgth (SP--) = PCL (SP--) = PCH PC = PC + dst Description The current PC register value is pushed onto the stack, then PC is loaded with the relative destination addresss. This instruction is used, once a program is debugged, to shrink the overall program size. The CALLR destination and the corresponding RET instruction address must be in the same section, as PCE is not stacked. Instruction overview mnem dst CALLR Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst Asm cy lgth Op-code(s) ST7 shortmem CALLR $10 4 2 AD XX ✗ See also: CALL, RET 76/148 PM0044 STM8 instruction set CCF Complement Carry Flag Syntax CCF Operation CC.C <- CC.C Description Complements the Carry flag of the Condition Code (CC) register. Instruction overview CCF mnem CCF Affected condition flags V I1 H I0 N Z C - - - - - - C C =C , Complements the carry flag of the CC register. Detailed description Addressing mode Asm cy lgth Op-code(s) ST7 Inherent CCF 1 1 8C See also: RCF, SCF 77/148 STM8 instruction set PM0044 CLR Clear CLR Syntax CLR dst e.g. CLR A Operation dst <= 00 Description The destination byte is forced to 00 value. The destination is either a memory byte location or the accumulator. This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem dst CLR CLR Mem A N: 0 Cleared Z: 1 Set Detailed description Affected condition flags V I1 H I0 N Z C - - - - 0 1 - 0 1 dst Asm cy lgth Op-code(s) ST7 A CLR A 11 4F ✗ shortmem CLR$10 12 3F XX ✗ longmem CLR$1000 14 72 5F MS LS (X) CLR(X) 11 7F ✗ (shortoff.X) CLR($10,X) 12 6F XX ✗ (longoff,X) CLR($1000,X) 14 72 4F MS LS (Y) CLR(Y) 12 90 7F ✗ (shortoff,Y) CLR($10,Y) 13 90 6F XX ✗ (longoff,Y) CLR($1000,Y) 14 90 4F MS LS (shortoff,SP) CLR($10,SP) 12 0F XX [shortptr.w] CLR[$10] 43 92 3F XX ✗ [longptr.w] CLR[$1000].w 44 72 3F MS LS ([shortptr.w],X) CLR([$10],X) 43 92 6F XX ✗ ([longptr.w].X] CLR([$1000.w],X ) 4 4 72 6F MS LS ([shortptr.w],Y) CLR([$10],Y) 43 91 6F XX ✗ See also: LD 78/148 PM0044 STM8 instruction set CLRW Clear word CLRW Syntax CLRW dst e.g. CLRW X Operation dst <= 00 Description The destination is forced to 0000 value. The destination is an index register. Instruction overview mnem dst CLRW X CLRW Y N: 0 Cleared Z: 1 Set Detailed description Affected condition flags V I1 H I0 N Z C - - - - 0 1 - - - - - 0 1 - dst Asm cy lgth Op-code(s) ST7 X CLRW X 11 5F Y CLRW Y 12 90 5F See also: LD 79/148 STM8 instruction set PM0044 CP Compare CP Syntax CP dst,src e.g. CP A,(tbl,X) Operation {N, Z, C} = Test (dst - src) Description The source byte is subtracted from the destination byte and the result is lost. However, N, Z, C flags of Condition Code (CC) register are updated according to the result.The destination is a register, and the source is a memory or data byte. This instruction generally is used just before a conditional jump instruction. Instruction overview mnem dst CP Reg src Mem Affected condition flags V I1 H I0 N Z C V - - - N Z C V⇒ (A7.M7 + A7.R7 + A7.M7.R7) + (A6.M6 + A6.R6 + A6.M6.R6) Set if the signed subtraction of the destination (dst) value from the source (src) value generates a signed overflow (signed result cannot be represented on 8 bits). N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ (A7.M7 + A7.R7 + A7.M7.R7) Set if the unsigned value of the contents of source (src) is larger than the unsigned value of the destination (dst), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte A shortmem CP A,#$10 CP A,$10 1 2 1 2 A1 XX ✗ B1 XX ✗ A longmem A (X) A (shortoff,X) A (longoff,X) CP A,$1000 CP A,(X) CP A,($10,X) CP A,($1000,X) 1 3 1 1 1 2 1 3 C1 MS LS ✗ F1 ✗ E1 XX ✗ D1 MS LS ✗ A (Y) A (shortoff,Y) A (longoff,Y) CP A,(Y) CP A,($10,Y) CP A,($1000,Y) 1 2 90 F1 ✗ 1 3 90 E1 XX ✗ 1 4 90 D1 MS LS ✗ A (shortoff,SP) CP A,($10,SP) 1 2 11 XX A [shortptr.w] CP A,[$10.w] 4 3 92 C1 XX ✗ A [longptr.w] CP A,[$1000.w] 4 4 72 C1 MS LS A ([shortptr.w],X) CP A,([$10.w],X) 4 3 92 D1 XX ✗ A ([longptr.w],X) CP A,([$1000.w],X) 4 4 72 D1 MS LS A ([shortptr.w],Y) CP A,([$10.w],Y) 4 3 91 D1 XX ✗ See also: CPW, TNZ, BCP 80/148 PM0044 STM8 instruction set CPW Compare word CPW Syntax CPW dst,src e.g. CPW Y,(tbl,X) Operation {N, Z, C} = Test (dst - src) Description The source byte is subtracted from the destination byte and the result is lost. However, N, Z, C flags of Condition Code (CC) register are updated according to the result. The destination is an index register, and the source is a memory or data word. This instruction generally is used just before a conditional jump instruction. Instruction overview mnem dst CPW Reg src Mem Affected condition flags V I1 H I0 N Z C V - - - N Z C V⇒ (X15.M15 + X15.R15 + X15.M15.R15) + (X14.M14 + X14.R14 + X14.M14.R14) Set if the signed subtraction of the destination (dst) value from the source (src) value generates a signed overflow (signed result cannot be represented on 16 bits). N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ (X15.M15 + X15.R15 + X15.M15.R15) Set if the unsigned value of the contents of source (src) is larger than the unsigned value of the destination (dst), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X #word X shortmem CPW X,#$10 CPW X,$10 2 3 A3 MS LS ✗ 2 2 B3 XX ✗ X longmem CPW X,$1000 2 3 C3 MS LS ✗ X (Y) CPW X,(Y) 2 2 90 F3 ✗ X (shortoff,Y) CPW X,($10,Y) 2 3 90 E3 XX ✗ X (longoff,Y) CPW X,($1000,Y) 2 4 90 D3 MS LS ✗ X (shortoff,SP) CPW X,($10,SP) 2 2 13 XX X [shortptr.w] CPW X,[$10.w] 5 3 92 C3 XX ✗ X [longptr.w] CPW X,[$1000.w] 5 4 72 C3 MS LS X ([shortptr.w],Y) CPW X,([$10.w],Y) 5 3 91 D3 XX ✗ 81/148 STM8 instruction set PM0044 Note: CPW detailed description (Cont’d) dst src Asm cy lgth Op-code(s) ST7 Y #word Y shortmem Y longmem Y (X) CPW Y,#$10 CPW Y,$10 CPW Y,$1000 CPW Y,(X) 2 4 90 A3 MS LS ✗ 2 3 90 B3 XX ✗ 2 4 90 C3 MS LS ✗ 2 1 F3 ✗ Y (shortoff,X) CPW Y,($10,X) 2 2 E3 XX ✗ Y (longoff,X) CPW Y,($1000,X) 2 3 D3 MS LS ✗ Y [shortptr.w] CPW Y,[$10.w] 5 3 91 C3 XX ✗ Y ([shortptr.w],X) CPW Y,([$10.w],X) 5 3 92 D3 XX ✗ Y ([longptr.w],X) CPW Y,([$1000.w],X) 5 4 72 D3 MS LS CPW Y, (shortoff, SP) is not implemented, but can be emulated through a macro using EXGW X,Y & CPW X, (shortoff, SP) See also: CP, TNZW, BCP 82/148 PM0044 STM8 instruction set CPL Logical 1’s Complement CPL Syntax CPL dst e.g. CPL (X) Operation dst <= dst XOR FF, or FF - dst Description The destination byte is read, then each bit is toggled (inverted) and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C CPL Mem - - - - N Z 1 CPL Reg - - - - N Z 1 N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z ⇒R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ 1 Set. Detailed description dst Asm cy lgth Op-code(s) ST7 A CPL A 11 43 ✗ shortmem CPL$10 12 33 XX ✗ longmem CPL$1000 14 72 53 MS LS (X) CPL(X) 11 73 ✗ (shortoff.X) CPL($10,X) 12 63 XX ✗ (longoff,X) CPL($1000,X) 14 72 43 MS LS (Y) CPL(Y) 12 90 73 ✗ (shortoff,Y) CPL($10,Y) 13 90 63 XX ✗ (longoff,Y) CPL($1000,Y) 14 90 43 MS LS (shortoff,SP) CPL($10,SP) 12 03 XX ✗ [shortptr.w] CPL[$10] 43 92 33 XX ✗ [longptr.w] CPL[$1000].w 44 72 33 MS LS ([shortptr.w],X) CPL([$10],X) 43 92 63 XX ✗ ([longptr.w].X] CPL([$1000.w],X) 4 4 72 63 MS LS ([shortptr.w],Y) CPL([$10],Y) 43 91 63 XX ✗ See also: NEG, XOR, AND, OR 83/148 STM8 instruction set PM0044 CPLW Logical 1’s Complement Word CPLW Syntax CPLW dst e.g. CPLW X Operation dst <= dst XOR FFFF, or FFFF - dst Description The destination index register is read, then each bit is toggled (inverted) and the result is written back to the destination index register. Instruction overview mnem CPLW Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z 1 N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ 1 Set Detailed description dst Asm cy lgth Op-code(s) ST7 X CPLW X 21 53 ✗ Y CPWL Y 22 90 53 ✗ See also: CPL, NEGW, XOR, AND, OR 84/148 PM0044 STM8 instruction set DEC Decrement DEC Syntax DEC dst Operation dst <= dst - 1 Description The destination byte is read, then decremented by one, and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C DEC DEC Mem Reg V - - - N Z - V - - - N Z - V⇒ (A7.M7 + M7.R7 + R7.A7) + (A6.M6 + M6.R6 + R6.A6) Set if the signed operation generates an overflow, cleared otherwise. N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst Asm cy lgth Op-code(s) ST7 A shortmem DEC A DEC $10 1 1 1 2 4A ✗ 3A XX ✗ longmem (X) DEC $1000 DEC(X) 1 4 72 5A MS LS 1 1 7A ✗ (shortoff.X) DEC($10,X) 1 2 6A XX ✗ (longoff,X) (Y) (shortoff,Y) DEC($1000,X) DEC(Y) DEC($10,Y) 1 4 72 4A MS LS 1 2 90 7A ✗ 1 3 90 6A XX ✗ (longoff,Y) DEC($1000,Y) 1 4 90 4A MS LS (shortoff,SP) DEC($10,SP) 1 2 0A XX [shortptr.w] DEC[$10] 4 3 92 3A XX ✗ [longptr.w] DEC[$1000].w ([shortptr.w],X) DEC([$10],X) 4 4 72 3A MS LS 4 3 92 6A XX ✗ ([longptr.w].X] DEC([$1000.w],X) 4 4 72 6A MS LS ([shortptr.w],Y) DEC([$10],Y) 4 3 91 6A XX ✗ See also: DECW, INC 85/148 STM8 instruction set PM0044 DECW Decrement word DECW Syntax DECW dst Operation dst <= dst - 1 Description The value of the destination index register is decremented by one. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C DECW Reg V - - - N Z - V⇒ (A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14) Set if the signed operation generates an overflow, cleared otherwise. N⇒ R15 Set if bit 15 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst Asm X DECW X Y DECW Y cy lgth Op-code(s) ST7 2 1 5A 2 2 90 5A See also: INCW, DEC 86/148 PM0044 STM8 instruction set Note: DIV Divide (unsigned) DIV Syntax DIV dst,A e.g. DIV X,A Operation dst <= dst / A (Quotient) A <= dst%A (Remainder) Description Divides a 16-bit unsigned value, dividend, contained in an index register (X or Y) by an 8-bit value, divisor, contained in A. The quotient is placed in the same index register and the remainder is placed in A. The register values are unchanged in the case of a division by zero. Note: This instruction is interruptible, generating a latency of 1 cycle only. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C DIV X DIV Y A 0 - 0 - 0 ZC A 0 - 0 - 0 ZC V⇒ 0 Reset. H⇒ 0 Reset. N⇒ 0 Reset. Z⇒ Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0 Set if the quotient is zero (0000h), cleared otherwise. C⇒ A7.A6.A5.A4.A3.A2.A1.A0 Set if division by 0, cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X A DIV X,A 2 to 17 1 62 Y A DIV Y,A 2 to 17 2 90 62 See also: DIVW, ADD, ADC, SUB, SBC, MUL 87/148 STM8 instruction set PM0044 Note: DIVW Divide word (unsigned) DIVW Operation X <= X / Y (Quotient) Y <= X%Y (Remainder) Description Divides a 16-bit unsigned value, dividend, contained in X register by a 16-bit value, divisor, contained in Y. The quotient is placed in the X register and the remainder is placed in Y register. The quotient and remainder values are indeterminate in the case of a division by zero. This instruction is interruptible, generating a latency of 1 cycle only. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C DIV X Y 0 - 0 - 0 ZC V⇒ 0 Reset H⇒ 0 Reset N⇒ 0 Reset Z⇒ Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0 Set if the quotient is zero (0000h), cleared otherwise. C⇒ Y15.Y14.Y13.Y12.Y11.Y10.Y9.Y8.Y7.Y6.Y5.Y4.Y3.Y2.Y1.Y0 Set if division by 0, cleared otherwise. Detailed description dst src X Y Asm DIV X,Y cy lgth 2 to 17 1 Op-code(s) ST7 65 See also: ADD, ADC, SUB, SBC, MUL, DIV 88/148 PM0044 STM8 instruction set EXG Exchange register contents EXG Syntax EXG dst, src e.g. EXG A, XL Operation dst <=> src dst<= src src <= dst Description Exchanges the contents of registers specified in the instruction as shown below. Instruction overview mnem dst EXG A EXG A EXG A Detailed description src XL YL Mem Affected condition flags V I1 H I0 N Z C - - - - - - - - - - - - - - - - - - - - - dst src Asm A XL EXG A,XL A YL EXG A,YL A longmem EXG A,$1000 cy lgth 11 11 33 Op-code(s) ST7 41 61 31 MS LS See also: EXGW, LD 89/148 STM8 instruction set PM0044 EXGW Exchange Index register contents EXGW Syntax EXG dst, src e.g. EXGW X, Y Operation dst <=> src src <= dst dst<= src Description Exchanges the contents of registers specified in the instruction as shown below. Instruction overview mnem dst EXGW X Detailed description Affected condition flags src V I1 H I0 N Z C Y - - - - - - - dst src Asm cy lgth Op-code(s) ST7 X Y EXGW X,Y 11 51 See also: EXG, LDW 90/148 PM0044 STM8 instruction set HALT HALT Oscillator (CPU + Peripherals) HALT Syntax HALT Operation I1 = 1, I0 = 0, The oscillator is stopped till an interrupt occurs. Description The interrupt mask is reset, allowing interrupts to be fetched. Then the oscillator is stopped thus stopping the CPU and all internal peripherals, reducing the microcontroller to its lowest possible power consumption. The microcontroller resumes program execution after an external interrupt or reset, by restarting the oscillator, and then, fetching the corresponding external interrupt, which is generally an I/O interrupt, or the reset vector. Instruction overview mnem HALT Affected condition flags V I1 H I0 N Z C - 1 - 0 - - - I1: 1 Set. I0: 0 Cleared. Detailed description Addressing mode Inherent Asm HALT cy lgth Op-code(s) ST7 10 1 8E ✗ See also: WFI 91/148 STM8 instruction set PM0044 INC Increment INC Syntax INC dst e.g. INC counter Operation dst <= dst + 1 Description The destination byte is read, then incremented by one, and the result is written to the destination byte. The destination is either a memory byte or a register. This instruction is compact, and does not affect any registers when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C INC Mem V - - - N Z - INC A V - - - N Z - V⇒ (A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6) Set if the signed operation generates an overflow, cleared otherwise. N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst Asm cy lgth Op-code(s) ST7 A INC A 1 1 4C ✗ shortmem INC$10 1 2 3C XX ✗ longmem INC$1000 1 4 72 5C MS LS (X) INC(X) 1 1 7C ✗ (shortoff.X) INC($10,X) 1 2 6C XX ✗ (longoff,X) INC($1000,X) 1 4 72 4C MS LS (Y) INC(Y) 1 2 90 7C ✗ (shortoff,Y) INC($10,Y) 1 3 90 6C XX ✗ (longoff,Y) INC($1000,Y) 1 4 90 4C MS LS (shortoff,SP) INC($10,SP) 1 2 0C XX [shortptr.w] INC[$10] 4 3 92 3C XX ✗ [longptr.w] INC[$1000].w 4 4 72 3C MS LS ([shortptr.w],X) INC([$10],X) 4 3 92 6C XX ✗ ([longptr.w].X] INC([$1000.w],X) 4 4 72 6C MS LS ([shortptr.w],Y) INC([$10],Y) 4 3 91 6C XX ✗ See also: INCW, DEC 92/148 PM0044 STM8 instruction set INCW Increment word Syntax INCW dst e.g. INCW X Operation dst <= dst + 1 Description The destination index register value is incremented by one. Instruction overview INCW mnem Affected condition flags dst V I1 H I0 N Z C INCW Reg V - - - N Z - V⇒ (A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14) Set if the signed operation generates an overflow, cleared otherwise. N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst Asm cy lgth Op-code(s) ST7 X INCW X 2 1 5C Y INCW Y 2 2 90 5C See also: INC, DECW 93/148 STM8 instruction set PM0044 IRET Interrupt Return IRET Syntax IRET Operation CC = (++SP) A = (++SP) XH = (++SP) XL = (++SP) YH = (++SP) YL = (++SP) PCE = (++SP) PCH = (++SP) PCL = (++SP) Description Placed at the end of an interrupt routine, returns to the original program context before the interrupt occurred. All registers, which have been saved/pushed onto the stack are restored/popped. The I bit will be reset if the corresponding bit stored on the stack is zero. Instruction overview mnem IRET Affected condition flags V I1 H I0 N Z C V I1 H I0 N Z C Condition flags set or reset according to the first byte pulled from the stack. Detailed description Addressing mode Inherent Asm IRET cy lgth Op-code(s) ST7 11 1 80 ✗ See also: Interrupts, TRAP 94/148 PM0044 STM8 instruction set JP Jump (absolute) JP Syntax JP dst e.g. JP test Operation PC <= dst Description The unconditional jump, simply replaces the content of PC by destination address in same section of memory. Control then passes to the statement addressed by the program counter. This instruction should be used instead of JRA during S/W development. Instruction overview mnem dst JP Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst Asm longmem JP $1000 (X) JP(X) (shortoff,X) JP($10,X) (longoff,X) JP($1000,X) (Y) JP(Y) (shortoff,Y) JP($10,Y) (longoff,Y) JP($1000,Y) [shortptr.w] JP[$10.w] [longptr.w] JP[$1000.w] ([shortptr.w],X) JP([$10.w],X) ([longptr.w],X) JP([$1000.w],X) ([shortptr.w],Y) JP([$10.w],Y) cy lgth Op-code(s) ST7 2 3 2 1 2 2 CC MS LS ✗ FC ✗ EC XX ✗ 2 3 DC MS LS ✗ 2 2 90 FC ✗ 2 3 90 EC XX ✗ 2 4 90 DC MS LS ✗ 5 3 92 CC XX ✗ 5 4 72 CC MS LS 5 3 92 DC XX ✗ 5 4 72 DC MS LS 5 3 91 DC XX ✗ See also: JRA 95/148 STM8 instruction set PM0044 JPF Jump far JPF Syntax JPF dst e.g.:JPF test Operation PC <= dst Description The unconditional jump simply replaces the content of the PC by a destination with an extended address. Control then passes to the statement addressed by the program counter. For safe memory usage, this instruction must be used, when the operation crosses a memory section. Instruction overview mnem dst JPF Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst Asm extmem JPF $2FFFFC [longptr.e] JPF [$2FFC.e] cy lgth 2 4 6 4 Op-code(s) ST7 AC ExtB MS LS 92 AC MS LS See also: JP, CALLF 96/148 PM0044 STM8 instruction set JRA Jump Relative Always JRA Syntax JRA dst e.g. JRA loop Operation PC = PC+lgth PC <= PC + dst Description Unconditional relative jump. PC is updated by the signed addition of PC and dst. Control then passes to the statement addressed by the program counter. This instruction may be used, once the software is debugged, to speed up and shrink a program. Instruction overview mnem dst JRA Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - dst Asm cy lgth Op-code(s) ST7 shortoff JRA $2B 2 2 20 XX ✗ See also: JP 97/148 STM8 instruction set PM0044 JRxx Conditional Jump Relative Instruction JRxx Syntax JRxx dst e.g. JRxx loop Operation PC = PC+lgth PC <= PC + dst, if Condition is True Description Conditional relative jump. PC is updated by the signed addition of PC and dst, if the condition is true. Control, then passes to the statement addressed by the program counter. Else, the program continues normally. Instruction overview mnem dst JRxx Instruction List Mem mnem JRC JREQ JRF JRH JRIH JRIL JRM JRMI JRNC JRNE JRNH JRNM JRNV JRPL JRSGE JRSGT JRSLE JRSLT JRT JRUGE JRUGT JRULE JRULT JRV meaning Carry Equal False Half-Carry Interrupt Line is High Interrupt Line is Low Interrupt Mask Minus Not Carry Not Equal Not Half-Carry Not Interrupt Mask Not Overflow Plus Signed Greater or Equal Signed Greater Than Signed Lower or Equal Signed Lower Than True Unsigned Greater or Equal Unsigned Greater Than Unsigned Lower or Equal Unsigned Lower Than Overflow Affected condition flags V I1 H I0 N Z C - - - - - - - sym = Condition C=1 Z=1 False H=1 <0 <> 0 >= 0 >= > <= < >= > <= < I=1 N=1 C=0 Z=0 H=0 I=0 V=0 N=0 (N XOR V) = 0 (Z OR (N XOR V)) = 0 (Z OR (N XOR V)) = 1 (N XOR V) = 1 True C=0 C = 0 and Z = 0 C = 1 or Z = 1 C=1 V=1 Op-code (OC) 25 27 21 90 29 90 2F 90 2E 90 2D 2B 24 26 90 28 90 2C 28 2A 2E 2C 2D 2F 20 24 22 23 25 29 Detailed description dst Asm cy lgth Op-code(s) ST7 shortoff JRxx $15 1/2 2 Op-code XX ✗ shortoff JRxx $15 1/2 3 90 Op-code XX ✗ 98/148 PM0044 STM8 instruction set LD Load LD Syntax LD dst,src e.g. LD A,#$15 Operation dst <= src Description Load the destination byte with the source byte. The dst and src can be a register, a byte (low/high) of an index register or a memory/data byte. When half of an index register is loaded, the other half remains unchanged. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C LD Reg LD Mem LD Reg Mem Reg Reg - - - - NZ - - - - - NZ - - - - - - - - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z ⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte A shortmem A longmem LD A,#$55 LD A,$50 LD A,$5000 1 2 A6 XX ✗ 1 2 B6 XX ✗ 1 3 C6 MS LS ✗ A (X) LD A,(X) 1 1 F6 ✗ A (shortoff,X) LD A,($50,X) 1 2 E6 XX ✗ A (longoff,X) LD A,($5000,X) 1 3 D6 MS LS ✗ A (Y) LD A,(Y) 1 2 90 F6 ✗ A (shortoff,Y) LD A,($50,Y) 1 3 90 E6 XX ✗ A (longoff,Y) LD A,($5000,Y) 1 4 90 D6 MS LS ✗ A (shortoff,SP) LD A,($50,SP) 1 2 7B XX A [shortptr.w] LD A,[$50.w] 4 3 92 C6 XX ✗ A [longptr.w] LD A,[$5000.w] 4 4 72 C6 MS LS A ([shortptr.w],X) LD A,([$50.w],X) 4 3 92 D6 XX ✗ A ([longptr.w],X) LD A,([$5000.w],X) 4 4 72 D6 MS LS A ([shortptr.w],Y) LD A,([$50.w],Y) 4 3 91 D6 XX ✗ 99/148 STM8 instruction set PM0044 LD detailed description (Cont’d) dst src Asm cy lgth Op-code(s) ST7 shortmem A LD $50,A 1 2 B7 XX ✗ longmem A LD $5000,A 1 3 C7 MS LS ✗ (X) A LD (X),A 1 1 F7 ✗ (shortoff,X) A LD ($50,X),A 1 2 E7 XX ✗ (longoff,X) A LD ($5000,X),A 1 3 D7 MS LS ✗ (Y) A LD (Y),A 1 2 90 F7 ✗ (shortoff,Y) A LD ($50,Y),A 1 3 90 E7 XX ✗ (longoff,Y) A LD ($5000,Y),A 1 4 90 D7 MS LS ✗ (shortoff,SP) A LD ($50,SP),A 1 2 6B XX [shortptr.w] A LD [$50.w],A 4 3 92 C7 XX ✗ [longptr.w] A LD [$5000.w],A 4 4 72 C7 MS LS ([shortptr.w], X) A LD ([$50.w],X),A 4 3 92 D7 XX ✗ ([longptr.w],X) A LD ([$5000.w],X),A 4 4 72 D7 MS LS ([shortptr.w], Y) A LD ([$50.w],Y),A 4 3 91 D7 XX ✗ dst src XL A A XL YL A A YL XH A A XH YH A A YH LD XL,A LD A,XL LD YL,A LD A,YL LD XH,A LD A,XH LD YH,A LD A,YH See also: LDW, LDF, CLR cy lgth Op-code(s) ST7 1 1 97 ✗ 1 1 9F ✗ 1 2 90 97 ✗ 1 2 90 9F ✗ 1 1 95 1 1 9E 1 2 90 95 1 2 90 9E 100/148 PM0044 STM8 instruction set LDF Load Far LDF Syntax LDF dst,src e.g. LDF A,($555555,X) Operation dst <= src Description Load the destination byte with the source byte. The dst and src can be a memory location or accumulator register. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C LDF A LDF Mem Mem A - - - - NZ - - - - - NZ - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A extmem LDF A, $500000 1 4 BC ExtB MS LS A (extoff,X) LDF A,($500000,X) 1 4 AF ExtB MS LS A (extoff,Y) LDF A,($500000,Y) 1 5 90 AF ExtB MS LS A ([longptr.e],X) LDF A,([$5000.e],X) 5 4 92 AF MS LS A ([longptr.e],Y) LDF A,([$5000.e],Y) 5 4 91 AF MS LS A [longptr.e] LDF A,[$5000.e] 5 4 92 BC MS LS dst src Asm cy lgth Op-code(s) ST7 extmem A LDF $500000,A 1 4 BD ExtB MS LS (extoff,X) A LDF ($500000,X),A 1 4 A7 ExtB MS LS (extoff,Y) A LDF ($500000,Y),A 1 5 90 A7 ExtB MS LS ([longptr.e],X) A LDF ([$5000.e],X),A 4 4 92 A7 MS LS ([longptr.e],Y) A LDF ([$5000.e],Y),A 4 4 91 A7 MS LS [longptr.e] A LDF [$5000.e],A 4 4 92 BD MS LS See also: LD, CALLF 101/148 STM8 instruction set PM0044 LDW Load word LDW Syntax LDW dst,src e.g. LDW X,#$1500 Operation dst <= src Description Load the destination word (16-bit value) with the source word. The dst and src can be a 16-bit register (X, Y or SP) or a memory/data 16-bit value. Instruction overview mnem LD LD LD LD LD dst Reg Mem Reg SP Reg src Mem Reg Reg Reg SP Affected condition flags V I1 H I0 N Z C - - - - NZ - - - - - NZ - - - - - - - - - - - - - - - - - - - - - - N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X #word X shortmem X longmem X (X) LDW X,#$55AA LDW X,$50 LDW X,$5000 LDW X,(X) 2 3 2 2 2 3 2 1 AE MS LS ✗ BE XX ✗ CE MS LS ✗ FE ✗ X (shortoff,X) LDW X,($50,X) 2 2 X (longoff,X) LDW X,($5000,X) 2 3 EE XX ✗ DE MS LS ✗ X (shortoff,SP) LDW X,($50,SP) 2 2 1E XX X [shortptr.w] LDW X,[$50.w] 5 3 92 CE XX ✗ X [longptr.w] LDW X,[$5000.w] 5 4 72 CE MS LS X ([shortptr.w],X) LDW X,([$50.w],X) 5 3 92 DE XX ✗ X ([longptr.w],X) LDW X,([$5000.w],X) 5 4 72 DE MS LS dst shortmem longmem (X) (shortoff,X) (longoff,X) src Asm X LDW $50,X X LDW $5000,X Y LDW (X),Y Y LDW ($50,X),Y Y LDW ($5000,X),Y cy lgth 22 23 21 22 23 Op-code(s) ST7 BF XX ✗ CF MS LS ✗ FF EF XX DF MS LS 102/148 PM0044 STM8 instruction set Note: LDW detailed description (Cont’d) dst src Asm cy lgth Op-code(s) ST7 (shortoff,SP) X LDW ($50,SP),X 22 1F [shortptr.w] X LDW [$50.w],X 53 92 CF XX ✗ [longptr.w] X LDW [$5000.w],X 54 72 CF MS LS ([shortptr.w],X) Y LDW ([$50.w],X),Y 53 92 DF XX ✗ ([longptr.w],X) Y LDW ([$5000.w],X),Y 54 72 DF MS LS dst src Asm cy lgth Op-code(s) ST7 Y #word LDW Y,#$55AA 2 4 90 AE MS LS ✗ Y shortmem LDW Y,$50 2 3 90 BE XX ✗ Y longmem LDW Y,$5000 2 4 90 CE MS LS ✗ Y (Y) LDW Y,(Y) 2 2 90 FE ✗ Y (shortoff,Y) LDW Y,($50,Y) 2 3 90 EE XX ✗ Y (longoff,Y) LDW Y,($5000,Y) 2 4 90 DE MS LS ✗ Y (shortoff,SP) LDW Y,($50,SP) 2 2 16 XX Y [shortptr.w] LDW Y,[$50.w] 5 3 91 CE XX ✗ Y ([shortptr.w],Y) LDW Y,([$50.w],Y) 5 3 91 DE XX ✗ dst src Asm cy lgth Op-code(s) ST7 shortmem Y LDW $50,Y 23 90 BF XX ✗ longmem Y LDW $5000,Y 24 90 CF MS LS ✗ (Y) X LDW (Y),X 22 90 FF ✗ (shortoff,Y) X LDW ($50,Y),X 23 90 EF XX ✗ (longoff,Y) X LDW ($5000,Y),X 24 90 DF MS LS ✗ (shortoff,SP) Y LDW ($50,SP),Y 22 17 XX [shortptr.w] Y LDW [$50.w],Y 53 91 CF XX ✗ ([shortptr.w],Y) X LDW ([$50.w],Y),X 5 3 91 DF XX ✗ dst src cy lgth Op-code(s) ST7 Y X LDW Y,X 1 2 90 93 ✗ X Y LDW X,Y 1 1 93 ✗ X SP LDW X,SP 1 1 96 ✗ SP X LDW SP,X 1 1 94 ✗ Y SP LDW Y,SP 1 2 90 96 ✗ SP Y LDW SP,Y 1 2 90 94 ✗ LDW Y,[longptr.w] and LDW [longptr.w],Y are not implemented. They can be emulated using EXGW X,Y. See also: LD, CLRW 103/148 STM8 instruction set PM0044 MOV Move MOV Syntax MOV dst,src e.g. MOV $80,#$AA Operation dst<= src Description Moves a byte of data from a source address to a destination address. Data is examined as it is moved. The accumulator is not affected. There are 3 addressing modes for the MOV instruction: ● An immediate byte to a direct memory location ● A direct memory location to another direct memory location (from $00 to $FF) ● A direct memory location to another direct memory location (from $1000 to $FFFF) Instruction overview mnem dst MOV MOV Mem Mem Detailed description src Imm Mem Affected condition flags V I1 H I0 N Z C - - - - - - - - - - - - - - dst src Asm longmem #byte MOV $8000, #$AA shortmem shortmem MOV $80,$10 longmem longmem MOV $8000,$1000 cy lgth 14 13 15 Op-code(s) ST7 35 XX MS LS 45 XX2 XX1 55 MS2 LS2 MS1 LS1 See also: LD, EXG 104/148 PM0044 STM8 instruction set MUL Multiply (unsigned) MUL Syntax MUL dst,src e.g. MUL X,A Operation dst:src <= dst x src Description Multiplies the 8-bit value in index register, low byte, (XL or YL) by the 8-bit value in the accumulator to obtain a 16-bit unsigned result in the index register. After the operation, index register contains the 16-bit result. The accumulator remains unchanged. The initial value of the high byte of the index register (XH or YH) is ignored. Instruction overview mnem dst MUL X MUL Y C: 0 Cleared. src XL,A YL,A Affected condition flags V I1 H I0 N Z C - - 0 - - - 0 - - 0 - - - 0 Detailed description dst src Asm cy lgth Op-code(s) ST7 X A MUL X,A 41 42 Y A MUL Y,A 42 90 42 See also: ADD, ADC, SUB, SBC 105/148 STM8 instruction set PM0044 NEG Negate (Logical 2’s complement) NEG Syntax NEG dst e.g. NEG (X) Operation dst <= (dst XOR FF) + 1, or 00 - dst Description The destination byte is read, then each bit is toggled (inverted), and the result is incremented before it is written at the destination byte. The destination is either a memory byte or a register. The Carry is cleared if the result is zero. This instruction is used to negate signed values. This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C NEG NEG Mem A V - - - N Z C V - - - N Z C V⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if there is an arithmetic overflow on the 8-bit representation of the result. The V bit will set when the content of "dst" was $80 (-128) prior to the NEG operation, cleared otherwise. N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ R7+R6+R5+R4+R3+R2+R1+R0 Set if a borrow in the implied subtraction from zero, cleared otherwise. The C bit will be set in all cases except when the contents of "dst" was $00 prior to the NEG operation. Detailed description dst Asm cy lgth Op-code(s) ST7 A NEG A 11 40 ✗ shortmem NEG $F5 12 30 XX ✗ longmem NEG $F5C2 14 72 50 MS LS (X) NEG(X) 11 70 ✗ (shortoff,X) NEG($F5,X) 12 60 XX ✗ (longoff,X) NEG($F5C2,X) 14 72 40 MS LS (Y) NEG(Y) 12 90 70 ✗ (shortoff,Y) NEG($F5,Y) 13 90 60 XX ✗ (longoff,Y) NEG($F5C2,Y) 14 90 40 MS LS (shortoff,SP) NEG($F5,SP) 12 00 XX [shortptr.w] NEG($F5) 43 92 30 XX ✗ 106/148 PM0044 STM8 instruction set NEG detailed description (Cont’d) dst Asm cy lgth Op-code(s) ST7 [longptr.w] NEG($F5C2.w) 44 72 30 MS LS ([shortptr.w],X) NEG([$F5],X) 43 92 60 XX ✗ ([longptr.w],X) NEG([$F5C2.w],X) 4 4 72 60 MS LS ([shortptr.w],Y) NEG([$F5],Y) 43 91 60 XX ✗ See also: NEGW, CPL, AND, OR, XOR 107/148 STM8 instruction set PM0044 NEGW Negate word (Logical 2’s Complement) NEGW Syntax NEGW dst e.g. NEGW X Operation dst <= (dst XOR FFFF) + 1, or 0000 - dst Description The destination word is read, then each bit is toggled (inverted), and the result is incremented before it is written at the destination word. The destination is an index register. Instruction overview. mnem Affected condition flags dst V I1 H I0 N Z C NEGW NEGW X V - - - N Z C Y V - - - N Z C V⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if there is an arithmetic overflow on the 16-bit representation. The V bit will set when the content of "dst" was $8000 prior to the NEGW operation, cleared otherwise. N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ R15+R14+R13+R12+R11+R10+R9+R8+R7+R6+R5+R4+R3+R2+R1+R0 Set if a borrow in the implied subtraction from zero, cleared otherwise. The C bit will be set in all cases except when the contents of "dst" was $0000 prior to the NEGW operation. Detailed description dst Asm cy lgth Op-code(s) ST7 X NEGW X 21 50 Y NEGW Y 22 90 50 See also: NEG, CPLW, AND, OR, XOR 108/148 PM0044 STM8 instruction set NOP No operation NOP Syntax NOP Operation Description This is a single byte instruction that does nothing. This instruction can be used either to disable an instruction, or to build a waiting delay.No register or memory contents are affected by this instruction Instruction overview mnem Affected condition flags V I1 H I0 N Z C NOP - - - - - - - Detailed description Addressing mode Inherent Asm NOP cy lgth Op-code(s) ST7 1 1 9D ✗ See also: JRF 109/148 STM8 instruction set PM0044 OR Syntax Operation Description Truth table Logical OR OR OR A,src e.g. OR A,#%00110101 A <= A OR src The source byte, is logically ORed with the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte. OR 0 1 0 0 1 1 1 1 Instruction overview mnem dst OR A src Mem Affected condition flags V I1 H I0 N Z C - - - - NZ - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte A shortmem A longmem A (X) OR A,#$55 OR A,$10 OR A,$1000 OR A,(X) 1 2 1 2 1 3 1 1 AA XX ✗ BA XX ✗ CA MS LS ✗ FA ✗ A (shortoff,X) OR A,($10,X) 1 2 EA XX ✗ A (longoff,X) OR A,($1000,X) 1 3 DA MS LS ✗ A (Y) OR A,(Y) 1 2 90 FA ✗ A (shortoff,Y) OR A,($10,Y) 1 3 90 EA XX ✗ A (longoff,Y) OR A,($1000,Y) 1 4 90 DA MS LS ✗ A (shortoff,SP) OR A,($10,SP) 1 2 1A XX A [shortptr.w] OR A,[$10.w] 4 3 92 CA XX ✗ A [longptr.w] OR A,[$1000.w] 4 4 72 CA MS LS A ([shortptr.w],X) OR A,([$10.w],X) 4 3 92 DA XX ✗ A ([longptr.w],X) OR A,([$1000.w],X) 4 4 72 DA MS LS A ([shortptr.w],Y) OR A,([$1000],Y) 4 3 91 DA XX ✗ See also: AND, XOR, CPL, NEG 110/148 PM0044 STM8 instruction set POP Pop from stack POP Syntax POP dst e.g. POP CC Operation dst <= (++SP) Description Restore from the stack a data byte which will be placed in dst location. The stack pointer is incremented by one. This instruction is used to restore a register/memory value. Instruction overview mnem POP POP POP dst A CC Mem Affected condition flags V I1 H I0 N Z C - - - - - - - V I1 H I0 N Z C - - - - - - - Detailed description dst A CC longmem Asm POP A POP CC POP $1000 See also: PUSH, POPW cy lgth 1 1 1 1 1 3 Op-code(s) ST7 84 ✗ 86 ✗ 32 MS LS 111/148 STM8 instruction set PM0044 POPW Pop word from stack POPW Syntax POPW dst e.g. POPW X Operation Description dstH <= (++SP) dstL <= (++SP) Restore from the stack a data value which will be placed in dst location (index register). The stack pointer is incremented by two. This instruction is used to restore an index register value. Instruction overview mnem dst POPW X POPW Y Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - - - - - - - - dst Asm cy lgth Op-code(s) ST7 X POPW X 2 1 85 ✗ Y POPW Y 2 2 90 85 ✗ See also: PUSHW, POP 112/148 PM0044 STM8 instruction set PUSH Push into the Stack PUSH Syntax PUSH src e.g.:PUSH A Operation (SP--) <= dst Description Save into the stack the dst byte location. The stack pointer is decremented by one. Used to save a register value and a memory byte on to the stack. Instruction overview mnem dst PUSH A PUSH CC PUSH PUSH Imm Mem Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - - - - - - - - - - - - - - - - - - - - - - dst Asm cy lgth Op-code(s) ST7 A PUSH A 1 1 88 ✗ CC PUSH CC 1 1 8A ✗ #byte PUSH #$10 1 2 4B XX longmem PUSH $1000 1 3 3B MS LS See also: POP, PUSHW 113/148 STM8 instruction set PM0044 PUSHW Push word onto the Stack PUSHW Syntax PUSHW src e.g. PUSHW X Operation Description (SP--) <= dstL (SP--) <= dstH Save the dst index register onto the stack. The stack pointer is decremented by two. Used to save an index register value onto the stack. Instruction overview mnem dst PUSHW X PUSHW Y Detailed description Affected condition flags V I1 H I0 N Z C - - - - - - - - - - - - - - dst Asm cy lgth Op-code(s) ST7 X PUSHW X 2 1 89 ✗ Y PUSHW Y 2 2 90 89 ✗ See also: POPW, PUSH 114/148 PM0044 STM8 instruction set RCF Reset Carry Flag RCF Syntax RCF Operation C=0 Description Clear the carry flag of the Condition Code (CC) register. May be used as a boolean user controlled flags. Instruction overview mnem RCF Affected condition flags V I1 H I0 N Z C - - - - - - 0 C: 0 Cleared. Detailed description Addressing mode Inherent Asm RCF cy lgth Op-code(s) ST7 1 1 98 ✗ See also: SCF, RVF 115/148 STM8 instruction set PM0044 RET Return from subroutine RET Syntax RET Operation MSB (PC) = (++SP) LSB (PC) = (++SP) Description Restore the PC from the stack. The stack pointer is incremented twice. This instruction, is the last instruction of a subroutine in same section. Instruction overview mnem Affected condition flags V I1 H I0 N Z C RET - - - - - - - Detailed description Addressing mode Inherent Asm RET cy lgth Op-code(s) ST7 4 1 81 ✗ Note: See also: CALL, CALLR Please note that the RET should be in the same section as the corresponding CALL. 116/148 PM0044 STM8 instruction set RETF Far Return from subroutine RETF Syntax RETF Operation PCE = (++SP) PCH = (++SP) PCL = (++SP) Description Restore the PC from the stack then restore the Condition Code (CC) register. The stack pointer is incremented three times. This instruction is the last one of a subroutine in extended memory. Instruction overview mnem Affected condition flags V I1 H I0 N Z C RETF - - - - - - - Detailed description Addressing mode Inherent Asm RETF cy lgth Op-code(s) ST7 5 1 87 See also: CALLF 117/148 STM8 instruction set PM0044 RIM Reset Interrupt Mask/Enable Interrupt RIM Syntax RIM Operation I1 = 1, I0 = 0 Description Clear the Interrupt mask of the Condition Code (CC) register, which enable interrupts. This instruction is generally put in the main program, after the reset routine, once all desired interrupts have been properly configured. This instruction is not needed before WFI and HALT instructions. Instruction overview mnem Affected condition flags V I1 H I0 N Z C RIM - 1 - 0 - - - I1: 1 Set. I0: 0 Cleared. Detailed description Addressing mode Inherent Asm RIM cy lgth Op-code(s) ST7 1 1 9A ✗ See also: SIM 118/148 PM0044 STM8 instruction set RLC Rotate Left Logical through Carry RLC Syntax RLC dst e.g. RLC (X) Operation Description The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables.This instruction shifts all bits of the register or memory, one place to the left, through the Carry bit. Bit 0 of the result is a copy of the CC.C value before the operation. Instruction overview mnem RLC RLC N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg Mem - - - - N Z bit7 - - - - N Z bit7 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b7 Set if, before the shift, the MSB of register or memory was set, cleared otherwise. C b7 Detailed description dst A shortmem longmem (X) (shortoff,X) (longoff,X) (Y) (shortoff,Y) (longoff,Y) (shortoff,SP) [shortptr.w] [longptr.w] ([shortptr.w],X) ([longptr.w],X) ([shortptr.w],Y) Asm RLC A RLC $10 RLC $1000 RLC (X) RLC ($10,X) RLC ($1000,X) RLC (Y) RLC ($10,Y) RLC ($1000,Y) RLC ($10,SP) RLC [$10] RLC [$1000].w RLC ([$10],X) RLC ([$1000.w],X) RLC ([$10],Y) cy lgth 1 1 1 2 1 4 1 1 1 2 1 4 1 2 1 3 1 4 1 2 4 3 4 4 4 3 4 4 4 3 Op-code(s) 49 39 XX 72 59 MS LS 79 69 XX 72 49 MS LS 90 79 90 69 XX 90 49 MS LS 09 XX 92 39 XX 72 39 MS LS 92 69 XX 72 69 MS LS 91 69 XX See also: RLCW, RRC, SLL, SRL, SRA, ADC, SWAP, SLA b0 ST7 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ 119/148 STM8 instruction set PM0044 RLCW Rotate Word Left Logical through Carry RLCW Syntax RLCW dst e.g. RLCW X Operation Description The destination is an index register. This instruction shifts all bits of the register one place to the left through Carry bit. Bit 0 of the result is a copy of CC.C value before the operation. Instruction overview mnem RLCW N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z bit15 R15 Set if bit 7 of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b15 Set if, before the shift, the MSB of register or memory was set, cleared otherwise. C b15 b0 Detailed description dst Asm cy lgth Op-code(s) ST7 X RLCW X 2 1 59 ✗ Y RLCW Y 2 2 90 59 ✗ See also: RLC, RRCW, SLLW, SRLW, SRAW, SWAPW, SLAW 120/148 PM0044 STM8 instruction set RLWA Rotate Word Left through A RLWA Syntax RLWA dst e.g. RLWA Y,A Operation Description A <= dstH <= dstL <= A The destination index register and Accumulator are rotated left by 1-byte. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C RLWA X RLWA Y A - - - - NZ - A - - - - NZ - N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X A RLWA X,A 11 02 Y A RLWA Y,A 12 90 02 See also: RRWA, SWAPW 121/148 STM8 instruction set PM0044 RRC Rotate Right Logical through Carry RRC Syntax RRC dst e.g. RRC (X) Operation Description The destination is either a memory byte location or a register. This instruction is compact, and does not affect any register when used with RAM variables.This instruction shifts all bits of the register or memory, one place to the right. Bit 7 of the result is a copy of the CC.C bit value before the operation. Instruction overview mnem RRC RRC N⇒ Z⇒ C⇒ dst Reg Mem Affected condition flags V I1 H I0 N Z C - - - - N Z bit0 - - - - N Z bit0 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b0 Set if, before the shift, the LSB of register or memory was set, cleared otherwise. C b7 b0 Detailed description dst Asm cy lgth Op-code(s) ST7 A RRC A 1 1 46 ✗ shortmem RRC $10 1 2 36 XX ✗ longmem RRC $1000 1 4 72 56 MS LS (X) RRC (X) 1 1 76 ✗ (shortoff,X) RRC ($10,X) 1 2 66 XX ✗ (longoff,X) RRC ($1000,X) 1 4 72 46 MS LS (Y) RRC (Y) 1 2 90 76 ✗ (shortoff,Y) RRC ($10,Y) 1 3 90 66 XX ✗ (longoff,Y) RRC ($1000,Y) 1 4 90 46 MS LS (shortoff,SP) RRC ($10,SP) 1 2 06 XX ✗ [shortptr.w] RRC [$10] 4 3 92 36 XX ✗ [longptr.w] RRC [$1000].w 4 4 72 36 MS LS ([shortptr.w],X) RRC ([$10],X) 4 3 92 66 XX ✗ ([longptr.w],X) RRC ([$1000.w],X) 4 4 72 66 MS LS ([shortptr.w],Y) RRC ([$10],Y) 4 3 91 66 XX ✗ See also: RLC, SRL, SLL, SRA, SWAP, ADC, SLA 122/148 PM0044 STM8 instruction set RRCW Rotate Word Right Logical through Carry RRCW Syntax RRCW dst e.g. RRCWX Operation Description The destination is an index register. This instruction shifts all bits of the register or memory, one place to the right, through the Carry bit. Bit 15 of the result is a copy of the CC.C bit value before the operation. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C RRCW Reg - - - - N Z bit0 N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ b0 Set if, before the shift, the MSB of register or memory was set, cleared otherwise. C b15 b0 Detailed description dst Asm cy lgth Op-code(s) ST7 X RRCW X 2 1 56 ✗ Y RRCW Y 2 2 90 56 ✗ See also: RRC, RLCW, SRLW, SLLW, SRAW, SWAPW, SLAW 123/148 STM8 instruction set PM0044 RRWA Rotate Right Word through A RRWA Syntax RRWA dst e.g. RRWA Y,A Operation Description A => dstH => dstL => A The destination index register and Accumulator are rotated right by 1-byte. Instruction overview mnem RLWA RLWA N⇒ Z⇒ Affected condition flags dst src V I1 H I0 N Z C X A - - - - NZ - Y A - - - - NZ - R15 Set if bit 7 of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X A RRWA X,A 11 01 Y A RRWA Y,A 12 90 01 See also: RLWA, SWAPW 124/148 PM0044 STM8 instruction set RVF Reset overflow flag RVF Syntax RVF Operation V=0 Description Clear the overflow flag of the Condition Code (CC) register. May be used as a boolean user controlled flags. Instruction overview mnem RCF Affected condition flags V I1 H I0 N Z C 0 - - - - - - V: 0 Cleared. Detailed description Addressing mode Inherent Asm RVF cy lgth Op-code(s) ST7 1 1 9C ✗ See also: RCF, SCF 125/148 STM8 instruction set PM0044 SBC Subtraction with Carry SBC Syntax SBC A,src e.g. SBC A,#$15 Operation A <= A- src - C Description The source byte, along with the carry flag, is subtracted from the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C SBC A Mem V - - - NZC V⇒ (A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6) Set if the signed subtraction generates an overflow, cleared otherwise. N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ A7.M7 + A7.R7 + A7.M7.R7 Set if a carry occurred from bit 7of the result, cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte SBC A,#$55 A shortmem SBC A,$10 A longmem SBC A,$1000 1 2 1 2 1 3 A2 XX ✗ B2 XX ✗ C2 MS LS ✗ A (X) SBC A,(X) 1 1 F2 ✗ A (shortoff,X) SBC A,($10,X) 1 2 E2 XX ✗ A (longoff,X) SBC A,($1000,X) 1 3 D2 MS LS ✗ A (Y) SBC A,(Y) 1 2 90 F2 ✗ A (shortoff,Y) SBC A,($10,Y) 1 3 90 E2 XX ✗ A (longoff,Y) SBC A,($1000,Y) 1 4 90 D2 MS LS ✗ A (shortoff,SP) SBC A,($10,SP) 1 2 12 XX A [shortptr.w] SBC A,[$10.w] 4 3 92 C2 XX ✗ A [longptr.w] SBC A,[$1000.w] 4 4 72 C2 MS LS A ([shortptr.w],X) SBC A,([$10.w],X) 4 3 92 D2 XX ✗ A ([longptr.w],X) SBC A,([$1000.w],X) 4 4 72 D2 MS LS A ([shortptr.w],Y) SBC A,([$10.w],Y) 4 3 91 D2 XX ✗ See also: ADD,ADC,SUB, MUL 126/148 PM0044 STM8 instruction set SCF Set Carry Flag SCF Syntax SCF Operation C=1 Description Set the carry flag of the Condition Code (CC) register. It may be used as user controlled flag. Instruction overview mnem SCF Instruction overview mnem V I1 SCF - - C: 1 Set. Detailed description Addressing mode Inherent Asm SCF Affected condition flags H I0 N Z - - - - cy lgth 1 1 Op-code(s) 99 C 1 ST7 ✗ See also: RCF, RVF 127/148 STM8 instruction set PM0044 SIM Set Interrupt Mask/Disable Interrupt SIM Syntax sim Operation I1 = 1, I0 = 1 Description Set the Interrupt mask of the Condition Code (CC) register, which disables interrupts. This instruction is useless at the beginning of reset routine. It need not be used at the beginning of interrupt routines as the interrupt level is set automatically in CC.I[1:0]. Instruction overview mnem Affected condition flags V I1 H I0 N Z C SIM - 1 - 1 - - - I1 and I0: 1 Set. Detailed description Addressing mode Inherent Asm SIM cy lgth Op-code(s) ST7 1 1 9B ✗ See also: RIM 128/148 PM0044 STM8 instruction set SLA Shift Left Arithmetic SLA Syntax SLA dst e.g. SLA (X) Operation Description The destination is either a memory byte or a register.This instruction is equivalent to SLL one. Instruction overview mnem SLA SLA N⇒ Z⇒ C ⇒ b7 dst Mem Reg Affected condition flags V I1 H I0 N Z C - - - - N Z bit7 - - - - N Z bit7 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Set if, before the shift, bit 7 of register or memory was set, cleared otherwise C b7 b0 0 Detailed description dst Asm cy lgth Op-code(s) ST7 A SLA A 11 48 ✗ shortmem SLA $15 12 38 XX ✗ longmem SLA $1505 14 72 58 MS LS (X) SLA (X) 11 78 ✗ (shortoff,X) SLA ($15,X) 12 68 XX ✗ (longoff,X) SLA ($1505,X) 14 72 48 MS LS (Y) SLA (Y) 12 90 78 ✗ (shortoff,Y) SLA ($15,Y) 13 90 68 XX ✗ (longoff,Y) SLA ($1505,Y) 14 90 48 MS LS (shortoff,SP) SLA ($15,SP) 12 08 XX ✗ [shortptr.w] SLA [$15] 43 92 38 XX ✗ [longptr.w] SLA [$1505].w 44 72 38 MS LS ([shortptr.w],X) SLA ([$15],X) 43 92 68 XX ✗ ([longptr.w],X) SLA ([$1505.w],X) 4 4 72 68 MS LS ([shortptr.w],Y) SLA ([$15],Y) 43 91 68 XX ✗ See also: SRL, SRA, RRC, RLC, SWAP, SLL 129/148 STM8 instruction set PM0044 SLAW Shift Left Arithmetic Word SLAW Syntax SLAW dst e.g. SLAW X Operation Description The destination is an index register. This instruction is equivalent to the SLLW one. Instruction overview mnem SLAW N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z bit15 R15 Set if bit 15 of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b15 Set if, before the shift, bit 15 of register or memory was set, cleared otherwise. C b15 b0 0 Detailed description dst Asm cy lgth Op-code(s) ST7 X SLAW X 21 58 Y SLAW Y 22 90 58 See also: SLA, SRLW, SRAW, RRCW, RLCW, SWAPW, SLLW 130/148 PM0044 STM8 instruction set SLL Shift Left Logical SLL Syntax SLL dst e.g. SLL (X) Operation Description The destination is either a memory byte or a register.It double the affected value. This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem SLL SLL N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Mem Reg - - - - N Z bit7 - - - - N Z bit7 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b7 Set if, before the shift, bit 7 of register or memory was set, cleared otherwise. C b7 b0 0 Detailed description dst A shortmem longmem (X) (shortoff,X) (longoff,X) (Y) (shortoff,Y) (longoff,Y) (shortoff,SP) [shortptr.w] [longptr.w] ([shortptr.w],X) ([longptr.w],X) ([shortptr.w],Y) Asm SLL A SLL $15 SLL $1505 SLL (X) SLL ($15,X) SLL ($1505,X) SLL (Y) SLL ($15,Y) SLL ($1505,Y) SLL ($15,SP) SLL [$15] SLL [$1505].w SLL ([$15],X) SLL ([$1505.w],X) SLL ([$15],Y) cy lgth 1 1 1 2 1 4 1 1 1 2 1 4 1 2 1 3 1 4 1 2 4 3 4 4 4 3 4 4 4 3 See also: SLA, SRA, SRL, RRC, RLC, SWAP Op-code(s) 48 38 XX 72 58 MS LS 78 68 XX 72 48 MS LS 90 78 90 68 XX 90 48 MS LS 08 XX 92 38 XX 72 38 MS LS 92 68 XX 72 68 MS LS 91 68 XX ST7 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ 131/148 STM8 instruction set PM0044 SLLW Shift Left Logical Word SLLW Syntax SLLW dst e.g. SLLW X Operation Description The destination is an index register.It double the affected value. Instruction overview mnem SLLW N⇒ Z⇒ C ⇒ b15 Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z bit15 R15 Set if bit 15of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Set if, before the shift, bit 15 of register or memory was set, cleared otherwise. C b15 b0 0 Detailed description dst X Y Asm cy lgth Op-code(s) ST7 SLLW X SLLW Y 2 1 2 2 58 90 58 See also: SLL, SRAW, SRLW, RRCW, RLCW, SWAPW, SLAW 132/148 PM0044 STM8 instruction set SRA Shift Right Arithmetic SRA Syntax SRA dst e.g. SRA (X) Operation Description The destination is either a memory byte or a register. It performs an signed division by 2: The sign bit 7 is not modified.This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem SRA SRA N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg Mem - - - - N Z bit0 - - - - N Z bit0 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b0 Set if, before the shift, the LSB of register or memory was set, cleared otherwise. b7 b7 b0 C Detailed description dst A shortmem longmem (X) (shortoff,X) (longoff,X) (Y) (shortoff,Y) (longoff,Y) (shortoff,SP) [shortptr.w] [longptr.w] ([shortptr.w],X) ([longptr.w],X) ([shortptr.w],Y) Asm SRA A SRA $15 SRA $1505 SRA (X) SRA ($15,X) SRA ($1505,X) SRA (Y) SRA ($15,Y) SRA ($1505,Y) SRA ($15,SP) SRA [$15] SRA [$1505].w SRA ([$15],X) SRA ([$1505.w],X) SRA ([$15],Y) cy lgth 1 1 1 2 1 4 1 1 1 2 1 4 1 2 1 3 1 4 1 2 4 3 4 4 4 3 4 4 4 3 See also: SRAW, SRL, SLL, RRC, RLC, SWAP Op-code(s) 47 37 XX 72 57 MS LS 77 67 XX 72 47 MS LS 90 77 90 67 XX 90 47 MS LS 07 XX 92 37 XX 72 37 MS LS 92 67 XX 72 67 MS LS 91 67 XX ST7 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ 133/148 STM8 instruction set PM0044 SRAW Shift Right Arithmetic Word SRAW Syntax SRAW dst e.g. SRAW X Operation Description The destination is an index register. It performs a signed division by 2. The sign bit (15) is not modified. Instruction overview mnem SRAW N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z bit0 R15 Set if bit 7 of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. b0 Set if, before the shift, the LSB of register or memory was set, cleared otherwise. b15 b15 b0 C Detailed description dst Asm cy lgth Op-code(s) ST7 X SRAW X 2 1 57 Y SRAW Y 2 2 90 57 See also: SRA, SRLW, SLLW, RRCW, RLCW, SWAPW 134/148 PM0044 STM8 instruction set SRL Shift Right Logical SRL Syntax SRL dst e.g. SRL (X) Operation Description The destination is either a memory byte or a register.It perform an unsigned division by 2.This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem SRL SRL N⇒ Z⇒ C ⇒ b0 Affected condition flags dst V I1 H I0 N Z C Reg Mem - - - - N Z bit0 - - - - N Z bit0 R7 Set if bit 7 of the result is set (negative value), cleared otherwise. R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Set if, before the shift, the LSB of register or memory was set, cleared otherwise. 0 b7 b0 C Detailed description dst A shortmem longmem (X) (shortoff,X) (longoff,X) (Y) (shortoff,Y) (longoff,Y) (shortoff,SP) [shortptr.w] [longptr.w] ([shortptr.w],X) ([longptr.w],X) ([shortptr.w],Y) Asm SRL A SRL $15 SRL $1505 SRL (X) SRLL ($15,X) SRL ($1505,X) SRL (Y) SRL ($15,Y) SRL ($1505,Y) SRL ($15,SP) SRL [$15] SRL [$1505].w SRL ([$15],X) SRL ([$1505.w],X) SRL ([$15],Y) cy lgth 1 1 1 2 1 4 1 1 1 2 1 4 1 2 1 3 1 4 1 2 4 3 4 4 4 3 4 4 4 3 See also: RLC, RRC, SRA, SWAP, SLL, SRLW Op-code(s) 44 34 XX 72 54 MS LS 74 64 XX 72 44 MS LS 90 74 90 64 XX 90 44 MS LS 04 XX 92 34 XX 72 34 MS LS 92 64 XX 72 64 MS LS 91 64 XX ST7 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ 135/148 STM8 instruction set PM0044 SRLW Shift Right Logical Word SRLW Syntax SRLW dst e.g. SRLW X Operation Description The destination is an index register. It performs an unsigned division by 2. Instruction overview mnem SRLW N⇒ Z⇒ C⇒ Affected condition flags dst V I1 H I0 N Z C Reg - - - - N Z bit0 R15 Set if bit 7 of the result is set (negative value), cleared otherwise. R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. b0 Set if, before the shift, the LSB of the register was set, cleared otherwise. 0 b15 b0 C Detailed description dst Asm cy lgth Op-code(s) ST7 X SRLW X 2 1 54 Y SRLW Y 2 2 90 54 See also: SRL, RLCW, RRCW, SRLW, SRAW, SWAPW, SLLW 136/148 PM0044 STM8 instruction set SUB Subtraction SUB Syntax SUB A,src e.g. SUB A,#%11001010 Operation A <= A- src Description The source byte is subtracted from the contents of the accumulator/SP and the result is stored in the accumulator/SP. The source is a memory or data byte. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C SUB A SUB SP Mem Imm V - - - N Z C - - - - - - - V⇒ (A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6) Set if the signed operation generates an overflow, cleared otherwise. N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ A7.M7 + A7.R7 + A7.M7.R7 Set if a carry occurred from bit 7, cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte SUB A,#$55 1 2 A0 XX ✗ A shortmem SUB A,$10 1 2 B0 XX ✗ A longmem SUB A,$1000 1 3 C0 MS LS ✗ A (X) SUB A,(X) 1 1 F0 ✗ A (shortoff,X) SUB A,($10,X) 1 2 E0 XX ✗ A (longoff,X) SUB A,($1000,X) 1 3 D0 MS LS ✗ A (Y) SUB A,(Y) 1 2 90 F0 ✗ A (shortoff,Y) SUB A,($10,Y) 1 3 90 E0 XX ✗ A (longoff,Y) SUB A,($1000,Y) 1 4 90 D0 MS LS ✗ A (shortoff,SP) SUB A,($10,SP) 1 2 10 XX A [shortptr.w] SUB A,[$10.w] 4 3 92 C0 XX ✗ A [longptr.w] SUB A,[$1000.w] 4 4 72 C0 MS LS A ([shortptr.w],X) SUB A,([$10.w],X) 4 3 92 D0 XX ✗ A ([longptr.w],X) SUB A,([$1000.w],X) 4 4 72 D0 MS LS A ([shortptr.w],Y) SUB A,([$10.w],Y) 4 3 91 D0 XX ✗ SP #byte SUB SP,#$9 2 2 52 XX See also: SUBW, ADD, ADC, SBC, MUL 137/148 STM8 instruction set PM0044 SUBW Word Subtraction SUBW Syntax SUBW dst,src e.g. SUBW X, #$5500 Operation dst <= dst - src Description The source 16-bit word is subtracted from the contents of the destination index register and the result is stored in the same index register. The source is a memory or 16-bit data. Instruction overview mnem dst Affected condition flags src V I1 H I0 N Z C SUBW X SUBW Y Mem Mem V - H - NZ C V - H - NZ C V⇒ (X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 + X14.M14.R14) Set if the signed operation generates an overflow, cleared otherwise. H⇒ X7.M7 + X7.R7 + X7.M7.R7 Set if a carry occurred from bit 7, cleared otherwise. N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. C⇒ X15.M15 + X15.R15 + X15.M15.R15 Set if a carry occurred from bit 15, cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 X #word SUBW X,#$5500 2 3 1D MS LS X longmem SUBW X,$1000 2 4 72 B0 MS LS X (shortoff, SP) SUBW X,($10,SP) 2 3 72 F0 XX Y #word SUBW Y,#$5500 2 4 72 A2 MS LS Y longmem SUBW Y,$1000 2 4 72 B2 MS LS Y (shortoff, SP) SUBW Y,($10,SP) 2 3 72 F2 XX See also: SUB, ADDW, ADC, SBC, MUL 138/148 PM0044 STM8 instruction set SWAP Swap nibbles SWAP Syntax SWAP dst e.g. SWAP counter Operation Description The destination byte upper and low nibbles are swapped over. The destination is either a memory byte or a register. This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C SWAP SWAP Reg Mem - - - - N Z - - - - - N Z - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst Asm cy lgth Op-code(s) ST7 A SWAP A 1 1 4E ✗ shortmem SWAP $15 1 2 3E XX ✗ longmem (X) SWAP $1505 1 4 72 5E MS LS SWAP (X) 1 1 7E ✗ (shortoff,X) SWAPL ($15,X) 1 2 6E XX ✗ (longoff,X) SWAP ($1505,X) 1 4 72 4E MS LS (Y) SWAP (Y) 1 2 90 7E ✗ (shortoff,Y) SWAP ($15,Y) 1 3 90 6E XX ✗ (longoff,Y) SWAP ($1505,Y) 1 4 90 4E MS LS (shortoff,SP) SWAP ($15,SP) 1 2 0E XX ✗ [shortptr.w] SWAP [$15] 4 3 92 3E XX ✗ [longptr.w] SWAP [$1505].w 4 4 72 3E MS LS ([shortptr.w],X) SWAP ([$15],X) 4 3 92 6E XX ✗ ([longptr.w],X) SWAP ([$1505.w],X) 4 4 72 6E MS LS ([shortptr.w],Y) SWAP ([$15],Y) 4 3 91 6E XX ✗ See also: SWAPW, RRC, RLC, SLL, SRL, SRA 139/148 STM8 instruction set PM0044 SWAPW Swap bytes SWAPW Syntax SWAPW dst e.g. SWAPW Y Operation Description The destination index register upper and low bytes are swapped over. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C SWAP Reg - - - - N Z - N⇒ R15 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst X Y Asm cy lgth Op-code(s) ST7 SWAPW X 1 1 5E ✗ SWAPW Y 1 2 90 5E ✗ See also: SWAP, RRC, RLC, SLL, SRL, SRA 140/148 PM0044 STM8 instruction set TNZ Test for Negative or Zero TNZ Syntax TNZ dst e.g. TNZ A Operation {N, Z} = Test(dst) Description The destination byte is tested and both N and Z flags of the Condition Code (CC) register are updated accordingly. This instruction is compact, and does not affect any register when used with RAM variables. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C TNZ Reg - - - - N Z - TNZ Mem - - - - N Z - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst Asm cy lgth Op-code(s) ST7 A TNZ A 1 1 4D ✗ shortmem TNZ $15 1 2 3D XX ✗ longmem (X) TNZ $1505 1 4 72 5D MS LS TNZ (X) 1 1 7D ✗ (shortoff,X) TNZL ($15,X) 1 2 6D XX ✗ (longoff,X) TNZ ($1505,X) 1 4 72 4D MS LS (Y) TNZ (Y) 1 2 90 7D ✗ (shortoff,Y) TNZ ($15,Y) 1 3 90 6D XX ✗ (longoff,Y) TNZ ($1505,Y) 1 4 90 4D MS LS (shortoff,SP) TNZ ($15,SP) 1 2 0D XX ✗ [shortptr.w] TNZ [$15] 4 3 92 3D XX ✗ [longptr.w] TNZ [$1505].w 4 4 72 3D MS LS ([shortptr.w],X) TNZ ([$15],X) 4 3 92 6D XX ✗ ([longptr.w],X) TNZ ([$1505.w],X) 4 4 72 6D MS LS ([shortptr.w],Y) TNZ ([$15],Y) 4 3 91 6D XX ✗ See also: TNZW, CP, BCP 141/148 STM8 instruction set PM0044 TNZW Word Test for Negative or Zero TNZW Syntax TNZW dst e.g. TNZW X Operation {N, Z} = Test(dst) Description The destination 16-bit word, index register, is tested and both N and Z flags of the Condition Code (CC) register are updated accordingly. Instruction overview mnem Affected condition flags dst V I1 H I0 N Z C TNZW Reg - - - - N Z - N⇒ R15 Set if bit 15 of the result is set (negative value), cleared otherwise. Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (0000h), cleared otherwise. Detailed description dst X Y Asm cy lgth Op-code(s) ST7 TNZW X TNZW Y 2 1 2 2 5D 90 5D See also: TNZ, CPW 142/148 PM0044 STM8 instruction set TRAP Syntax Operation Software interrupt TRAP PC = PC + 1 (SP--) = LSB (PC) (SP--) = MSB (PC) (SP--) = Ext(PC) (SP--) = YL (SP--) = YH (SP--) = XL (SP--) = XH (SP--) = A (SP--) = CC PC = TRAP Interrupt Vector Contents TRAP Description When processed, this instruction forces the trap interrupt to occur and to be processed. It cannot be masked by the I0 or I1 flags. Instruction overview mnem TRAP Affected condition flags V I1 H I0 N Z C - 1 - 1 - - - I1 and I0: 1 Set. Detailed description Addressing mode Inherent Asm TRAP cy lgth Op-code(s) ST7 9 1 83 ✗ See also: IRET 143/148 STM8 instruction set PM0044 WFE Wait for Event (CPU stopped, low power mode) WFE Syntax WFE Operation The CPU Clock is stopped till an external event occurs. Internal peripherals are still running. It is used for synchronization with other computing resources (e.g coprocessor). Description The state of the CPU is frozen, waiting for synchronization with an external event. The CPU clock also is stopped, reducing the power consumption of the microcontroller. Interrupt requests during this period are served normally, depending on the CC.I[1:0] value. Instruction overview mnem Affected condition flags V I1 H I0 N Z C WFE - - - - - - - Detailed description Addressing mode Inherent Asm WFE cy lgth Op-code(s) ST7 1 2 72 8F See also: HALT 144/148 PM0044 STM8 instruction set WFI Wait for Interrupt (CPU stopped, low power mode) WFI Syntax WFI Operation CC.I1= 1, CC.I0 = 0. The CPU Clock is stopped till an interrupt occurs. Internal peripherals are still running. Description The interrupt flag is cleared, allowing interrupts to be fetched. Then the CPU clock is stopped, reducing the power consumption of the microcontroller. The micro will continue the program upon an internal or external interrupt. Instruction overview mnem WFI Affected condition flags V I1 H I0 N Z C - 1 - 0 - - - I1: 1 Set. I0: 0 Cleared. Detailed description Addressing mode Inherent Asm WFI cy lgth Op-code(s) ST7 10 1 8F ✗ See also: HALT 145/148 STM8 instruction set PM0044 XOR Syntax Operation Description Truth table Logical Exclusive OR XOR XOR A,src e.g. XOR A,#%00110101 A <= A XOR src The source byte, is logically XORed with the contents of the accumulator and the result is stored in the accumulator. The source is a memory or data byte. XOR 0 1 0 0 1 1 1 0 Instruction overview mnem dst XOR A src Mem Affected condition flags V I1 H I0 N Z C - - - - NZ - N⇒ R7 Set if bit 7 of the result is set (negative value), cleared otherwise. Z⇒ R7.R6.R5.R4.R3.R2.R1.R0 Set if the result is zero (00h), cleared otherwise. Detailed description dst src Asm cy lgth Op-code(s) ST7 A #byte A shortmem A longmem A (X) XOR A,#$55 XOR A,$10 XOR A,$1000 XOR A,(X) 1 2 1 2 1 3 1 1 A8 XX ✗ B8 XX ✗ C8 MS LS ✗ F8 ✗ A (shortoff,X) XOR A,($10,X) 1 2 E8 XX ✗ A (longoff,X) XOR A,($1000,X) 1 3 D8 MS LS ✗ A (Y) XOR A,(Y) 1 2 90 F8 ✗ A (shortoff,Y) XOR A,($10,Y) 1 3 90 E8 XX ✗ A (longoff,Y) XOR A,($1000,Y) 1 4 90 D8 MS LS ✗ A (shortoff,SP) XOR A,($10,SP) 1 2 18 XX A [shortptr.w] XOR A,[$10.w] 4 3 92 C8 XX ✗ A [longptr.w] XOR A,[$1000.w] 4 4 72 C8 MS LS A ([shortptr.w],X) XOR A,([$10.w],X) 4 3 92 D8 XX ✗ A ([longptr.w],X) XOR A,([$1000.w],X) 4 4 72 D8 MS LS A ([shortptr.w],Y) XOR A,([$1000],Y) 4 3 91 D8 XX ✗ See also: AND, OR, CPL, NEG 146/148 PM0044 7 Revision history Revision history Table 5. Document revision history Date Revision Changes 14-Jan-2008 1 Initial release. 05-Jun-2008 2 Modified Figure 2: Context save/restore for interrupts on page 13 147/148 PM0044 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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