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4047 CMOS 单稳态、无稳态多谐振荡器.pdf

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4047 CMOS 单稳态、无稳态多谐振荡器.pdf

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CD4047BC Low Power Monostable/Astable Multivibrator October 1987 Revised May 1999 CD4047BC Low Power Monostable/Astable Multivibrator General Description The CD4047B is capable of operating in either the monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor (between pins 2 and 3) to determine the output pulse width in the monostable mode, and the output frequency in the astable mode. Astable operation is enabled by a high level on the astable input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of Q is available at the Oscillator Output; a 50% duty cycle is not guaranteed. Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or HIGH-to-LOW transition at − trigger input. The device can be retriggered by applying a simultaneous LOW-to-HIGH transition to both the + trigger and retrigger inputs. A high level on Reset input resets the outputs Q to LOW, Q to HIGH. Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS SPECIAL FEATURES s Low power consumption: special CMOS oscillator configuration s Monostable (one-shot) or astable (free-running) operation s True and complemented buffered outputs s Only one external R and C required MONOSTABLE MULTIVIBRATOR FEATURES s Positive- or negative-edge trigger s Output pulse width independent of trigger pulse duration s Retriggerable option for pulse width expansion s Long pulse widths possible using small RC components by means of external counter provision s Fast recovery time essentially independent of pulse width s Pulse-width accuracy maintained at duty cycles approaching 100% ASTABLE MULTIVIBRATOR FEATURES s Free-running or gatable operating modes s 50% duty cycle s Oscillator output available s Good astable frequency stability typical= ±2% + 0.03%/°C @ 100 kHz frequency= ±0.5% + 0.015%/°C @ 10 kHz deviation (circuits trimmed to frequency VDD = 10V ±10%) Applications • Frequency discriminators • Timing circuits • Time-delay applications • Envelope detection • Frequency multiplication • Frequency division Ordering Code: Order Number Package Number Package Description CD4047BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4047BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS005969.prf www.fairchildsemi.com CD4047BC Connection Diagram Pin Assignments for SOIC and DIP Top View Function Table Terminal Connections Function To VDD To VSS Input Pulse To Astable Multivibrator Free-Running 4, 5, 6, 14 7, 8, 9, 12 True Gating 4, 6, 14 7, 8, 9, 12 5 Complement Gating 6, 14 5, 7, 8, 9, 12 4 Monostable Multivibrator Positive-Edge Trigger 4, 14 5, 6, 7, 9, 12 8 Negative-Edge Trigger 4, 8, 14 5, 7, 9, 12 6 Retriggerable 4, 14 5, 6, 7, 9 8, 12 External Countdown (Note 1) 14 5, 6, 7, 8, 9, 12 Figure 1 Output Pulse From Typical Output Period or Pulse Width 10, 11, 13 10, 11, 13 10, 11, 13 tA(10, 11) = 4.40 RC tA (13) = 2.20 RC 10, 11 10, 11 10, 11 Figure 1 tM (10, 11) = 2.48 RC Figure 1 Note 1: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3. Typical Implementation of External Countdown Option tEXT = (N − 1) tA + (tM + tA/2) FIGURE 1. www.fairchildsemi.com 2 CD4047BC Block Diagram Logic Diagram *Special input protection circuit to permit larger input-voltage swings. 3 www.fairchildsemi.com CD4047BC Absolute Maximum Ratings(Note 2) (Note 3) DC Supply Voltage (VDD) −0.5V to +18VDC Input Voltage (VIN) −0.5V to VDD +0.5VDC Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260°C Recommended Operating Conditions (Note 3) DC Supply Voltage (VDD) 3V to 15VDC Input Voltage (VIN) 0 to VDD VDC Operating Temperature Range (TA) −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol Parameter Conditions IDD Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage |IO| < 1 µA VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1 µA VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VIH HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V IOL LOW Level Output Current VDD = 5V, VO = 0.4V (Note 4) VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V IOH HIGH Level Output Current VDD = 5V, VO = 4.6V (Note 4) VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V IIN Input Current VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 4: IOH and IOL are tested one output at a time. −40°C 25°C 85°C Units Min Max Min Typ Max Min Max 20 20 150 µA 40 40 300 µA 80 80 600 µA 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V 4.95 4.95 5 4.95 V 9.95 9.95 10 9.95 V 14.95 14.95 15 14.95 V 1.5 2.25 1.5 1.5 V 3.0 4.5 3.0 3.0 V 4.0 6.75 4.0 4.0 V 3.5 3.5 2.75 3.5 V 7.0 7.0 5.5 7.0 V 11.0 11.0 8.25 11.0 V 0.52 0.44 0.88 0.36 mA 1.3 1.1 2.25 0.9 mA 3.6 3.0 8.8 2.4 mA −0.52 −0.44 −0.88 −0.36 mA −1.3 −1.1 −2.25 −0.9 mA −3.6 −3.0 −8.8 −2.4 mA −0.3 −10−5 −0.3 −1.0 µA 0.3 10−5 0.3 1.0 µA www.fairchildsemi.com 4 CD4047BC AC Electrical Characteristics (Note 5) TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified. Symbol Parameter Conditions Min Typ tPHL, tPLH Propagation Delay Time Astable, VDD = 5V 200 Astable to Osc Out VDD = 10V 100 VDD = 15V 80 tPHL, tPLH Astable, Astable to Q, Q VDD = 5V 550 VDD = 10V 250 VDD = 15V 200 tPHL, tPLH + Trigger, − Trigger to Q VDD = 5V 700 VDD = 10V 300 VDD = 15V 240 tPHL, tPLH + Trigger, Retrigger to Q VDD = 5V 300 VDD = 10V 175 VDD = 15V 150 tPHL, tPLH Reset to Q, Q VDD = 5V 300 VDD = 10V 125 VDD = 15V 100 tTHL, tTLH Transition Time Q, Q, Osc Out VDD = 5V 100 VDD = 10V 50 VDD = 15V 40 tWL, tWH Minimum Input Pulse Duration Any Input VDD = 5V 500 VDD = 10V 200 VDD = 15V 160 tRCL, tFCL + Trigger, Retrigger, Rise and VDD = 5V Fall Time VDD = 10V VDD = 15V CIN Average Input Capacitance Any Input 5 Note 5: AC Parameters are guaranteed by DC correlated testing. Max 400 200 160 900 500 400 1200 600 480 600 300 250 600 250 200 200 100 80 1000 400 320 15 5 5 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs pF 5 www.fairchildsemi.com CD4047BC Typical Performance Characteristics Typical Q, Q, Osc Out Period Accuracy vs Supply Voltage (Astable Mode Operation) Typical Q, Q, Pulse Width Accuracy vs Supply Voltage Monostable Mode Operation fQ, Q A 1000 kHz B 100 kHz C 10 kHz D 1 kHz E 100 Hz R 22k 22k 220k 220k 2.2M C 10 pF 100 pF 100 pF 1000 pF 1000 pF Typical Q, Q and Osc Out Period Accuracy vs Temperature Astable Mode Operation tM A 2 µs B 7 µs C 60 µs D 550 µs E 5.5 ms R 22k 22k 220k 220k 2.2M C 10 pF 100 pF 100 pF 1000 pF 1000 pF Typical Q and Q Pulse Width Accuracy vs Temperature Monostable Mode Operation fQ, Q A 1000 kHz B 100 kHz C 10 kHz D 1 kHz R 22k 22k 220k 220k C 10 pF 100 pF 100 pF 1000 pF tM A 2 µs B 7 µs C 60 µs D 550 µs R 22k 22k 220k 220k C 10 pF 100 pF 100 pF 1000 pF www.fairchildsemi.com 6 CD4047BC Timing Diagrams Astable Mode Monostable Mode Retrigger Mode 7 www.fairchildsemi.com CD4047BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 8 CD4047BC Low Power Monostable/Astable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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