首页资源分类IC设计及制造 > physics of semiconductor devices

physics of semiconductor devices

已有 460162个资源

下载专区


TI最新应用解决方案

工业电子 汽车电子 个人消费电子

上传者其他资源

文档信息举报收藏

标    签: 电子器件

分    享:

文档简介

半导体物理器件基础,施敏

文档预览

Physics of Semiconductor Devices Physics of Semiconductor Devices Third Edition S. M. Sze Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan and Kwok K. Ng Central Laboratory MVC (a subsidiary of ProMOS Technologies,Taiwan) San Jose, California @ZZClE*CE A JOHN WILEY & SONS, JNC., PUBLICATION Description of cover photograph. A scanning electron micrograph of an array of the floating-gate nonvolatile semiconductor memory (NVSM) magnified 100,000times. NVSM was invented at Bell Telephone Laboratories in 1967. There are more NVSM cells produced annually in the world than any other semiconductor device and, for that matter, any other human-made item. For a discussion of this device, see Chapter 6. Photo courtesy of Macronix International Company, Hsinchu, Taiwan, ROC. Copyright 0 2007 by John Wiley & Sons, Inc. All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-601 I , fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of LiabilityiDisclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data is available. ISBN-I 3: 978-0-47 1-1 4323-9 ISBN-10: 0-471-14323-5 Printed in the United States of America 10987654321 Preface Since the mid-20th Century the electronics industry has enjoyed phenomenal growth and is now the largest industry in the world. The foundation of the electronics industry is the semiconductor device. To meet the tremendous demand of this industry, the semiconductor-device field has also grown rapidly. Coincident with this growth, the semiconductor-device literature has expanded and diversified. For access to this massive amount of information, there is a need for a book giving a comprehensive introductory account of device physics and operational principles. With the intention of meeting such a need, the First Edition and the Second Edition of Physics of Semiconductor Devices were published in 1969 and 1981, respectively. It is perhaps somewhat surprising that the book has so long held its place as one of the main textbooks for advanced undergraduate and graduate students in applied physics, electrical and electronics engineering, and materials science. Because the book includes much useful information on material parameters and device physics, it is also a major reference for engineers and scientists in semiconductor-device research and development. To date, the book is one of the most, if not the most, cited works in contemporary engineering and applied science with over 15,000 citations (ISI, Thomson Scientific). Since 1981, more than 250,000 papers on semiconductor devices have been published, with numerous breakthroughs in device concepts and performances. The book clearly needed another major revision if it were to continue to serve its purpose. In this Third Edition of Physics of Semiconductor Devices, over 50% of the material has been revised or updated, and the material has been totally reorganized. We have retained the basic physics of classic devices and added many sections that are of contemporary interest such as the three-dimensional MOSFETs, nonvolatile memory, modulation-doped field-effect transistor, single-electron transistor, resonant-tunneling diode, insulated-gate bipolar transistor, quantum cascade laser, semiconductor sensors, and so on. On the other hand, we have omitted or reduced sections of lessimportant topics to maintain the overall book length. We have added a problem set at the end of each chapter. The problem set forms an integral part of the development of the topics, and some problems can be used as worked examples in the classroom. A complete set of detailed solutions to all end-ofchapter problems has been prepared. The solution manuals are available free to all adopting faculties. The figures and tables used in the text are also available, in electronic format, to instructors from the publisher. Instructors can find out more information at the publisher’s website at http://ww.wiley.com/interscience/sze. V vi PREFACE In the course of writing this text, we had the fortune of help and support of many people. First we express our gratitude to the management of our academic and industrial institutions, the National Chiao Tung University, the National Nan0 Device Laboratories, Agere Systems, and MVC, without whose support this book could not have been written. We wish to thank the Spring Foundation of the National Chiao Tung University for the financial support. One of us (K. Ng) would like to thank J. Hwang and B. Leung for their continued encouragement and personal help. We have benefited greatly from suggestions made by our reviewers who took their time from their busy schedule. Credits are due to the following scholars: A. Alam, W. Anderson, S. Banerjee, J. Brews, H. C. Casey, Jr., P. Chow, N. de Rooij, H. Eisele, E. Kasper, S. Luryi, D. Monroe, P. Panayotatos, S. Pearton, E. F. Schubert, A. Seabaugh, M. Shur, Y. Taur, M. Teich, Y. Tsividis, R. Tung, E. Yang, and A. Zaslavsky. We also appreciate the permission granted to us from the respective journals and authors to reproduce their original figures cited in this work. It is our pleasure to acknowledge the help of many family members in preparing the manuscript in electronic format; Kyle Eng and Valerie Eng in scanning and importing text from the Second Edition, Vivian Eng in typing the equations, and Jennifer Tao in preparing the figures which have all been redrawn. We are further thankful to Norman Erdos for technical editing of the entire manuscript, and to Iris Lin and Nai-Hua Chang for preparing the problem sets and solution manual. At John Wiley and Sons, we wish to thank George Telecki who encouraged us to undertake the project. Finally, we are grateful to our wives, Therese Sze and Linda Ng, for their support and assistance during the course of the book project. S. M. Sze Hsinchu, Taiwan Kwok K. Ng San Jose, California July 2006 Contents Introduction 1 Part I Semiconductor Physics Chapter 1 Physics and Properties of Semiconductors-A Review 7 1.1 Introduction, 7 1.2 Crystal Structure, 8 1.3 Energy Bands and Energy Gap, 12 1.4 Carrier Concentration at Thermal Equilibrium, 16 1.5 Carrier-Transport Phenomena, 28 1.6 Phonon, Optical, and Thermal Properties, 50 1.7 Heterojunctions and Nanostructures, 56 1.8 Basic Equations and Examples, 62 Part I1 Device Building Blocks Chapter 2 p-n Junctions 79 2.1 Introduction, 79 2.2 Depletion Region, 80 2.3 Current-Voltage Characteristics, 90 2.4 Junction Breakdown, 102 2.5 Transient Behavior and Noise, 114 2.6 Terminal Functions, 118 2.7 Heterojunctions, 124 Chapter 3 Metal-Semiconductor Contacts 134 3. I Introduction, 134 3.2 Formation of Barrier, 135 3.3 Current Transport Processes, 153 3.4 Measurement of Barrier Height, 170 3.5 Device Structures, 181 3.6 Ohmic Contact, 187 Vii viii CONTENTS Chapter 4 Metal-Insulator-Semiconductor Capacitors 197 4.1 Introduction, 197 4.2 Ideal MIS Capacitor, 198 4.3 Silicon MOS Capacitor, 213 Part I11 Transistors Chapter 5 Bipolar Transistors 243 5.1 Introduction, 243 5.2 Static Characteristics, 244 5.3 Microwave Characteristics, 262 5.4 Related Device Structures, 275 5.5 Heterojunction Bipolar Transistor, 282 Chapter 6 MOSFETs 293 6.1 Introduction, 293 6.2 Basic Device Characteristics, 297 6.3 Nonuniform Doping and Buried-Channel Device, 320 6.4 Device Scaling and Short-Channel Effects, 328 6.5 MOSFET Structures, 339 6.6 Circuit Applications, 347 6.7 Nonvolatile Memory Devices, 350 6.8 Single-Electron Transistor, 360 Chapter 7 JFETs, MESFETs, and MODFETs 374 7.1 Introduction, 374 7.2 JFET and MESFET, 375 7.3 MODFET, 401 Part IV Negative-Resistance and Power Devices Chapter 8 Tunnel Devices 417 8.1 Introduction, 417 8.2 Tunnel Diode, 418 8.3 Related Tunnel Devices, 435 8.4 Resonant-Tunneling Diode, 454 Chapter 9 IMPATT Diodes 466 9.1 Introduction, 466 9.2 Static Characteristics, 467 9.3 Dynamic Characteristics, 474 9.4 Power and Efficiency, 482 9.5 Noise Behavior, 489 9.6 Device Design and Performance, 493 9.7 BARITT Diode, 497 9.8 TUNNETT Diode, 504 CONTENTS ix Chapter 10 Transferred-Electron and Real-Space-Transfer Devices 510 10.1 Introduction, 510 10.2 Transferred-Electron Device, 511 10.3 Real-Space-Transfer Devices, 536 Chapter 11 Thyristors and Power Devices 548 11.1 Introduction, 548 11.2 Thyristor Characteristics, 549 11.3 Thyristor Variations, 574 11.4 Other Power Devices, 582 Part V Photonic Devices and Sensors Chapter 12 LEDs and Lasers 60 1 12.1 Introduction, 601 12.2 Radiative Transitions, 603 12.3 Light-Emitting Diode (LED), 608 12.4 Laser Physics, 621 12.5 Laser Operating Characteristics, 630 12.6 Specialty Lasers, 651 Chapter 13 Photodetectors and Solar Cells 663 13.1 Introduction, 663 13.2 Photoconductor, 667 13.3 Photodiodes, 671 13.4 Avalanche Photodiode, 683 13.5 Phototransistor, 694 13.6 Charge-Coupled Device (CCD), 697 13.7 Metal-Semiconductor-Metal Photodetector, 7 12 13.8 Quantum-Well Infrared Photodetector, 7 16 13.9 Solar Cell, 719 x CONTENTS Chapter 14 Sensors 743 14.1 Introduction, 743 14.2 Thermal Sensors, 744 14.3 Mechanical Sensors, 750 14.4 Magnetic Sensors, 758 14.5 Chemical Sensors, 765 Appendixes 773 A. List of Symbols, 775 B. International System of Units, 785 C. Unit Prefixes, 786 D. Greek Alphabet, 787 E. Physical Constants, 788 F. Properties of Important Semiconductors, 789 G. Properties of Si and GaAs, 790 H. Properties of SiO, and Si,N,, 791 Index 793 Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. Introduction The book is organized into five parts: Part I: Semiconductor Physics Part 11: Device Building Blocks Part 111: Transistors Part IV: Negative-Resistance and Power Devices Part V Photonic Devices and Sensors Part I, Chapter 1, is a summary of semiconductor properties that are used throughout the book as a basis for understanding and calculating device characteristics. Energy band, carrier concentration, and transport properties are briefly surveyed, with emphasis on the two most-important semiconductors: silicon (Si) and gallium arsenide (GaAs). A compilation of the recommended or most-accurate values for these semiconductors is given in the illustrations of Chapter 1 and in the Appendixes for convenient reference. Part 11, Chapters 2 through 4, treats the basic device building blocks from which all semiconductor devices can be constructed. Chapter 2 considers the p-n junction characteristics. Because thep-n junction is the building block of most semiconductor devices, p-n junction theory serves as the foundation of the physics of semiconductor devices. Chapter 2 also considers the heterojunction, that is a junction formed between two dissimilar semiconductors. For example, we can use gallium arsenide (GaAs) and aluminum arsenide (AlAs) to form a heterojunction. The heterojunction is a key building block for high-speed and photonic devices. Chapter 3 treats the metal-semiconductor contact, which is an intimate contact between a metal and a semiconductor. The contact can be rectifying similar to ap-n junction if the semiconductor is moderately doped and becomes ohmic if the semiconductor is very heavily doped. An ohmic contact can pass current in either direction with a negligible voltage drop and can provide the necessary connections between devices and the outside world. Chapter 4 considers the metal-insulator-semiconductor (MIS) capacitor of which the Si-based metal-oxide-semiconductor (MOS) structure is the dominant member. Knowledge of the surface physics associated with the MOS capacitor is important, not only for understanding MOS-related devices such as the MOSFET and the floating-gate nonvolatile memory but also because of its relevance to the stability and reliability of all other semiconductor devices in their surface and isolation areas. 1 2 INTRODUCTION Part 111,Chapters 5 through 7 ,deals with the transistor family. Chapter 5 treats the bipolar transistor, that is, the interaction between two closely coupled p-n junctions. The bipolar transistor is one of the most-important original semiconductor devices. The invention of the bipolar transistor in 1947 ushered in the modern electronic era. Chapter 6 considers the MOSFET (MOS field-effect transistor). The distinction between a field-effect transistor and a potential-effect transistor (such as the bipolar transistor) is that in the former, the channel is modulated by the gate through a capacitor whereas in the latter, the channel is controlled by a direct contact to the channel region. The MOSFET is the most-important device for advanced integrated circuits, and is used extensively in microprocessors and DRAMS (dynamic random access memories). Chapter 6 also treats the nonvolatile semiconductor memory which is the dominant memory for portable electronic systems such as the cellular phone, notebook computer, digital camera, audio and video players, and global positioning system (GPS). Chapter 7 considers three other field-effect transistors; the JFET (junction field-effect-transistor), MESFET (metal-semiconductor field-effect transistor), and MODFET (modulation-doped field-effect transistor). The JFET is an older member and now used mainly as power devices, whereas the MESFET and MODFET are used in high-speed, high-input-impedance amplifiers and monolithic microwave integrated circuits. Part IV, Chapters 8 through 1 1 , considers negative-resistance and power devices. In Chapter 8, we discuss the tunnel diode (a heavily dopedp-n junction) and the resonant-tunneling diode (a double-barrier structure formed by multiple heterojunctions). These devices show negative differential resistances due to quantummechanical tunneling. They can generate microwaves or serve as functional devices, that is, they can perform a given circuit function with a greatly reduced number of components. Chapter 9 discusses the transit-time devices. When a p-n junction or a metal-semiconductor junction is operated in avalanche breakdown, under proper conditions we have an IMPATT diode that can generate the highest CW (continuous wave) power output of all solid-state devices at millimeter-wave frequencies (i.e., above 30 GHz). The operational characteristics of the related BARITT and TUNNETT diodes are also presented. The transferred-electron device (TED) is considered in Chapter 10. Microwave oscillation can be generated by the mechanism of electron transfer from a high-mobility lower-energy valley in the conduction band to a low-mobility higher-energy valley (in momentum space), the transferred-electron effect. Also presented are the real-space-transfer devices which are similar to TED but the electron transfer occurs between a narrow-bandgap material to an adjacent wide-bandgap material in real space as opposed to momentum space. The thyristor, which is basically three closely coupledp-n junctions in the form of ap-n-p-n structure, is discussed in Chapter 11. Also considered are the MOS-controlled thyristor (a combination of MOSFET with a conventional thyristor) and the insulated-gate bipolar transistor (IGBT, a combination of MOSFET with a conventional bipolar transistor). These devices have a wide range of power-handling and switching capability; they can handle currents from a few milliamperes to thousands of amperes and voltages above 5000 V. INTRODUCTION 3 Part V, Chapters 12 through 14, treats photonic devices and sensors. Photonic devices can detect, generate, and convert optical energy to electric energy, or vice versa. The semiconductor light sources-light-emitting diode (LED) and laser, are discussed in Chapter 12. The LEDs have a multitude of applications as display devices such as in electronic equipment and traffic lights, and as illuminating devices such as flashlights and automobile headlights. Semiconductor lasers are used in optical-fiber communication, video players, and high-speed laser printing. Various photodetectors with high quantum efficiency and high response speed are discussed in Chapter 13. The chapter also considers the solar cell which converts optical energy to electrical energy similar to a photodetector but with different emphasis and device configuration. As the worldwide energy demand increases and the fossil-fuel supply will be exhausted soon, there is an urgent need to develop alternative energy sources. The solar cell is considered a major candidate because it can convert sunlight directly to electricity with good conversion efficiency, can provide practically everlasting power at low operating cost, and is virtually nonpolluting. Chapter 14 considers important semiconductor sensors. A sensor is defined as a device that can detect or measure an external signal. There are basically six types of signals: electrical, optical, thermal, mechanical, magnetic, and chemical. The sensors can provide us with informations about these signals which could not otherwise be directly perceived by our senses. Based on the definition of sensors, all traditional semiconductor devices are sensors since they have inputs and outputs and both are in electrical forms. We have considered the sensors for electrical signals in Chapters 2 through 11, and the sensors for optical signals in Chapters 12 and 13. In Chapter 14, we are concerned with sensors for the remaining four types of signals, i.e., thermal, mechanical, magnetic, and chemical. We recommend that readers first study semiconductor physics (Part I) and the device building blocks (Part 11)before moving to subsequent parts of the book. Each chapter in Parts I11through V deals with a major device or a related device family, and is more or less independent of the other chapters. So, readers can use the book as a reference and instructors can select chapters appropriate for their classes and in their order of preference. We have a vast literature on semiconductor devices. To date, more than 300,000 papers have been published in this field, and the grand total may reach one million in the next decade. In this book, each chapter is presented in a clear and coherent fashion without heavy reliance on the original literature. However, we have an extensive listing of key papers at the end of each chapter for reference and for further reading. REFERENCE 1. K. K. Ng, Complete Guide to Semiconductor Devices, 2nd Ed., Wiley, New York, 2002. Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. 1 PART SEMICONDUCTOR PHYSICS + Chapter 1 Physics and Properties of Semiconductors -A Review Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. Physics and Properties of Semiconductors-A Review 1.1 INTRODUCTION 1.2 CRYSTAL STRUCTURE 1.3 ENERGY BANDS AND ENERGY GAP 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 1.5 CARRIER-TRANSPORT PHENOMENA 1.6 PHONON, OPTICAL, AND THERMAL PROPERTIES 1.7 HETEROJUNCTIONS AND NANOSTRUCTURES 1.8 BASIC EQUATIONS AND EXAMPLES 1.1 INTRODUCTION The physics of semiconductor devices is naturally dependent on the physics of semiconductor materials themselves. This chapter presents a summary and review of the basic physics and properties of semiconductors. It represents only a small cross section of the vast literature on semiconductors; only those subjects pertinent to device operations are included here. For detailed consideration of semiconductor physics, the reader should consult the standard textbooks or reference works by Dunlap,' Madelung,2 Moll,3 Moss,4 Smith.s Boer: Seeger,' and Wang,s to name a few. To condense a large amount of information into a single chapter, four tables (some in appendixes) and over 30 illustrations drawn from experimental data are compiled and presented here. This chapter emphasizes the two most-important semiconductors: silicon (Si) and gallium arsenide (GaAs). Silicon has been studied extensively and widely used in commercial electronics products. Gallium arsenide has been intensively investigated in recent years. Particular properties studied are its direct bandgap 7 8 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW for photonic applications and its intervalley-carrier transport and higher mobility for generating microwaves. 1.2 CRYSTAL STRUCTURE 1.2.1 Primitive Cell and Crystal Plane A crystal is characterized by having a well-structured periodic placement of atoms. The smallest assembly of atoms that can be repeated to form the entire crystal is called a primitive cell, with a dimension of lattice constant a. Figure 1 shows some important primitive cells. Many important semiconductors have diamond or zincblende lattice structures which belong to the tetrahedral phases; that is, each atom is surrounded by four equidistant nearest neighbors which lie at the corners of a tetrahedron. The bond between two nearest neighbors is formed by two electrons with opposite spins. The diamond and the zincblende lattices can be considered as two interpenetrating face-centered cubic (fcc) lattices. For the diamond lattice, such as silicon (Fig. Id), all the atoms are the same; whereas in a zincblende lattice, such as gallium arsenide (Fig. le), one sublattice is gallium and the other is arsenic. Gallium arsenide is a 111-V compound, since it is formed from elements of groups I11 and V of the periodic table. Most 111-V compounds crystallize in the zincblende ~tructure;h~o,w~ ever, many semiconductors (including some 111-V compounds) crystallize in the rock-salt or wurtzite structures. Figure If shows the rock-salt lattice, which again can be considered as two interpenetrating face-centered cubic lattices. In this rock-salt structure, each atom has six nearest neighbors. Figure l g shows the wurtzite lattice, which can be considered as two interpenetrating hexagonal close-packed lattices (e.g., the sub- lattices of cadmium and sulfur). In this picture, for each sublattice (Cd or s),the two planes of adjacent layers are displaced horizontally such that the distance between these two planes are at a minimum (for a fixed distance between centers of two atoms), hence the name close-packed. The wurtzite structure has a tetrahedral arrangement of four equidistant nearest neighbors, similar to a zincblende structure. Appendix F gives a summary of the lattice constants of important semiconductors, together with their crystal structures.loJ1Note that some compounds, such as zinc sulfide and cadmium sulfide, can crystallize in either zincblende or wurtzite structures. Since semiconductor devices are built on or near the semiconductor surface, the orientations and properties of the surface crystal planes are important. A convenient method of defining the various planes in a crystal is to use Miller indices. These indices are determined by first finding the intercepts of the plane with the three basis axes in terms of the lattice constants (or primitive cells), and then taking the reciprocals of these numbers and reducing them to the smallest three integers having the same ratio. The result is enclosed in parentheses (hkl) called the Miller indices for a single plane or a set of parallel planes {hkl}.Figure 2 shows the Miller indices of important planes in a cubic crystal. Some other conventions are given in Table 1. For Body-centered cubic (Na, W, etc.) ib) Face-centered cubic (A], Au, etc.) ic) TetrahedrA Diamond (Si, Ge, C, etc.) id) Tetrahedroh Zincblende (GaAs, Gap, etc.) ie) Rock-salt (PbS, PbTe, etc.) if) Wurtzite (CdS, ZnS, etc.) (9) Fig. 1 Some important primitive cells (direct lattices) and their representative elements; a is the lattice constant. 9 10 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW Fig. 2 Miller indices of some important planes in a cubic crystal. silicon, a single-element semiconductor, the easiest breakage or cleavage planes are the { 111} planes. In contrast, gallium arsenide, which has a similar lattice structure but also has a slight ionic component in the bonds, cleaves on { 1lo} planes. Three primitive basis vectors, a, b, and c of a primitive cell, describe a crystalline solid such that the crystal structure remains invariant under translation through any vector that is the sum of integral multiples of these basis vectors. In other words, the direct lattice sites can be defined by the set12 R = ma+nb+pc (1) where m, n, andp are integers. 1.2.2 Reciprocal Lattice For a given set of the direct basis vectors, a set of reciprocal lattice basis vectors a*, b*,c* can be defined as Table 1 Miller Indices and Their Represented Plane or Direction of a Crystal Surface Miller Indices (hkl) (hkl) { hkl} [hkl] (hkl) [hklm] Description of plane or direction For a plane that intercepts llh, llk, 1ll on the x-, y-, and z-axis, respectively. For a plane that intercepts the negative x-axis. For a full set of planes of equivalent symmetry, such as { 100) for (100), (0lo), (OOl),(iOO),(OiO), and(O0i)incubicsymmetry. For a direction of a crystal such as [1001 for the x-axis. For a full set of equivalent directions. For a plane in a hexagonal lattice (such as wurtzite) that intercepts llh, llk,1/l, llm on the q-,a*-, q-,andz-axis, respectively (Fig. lg). 1.2 CRYSTAL STRUCTURE 11 - such that a * a* = 2 r , a b* = 0, and so on. The denominators are identical due to the - - equality that a b x c = b c x a = c * a x b which is the volume enclosed by these vectors. The general reciprocal lattice vector is given by G = ha* + kb* + Ic* (3) where h, k,and I are integers. It follows that one important relationship between the direct lattice and the reciprocal lattice is G,R= 2 z x Integer, (4) and therefore each vector of the reciprocal lattice is normal to a set of planes in the direct lattice. The volume Vz of a primitive cell of the reciprocal lattice is inversely proportional to that (V,) of the direct lattice; that is, V: = ( ~ Z ) ~ / wVh~er, e V,=a*bxc. The primitive cell of a reciprocal lattice can be represented by a Wigner-Seitz cell. The Wigner-Seitz cell is constructed by drawing perpendicular bisector planes in the reciprocal lattice from the chosen center to the nearest equivalent reciprocal lattice sites. This technique can also be applied to a direct lattice. The Wigner-Seitz cell in the reciprocal lattice is called the first Brillouin zone. Figure 3a shows a typical example for a body-centered cubic (bcc) reciprocal 1atti~e.Ilf~one first draws lines from the center point (r)to the eight comers of the cube, then forms the bisector t kz (4 Fig. 3 Brillouin zones for (a) fcc, diamond, and zincblende lattices, (b) bcc lattice, and (c) wurtzite lattice. 12 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW planes, the result is the truncated octahedron within the cube-a Wigner-Seitz cell. It can be shown that14 a face-centered cubic (fcc) direct lattice with lattice constant a has a bcc reciprocal lattice with spacing 4nla. Thus the Wigner-Seitz cell shown in Fig. 3a is the primitive cell of the reciprocal (bcc) lattice for an fcc direct lattice. The Wigner-Seitz cells for bcc and hexagonal direct lattices can be similarly constructed and shown in Figs. 3b and 3c.15It will be shown that the reciprocal lattice is useful to visualize the E-k relationship when the coordinates of the wave vectors k (lkl = k = 2 d A )are mapped into the coordinates of the reciprocal lattice. In particular, the Brillouin zone for the fcc lattice is important because it is relevant to most semiconductor materials of interest here. The symbols used in Fig. 3a will be discussed in more details. 1.3 ENERGY BANDS AND ENERGY GAP The energy-momentum (E-k) relationship for carriers in a lattice is important, for example, in the interactions with photons and phonons where energy and momentum have to be conserved, and with each other (electrons and holes) which leads to the concept of energy gap. This relationship also characterizes the effective mass and the group velocity, as will be discussed later. The band structure of a crystalline solid, that is, the energy-momentum (E-k)rela- tionship, is usually obtained by solving the Schrodinger equation of an approximate one-electron problem. The Bloch theorem, one of the most-important theorems basic to band structure, states that if a potential energy V(r) is periodic in the direct lattice space, then the solutions for the wavefunction dr,k) of the Schrodinger e q ~ a t i o n ' ~ , ' ~ 1 - -V2 + V(r) W(r,k) = E(k)W(r, k ) (5) are of the form of a Bloch function W(r,k) = exp(jk. r)Ub(r,k ) . (6) Here b is the band index, &r,k) and Ub(r,k) are periodic in R of the direct lattice. Since W(r+R, k ) = expLjk. ( r + R)]U,(r + R, k ) = exp(jk.r)exp(jk.R)Ub(r, k), (7) and is equal to dr,k), it is necessary that k R is a multiple of 227. It is the property of Eq. 4 that the reciprocal lattice can be used when G is replaced with k for visualizing the E-k relationship. From the Bloch theorem one can also show that the energy E(k) is periodic in the reciprocal lattice, that is, E(k) = E(k+G), where G is given by Eq. 3. For a given band index, to label the energy uniquely, it is sufficient to use only k's in a primitive cell of the reciprocal lattice. The standard convention is to use the Wigner-Seitz cell in the reciprocal lattice (Fig. 3). This cell is the Brillouin zone or the first Brillouin 20ne.l~ It is thus evident that we can reduce any momentum k in the reciprocal space to a 1.3 ENERGY BANDS AND ENERGY GAP 13 point inside the Brillouin zone, where any energy state can be given a label in the reduced zone schemes. The Brillouin zone for the diamond and the zincblende lattices is the same as that of the fcc and is shown in Fig. 3a. Table 2 summarizes its most-important symmetry points and symmetry lines, such as the center of the zone, the zone edges and their corresponding k axes. The energy bands of solids have been studied theoretically using a variety of numerical methods. For semiconductors the three methods most frequently used are the orthogonalized plane-wave method,l79l8the pseudopotential method,19 and the k - p m e t h ~ dF. i~gure 4 shows results of studies of the energy-band structures of Si and GaAs. Notice that for any semiconductor there is a forbidden energy range in which allowed states cannot exist. Energy regions or energy bands are permitted above and below this energy gap. The upper bands are called the conduction bands; the lower bands, the valence bands. The separation between the energy of the lowest conduction band and that of the highest valence band is called the bandgap or energy gap Eg, which is one of the most-important parameters in semiconductor physics. In this figure the bottom of the conduction band is designated E,, and the top of the valence band E, Within the bands, the electron energy is conventionally defined to be positive when measured upward from E,, and the hole energy is positive when measured downward from E,. The bandgaps of some important semiconductors are listed in Appendix F. The valence band in the zincblende structure, such as that for GaAs in Fig. 4b, consists of four subbands when spin is neglected in the Schrodinger equation, and each band is doubled when spin is taken into account. Three of the four bands are degenerate at k = 0 (rpoint) and form the upper edge of the band, and the fourth band forms the bottom (not shown). Furthermore, the spin-orbit interaction causes a splitting of the band at k = 0. Near the band edges, i.e., bottom of E, and top of E, the E-k relationship can be approximated by a quadratic equation where m*is the associated effective mass. But as shown in Fig. 4, along a given direction, the two top valence bands can be approximated by two parabolic bands with different curvatures: the heavy-hole band (the wider band in k-axis with smaller d2Eldk2) Table 2 Brillouin Zone of fcc, Diamond, and Zincblende Lattices: Zone Edges and Their Corresponding Axes (ris the Center) Point r, ( 0 ~ 0 ) Degeneracy Axis 1 14 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 6 5 4 3 2 h ? v I xl Fs W 0 valley valley -1 -2 -3 L [111] r [ioo] x Wave vector 4 L [1111 r [ioo] Wave vector (a) (b) Fig. 4 Energy-band structures of (a) Si and (b) GaAs, where Eg is the energy bandgap. Plus signs (+) indicate holes in the valence bands and minus signs (-) indicate electrons in the conduction bands. (After Ref. 20.) and the light-hole band (the narrower band with larger d2E/ak2)T. he effective mass in general is tensorial with components m i defined as 1 -- 1 d 2 E ( k ) m?'J . h2 dkidkj (9) The effective masses are listed in Appendix F for important semiconductors. Carriers in motion are also characterized by a group velocity lJ = -1-dE g hdk and with momentum p = hk. (1 1) The conduction band consists of a number of subbands (Fig. 4). The bottom of the conduction band can appear at the center k = 0 (r)or off center along different k axes. Symmetry considerations alone do not determine the location of the bottom of the conduction band. Experimental results show, however, that in Si it is off center and 1.3 ENERGY BANDS AND ENERGY GAP 15 along the [1001axis (A), and in GaAs the bottom is at k = 0 (r).Considering that the valence-band maximum (E,) occurs at r, the conduction-band minimum can be aligned or misaligned in k-space in determining the bandgap. This results in direct bandgap for GaAs and indirect bandgap for Si. This bears significant consequences when carriers transfer between this minimum gap in that momentum (or k) is conserved for direct bandgap but changed for indirect bandgap. Figure 5 shows the shapes of the constant-energy surfaces. For Si there are six ellipsoids along the (100)-axes, with the centers of the ellipsoids located at about three-fourths of the distance from the Brillouin zone center. For GaAs the constant energy surface is a sphere at the zone center. By fitting experimental results to parabolic bands, we obtain the electron effective masses; one for GaAs and two for Si, mf along the symmetry axes and mf transverse to the symmetry axes. Appendix G also includes these values. At room temperature and under normal atmospheric pressure, the values of the bandgap are 1.12 eV for Si and 1.42 eV for GaAs. These values are for high-purity materials. For highly doped materials the bandgaps become smaller. Experimental results show that the bandgaps of most semiconductors decrease with increasing temperature. Figure 6 shows variations of bandgaps as a function of temperature for Si and GaAs. The bandgap approaches 1.17 and 1.52 eV respectively for these two semiconductors at 0 K. The variation of bandgaps with temperature can be expressed approximately by a universal function E,( T )= E,( 0 ) - - aTZ T+ P where E,(O), a, and P are given in the inset of Fig. 6. The temperature coefficient dEJdT is negative for both semiconductors. Some semiconductors have positive dE$dT; for example, the bandgap of PbS (Appendix F) increases from 0.286 eV at 0 K to 0.41 eV at 300 K. Near room temperature, the bandgap of GaAs increases with pressure P,24 and dEJdP is about 1 2 . 6 ~ 1 0 e-V~-cm2/N, while the Si bandgap decreases with pressure, with dE/dP = - 2 . 4 ~ eV-cm2/N. Si GaAs Fig. 5 Shapes of constant-energy surfaces for electrons in Si and GaAs. For Si there are six ellipsoids along the (100)-axes with the centers of the ellipsoids located at about three-fourths of the distance from the Brillouin zone center. For GaAs the constant-energy surface is a sphere at zone center. (After Ref. 21 .) 16 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW GaAs 1.519 5 . 4 ~ 1 0 - ~204 1.169 4.9~10" 655 T (K) Fig. 6 Energy bandgaps of Si and GaAs as a function of temperature. (After Refs. 22-23.) 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM One of the most-important properties of a semiconductor is that it can be doped with different types and concentrations of impurities to vary its resistivity. Also, when these impurities are ionized and the carriers are depleted, they leave behind a charge density that results in an electric field and sometimes a potential barrier inside the semiconductor. Such properties are absent in a metal or an insulator. Figure 7 shows three basic bond representations of a semiconductor. Figure 7a shows intrinsic silicon, which is very pure and contains a negligibly small amount of impurities. Each silicon atom shares its four valence electrons with the four neigh- :@:&@: .. .. t. .* *. .. (a) (b) (c) Fig. 7 Three basic bond pictures of a semiconductor. (a) Intrinsic Si with no impurity. (b) n-type Si with donor (phosphorus). (c)p-type Si with acceptor (boron). 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 17 boring atoms, forming four covalent bonds (also see Fig. 1). Figure 7b shows an n-type silicon, where a substitutional phosphorous atom with five valence electrons has replaced a silicon atom, and a negative-charged electron is donated to the lattice in the conduction band. The phosphorous atom is called a donor. Figure 7c similarly shows that when a boron atom with three valence electrons substitutes for a silicon atom, a positive-charged hole is created in the valence band, and an additional electron will be accepted to form four covalent bonds around the boron. This is p-type, and the boron is an acceptor. These names of n- andp-type had been coined when it was observed that if a metal whisker was pressed against ap-type material, forming a Schottky barrier diode (see Chapter 3), a positive bias was required on the semiconductor to produce a noticeable ~ u r r e n t .A~ls~o, ~wh~en exposed to light, a positive potential was generated with respect to the metal whisker. Conversely, a negative bias was required on an n-type material to produce a large current. 1.4.1 Carrier Concentration and Fermi Level We first consider the intrinsic case without impurities added to the semiconductor. The number of electrons (occupied conduction-band levels) is given by the total number of states N(E) multiplied by the occupancy F(E), integrated over the conduc- tion band, !1,m y1 = N(E)F(E)dE. (13) The density of states N(E) can be approximated by the density near the bottom of the conduction band for low-enough carrier densities and temperature^:^ M, is the number of equivalent minima in the conduction band and mdeis the densityof-state effective mass for electrons:5 mde = (m;m;~n;)”~ (15) where m i , m; , m i are the effective masses along the principal axes of the ellipsoidal energy surface. For example, in silicon mde= (mj+mf2)’/T3.he occupancy is a strong function of temperature and energy, and is represented by the Fermi-Dirac distribution function F(E) = 1 1 + exp[(E-E,)/kT] where EF is the Fermi energy level which can be determined from the charge neutrality condition (see Section 1.4.3). The integral of Eq. 13 can be evaluated to be 18 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW where Nc is the effective density of states in the conduction band and is given by The Fermi-Dirac integral, changing variables with (EF - Ec)/kT, is given by - (E - Ec)/KT and l;lF = whose values are plotted in Fig. 8. Note that for l;lF < -1, the integral can be approxi- vF mated by an exponential function. At = 0 when the Fermi level coincides with the band edge, the integral has a value of = 0.6 such that n = O.7Nc Nondegenerate Semiconductors. By definition, in nondegenerate semiconductors, the doping concentrations are smaller than Nc and the Fermi levels are more than several kT below E, (negative l;lF), the Fermi-Dirac integral approaches Fig. 8 Fermi-Dirac integral F,,, as a function of Fermi energy. (After Ref. 27.) Dashed line is approximation of Boltzmann statistics. 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 19 and Boltzmann statistics apply. Equation 17 becomes ( ) n = N,exp - E- Ck- TEF or E,- EF = k T l n ( y ) . Similarly, for p-type semiconductors we can obtain the hole density and its Fermi level near the top of the valence band; which can be simplified to ( ) p = Nvexp - E- Fk-TEv or E F - E , = kTln(?), hF 33'2. where N, is the effective density of states in the valence band and is given by Nv=2(2 m k Here mdh is the density-of-state effective mass of the valence band? + m d h = (m;h3I2 mih3'2)2'3 (25) where the subscripts refer to light and heavy hole masses previously referenced in Eq. 9. Degenerate Semiconductors. As shown in Fig. 8, for degenerate levels where n- or p-concentrations are near or beyond the effective density of states (N, or Nv), the value of Fermi-Dirac integral has to be used instead of the simplified Boltzmann sta- tistics. For vF> -1, the integral has weaker dependence on the carrier concentration. Note that also the Fermi levels are outside the energy gap. A useful estimate of the Fermi level as a function of carrier concentration is given by, for n-type semiconductor2* and forp-type E,- EF = kT[ l n ( 6 ) + 2-3'2(f-)] Intrinsic Concentration. For intrinsic semiconductors at finite temperatures, thermal agitation occurs which results in continuous excitation of electrons from the valence band to the conduction band, and leaving an equal number of holes in the valence band. This process is balanced by recombination of the electrons in the conduction band with holes in the valence band. At steady state, the net result is n =p = n , where ni is the intrinsic carrier density. The Fermi level for an intrinsic semiconductor (which by definition is nondegenerate) is obtained by equating Eqs. 21 and 23: 20 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW Hence the Fermi level Eiof an intrinsic semiconductor generally lies very close to, but not exactly at, the middle of the bandgap. The intrinsic carrier density nican be obtained from Eq. 21 or 23: ( ) 'G) ( s) EC-Ei ni = N,exp - - kT = N,exp(- " = f l e x - 2 k T Figure 9 shows the temperature dependence of ni for Si and GaAs. As expected, the larger the bandgap is, the smaller the intrinsic carrier density will be.30 It also follows that for nondegenerate semiconductors,the product of the majority and minority carrier concentrationsis fixed to be 1 -I"" 11000 500 \' i 'i 200 100 27 0 -20 0 1OOO/T (K-I) Fig. 9 Intrinsic carrier concentrations of Si and GaAs as a function of reciprocal temperature. (After Refs. 22 and 29.) 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 21 ( 3 p n = N,N,exp - = n' , (29) which is known as the mass-action law. But for degenerate semiconductors,pn < n; . Also using Eq. 28 and E; as the reference energy, we have the alternate equations for n-type materials; 7) EF-Ei n = niexp( or EF-E; = kTln and for p-type materials; 1.4.2 Donors and Acceptors When a semiconductor is doped with donor or acceptor impurities, impurity energy levels are introduced that usually lie within the energy gap. A donor impurity has a donor level which is defined as being neutral if filled by an electron, and positive if empty. Conversely, an acceptor level is neutral if empty and negative if filled by an electron. These energy levels are important in calculating the fraction of dopants being ionized, or electrically active, as discussed in Section 1.4.3. To get a feeling of the magnitude of the impurity ionization energy, we use the simplest calculation based on the hydrogen-atom model. The ionization energy for the hydrogen atom in vacuum is E, = m0q4 = 13.6 eV 32$&$2h2 The ionization energy for a donor (E, -ED)in a lattice can be obtained by replacing moby the conductivity effective mass of electrons5 and by replacing q., by the permittivity of the semiconductor .cSin Eq. 31: The ionization energy for donors as calculated from Eq. 33 is 0.025 eV for Si and 0.007 eV for GaAs. The hydrogen-atom calculation for the ionization level for the acceptors is similar to that for the donors. The calculated acceptor ionization energy (measured from the valence-band edge, E, = (EA- E,) is 0.05 eV for Si and GaAs. Although this simple hydrogen-atom model given above certainly cannot account for the details of ionization energy, particularly the deep levels in semiconduct o r ~ , t~he~ca-lc~ul~ated values do predict the correct order of magnitude of the true ionization energies for shallow impurities. These calculated values are shown to be 22 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW much smaller than the energy gap, and often are referred to as shallow impurities if they are close to the band edges. Also, since these small ionization energies are comparable to the thermal energy kT, ionization is usually complete at room temperature. Figure 10 shows the measured ionization energies for various impurities in Si and GaAs. Note that it is possible for a single atom to have many levels; for example, gold in silicon has both an acceptor level and a donor level in the forbidden energy gap. 1.4.3 Calculation of Fermi Level The Fermi level for the intrinsic semiconductor (Eq. 27) lies very close to the middle of the bandgap. Figure 1la depicts this situation, showing schematically from left to right the simplified band diagram, the density of states N(E), the Fermi-Dirac distribution fimction F(E), and the carrier concentrations. The shaded areas in the conduction band and the valence band represent electrons and holes, and their numbers are the same; i.e., n = p = nj for the intrinsic case. When impurities are introduced to the semiconductor crystals, depending on the impurity energy level and the lattice temperature, not all dopants are necessarily ionized. The ionized concentration for donors is given by36 where g , is the ground-state degeneracy of the donor impurity level and equal to 2 because a donor level can accept one electron with either spin (or can have no electron). When acceptor impurities of concentration NA are added to a semiconductor crystal, a similar expression can be written for the ionized acceptors where the ground-state degeneracy factor gA is 4 for acceptor levels. The value is 4 because in most semiconductors each acceptor impurity level can accept one hole of either spin and the impurity level is doubly degenerate as a result of the two degenerate valence bands at k = 0. When impurity atoms are introduced, the total negative charges (electrons and ionized acceptors) must equal the total positive charges (holes and ionized donors), represented by the charge neutrality n+Nj =p+NA. (36) With impurities added, the mass-action law (pn = n:) in Eq. 29 still applies (until degeneracy), and the pn product is always independent of the added impurities. Consider the case shown in Fig. 11b, where donor impurities with the concentration No ( ~ m - a~re) added to the crystal. The charge neutrality condition becomes n = NS+p = NL (37) With substitution, we obtain Li Sb P As Bi Me. 0 Fe Ta Pb Te N W Cr C Sn K Ge Ti Sr Cs Se Ba S MoMn V Si Na 1Si 0.08 .12 EC 0 z - - - 2 2 2 2 ;?z .31 .32 .32 ,33 .42 0 1.12 eV I I- .43 I ' B ' y ( G a In T1 Be Pd Ni Cu Cd Zn Co Pt Au Hg Ag E" (4 Si Se Ge S Sn Te 0 A 5 . O r 8 . O r 9 . 5 6 . 5 6 . c 6 GaAs 1.42 eV 1 .4 I .63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CI . 2 I .67 - .52 .44 .025 .17 CI Go4 .%6 .E8 .%8 .El .g502jg ' ' 'g5 .16 O CI 2 .24 3 7 =19 ,140' -.023 C Be Mg Zn Cd Li Ge Au Mn Ag Pb Co Ni Cu Fe Cr (b) Fig. 10 Measured ionization energies for varies impurities in (a) Si and (b) GaAs. Levels below the gap center are measured from E , Levels above the gap center are measured from E,. Solid bars represent donor levels and hollow boxes represent acceptor levels. (After Refs. 29,31, w 34, and 35.) 24 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS--A REVIEW Fig. 11 Schematic band diagram, density of states, Fermi-Dirac distribution, and carrier concentrations for (a) intrinsic, (b) n-type, and (c)p-type semiconductors at thermal equilibrium. Note that pn = n? for all three cases. - E C - E F 7-) Ncexp(- ND 1 +2exp[(EF-ED)lkT] Thus for a set of given N,, ED,N,, and T, the Fermi level EF can be uniquely determined implicitly. Knowing Ep the carrier concentrations n can be calculated. Equation 38 can also be solved graphically. In Fig. 12, the values of n and NA are plotted as a function of Ep Where the two curves meet determines the position of Ep 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 25 Without solving for Eq. 38, it can be shown that for No >> YiN&xp[-(EcED)lkT] >> NA,the electron concentration can be approximated by5 For compensated n-type material (No >NA) with nonnegligible acceptor concentration, when NA >> ?4N&xp[4Ec - EJkT], the approximate expression for the electron density is then Figure 13 shows a typical example, where n is plotted as a function of the reciprocal temperature. At high temperatures we have the intrinsic range since n z p = ni >>No. At medium temperatures, n = N o . At very low temperatures most impurities are frozen out and the slope is given by either Eq. 39 or Eq. 40, depending on the compensation conditions. The electron density, however, remains essentially constant over a wide range of temperatures (-100 to 500 K). Figure 14 shows the Fermi level for Si and GaAs as a hnction of temperature and impurity concentration, as well as the dependence of the bandgap on temperature (see Fig. 6). At relatively high temperatures, most donors and acceptors are ionized, so the neutrality condition can be approximated by n+NA = p+ND. (41) Equations 29 and 41 can be combined to give the concentrations of electrons and holes. In an n-type semiconductor where N D > NA: n,, = -21[(ND-NA)+.J(ND-NA)2+4nf] The Fermi level can be obtained from ’( ) E C - EF E F - Ei n,, = ND = N ex - - kT = n i e x p ( T ) (44) Similarly, the carrier concentrations in a p-type semiconductor (NA >N o ) are given by = -1[ ( N A - N D ) +, / ( N A - N D ) 2 + 4 n f ] PPO 2 1019 - Si (300 K) NC n-type with N, = 10l6 1018 - p 1017 - .u r b109 I I I I 0.2 0.4 ,E)20.6 II II EOll I ED2 EL^^^ ' I I , , I 0.8 1.0 E , EV EF (ev) Fig. 12 Graphical method to determine the Fermi energy level EF and electron concentration n, when ionization is not complete. Examples with two different values of impurity levels ED are shown. 500 10001 300 200 1017 E I Intrinsic range T (K) 100 75 ,. Si A1 - 1A15 CX 1015 1 Fig. 13 Electron density as a function of temperature for a Si sample with donor impurity concentration of 1015~ r n - ~(A.fter Ref. 5.) 26 1.4 CARRIER CONCENTRATION AT THERMAL EQUILIBRIUM 27 0.8 0.6 EC E, -4 -0.4 EV -0.6 0 100 200 300 400 500 600 T (K) 1.o 0.8 0.6 0.4 ?v o.2 rr- 0 rr“ -0.2 -0.4 -0.6 -0.8 -1.0 0 100 200 300 400 500 600 T (K) Fig. 14 Fermi level for (a) Si and (b) GaAs as a function of temperature and impurity concentration. The dependence of the bandgap on temperature is also shown. (After Ref. 37.) and ( ppo= NA = Nvexp - E- F -kETV = Ei - EF niexp(47( ) y) In the formulas above, the subscripts n andp refer to the type of semiconductors, and the subscript ‘‘0”refers to the thermal equilibrium condition. For n-type semiconductors the electron is referred to as the majority carrier and the hole as the minority carrier, since the electron concentration is the larger of the two. The roles are reversed for p-type semiconductors. 28 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 1.5 CARRIER-TRANSPORT PHENOMENA 1.5.1 Drift and Mobility At low electric fields, the driR velocity vd is proportional to the electric field strength g and the proportionality constant is defined as the mobility p in cm2N-s,or vd = ,Ldg. (48) For nonpolar semiconductors, such as Ge and Si, the presence of acoustic phonons (see Section 1.6.1) and ionized impurities results in carrier scattering that significantly affects the mobility. The mobility from interaction with acoustic phonon of the lattice, p,, is given by38 where C, is the average longitudinal elastic constant of the semiconductor,Edsthe displacement of the band edge per unit dilation of the lattice, and m; the conductivity effective mass. From Eq. 49 mobility decreases with the temperature and with the effective mass. The mobility from ionized impurities pican be described by39 where NI is the ionized impurity density. The mobility is expected to decrease with the effective mass but to increase with the temperature because carriers with higher thermal velocity are less deflected by Coulomb scattering. Note the common dependence of the two scattering events on the effective mass but opposite dependence on temperature. The combined mobility, which includes the two mechanisms above, is given by the Matthiessen rule In addition to the scattering mechanisms discussed above, other mechanisms also affect the actual mobility. For example, (1) the intravalley scattering in which an electron is scattered within an energy ellipsoid (Fig. 5) and only long-wavelength phonons (acoustic phonons) are involved; and (2) the intervalley scattering in which an electron is scattered from the vicinity of one minimum to another minimum and an energetic phonon (optical phonon) is involved. For polar semiconductors such as GaAs, polar-optical-phonon scattering is significant. Qualitatively, since mobility is controlled by scattering, it can also be related to the mean free time zm or mean free path Amby The last term uses the relationship 1.5 CARRIER-TRANSPORT PHENOMENA 29 ‘ i n = ‘th‘m (53) where uth is the thermal velocity given by For multiple scattering mechanisms, the effective mean free time is derived from the individual mean free times of scattering events by -1 = -+1 -+..1. (55) ‘m ‘ml ‘m2 It can be seen that Eqs. 51 and 55 are equivalent. Figure 15 shows the measured mobilities of Si and GaAs versus impurity concen- trations at room temperature. As the impurity concentration increases (at room temperature most shallow impurities are ionized) the mobility decreases, as predicted by Eq. 50. Also for larger m*,p decreases; thus for a given impurity concentration the electron mobilities for these semiconductors are larger than the hole mobilities (Appendixes F and G list the effective masses). Figure 16 shows the temperature effect on mobility for n-type andp-type silicon samples. For lower impurity concentrations the mobility is limited by phonon scattering and it decreases with temperature as predicted by Eq. 49. The measured slopes, however, are different from -312 because of other scattering mechanisms. For these 104 .h v) >I Iv -g.- 103 I 102 1014 1015 1016 1017 1018 1019 Impurity concentration ( ~ m - ~ ) 102 1014 1015 10’6 1017 10’8 1019 Impurity concentration (cm”) Fig. 15 Drift mobility of (a) Si (After Ref. 40.) and (b) GaAs at 300 K vs. impurity concentration (after Ref. 11). 30 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW Temperature (K) Fig. 16 Mobility of electrons and holes in Si as a function of temperature. (After Ref. 41.) pure materials, near room temperature, the mobility vanes as T2.4a2nd T2.2fo0r nandp-type Si, respectively; and as and T2.f'or n- andp-type GaAs (not shown), respectively. The mobilities discussed above are the conductivity mobilities, which have been shown to be equal to the drift m ~ b i l i t i e sT. ~he~y are, however, different from but related to the Hall mobilities considered in the next section. 1.5.2 Resistivity and Hall Effect For semiconductors with both electrons and holes as carriers, the drift current under an applied field is given by J = crZ? = q(Pnn + P ~ P ) (56) where c i s the conductance 0 = -1 = q(Pnn+PpP) (57) P and p is the resistivity. If n >>p, as in n-type semiconductors, p = - 1 9Pnn and 1.5 CARRIER-TRANSPORT PHENOMENA 31 The most-common method for measuring resistivity is the four-point probe method (insert, Fig. 17),42,4A3 small constant current is passed through the outer two probes and the voltage is measured between the inner two probes. For a thin wafer with thickness Wmuch smaller than either a or d, the sheet resistance R, is given by R , = -IV. C F QIo (60) where CF is the correction factor shown in Fig. 17. The resistivity is then p = ROW Q-cm. (61) In the limit when d >> S, where S is the probe spacing, the correction factor becomes d n 2 (= 4.54). Figure 18a shows the measured resistivity (at 300 K) as a function of the impurity concentration (n-type phosphorus and p-type boron) for silicon. Resistivity is not a linear function of concentration because mobility is not constant and usually decreases with increasing concentration. Figure 18b shows the measured resistivities for GaAs. We can obtain the impurity concentration of a semiconductor if its resistivity is known and vice versa. Note that the impurity concentration may be different from the carrier concentration because of incomplete ionization. For example, in a p-type silicon with 1017~ m g-all~ium acceptor impurities, unionized acceptors at room temperature make up about 23% (from Eq. 35, Figs. 10 and 14); in other words, the carrier concentration is only 7 . 7 ~ 1 0~' ~m - ~ . TI I I- a -I R,= $ C F (nlo) p=R,W (a-cm) Correction factor CF Fig. 17 Correction factor for measurement of resistivity using a four-point probe. (After Ref. 42.) h cE .0- ." .c- d Impurity concentration (cm-3) Fig. 18 Resistivity vs. impurity concentration at 300 K for (a) silicon (after Ref. 40) and (b) GaAs (after Ref. 35). 32 1.5 CARRIER-TRANSPORT PHENOMENA 33 Hall Effect. Measurement of the resistivity only gives the product of the mobility and carrier concentration. To measure each parameter directly, the most-common method uses the Hall effect. The Hall effect is named after the scientist who made the discovery in 1879.44Even today it remains one of the most fascinating phenomena and is both fundamentally interesting and practical. Examples include the recent study of the fractional quantum Hall effect and the applications as magnetic-field sensors. The Hall effect is used in common practice to measure certain properties of semiconductors: namely, the carrier concentration (even down to a low level of 10l2~ m - ~th)e, mobility, and the type (n orp). It is an important analytical tool since a simple conductance measurement can only give the product of concentration and mobility, and the type remains unknown. Figure 19 shows the basic setup where an electric field is applied along the x-axis and a magnetic field is applied along the z-axis.45Consider a p-type sample. The Lorentz force exerts an average downward force on the holes Lorentz force = qv, x Bz, (62) and the downward-directed current causes a piling up of holes at the bottom side of the sample, which in turn gives rise to an electric field gYSince there is no net current along the y-direction in the steady state, the electric field along the y-axis (Hall field) balances exactly the Lorentz force such that the carriers travel in a path parallel to the applied field gX.(For n-type material, electrons also pile up at the bottom surface, setting up a voltage of opposite polarity.) The carrier velocity v is related to the current density by J, = q v g . (63) Since for each carrier the Lorentz force must be equal to the force exerted by the Hall field, 9 q J = 9VX%I (64) v, Fig. 19 Basic setup to measure carrier concentration using the Hall effect. 34 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW this Hall voltage can be measured externally and is given by v, = g y w= J-.XBZW 4P When scattering is taken into account, the Hall voltage becomes VH = RHJxB,W (66) where RH is the Hall coefficient and is given by with a Hall factor Thus, the carrier concentration and carrier type (electrons or holes from the polarity of the Hall voltage) can be obtained directly from the Hall measurement, provided that one type of carrier dominates and rH is known. Equation 67a or b also assumes conduction by a single type of carrier. A moregeneral solution is described by5 It can be seen in Eq. 69 that the sign of R, and thus V, reveals the majority type of the semiconductor sample. The Hall mobility p, is defined as the product of the Hall coefficient and conductivity: pH = lRHl o. (70) The Hall mobility should be distinguished from the drift mobility p,, (or pp)as given in Eq. 59 which does not contain the Hall factor rW Their relationship is given by pH = rHP. (71) The parameter ,z for the Hall factor is the mean free time between carrier collisions, which depends on the carrier energy. For example, for semiconductors with spherical constant-energysurfaces, ,z cc E-lt2 for phonon scattering and ,z cc E3I2for ionized impurity scattering. In general, ,z = C,E-”, (72) where C, and s are constants. From Boltzmann distribution for nondegenerate semiconductors, the average value of the nth power of ,z is 1.5 CARRIER-TRANSPORT PHENOMENA 35 j[-00 ((z;)GI>= GE3I2exp(- ;kL)Td)Ed/E / r E 3j"fE23eIx2epx(p-(- gkLT) d E, (73) J O0 0 so that using the general form of,,z we obtain and C,(kT)-T(;-8) (r,> = (75) U$) where r(n)is the gamma function defined as Ir(n)= xn-le-xdx. (76) [r(1/2) = &.] From the expression above we obtain rH= 3d8 = 1.18 for phonon scattering and rH= 3 15d512 = 1.93 for ionized-impurity scattering. In general rHlies in the range of 1-2. At very high magnetic fields, it approaches a value slightly below unity. In the preceding discussion the applied magnetic field is assumed to be small enough that there is no change in the resistivity of the sample. However, under strong magnetic fields, a significant increase in the resistivity is observed, the so-called magnetoresistance effect, resulting from carriers travelling in a path that deviates from the applied electric field. For spherical-energy surfaces the ratio of the incremental resistivity to the bulk resistivity at zero magnetic field is given by5 9: . (77) The ratio is proportional to the square of the magnetic field component perpendicular to the direction of the current flow. For n >>p,(ApIpo)K p;BA,2.A similar result can be obtained for the casep >> n. 1.5.3 High-Field Properties In the preceding sections we considered the effect of low electric field on the transport of carriers in semiconductors. In this section we briefly consider some special effects and properties of semiconductors when the electric field is increased to moderate and high levels. As discussed in Section 1.5.1, at low electric fields the drift velocity in a semiconductor is proportional to the field and the proportionality constant is the mobility that 36 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW is independent of the electric field. When the fields are sufficiently large, however, nonlinearities in mobility and, in some cases, saturation of drift velocity are observed. At still larger fields, impact ionization occurs. First, we consider the nonlinear mobility. At thermal equilibrium the carriers both emit and absorb phonons and the net rate of exchange of energy is zero. The energy distribution at thermal equilibrium is Maxwellian. In the presence of an electric field the carriers acquire energy from the field and lose it to phonons by emitting more phonons than are absorbed. At moderately high fields, the most frequent scattering events involve in the emission of acoustic phonons. Thus, the carriers on average acquire more energy than they have at thermal equilibrium. As the field increases, the average energy of the carriers also increases and they acquire an effective temperature T, that is higher than the lattice temperature T. Balancing the rate at which energy is transferred from the field to the carriers by an equal rate of energy loss to the lattice, we obtain from the rate equation, for Ge and Si (semiconductors without transferred-electron e f f e ~ t ) : ~ and where ,L+, is the low-field mobility, and cs the velocity of sound. For moderate field me. strength when p&5 is comparable to c, the carrier velocity vd starts to deviate from being linearly dependent on the applied field, by a factor of Finally at suffi- ciently high fields, carriers start to interact with optical phonons and Eq. 78 is no longer accurate. The drift velocities for Ge and Si become less and less dependent on the applied field and approach a saturation velocity where Ep is the optical-phonon energy (listed in Appendix G). To eliminate the discontinuity between the regimes covered by Eqs. 78-80, a single empirical formula is often used to describe the whole range, from low-field drift velocity to velocity ~ a t u r a t i o n : ~ ~ vd = PO 8 [1 + (Pog/vs)c'I llC2' (81) The constant C, has a value near two for electrons and one for holes, and it is a func- tion of temperature. The velocity-field relationship is more complicated for GaAs, and we must con- sider its band structure (Fig. 4). A high-mobility valley (p = 4,000 to 8,000 cm2N-s) is located at the Brillouin zone center, and a low-mobility satellite valley ( p = 1.5 CARRIER-TRANSPORT PHENOMENA 37 100 cm2/V-s)along the (11l)-axe~,4ab~out 0.3 eV higher in energy. The difference in mobility is due to the different electron effective masses (Eq. 52): 0.063mo in the lower valley and about 0.55m0in the upper valley. As the field increases, the electrons in the lower valley can be excited to the normally unoccupied upper valley, resulting in a differential negative resistance in GaAs. The intervalley transfer mechanism, called transferred-electron effect, and the velocity-field relationship are considered in more detail in Chapter 10. Figure 20a shows the measured room-temperature drift velocities versus electric field for high-purity (low impurity concentration) Si and GaAs. For high-level impurity dopings, the drift velocity or mobility at low fields is decreased due to impurity scattering. However, the velocity at high fields is essentially independent of impurity dopings, and it approaches a saturation value.52For Si the saturation velocities v, for electrons and holes are about 1x lo7 c d s . For GaAs a wide range of negative differential mobility exists for fields above 3x lo3V/cm, and the high-field saturation velocity approaches 6x lo6 cm/s. Figure 20b shows the temperature dependence of electron saturation velocity. As the temperature increases, the saturation velocities for both Si and GaAs decrease. Up to now, the drift velocities discussed are for steady-state condition where carriers go through enough scattering events to get to their equilibrium values. In modem devices, the critical dimension where carriers transit across becomes smaller and smaller. When this dimension becomes comparable to or shorter than the mean free path, ballistic transport is said to occur before carriers start to be scattered. Figure 2 1 shows the drift velocity as a function of distance. Without scattering, the velocity increases with time (and distance) according to FZ qgt/m*.At high fields, drift velocity can attain a higher value momentarily than that at steady state, within a short space (of the order of mean free path) and time (of the order of mean free time). This phenomenon is called velocity overshoot. (In literature, confusion might arise when the peak velocity of GaAs shown in Fig. 20a-the transferred-electron effect, is also called velocity overshoot.) At low fields, the acceleration of velocity is lower and when scattering starts to occur, the attained velocity is not that high and so velocity overshoot does not occur. Note that this shape of velocity overshoot is similar to that in the transferred-electron effect but the abscissa here is distance (or time) while that in the latter is electric field. We next consider impact ionization. When the electric field in a semiconductor is increased above a certain value, the carriers gain enough energy to excite electronhole pairs by a process called impact ionization. The threshold energy obviously has to be larger than the bandgap. This multiplication process is characterized by an ionization rate a defined as the number of electron-hole pairs generated by a carrier per unit distance traveled (Fig. 22). So for a primary carrier of electron traveling with a velocity v,, an = 1 dn n--d(tv,) -- 1 dn - nu,-dt ’ 38 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS--A REVIEW 1.4 1 I I - 1.2 - - - us = $ 1 +0.8exp(T/600K) 5 1.0 - v 2- - -'Y xg 0.8 - - 0 - E .4i 0.6 - - c E 3 - 0.4 - - 0.2 10 I , 100 - ,I I /I, 1000 Considering both electrons and holes, the generation rate at any fixed location is given by + @ = = annu, + appvp dt dt (83) 44 1.5 CARRIER-TRANSPORT PHENOMENA 39 1.5 5 kV/cm 'b ' 0.02 ' O.b4 ' 0.06 ' 0.b8 ' O.\O Distance (pm) Fig. 21 Velocity overshoot in ultrashort distance. Similar behavior can be observed when the abscissa of distance is replaced with time. Example is for silicon. (After Ref. 53.) Conversely, at any given time, the carrier density or current varies with distance and can be shown to be: "d- J = a,,J,, + apJ,, dx (844 dJ 9 = -a,,J,-a,J,. dx The total current (J,, + J,) remains constant over distance and dJ,,l& = - dJ&. The ionization rates a,, and a, are strongly dependent on the electric field. A physical expression for the ionization rate is given by54 Fig. 22 Multiplication of electrons and holes from impact ionization, due to electrons (a,) in this example (ap= 0). 40 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW where EI is the high-field effectiveionizationthreshold energy, and g p gP,and g1are threshold fields for carriers to overcome the decelerating effects of thermal, opticalphonon, and ionization scattering, respectively. For Si, the value of EI is found to be 3.6 eV for electronsand 5.0 eV for holes. Over a limited field range, Equation 85 can be reduced to or Figure 23a shows the experimentalresults of the ionization rates for Ge, Si, Sic, and GaN. Figure 23b shows the measured ionization rates of GaAs and a few other binary and ternary compounds. These results are obtained by using photomultiplication measurements on p-n junctions. Note that for certain semiconductors, such as GaAs, the ionization rate is a hnction of crystal orientation. There is also a general trend that the ionization rate decreases with increasing bandgap. It is for this reason that materials of higher bandgaps generally yield higher breakdown voltage. Note that Eq. 86 is applicable to most semiconductors shown in Fig. 23, except GaAs and Gap, for which Eq. 87 is applicable. At a given electric field, the ionizationrate decreaseswith increasingtemperature. Figure 24 shows the theoretical predicted electron ionization rates in silicon as an example, together with the experimentalresults at three different temperatures. 1.5.4 Recombination, Generation, and Carrier Lifetimes Whenever the thermal-equilibrium condition of a semiconductor system is disturbed (i.e., pn f n’ ), processes exist to restore the system to equilibrium (i.e., pn = n’ ). These processes are recombination when pn > n’ and thermal generation when pn < n’ . Figure 25a illustrates the band-to-band electron-hole recombination. The energy of an electron in transition from the conduction band to the valence band is conserved by emission of a photon (radiative process) or by transfer of the energy to another free electron or hole (Auger process). The former process is the inverse of direct optical absorption,and the latter is the inverse of impact ionization. Band-to-band transitions are more probable for direct-bandgap semiconductors which are more common among 111-V compounds. For this type of transition, the recombination rate is proportional to the product of electron and hole concentrations, given by Re = R , g n . (88) The term Re,, calledthe recombination coeficient, is related to the thermal generation rate G, by 106 Electrons a, Holes ap GaN \ (3.36 eV) I Fig. 23 Ionization ratesaf300 K versus reciprocal electric field for Si, GaAs, and some IV-IV and 111-V compound semiconductors. (After Refs. 55-65.) \ T = 100K Experimental o l00K 213K A 300K Theoretical - - - 100K A Fig. 24 Electron ionization rate versus reciprocal electric field in Si for four temperatures. (After Ref. 66.) 41 42 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 3 j3- 3 1 Auger process EC Photon emission 1 (radiative) Augerprocess E" (hole) oT Ec 0 Et EV Fig. 25 Recombination processes (the reverse are generation processes). (a) Band-to-band recombination.Energy is exchanged to a radiative or Auger process. (b) Recombination through single-level traps (nonradiative). Re, = -G.th n: (89) Re, is a function of temperature and is also dependent on the band structure of the semiconductor. A direct-bandgap semiconductor, being more efficient in band-to- band transitions, has a much larger R, (= 1O-Io cm3/s)than an indirect-bandgap semi- conductor (= l W 5cm3/s).In thermal equilibrium, sincepn = n;, Re= Gthand the net transition rate U (= Re - Gth)equals zero. Under low-level injection, defined as the case where the excess carriers Ap = An are fewer than the majority carriers, for an n-type materialp, =pno+ Ap and n, = ND, the net transition rate is given by u = Re- G,h = R&n - n?> = RecApND= & (90) zP where the carrier lifetime for holes z =- 1 P and in p-type material, z, = -. 1 However, in indirect-bandgap semiconductors such as Si and Ge, the dominant transitions are indirect recombinationlgeneration via bulk traps, of density Nt and energy E, present within the bandgap (Fig. 25b). The single-level recombination can be described by two processes-electron capture and hole capture. The net transition rate can be described by the Shockley-Read-Hall statistics6749as 1.5 CARRIER-TRANSPORT PHENOMENA 43 where onand opare the electron and hole capture cross sections, respectively. Without deriving this equation, some qualitative observations can be made on the final form. First, the net transition rate is proportional to pn - n?, similar to Eq. 90, and the sign determines whether there is net recombination or generation. Second, U is maximized when El = Ei, indicating for an energy spectrum of bulk traps, only those near the mid-gap are effective recombinatiodgeneration centers. Considering only these traps, Eq. 92 is reduced to a,a,v,,Nl(pn - n:) U = an(n+ ni)+ opO,+ ni) (93) Again for low-level injection in n-type semiconductors, the net recombination rate becomes U = onapvthNt[(Pno + Ap>n- an' where r =-. 1 P apvthNi Similarly for ap-type semiconductor, the electron lifetime is given by (95a) As expected, the lifetime arising from indirect transitions is inversely proportional to the trap density N,, while in the previous case, the lifetime from direct transitions is inversely proportional to the doping concentration (Eqs. 91a and 91b). For multiple-level traps, the recombination processes have gross qualitative features that are similar to those of the single-level case. However, the behavioral details are different, particularly in the high-level injection condition (i.e., where An = Ap approaches the majority-carrier concentration), where the asymptotic lifetime is an average of the lifetimes associated with all the positively charged, negatively charged, and neutral trapping levels. For high-level injection (An = Ap > n andp), the carrier lifetime for band-to-band recombination becomes 1 r r l = r = R- ,,An The lifetime resulting from traps can be derived from Eq. 93 to be 44 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS--A REVIEW Comparing Eq. 97 to Eqs. 95a and 95b, the lifetime is actually higher with high-level injection. It is interesting to note that the lifetime due to band-to-band recombination decreases with injection level, while that due to trap recombination increases with injection level. Equations 95a and 95b have been verified experimentally by using solid-state diffusion and high-energy radiation. Many impurities have energy levels close to the middle of the bandgap (Fig. 10). These impurities are efficient recombination centers. A typical example is gold in silicon;70the minority-carrier lifetime decreases linearly with the gold concentration over the range of 1014to 1017~ m - w~h,ere zdecreases from about 2 ~ 1 s0to ~2 ~ 1 O s-.~This effect is sometimes advantageous, as in some high-speed applications when a short lifetime to reduce the charge storage time is a desirable feature. Another method of shortening the minority-carrier lifetime is highenergy-particle irradiation, which causes displacement of host atoms and damage to the lattice. These, in turn, introduce energy levels in the bandgap. For example, electron irradiation in Si gives rise to an acceptor level at 0.4 eV above the valence band and a donor level at 0.36 eV below the conduction band. Also neutron irradiation creates an acceptor level at 0.56 eV; and deuteron irradiation gives rise to an interstitial state with an energy level 0.25 eV above the valence band. Similar results are obtained for Ge, GaAs, and other semiconductors. Unlike the solid-state diffusion, the radiation-induced trapping centers may be annealed out at relatively low temperatures. When carriers are below their thermal-equilibrium values, i.e., pn < n? , generation of carriers rather than recombination of excess carriers will occur. The generation rate can be found by starting with Eq. 93, where the generation carrier lifetime zg is equal to Depending on the electron and hole concentrations, the generation lifetime can be much longer than the recombination lifetime and has a minimum value of roughly twice that of the recombination lifetime, when both n a n d p are much smaller than ni. The minority-carrier lifetime z has generally been measured using the photoconductive (PC) effect71or the photoelectromagnetic (PEM) effect7*.The basic equation for the PC effect is given by 1.5 CARRIER-TRANSPORT PHENOMENA 45 where Jpcis the incremental current density as a result of illumination with generation rate G,, and 25’ is the applied electric field along the sample. The quantity An is the incremental carrier density or the number of electron-hole pairs per volume created by the illumination, which equals the product of the generation rate Geand the lifetime z, or An = zGe.For the PEM effect we measure the short-circuit current, which appears when a constant magnetic field gZis applied perpendicular to the direction of incoming radiation. The current density is given by where D and Ld[= (Dz)”~a]re the diffusion coefficient and the diffusion length, to be discussed in the next section. Another approach to measure the carrier lifetime will be discussed in Section 1.8.2. 1.5.5 Diffusion In the preceding section the excess carriers are uniform in space. In this section, we discuss the situations where excess carriers are introduced locally, causing a condi- tion of nonuniform carriers. Examples are local injection of carriers from a junction, and nonuniform illumination. Whenever there exists a gradient of carrier concentra- tion, a process of diffusion occurs by which the carriers migrate from the region of high concentration toward the region of low concentration, to drive the system toward a state of uniformity. This flow or flux of carriers, taking electrons as an example, is governed by the Fick’s law, ?Ix dAn = - D,-,dx and is proportional to the concentration gradient. The proportionality constant is called the diffusion coefficient or diffusivity D,. This flux of carriers constitutes a diffusion current, given by J , = qDnd-d,Axn (103a) and J =-qD d A P P dx (103b) Physically, diffusion is due to random thermal motion of carriers as well as scattering. Because of this, we have D = v~~z,. ( 104) 46 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW One also expects certain relationship between the diffusion coefficient and mobility. To derive such a relationship, we consider an n-type semiconductor with nonuniform doping concentration but without an external applied field. The zero net current necessitates that the drift current exactly balances the diffusion current, qn,un8 = - qDnd--n. & (105) In this case, the electric field is created by the nonuniform doping (Z? = dE,/q&, and EF is constant for equilibrium). Using Eq. 21 for n, we obtain - -3En kT ' Substituting this into Eq. 105 will give the relationship (107a) Similarly forp-type semiconductor, one can derive (107b) These are known as the Einstein relation (valid for nondegenerate semiconductors). At 300 K, kTlq = 0.0259 V, and values of D are readily obtainable from the mobility results shown in Fig. 15. Another parameter closely related to diffusion is the diffusion length, L,= JIG. (108) In common diffusion problems arising from some fixed injection source as a boundary condition, the resultant concentration profile is exponential in nature with distance, with a characteristic length of L,. This difhsion length can also be viewed as the distance carriers can diffuse in a carrier lifetime before they are annihilated. 1.5.6 Thermionic Emission Another current conduction mechanism is thermionic emission. It is a majoritycarrier current and is always associated with a potential barrier. Note that the critical parameter is the barrier height, not the shape of the barrier. The most-common device is the Schottky-barrierdiode or metal-semiconductorjunction (see Chapter 3). Referring to Fig. 26, for the thermionic emission to be the controlling mechanism, the criterion is that collision or the drift-diffusion process within the barrier layer to be negligible. Equivalently, the barrier width has to be narrower than the mean free path, or in the case of a triangular barrier, the slope of the barrier be reasonably steep such that a drop in kT in energy is within the mean free path. In addition, after the carriers are injected over the barrier, the diffusion current in that region must not be the lim- 1.5 CARRIER-TRANSPORT PHENOMENA 47 . .. ........... .. ..... I LI, / Ec EF n-Semiconductor Barrier Metal or n-Semiconductor Fig. 26 Energy-band diagram showing thermionic emission of electrons over the barrier. Note that the shape of the barrier (shown as rectangular) does not matter. iting factor. Therefore, the region behind the barrier must be another n-type semiconductor or a metal layer. Due to Fermi-Dirac statistics, the density of electrons (for n-type substrate) decreases exponentially as a function of their energy above the conduction band edge. At any finite (nonzero) temperature, the carrier density at any finite energy is not zero. Of special interest here is the integrated number of carriers above the barrier height. This portion of the thermally generated carriers are no longer confined by the barrier so they contribute to the thermionic-emission current. The total electron current over the barrier is given by (see Chapter 3) where q& is the barrier height, and A~ = 4xqm*k2 h3 is called the effective Richardson constant and is a function of the effective mass. The A* can be further modified by quantum-mechanical tunneling and reflection. 1.5.7 Tunneling Tunneling is a quantum-mechanical phenomenon. In classical mechanics, carriers are completely confined by the potential walls. Only those carriers with excess energy higher than the barriers can escape, as in the case of thermionic emission discussed above. In quantum mechanics, an electron can be represented by its wavefunction. The wavefunction does not terminate abruptly on a wall of finite potential height and it can penetrate into and through the barrier (Fig. 27). The probability of electron tunneling through a barrier of finite height and width is thus not zero. To calculate the tunneling probability, the wavefunction ry has to be determined from the Schrodinger equation 9,X [ E - U(x)]ry = 0 dx2 h2 48 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW Region-A -1-I \ I \ I I1 I\ I x1 x2 Fig. 27 V.-vefunctions showing electron tunneling through a rectangular barrier. In the case of a simple rectangular barrier of height Uoand width W, ry has a general form of exp(*ikx) where k = , , / q ) / h . Note that for tunneling, the energy E is below the barrier U, so that the term within the square root is negative and k is imaginary. The solution of the wavefunctions and the tunneling probability are calculated to be For more complicated barrier shapes, simplification of the Schrodinger equation is made by the WKB (Wentzel-Kramers-Brillouin) approximation if the potential U(x) does not vary rapidly. The wavefunction now has a general form of expjik(x)dx. The tunneling probability can be calculated by Together with known tunneling probability, the tunneling current J, can be calculated from the product of the number of available carriers in the originating Region-A (Fig. 27), and the number of empty states in the destination Region-B, where FA, FB,NA, and NBrepresent the Fermi-Dirac distributions and densities of states in the corresponding regions. 1.5 CARRIER-TRANSPORT PHENOMENA 49 1.5.8 Space-Charge Effect The space charge in a semiconductor is determined by both the doping concentrations and the free-carrier concentrations, p = (P-n+ND-NA)q . (115) In the neutral region of a semiconductor, n =No andp = NA,so that the space-charge density is zero. In the vicinity of a junction formed by different materials, dopant types, or doping concentrations, n and p could be smaller or larger than No and NA, respectively. In the depletion approximation, n and p are assumed zero so that the space charge is equal to the majority-carrier doping level. Under bias, the carrier concentrations n and p can be increased beyond their values in equilibrium. When the injected n o r p is larger than its equilibrium value as well as the doping concentration, the space-charge effect is said to occur. The injected carriers thus control the space charge and the electric-field profile. This results in a feedback mechanism where the field drives the current, which in turn sets up the field. The space-charge effect is more common in lightly doped materials, and it can occur outside the depletion region. In the presence of a space-charge effect, if the current is dominated by the drift component of the injected carriers, it is called the space-charge-limited current. Since it is a drift current, it is given by, in the case of electron injection, J = gnu. (1 16) The space charge again is determined by the injected carriers giving rise to the Poisson equation of the form The carrier velocity u is related to the electric field by different functions, depending on the field strength. In the low-field mobility regime, u=pz. (118) In the velocity-saturation regime, velocity usis independent of the field. In the limit of ultra-short sample or time scale, we have the ballistic regime where there is no scattering, and u= From Eqs. 116-1 19, the space-charge-limited current in the mobility regime (the Mott-Gurney law) can be solved to be (see Vol. 4 of Ref. 4) in the velocity-saturation regime v J = 2- &,U, L2 ’ 50 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW and in the ballistic regime (the Child-Langmuir law) Here L is the length of the sample in the direction of the current flow. Note that the voltage dependence is different in these regimes. 1.6 PHONON, OPTICAL, AND THERMAL PROPERTIES In the preceding section we considered different carrier transport mechanisms in semiconductors. In this section we briefly consider other effects and properties of semiconductorsthat are important to the operation of semiconductor devices. 1.6.1 Phonon Spectra Phonons are quanta of lattice vibrations, mainly resulting from the lattice thermal energy. Similar to photons and electrons, they have characteristic frequencies (or energy) and wave numbers (momentum or wavelengths). It is known that, as a demonstration in a one-dimensional lattice, with only nearest-neighbor coupling and two different masses ml and m2 placed alternately,the frequencies of oscillation are given by3 where afis the force constant of the Hooke's law, kphthe phonon wave number, and a the lattice spacing. The frequency v- is proportional to k near kph= 0. This branch is the acoustic branch, because it is the long-wavelengthpvhi.bration of the lattice and the velocity wlk is near that of sound in such a medium. The frequency v+ tends to be a constant = [2abl/m1+ l/m2)]112as kphapproaches zero. This branch, separated con- siderably from the acoustic mode, is the optical branch, because the frequency v+ is generally in the optical range. For the acoustic mode the two sublattices of the atoms with different masses move in the same direction, whereas for the optical mode they move in opposite directions. The total number of acoustic modes is equal to the dimension times the number of atoms per cell. For a realistic three-dimensional lattice with one atom per primitive cell, such as a simple cubic, body-centered, or face-centered cubic lattice, only three acoustic modes exist. For a three-dimensional lattice with two atoms per primitive cell, such as Si and GaAs, three acoustic modes and three optical modes exist. Longitudinally polarized modes are modes with the displacement vectors of each atom along the direction of the wave vector; thus we have one longitudinal acoustic mode (LA) and one longitudinal optical mode (LO). Modes with atoms moving in the planes normal to the wave vector are called transversely polarized modes. We have two transverse acoustic modes (TA) and two transverse optical modes (TO). 1.6 PHONON, OPTICAL, AND THERMAL PROPERTIES 51 Figure 28 shows the measured results for Si and GaAs in one of the crystal directions. The range ofk,, = f d de~fines the Brillouin zone outside which the frequencykphrelationship repeats itself. Note that at small values of kph,for both LA and TA modes, the energies (or frequencies) are proportional to kph.The longitudinal optical phonon energy at kph= 0 is the first-order Raman scattering energy. Their values are 0.063 eV for Si and 0.035 eV for GaAs. Appendix G lists these results, together with other important properties. 1.6.2 Optical Properties Optical measurement constitutes the most-important means of determining the band structures of semiconductors. Photon-induced electronic transitions can occur between different bands, which lead to the determination of the energy bandgap, or within a single band such as the free-carrier absorption. Optical measurements can also be used to study lattice vibrations (phonons). The optical properties of semiconductor are characterized by the complex refractive index, fi = n,- ik,. (124) The real part of the refractive index n, determines the propagation velocity (v and wavelength A) in the medium (assuming ambient is a vacuum having wavelength A,,) The imaginary part k,, called the extinction coefficient, determines the absorption coefficient 16 I I 14 GaAs 0.04 U 2 b4 2 0.03 $ 0.02 L5 0.01 r X kph (4 (b) Fig. 28 Measured phonon spectra in (a) Si (After Ref. 73.) and (b) GaAs (After Ref. 74.). TO and LO stand for transverse and longitudinal optical modes, and TA and LA for transverse and longitudinal acoustic modes. 52 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW In semiconductors, the absorption coefficient is a strong function of the wavelength or photon energy. Near the absorption edge, the absorption coefficient can be expressed as5 a K ( h v- E,)’ (127) where h v is the photon energy and y is a constant. There exist two types of band-toband transitions: allowed and forbidden. (Forbidden transitions take into account the small but finite momentum of photons and are much less probable.) For directbandgap materials, transitions mostly occur between two bands of the same k value, as transitions (a) and (b) in Fig. 29. While allowed direct transitions can occur in all k values, forbidden direct transitions can only occur at k # 0. In the one-electron approximation, y equals 1/2 and 3/2 for allowed and forbidden direct transitions, respectively. Note that for k = 0 at which the bandgap is defined, only allowed transition (y= 1/2) occurs and thus it is used in determining the bandgap experimentally. For indirect transitions [transition (c) in Fig. 291, phonons are involved in order to conserve momentum. In these transitions, phonons (with energy E p ) are either absorbed or emitted, and the absorption coefficient is modified to a K ( h v- EgkEP)’ . (128) Here the constant yequals 2 and 3 for allowed and forbidden indirect transitions, respectively. In addition, increased absorption peaks and steps can be due to formation of excitons, which are bound electron-hole pairs with energy levels within the bands that move through the crystal lattice as a unit. Near the absorption edge, where the values of (Eg- h v)become comparable with the binding energy of an exciton, the Coulomb interaction between the free electron and hole must be taken into account. The photon energy required for absorption is lowered by this binding energy. For h v 7 Eg the Fig. 29 Optical transitions: (a) allowed and (b) forbidden direct transitions; (c) indirect transition involving phonon emission (upper arrow) and phonon absorption (lower arrow). 1.6 PHONON, OPTICAL, AND THERMAL PROPERTIES 53 absorption merges continuously into the fundamental absorption. When h v>> Eg, higher energy bands participate in the transition processes, and complicated band structures are reflected in the absorption coefficient. Figure 30 plots the experimental absorption coefficients anear and above the fundamental absorption edge (band-to-band transition) for Si and GaAs. The shift of the curves toward higher photon energies at lower temperature is associated with the temperature dependence of the bandgap (Fig. 6). An a of lo4cm-' means that 63% of light will be absorbed in one micron of semiconductor. When light passes through a semiconductor, absorption of light and generation of electron-hole pairs (G,) occur, and the light intensity Popdiminishes with distance according to dPOP(X)= - aPop(x) = G,hv. dx Solution of the above gives an exponential decay of intensity Pop(x) = P,(1 -R)exp(- ax) (130) where Pois the external incident light intensity and R is the reflection of the ambientsemiconductor interface at normal incidence, R = ( 1 - nr)2 + k2 (1 +nr)2+k,2' 107 106 10' 1 h v (eV) Fig. 30 Measured absorption coefficients near and above the fundamental absorption edge for Si and GaAs. (After Refs. 75-78.) 54 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW In a semiconductor sample of thickness Wwhere the product aW is not large, multiple reflectionswill occur between the two interfaces. Summingup all the light components in the backward direction,the total reflection coefficient is calculatedto be R, = R[1+( 1 - R)*exp(- 2 a q 1 -R2exp(- 2 a W ) and the total transmission coefficient is given by T, = (1 -R)2exp(- aw) 1 - R2exp(- 2 a W ) (133) The transmission coefficient T, and the reflection coefficient R, are two important quantities generally measured. By analyzing the Tz-Aor R,-A data at normal incidence, or by making observationson R, or T, for different angles o f incidence,both n, and k, can be obtained and related to the transition energy between bands. 1.6.3 Thermal Properties When a temperature gradient exists in a semiconductorin addition to an applied electric field, the total current density (in one dimension) is5 (134) w h e r e 9 is the thermoelectric power, so named to indicate that for an open-circuit condition the net current is zero and an electric field is generated by the temperature gradient. For a nondegenerate semiconductor with a mean free time between collisions zm cc E-s as discussed previously, the thermoelectric power is given by { } k [i-S+ l n ( ~ ~ / n ) I n P n 5- [ ~ - S - l n ( ~ ~ / P ) I p P p 9= -- 4 nPn +PPp (135) ( k is Boltzmann constant). This equation indicates that the thermoelectric power is negative for n-type semiconductors and positive for p-type semiconductors, a fact often used to determine the conduction type of a semiconductor. The thermoelectric power can also be used to determinethe resistivity and the position of the Fermi level relativeto the band edges.At room temperaturethe thermoelectricpower9 ofp-type silicon increases with resistivity: 1 mV/K for a 0.1 a-cm sample and 1.7 mV/K for a 100 Q-cm sample. Similarresults (except a change of the sign for9) can be obtained for n-type silicon samples. Another important thermal effect is thermal conduction. It is a diffusion type of process where the heat flow Q is driven by the temperature gradient The thermal conductivity K has the major components of phonon (lattice) conduction K~ and mixed free-carrierconduction K M o felectrons and holes, + K = KL K M . (137) 1.6 PHONON, OPTICAL, AND THERMAL PROPERTIES 55 The lattice contribution is carried out by diffusion and scattering of phonons. These scattering events include many types, such as phonon-to-phonon, phonon-to-defects, phonon-to-carriers, boundaries and surfaces, and so on. The overall effect can be interpreted as where C,, is the specific heat, uphthe phonon velocity, and 'zphthe phonon mean free path. The contribution due to mixed carriers, if zm cc E-" holds for both electron and hole scattering, is given by Figure 31 shows the measured thermal conductivity as a function of lattice temperature for Si and GaAs. Appendix G lists the room-temperature values. The contri- 1 quite small, D Fig. 31 Measured thermal conductivity versus temperature for pure Si, GaAs, Sic, GaN, Cu, and diamond (Type 11). (After Refs. 79-83.) 56 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW so the general temperature dependence follows that of K~ and has a inverted V-shape. At low temperatures, the specific heat has a T 3dependence and Kgoes up sharply. At high temperatures, phonon-phonon scattering dominates and /Iph (and K ~ d)rops according to 1/T. Figure 31 also shows the thermal conductivities for Cu, diamond, Sic, and GaN. Copper is the most commonly used metal for thermal conduction in p-n junction devices; diamond has the highest room-temperature thermal conductivity known to date and is useful as the thermal sink for semiconductor lasers and IMPATT oscillators. S i c and GaN are important semiconductors for power devices. 1.7 HETEROJUNCTIONS AND NANOSTRUCTURES A heterojunction is a junction formed between two dissimilar semiconductors. For semiconductor-device applications, the difference in energy gap provides another degree of freedom that produces many interesting phenomena. The successful applications of heterojunctions in various devices is due to the capability of epitaxy technology to grow lattice-matched semiconductor materials on top of one another with virtually no interface traps. Heterojunctions have been widely used in various device applications. The underlying physics of epitaxial heterojunction is matching of the lattice constants. This is a physical requirement in atom placement. Severe lattice mismatch will cause dislocations at the interface and results in electrical defects such as interface traps. The lattice constants of some common semiconductors are shown in Fig. 32, together with their energy gaps. A good combination for heterojunction devices is two materials of similar lattice constants but different Eg. As can be seen, GaAdAlGaAs (or /AlAs) is a good example. It turns out that if the lattice constants are not severely mismatched, good-quality heteroepitaxy can still be grown, provided that the epitaxial-layer thickness is small enough. The amount of lattice mismatch and the maximum allowed epitaxial layer are directly related. This can be explained with the help of Fig. 33. For a relaxed, thick heteroepitaxial layer, dislocations at the interface are inevitable due to the phys- + Strain c Fig. 33 Two materials with slightly mismatched lattice constants a, and a,. (a) In isolation. (b) Heteroepitaxy with thick, relaxed epitaxial layer having dislocations at the interface. (c) With thin, strained epitaxial layer without dislocations. Epitaxial lattice constant a, is strained to follow that of the substrate a,. 1.7 HETEROJUNCTIONS AND NANOSTRUCTURES 57 ical mismatch of terminating bonds at the interface. However, if the heteroepitaxial layer is thin enough, the layer can be physically strained to the degree that its lattice constant becomes the same as the substrate (Fig. 33c). When that happens, dislocations can be eliminated. To estimate the critical thickness of this strained layer, we visualize the heteroepitaxial process from the beginning. At the start, the epitaxial layer follows the lattice of the substrate, but the strain energy builds up as the film becomes thicker. Eventually the film has built up too much strain to sustain and it transforms to a relaxed state, i.e. going from Figs. 33c to 33b. The lattice mismatch is defined as where a, and a, are the lattice constants of the epitaxial layer and substrate respectively. The critical thickness has been found to follow an empirical formula given by A typical number for the critical thickness, from a mismatch of 2% and an a, of 5 A, is about 10 nm. This technique of growing strained heteroepitaxy has bough an extra degree of freedom and permits the use of a wider range of materials. It has had great impacts on expanding the applications of heterostructures, for making novel devices as well as improving their performances. Fig. 32 Energy gap vs. lattice constant for some common elementary and binary semiconductors. 58 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW In addition to having different energy gaps, the electron affinities of these semiconductors are also different and need to be considered in device applications. This leads to different combinations of E , and E , alignment at the interface. According to their band alignment, heterojunctions can be classified into three groups as shown in Fig. 34: (1) Type4 or straddling heterojunction, (2) Type-I1 or staggered heterojunction, and (3) Type-I11 or broken-gap heterojunction. In a Type-I (straddling) heterojunction, one material has both lower E , and higher E , and naturally it must have a smaller energy gap. In a Type-I1(staggered) heterojunction, the locations of lower E , and higher E , are displaced, so electrons being collected at lower E , and holes being collected at higher E , are confined in different spaces. A Type-111(broken-gap) heterojunction is a special case of Type-11, but the E , of one side is lower than the E , of the other. The conduction band thus overlaps the valence band at the interface, hence the name broken gap. Quantum Well and Superlattice. One important application of heterojunction is to use AE, and AE, to form barriers for carriers. A quantum well is formed by two heterojunctions or three layers of materials such that the middle layer has the lowest E, for an electron well or the highest E , for a hole well. A quantum well thus confines electrons or holes in a two-dimensional (2-D) system. When electrons are free to move in a bulk semiconductor in all directions (3-D), their energy above the conduction-band edge is continuous, given by the relationship to their momentum (Eq. 8): In a quantum well, carriers are confined in one direction, say in the x-coordinate such that k, = 0. It will be shown that the energy within this well is no longer continuous with respect to the x-direction, but becomes quantized in subbands. The most-importantparameters for a quantum well are the well width L, and well height 4b.The energy-band diagram in Fig. 35a shows that the potential barrier is obtained from the conduction-band and valence-band offsets (AE, and AE,). The solution for the wavefunction of the Schrodinger equation inside the well is Ec I Ec Ev I ' Ev EV (a) (b) (c) Fig. 34 Classification of heterojunctions.(a) Type-I or straddlingheterojunction.(b) Type41 or staggered heterojunction. (c) Type-111or broken-gap heterojunction. 1.7 HETEROJUNCTIONSAND NANOSTRUCTURES 59 Fig. 35 Energy-band diagrams for (a) heterostructure (composition) multiple quantum wells and (b) heterostructure superlattice. ~ ( x =) sin(?) (143) where i is an integer. It should be noted that at the well boundaries, t,u is truly zero only when (bb is infinite. With finite @b, carriers can “leak” out (by tunneling) of the well with finite probability. This is important for the formation of a superlattice, discussed later. The pinning of nodes at the well boundaries leads to the quantization of subbands, each has a bottom energy of (with respect to the band edges) These solutions do not take into account a finite barrier height. With L, as a variable, a quantum well can only be loosely defined. The minimum requirements should be that the quantized energy h2x22/2m*L,2is much larger than kT,and L, is smaller than the mean free path and the de Broglie wavelength. (Notice that the de Broglie wave- length A = hl(2m*E)”*has a form similar to L, of Eq. 144.) Also, it is interesting to note that since the continuous conduction band is now divided into subbands, carriers no longer reside on the band edges E, or E , but on these subbands only. In effect, the effective energy gap for interband transitions inside the quantum well becomes larger than the bulk Eg. When quantum wells are separated from one another by thick barrier layers, there is no communication between them and this system can only be described as multiple quantum wells. However, when the barrier layers between them become thinner, to 60 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW the extent that wavefunctions start to overlap, a heterostructure (composition)superlattice is formed. The superlattice has two major differences from a multiplequantum-well system: (1) the energy levels are continuous in space across the barrier, and (2) the discrete bands widen into minibands (Fig. 35b). The transition from multiple quantum wells into a superlattice is analogous to the formation of a regular lattice by pulling atoms together. The isolated atoms have discrete levels, whereas a lattice transforms these discrete levels into the continuous conduction band and valance band. Another approach to form quantum wells and superlattices is by spatial variation in doping,84where the potential barriers are formed by space-chargefields (Fig. 36a). The barrier shape in this case is parabolic rather than rectangular. There are two interesting features in this doping (or n-i-pi) multiple-quantum-wellstructure. First, the conduction-band minimum and the valence-band maximum are displaced from each other, meaning that electrons and holes accumulate at different locations. This leads to minimal electron-hole recombination and very long carrier lifetime, many orders of magnitude higher than that of the regular material. This is similar to a Type-I1heterojunction. Second, the effective energy gap, which is now between the first quantized levels for the electrons and holes, is reduced from the fundamental material. This tunable effective energy gap enables light emission and absorption of longer wavelengths. This structure is unique in that it has an indirect energy gap in “real space”, as opposed to k-space. When the doping quantum wells are close together, a doping (n-i-pi)superlatticeis again formed (Fig. 36b). Quantum Wire and Quantum Dot. The physical dimensions of a semiconductor have significant implications on the electronic properties, as these dimensions are Miniband; (b) Fig. 36 Energy-band diagrams for (a) doping (n-i-p-im) ultiple quantum wells, and (b) doping superlattice. 1.7 HETEROJUNCTIONS AND NANOSTRUCTURES 61 reduced to the order of the de Broglie wavelength. The confinement of carriers can be further extended to one- and zero-dimension, resulting in what are known as quantum wire and quantum dot. One of the major effects is on the density of states N(E). Depending on the degree of confinement, N(E)has very different shapes as a function of energy. The qualitative shapes of N(E) for bulk semiconductor, quantum well, quantum wire, and quantum dot are shown in Fig. 37. For a 3-D system, the density of states has been given earlier (Eq. 14) and is repeated here N ( E ) = m*J2m*E s2A3 The density of states in a 2-D system (quantum well) has a step function of (145) N ( E ) = - m*i mVL,. The density of states in a 1-D system (quantum wire) has an inverse energy relationship of where N ( E ) = - J2m* C ( E - Ei,,)-112, n--%L, i,j The density of states in a 0-D system (quantum dot) is continuous and independent of energy, 1-D 4 . . Fig. 37 Density of states N(E) for (a) bulk semiconductor (3-D), (b) quantum well (2-D), (c) quantum wire (1-D), and (d) quantum dot (0-D). 62 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW where Since the carrier concentration and its distribution in energy is given by the density of states multiplied by the Fermi-Dirac distribution, these density-of-state functions are important for the device operation as their physical dimensions are scaled to near the de Broglie wavelength (= 20 nm). 1.8 BASIC EQUATIONS AND EXAMPLES 1.8.1 Basic Equations The basic equations for semiconductor-device operation describe the static and dynamic behavior of carriers in semiconductors under external influences, such as applied field or optical excitation, that cause deviation from the thermal-equilibrium condition^.^^ The basic equations can be classified in three groups; electrostatic equations, current-density equations, and continuity equations. Electrostatic Equations. There are two important equations relating charge to electric field (= 9/sswhere 9is electric displacement). The first is from one of Maxwell equations, v . 9 = P(X,Y,Z), (151) also known as Gauss' law or Poisson equation. For a one-dimensional problem, this reduces to a more useful form of (V/I = 4 1 4 ) . This is commonly used, for example, to determine the potential and field distribution caused by a charge density pwithin the depletion layer. The second equation deals with charge density along an interface, instead of bulk charge. The boundary conditions across an interface of charge sheet Q is given by 81(O-)s,= 8 2 ( 0 + ) ~-2Q . (153) Current-Density Equations. The most-common current conduction consists of the drift component, caused by the electric field, and the diffusion component, caused by the carrier-concentration gradient. The current-density equations are: J,, = qp,n8+ qD,,Vn, (1 54a) Jp = 4PpP8-4DpVP, (1 54b) Jcond = J~ + J p ~ (155) 1.8 BASIC EQUATIONS AND EXAMPLES 63 where J, and Jp are the electron and hole current densities, respectively. The values of the electron and hole mobilities (pnand pp)have been given in Section 1.5.1. For nondegenerate semiconductors the carrier diffusion constants (D, and Dp)and the mobilities are given by the Einstein relation [D, = (kT/q)p,, etc.]. For a one-dimensional case, Eqs. 154a and 154b reduce to dm Jp = qpppg-qD P dx = qpp p g - -kqTdd p j - - 'PP &d dx (156b) where EFnand EFpare quasi Fermi levels for electrons and holes, respectively. These equations are valid for low electric fields. At sufficiently high fields the term p,g or p p gshould be replaced by the saturation velocity v, (and the last equalities about EFn and EFpdo not hold any more). These equations do not include the effect from an externally applied magnetic field where the magneto-resistive effect reduces the current. Continuity Equations. While the above current-density equations are for steadystate conditions, the continuity equations deal with time-dependent phenomena such as low-level injection, generation and recombination. Qualitatively, the net change of carrier concentration is the difference between generation and recombination, plus the net current flowing in and out of the region of interest. The continuity equations are: a-n-- G,-U,,+-V1 .J,, at 9 (1 57a) (157b) where G, and Gpare the electron and hole generation rate (~m-~-s-')r,espectively, caused by external influences such as the optical excitation with photons or impact ionization under large electric fields. The recombination rates, U,, = An/', and Up= Ap/zp,have been discussed in Section 1.5.4. For the one-dimensional case under a low-injection condition, Eqs. 157a and 157b reduce to (1 58a) (158b) 1.8.2 Examples In this section, we demonstrate the use of the continuity equations for studying the time dependence and space dependence of excess carriers. Excess carriers can be 64 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW created by optical excitation or injection from a nearby junction. In these examples we use optical excitation for simplicity. Decay of Excess Carriers with Time. Consider an n-type sample, as shown in Fig. 38a, that is illuminated with light in which the electron-hole pairs are generated uniformly throughout the sample with a uniform generation rate Gp.In this example the sample thickness is much smaller than l/a,and the space dependence is absent here. The boundary conditions are 8= d8/dx= 0 and apn/dx= 0. We have from Eq. 158b: d- Pn = G p - P-n. -Pno dt 5 At steady state, dp,ldt = 0 and (159) pn-pno = zpGp = constant. If at an arbitrarytime, say t = 0, the light is suddenlyturned off, the differentialequation is now hv I I c 0 5 t Light pulse I I I I ,I I i" Fig. 38 Decay of photo-excited carriers. (a) n-type sample under constant illumination. (b) Decay of minority carriers (holes) with time. (c) Schematic experimental setup to measure minority carrier lifetime. (After Ref. 71.) 1.8 BASIC EQUATIONS AND EXAMPLES 65 With the boundary conditions p,(t = 0) = pno+ rpGp,as given in Eq. 160, and p,(oo) =pno,the solution is Figure 38b shows the variation ofp, with time. The example above presents the main idea of the Stevenson-Keyes method for measuring minority-carrier lifetime.'l Figure 38c shows a schematic setup. The excess carriers generated uniformly throughout the sample by the light pulses cause a momentary increase in the conductivity and current. During the periods when the light pulses are off, the decay of this photoconductivity can be observed on an oscilloscope which monitors the voltage drop across a resistor load R,, and is a measure of the lifetime. Decay of Excess Carriers with Distance. Figure 39a shows another simple example where excess carriers are injected from one side (e.g., by high-energy photons that create electron-hole pairs at the surface only). Referring to Fig. 30, note that for h v = 3.5 eV, the absorption coefficient is about lo6cm-', in other words, the light intensity decreases by a factor of e in a distance of 10 nm. At steady state there is a concentration gradient near the surface. The differential equation for an n-type sample without bias is, from Eq. 158b, :h. . ...... ... . . . hV~-':::::.: ::::.:....... . ... . ------+ 0 . . 0. . ::::;k ------+::***. ---J---..:............. hv-.-,--+::::*. ' All excess ./carrieerxstracted Pno __-__ ~ ~ ~ Pno - - - - 0 Lp= J.a;- X 0 W X (4 (b) Fig. 39 Steady-state carrier injection from one side. (a) Semiinfinite sample. (b) Sample with length K 66 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW The boundary conditions are p,(x = 0) = constant, depending on the injection level, andp,(co) =pno.The solution ofp,(x) is where the diffusion length is L, = (D,Z,)~/~(Fig. 39a). The maximum values of L, and L, are of the order of 1 cm in silicon, but only of the order of 10-2 cm in gallium arsenide. Of special interest is the case where the second boundary condition is changed so that all excess carriers at the back surface (x = W)are extracted or p,( W)=pno,then we obtain from Eq. 163 a new solution, This result is shown in Fig. 39b. The current density at x = W is given by Eq. 156b: It will be shown later that Eq. 166 is related to the current gain in bipolar transistors (Chapter 5). Decay of Excess Carriers with Time and Distance. When localized light pulses generate excess carriers in a semiconductor (Fig. 40a), the transport equation after the pulse without bias is given by Eq. 158b by setting G, = g =dW:/dx= 0: The solution is given by where N' is the number of electrons or holes generated initially per unit area. Figure 40b shows this solution as the carriers difhse away fiom the point of injection, and they also recombine (area under curve is decreased). If an electric field is applied along the sample, the solution is in the same form but with x replaced by (x - p,gt) (Fig. 40c); thus the whole package of excess carrier moves toward the negative end of the sample with a drift velocity ,u,Z'. At the same time, the carriers diffuse outward and recombine as in the field-free case. The example above is similar to the celebrated Haynes-Shockley experiment for the measurement of carrier drift mobility in semicond~ctorsW.~i~th known sample length, applied field, and the time delay between the applied signals (bias on and light on) and the detected signal at the sample end (both displayed on the oscilloscope), the drift mobility p =xlgt can be calculated. 1.8 BASIC EQUATIONS AND EXAMPLES 67 Fig. 40 Transient and steady-state carrier diffusion after a localized light pulse, (a) Experimental setup. (b) Without applied field. (c) With applied field. Surface Recombination. When surface recombination is introduced at one end of a semiconductor sample (Fig. 41), the boundary condition at x = 0 is governed by which states that the minority carriers that reach the surface recombine there. The constant Spwith units crnls is defined as the surface recombination velocity for holes. The boundary condition at x = co is given by Eq. 160. The differential equation, without bias and at steady state, is The solution of the equation subject to the boundary conditions above is 68 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW hv Surface recombination Fig. 4 1 Surface recombination at x = 0. The minority-carrier distribution near the surface is affected by the surface recombination velocity. which is plotted in Fig. 41 for a finite Sp. When Sp+0, then p,(x) -+ pno+ zpGp, which was obtained previously (Eq. 160). When + Sp 00, then p , ( x ) + p n o+ zpGp[1- exp(- x/Lp)],and the minority carrier density at the surface approaches its thermal equilibrium value pno.Analogous to the low-injection bulk-recombination process, in which the reciprocal of the minority-carrier lifetime (1/z) is equal to oput,jVt(Eq. 95a), the surface recombination velocity is given by s p = oputhN;* (172) where Nit is the number of surface trapping centers per unit area at the boundary region. REFERENCES 1. W. C. Dunlap, An Introduction to Semiconductors, Wiley, New York, 1957. 2. 0.Madelung, Physics ofIII-VCompounds, Wiley, New York, 1964. 3. J. L. Moll, Physics of Semiconductors, McGraw-Hill, New York, 1964. 4. T. S. Moss, Ed., Handbook on Semiconductors, Vols. 1 4 , North-Holland, Amsterdam, 1980. 5 . R. A. Smith, Semiconductors, 2nd Ed., Cambridge University Press, London, 1979. 6. K. W. Boer, Survey of Semiconductor Physics, Van Nostrand Reinhold, New York, 1990. 7. K. Seeger, Semiconductor Physics, 7th Ed., Springer-Verlag, Berlin, 1999. 8. S. Wang, Fundamentals of Semiconductor Theory and Device Physics, Prentice-Hall, Englewood Cliffs, New Jersey, 1989. 9. R. K. Willardson and A. C. Beer, Eds., Semiconductors and Semimetals, Vol. 2, Physics of III-V Compounds, Academic, New York, 1966. REFERENCES 69 10. W. B. Pearson, Handbook of Lattice Spacings and Structure of Metals and Alloys, Pergamon, New York, 1967. 11. H. C. Casey, Jr. and M. B. Panish, Heterostructure Lasers, Academic, New York, 1978. 12. See, for example, C. Kittel, Introduction to SolidState Physics, 7th Ed., Wiley, New York, 1996. 13. L. Brillouin, WavePropagation in Periodic Structures, 2nd Ed., Dover, New York, 1963. 14. J. M. Ziman, Principles of the Theory of Solids, Cambridge University Press, London, 1964. 15. M. L. Cohen, “Pseudopotential Calculations for 11-VI Compounds,” in D. G. Thomas, Ed., 11-VISemiconductingCompounds,W. A. Benjamin, New York, 1967, p. 462. 16. C. Kittel, Quantum Theoryof Solids, Wiley, New York, 1963. 17. L. C. Allen, “Interpolation Scheme for Energy Bands in Solids,” Phys. Rev., 98, 993 (1955). 18. F. Herman, “The Electronic Energy Band Structure of Silicon and Germanium,” Proc. IRE, 43, 1703 (1955). 19. J. C. Phillips, “Energy-Band Interpolation Scheme Based on a Pseudopotential,” Phys. Rev., 112, 685 (1958). 20. M. L. Cohen and J. R. Chelikowsky, Electronic Structure and Optical Properties of Semi- conductors, 2nd Ed., Springer-Verlag, Berlin, 1988. 2 1. J. M. Ziman, Electrons and Phonons, Clarendon, Oxford, 1960. 22. C. D. Thurmond, “The Standard Thermodynamic Function of the Formation of Electrons and Holes in Ge, Si, GaAs and GaP,”J. Electrochem. SOC.,122, 1133 (1975). 23. V. Alex, S. Finkbeiner, and J. Weber, “Temperature Dependence of the Indirect Energy Gap in Crystalline Silicon,”J. Appl. Phys., 79, 6943 (1996). 24. W. Paul and D. M. Warschauer, Eds., Solids under Pressure, McGraw-Hill, New York, 1963. 25. R. S. Ohl, “Light-Sensitive Electric Device,” U.S. Patent 2,402,662. Filed May 27, 1941. Granted June 25, 1946. 26. M. Riordan and L. Hoddeson, “The Origins of thepn Junction”, IEEE Spectrum, 34-6,46 (1997). 27. J. S. Blackmore, “Carrier Concentrations and Fermi Levels in Semiconductors,” Electron. Commun.,29, 131 (1952). 28. W. B. Joyce and R. W. Dixon, “Analytic Approximations for the Fermi Energy of an Ideal Fermi Gas,” Appl. Phys. Lett., 31,354 (1977). 29. 0.Madelung, Ed., Semiconductors-Basic Data, 2nd Ed., Springer-Verlag, Berlin, 1996. 30. R. N. Hall and J. H. Racette, “Diffusion and Solubility of Copper in Extrinsic and Intrinsic Germanium, Silicon, and Gallium Arsenide,” J. Appl. Phys., 35, 379 (1964). 31. A. G. Milnes, Deep Impurities in Semiconductors, Wiley, New York, 1973. 32. J. Hermanson and J. C. Phillips, “Pseudopotential Theory of Exciton and Impurity States,” Phys. Rev., 150, 652 (1966). 33. J. Callaway and A. J. Hughes, “Localized Defects in Semiconductors,” Phys. Rev., 156, 860 (1967). 34. E. M. Conwell, “Properties of Silicon and Germanium, Part 11,” Proc. IRE, 46, 1281 (1 958). 70 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 35. S. M. Sze and J. C. Irvin, “Resistivity, Mobility, and Impurity Levels in GaAs, Ge, and Si at 300 K,” Solid-state Electron., 11, 599 (1968). 36. W. Shockley, Electrons and Holes in Semiconductors, D. Van Nostrand, Princeton, New Jersey, 1950. 37. A. S. Grove, Physics and Technologyof Semiconductor Devices, Wiley, New York, 1967. 38. J. Bardeen and W. Shockley, “Deformation Potentials and Mob es in Nonpolar Crys- tals,”Phys. Rev.,80, 72 (1950). 39. E. Conwell and V. F. Weisskopf, “Theory of Impurity Scattering in Semiconductors,” Phys. Rev., 77,388 (1950). 40. C. Bulucea, “Recalculation of Irvin’s Resistivity Curves for Diffused Layers in Silicon Using Updated Bulk Resistivity Data,” Solid-state Electron., 36, 489 (1993). 41. C. Jacoboni, C. Canali, G Ottaviani, and A. A. Quaranta, “A Review of Some Charge Transport Properties of Silicon,” Solid-state Electron., 20,77 (1977). 42. W. E. Beadle, J. C. C. Tsai, and R. D. Plummer, Eds., Quick Reference Manualfor Silicon Integrated Circuit Technology,Wiley, New York, 1985. 43. F. M. Smits, “Measurement of Sheet Resistivities with the Four-Point Probe,” Bell Syst. Tech.J., 37,711 (1958). 44. E. H. Hall, “On a New Action of the Magnet on Electric Currents,” Am.J. Math., 2, 287 (1879). 45. L. J. Van der Pauw, “A Method of Measuring Specific Resistivity and Hall Effect of Disc or Arbitrary Shape,” Philips Res. Rep., 13, 1 (Feb. 1958). 46. D. M. Caughey and R. E. Thomas, “Carrier Mob es in Silicon Empirically Related to Doping and Field,” Proc. IEEE, 55,2192 (1967). 47. D. E. Aspnes, “GaAs Lower Conduction-Band Minima: Ordering and Properties,” Phys. Rev., B14,5331 (1976). 48. P. Smith, M. Inoue, and J. Frey, “Electron Velocity in Si and GaAs at Very High Electric Fields,” Appl. Phys. Lett., 37, 797 (1980). 49. J. G. Ruch and G. S. Kino, “Measurement of the Velocity-Field Characteristics of Gallium Arsenide,” Appl. Phys. Lett., 10,40 (1967). 50. K. Brennan and K. Hess, “Theory of High-Field Transport of Holes in GaAs and InP,” Phys. Rev.B, 29,5581 (1984). 5 1. B. Kramer and A. Mircea, “Determination of Saturated Electron Velocity in GaAs,” Appl. Phys. Lett., 26,623 (1975). 52. K. K. Thomber, “Relation of Drift Velocity to Low-Field Mobility and High Field Satura- tion Velocity,”J. Appl. Phys., 51,2127 (1980). 53. J. G Ruch, “Electron Dynamics in Short Channel Field-Effect Transistors,” IEEE Trans. Electron Devices, ED-19, 652 (1972). 54. K. K. Thornber, “Applications of Scaling to Problems in High-Field Electronic Transport,” J. Appl. Phys., 52,279 (1981). 55. R. A. Logan and S. M. Sze, “Avalanche Multiplication in Ge and GaAs p-n Junctions,” Proc. Int. Conf. Phys. Semicond., Kyoto, andJ. Phys. SOC.Jpn. Suppl., 21,434 (1966). 56. W. N. Grant, “Electron and Hole Ionization Rates in Epitaxial Silicon at High Electric Fields,” Solid-state Electron., 16, 1189 (1973). REFERENCES 71 57. G. H. Glover, “Charge Multiplication in Au-Sic (6H) Schottky Junction,” J. Appl. Phys., 46,4842 (1975). 58. T. P. Pearsall, F. Capasso, R. E. Nahory, M. A. Pollack, and J. R. Chelikowsky, “The Band Structure Dependence of Impact Ionization by Hot Carriers in Semiconductors GaAs,” Solid-state Electron., 21,297 (1978). 59. I. Umebu, A. N. M. M. Choudhury, and P. N. Robson, “Ionization Coefficients Measured in Abrupt InP Junction,” Appl. Phys. Lett., 36, 302 (1980). 60. R. A. Logan and H. G. White, “Charge Multiplication in GaP p-n Junctions,” J. Appl. Phys., 36,3945 (1965). 61. T. P. Pearsall, “Impact Ionization Rates for Electrons and Holes in Ga,,471no,53As,A” ppl. Phys. Lett., 36,218 (1980). 62. T. P. Pearsall, R. E. Nahory, and M. A. Pollack, “Impact Ionization Rates for Electrons and Holes in GaAs,,Sb, Alloys,” Appl. Phys. Lett., 28,403 (1976). 63. L. W. Cook, G. E. Bulman, and G E. Stillman, “Electron and Hole Impact Ionization Coefficients in InP Determined by Photomultiplication Measurements,” Appl. Phys. Lett., 40, 589 (1982). 64. I. H. Oguzman, E. Bellotti, K. F. Brennan, J. Kolnik, R. Wang, and P. P. Ruden, “Theory of Hole Initiated Impact Ionization in Bulk Zincblende and Wurtzite GaN,” J. Appl. Phys., 81, 7827 (1997). 65. M. R. Brozel and G. E. Stillman, Eds., Properties of Gallium Arsenide, 3rd Ed., INSPEC, London, 1996. 66. C. R. Crowell and S. M. Sze, “Temperature Dependence of Avalanche Multiplication in Semiconductors,” Appl. Phys. Lett., 9,242 (1966). 67. C. T. Sah, R. N. Noyce, and W. Shockley, “Carrier Generation and Recombination in p-n Junction andp-n Junction Characteristics,” Proc. IRE, 45, 1228 (1957). 68. R. N. Hall, “Electron-Hole Recombination in Germanium,” Phys. Rev., 87,387 (1952). 69. W. Shockley and W. T. Read, “Statistics of the Recombination of Holes and Electrons,” Phys. Rev., 87, 835 (1952). 70. W. M. Bullis, “Properties of Gold in Silicon,” Solid-state Electron., 9, 143 (1966). 71. D. T. Stevenson and R. J. Keyes, “Measurement of Carrier Lifetime in Germanium and Silicon,” J. Appl. Phys., 26, 190 (1955). 72. W. W. Gartner, “Spectral Distribution of the Photomagnetic Electric Effect,” Phys. Rev., 105, 823 (1957). 73. S. Wei and M. Y.Chou, “Phonon Dispersions of Silicon and Germanium from First-Principles Calculations,” Phys. Rev. B, 50,2221 (1994). 74. C. Patel, T. J. Parker, H. Jamshidi, and W. F. Sherman, “Phonon Frequencies in GaAs,” Phys. Stat. Sol. (b), 122,461 (1984). 75. W. C. Dash and R. Newman, “Intrinsic Optical Absorption in Single-Crystal Germanium and Silicon at 77°K and 300”K,”Phys. Rev., 99, 115 1 (1955). 76. H. R. Philipp and E. A. Taft, “Optical Constants of Silicon in the Region 1to 10 eV,” Phys. Rev. Lett., 8, 13 (1962). 77. D. E. Hill, “Infrared Transmission and Fluorescence of Doped Gallium Arsenide,” Phys. Rev., 133, A866 (1964). 72 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 78. H. C. Casey, Jr., D. D. Sell, and K. W. Wecht, “Concentration Dependence of the Absorption Coefficient for n- andp-type GaAs between 1.3 and 1.6 eV,” J. Appl. Phys., 46,250 (1975). 79. C. Y. Ho, R. W. Powell, and P. E. Liley, Thermal Conductivity of the Elements-A Comprehensive Review, Am. Chem. SOC.and Am. Inst. Phys., New York, 1975. 80. M. G. Holland, “Phonon Scattering in Semiconductors from Thermal Conductivity Studies,”Phys. Rev., 134,A471 (1964). 81. B. H. Armstrong, “Thermal Conductivity in SiO,”, in S. T. Pantelides, Ed., The Physics of SiO, andlts Interfaces, Pergamon, New York, 1978. 82. G. A. Slack, “Thermal Conductivity of Pure and Impure Silicon, Silicon Carbide, and Diamond,” J. Appl. Phys., 35, 3460 (1964). 83. E. K. Sichel and J. I. Pankove, “Thermal Conductivity of GaN, 25-360 K,”J. Phys. Chem. Solids, 38,330 (1977). 84. G. H. Dohler, “Doping Superlattices-Historical Overview”, in P. Bhattacharya, Ed., IIZ-V Quantum Wells and Superlattices, INSPEC, London, 1996. 85. J. R. Haynes and W. Shockley, “The Mobility and Life of Injected Holes and Electrons in Germanium,”Phys. Rev., 81, 835 (1951). PROBLEMS 1. (a) Find the maximum fraction of a conventional unit-cell volume which can be filled by identical hard spheres in a diamond lattice. (b) Find the number of atoms per square centimeter in silicon in (111) plane at 300 K. 2. Calculate the tetrahedral bond angle, i.e., the angle between any pair of the four bonds. (Hint: Represent the 4 bonds as vectors of equal lengths. What must be the sum of the 4 vectors equal? Take components of this vector equation along the direction of one of these vectors.) 3. For a face centered cubic, the volume of a conventional unit cell is a3.Find the volume of a fcc primitive unit cell with three basis vectors: (0,0,0+a/2,0,a/2), (O,O,O+a/2,a/2,0), and (0,0,0-+0,a/2,a/2). 4. (a) Derive an expression for the bond length d i n the diamond lattice in terms of the lattice constant a. (b) In a silicon crystal, if a plane has intercepts at 10.86 A, 16.29 A, and 21.72 8, along the three Cartesian coordinates, find the Miller indices of the plane. 5. Show (a) that each vector of the reciprocal lattice is normal to a set of planes in the direct lattice, and (b) the volume of a unit cell of the reciprocal lattice is inversely proportional to the volume of a unit cell of the direct lattice. 6. Show that the reciprocal lattice of a body-centered cubic (bcc) lattice with a lattice constant a is a face-centered cubic (fcc) lattice with the side of the cubic cell to be 4 d a . [Hint: Use a symmetric set of vectors for bcc: a = a-2(y+z-x), b = a-2( z + x - y ) , c = U2- ( x + y - 2 ) where a is the lattice constant of a conventional primitive cell, andx,y, z are unity vectors of a Cartesian coordinate. For fcc; PROBLEMS 73 a = a2-b+z), b = -a2( z + x ) , c = -a2( x + Y ) . ] 7. Near the conduction band minima the energy can be expressed as In Si there are six cigar-shaped minima along [1001. If the ratio of the axes of constant energy ellipsoid is 5:1, find the ratio of longitudinal effective mass m; to the transverse effective mass mf . 8. In the conduction band of a semiconductor, it has a lower valley at the center of the Brillouin zone, and six upper valleys at the zone boundary along [loo]. If the effective mass for the lower valley is O.lmo and that for the upper valleys is l.Orno,find the ratio of the effective density of states in the upper valleys to that in the lower valley. 9. Derive the density of states in the conduction band as given by Eq. 14. (Hint:The wavelength il of a standing wave is related to the length of the semiconductorL by L/il = n, where n, is an integer. The wavelength can be expressed by de Broglie hypothesis il = h/p,. Consider a three-dimensional cube of side L.) 10. Calculate the average kinetic energy of electrons in the conduction band of an n-type nondegenerate semiconductor. The density of states is given by Eq. 14. 11. Show that [ : (“31’ [Hint:The probability of occupancy is F(E) = 1+-exp - where h is the number of electrons that can physically occupy the level E, and g is the number of electrons that can be accepted by the level, also called the ground-state degeneracy of the donor impurity level (g= 2).] 12. If a silicon sample is doped with l o i 6phosphorous impurities/cm3, find the ionized donor density at 77 K. Assume that the ionization energy for phosphorous donor impurities and the electron effective mass are independent of temperature. (Hint: First select a Nh value to calculate the Fermi level, then find the corresponding N; . If they don’t agree, select another NL value and repeat the process until a consistent Nh is obtained.) 13. Using graphic method to determine the Fermi level for a boron-doped silicon sample with an impurity concentration of 1015cm-) at 300 K (note ni= 9 . 6 5 ~ 1 0~~r n - ~ ) . 14. The Fermi-Dirac distribution function is given by F(E) = 1 1 + exp[(E-E,)/kT] . The differentiation of F(E) with respect to energy is F’(E). Find the width of F’(E), i.e., E( at FAax-) E(at I2Fh,,,)] where lF,f,,axils the maximum value of F‘(E). 15. Find the position of the Fermi level with respect to the bottom of the conduction band (Ec -E,) for a silicon sample at 300 K, which is doped with 2 x 1O1O ~ m fu- lly~ ionized donors. 74 CHAPTER 1. PHYSICS AND PROPERTIES OF SEMICONDUCTORS-A REVIEW 16. Gold in Si has two energy levels in the bandgap: E, - EA= 0.54 eV, ED- E , = 0.29 eV. Assume the third level ED- E , = 0.35 eV is inactive. (a) What will be the state of charge of the gold levels in Si doped with high concentration of boron atoms? Why? (b) What is the effect of gold on electron and hole concentrations? 17. From Fig. 13, evaluate and determine what kind of impurity atoms is used to dope the Si sample? 18. For an n-type silicon sample doped with 2.86x 10l6~ m ph- os~phorous atoms, find the ratio of the neutral to ionized donors at 300 K. (E, - ED)= 0.045 eV. 19. (a) Assume the mobility ratio ,u,/,up= b in Si is a constant independent of impurity concen- tration. Find the maximum resistivity p, in terms of the intrinsic resistivity piat 300 K. If b = 3 and the hole mobility of intrinsic Si is 450 cm2/V-s,calculate p, and p,. (b) Find the electron and hole concentration, mobility, and resistivity of a GaAs sample at 300 K with 5 ~ 1 0z'in~c atoms/cm3, lo1' sulfur atoms/cm3, and lo1' carbon atoms/cm3. 1 20. The Gamma Function is defined as T(n)= x n- exp (-x)dx . (a) Find r(1/2), and (b) show that r ( n ) = (n- I)r(n - I). 21. Consider a compensated n-type silicon at T = 300 K, with a conductivity of a=16 S/cm and an acceptor doping concentration of 1OI7 ~ m - D~e.termine the donor concentration and the electron mobility. (A compensated semiconductor is one that contains both donor and acceptor impurity atoms in the same region.) 22. Find the resistivity at 300 K for a silicon sample doped with 1.Ox lOI4 ~ m o-f p~hosphorous atoms, 8 . 5 ~ 1 0~' ~m o-f a~rsenic atoms, and 1 . 2 ~ 1 ~0 ~m~o-f b~oron atoms. Assume that the impurities are completely ionized and the mobilities are p , = 1500 cm2/V-s, ,up = 500 cm2N-s,independent of impurity concentrations. 23. A semiconductor has a resistivity of 1.0 a - c m , and a Hall coefficient of -1250 cm2/Coul. Calculate the carrier density and mobility, assuming that only one type of carrier is present and the mean free time is proportional to the carrier energy, i.e., r a E. 24. Derive the recombination rate for indirect recombination as given by Eq. 92. (Hint: Refer to Fig. 25b, the capture rate of an electron by a recombination center is pro- portional to R, = nN,( 1-F)where n is the density of electrons in the conduction band, N, is the density of recombination centers, F is the Fermi distribution, and N,( 1 - F) is the density of unoccupied recombination centers available for electron capture.) 25. The recombination rate is given by Eq. 92. Under low injection condition, U can be expressed as (p, -pno)/rowhere r, is the recombination lifetime. If a, = ap= a,, nno= 1015~ r n -a~n,d r, = (u,~oJV,)-fIin,d the values of (E,-E,) at which the recombination life- time rr becomes 2 rro. 26. For single-level recombination with identical electron and hole capture cross sections, find the number of trap centers per unit volume per generation rate under the condition of complete depletion of carriers. Assume that the trap centers are located at mid bandgap, o=2x10-"3 cm2, and u,h = 107 c d s . 27. In a region of semiconductor which is completely depleted of carriers (i.e., n << n,,p << n,), electron-hole pairs are generated by alternate emission of electrons and of holes by the centers. Derive the average time that takes place between such emission process (assume PROBLEMS 75 om= op= n);also find the average time for n= 2x 10-l6 cm2, ulh= lo7 c d s , and El = Ei. ( T = 300 K). 28. For a single-level recombination process, find the average time that takes place between each recombination process in a region of a silicon sample where n = p = 1013~ m - o~n,= op= 2 ~ 1 0 - lc~m2,uth= lo7c d s , N1= 10I6~ m - a~nd, (E,-E,) = 5kT 29. (a). Derive Eq. 123. (Hint: Assume a linear chain of atoms and the atoms interact only with nearest neighbors. The even-numbered atoms have mass m ,and the odd-numbered atoms have mass m,.) (b) For a silicon crystal with m l= m, and = 7 . 6 31~0l2Hz, find the optical phonon energy at the boundary of the Brillouin zone. The force constant is a? 30. Assume G%,,In,,,As is lattice matched with InP substrate at 500°C. When the sample is cooled to 27"C, find the lattice mismatch between the layers. 3 1. Find the ratio of the conduction-band discontinuity of the heterojunction A1,,,Gao,6As/GaAsto the A10,4Ga,,6Asbandgap. 32. In a Haynes-Shockley experiment, the maximum amplitudes of the minority carriers at tl = 25 ps and t, = 100 ps differ by a factor of 10. Find the minority carrier lifetime. 33. From the expression which describes the drift and diffusion of carriers in the HaynesShockley experiment, find the half-width of the pulse of carriers at t = 1 s. Assume the diffusion coefficient is 10 cm2/s. 34. Excess carriers are injected on one surface (x = 0) of a thin slide of n-type ( 3 ~ 1 0~' ~m - ~ ) silicon with length W = 0.05 mm and extracted at the opposite surface wherep,(W) =pno. If the carrier lifetime is 50 ps, find the portion of injected current which reaches the opposite surface by diffusion. 35. A GaAs n-type sample with No = 5 ~ 1 ~0 m~ is-~il~luminated. The uniformly absorbed light creates lOI7 electron-hole pairs/cm3-s. The lifetime 5 is s, Lp = 1 . 9 3 ~ 1 0 -c~m, the surface recombination velocity Spis lo5 cm/s. Find the number of holes recombining at the surface per unit surface area in unit time. 36. An n-type semiconductor has excess carrier holes lOI4~ m - a~ m, inority carrier lifetime s in the bulk material, and a minority carrier lifetime lIY7 s at the surface. Assume zero applied electric field and let Dp = 10 cm2/s. Determine the steady-state excess carrier concentration as a function of distance from the surface (x = 0) of the semiconductor. Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. DEVICE BUILDING BLOCKS + Chapter 2 p-n Junctions + Chapter 3 Metal-Semiconductor Contacts + Chapter 4 Metal-Insulator-Semiconductor Capacitors Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. p-n Junctions 2.1 INTRODUCTION 2.2 DEPLETION REGION 2.3 CURRENT-VOLTAGECHARACTERISTICS 2.4 JUNCTION BREAKDOWN 2.5 TRANSIENT BEHAVIOR AND NOISE 2.6 TERMINAL FUNCTIONS 2.7 HETEROJUNCTIONS 2.1 INTRODUCTION p-n junctions are of great importance both in modern electronic applications and in understanding other semiconductor devices. The p-n junction theory serves as the foundation of the physics of semiconductor devices. The basic theory of currentvoltage characteristics of p-n junctions was established by Shockley.',* This theory was then extended by Sah, Noyce, and Shockley3,and by Moll.4 The basic equations presented in Chapter 1 are used to develop the ideal static and dynamic characteristics of p-n junctions. Departures from the ideal characteristics due to generation and recombination in the depletion layer, to high injection, and to series resistance effects are then discussed. Junction breakdown, especially that due to avalanche multiplication, is considered in detail, after which transient behavior and noise performance in p-n junctions are presented. Ap-n junction is a two-terminal device. Depending on the doping profile, device geometry, and biasing condition, a p-n junction can perform various terminal fimctions which are considered briefly in Section 2.6. The chapter closes with a discussion of an important group of devices-the heterojunctions, which are junctions formed between dissimilar semiconductors (e.g., n-type GaAs on p-type AlGaAs). 79 80 CHAPTER 2. p-n JUNCTIONS 2.2 DEPLETION REGION 2.2.1 Abrupt Junction Built-in Potential and Depletion-Layer Width. When the impurity concentration in a semiconductor changes abruptly from acceptor impuritiesNAto donor impurities N,, as shown in Fig. la, one obtains an abrupt junction. In particular, if NA>> No (or vice versa), one obtains a one-sided abruptp+-n (or n'-p) junction. 000 0 WD" 000 000 @) Area = built-in potential tybi G + r x EC E, -fb';~" EF (d) Ev 4 Fig. 1 Abrupt p-n junction in thermal equilibrium. (a) Space-charge distribution. Dashed lines indicatecorrectionsto depletion approximation. (b) Electric-fielddistribution.(c) Potential distribution where ybiis the built-in potential. (c) Energy-band diagram. 2.2 DEPLETION REGION 81 We first consider the thermal equilibrium condition, that is, one without applied voltage and current flow. From the current equation of drift and difhsion (Eq. 156a in Chapter l), or Similarly, d- EF = 0 . dx Thus the condition of zero net electron and hole currents requires that the Fermi level must be constant throughout the sample. The built-in patential vbi, or diffusion potential, as shown in Fig. 1b, c, and d, is equal to q v b i = Eg-(q@n+4qp) = q v B n + q v B p . (4) For nondegenerate semiconductors, Since at equilibrium nngno= npgpo= n: , This gives the relationship between carrier densities on either side of the junction. If one or both sides of the junction are degenerate, care has to be taken in calcu- lating the Fermi-levels and built-in potential. Equation 4 has to be used since Boltzmann statistics cannot be used to simplify the Fermi-Dirac integral. Furthermore, incomplete ionization has to be considered, i.e., nnof NO andlorp,, f NA(Eqs. 34 and 35 of Chapter 1). Next, we proceed to calculate the field and potential distribution inside the depletion region. To simplify the analysis, the depletion approximation is used which assumes that the depleted charge has a box profile. Since in thermal equilibrium the electric field in the neutral regions (far from the junction at either side) of the semiconductor must be zero, the total negative charge per unit area in the p-side must be precisely equal to the total positive charge per unit area in the n-side: N A wDp = wDn ' (7) From the Poisson equation we obtain 82 CHAPTER 2. p-n JUNCTIONS - dx2 = dx = E~ = 4[N2,(x)-n(x)-Nj(x) +p(x)]. E~ Inside the depletion region, n(x) =p(x)= 0, and assuming complete ionization, &y/,=-q N A dx2 sS for - WDpI x I 0 , - -&wi =-qND dx2 cS for O l x l W D n . The electric field is then obtained by integrating the above equations, as shown in Fig. lb: where grnis the maximum field that exists at x = 0 and is given by Integrating Eqs. 10 and 11 once again gives the potential distribution I&) (Fig. lc) With these, the potentials across different regions can be found as: qND6n lwnl = -’ 25 (15b) (w, is relative to the n-type bulk and is thus negative. See definition in Appendix A) where grncan also be expressed as: 2.2 DEPLETION REGION 83 From Eqs. 16 and 7, the depletion widths are calculated to be: The following relationships can be hrther deduced: For a one-sided abrupt junction (p+-nor n+-p),Eq. 4 is used to calculate the builtin potential. In this case, the majority of the potential variation and depletion region will be inside the lightly doped side. Equation 19 reduces to where N is NO or NA depending on whether NA>> NO or vice versa, and This discussion uses box profiles for the depletion charges, i.e., depletion approximation. A more accurate result for the depletion-layer properties can be obtained by considering the majority-carrier contribution in addition to the impurity concentration in the Poisson equation, that is, p z - q[NA- p ( x ) ] on thep-side and p = q[ND- n(x)] on the n-side. The depletion width is essentially the same as given by Eq. 19, except that ybjis replaced by ( Y b i- 2kT/q).* The correction factor 2kTlq comes about because of the two majority-carrier distribution tail^^,^ (electrons in n-side and holes inp-side, as shown by the dashed lines in Fig. la) near the edges of the depletion region. Each contributes a correction factor kT/q. The depletion-layer width at thermal equilibrium for a one-sided abrupt junction becomes Furthermore, when a voltage V is applied to the junction, the total electrostatic potential variation across the junction is given by ( Ybi - v)where V is positive for forward bias (positive voltage onp-region with respect to n-region) and negative for reverse bias. Substituting (ybi- v)for Ybi in Eq. 23 yields the depletion-layer width as a function of the applied voltage. The results for one-sided abrupt junctions in 84 CHAPTER 2. p-n JUNCTIONS 102 h 103 " U 1i n 4 .- 9 a 3 - -E .- 5 =. 105 a, - 2 - 10 0.1 1 - -- = I06 10 I00 Net potential, - V ( V ) Fig. 7 Depletion-layer width and depletion-layercapacitanceper unit area as a function of net potential (I - V ) for different impurity gradients in linearly graded junctions in Si. Dashed lines represent breakdown conditions. 90 CHAPTER 2. p-n JUNCTIONS Meanwhile, the total depletion-layer charge is given by WLJ QD = q l N D ( x ) ~ . Differentiating the above quantities with respect to the depletion width gives From these we obtain the depletion-layer capacitance, Again the general expression of EJ WDis obtained and is applicable to any arbitrary doping profile. From this we can derive Eq. 26 for a general nonuniform profile; d-(-l / C i ) - d ( l / C i ) d W D - ~ W D ~ W D dV dwD dV E; d V This C-Vtechnique can be used to measure nonuniform doping profile. The 1/ C i - V plot (like that shown in Fig. 3 ) would deviate from a straight line if the doping is not constant. 2.3 CURRENT-VOLTAGE CHARACTERISTICS 2.3.1 Ideal Case-Shockley The ideal current-voltage characteristics are based on the following four assumptions: ( 1 ) the abrupt depletion-layer approximation; that is, the built-in potential and applied voltages are supported by a dipole layer with abrupt boundaries, and outside the boundaries the semiconductor is assumed to be neutral; ( 2 )the Boltzmann approximation, similar to Eqs. 21 and 23 of Chapter 1, is valid; ( 3 )the low-injection assumption; that is, the injected minority carrier densities are small compared with the majority-carrier densities; and ( 4 )no generation-recombination current exists inside the depletion layer, and the electron and hole currents are constant throughout the depletion layer. 2.3 CURRENT-VOLTAGECHARACTERISTICS 91 We first consider the Boltzmann relation. At thermal equilibrium this relation is given by Obviously, at thermal equilibrium, the pn product from the above equations is equal to n,?. When voltage is applied, the minority-carrier densities on both sides of the junction are changed, and the p n product is no longer equal to n,?. We shall now define the quasi-Fermi (imref) levels as follows: “3 n=niexp - (EF;, ’ (474 where EFnand EFpare the quasi-Fermi levels for electrons and holes, respectively. From Eqs. 47a and 47b we obtain (;I EFn=Ei+ kTln - , (k) EFp=Ei - kTln The pn product becomes p n = ni exp (EFn;?). (49) For a forward bias, (EF,,-EFp)> 0 and pn > n: ; on the other hand, for a reversed bias, (EFn-EFp)< 0 and pn < n: . From Eq. 156a of Chapter 1, Eq. 47a, and the fact that ZY = VEilq,we obtain L J,, = qp,, n 8 + “-‘.n) = ,u,,nVE, + p,kT [k-“(TVEF,, - V E , ) ] = ,U,,nVEF,, . (50) Similarly, we obtain, Jp = PpPvEFp. (51) Thus, the electron and hole current densities are proportional to the gradients of the electron and hole quasi-Fermi levels, respectively. If EFn=EFp = constant (at thermal equilibrium), then J,, =Jp = 0. The idealized potential distributions and the carrier concentrations in a p-n junction under forward-bias and reverse-bias conditions are shown in Fig. 8. The variations of EFnand EFpwith distance are related to the carrier concentrations as given in 92 CHAPTER 2. p-n JUNCTIONS 11 P"0 Fig. 8 Energy-band diagram, with quasi-Fermi levels for electrons and holes, and carrier distributions under (a) forward bias and (b) reverse bias. Eqs. 48a and 48b, and to the current as given by Eqs. 50 and 51. Inside the depletion region, EFn and EFpremain relatively constant. This comes about because the carrier concentrations are relatively much higher inside the depletion region, but since the currents remain fairly constant, the gradients of the quasi-Fermi levels have to be small. In addition, the depletion width is typically much shorter than the diffusion length, so the total drop of quasi-Fermi levels inside the depletion width is not significant. With these arguments, it follows that within the depletion region, qV = EFn-EFp, (52) Equations 49 and 52 can be combined to give the electron density at the boundary of the depletion-layer region on thep-side (x = - WDp): where pp=p for low-level injection, and npois the equilibrium electron density on the p-side. SiPmO ilarly, 2.3 CURRENT-VOLTAGE CHARACTERISTICS 93 at x = W, for the n-type boundary. The preceding equations are the most-important boundary conditions for the ideal current-voltage equation. From the continuity equations we obtain for the steady-state condition in the n-side of the junction: - U + p n 8dd-nx+np n d-Z+7Dn-!! 8 n = 0 , "dx dx2 (544 - U - , U ~ dZdPx~n- - , U ~d~gdx +D 8P n- dx2 = 0. In these equations, U is the net recombination rate. Note that due to charge neutrality, majority carriers need to adjust their concentrations such that (n, - nno)= (p, -pn0).It also follows that dn,,Idx = dp,/dx. Multiplying Eq. 54a by ,upnand Eq. 54b by ,unnn, and combining with the Einstein relation D = (kT/q),u,we obtain where is the ambipolar diffusion coefficient, and p u z =-P n - P n o (57) From the low-injection assumption [e.g., p n<< (n, = nno) in the n-type semicon- ductor], Eq. 55 reduces to P n - P n o p p gd-P+nD 8P 3 = 0 dx dx2 which is Eq. 54b except that the term pgnd8ldxis ignored under the low-injection assumption. In the neutral region where there is no electric field, Eq. 58 further reduces to The solution of Eq. 59, with the boundary conditions of Eq. 53b andp,(x = a)=pn0, gives where Lp=fip. At x = W,, the hole diffusion current is 94 CHAPTER 2. p-n JUNCTIONS Similarly, we obtain the electron diffusion current in the p-side The minority-carrier densities and the current densities for the forward-bias and reverse-bias conditions are shown in Fig. 9. It is interesting to note that the hole current is due to injection of holes from thep-side to the n-side, but the magnitude is determined by the properties in the n-side only (Dp,Lp,pn,,)T. he analogy holds for the electron current. The total current is given by the sum of Eqs. 62a and 62b: [ 1 J = J,+J,, = J,, exp( k 3 - I , I I I I I I I I I I I I I -X J I -x 14 I I I I I I I I I I I I I I J, 0 tX - wDp wDn Fig. 9 Carrier distributions and current densities (both linear plots) for (a) forward-biased conditionsand (b) reverse-biasedconditions. 2.3 CURRENT-VOLTAGE CHARACTERISTICS 95 Equation 63 is the celebrated Shockley equation,',2 which is the ideal diode law. The ideal current-voltage relation is shown in Figs. 10a and b in the linear and semilog plots, respectively. In the forward direction (positive bias on the p-side) for V > 3kT/q, the rate of current rise is constant (Fig. lob); at 300 K for every decade change of current, the voltage changes by 59.5 mV (= 2.3kTlq). In the reverse direction, the current density saturates at -J,. We shall now briefly consider the temperature effect on the saturation current density J,. We shall consider only the first term in Eq. 64, since the second term will behave similarly to the first one. For the one-sided p+-n abrupt junction (with donor concentration ND),p >> npo,the second term can also be neglected. The quantities n , Dp,pno,and Lp (= &p) are all temperature-dependent. If Dp/7pis proportional to TY,where yis a constant, then The temperature dependence of the term T(3+"2) is not important compared with the exponential term. The slope of a plot J, versus l/Tis determined mainly by the energy gap Eg. It is expected that in the reverse direction, where lJRl= J,, the current will increase approximately as exp(-E$kT) with temperature; and in the forward direc- tion, where JF= J,exp(qV/kT), the current will increase approximately as exp[Wg- 4 v)lkTl. IJJJol 104 103 102 xward I I, I I ./ I I I I 1) -5 qVlkT Reverse 10' 1 lo-' Fig. 10 Ideal current-voltage characteristics. (a) Linear plot. (b) Semilog plot. 96 CHAPTER 2. p-n JUNCTIONS The Shockley equation adequately predicts the current-voltage characteristics of germanium p-n junctions at low current densities. For Si and GaAs p-n junctions, however, the ideal equation can only give qualitative agreement. The departures from the ideal are mainly due to: (1) the generation and recombination of carriers in the depletion layer, (2) the high-injection condition that may occur even at relatively small forward bias, (3) the parasitic IR drop due to series resistance, (4) the tunneling of carriers between states in the bandgap, and (5) the surface effects. In addition, under sufficiently larger field in the reverse direction, the junction will breakdown as a result, for example, of avalanche multiplication. The junction breakdown will be discussed in Section 2.4. The surface effects on p-n junctions are primarily due to ionic charges on or outside the semiconductor surface that induce image charges in the semiconductor, and thereby cause the formation of the so-called surface channels or surface depletion-layer regions. Once a channel is formed, it modifies the junction depletion region and gives rise to surface leakage current. For Si planar p-n junctions, the surface leakage current is generally much smaller than the generation-recombination current in the depletion region. 2.3.2 Generation-RecombinationProcess3 Consider first the generation current under the reverse-bias condition. Because of the reduction in carrier concentration under reverse bias (pn << n ; ), the dominant generation processes, as discussed in Section 1.5.4, are those of emission. The rate of generation of electron-hole pairs can be obtained from Eq. 92 of Chapter 1 with the conditionp << ni and n << ni: u=-{ O pOnvthNt Onexp[(E,-Ei)/kT] + opexp[(Ei-Ef)/kT] (66) where zg is the generation lifetime and is defined as the reciprocal of the expression in brackets (see Eq. 98 of Chapter 1 and the discussion following). The current due to generation in the depletion region is thus given by where WDis the depletion-layer width. If the generation lifetime is a slowly varying function of temperature, the generation current will then have the same temperature dependence as ni. At a given temperature, J is proportional to the depletion-layer width, which in turn is dependent on the applgieed reverse bias. It is thus expected that for abrupt junctions, and for linearly graded junctions. 2.3 CURRENT-VOLTAGE CHARACTERISTICS 97 The total reverse current (for p,, >> npoand IPI > 3kT/q) can be approximated by the sum of the diffusioncomponent in the neutral region and the generation current in the depletion region: For semiconductorswith large values of ni(such as Ge), the diffusioncomponentwill dominate at room temperature and the reverse current will follow the Shockley equation; but if yli is small (such as for Si), the generation current may dominate. A typical result for Si is shown in Fig. 11, curve (e). At sufficiently high temperatures, however, the diffusion current will dominate. At forward bias, where the major recombination-generation processes in the depletion region are the capture processes, we have a recombination current J,, in addition to the diffusion current. Substituting Eq. 49 in Eq. 92 of Chapter 1 yields U = o,{,n + n,exp opcT,v,hN,n?[exp(qVlkT)- 1 3 [( E ,-Ei)/kT]} + op{ p + niexp [(E i- E, ) / k T ]} . (71) 108 107 106 105 3104 103 102 10' 1 10-1 Fig. 11 Current-voltage characteristics of a practical Si diode. (a) Generation-recombination current region. (b) DifTusion-current region. (c) High-injection region. (d) Series-resistance effect. (e) Reverse leakage current due to generation-recombination and surface effects. 98 CHAPTER 2. p-n JUNCTIONS Under the assumptions that E, = Ei and on= op= o,Eq. 71 reduces to O7l,hNtfl;[eXP(qv/kr) - 11 U= n + p+ 2ni -- m,hNtn;[ exp(qV/kT) - 11 ni{exp[(EFn-E,)/kT] + exp[(Ei-EFp)/kT] + 2) ’ (72) The maximum value of U exists in the depletion region where Ei is halfway between EFnand EFp, and so the denominator of Eq. 72 becomes 2ni[exp(qV/2kT) + 11. We obtain for V kT/g, u=-1 m t h N , n i e x p ( g J 2 (73) and The above approximation assumes that most part of the depletion layer has this maximum recombination rate, and Jreis thus somewhat an overestimate. A more rigorous derivation gives9 where gois the electric field at the location of maximum recombination, and it is equal to Similar to the generation current in reverse bias, the recombination current in forward bias is also proportional to ni. The total forward current can be approximated by the sum of Eqs. 63 and 75. For ap+-njunction (pn0>> npo)and V >> kT/q: +F- (c) JF = q pDi enx2 p ( $ $ kTn . rp No 2 rpgOex2pkT (77) The experimental results in general can be represented by the empirical form, (5) JF CC exp where the ideality factor 7 equals 2 when the recombination current dominates [Fig. 11, curve (a)] and 7 equals 1 when the diffusion current dominates [Fig. 11, curve (b)]. When both currents are comparable, 7 has a value between 1 and 2. 2.3 CURRENT-VOLTAGE CHARACTERISTICS 99 2.3.3 High-Injection Condition At high current densities (under the forward-bias condition) such that the injected minority-carrier density is comparable to the majority concentration, both drift and diffusion current components must be considered. The individual conduction current densities can always be given by Eqs. 50 and 51. Since Jp, q, pp,and p are positive, the quasi-Fermi level for holes E increases monotonically to the right as shown in Fig. 8a. Similarly, the quasi-FermFiplevel for electrons EF,,decreases monotonically to the left. Thus, everywhere the separation of the two quasi-Fermi levels must be equal to or less than the applied voltage, and thereforelo pn In j e x p ( 3 (79) even under the high-injection condition. Note also that the foregoing argument does not depend on recombination in the depletion region. To illustrate the high-injection case, we present in Fig. 12 plots of numerical simulation results for carrier concentrations and energy-band diagram with quasi-Fermi levels for a siliconp+-n step junction. The current densities in Figs. 12a, b, and c are 10, lo3, and lo4A/cm2, respectively. At 10 A/cm2 the diode is in the low-injection regime. Almost all of the potential drop occurs across the junction. The hole concentration in the n-side is small compared to the electron concentration. At lo3A/cm2 the electron concentration near the junction exceeds the donor concentration appreciably (bear in mind that from charge neutrality, injected carriers Ap = An). An ohmic potential drop appears on the n-side. At lo4A/cm2 we have very high injection; the poten- p-side n-side p-side n-side I/ / IE‘/ Fig. 12 Carrier concentrations and energy-band diagrams for a Sip+-njunction operated at different current densities. (a) 10 A/cm2.(b) lo3A/cm2. (c) lo4 A/cm2.Device parameters: NA = 1Ols ~ m -N~o,= 10I6~ m - ~T,,,= 3 ~ 1 0 - sl,~and zp = 8.4~10-sl.~(After Ref. 10.) 100 CHAPTER 2. p-n JUNCTIONS tial drop across the junction is insignificantcompared to ohmic drops on both sides of the neutral regions. Even though only the center region of the diode is shown in Fig. 12, it is apparent that the separation of the quasi-Fermi levels is equal to or less than the applied voltage (qV). From Fig. 12b and c, the carrier densities at the n-side of the junction are compa- rable ( n = p ) . Substituting this condition in Eq. 79, we obtain pn(x = WDn)= n,exp(q V/2kT). The current then becomes roughly proportional to exp(qV/2kT), as shown in Fig. 11, curve (c). At high-current levels we should consider another effect associatedwith the finite resistivity in the quasi-neutral regions. This resistance absorbs an appreciable amount of the applied voltage between the diode terminals. This is shown in Fig. 11 as curve-(d). One can estimate the series resistance from comparing the experimental curve to the ideal curve (AV= IR). The series resistance effect can be substantially reduced by the use of epitaxial materials (p+-n-n+). 2.3.4 Diffusion Capacitance The depletion-layer capacitance considered previously accounts for most of the junction capacitance when the junction is reverse-biased. When forward-biased,there is, in addition, a significantcontributionto junction capacitancefrom the rearrangement of minority carrier density, the so-called diffusion capacitance. In other words, the latter is due to the injected charge, while the former to the depletion-layer charge. When a small ac signal is applied to a junction that is forward-biased at a dc voltage V,and current density J,, the total voltage and current are defined by V(t) = V o + VlexpGwt), (80) J(t) = J,+J,exp(jwt) (8 1) where V, and J, are the small-signal voltage and current density, respectively. The imaginary part of the admittanceJl/Vl will give the diffusion conductanceand d i f i sion capacitance: Y = J-l E G,+jwC,. Vl The electron and hole densities at the depletion region boundaries can be obtained from Eqs. 53a and 53b by using [V,+ V,exp(jwt)] instead of V.We obtain for the n-side of the junction and Vl << V,, A similar expression can be obtained for the electron density in the p-side. The first term in Eq. 83 is the dc component, and the second term is the small-signal ac com- 2.3 CURRENT-VOLTAGE CHARACTERISTICS 101 in ponent. Substituting into the continuity equation (Eq. 158b of Chapter 1 with Gp= Z? = dE/& = 0) yields * join= - -Pz+npD &- i n dx2 (84) or Equation 85 is identical to Eq. 59 if the carrier lifetime is expressed as z* = z 1+ j u z p ' (86) We can then obtain the alternating current density from Eq. 63 by making the appropriate substitutions: with the ac component being From J1/Vl, both Gdand c d can be found and they are frequency dependent. For relatively low frequencies (wz,,wzn<< l), the diffusion conductance GdOis given by which has exactly the same value obtained by differentiating Eq. 63. The low-fre- quency diffusion capacitance Cdocan be obtained by using the approximation -/.+ = (1 + 0.5jwz) This diffusion capacitance is proportional to the forward current. For an n+-p onesided junction, it can shown that The frequency dependenceof the diffusion conductanceand capacitance is shown in Fig. 13 as a function of the normalized frequency wzwhere only one term in Eq. 88 102 CHAPTER 2. p-n JUNCTIONS Fig. 13 Normalized diffusion conductance and diffusion capacitance versus wz.Inset shows the equivalent circuit of ap-n junction under forward bias. is considered (e.g., the term containsp,, ifp,, >> npo).The inset shows the equivalent circuit of the ac admittance. It is clear from Fig. 13 that the diffusion capacitance decreases with increasing frequency. For high frequencies, c d is approximately proportional to w-"~T.he diffusion capacitance is also proportional to the dc current level [.c exp(qV&r)]. For this reason, c d is especially important at low frequencies and under forward-bias conditions. 2.4 JUNCTION BREAKDOWN When a sufficiently high field is applied to ap-n junction, the junction breab down and conducts a very large current." Breakdown occurs only in the reverse-bias regime because high voltage can be applied resulting in high field. There are basically three breakdown mechanisms: (1) thermal instability, (2) tunneling, and (3) avalanche multiplication. We consider the first two mechanisms briefly, and discuss avalanche multiplication in more detail. 2.4.1 Thermal Instability Breakdown due to thermal instability is responsible for the maximum dielectric strength in most insulators at room temperature, and is also a major effect in semiconductors with relatively small bandgaps (e.g., Ge). Because of the heat dissipation caused by the reverse current at high reverse voltage, the junction temperature increases. This temperature increase, in turn, increases the reverse current in comparison with its value at lower voltages. This positive feedback is responsible for breakdown. The temperature effect on the reverse current-voltage characteristics is explained in Fig. 14. In this figure the reverse currents Jo are represented by a family 2.4 JUNCTION BREAKDOWN 103 I I ) /b\\\ \ \ 50 35"30" 25" 22.5% 450 400 I \ / I Constant power I 103 102 " u 10' 1 10-1 v. (V) Fig. 14 Reverse current-voltagecharacteristics of thermal breakdown, where V , is the tum- over voltage. (Note decreasing values of coordinates.) (After Ref. 12.) of horizontal lines. Each line represents the current at a constant junction temperature, and the current varies as T3fUl2exp(-EJkZ'), as discussed previously. The heat dissipation hyperbolas which are proportional to the power, given by the I-Vproduct, are shown as sloped straight lines in the log-log plot. These lines also have to satisfy the curves of constant junction temperature. So the reverse current-voltage characteristics are obtained by the intersection points of these two sets of curves. Because of the heat dissipation at high reverse voltage, the characteristics show a negative differential resistance. In this condition, the diode will be destroyed unless some special measure such as a large series-limiting resistor is used. This effect is called thermal instability or thermal runaway. The voltage V , is called the turnover voltage. Forp-n junctions with relatively large saturation currents (e.g., in Ge), the thermal instability is important at room temperature, but at very low temperatures it becomes less important compared with other mechanisms. 2.4.2 Tunneling We next consider the tunneling effect (see Section 1S.7) when the junction is under a large reverse bias. It is well known that carriers can tunnel through a potential barrier if this barrier is sufficiently thin, induced by a large field as shown in Fig. 15a. In this particular case, the barrier has a triangular shape with the maximum height given by the energy gap. The derivation of the tunneling current of a p-n junction (tunnel diode) is considered in details in Chapter 8, and the result is given here as: Since the field is not constant, Z? is some average field inside the junction. 104 CHAPTER 2. p-n JUNCTIONS (a) Fig. 15 Energy band diagrams showing breakdown mechanisms of (a) tunneling and (b) avalanche multiplication (example initiated by hole current I,,). When the field approaches lo6Vlcm in Si, significant current begins to flow by means of this band-to-band tunneling process. To obtain such a high field, the junction must have relatively high impurity concentrationson both thep- and n-side. The mechanism of breakdown forp-n junctions with breakdown voltages less than about 4EJq is due to the tunneling effect. Forjunctions with breakdown voltages in excess of 6EJ9, the mechanism is caused by avalanche multiplication.At voltages between 4 and 6 EJq, the breakdown is due to a mixture of both avalanche and tunneling. Since the energy bandgaps Eg in Si and GaAs decrease with increasing temperature (refer to Chapter l), the breakdown voltage in these semiconductorsdue to the tunneling effect has a negative temperature coefficient; that is, the breakdown voltage decreases with increasing temperature. This is because a given breakdown current Jt can be reached at smaller reverse voltages (or fields) at higher temperatures (Eq. 92). This temperature effect is generally used to distinguish the tunneling mechanism from the avalanche mechanism, which has a positive temperature coefficient;that is, the breakdown voltage increases with increasing temperature. 2.4.3 Avalanche Multiplication Avalanche multiplication, or impact ionization, is the most-important mechanism in junction breakdown. The avalanchebreakdown voltage imposes an upper limit on the reverse bias for most diodes, on the collector voltage of bipolar transistors, and on the drain voltages of MESFETs and MOSFETs. In addition, the impact ionization mech- 2.4 JUNCTION BREAKDOWN 105 anism can be used to generate microwave power, as in IMPATT devices, and to amplify optical signals, as in avalanche photodetectors. We first derive the basic ionization integral which determines the breakdown con- dition. Assume that a current Ipo is incident at the left-hand side of the depletion region with width W, (Fig. 15b). If the electric field in the depletion region is high enough that electron-hole pairs are generated by the impact ionization process, the hole current Ip will increase with distance through the depletion region and reach a value MpIpoat x = W,. Similarly, the electron current I, will increase from I,@’,,) = 0 to I,@) = I - Ipo,where the total current I (= Ip + I,) is constant at steady state. The incremental hole current is equal to the number of electron-hole pairs gen- erated per second in the distance dx, dIp = Ipapdx+I,a,dx (93) or dI dx- ( a p - a,)~,= a , I . (94) The electron and hole ionization rates (a,and ap)have been considered in Chapter 1. The solution of Eq. 94 with the boundary condition of I = Ip( W,) = MJpo is given by* where Mp is the multiplication factor of holes and is defined as With a relationshipt Equation 95 can be evaluated at x = W, and be rewritten as * Equation 94 has the form y ’+ Py = Q, where y = Ip. The standard solution is where C is the constant of integration. 106 CHAPTER 2. p-n JUNCTIONS 1 -MP1 = r a p e x p [ - I ( a p - a,)a!xjh. (98) Note that Mp is a function of a, in addition to ap.The avalanche breakdown voltage is defined as the voltage where Mp approaches infinity. Hence the breakdown condition is given by the ionization integral r m a p e x p [ - I ( a p - a;,)kjcix = 1. (994 If the avalanche process is initiated by electrons instead of holes, the ionization inte- 1 gral is given by ~ a ; , e x p [ - ~ ( a , - a cpix ~= ~1 . (99b) Equations 99a and 99b are eq~ivalent;t'h~at is, the breakdown condition depends only on what is happening within the depletion region and not on the carriers (or primary current) that initiate the avalanche process. The situation does not change when a mixed primary current initiates the breakdown, so either Eq. 99a or Eq. 99b gives the breakdown condition. For semiconductors with equal ionization rates (a;,= ap= a) such as Gap, Eq. 99a or 99b reduces to the simple expression I""a k = 1. From the breakdown conditions described above and the field dependence of the ionization rates, the breakdown voltage, maximum electric field, and depletion-layer width can be calculated.As discussedpreviously, the electric field and potential in the depletion layer are determined from the solutions of the Poisson equation. Depletionlayer boundariesthat satis@ Eq. 99a or 99b can be obtainednumericallyusing an iteration method. With known boundaries we obtain the breakdown voltage for one-sided abruptjunctions, and The integral can be simplifiedto I eUdU = eu = exp y h ' . 2.4 JUNCTION BREAKDOWN 107 for linearly graded junctions, where N is the ionized background impurity concentration of the lightly doped side, a the impurity gradient, and the maximum field. Figure 16a shows the calculated breakdown voltage as a fbnction of N for abrupt junctions in Si, (100)-oriented GaAs, and Gap. The experimental results are generally in good agreement with the calculated ~ a 1 u e s .Tl ~he dashed line in the figure indicates the upper limit of N for which the avalanche breakdown calculation is valid. This limitation is based on the criterion of 6E#q. Above these corresponding values of N, the tunneling mechanism will contribute to the breakdown process and eventually dominates. In GaAs, the ionization rates and thus breakdown voltage depend on crystal orientations, besides doping concentration (refer to Chapter 1).I6At a doping concentration of around 10l6~ m - t~he, breakdown voltages are essentially independent of orientations. At lower dopings, V,, in (111) becomes the largest whereas at higher dopings, V,, in (100) is the largest. Figure 16b shows the calculated breakdown voltage versus the impurity gradient for linearly graded junctions. The dashed line indicates the upper limit of a for which the avalanche breakdown calculation is valid. The calculated values of the maximum field Em and the depletion-layer width at breakdown for the three semiconductors above are shown in Fig. 17a for the abrupt junctions, and in Fig. 17b for the linearly graded junctions. For the Si abrupt junctions, the maximum field at breakdown can be expressed asI7 gm = 4x105 Vlcm 1 - (1/3)10g,~(N/10'~~ m - ~ ) (103) where N is in ~ m - ~ . Because of the strong dependence of the ionization rates on the field, the maximum field at breakdown, sometimes called the critical$eld, varies very slowly with either N o r a (within a factor of 4 over many orders of magnitude in N and a). Thus, as a first approximation, we can assume that for a given semiconductor, if:mhas a fixed value. Then from Eqs. 101 and 102we obtain VBDoc N-'.O for abrupt junctions and VBDoc u-O.~ for linearly graded junctions. Figure 16 shows that the foregoing patterns are generally followed (within a factor of 3). Also as expected, for a given N o r a, the breakdown voltage increases with the energy bandgap of the material, since the avalanche process requires band-to-band excitations. It should be cautioned that the critical field is only a rough guide line but not a fundamental material property. It assumes a uniform field over a large distance. For example, if there is a high field but only occurring over a small distance, breakdown would not happen since Eq. 100 cannot be satisfied. Also, the total voltage (field times distance) needs to be larger than the bandgap for band-to-band carrier multiplication. An example is the high field but small voltage drop in an accumulation layer. 1000 C a 24 10 1 1014 1000 z 2Q 100 -3 > C z5 10 2 1015 10'6 1017 Impurity concentration N(crn") (a) 1' ' 1019 ' """' ' 1020 ' """' ' ' """' ' ' """' ' 102' 1022 1023 Impurity gradient a (cm-l) ' """' 1024 (b) Fig. 16 Avalanche breakdown voltage in Si, (100)-oriented GaAs, and Gap, for (a) one-sided abrupt junctions (vs. impurity concentration) and (b) linearly graded junctions (vs. impurity gradient). The dashed lines indicate the maximum doping or doping gradient beyond which tunneling will dominate the breakdown characteristics. (AEter Ref. 14.) 108 h % -& 100 4 10 eE c 2 .$ 1 L. e 3 A .* Y 3 0.1 nP 0.01 1014 1015 10'6 1017 Background doping N ( ~ r n - ~ ) (a) d 2106 i .3 105 E" 1018 Fig. 17 Depletion-layer width and maximum field at breakdown in Si, (100)-oriented GaAs, and GaP for (a) one-sided abrupt junctions and (b) linearly graded junctions. (After Ref. 14.) 109 110 CHAPTER 2. p-n JUNCTIONS An approximate universal expression can be given as follows for the results above comprising all semiconductors studied: vBDz60(&)312( N -314 1016 cm- V for abrupt junctions where Eg is the room-temperature bandgap in eV, and N is the background doping in ~ m - a~nd; for linearly graded junctions where a is the impurity gradient in cm4. For diffused junctions with a linear gradient near the junction and a constant doping on one side (Fig. 18 inset), the breakdown voltage lies between the two limiting cases considered previously'* (Fig. 16). As shown in Fig. 18, for large a, the breakdown voltage of these junctions is given by the abrupt junction results (bottom line); on the other hand, for small a, V,, will be given by the linearly graded junction results (parallel lines) and is independent of NB. In Figs. 16 and 17, it is assumed that the semiconductor layer is thick enough to support the maximum depletion-layer width W,, at breakdown. If, however, the semiconductor layer Wis smaller than W, (shown in Fig. 19, inset), the device will be punched through (i.e., the depletion layer reaches the n+ substrate) prior to breakdown. As the reverse bias increases further, the depletion width cannot continue to expand and the device will break down prematurely. The maximum electric field 8, 104 103 h L 2 1 02 l x l O ' s cm4 = a 2 5 1x10'6 2 5 I x 10'7 2 5 1x10'8 2 5 1x10'9 2 5 lXlO*O 2 10 10'3 1014 1015 1016 Background concentration NB( ~ r n - ~ ) Fig. 18 Breakdown voltage for Si diffused junctions at 300 K. The inset shows the spacecharge distribution. (After Ref. 18.) 2.4 JUNCTION BREAKDOWN 111 104. 1013 1014 1015 10'6 1017 Impurity concentration N(cm-3) Fig. 19 Breakdown voltage for Sip+-n-n+andp+-v-n+junctions, where zstands for lightly dopedp-typeand v for lightly doped n-type. Wis the thickness of the z- or v-region. is essentially the same as for the nonpunched-through diode. Therefore, the reduced breakdown voltage VLD for the punched-through diode, compared to a regular device with VBDfor the same doping, can be given by -V B-D - Shaded area in figure insert VBD ( gin wDm )I2 Punch-through usually occurs when the doping concentration N becomes sufficiently low as in ap+-n-n+orp+-v-n+diode, where nstands for a lightly dopedp-type and v for a lightly doped n-type semiconductor. The breakdown voltages for such diodes as calculated from Eq. 106 are shown in Fig. 19 as a function of the background doping for Si one-sided abrupt junction formed on epitaxial substrates (e.g., v on n+with the epitaxial-layer thickness Was a parameter). For a given thickness, the breakdown voltage approaches a constant value as the doping decreases, corresponding to the punch-through of the epitaxial layer. The results shown so far are for avalanche breakdowns at room temperature. At higher temperatures the breakdown voltage increases. A qualitative explanation of this increase is that hot carriers passing through the depletion layer under a high field lose part of their energy to optical phonons via scattering, resulting in a smaller ionization rate (see Fig. 24 of Chapter 1). Therefore, the carriers lose more energy to the crystal lattice along a given distance at a constant field. Hence, the carriers must pass through a greater potential difference (or higher voltage) before they can acquire sufficient energy to generate an electron-hole pair. The predicted values of V B Dnormal- 112 CHAPTER 2. p-n JUNCTIONS ized to the room-temperature value are shown in Fig. 20 for silicon. Note that there are substantial increases of the breakdown voltage, especially for lower dopings (or small gradient) at higher temperatures.20 Edge Effects. For junctions formed by a planar process, a very important junction curvature effect at the perimeter should be considered. A schematic diagram of a planar junction is shown in Fig. 21a. Note that at the perimeter, the depletion region is narrower and the field is higher. Since the cylindrical and/or spherical regions of the junction have a higher field intensity, the avalanche breakdown voltage is determined by these regions. The potential &r) and the electric field 8 ( r ) in a cylindrical or sphericalp-n junction can be calculated from Poisson equation: where n equals 1 for the cylindrical junction, and 2 for the spherical junction. The $lr solution for g(r)can be obtained from this equation and is given by 8(r) = r"p(r)dr+ - Cl rn J where rj is the radius of curvature of the metallurgical junction, and the constant C, must be adjusted so that the integration of the field is equal to the built-in potential. The calculated results for Si one-sided abruptjunctions at 300 K can be expressed by a simple equation:l 8 v,, 4 = [I1(772+2776/7)1n(+1277-8/7)- VBD (109) for cylindricaljunctions, and 5 = [ 772 + 2.14 7776'7 - ( 773 + 3 $3/7)2/3] VBD (110) for sphericaljunctions, where Vcr and Vspare the breakdown voltages of cylindrical and spherical junctions, respectively, VB,and WD,are the breakdown voltage and maximum depletion width of a plane junction having the same background doping, and 17 = rj/wD,,,. Figure 21b illustrates the numerical results as a function of 7. Clearly, as the radius of curvature becomes smaller, so does the breakdown voltage. However, for linearly graded cylindrical or spherical junctions, the calculated results show that the breakdown voltage is relatively independent of its radius of curvature.21 Another edge effect that causes premature breakdown is due to an MOS (metaloxide semiconductor) structure over the junction at the surface. Such a configuration is often called a gated diode. At certain gate biases, the field near the gate edge is higher than in the planar portion of the junction and breakdown changes location from the surface area of the metallurgical junction to the edge of the gate. This gatevoltage dependence of breakdown is shown in Fig. 22. At high positive gate bias on ap+-njunction, the p+-surface is depleted while the n-surface is accumulated. Breakdown occurs near the metallurgical junction at the surface. As the gate bias is swept I' II N = 10i4cm-3 1.5 h ?L 0 32 1 6 2 0.5 I 1 1 -Abrupt junctions - - - - Linearly graded junctions 0 0 100 200 300 400 500 6 I0 T (K) Fig. 20 Normalized avalanche breakdown voltage versus lattice temperature, in silicon. The breakdown voltage generally increases with temperature. (After Ref. 19.) Insulator J 0.7 0.6 '28 0.5 $ 0.4 P %' 0.3 2 0.2 0.1 \Cylindrical region Spherical region 001 .02 .04 .06 0.1 0.2 0.4 0.6 1.0 q=rjlWD,,, (c) Fig. 21 (a) A planar diffusion or implantation process forms a junction curvature near the edges of the mask with rj the radius of curvature. (b) Three-dimensional view of the junction curvature showing the spherical region at the corners. (c) Normalized breakdown voltage of cylindrical and spherical junctions as a function of the normalized radius of curvature. (After Ref. 18.) 113 114 CHAPTER 2. p-n JUNCTIONS 4 I - -150 -100 I I -50 0 Gate voltage V, (V) I 50 1 Fig. 22 Gate-voltage dependence of breakdown in a gated diode. The location of high-field breakdown shifts with gate bias. (After Ref. 22.) more negatively, the location of breakdown moves toward the n-side (to the right). In the middle gate-bias range, the breakdown voltage has a linear dependence on the gate bias, V,, = m V , + constant (111) and m I1. At some high negative gate bias, the field directly under the gate edge is high enough to cause breakdown, and the breakdown voltage collapses. This gateddiode breakdown phenomenon is reversible and the measurement can be repeated. To minimize this edge effect, the oxide thickness should be above a critical value.22This mechanism is also responsible for the gate-induced drain leakage (GIDL) of the MOSFET (see Section 6.4.5). 2.5 TRANSIENT BEHAVIOR AND NOISE 2.5.1 Transient Behavior For switching applications the transitions from forward bias to reverse bias and vice versa must be nearly abrupt and the transient time short. For ap-n junction, while the latter is reasonably fast, the response from forward to reverse is limited by minoritycarrier charge storage. Figure 23a shows a simple circuit in which a forward current IFflows in thep-n junction; at time t = 0, the switch S is suddenly thrown to the right, 2.5 TRANSIENT BEHAVIOR AND NOISE 115 Fig. 23 Transient behavior of ap-njunction. (a) Basic switching circuit. (b) Transient current response. (c) Minority-carrier distribution outside depletion edge for various time intervals. (d) Transientjunction-voltage response. (After Ref. 24.) and an initial reverse current 1, = (VR- V,)/R flows. The transient time is defined as the time in which the current drops to 10% of the initial reverse current ZR,and is equal to the sum of tl and t2 as shown in Fig. 23b, where tland t2 are the time intervals for the constant-current phase and the decay phase, respectively. Consider the constant-current phase (also called storage phase) first. The continuity equation as given in Chapter 1 can be written for the n-type side of ap+-njunction (ppo >> n,,) as The boundary conditions are that at t = 0 the initial distribution of holes is a steadystate solution to the diffusion equation, and that under forward bias the voltage across the junction is given from Eq. 53b as The distribution of the minority-carrier densityp, with time is shown in Fig. 23c. From Eq. 113 it can be calculated that, as long as p,(O,t) is greater than pno(in the 5 interval 0 < t < t,), the junction voltage remains of the order of kTlq, as shown in Fig. 23d. In this time interval the reverse current is approximately constant and we 116 CHAPTER 2. p-n JUNCTIONS have the constant-current phase. The solution of the time-dependent continuity equation gives t, by the transcendentalequations24 d: 7 erf - = 1 1 +(ZR/IF) However, an explicit expression for t , can be obtained, using a charge-control model which can also provide some insight into the problem. The stored minority- s carrier charge in the lightly doped side is given by the integral Qs = q A A P n h . (115) Integration of the continuity equation, after the current is switched to the reversed mode, becomes With the initial condition given by the forward current Qs(0)= ZF5t,he solution is given by .[ Q J t ) = z - Z R + ( Z F + Z R )exP(:)]. By setting Qs= 0, t, can be obtained as A comparison of Eq. 118 to the exact solution of Eq. 114 shows that this estimate gives higher values by a factor of = 2 for Z d I R = 0.1 and = 20 for ZF/IR = 10. After t l , the hole density starts to decrease below its equilibrium value pno.The junction voltage tends to reach - VRand a new boundary condition now holds. This phase is the decay phase with the initial boundary condition p,(O,t,) =pno.The solution for t2 is given by another transcendental equation The total results for t , and t2 are shown in Fig. 24 where the solid lines are for the plane junction with the length of the n-type material Wmuch greater than the diffusion length (W>> L J , and the dashed lines are for the narrow-base junction with W<< Lp.For a large ZR/ZF ratio, the transient time can be approximatedby 21 for W>> Lp,or 2.5 TRANSIENT BEHAVIOR AND NOISE 117 ;,(liLq - 7 10-2 lo-‘ 1 10‘ 10 2 103 Reverse current/Forward current (IRIIF) Fig. 24 Normalized time versus the ratio of reverse current to forward current. Wis width of the n-region in ap+-njunction. (After Ref. 24.) for W<< L,. For example, if one switches a junction (of W>> L,) from forward 10 mA to reverse 10 mA (ZR/ZF = I), the time for the constant-current phase is 0.3zp, and that for the decay phase is about 0.62,. Total transient time is then 0.9%.A fast switch requires that zpbe small for all cases. The lifetime 2, can be substantially reduced by introducing impurities with deep levels in the forbidden gap, such as gold in silicon. 2.5.2 Noise The term “noise” refers to spontaneous fluctuations in the current passing through, or the voltage developed across, semiconductor bulk materials or devices. Since semiconductor devices are mainly used to amplify small signals or to measure small physical quantities, spontaneous fluctuations in current or voltage set a lower limit to these signals. It is important to know the factors contributing to these limits, to use this knowledge to optimize operating conditions, and to find new methods and new technologies to reduce noise. Observed noise is generally classified into (1) thermal noise or Johnson noise, ( 2 ) flicker noise, and (3) shot noise. Thermal noise occurs in any conductor or semiconductor device and is caused by the random thermal motion of the current carriers. It 118 CHAPTER 2. p-n JUNCTIONS is also called white noise because its level is the same at all frequencies. The open- circuit mean-square voltage of thermal noise is given by25>26 (c)= 4kTBR (122) where B is the bandwidth in Hz, and R the real part of the dynamic impedance (dV/dQ between terminals. At room temperature, for a semiconductor device with 1 WZ resis- tance, the root-mean-square voltage measured with a 1-Hz bandwidth is only about 4 nV. Flicker noise is distinguished by its peculiar spectral distribution which is propor- tional to llf" with a generally close to unity (the so-called llfnoise). Flicker noise is thus important at lower frequencies. For most semiconductor devices, the origin of flicker noise is the surface effect. The llfnoise-power spectrum has been correlated both qualitatively and quantitatively with the lossy part of the metal-insulator-semi- conductor (MIS) gate impedance due to carrier recombination at the interface traps. Shot noise is due to the discreteness of charge carriers that contribute to current flow, and it constitutes the major noise in most semiconductor devices. It is indepen- dent of frequency (white spectrum) at low and intermediate frequencies. At higher frequencies the shot-noise spectrum also becomes frequency-dependent. The mean- square noise current of shot noise for ap-n junction is given by (i,3 = 2qBIA (123) where I can be forward or reverse current. For low injection the total mean-square noise current (neglecting llf noise) is the sum From the Shockley equation we obtain Substituting Eq. 125 into Eq. 124 yields for the forward-bias condition, [ r3 1 qv, (i:) = 4qZoBexp + 2qZoB exp - - 1 (kT) Experimental measurements indeed confirm that the mean-square noise current is proportional to the saturation current I,, which can be increased by irradiation. 2.6 TERMINAL FUNCTIONS A p-n junction is a two-terminal device that can perform various terminal functions, depending upon its biasing condition as well as its doping profile and device geometry. In this section we discuss briefly some interesting device performances based on 2.6 TERMINAL FUNCTIONS 119 its current-voltage, capacitance-voltage, and breakdown characteristics discussed in previous sections. Many other related two-terminal devices will be considered in subsequent chapters (e.g., tunnel diode in Chapter 8 and IMPATT diode in Chapter 9). 2.6.1 Rectifier A rectifier is a two-terminal device that gives a very low resistance to current flow in one direction and a very high resistance in the other direction, i.e., it allows current in only one direction. The forward and reverse resistances of a rectifier can be derived from the current-voltage relationship of a practical diode, where I,, is the saturation current and the ideality factor generally has a value between 1 (for difhsion current) and 2 (for recombination current). The forward dc (or static) resistance R, and small-signal (or dynamic) resistance rF are obtainable from Eq. 127: The reverse dc resistance RRand small-signal resistance rRare given by Comparing Eqs. 128-131 shows that the dc rectification ratio RRIRFvaries with the factor (vR/V,)exp(qV,/VkT), while the ac rectification ratio i-R/rF varies with (IdlO)exp(ql 'R1/VkT). p-n junction rectifiers generally have slow switching speeds; that is, a significant time delay is necessary to obtain high impedance after switching from the forwardconduction state to the reverse-blocking state. This time delay (proportional to the minority-carrier lifetime as shown in Fig. 24) is of little consequence in rectifying 60-Hz currents. For high-frequency applications, the lifetime should be sufficiently reduced to maintain rectification efficiency. The majority of rectifiers have powerdissipation capabilities from 0.1 to 10 W, reverse breakdown voltages from 50 to 2500 V (for a high-voltage rectifier two or more p-n junctions are connected in series), and switching times from 50 ns for low-power diodes to about 500 ns for high-power diodes. A rectifier has many circuit application^.^^ It is used to transform ac signals into different specials waveforms. Examples are half-wave and full-wave rectifiers, 120 CHAPTER 2. p-n JUNCTIONS clipper and clamper circuits, peak detector (demodulator), etc. It can also be used as a ESD (electrostatic discharge) protection device. 2.6.2 Zener Diode A Zener diode (also called voltage regulator) has a well-controlled breakdown voltage,calledthe Zener voltage,with sharpbreakdown characteristicsin the reversebias region. Prior to breakdown, the diode has a very high resistance; after breakdown the diode has a very small dynamic resistance. The terminal voltage is thus limited (or regulated) by the breakdown voltage, and this is used to establish a fixed reference voltage. Most Zener diodes are made of Si, because of the low saturation current in Si diodes and the advanced Si technology. They are special p-n junctions with higher doping concentrations on both sides. As discussed in Section 2.4, for breakdown voltage V, larger than 6EJq (= 7 V for Si), the breakdown mechanism is mainly avalanche multiplication, and the temperature coefficient of V, is positive. For V,, < 4EJq (= 5 V for Si), the breakdownmechanism is band-to-band tunneling, and the temperature coefficient of V,, is negative. For 4EJq < V, < 6EJq, the breakdown is due to a combination of these two mechanisms. One can connect, for example, a negative-temperature-coefficient diode in series with a positive-temperature-coefficient diode to produce a temperature-independent regulator (with a temperature coefficient of the order of 0.002% per "C),which is suitable as a voltage reference. 2.6.3 Varistor A varistor (variable resistor) is a two-terminal device that shows nonohmic behavior, i.e., voltage-dependent resistance.**Equations 128 and 129 show the nonohmic characteristics of ap-n junction diode in the forward-biasregion. Similar nonohmic characteristics are obtainable from metal-semiconductor contacts considered in Chapter 3. An interesting application of varistors is their use as a symmetrical fractional-voltage (= 0.5 V) limiter by connecting two diodes in parallel, oppositely poled. The two-diode unit will exhibit the forward I- Vcharacteristicsin either direction. A varistor, being a nonlinear device, is also useful in microwave modulation, mixing, and detection (demodulation).Varistors based on metal-semiconductorcontacts are more common due to their higher speed from the absence of minority-charge storage. 2.6.4 Varactor The term varactor comes from variable reactor and means a device whose reactance (or capacitance) can be varied in a controlled manner with a dc bias voltage. Varactor diodes are widely used in parametric amplification, harmonic generation, mixing, detection, and voltage-variabletuning. For this application,the forward bias is to be avoidedbecause of excessivecurrent which is undesirablefor any capacitor. The basic capacitance-voltagerelationships in 2.6 TERMINAL FUNCTIONS 121 reverse bias have already been derived in Section 2.2. We shall now extend the previous derivations of abrupt and linearly graded doping distributions to a more general case. The one-dimensional Poisson equation is given as where N is the generalized doping distribution (negative sign for donors) as shown in Fig. 25a (assuming one side is heavily doped): N = Bxm for x20. (133) For m = 0 we have N = B, corresponding to the uniformly doped (or one-sided abrupt junction) case. For m = 1 , the doping profile corresponds to a one-sided linearly graded case. For m < 0, the device is called a "hyper-abrupt" junction. The hyper- abrupt doping profile can be achieved by an epitaxial process or by ion implantation. The boundary conditions are @ ,I = 0) = 0 and +I+ = W,) = VR+ vbiw,here VRis the applied reverse voltage and tybi is the built-in potential. Integrating the Poisson equa- tion with the boundary conditions, we obtain for the depletion-layer width and the dif- ferential capacitance per unit area29 [ I ' + E,( m 2)( VR+ tybi) 2, + wD = qB (134) 1 SE- m+2' One important parameter in characterizing the varactor is the sensitivity defined by30 A I Abrupot s = 112 junction \ 0 0 X Fig. 25 (a) Various impurity distributions (normalized at xo)for varactors. (b) Log-log plot of depletion-layer capacitance versus reverse bias. (After Refs. 29 and 30.) 122 CHAPTER 2. p-n JUNCTIONS The larger the s, the larger will be the capacitance variation with biasing voltage. For linearly graded junctions, m = 1 and s = W3; for abrupt junctions, m = 0 and s = 112; for hyper-abruptjunction with m = -1, -312, or -513, the value of s is 1,2, or 3, respectively. The capacitance-voltage relationships for these junction diodes are shown in Fig. 25b. The hyper-abruptjunction, as expected, has the highest sensitivity and gives rise to the largest capacitance variation. 2.6.5 Fast-Recovery Diode Fast-recovery diodes are designed to give ultrahigh switching speed. The devices can be classified into two types: p-n junction diodes and metal-semiconductor diodes. The general switching behavior of both types can be described by Fig. 23b. The total recovery time ( t l + t2) for ap-n junction diode can be substantially reduced by intro- ducing recombination centers, such as Au in Si, to reduce the carrier lifetime. Although the recovery time is directly proportional to the lifetime z, as shown in Fig. 24, it is not possible, unfortunately, to reduce the recovery time indefinitely by introducing an extremely large number of recombination centers N,, because the reverse generation current of ap-n junction is proportional to Nt (Eqs. 66 and 67). For direct bandgap semiconductors, such as GaAs, the minority-carrier lifetimes are generally much smaller than that of Si. This results in ultra-high-speed GaAsp-n junction diodes with recovery times of the order of 0.1 ns or less. For Si the practical recovery time is in the range of 1 to 5 ns. The metal-semiconductor diodes (Schottky diodes) fundamentally exhibit ultrahigh-speed characteristics, because they are majority-carrier devices and the minority-carrier storage effect is negligible. We discuss metal-semiconductor contacts in detail in Chapter 3. 2.6.6 Charge-Storage Diode In contrast to fast-recovery diodes, a charge-storage diode is designed to store a charge while conducting in the forward direction and, upon switching to the reverse direction, to conduct a reverse current for a short period. A particularly interesting charge-storage diode is the step-recovery diode (also called the snapback diode) that conducts in the reverse direction for a short period and then abruptly cuts off the current as the stored charge has been dissipated. In other words, it is desirable here to reduce the decay phase or t2 without shortening the storage phase or t,. Most chargestorage diodes are made from Si with relatively long minority-carrier lifetimes ranging from 0.5 to 5 ps. Note that the lifetimes are about 1000 times longer than for fast-recoverydiodes. The mechanism to reduce the decay phase is by a special doping profile such that the injected charge is confined closer to the junction. This cutoff occurs in the range of picoseconds and results in a fast-rising wavefront which is rich in harmonics. Because of these characteristics, step-recovery diodes are used in harmonic generation and pulse shaping. 2.6 TERMINAL FUNCTIONS 123 2.6.7 p-i-n Diode Ap-i-n diode is ap-n junction with an intrinsic layer (i-region) sandwiched between the p-layer and the n-layer. In practice, however, the idealized i-region is approximated by either a high-resistivity p-layer (referred to as z-layer) or a high-resistivity n-layer (v-layer). Thep-i-n diode has found wide applications in microwave circuits. Its special feature is a wide intrinsic layer that provides unique properties such as low and constant capacitance, high breakdown voltage in reverse bias, and most interestingly, as a variolosser (variable attenuator) by controlling the device resistance which varies approximately linearly with the forward bias current. The switching time is approximately given by W/2vs,where Wis the width of the i - r e g i ~ n .I~t 'can modulate signals up to the GHz range. Furthermore, the forward characteristics of a thyristor (refer to Chapter 1I ) in its on-state closely resemble those of ap-i-n diode. At near zero or low reverse bias, the lightly doped intrinsic layer starts to be fully depleted, and the capacitance is given by c = -ES . W Once fully depleted, its capacitance is independent of reverse bias. Figure 19 gives the breakdown voltage of a p-i-n diode under reverse bias. Since there is little net charge within the intrinsic layer, the electric field is constant and the breakdown voltage can be estimated by VBD= Emw (139) where the maximum breakdown field FZm for Si at lower dopings is about 2 . 5 ~ 1 0V~lcm. These two equations show that the width of the i-region Wcontrols the trade-off between frequency response and power (from maximum voltage). Under forward conditions, holes are injected from thep-region and electrons from the n-region. As the injected carrier densities are nearly equal (and uniform) due to charge neutrality, they are much higher than the i-region doping concentration, so the p-i-n diode is generally operated in the high-injection condition, Ap = An >> ni. The current conduction is via recombination within the i-region and is given by (see Eq. 74) JO For a detailed discussion of the dc I-V characteristics, the readers are referred to Section 11.2.4. The most interesting phenomenon for ap-i-n diode, however, is for small signals at high frequencies (> ll2zi.z) at which the stored carriers within the intrinsic layer are not completely swept away by the RF signal or by recombination. At these frequen- cies there is no rectification and the p-i-n diode behaves like a pure resistor whose value is determined solely by the injected charge, proportional to the dc bias current. This dynamic RF resistance is simply given by 124 CHAPTER 2. p-n JUNCTIONS Here the relationshipJF = qWAnlzhas been assumed. The RF resistance is controlled by the dc bias current, and typical characteristics are shown in Fig. 26. 2.7 HETEROJUNCTIONS Some properties of heterojunctions have been discussed in Section 1.7.When the two semiconductors have the same type of conductivity, the junction is called an isotype heterojunction. When the conductivity types differ, the junction is called an anisotype heterojunction which is a much more useful and common structure than its counterpart. In 1951, Shockley proposed the abrupt heterojunction to be used as an efficient emitter-base injector in a bipolar t r a n ~ i s t o rI.n~t~he same year, Gubanov published a theoretical paper on heterojun~tionsK.~ro~emer later analyzed a similar, although graded, heterojunction as a wide-bandgap emitter.35Since then, heterojunctions have been extensively studied, and many important applications have been made, among them the room-temperature injection laser, light-emitting diode (LED), photodetector, and solar cell, to name a few. In many of these applications, by forming periodic heterojunctions with layer thickness of the order of 10 nm, we utilize the interesting properties of quantum wells and superlattices. Additional information on heterojunctions can be found in Refs. 36-39. 2.7.1 Anisotype Heterojunction The energy-band model of an idealized anisotype abrupt heterojunction without interface traps was proposed by Anderson40based on the previous work of Shockley. We consider this model next, since it can adequately explain most transport processes, dc bias current (mA) Fig. 26 Typical RF resistance as a 12 function of dc forward current. (After Ref. 32.) 2.7 HETEROJUNCTIONS 125 and only slight modification of the model is needed to account for nonideal cases such as interface traps. Figures 27a and c show the energy-band diagrams of two isolated semiconductors of opposite types. The two semiconductors are assumed to have dif- ferent bandgaps Eg,different permittivities E,, different work functions &,, and dif- x. ferent electron affinities Work function and electron affinity are defined as the energy required to remove an electron from the Fermi level EF and from the bottom of the conduction band E,, respectively, to a position just outside the material (vacuum level). The difference in energy of the conduction-band edges in the two semiconductors is represented by AE, and that in the valence-band edges by AE, The Vacuum level 1 Vacuum level + - - -,-+- ;- Vacuum level -- Vacuum level Fig. 27 Energy-banddiagrams for (a) two isolated semiconductors of opposite types and different Eg(of which the smaller bandgap is n-type) and (b) their idealized anisotype heterojunction at thermal equilibrium. In (c) and (d), the smaller bandgap is p-type. In (b) and (d), the dashed lines across the junctions represent graded composition. (After Ref. 40.) 126 CHAPTER 2. p-n JUNCTIONS electron affinity rule (AE,= SAX) shown in Figure 27 may not be a valid assumption in all cases. However, by choosing AE, as an empirical quantity, the Anderson model remains satisfactory and ~ n a l t e r e d . ~ ' When a junction is formed between these semiconductors, the energy-band profile at equilibrium is as shown in Fig. 27b for an n-p anisotype heterojunction where, in this example, the narrow-bandgap material is n-type. Since the Fermi level must coincide on both sides in equilibrium and the vacuum level is everywhere parallel to the band edges and is continuous, the discontinuity in the conduction-band edges (AEc)and valence-band edges (AE,)is invariant with doping in those cases x where Eg and are not functions of doping (i.e., nondegenerate semiconductors). The total built-in potential v b j is equal to the sum of the partial built-in voltages ($vbl+ $vb2), where v b l and v b 2 are the electrostatic potentials supported at equilibrium by semiconductors 1 and 2, respectively.; From Fig. 27, it is apparent that since at equilibrium, EF1= Em, the total built-in potential is given by I vbi = @m 1 - @m21. (142) The depletion widths and capacitance can be obtained by solving the Poisson equation for the step junction on either side of the interface. One boundary condition is the continuity of electric displacement, that is, g1= S2= E ~ ~ ' &=' ~cS2E2at the interface. We obtain (143a) (143b) and qNDlNA2'slEs2 cD = [ 2 ( E s 1 N D I + ' ~ 2 ~ , 4 2 v) (b i - v) The relative voltage supported in each semiconductor is -v b-l -- ' 1 - NA2Es2 V b 2 - '2 NDIEsl (145) where the applied voltage is divided into the two regions V = Vl + V2.It is apparent that the foregoing expressions will reduce to the expression for the p-n junction (homojunction) discussed in Section 2.3, when both sides of the heterojunction become the same materials. In considering the current flow, the example in Fig. 27b shows that the conduc- tion-band edge E , increases monotonically while the valence-band edge E , goes through some peak near the junction. The hole current could become complicated * The convention is to list the material with the smaller bandgap as the first symbol. 2.7 HETEROJUNCTIONS 127 because of the added barrier which might present a bottle-neck in thermionic emission, in series with diffusion. The analysis can be greatly simplified by assuming a graded junction where AEc and AEv become smooth transitions inside the depletion region. With this assumption, the difision currents are similar to a regularp-n junction but with the appropriate parameters in place. The electron and hole diffusion currents are: ( 146a) (146b) Note that the band offsets AEc and AEv are not in these equations, and also that each diffusion current component depends on the properties of the receiving side only, as in the case of a homojunction. The total current becomes Of particular interest is the ratio of the two diffusion currents. Therefore the injection ratio depends exponentially on the bandgap difference, in addition to their doping ratio. This is critical in designing a bipolar transistor where the injection ratio is directly related to the current gain. The heterojunction bipolar transistor (HBT) uses a wide-bandgap emitter to suppress the base current and will be discussed in more details in Chapter 5 . 2.7.2 Isotype Heterojunction The case of an isotype heterojunction is somewhat different. In an n-n heterojunction, since the work function of the wide-bandgap semiconductor is smaller, the energy bands will be bent oppositely to those for the n-p case (Fig. 28a).42 The relation between ( yb,- Vl) and (yb2- V2)can be found from the boundary condition of continuity of electric displacement (9= sSZ7)at the interface. For an accumulation (increase of carriers at the interface) in Region-1 governed by Boltzmann statistics, the electric field at xois given by (for detailed derivation see footnote on p. 84) The electric field at the interface for a depletion in Region-2 is given by 128 CHAPTER 2. p-n JUNCTIONS n-Ge -1p" EF t n-GaAs 1 Region-1 Region-2 I Region-1 Region-2 (a) (b) Fig. 28 Energy-band diagrams for ideal (a) n-n and (b)p-p isotype heterojunctions. (After Refs. 40 and 42.) Equating the electric displacement 9= 8 :of~Eq~s. 149 and 150 gives a relation between (vbl- Vl) and (vb2 - V2)that is quite complicated. However, if the ratio E ~ ~ N ~is~ofIthEe or~de~r ofNun~ity~and v/bj(= v/bl+ vb2) >> kTlq, we obtain42 where Vis the total applied voltage and is equal to (Vl + V2)A. lso shown in Fig. 28b is the idealized equilibrium energy-band diagram forp-p heterojunctions. For the carrier transport, because of the potential barrier as shown in Fig. 28a, the conduction mechanism is governed by thermionic emission of majority carriers, electrons in this case (refer to Chapter 3 for details). The current density is given bf2 J = q N D 22 mF e; x p (-~4 )vb[2e x p r $ ) - e x p ( - s ) ] . Substituting Eq. 151 into Eq. 152 yields the current-voltage relationship: Since the current is thermionic emission as in a metal-semiconductor contact, the preexponential factor is often expressed in terms of the effective Richardson constant A" and the barrier height 4,,. With substitution for A" and the appropriate expression for ND2,the current equation above becomes REFERENCES 129 J=- * T( 1 - L)exp(-=) [,,( 9 exp(-@) - 11 k vb i kT = JoPP(9- 11 (154) This expression is quite different from that for metal-semiconductor contact. The value of J, is different [fromA*Pexp(-q&kT)] and so is its temperature dependence. The reverse current never saturates but increases linearly with voltage at large - K In the forward direction, the dependence of J on V can be approximated by an exponential function Joc exp(qV/qkT). REFERENCES 1. W. Shockley, “The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors,” Bell Syst. Tech. J., 28,435 (1949); 2. W. Shockley, Electrons and Holes in Semiconductors, D. Van Nostrand, Princeton, New Jersey, 1950. 3. C. T. Sah, R. N. Noyce, and W. Shockley, “Carrier Generation and Recombination in p-n Junction andp-n Junction Characteristics,” Proc. IRE, 45, 1228(1957). 4. J. L. Moll, “The Evolution of the Theory of the Current-Voltage Characteristics of p-n Junctions,” Proc. IRE, 46, 1076(1958). 5. C. G. B. Garrett and W. H. Brattain, “Physical Theory of Semiconductor Surfaces,” Phys. Rev., 99, 376 (1955). 6. C. Kittel and H. Kroemer, 7’hermal Physics, 2nd Ed., W. H. Freeman and Co., San Francisco, 1980. 7. W. C. Johnson and P. T. Panousis, “The Influence of Debye Length on the C-VMeasurement of Doping Profiles,” ZEEE Trans.Electron Devices, ED-18,965 (1971). 8. B. R. Chawla and H. K. Gummel, “Transition Region Capacitance of Difhsedp-n Junctions,” IEEE Trans. Electron Devices, ED-18, 178 (1971). 9. M. Shur, Physics of SemiconductorDevices, Prentice-Hall, Englewood Cliffs, New Jersey, 1990. 10. H. K. Gummel, “Hole-Electron Product of p-n Junctions,” Solid-state Electron., 10, 209 (1 967). 11. J. L. Moll, Physics of Semiconductors, McGraw-Hill, New York, 1964. 12. M. J. 0.Strutt, SemiconductorDevices, Vol. 1,Semiconductorand Semiconductor Diodes, Academic, New York, 1966, Chapter 2. 13. P. J. Lundberg, private communication. 14. S. M. Sze and G. Gibbons, “Avalanche Breakdown Voltages of Abrupt and Linearly Gradedp-n Junctions in Ge, Si, GaAs, and Gap,” Appl. Phys. Lett., 8, 111 (1966). 15. R. M. Warner, Jr., “Avalanche Breakdown in Silicon Diffused Junctions,” Solid-state Elec- tron., 15, 1303 (1972). 16. M. H. Lee and S. M. Sze, “Orientation Dependence of Breakdown Voltage in GaAs,” Solid-state Electron., 23, 1007 (1980). 130 CHAPTER 2. p-n JUNCTIONS 17. F. Waldhauser, private communication. 18. S. K. Ghandhi, Semiconductor Power Devices, Wiley, New York, 1977. 19. C. R. Crowell and S. M. Sze, “Temperature Dependence of Avalanche Multiplication in Semiconductors,” Appl. Phys. Lett., 9, 242 (1966). 20. C. Y. Chang, S. S. Chiu, and L. P. Hsu, “Temperature Dependence of Breakdown Voltage in Silicon Abruptp-n Junctions,” IEEE Trans. Electron Devices, ED-18,391 (1971). 2 1. S. M. Sze and G. Gibbons, “Effect of Junction Curvature on Breakdown Voltages in Semi- conductors,” Solid-state Electron., 9,831 (1966). 22. A. Rusu, 0. Pietrareanu, and C. Bulucea, “Reversible Breakdown Voltage Collapse in Silicon Gate-Controlled Diodes,” Solid-state Electron., 23,473 (1980). 23. A. S. Grove, 0. Leistiko, Jr., and W. W. Hooper, “Effect of Surface Fields on the Break- down Voltage of Planar Siliconp-n Junctions,” IEEE Trans. Electron Devices, ED-14, 157 (1967). 24. R. H. Kingston, “Switching Time in Junction Diodes and Junction Transistors,” Proc. IRE, 42, 829 (1954). 25. A. Van der Ziel, Noise in Measurements, Wiley, New York, 1976. 26. A. Van der Ziel and C. H. Chenette, “Noise in Solid State Devices,” in Advances in Electronics andElectron Physics, Vol. 46, Academic, New York, 1978. 27. K. K. Ng, Complete Guide to Semiconductor Devices, 2nd Ed., Wiley, New York, 2002. 28. J. P. Levin, “Theory of Varistor Electronic Properties”, Crit. Rev. Solid State Sci., 5, 597 (1975). 29. M. H. Nonvood and E. Shatz, “Voltage Variable Capacitor Tuning-A Review,” Proc. IEEE, 56,788 (1968). 30. R. A. Moline and G. F. Foxhall, “Ion-Implanted Hyperabrupt Junction Voltage Variable Capacitors,” ZEEE Trans. Electron Devices, ED-19,267 (1972). 3 1. G. Lucovsky, R. F. Schwarz, and R. B. Emmons, “Transit-Time Considerations in p-i-n Diodes,” J. Appl. Phys., 35,622 (1964). 32. A. G. Milnes, Semiconductor Devices and Integrated Electronics, Van Nostrand, New York, 1980 33. W. Shockley, US.Patent 2,569,347 (1951). 34. A. I. Gubanov,Zh. Tekh.Fiz., 21, 304(1951);Zh. Eksp. Teor.Fiz., 21, 721 (1951). 35. H. Kroemer, “Theory of a Wide-Gap Emitter for Transistors,” Proc. IRE,45, 1535 (1957). 36. H. C. Casey, Jr., and M. B. Panish, Heterostructure Lasers, Academic, New York, 1978. 37. A. G. Milnes and D. L. Feucht, Heterojunctions and Metal-Semiconductor Junctions, Academic, New York, 1972. 38. B. L. Sharma and R. K. Purohit, Semiconductor Heterojunctions, Pergamon, London, 1974. 39. P. Bhattacharya, Ed., III-V Quantum Wellsand Superlattices, INSPEC, London, 1996. 40. R. L. Anderson, “Experiments on Ge-GaAs Heterojunctions,” Solid-state Electron., 5,341 (1962). 41. W. R. Frensley and H. Kroemer, “Theory of the Energy-Band Lineup at an Abrupt Semiconductor Heterojunction,” Phys. Rev.B, 16, 2642 (1977). 42. L. L. Chang, “The Conduction Properties of Ge-GaAs,-xP, n-n Heterojunctions,” SolidState Electron., 8, 721 (1965). PROBLEMS PROBLEMS 131 1. A siliconp-njunction of 1 cm2area consists of a two-sided step junction with an n-region ---k;;; of 10'' donors/cm3and ap-region of 2 ~ 1 0a'c~ceptors/cm3. All donors and acceptors are ionized. Find the built-in potential. 2. The measured depletion capacitance of a p+-n silicon junction (formed in an n-type epitaxial layer) is shown. The device area is cm2 and the p+-layer thickness is 0.07 pm. Find the thickness of the epitaxial layer. -3 -2 -1 0.95V 3. A silicon p-n junction has a linearly graded junction on the p-side with an impurity gradient of IOl9 cm4, and a uniform doping of 3 ~ 1 0~' ~m o-n t~he n-side. (a) Ifthe depletion width of thep-side is 0.8 pm at zero bias, find the total depletion width, the built-in potential and the maximum field at thermal equilibrium. (b) Plot the impurity and field distribution of this junction. 4. Find the depletion-layer width and the maximum field at thermal equilibration for the p+-nl-n2structure. 0.2 pm 5. (a) A silicon p+-n junction has the following parameters at 300 K: 5= ig = 10" s, No = 1015~ m -F~in.d the generation current density in the depletion region and the total reverse current density at a bias of 5 V. (b) Will there be any significant change of the total reverse current density if zpis reduced by a factor of 100 while igremains the same? 6. Ap+-njunction is formed in an n-type substrate with No = l O I 5 ~ r n - I~f.the junction contains 1OI5 ~ m g-ene~ration-recombination centers located 0.02 eV above the intrinsic Fermi level of silicon with o,= op= cm2 (uth= lo7 cm/s), calculate the generation and recombination current at -0.5 V. 7. For ap-n junction with thep-side doped to IxlOl7 ~ m - t~he, n-side doped to 1 ~ 1 0~' m~ - ~ , and a reverse bias of -2 V, calculate the generation-recombination current density, assuming that the effective lifetime is 1x 10-5 s. 8. Design an abrupt Sip+-njunction diode that has a reverse breakdown voltage of 130 V and has a forward-bias current of 2.2 mA at V = 0.7 volt. Assume 5 = lo-' s. 9. (a) Assume a = U,,(Z%~)~ where ao,go,and rn are constants. Also assume a, = ap= a. Derive an expression for the avalanche breakdown voltage of an n+-pjunction with a uniform acceptor concentration N, and a dielectric permittivity E ~ . (b) If a. = lo4cm-I, go= 4x105V/cm, m = 6, NA= 2x1Ol6~ m an- d~.sS=10-l2 Fkm, what is the breakdown voltage? 132 CHAPTER 2. p-n JUNCTIONS 10. When a silicon p+-njunction is reverse-biased to 30 V, the depletion-layer capacitance is 1.75 nF/cm2. If the maximum electric field at avalanche breakdown is 3.1x 1O5 V/cm, find the breakdown voltage. 11. A silicon junction diode has a doping profile ofp+-i-n+-i-n+which contains a very narrow n+-region sandwiched between two i-regions. This narrow region has a doping of 10l8~ m a-nd~a width of 10 nm. The first i-region has a thickness of 0.2 pm, and the second i-region is 0.8 pm in thickness. Find the electric field in the second i-region (i.e., in the n+-i-n+)when a reverse bias of 20 V is applied to the junction diode. p + i n 12. For a silicon one-sidedp+-n-n+abruptjunction with a donor concentration of 5x1Ol4~ m - ~ , the maximum field at breakdown is 3x 1O5 V/cm. If the thickness of the n-type epitaxial layer is reduced to 5 pm, find the breakdown voltage. 13. For a s i p+-n one-sided abrupt junction with N o = 2x1016cm-3 ~ 2x 10l6~ r n - ~th,e breakdown voltage is 32 V (Fig. a). If the doping distribution is modified to Fig. b, find the (a) breakdown voltage. X I I 0 0.5 pm b X 14. Find the value of the electron multiplication factor Mnfor a silicon p+-i-n+diode having a reverse bias of 200 V. The corresponding capacitance of the diode is 1.05 nF/cm2. 15. In an “ideal” silicon n+-p junction with NA= loL6~ m - a~ m, inority carrier lifetime of 10-8 s, and a mobility of 966 cm2/V-s, find the stored minority carriers in the neutral p-region of 1 pm, under a forward bias of 1 V. 16. For an ideal abrupt siliconp+-njunctionwith No = lOI5~ m -f~ind, the stored minority carriers (in C/cm2) in the neutral region when a forward bias of 1 V is applied. Assume the length of the neutral region is 1 pm and the diffusion length of holes is 5 pm. The hole distribution is given by 17. For a hyperabrupt p+-njunction varactor, the n-side doping profile is given by n(x) = Bxm where B is a constant and rn = -3/2. Derive the express for the differential capacitance. 18. Consider an ideal abrupt heterojunction with a built-in potential of 1.6 V. The impurity concentrations in semiconductor 1 and 2 are 1 ~ 1 0d‘o~nors/cm3 and 3 ~ 1 0a’cc~eptors/cm3, and dielectric constants are 12 and 13, respectively. Find the electrostatic potential and depletion width in each material for applied voltages of 0.5 V and -5 V. 19. For an n-GaAs/p-Al,,,Ga,,As heterojunctIon at room-temperature, AE, = 0.2 1 eV. (1) What type of heterojunction is this? (2) Based on the Anderson Model, find the total depletion width at thermal equilibrium when both sides have impurity concentration of 5x1Ol5~ m - (~3). Draw the band diagram. [Hint: For the bandgap of AIGaAs, refer to Fig. 32 of Chapter 1. The dielectric constant is (12.9 - 3 . 1 2 ~f)or AI,Ga,-,As. Assume N , and N , are the same for A1,Gal-&s with 0 WD,where WDis the depletion width, we obtain 3.2 FORMATION OF BARRIER 137 lllll 1 Period I I I I 10 20 30 40 50 Atomic number 70 80 90 95 Fig. 2 Metal work function for a clean metal surface in a vacuum versus atomic number. Note the periodic nature of the increase and decrease of the work functions within each group. (After Ref. 12.) where the term kTlq arises from the contribution of the majority-carrier distribution tail (electrons in n-side, see the footnote on p. 84) and grnis the maximum field strength which occurs at x = 0: The space charge Qs, per unit area of the semiconductor and the depletion-layer capacitance C, per unit area are given by 138 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS n-type semiconductor p-type semiconductor f Fig. 3 Energy-band diagrams of metal on n-type (left) and onp-type (right) semiconductors under different biasing conditions. (a) Thermal equilibrium. (b) Forward bias. (c) Reverse bias. or -[- 1- ND = 2 9% d( l / C i ) / dV 3.2 FORMATION OF BARRIER 139 If No is constant throughout the depletion region, one should obtain a straight line by plotting 1/C& versus voltage. If No is not a constant, the differential capacitance method can be used to determine the doping profile from Eq. 11, similar to the case of a one-sidedp-n junction as discussed in Section 2.2.1. The C-V measurement can also be used to study deep impurity levels. Figure 4 shows a semiconductor with one shallow donor level and one deep donor 1 e ~ e l . l ~ While all the shallow donors above the Fermi level will be ionized, only deep impurities near the surface are above the Fermi level and ionized, giving a higher effective doping concentration near the interface. In a C-V measurement where a small ac signal is superimposed on the dc bias, there will be a frequency dependence on capacitance since the deep impurities can only follow slow signals, i.e. dNddV is absent at high frequencies. Comparing C- Vmeasurements at various frequencies can reveal the properties of these deep-level impurities. 3.2.3 Interface States The barrier heights of metal-semiconductor systems are, in general, determined by both the metal work function and the interface states. A general expression of the barrier height can be obtained on the basis of the following two assumption^:^^ (1) with intimate contact between the metal and the semiconductor, and with an interfa- -. I UlVT Fig. 4 Semiconductor with one shallow donor level and one deep donor level. No and N , are the shallow donor and deep donor concentration, respectively. (After Ref. 13.) 140 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS cia1 layer of atomic dimensions, this layer will be transparent to electrons but can withstand potential across it, and (2) the interface states per unit area per energy at the interface are a property of the semiconductor surface and are independent of the metal. A more detailed energy-band diagram of a practical metal-n-semiconductor contact is shown in Fig. 5 . The various quantities used in the derivation that follows are defined in this figure. The first quantity of interest is the energy level q40 above E , at the semiconductor surface. It is called the neutral level above which the states are of acceptor type (neutral when empty, negatively charged when full) and below which the states are of donor type (neutral when full of electrons, positively charged when empty). Consequently, when the Fermi level at the surface coincides with this neutral level, the net interface-trap charge is zero.15This energy level also tends to pin the semiconductor Fermi level at the surface before the metal contact was formed. m,#m = Work function of metal = Barrier height (without image-force lowering) & = Neutral level (above E,) of interface states A = Potential across interfacial layer x = Electron affinity of semiconductor vbr= Built-in potential 6 = Thickness of interfacial layer Q,, = Space-charge density in semiconductor Q, = Interface-trap charge QM = Surface-charge density on metal D,,= Interface-trap density sj = Permittivity of interfacial layer (vacuum) gS = Permittivity of semiconductor Fig. 5 Detailed energy-band diagram of a metal-n-semiconductor contact with an interfacial layer (vacuum) of the order of atomic distance. (After Ref. 14.) 3.2 FORMATION OF BARRIER 141 The second quantity is q4BBn0t,he barrier height of the metal-semiconductor contact; it is this barrier that must be surmounted by electrons flowing from the metal into the semiconductor. The interfacial layer will be assumed to have a thickness of a few angstroms and will therefore be essentially transparent to electrons. We consider a semiconductor with acceptor interface traps (since in this particular example EF is above the neutral level) whose density is Di, states/cm2-eV, and is a constant over the energy range from qq40+ E , to the Fermi level. The interface-trap charge density on the semiconductor Q,, is therefore negative and is given by The quantity in parentheses is simply the energy difference between the Fermi level at the surface and the neutral level. The interface-trap density D, times this quantity yields the number of surface states above the neutral level that are full. The space charge that forms in the depletion layer of the semiconductor at thermal equilibrium is given as The total equivalent surface charge density on the semiconductor surface is given by the sum of Eqs. 12 and 13. In the absence of any space-charge effects in the interfacial layer, an exactly equal and opposite charge, QM(C/cm2), develops on the metal surface. For thin interfacial layers such space-charge effects are negligible and QMcan be written as QM = -(Qss + Qsc) . (14) The potential A across the interfacial layer can be obtained by applying Gauss' law to the surface charge on the metal and semiconductor: where ci is the permittivity of the interfacial layer and 6 its thickness. Another relation for A can be obtained by inspection of the energy-band diagram of Fig. 5: A = 4m-CX+ &no). (16) This relation results from the fact that the Fermi level must be constant throughout this system at thermal equilibrium. If A is eliminated from Eqs. 15 and 16, and Eq. 14 is used to substitute for Q , we obtain Equation 17 can now be solved for hnoW.e introduce the quantities 142 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS + c2 = E; E~ q2SDit which contain all the interfacial properties. Equation 18 can be used to calculate c1if values of Sand .ciare estimated. For vacuum-cleaved or well-cleaned semiconductor substrates the interfacial layer will have a thickness of atomic dimensions (i.e., 4 or 5 A). The permittivity of such a thin layer can be well approximated by the free-space value and since this approximation represents a lower limit for E ~i,t leads to an over- estimation of c2.For E~= loco,E~= so,and No < lo1*~ m - c~1i,s small, of the order of 0.01 V and the square-root term in Eq. 17 is estimated to be less than 0.1 V. Neglecting this square-root term, Eq. 17 reduces to With known c2 and c3from experiments of varying $, the interfacial properties are given by Using the previous assumptions for 6 and E ~w, e obtain Dit = 1.1x1013(1 - c 2 ) / c 2 states/cm2-eV. There are two limiting cases which can be obtained directly from Eq. 20: 1. When Dit -+ 00, then c2 + 0 and In this case the Fermi level at the interface is pinned by the surface states at the value qd0above the valence band. The barrier height is independent of the metal work function and is determined entirely by the surface properties of the semiconductor. 2. When Di, -+ 0, then c2-+ 1 and 4 hBn0 = 4 (4 m - X). (24) This equation for the barrier height of an ideal Schottky barrier where surfacestate effects are neglected, is identical to Eq. 1. The experimental results of the metal-n-silicon system are shown in Fig. 6a. A least-square straight-line fit to the data yields q 4 B B n 0= 0.27q4m- 0.52. (25) Comparing this expression with Eq. 20 (c2= 0.27, c3= - 0.52) and using Eqs. 21 and 22, we obtain q40= 0.33 eV, and Di, = 4x 1013states/cm2-eV. Similar results are obtained for GaAs, Gap, and CdS, which are shown in Fig. 6b and listed in Table 1. 3.2 FORMATION OF BARRIER 143 2.0 L 1.0 P 0 3.0 4.0 5.0 6.0 Gk (V) Fig. 6 Experimental barrier heights for different metals on n-type (a) silicon and (b) GaAs, Gap, and CdS. (After Ref. 14.) It should be pointed out that in spite of nonideal factors such as interface states, the relationship of Eq. 3, that the sum of barrier heights on n- and p-type substrates equals the energy gap of the semiconductor, is still generally valid. We note that the values of q4,, for Si, GaAs, and GaP are very close to one-third of the bandgap. Similar results are obtained for other semiconductors.16 This fact indicates that most covalent semiconductor surfaces have a high peak density of 144 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS Table 1 Summary of Barrier Height Data and Calculations of Interface Properties for Si, GaAs, Gap, and CdS (After Ref. 14) Si GaAs GaP CdS 0.27h0.05 -0.52*0.22 4.05 0.07*0.05 0.51+0.24 4.07 0.27*0.03 0.02+0.13 4.0 0.38+0.16 -1.17k0.77 4.8 2.7*0.7 12.5h10.0 2.7+0.4 1.651.1 0.3050.36 0.53+0.33 0.66+0.2 1.511.5 0.27 0.38 0.294 0.6 surface states or defects near the neutral level and that the neutral level is about onethird of the bandgap from the valence-band edge. The theoretical calculation by PughI7for (I 11) diamond indeed gives a narrow band of surface states slightly below the center of the forbidden gap. It is thus expected that a similar situation may exist for other semiconductors. For 111-V compounds, extensive measurements using photoemission spectroscopy indicate that the Schottky-barrier formation is due mainly to defects generated near the interface by deposition of the metal.I8 It has been shown that on a few compound semiconductors such as GaAs, GaSb, and InP, the surface Fermi-level positions obtained from a number of metals are pinned at an energy level quite independent of the rnetal.I9 This pinning of surface Fermi level can explain the fact that for most 111-V compounds, the barrier height is essentially independent of metal work function. For ionic semiconductors such as CdS and ZnS, the barrier height generally depends strongly on the metal and a correlation has been found between interface behavior and the electronegativity. The electronegativity X , is defined as the power of an atom in a molecule to attract electrons to itself. Figure 7 shows Pauling's electronegativity scale. Note that the periodicity is similar to that for the work function (Fig. 2 ) . Figure 8a shows a plot of the barrier height versus the electronegativity of metals deposited on Si, GaSe, and SiO,. From the plot we define the slope as an index of interface behavior: Note the comparison of Sto c2 (= d4B,,dd4,,,)W. e can also plot the index S as a function of the electronegativity difference (ionicity AX) of the semiconductors, shown in Fig. 8b. The electronegativity difference is defined as the difference in the Pauling electronegativities between the cation and the anion of the semiconductor. Note a sharp transition from the covalent semiconductors (such as GaAs with AX= 0.4) to ionic semiconductors (such as A1N with AX= 1.5). For semiconductors with AX< I, the index S is small, indicating that the barrier height is only weakly dependent on metal electronegativity (or the work function). On the other hand, for AX> 1, the Fig. 7 Pauling's electronegativity scale. Note the trend of increasing electronegativity within each group. (After Ref. 20.) 1.0- 7s 1.O) .82 0.8 - Ga203 01; , ; P;Ag,j;d 4 0.6 - GaSe 1";w %.c- L 0 0.4 - Au, ZnSe Sic G".T" CdSe ,,, , , , , , 0.5 Ni cu Ge GaAs InSb SI(S= 0.05) InP 0 1 .o 1.5 2.0 2.5 0 0.4 0.8 1.2 1.6 2.0 2.4 Electronegativity of metal X, Electronegativity difference AX (a) (b) Fig. 8 (a) Barrier height versus electronegativity of metals deposited on Si, GaSe, and SO,. (b) Index of interface behavior S as a function of the electronegativity difference of the semi- conductors. (After Ref. 2 1.) 145 146 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS index S approaches 1, and the barrier height is strongly dependent on the metal electronegativity (or the work function). For technological applications in silicon integrated circuits, an important class of Schottky barrier contacts has been developed in which a chemical reaction between the metal and the underlying silicon is induced to form silicides.22The formation of metal silicides by solid-solid metallurgical reaction provides more reliable and reproducible Schottky barriers, because the interface chemical reactions are well defined and can be maintained under good control. It is thought that since the silicide interfacial properties depends on the eutectic temperature, there should be a correlation between the barrier height and the eutectic temperature. Figure 9 shows such an empirical fit for the barrier heights on n-type silicon of transition-metal silicides plotted against the eutectic temperature of the silicides. Similar correlation had been observed when barrier heights are plotted against the heat of formation of ~ i l i c i d e s . ~ ~ 3.2.4 Image-Force Lowering The image-force lowering, also known as the Schottky effect or Schottky-barrier lowering, is the image-force-induced lowering of the barrier energy for charge carrier emission, in the presence of an electric field. Consider a metal-vacuum system first. The minimum energy necessary for an electron to escape into vacuum from an initial energy at the Fermi level is the work function q4mas shown in Fig. 10.When an electron is at a distance x from the metal, a positive charge will be induced on the metal surface. The force of attraction between the electron and the induced positive charge is equivalent to the force that would exist between the electron and an equal positive Eutectic temperature (K) Fig. 9 Correlation of barrier height of transition-metal silicides with their eutectic temperature. (After Ref. 23.) “f Metal 3.2 FORMATION OF BARRIER 147 Vacuum Fig. 10 Energy-band diagram between a metal surface and a vacuum. The metal work function is q+m.The effective barrier is lowered when an electric field is applied to the surface. The lowering is due to the combined effects of the field and the image force. charge located at - x . This positive charge is referred to as the image charge. The attractive force toward the metal, called the image force, is given by -2 2 F = 4 ~ & , ( 2 x = ) ~l 6 m-O x4 2 (27) where q,is the permittivity of free space. The work done to an electron in the course of its transfer from infinity to the point x is given by 1r x 2 E ( x ) = Fdx = -4. 16 m n x .’a This energy corresponds to the potential energy of an electron placed at a distance x from the metal surface, shown in Fig. 10, and is measured downwards from the x-axis.When an external field 8is applied (in this example in the -x direction), the total potential energy PE as a function of distance is given by the sum This equation has a maximum value. The image-force lowering A# and the location of the lowering x, (as shown in Fig. l o ) , are given by the condition d(PE)la!x = 0, or 148 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS From Eqs. 30 and 31 we obtain A # = 0.12 V and x, = 6 nm for g = lo5Vlcm; and A 4 = 1.2 V and x, = 1 nm for 'iZ = lo7Vlcm. Thus at high fields the Schottky barrier is considerably lowered, and the effective metal work hnction for thermionic emission (q&) is reduced. These results can be applied to metal-semiconductor systems. However, the field should be replaced by the appropriatefield at the interface,and the free-spacepermittivity &,, should be replaced by an appropriatepermittivity &, characterizingthe semiconductor medium, that is, Note that inside a device such as metal-semiconductor contact, the field is not zero even without bias due to the built-in potential. Because of the larger values of E, in a metal-semiconductor system, the barrier lowering is smaller than that in a corre- sponding metal-vacuum system. For example, for E, = 12s0,A 4 as obtained from Eq. 32 is only 0.035 V for 'iZ = lo5Vlcm and even smaller for smaller fields. Also a typical value for x, is calculated to be less than 5 nm. Although the barrier lowering is small, it does have a profound effect on current transport processes in metal-semiconductor systems. These are considered in Section 3.3. In a practical Schottky-barrier diode, the electric field is not constant with distance, and the maximum value at the surface based on the depletion approximation can be used, where the surface potential w,(on n-type substrate) is Substituting g, into Eq. 32 gives Figure 11 shows the energy diagram incorporatingthe Schottkyeffect for a metal on n-type semiconductor under different biasing conditions. Note that for forward bias (V > 0), the field and the image force are smaller and the barrier height q4BBnO- qA4F is slightly larger than the barrier height at zero bias of 4 4Bn = q4BnO -qA4. (36) For reverse bias (V, > O), the barrier height qqjBnO - qA4, is slightly smaller. In effect, the barrier height becomes bias dependant. The value E, may also be different from the semiconductor static permittivity. If during the emission process, the electron transit time from the metal-semiconductor interface to the barrier maximum x, is shorter than the dielectric relaxation time, the semiconductor medium does not have enough time to be polarized, and smaller per- 3.2 FORMATION OF BARRIER 149 Fig. 11 Energy-band diagram incorporating the Schottky effect for a metal n-type semiconductor contact under different biasing conditions. The intrinsic barrier height is q&+,. The barrier height at thermal equilibrium is q&. The barrier lowerings under forward and reverse bias are Aq& and A#R respectively. (After Ref. 10.) mittivity than the static value is expected. It will be shown, however, that for Si the appropriate permittivities are about the same as their corresponding static values. The dielectric constant (K,= E J E ~ )in gold-silicon barriers has been obtained from photoelectric measurements, which will be discussed in Section 3.4.4. The experi- mental results are shown in Fig. 12, where the measured barrier lowering is plotted as a function of the square root of the maximum electric field.25From Eq. 35 the image- force dielectric constant is determined to be 12 f 0.5. For E J E ~= 12, the distance x, varies between 1 and 5 nm for the field range shown in Fig. 12. Assuming a carrier velocity of the order of lo7 cm/s, the transit time for these distances should be between 1-5x s. The image-force dielectric constant should thus be comparable to the value of approximately 12 for electromagnetic radiation of roughly these periods (wavelengths between 3 and 15 pm).26The dielectric constant of bulk silicon is essentially constant (11.7) from dc to A = 1 pm, therefore the lattice has time to polarize while the electron is traversing the depletion layer. The photoelectric mea- surements and data deduced from the optical constants are in excellent agreement. For Ge and GaAs, the dependence of the optical dielectric constant on wavelength is similar to that of Si. The image-force permittivities of these semiconductors in the foregoing field range are thus expected to be approximately the same as the corre- sponding static bulk values. 150 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS I I 103 104 I I 5~10~ 105 I 1.5 x 1O5 Zm(V/cm) Fig. 12 Measurement of barrier lowering as a h c t i o n of the electric field in a Au-Si diode. (After Ref. 25.) 3.2.5 Barrier-Height Adjustment For an ideal Schottky barrier, the barrier height is determined primarily by the characters of the metal and the metal-semiconductor interface properties and is nearly independent of the doping. Usual Schottky barriers on a given semiconductor (e.g., norp-type Si) therefore give a finite number of choices for barrier height. However, by introducing a thin layer (= 10 nm or less) of controllable number of dopants on a semiconductor surface (e.g., by ion implantation), the effective barrier height for a given metal-semiconductor contact can be ~ a r i e d . T~h~is-a~pp~roach is particularly useful in order to select a metal having the most desirable metallurgical properties required for reliable device operation and at the same time to be able to adjust the effective barrier height between this metal and the semiconductor in a controlled manner. Figure 13a shows the idealized controlled barrier contacts with a thin n+-layer or a thinp+-layer on an n-type substrate for barrier reduction or barrier increase, respectively. Consider the reduction of barrier first. The field distribution in Fig. 13b is given by 3.2 FORMATION OF BARRIER 151 Increasing 4B "t Semiconductor .EC X EC t X I Metal Semiconductor Fig. 13 Idealized controlled barrier contacts with a thin n+-layer or a thin p+-layer on an n-type substrate for barrier reduction (left) or barrier increase (right), respectively. Dashed lines indicate original barrier with uniform doping. g = -lgml +-4nlx for O> n2 and ap, >> Wn,. Therefore, as the product up, increases, the effective barrier height will increase accordingly. Figure 15 shows the measured results of Ni-Si diodes with shallow antimony implantation on the surface. As the implant dose increases, the effective barrier height decreases for n-type substrates and increases for p-type substrates. 3.3 CURRENT TRANSPORT PROCESSES The current transport in metal-semiconductor contacts is due mainly to majority carriers, in contrast to p-n junctions where the minority carriers are responsible. Figure 16 shows five basic transport processes under forward bias (the inverse processes occur under reverse bias).* These five processes are (1) emission of electrons from the semiconductor over the potential barrier into the metal [the dominant process for Schottky diodes with moderately doped semiconductors (e.g., Si with No 5 lOI7 ~ m - o~p)erated at moderate temperatures (e.g., 300 K)], (2) quantummechanical tunneling of electrons through the barrier (important for heavily doped semiconductors and responsible for most ohmic contacts), (3) recombination in the space-charge region [identical to the recombination process in ap-n junction (refer to & 0.3 - 5 keV, 750°C anneal W 00.2 I I I I 1 246810 2 Antimony atoms implanted (lo1*cm-*) Fig. 15 Effective barrier height for holes in p-type substrates and for electrons in n-type substrates as a function of the implanted antimony dose. (After Ref. 30.) 154 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS n-semiconductor Fig. 16 Five basic transport processes under forward bias. (1) Thermionic emission. (2) Tunneling. (3) Recombination. (4) Diffusion of electrons. ( 5 ) Diffusion of holes. chapter 2)], (4) difision of electrons in the depletion region, and (5) holes injected from the metal that diffuse into the semiconductor (equivalent to recombination in the neutral region). In addition, we may have edge leakage current due to a high electric field at the metal-contact periphery or interface current due to traps at the metal-semiconductor interface. Various methods have been used to improve the interface quality, and many device structures have been proposed to reduce or eliminate the edge leakage current (see Section 3.5). For common high-mobility semiconductors (e.g., Si and GaAs) the transport can be adequately described by this thermionic-emission theory. We shall also consider the diffusion theory applicable to low-mobility semiconductors and a generalized thermionic-emission-diffusiontheory that is a synthesis of the preceding two theories. Schottky diode behavior is to some extent electrically similar to a one-sided abruptp-n junction, and yet the Schottky diode can be operated as a majority-carrier device with inherent fast response. Thus, the terminal functions of a p-n junction diode can general be performed by a Schottky diode with one exception as a chargestorage diode. This is because the charge-storage time in a majority-carrier device is extremely small. Another difference is the larger current density in a Schottky diode due to the smaller built-in potential as well as the nature of thermionic emission compared to diffusion. This results in a much smaller forward voltage drop. By the same token, the disadvantage is the larger reverse current in the Schottky diode and a lower breakdown voltage. 3.3.1 Thermionic-Emission Theory The thermionic-emission theory by Bethe6 is derived from the assumptions that (1) the barrier height q#Bnis much larger than kT,(2) thermal equilibrium is established at the plane that determines emission, and (3) the existence of a net current flow does not affect this equilibrium so that one can superimpose two current fluxes-ne from metal to semiconductor, the other from semiconductor to metal, each with a different quasi Fermi level. If thermionic emission is the limiting mechanism, then EFnis flat 3.3 CURRENT TRANSPORT PROCESSES 155 throughout the deletion region (Fig. 16). Because of these assumptions, the shape of the barrier profile is immaterial and the current flow depends solely on the barrier height. The current density from the semiconductor to the metal J,, is then given by the concentration of electrons with energies sufficient to overcome the potential barrier and traversing in the x-direction: 1m J,,, = Pxdn (43) EFn + 4Bn where EFn+ q&, is the minimum energy required for thermionic emission into the metal, and uxis the carrier velocity in the direction of transport. The electron density in an incremental energy range is given by where N(E) and F(E) are the density of states and the distribution function, respectively. If we postulate that all the energy of electrons in the conduction band is kinetic energy, then E - E c --2-1m*u2 (45) dE = m*udu (46) 2) Substituting Eqs. 4 5 4 7 into Eq. 44 gives dn z 2(7m-)* exp[- exp(- d ) ( 4 m 2 d u ) . 2kT (48) Equation 48 gives the number of electrons per unit volume that have velocities between u and u + du, distributed over all directions. If the velocity is resolved into its components along the axes with the x-axis parallel to the transport direction, we have + + u2 = u,' uy2 u,'. (49) With the transformation 4 d d u = duxdv,du,, we obtain from Eqs. 43,48, and 49 g- 2) 2) exp(- (- d u y r exp dv, -W -m 156 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS The velocity voxis the minimum velocity required in the x-direction to surmount the barrier and is given by Substituting Eq. 51 into Eq. 50 yields = A*Pexp(- % ) e x p ( S , and A * -- 4zqm*k2 h3 (53) is the effective Richardson constant for thermionic emission, neglecting the effects of optical-phonon scattering and quantum mechanical reflection (see Section 3.3.3). For free electrons (m*= mo)the Richardson constant A is 120 A/cm2-K2.Note that when the image-force lowering is considered, the barrier height 4Bnin Eq. 52 is reduced by A+. For semiconductors with isotropic effective mass in the lowest minimum of the conduction band such as n-type GaAs, A*IA simply is equal to m*lmo.For multiple- valley semiconductors the appropriate Richardson constant associated with a single energy minimum is given by3' where I,, 12, and l3are the direction cosines of the normal to the emitting plane relative to the principal axes of the ellipsoid, and m: , m; ,and m; are the components of the effective mass tensor. For Si the conduction band minima occur in the (100)-directions and m; = 0.98m0, mf = 0.19mo.The minimum value of A* occurs for the (100)-directions: In the ( 1 1 1)-directions all minima contribute equally to the current, yielding the maximum A*: For holes in Si and GaAs the two energy maxima at k = 0 give rise to approximately isotropic current flow from both the light and heavy holes. Adding the currents due to these carriers, we obtain 3.3 CURRENT TRANSPORT PROCESSES 157 Table 2 gives a summary of the values of A*/A for Si and GaAs. Since the barrier height for electrons moving from the metal into the semicon- ductor remains the same under bias, the current flowing into the semiconductor is thus unaffected by the applied voltage. It must therefore be equal to the current flowing from the semiconductor into the metal when thermal equilibrium prevails (i.e., when V= 0). This corresponding current density is obtained from Eq. 52 by setting V = 0, q!3 ( J,,,, = -A*Pexp -- The total current density is given by the sum of Eqs. 52 and 58. where Equation 59 is similar to the transport equation for p-n junctions. However, the expressions for the saturation current densities are quite different. An alternative approach to derive the thermionic-emission current is the following.*Without decomposing the velocity components, only electrons with energy above the barrier will contribute to the forward current. This number of electrons above the barrier is given by n = N e xp[-4(4B;-v)] It is known that for a Maxwellian distribution of velocities, the current from random motion of carriers across a plane is given by J = nq-ua4ve where u,,, is the average thermal velocity, Table 2 Values of A'IA (After Ref. 31) Semiconductor P-tYPe n-type (100) n-type (111) Si GaAs 0.66 0.62 2.1 0.063 (low field) 0.55 (high field) 2.2 158 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS [ :B- “1 Substitution of Eqs. 61 and 63 into Eq. 62 gives J = 4( k T )2qm*exp -4 ( h3 which is identical to Eq. 52. 3.3.2 Diffusion Theory The diffusion theory by Schottkf is derived from the assumptions that (1) the barrier height is much larger than kT, (2) the effect of electron collisions within the depletion region, i.e., diffusion, is included, (3) the carrier concentrations at x = 0 and x = W, are unaffected by the current flow (i.e., they have their equilibrium values), and (4) the impurity concentration of the semiconductor is nondegenerate. Since the current in the depletion region depends on the local field and the concentration gradient, we must use the current density equation: J, = J,, = q(np,,W+D,,&) dx Under the steady-state condition, the current density is independent of x , and Eq. 65 can be integrated using exp[E&x)/kT] as an integrating factor. We then have and the boundary conditions using EFm= 0 as the reference (see Fig. 16 but ignore image force for difision): ‘do) = q4BBnJ (67) Ec(WD)= 4 ( 4 n + 0, (68) Substituting Eqs. 67-70 into Eq. 66 yields ]/jwDexp[%]&. [ J,, = qN,D,, exp( k 3 - 1 0 3.3 CURRENT TRANSPORT PROCESSES 159 For Schottky barriers, neglecting image-force effect, the potential distribution is given by Eq. 6. Substituting this expression for E d x ) into Eq. 71 and expressing WD in terms of ybi+ Vleads to ( = qp,,NcEmexp - - qfp)[exp($ ‘1 ‘1. - = JD[exp($ - (72) The current density expressions of the diffusion and thermionic-emission theories, Eqs. 59 and 72, are basically very similar. However, the saturation current density for the diffusion theory JDis dependent on the bias and is less sensitive to temperature compared to the saturation current density of the thermionic-emission theory JTH. 3.3.3 Thermionic-Emission-Diffusion Theory A synthesis of the thermionic-emission and d i f i s i o n approaches described above has been proposed by Crowell and S Z ~Th.is~ap~proach is derived from the boundary condition of a thermionic recombination velocity uRnear the metal-semiconductor interface. Since the diffusion of carriers is strongly affected by the potential configuration in the region through which the diffusion occurs, we consider the electron potential energy [orE d x ) ]versus distance incorporating the Schottky lowering effect as shown in Fig. 17. We consider the case where the barrier height is large enough that the charge density between the metal surface and x = WDis essentially that of the ionized donors (i.e., depletion approximation). As drawn, the applied voltage Vbetween the EFm= 0 X I Metal n-semiconductor Fig. 17 Energy-band diagram incorporating the Schottky effect to show the derivations of therrnionic-emission-diffusiontheory and tunneling current. 160 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS metal and the semiconductorbulk would give rise to a flow of electrons toward the metal. The electron quasi-Fermi level EFn in the barrier is also shown schematically as a function of distance. Throughout the region between x , and WD, where the electron density at any point x is given by Ec;3 ( - n = Ncexp - (74) We will assume that the region between x, and WDis isothermal and that the electron temperature T is equal to the lattice temperature. If the portion of the barrier between x , and the interface (x = 0) acts as a sink for electrons, we can describe the current flow in terms of an effective recombination velocity u, at the potential energy maximum x,: = q(nm-nCl)vR (75) where n, is the electron density at x, when the current is flowing, nois a quasi-equilibrium electron density at x,, the density that would occur if it were possible to reach equilibrium without altering the magnitude or position of the poten- tial energy maximum, i.e., EFn(x,) = EFm ‘2). no = Ncexp(- (77) Another boundary condition, taking EF, = 0 as reference, is EFn( wD) = q v . (78) If n is eliminated from Eqs. 73 and 74 and the resulting expression for EFn is integrated between x , and WD, Then from Eqs. 75 and 79, EFn(x,) can be solved as where 3.3 CURRENT TRANSPORT PROCESSES 161 is an effective diffusion velocity associated with the transport of electrons from the edge of the depletion layer W, to the potential energy maximum x,. Substituting Eq. 80 into Eq. 75 gives the end result of the thermionic-emission-diffusiontheory In this equation, the relative values of U, and V, determines the relative contribution of thermionic emission versus diffusion. The parameter U, can be evaluated as the Dawson’s integral and can be approximated by U, Y pn8, in this case of depletion region.8If the electron distribution is Maxwellian forx 2 x, and if no electrons return from the metal other than those associated with the current density qn,vR, the semiconductor acts as a thermionic emitter. Then V, is the thermal velocity given by where A* is the effective Richardson constant, as shown in Table 2. At 300 K, U, is 5 . 2 l~o6 and 1.Ox lo7 cm/s for (111) n-type Si and n-type GaAs respectively. It can be seen that if uD>> u,, the pre-exponential term in Eq. 82 is dominated by U, and the thermionic-emission theory applies (JTED = JTE).If, however, U, << u,, the difhsion process is the limiting factor (JTED = .ID). In summary, Eq. 82 gives a result that is a synthesis of Schottky’s diffusion theory and Bethe’s thermionic-emission theory, and it predicts currents in essential agreement with the thermionic-emission theory if p2?(x,) > u,. The latter criterion is more rigorous than Bethe’s condition 2?(x,) > kT/qil,where il is the carrier mean free path. In the preceding section a recombination velocity u, associated with thermionic emission was introduced as a boundary condition to describe the collecting action of the metal in a Schottky barrier. In many cases an appreciable probability exists that an electron which crosses the potential energy maximum will be back-scattered by electron optical-phonon ~ c a t t e r i n g .A~s~a, ~fir~st approximation the probability of electron emission over the potential maximum can be given by& = exp(-x,/A). In addition, the electron energy distribution can be hrther distorted from a Maxwellian distribution because of quantum-mechanical reflection of electrons by the Schottky barrier, and also because of tunneling of electrons through the b a ~ ~ i e Tr h. e~ra~ti,o&~ ~ of the total current flow, considering the quantum-mechanical tunneling and reflection, to the current flow neglecting these effects depends strongly on the electric field and the electron energy measured from the potential maximum. The complete expression of the J-Vcharacteristics taking into account4 andfe is thus 162 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS where The impacts of these effects are reflected in the reduced effective Richardson constant from A* to A**,by as much as 50%. Figure 18 shows the calculated room-temperature values of A** for metal-% systems with an impurity concentration of 10I6~ m - W~ e. note that for electrons (n-type Si), A** in the field range lo4to 2x105 V/cm remains essentially at a constant value of about 110 A/cm2-K2.For holes (p-type Si), A** in this field range also remains essentially constant but at a considerably lower value (:. 30 A/cm2-K2).For n-type GaAs, A**has been calculated to be 4.4 A/cm2-K2. We conclude from the foregoing discussions that at room temperature in the electric field range of lo4to about lo5Vhm, the current transport mechanism in most Si and GaAs Schottky-barrier diodes is mainly due to thermionic emission of majority carriers. The spatial dependence of the electron Fermi level EFnnear the metal-semiconductor interface has been studied by substituting Eqs. 6 and 74 into Eq. 73 and evaluating the difference, EFn(W,) -EFn(0).The EFn as shown in Fig. 16 is essentially flat throughout the depletion region.38The difference EFn(W,) - EFn(0)for a Au-Si diode with No = 1 . 2 ~ 1 0~’ ~m - i~s ,only 8 meV for a forward bias of 0.2 V at 300 K. At higher doping levels the difference is even smaller. These results further confirm that for high-mobility semiconductors with moderate dopings, the thermionic-emission theory is applicable. 3.3.4 Tunneling Current For more heavily doped semiconductors and/or for operation at low temperatures, the tunneling current may become more significant. In the extreme of an ohmic contact, 140 - 120 Si N, or N, = 10I6~ 1 1 1 1 ~ T = 300 K - 5 100 “E - - 0 5 ~ 1 0 ~104 105 8(V/cm) 5~10~ Fig. 18 Calculated effective Richardson constant A** versus electric field for metal-silicon barriers. (After Ref. 37.) 3.3 CURRENT TRANSPORT PROCESSES 163 which is a metal contact on degenerate semiconductor, the tunneling current is the dominant transport process. We will concentrate on ohmic contacts in the last section of this chapter. The tunneling current from semiconductor to metal J,, is proportional to the quantum transmission coefficient (tunneling probability) multiplied by the occupation probability in the semiconductor and the unoccupied probability in the metal, that is,36 Js+m - A2k[T:FsT(E)(I -F,)dE. (86) Fs and F, are the Fermi-Dirac distribution functions for the semiconductor and the metal respectively, and T(E)is the tunneling probability which depends on the width of the barrier at a particular energy. A similar expression can be given for the current J,, which traverses in the opposite direction. In that case F, and F, would be interchanged in using the same equation. The net current density is the algebraic sum of the two components. Further analytical expression for the above equation is diEcult, and the results can be obtained by numerical evaluation by computer. Theoretical and experimental values of typical current-voltage characteristics for Au-Si barriers are shown in Fig. 19. We note that the total current density, which consists of both thermionic emission and tunneling, can be conveniently expressed as c 1e70 0.1 0.2 Fig. 19 Theoretical and experimental current-voltage characteristics for Au-Si Schottky barriers. 3 Increased current is due to tunneling. Forward bias (V) (After Ref. 36.) 164 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS J = Jo[exP(5) - 11 (87) where J, is the saturation current density obtained by extrapolating the current density from the log-linearplot to V = 0, and 7 is the ideality factor, related to the slope. With little or no tunneling current or depletion-layer recombination, J, is determined by that of thermionic emission and 7 is close to unity. For higher doping andor lower temperature, tunneling starts to occur and both J, and 7 increase. The saturation current density Joand 77 are plotted in Fig. 20 for Au-Si diodes as a finction of doping concentration, with temperature as a parameter. Note that J, is essentially a constant for low dopings but begins to increase rapidly when No > 1017~ m - T~h.e ideality factor 77 is very close to unity at low dopings and high temperatures. However, it can depart substantially from unity when the doping is increased or the temperature is lowered. Figure 21 shows the ratio of the tunneling current to the thermionic current of a Au-Si barrier diode. Note that for No I lOI7~ m a-nd~T 2 300 K, the ratio is much less than unity and the tunneling component can be neglected. However, for higher dopings and lower temperatures, the ratio can become much larger than unity, indicating that the tunneling current becomes dominant. Alternatively, the tunneling current can be expressed analytically and will give more physical insight. This formulation, based on the work of Padovani and S t r a t t ~ nis, ~al~so used to derive the ohmic contact resistance. Referring to the energyband diagrams in Fig. 22, we can roughly categorize the components into three types: N , (cm-3) No ( ~ m - ~ ) (a) (b) Fig. 20 (a) Saturation current density versus doping concentration for Au-Si Schottky bar- riers at three temperatures. (b) Ideality factor 7versus doping concentration at different tem- peratures. (After Ref. 36.) 3.3 CURRENT TRANSPORT PROCESSES 165 s3 10-10- - I2 I I I component to the thermionic-current component of a Au-Si barrier. The tunneling current will dominate at higher dopings and lower tempera- (1) thermionic emission (TE) over the barrier, (2) field emission (FE) near the Fermi level, and (3) thermionic-field emission (TFE) at an energy between TE and FE. While FE is a pure tunneling process, TFE is tunneling of thermally excited carriers which see a thinner barrier than FE. The relative contributions of these components depend on both temperature and doping level. A rough criterion can be set by com- paring the thermal energy kT to E,, which is defined as When kT >> E,,, TE dominates and the original Schottky-barrier behavior prevails without tunneling. When kT << Eoo,FE (or tunneling) dominates. When kT = Eoo,TFE is the main mechanism which is a combination of TE and FE. L (4 (b) Fig. 22 Energy-band diagrams showing qualitatively tunneling currents in a Schottky diode (on n-type degenerate semiconductor) under (a) forward bias and (b) reverse bias. TE = ther- mionic emission. TFE = thermionic-field emission. FE = field emission. 166 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS Under forward bias, the current due to FE can be expressed as39 where (4nis negative for degenerate semiconductors.) Notice the much weaker temperature dependence here (absent in the exponential term) compared to TE which is a characteristic of tunneling. The current due to TFE is given by Eo= EoocothE(oEo) . This TFE peaks roughly at an energy where Em is measured from E, of the neutral region. Under reverse bias, the tunneling current can be much larger because a large voltage is possible. The currents due to FE and TFE are given by where Eoo &= (E,,/kT) - tanh(Eoo/kT)‘ These analytical expressions, although complicated, can be easily evaluated if all the parameters are known. These equations are also used to derive the ohmic contact resistance in the last section of this chapter. 3.3.5 Minority-Carrier Injection The Schottky-barrier diode is mainly a majority-carrier device. The minority-carrier injection ratio y, which is the ratio of minority-carrier current to total current, is small because the minority-carrier diffusion is much smaller than the majority-carrier ther- 3.3 CURRENT TRANSPORT PROCESSES 167 mionic-emission current. However, at sufficiently large forward bias, the drift component of the minority carriers cannot be ignored anymore and the increased drift component will increase the overall injection efficiency. Both drift and difision of holes lead to the total current of The increased field is set up by the large majority-carrier thermionic-emission current, Jn = q p n N O 8 . (98) We consider the energy-band diagram shown in Fig. 23 where x1is the boundary of the depletion layer, and x2 marks the interface between the n-type epitaxial layer and the n+-substrate.From the junction theory discussed in Chapter 2, the minoritycarrier density at x1is This quantityp,,(x,) can also be expressed as a function of the forward current density, obtained from Eqs. 84 and 99: where J,,,(saturation current density) and J,,are representations of the thermionicemission current (Eq. 84) in the following form: The other boundary condition for pn(x2)is also necessary to calculate the diffusion current. We use the term transport velocity Sp (or surface recombination velocity) for the minority carriers to relate the current and concentration by Depleltaioyne-r! I. Metal I 0 -~ Qu;mgoytral 1. n-type epitaxial layer I I n+-substrate , 11 12 Fig. 23 Energy-band diagram of an epitaxial Schottky barrier under forward bias. 168 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS Jp(x2) = qSpbn(x2) - ~ n o l . ( 102) We first consider the case with Sp = 00 or equivalently pn(x2)=pno.Under this boundary condition,the diffusioncomponent has a standard form as in ap-n junction. From Eqs. 97,98, and 100we obtain the total hole current as (for L << Lp) The injection ratio is given by For Au-Si diodes, the injection ratio has been measured to be very small, of the order of in agreement with the above equation.40Notice that yhas two terms. The second term is due to diffusion and is bias independent. This is the injection ratio for low-level bias, qDpn,2 Yo = NDLJnO The first term is due to the drift process, and is bias (or current) dependent. It can surpass the diffusion component at high current. It is evident that to reduce the minority-carrier injectionratio (to reduce the charge storage time to be discussedbelow) one must use a metal-semiconductorsystem with largeNo (correspondingto low resistivitymaterial), large Jno(correspondingto small barrier height), and small ni (corresponding to large bandgap). Furthermore, highlevel bias is to be avoided. As an example, a gold-n-silicondiode withND= 1015~ m - ~ and Jno= 5x lo-’ A/cm2would give a low-bias injection yo of = 5x 104. But it would be expected to have an injection ratio of about 5% at a current density of 350 A/cm2. The above assumes thatpn(x,) =pno.Notice that at x2,there is a barrier for holes that causes the holes to build up. These intermediate cases have been considered by Scharfetter using Sp as a parameter.41The computed results are shown in Fig. 24a, where the normalization factors are given by yo and Joo is the majority-carrier current at which the hole drift and diffusion components become equal, obtained by equating the two terms in Eq. 103. Another quantity associated with the injectionratio is the minority-carrierstorage time z, which is defined as the minority carrier stored in the quasi-neutralregion per unit current density: 3.3 CURRENT TRANSPORT PROCESSES 169 J/JOO JIJOO (a) (b) Fig. 24 (a) Normalized minority-carrier injection ratio versus normalized current density. (b) Normalized minority-carrierstorage time versus normalized current density. L/Lp= lo-*. (After Ref. 41.) JXl For the low-current limit, depending onp,(x,) or S,, r, is given approximately by (for L << L,) z, = - qn?L NDJnO’ and is independent of current. For high-current biases, pn(x2)can become much higher, even to the extent that it is larger than in the rest of the quasi-neutral region L , i.e. a profile that increases with distance. The general results, using S, again as a parameter, for zs versus the current density are shown in Fig. 24b. It can be seen that for finite Sp (S, f a),z, can increase by orders of magnitude. Also, a high doping level is critical to reduce storage time in all cases. 3.3.6 MIS Tbnnel Diode In the metal-insulator-semiconductor (MIS) tunnel diode, a thin interfacial layer such as an oxide is intentionally (or sometimes unintentionally) introduced before metal d e p ~ s i t i o n .T~h~is, i~nt~erfacial-layer thickness lies in the range of 1-3 nm. This device differs from the MIS capacitor (to be considered in Chapter 4) in having appreciable current and under bias the semiconductor is not in equilibrium, i.e., the 170 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS quasi Fermi levels for electrons EFnand holes EFesplit. The major differences of this structure compared to a conventional metal-semiconductor contact are: (1) reduced current because of the added interfacial layer, (2) lower barrier height (some potential is developed across the interfacial layer), and ( 3 )higher ideality factor 7. The energyband diagram is similar to Fig. 5 . The current equation can be written as42 The derivation for this equation can be found in Section 8.3.2. For the same barrier, the current is suppressed by the tunneling probability e x p ( - x s) . Here <(in eV) and 6(in A) are the effective barrier and thickness of the interfacial layer. (A constant of [2(2rn*/h2)]1w/2hich has the value of 1.01 eV-"*A-' is omitted.) This added tunneling probability can be considered as a modification to the effective Richardson constant, as discussed before. The ideality factor is increased to42 where Di,and Ditmare interface traps in equilibrium with the semiconductor and metal, respectively. In general, when the oxide thickness is less than 3 nm, the interface traps are in equilibrium with the metal, whereas for thicker oxides, these traps tend to be in equilibrium with the semiconductor. The interfacial layer reduces the majority-carrier thermionic-emission current without affecting the minority-carrier current, which is from diffusion, and raises the minority injection efficiency. This phenomenon is exploited in improving the injection efficiency of an electroluminescent diode and the open-circuit voltage of the Schottky-barrier solar cell. 3.4 MEASUREMENT OF BARRIER HEIGHT Basically, four methods are used to measure the barrier height of a metal-semiconductor contact: the (1) current-voltage, (2) activation-energy,( 3 ) capacitance-voltage, and (4) photoelectric methods. 3.4.1 Current-VoltageMeasurement For moderately doped semiconductors,the I- V characteristics in the forward direction with V> 3kTlq is given by Eq. 84: y;) ( J = A**Pexp - - e x p [ Y ] . Since both A** and A@(image-force lowering) are weak functions of the applied voltage, the forward J - V characteristic (for V> 3kTlq) is represented by J =J,,exp(qV/vkT), as given previously in Eq. 87, where is the ideality factor: 3.4 MEASUREMENT OF BARRIER HEIGHT 171 q ' 4 - dV kTd( 1nJ) - &d kTd( lnA**)]-' - [ ' + d V + y dV Typical examples are shown in Fig. 25, where 77 = 1.02 for the W-Si diode and q = 1.04 for the W-GaAs diode. The extrapolated value of current density at zero voltage is the saturation current Jo, and the barrier height can be obtained from the equation The value of &n is not very sensitive to the choice of A**,since at room temperature, a 100% increase in A** will cause an increase of only 0.018 V in &. The theoretical relationship between Jo and h (& or &,) at room temperature is plotted in Fig. 26 for A**= 120 A/cm2-K2.For other values of A**,parallel lines can be drawn on this plot to obtain the proper relationship. In the reverse direction, the dominant voltage dependence is due mainly to the Schottky-barrier lowering, or JR= J,, (for VR> 3kT/q) where Fig. 25 Forward current density versus applied voltage of W-Si and W-GaAs diodes. (After Ref. 44.) 172 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS 9 Fig. 26 Theoretical saturation current density at 300 K versus barrier height for an effective Richardson constant of 120 A/cm2-K2. If the barrier height qqbBBisnsufficiently smaller than the bandgap so that the depletionlayer generation-recombination current is small in comparison with the Schottky emission current, then the reverse current will increase gradually with the reverse bias as given by Eq. 114, due mainly to image-force lowering. For most of the practical Schottky diodes, however, the dominant reverse current component is the edge leakage current, which is caused by the sharp edge around the periphery of the metal plate. This sharp-edge effect is similar to the junction-curva- ture effect (with rj + 0) as discussed in Chapter 2. To eliminate this effect, metal- semiconductor diodes have been fabricated with a diffused guard ring (these structures will be discussed later). The guard ring is a deep p-type diffusion, and the doping profile is tailored to give the p-n junction a higher breakdown voltage than that of the metal-semiconductor contact. Because of the elimination of the sharp-edge effect, near-ideal forward and reverse I-V characteristics have been obtained. Figure 27 shows a comparison between experimental measurement from a PtSi-Si diode with guard ring, and theoretical calculation based on Eq. 114. The agreement is excellent. The sharp increase of current near 30 V is due to avalanche breakdown and is expected for the diode with a donor concentration of 2 . 5 ~ 1 0~' ~m - ~ . The efficacy of guard ring structures in preventing premature breakdown and surface leakage can be ascertained by studying the reverse leakage current as a function of diode diameter at constant reverse bias. For this purpose, arrays of Schottky 3.4 MEASUREMENT OF BARRIER HEIGHT 173 10-1110-3 10-2 10-1 100 v, (V) Fig. 27 Comparison of measurement with the theoretical prediction 101 102 of reverse-bias current from Eq. 114 for a PtSi-Si diode. (After Ref. 45.) diodes with different diameters can be formed on the semiconductor. The reverse leakage current can be measured and plotted as a function of diode diameter.46If the experimental data have a slope equal to two, the leakage currents are proportional to the device area. If, on the other hand, the leakage currents are dominated by edge effects, the data would be expected to lie along a straight line with a slope equal to unity. For some Schottky diodes, the reverse current has an additional component. This component arises from the fact that if the metal-semiconductor interface is free from intervening layers of oxide and other contaminants, the electrons in the metal have wave functions that penetrate into the semiconductor energy gap. This is a quantummechanical effect that results in a static dipole layer at the metal-semiconductor interface. The dipole layer causes the intrinsic barrier height to vary slightly with the field, so d@Bo/d8#m0. To a first approximation the static lowering can be expressed as '4 static a'm (1 16) or a = d@,ddgm.Figure 28 shows good agreement between the theory and measure- ments of the reverse current in a RhSi-Si diode, based on an empirical value of a = 1.7 nm. 3.4.2 Activation-Energy Measurement The principal advantage of Schottky-barrier determination by means of an activation energy measurement is that no assumption of electrically active area is required. This feature is particularly important in the investigation of novel or unusual metal-semiconductor interfaces because often the true value of the contacting area is not known. In the case of poorly cleaned or incompletely reacted surfaces, the electrically active 174 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS 103 102 h "E Y s 9 10' Additional static / ,/;mage-force / lowering -----------___ Saturation current density IU- 10-3 10-2 lo-' 1 00 10' 1 02 VR (V) Fig. 28 Theory and experimental results of reverse characteristics for a RhSi-Si diode. (After Ref. 37.) area may be only a small fraction of the geometric area. On the other hand, a strong metallurgical reaction could result in rough nonplanar metal-semiconductor interface with an electrically active area that is larger than the apparent geometric area. If Eq. 84 is multiplied by A , the electrically active area, we obtain where q(q4Bn - VF)is considered the activation energy. Over a limited range of temper- ature around room temperature, the value of A** and bBBarne essentially temperature independent. Thus for a fixed forward bias V, the slope of a plot of In(IF/P) versus 1/Tyields the barrier height 4Bna,nd the ordinate intercept at 1/T= 0 yields the product of the electrically active area A and the effective Richardson constant A**. To illustrate the importance of the activation-energy method in the investigation of interfacial metallurgical reactions, Fig. 29 shows the activation-energy plots of the saturation current in Al-n-Si contacts of different barrier heights, formed simply by annealing at various temperature^.^^ The slopes of these plots indicate a nearly linear increase of effective Schottky barrier height from 0.71 to 0.81 V for annealing temperatures between 450°C and 650°C. These observations were also confirmed with I-V and C-V measurements. Also supposedly when the A1-Si eutectic temperature (= 580°C) is reached, the true metallurgical nature of the metal-semiconductor inter- face must be considerably modified. Determination of the ordinate intercepts from the plots shown in Fig. 29 indicates that the electrically active area increases by a factor of two, when the annealing temperature exceeds the Al-Si eutectic temperature. 150 10-9 I 3.4 MEASUREMENT OF BARRIER HEIGHT 175 T ("C) 100 50 25 0 I I I I 1W'O Annealing temperature Without anneal 1V'* 10-13 2.5 3.0 3.5 4.0 Measurement temperature 1000/T (K-l) Fig. 29 Activation energy plots for determination of barrier height. (After Ref. 47.) 3.4.3 Capacitance-Voltage Measurement The barrier height can also be determined by the capacitance measurement. When a small ac voltage is superimposed upon a dc bias, incremental charges of one sign are induced on the metal surface and charges of the opposite sign in the semiconductor. The relationship between C (depletion-layer capacitance per unit area) and Vis given by Eq. 10. Figure 30 shows some typical results where 1/C? is plotted against the applied voltage. The intercept on the voltage axis gives the built-in potential vbi from which the barrier height can be d e t e m ~ i n e d : ~ ~ , ~ ~ From the slope the carrier density can also be determined (Eq. 11) and it can be used to calculate @,. 176 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS 14 14 12 12 - 10 p E -v m 2 L6 B4 4 10 8 6 Bc 4 2 2 0 0 1 0 1 2 3 4 v, (V) VR (V) Fig. 30 1/C? versus applied voltage for W-Si and W-GaAs diodes. (After Ref. 44.) To obtain the barrier height of semiconductor which contain both shallow-level and deep-level impurities (Fig. 4),we need to measure the C-Vcurves at two different temperatures at multiple f r e q u e n c i e ~ . ~ ~ 3.4.4 Photoelectric Measurement The photoelectric measurement is an accurate and direct method of determining the barrier height.50When a monochromatic light is incident upon a metal surface, photocurrent may be generated. The basic setup is shown in Fig. 3 1. In a Schottky-barrier diode, two kinds of carrier excitation can occur that contribute to photocurrent; excitation over the barrier (process-1) and band-to-band excitation (process-2). In measuring the barrier height, only process-l is useful and the most useful wavelengths should be in the range of qq&B> h v and x > 3, Eq. 119 reduces to R cc (hv - h ~ , ) ~ . (120) When the square root of the photoresponse is plotted as a function of photon energy, a straight line should be obtained, and the extrapolated value on the energy axis should give directly the barrier height. Figure 32 shows the photoresponse of W-Si and W-GaAs diodes, and the barrier heights of 0.65 and 0.80 eV are obtained respectively. The photoelectric measurement can be used to study other device and material parameters. It has been used to determine the image-force dielectric constant of Au-Si diodes.25By measuring the shift of the photothreshold under different reverse biases, one can determine the image-force lowering A@.From a plot of A 4 versus f i mth,e dielectric constant (E,/E,) can be determined, as shown previously in Fig. 12. Photoelectric measurement has been used to study the temperature dependence of the barrier height.52The photothreshold is measured as a function of the temperature of Au-Si diodes. The shift of photothreshold correlates reasonably well with the temperature dependence of the silicon bandgap. This result implies that the Fermi level at the Au-Si interface is pinned in relation to the valence-band edge and this is in agreement with our discussion in Section 3.2.3. 3.4.5 Measured Barrier Heights The I-K C-K activation-energyand photoelectric methods have been used to measure the barrier heights. For intimate contacts with a clean interface, these methods gener- ally yield consistent barrier heights within f 0.02 V. A large discrepancy between dif- ferent methods may result from such causes as contamination in the interface, an intervening insulating layer, edge leakage current, or deep impurity levels. The measured Schottky barrier heights for some elemental and compound semi- conductors are listed in Table 3. The barrier heights are representative values for metal-semiconductor contacts made by deposition of high-purity metals in a good vacuum system onto cleaved or chemically cleaned semiconductor surfaces. As expected, silicon and GaAs metal-semiconductor contacts are most extensively studied. Among the metals, gold, aluminum, and platinum are most commonly used. The barrier heights of metal silicides on n-type silicon and some of their properties are listed in Table 4. It should be pointed out that the barrier height is generally sensitive to pre-depo- sition surface preparation and post-deposition heat treatment^.^^ Figure 33 shows the barrier heights on n-type Si and GaAs measured at room temperature after annealing at various temperatures. When an AI-Si diode is annealed above 450°C, the barrier height begins to presumably due to diffusion of Si in A1 (also see Fig. 29). Table 3 Measured Schottky-Barrier Heights q&Bn(V) at 300 K on n-type Semiconductors. Each Entry Represents the Highest Value Reported for that System. Barrier Heights onp-type Can Be Estimated by &, + q5BB=n E$q (After Refs. 8, 53-59) Si GaAs Ge AlAs S i c GaP GaSb InP ZnS ZnSe ZnO CdS CdSe CdTe PbO E" 1.12 1.42 0.66 2.16 3.0 2.24 0.67 1.29 3.6 2.82 3.2 2.43 1.7 1.6 Ag 0.83 1.03 0.54 1.2 0.45 0.54 1.81 1.21 0.56 0.43 0.8 0.95 Al 0.81 0.93 0.48 1.3 1.06 0.6 0.5 0.8 0.75 0.68 0.76 ~ ~~ Au 0.83 1.05 0.59 1.2 1.4 1.3 0.61 0.52 2.2 1.51 0.65 0.78 0.7 0.86 Bi 0.9 0.2 1.14 0.78 Ca 0.4 0.56 Co 0.81 0.86 0.5 1.4 Cr 0.60 0.82 1.2 1.18 0.45 cu 0.8 1.08 0.5 1.3 1.2 0.47 0.42 1.75 1.1 0.45 0.5 0.33 0.82 Fe 0.98 0.84 0.42 1.11 0.78 Hf 0.58 0.82 1.84 In 0.83 0.64 0.6 1.5 0.91 0.3 0.69 0.93 Tr 0.77 0.91 0.42 Mg 0.6 0.66 1.04 0.3 0.82 0.49 Mo 0.69 1.04 1.3 1.13 Ni 0.74 0.91 0.49 1.4 1.27 0.32 0.45 0.83 0.96 0_ s_ 0.7 0.4 0.53 Pb 0.79 0.91 0.38 1.15 0.59 0.68 0.95 Pd 0.8 0.93 1.2 0.6 0.41 1.87 0.68 0.62 0.86 Pt 0.9 0.98 1.0 1.7 1.45 1.84 1.4 0.75 1.1 0.37 0.89 Rh 0.72 0.90 0.4 Ru 0.76 0.87 0.38 Sb 0.86 0.42 1.34 0.76 Sn 0.82 0.35 Ta 0.85 1.1 0.3 Ti 0.6 0.84 1.1 1.12 0.84 W 0.66 0.8 0.48 180 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS Table 4 Barrier Height of Metal Silicide on n-type Si. For Each System, the Barrier-Height Entry Represents the Highest Reported Value (After Refs. 8, 22, 56,6042) Metal Silicide CoSi CoSi, CrSi, DySi, ErSi, GdSi, HfSi HoSi, IrSi Ir,Si3 IrSi, MnSi Mn,,Si,, MoSi, Ni,Si Nisi Nisi, Pd,Si PtSi PQSi RhSi TaSi, TiSi, VSi, WSi, YSi, ZrSi, q5BBn(V) 0.68 0.64 0.57 0.37 0.39 0.37 0.53 0.37 0.93 0.85 0.94 0.76 0.72 0.69 0.75 0.75 0.66 0.75 0.87 0.78 0.74 0.59 0.60 0.65 0.86 0.39 0.55 Structure Cubic Cubic Hexagonal Forming Melting Temperature ("C) Temperature ("C) 400 1460 450 1326 450 1475 Orthorhombic 550 300 Cubic Tetragonal Tetragonal Orthorhombic Orthorhombic Cubic Hexagonal Orthorhombic Cubic Hexagonal Orthorhombic Tetragonal Orthorhombic 400 800a 1o o o a 200 400 800a 200 300 300 750a 650 650 600 2200 1275 1145 1980 1318 992 993 1330 1229 2200 1540 2150 1520 a Can be < 700°C under clean interface condition. Also, for metals that form silicides on silicon, the barrier height changes abruptly when the eutectic temperature is reached. The barrier height of a Pt-Si diode is 0.9 V. After annealing at 300°C or higher temperatures, PtSi is formed at the interface and $BBn decreases to 0.85 V.64For Pt-GaAs contact the barrier height increases from 0.84 V to 0.87 V when PtAs, is formed at the i n t e r f a ~ eF. o~r~a W-Si diode the barrier height remains constant until the annealing temperature is above lOOO"C, when WSi, is formed.66 So far in all the Schottky diodes discussed above, the metal layers are deposited so they are polycrystalline or amorphous in structure. For certain silicide contacts on silicon, it has been demonstrated that single-crystalline form can be grown epitaxially 3.5 DEVICE STRUCTURES 181 ?J ,' '- h 5 0 -- x Pt-GaAs PtSi-Si I s 8 Al-Si - WSi,-Si 'E 0.7 W-Si '0.6 0 200 400 600 800 1000 1200 Annealing temperature ("C) Fig. 33 Barrier heights on n-type Si and GaAs measured at room temperature after annealing at various temperatures. from the underlying single-crystalline silicon.67These epitaxial silicides include Nisi,, CoSi,, CrSi,, Pd,Si, EI-S~,-~Tb, Si,,, YSi,-,, and FeSi,. The epitaxial silicides have the properties of high uniformity and thermal stability. They provide a unique opportunity to study the fundamentalrelationship of barrier height to the microscopic interfacial configuration. It has been demonstrated that even on the same orientation of Si surface, different types (A and B) and interface structures (6-, 7-, or 8-folded) can be formed and that they give a difference in barrier height of as much as 0.14 eV. With this insight, the range of barrier heights observed on the same metal-semiconductor system can be rationalized, due to the statistical spacial distribution of the interfacial structure. 3.5 DEVICE STRUCTURES The earliest device structure is the point-contact rectifier using a small metal wire with a sharp point making contact with a semiconductor. The contact may be just a simple mechanical contact or it may be formed by an electrical discharge processes that may result in a small alloyedp-n junction. A point-contact rectifier usually has poor forward and reverse I-Vcharacteristics compared to a planar Schottky diode. Its characteristics are also dificult to predict 182 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS from theory, since the rectifiers are subject to wide variations such as the whisker pressure, contact area, crystal structure, surface condition, whisker composition, and heat or forming processes. The advantage of a point-contact rectifier is its small area, which can give very small capacitance, a desirable feature for microwave application. The disadvantages are its large spreading resistance (R, x p/2nro,where ro is the radius of the hemispheric point contact); large leakage current mainly due to the surface effect, which gives rise to poor rectification ratio, and soft reverse-breakdown characteristics due to a large concentrated field beneath the metal point. Most modern metal-semiconductor diodes are made by a planar process. The metal-semiconductor contacts are formed by various methods including thermal evaporation (resistive or electron-beam heating), sputtering, chemical decomposition, or plating of metals. Surface preparation methods include chemical etch, mechanical polish, vacuum cleaving, back sputtering, heat treatment, or ion bombardment. Since most metal-semiconductor contacts are formed in a vacuum system,68an important parameter concerning vacuum deposition of metals is the vapor pressure, which is defined as the pressure exerted when a solid or liquid is in equilibriumwith its own vapor.69Metals with high vapor pressure can be problematic during evaporation. The most-common structures in integrated circuits have oxide isolation at the metal perimeter. The small-area contact device, Fig. 34a, fabricated by a planar process on epitaxial n on n+-substrate,is useful as a microwave mixer d i ~ d e . ~ OT,o~ l achieve good performance, we have to minimize the series resistance and the diode capacitance. The metal overlap structure,’* Fig. 34b, gives near-ideal forward I- V characteristics and low leakage current at moderate reverse bias but the electrode sharp-edge effect will increase the reverse current when a large reverse bias is applied. This structure is extensively used in integrated circuits since it can be formed as an integral part of the metallization. Another approach is to use local-oxide isolation73to reduce the edge field, Fig. 34c. This approach requires a special planar process to incorporate a local oxidation step. In Fig. 34d, the diode is surrounded by a void or moat.74In this case, reliability problems can result from burying contaminants in the moat. To eliminate the electrode sharp-edge effects, many device structures have been proposed. Figure 34e uses a diffused guard ring4s to give near-ideal forward and reverse characteristics. This structure is useful as a tool to study static characteristics; however, it suffers from long recovery time and large parasitic capacitance due to the adjacent p-n junction. Figure 34f uses a double-diffused guard ring75to reduce the recovery time but the process is relatively complicated. Another guard-ring structure with a high resistivity layer on top of the active layer76is shown in Fig. 34g. Since the dielectric constant of the semiconductor is higher than that of an insulator, the parasitic capacitance is generally higher than the structure shown in Fig. 34b. The metaloverlap laterally diffused structure77is basically a double-Schottky diode (in parallel) that does not involve ap-n junction, Fig. 34h. This structure gives nearly ideal forward and reverse I- Vcharacteristics with very short reverse recovery time. How- s10 I n+ (a) Small-area contact n+ (0Double-diffused guard ring n+ (b) Metal overlap n+ (8) High-resistivity guard layer n+ (e) Oxide isolated n+ (h) Metal-overlap laterally difised 2 (d) Moat-etched n+ (i) Metal guard ring Metal \ n+ I ~~ ( e )Diffused guard ring (j)Truncated cone Fig. 34 Various metal-semiconductor device structures. Depletion widths are indicated by dashed lines. 183 184 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS ever, the process involves extra oxidation and difision steps, and the outer n--ring may increase the device capacitance. The guard-ring structure, Fig. 34i, has been proposed that uses an additional metal with higher barrier height. However, large variations in barrier height are generally difficult to obtain for covalent semiconductors. For certain microwave power generators (e.g., IMPATT diodes) one uses the truncated-cone structure,78Fig. 34J. The angle between the metal overhang and the semiconductor cone must be larger than 90" so that the electric field at the contact periphery is always smaller than that in the center. This angle ensures that the avalanche breakdown will occur uniformly inside the metal-semiconductor contact. One important application of Schottky diodes is the clamped bipolar transistor79 (Fig. 35). (For a detailed discussion of the bipolar transistor, see Chapter 5.) A Schottky diode can be incorporated into the base-collector terminal to form a clamped (composite) transistor with a very short saturation time constant (see Section 5.3.3). Fabrication is simply achieved by allowing the base contact to extend to straddle the surrounding collector region in the standard buried-collector t e ~ h n o l o g yI.n~t~he saturation region, the base-collector junction of the original transistor is slightly forward-biased instead of reverse-biased. If the forward voltage drop in the Schottky diode is much lower than the base-collector on-voltage of the original transistor, most of the excess base current flows through the Schottky diode which does not store minority carriers. Thus, the saturation time is reduced markedly compared with that of the original transistor. Since a Schottky diode in general carries a larger current compared to other diodes, the series resistance is critical to this device. To characterize the series resistance, we start with a modified current equation from Eq. 87, 00 Collector I Base a Emitter Base Emitter Collector n+ 1 Fig. 35 Composite bipolar transistor (npn)with a Schottky diode clamp connected between the base and the n-collector. (a) Circuit representation. (b) Cross-section of structure. 3.5 DEVICE STRUCTURES 185 From this, the differential resistance in the forward-bias regime is dependent on the bias or current, given by This equation shows that the differential resistance of the diode at low bias is inversely proportional to the current (= VkTlql).At high current when IR,>> VkTlq, the differential resistance would saturate to the value of R,. Typical experimental results of differential resistance versus current are shown in Fig. 36a for Au-Si and Au-GaAs diodes. Also shown is the result for Si point contact, discussed previously. We note that for a sufficiently high forward bias the junction resistance approaches a constant value. This value is the series resistance R, given by Ps where the first term on the right is the resistance integrated over the quasi-neutral region (between the depletion-layer edge and the heavily doped substrate, as in Fig. 23). The second term is the spreading resistance in the substrate of resistivity ps and thickness h, and a diode circular area of radius r (see last section). The last term R,, is the resistance due to the ohmic contact with the substrate. For a Schottky diode on a bulk semiconductor substrate, the first term is absent. Another simple method to extract the series resistance is from the semilog plot of the I-V curve shown in Fig. 36b. In the region where the current deviates from the exponential rise, the resistance is estimated by AV= IR,. An important figure of merit for microwave application of the Schottky diodes is the forward-bias cutoff frequencyLo,which is defined as f =- 1 ‘O- 2 nRFCF where R, and C, are the differential resistance and capacitance in a forward-bias range of z 0.1 V to the flat-band condition.81The value offd is considerably smaller than the corresponding cutoff frequency at zero bias, and can be used as a lower limit for practical consideration. A typical result is shown in Fig. 37. Note the higher cutoff frequency with a smaller junction diameter. Also for the same doping and junction diameter (e.g., 10 pm), the Schottky diode on n-type GaAs gives the highest cutoff frequency, mainly because the electron mobility is considerably higher, resulting in lower series resistance. To improve the high-frequency performance, devices that have smaller capacitance but larger contact areas are desirable. It has been shown that the Mott barrier can meet this requirement. A Mott barrier is a metal-semiconductor contact in which the epitaxial layer is very lightly doped so that the whole epitaxial layer is fully depleted, resulting in low capacitance. This holds true even under forward bias so the capacitance remains constant, independent of bias. Figure 38 shows the band diagram of a Mott barrier. Since for a given cutoff frequency the capacitance is much lower than that of a standard Schottky diode, the Mott diode diameter can be made much 109- 10’ 100 - A ‘O>.o ’ -i.o ’ -4.0 ’ -i.o ’ ’ I ~ O Bias (V) Fig. 36 (a) Measured differential resistance as a function of applied voltage for Au-Si, Au-GaAs, and point-contact diodes. (After Ref. 80.) (b) Estimate of series resistance from forward I-Vcurve. I I I I Ill11 I I 10‘6 2 4 6 8 10” 2 4 Dopant concentration in epitaxial layer (cm”) Fig. 37 Forward-bias cutoff frequency versus doping concentration in the epitaxial layer (0.5 pm thick) and with various junction diameters. (After Ref. 80.) 186 3.6 OHMIC CONTACT 187 E" barrier at zero bias. larger.82The current transport in a Mott barrier is dominated by diffusion, given by Eq. 72, due to the low majority-carrier concentration in the depletion region. 3.6 OHMIC CONTACT An ohmic contact is defined as a metal-semiconductor contact that has a negligible junction resistance relative to the total resistance of the semiconductor device. A satisfactory ohmic contact should not significantly perturb the device performance and can supply the required current with a voltage drop that is sufficiently small compared with the drop across the active region of the device. The last connection to any semiconductor device is always an on-chip metallic layer. Thus, for every semiconductor device there are at least two metal-semiconductor contacts to form connections. So a good ohmic is a must for every semiconductor device. The macroscopic parameter-specific contact resistance is defined as the reciprocal of the derivative of the current density with respect to the voltage across the interface. When evaluated at zero bias, this specific contact resistance R, is an important figure-of-merit for ohmic contacts:s3 Computer numerical simulation can be performed to get the ~ o l u t i o nA.l~ter~na~- ~ ~ tively, to derive this R, analytically, the I- V relationships described earlier in the chapter can be used. Again we use the comparison of doping (/Zoo) to temperature (kT) to decide which current mechanism is the dominant one. For low to moderate doping levels and/or moderately high temperatures, kT >> Eoo,the standard thermionic-emission expression (Eq. 84) is used to obtain Since only small applied voltage is relevant, the voltage dependence of the barrier height can be neglected. Equation 126 shows that low barrier height should be used to obtain small R,. For higher doping level, kT = E,,, TFE dominates and R, is given by39,s5 188 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS k K 0 cosh(EoolkT)coth(E00lk0exp[ q(@BBn-@n) R, = A * * T9 JGGZa Eoocoth(E,,lkT) kT I a exp[Eoocoqth@(BEn,,lkT) * (bnis negative for degenerate semiconductor.) This type of tunneling occurs at an energy above the conduction band where the product of carrier density and tunneling probability is at a maximum, given by Emof Eq. 93. With even higher doping level, kT << E,,, FE dominates, and the specific contact resistance is given by39,85 Provided that the barrier height cannot be made very small, a good ohmic contact should operate in this regime of tunneling. Specific contact resistance is a function of the barrier height (in all regimes), doping concentration (in TFE and FE), and temperature (more sensitive in TE and TFE). Qualitative dependence on these parameters is shown in Fig. 39 for a fixed semiconductor material. The trend and the regimes of operation are also indicated in the figure. In TE, R, is independent of doping concentration and dependent only on the barrier height &. In the other extreme of FE, in addition to &, R, has a depen- dence of a exp(N-1’2). The results of calculated specific contact resistance on silicon are given in Fig. 40. It is quite obvious that to obtain low values of R,, high doping concentration, low barrier height, or both must be used. And these are exactly the approaches used for all 11~71 1017 I 10’8 10’9 1020 102’ Doping concentration ( ~ r n - ~ ) Fig. 39 Dependence of specific contact resistance on doping concentration (and E,,), barrier height, and temperature. Regimes of TE, TFE, and FE are indicated. 3.6 OHMIC CONTACT 189 Doping concentration ( ~ r n - ~ ) Doping concentration ( ~ r n - ~ ) (4 (b) Fig. 40 Calculated specific contact resistance R, on (a) n-type and (b)p-type (100) Si sur- faces for various barrier heights (in eV) at room temperature. (After Ref. 86) ohmic contacts. On wide-gap semiconductors it is difficult to make good ohmic contacts. A metal does not generally exist with a low enough work hnction to yield a low barrier. In such cases, the general technique for making an ohmic contact involves the establishment of a more heavily doped surface layer. Another common technique is to add a heterojunction with a layer of small bandgap material and with high-level doping of the same type. For GaAs and other 111-V compound semiconductors, various technologies have been developed for the ohmic contact^.^' A summary of contact materials on common semiconductors is listed in Table 5 . As devices are miniaturized for advanced integrated circuits, the device current density usually increases. This demands not only smaller ohmic resistance but also a smaller contact area. The challenge of fabricating good ohmic contacts has been increasing with device miniaturization. The total contact resistance is given by R = - -R" A However, this expression is valid only for uniform current density across the whole area. We mention here two practical conditions that additional resistance components are important. For a small contact of radius r as shown in Fig. 41a, there is a spreading resistance in series with the ohmic contact given by89 R , = -L tan-1(') . 2nr 190 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS Table 5 Metal Ohmic Contacts for Various Semiconductors (After Ref. 88) Semiconductor Metal ~~ ~ n-Ge Ag-Al-Sb, Al, A1-Au-P, Au, Bi, Sb, Sn, Pb-Sn n-Si Ag, Al, A1-Au, Ni, Sn, In, Ge-Sn, Sb, Au-Sb, Ti, TiN n-GaAs Au(.88)Ge(.12)-Ni, Ag-Sn, Ag(.95)In(.05)-Ge n-GaP Ag-Te-Ni, Al, Au-Si, Au-Sn, In-Sn n-GaAsP Au-Sn n-GaAlAs Au-Ge-Ni n-InAs Au-Ge, Au-Sn-Ni, Sn n-InGaAs Au-Ge, Ni n-InP Au-Ge, In, Ni, Sn n-InSb Au-Sn, Au-In, Ni, Sn n-CdS Ag, Al, Au, Au-In, Ga, In, Ga-In n-CdTe In n-ZnSe In, In-Ga, Pt, InHg n-Sic W Semiconductor Metal p-Ge Ag, Al, Au, Cu, Ga, Ga-In, In, A1-Pd, Ni, Pt, Sn p-Si Ag, Al, A1-Au, Au, Ni, Pt, Sn, In, Pb, Ga, Ge, Ti, TIN p-GaAs Au(.84)Zn(. 16), Ag-In-Zn, Ag-Zn p-GaP Au-In, Au-Zn, Ga, In-Zn, Zn, Ag-Zn p-GaAsP Au-Zn p-GaAlAs Au-Zn p-InAs Al p-InGaAs Au-Zn, Ni p-InSb Au-Ge p-CdTe Au, In-Ni, Indalloy 13, Pt, Rh p-Sic Al-Si, Si, Ni This component approaches the bulk resistance of phlA for large rlh ratios. In cases where the contact is made on a horizontal diffusion layer (Fig. 41b, as in the case of a MOSFET), the total resistance between point X (leading edge of the contact) and the metal contact is given by90 h P P REFERENCES 191 R = JRW,R,coth(l&) where R, is the sheet resistance (Wo)of the diffusion layer. This equation takes into account nonuniform current density through the contact (current crowding) and contributions due to the sheet resistance itself. It can also be shown that in the limit of R, + 0, Eq. 131 reduces to Eq. 129. REFERENCES 1. F. Braun, “Uber die Stromleitung durch Schwefelmetalle,” Ann. Phys. Chem., 153, 556 (1 874). 2. J. C. Bose, U S . Patent 775,840 (1904). 3. A. H. Wilson, “The Theory of Electronic Semiconductors,” Proc. R. SOC.Lond. Ser: A , 133,458 (1931). 4. W. Schottky, “Halbleitertheorie der Sperrschicht,” Naturwissenschaften, 26, 843 ( 1938). 5. N. F. Mott, “Note on the Contact between a Metal and an Insulator or Semiconductor,” Proc. Cambr: Philos. SOC.3, 4, 568 (1938). 6. H. A. Bethe, “Theory of the Boundary Layer of Crystal Rectifiers,” MTRadiat. Lab. Rep., 43-12 (1942). 7. H. K. Henisch, Rectzfiing Semiconductor Contacts, Clarendon, Oxford, 1957. 8. E. H. Rhoderick and R. H. Williams, Metal-Semiconductor Contacts, 2nd Ed., Clarendon, Oxford, 1988. 9. E. H. Rhoderick, “Transport Processes in Schottky Diodes,” in K. M. Pepper, Ed, Inst. Phys. Con$ Ser:,No. 22, Institute of Physics, Manchester, England, 1974,p. 3. 10. V. L. Rideout, “A Review of the Theory, Technology and Applications of Metal-Semicon- ductor Rectifiers,” Thin Solid Films,48,261 (1978). 11. R. T. Tung, “Recent Advances in Schottky Barrier Concepts,” Muter. Sci.Eng. R., 35, 1 (2001). 12. H. B. Michaelson, “Relation between an Atomic Electronegativity Scale and the Work Function,” IBMJ. Res. Dev.,22, 72 (1978). 13. G. I. Roberts and C. R. Crowell, “Capacitive Effects of Au and Cu Impurity Levels in Pt n-type Si Schottky Barriers,” Solid-State Electron., 16,29 (1973). 14. A. M. Cowley and S. M. Sze, “Surface States and Barrier Height of Metal-Semiconductor Systems,” J. Appl. Phys., 36, 3212 (1965). 15. J. Bardeen, “Surface States and Rectification at a Metal Semiconductor Contact,” Phys. Rev.,71,717 (1947). 16. C. A. Mead and W. G. Spitzer, “Fermi-Level Position at Metal-Semiconductor Interfaces,” Phys. Rev., 134, A713 (1964). 17. D. Pugh, “Surface States on the (111) Surface of Diamond,” Phys. Rev. Lett., 12, 390 (1964). 192 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS 18. W. E. Spicer, P. W. Chye, C. M. Garner, I. Lindau, and P. Pianetta, “The Surface Electronic Structure of 111-V Compounds and the Mechanism of Fermi Level Pinning by Oxygen (Passivation) and Metals (Schottky Barriers),” Surface Sci., 86,763 (1979). 19. W. E. Spicer, I. Lindau, P. Skeath, C. Y. Su, and P. Chye, “Unified Mechanism for Schottky-Barrier Formation and 111-V Oxide Interface States,” Phys. Rev. Lett., 44, 420 (1980). 20. L. Pauling, The Nature of& Chemical Bond, 3rd Ed., Cornell University Press, Ithaca, New York, 1960. 2 1. S. Kurtin, T. C. McGill, and C. A. Mead, “Fundamental Transition in Electronic Nature of Solids,” Phys. Rev.Lett., 22, 1433 (1969). 22. S. P. Murarka, Silicidesfor VLSIApplications,Academic Press, New York, 1983. 23. G. Ottaviani, K. N. Tu, and J. W. Mayer, “Interfacial Reaction and Schottky Barrier in Metal-Silicon Systems,” Phys. Rev.Lett., 44,284 (1980), 24. J. M. Andrews, Extended Abstracts, Electrochem. SOC.Spring Meet., Abstr. 191 (1975), p. 452. 25. S. M. Sze, C. R. Crowell, and D. Kahng, “Photoelectric Determination of the Image Force Dielectric Constant for Hot Electrons in Schottky Barriers,” J. Appl. Phys., 35, 2534 (1 964). 26. C. D. Salzberg and G. G. Villa, “Infrared Refractive Indexes of Silicon Germanium and Modified Selenium Glass,”J. Opt. SOC.Am.,47, 244 (1957). 27. J. M. Shannon, “Reducing the Effective Height of a Schottky Barrier Using Low-Energy Ion Implantation,” Appl. Phys. Lett., 24, 369 (1974). 28. J. M. Shannon, “Increasing the Effective Height of a Schottky Barrier Using Low-Energy Ion Implantation,” Appl. Phys. Lett., 25, 75 (1974). 29. J. M. Andrews, R. M. Ryder, and S. M. Sze, “Schottky Barrier Diode Contacts,” US. Patent 3,964,084 (1976). 30. J. M. Shannon, “Control of Schottky Barrier Height Using Highly Doped Surface Layers,” Solid-state Electron., 19,537 (1976). 31. C. R. Crowell, “The Richardson Constant for Thermionic Emission in Schottky Barrier Diodes,” Solid-state Electron., 8, 395 (1965). 32. C. R. Crowell and S. M. Sze, “Current Transport in Metal-Semiconductor Barriers,” SolidState Electron., 9, 1035 (1966). 33. C. R. Crowell and S. M. Sze, “Electron-Optical-PhononScattering in the Emitter and Collector Barriers of Semiconductor-Metal-Semiconductor Structures,” Solid-state Electron., 8, 979 (1965). 34. C. W. Kao, L. Anderson, and C. R. Crowell, “Photoelectron Injection at Metal-Semiconductor Interface,” Surface Sci., 95,321 (1980). 35. C. R. Crowell and S. M. Sze, “Quantum-Mechanical Reflection of Electrons at MetalSemiconductor Barriers: Electron Transport in Semiconductor-Metal-Semiconductor Structures,”J. Appl. Phys., 37,2685 (1966). 36. C. Y. Chang and S. M. Sze, “Carrier Transport across Metal-Semiconductor Barriers,” Solid-State Electron., 13,727 (1970). 37. J. M. Andrews and M. P. Lepselter, “Reverse Current-Voltage Characteristics of MetalSilicide Schottky Diodes,” Solid-state Electron., 13, 1011 (1970). REFERENCES 193 38. C. R. Crowell and M. Beguwala, “Recombination Velocity Effects on Current Diffusion and Imref in Schottky Barriers,” Solid-state Electron., 14, 1149 (1971). 39. F. A. Padovani and R. Stratton, “Field and Thermionic-FieldEmission in Schottky Barriers,” Solid-state Electron., 9, 695 (1966). 40. A. Y. C. Yu and E. H. Snow, “MinorityCarrier Injection of Metal-SiliconContacts,”SolidState Electron., 12, 155 (1969). 41. D. L. Scharfetter, “Minority Carrier Injection and Charge Storage in Epitaxial Schottky Barrier Diodes,” Solid-state Electron., 8,299 (1965). 42. H. C. Card, “TunnellingMIS Structures,”Inst. Phys. ConJ Sex, 50, 140 (1980). 43. M. Y. Doghish and F. D. Ho, “A Comprehensive Analytical Model for Metal-Insulator- Semiconductor (MIS) Devices,” ZEEE Trans. Electron Dev., ED-39, 2771 (1992). 44. C. R. Crowell, J. C. Sarace, and S. M. Sze, “Tungsten-SemiconductorSchottky-Barrier Diodes,” Trans. Met. SOCA. I M ,233,478 (1965). 45. M. P. Lepselter and S. M. Sze, “Silicon Schottky Barrier Diode with Near-Ideal I-VCharacteristics,”Bell Syst. Tech.J., 47, 195 (1968). 46. J. M. Andrews and F. B. Koch, “Formation of Nisi and Current Transport across the Nisi-Si Interface,”Solid-state Electron., 14,901 (1971). 47. K. Chino, “Behavior of Al-Si Schottky Barrier Diodes under Heat Treatment,” Solid-state Electron., 16, 119 (1973). 48. A. M. Goodman, “Metal-Semiconductor Barrier Height Measurement by the Differential CapacitanceM e t h o d a n e Carrier System,”J. Appl. Phys., 34,329 (1963). 49. M. Beguwala and C. R. Crowell, “Characterization of Multiple Deep Level Systems in Semiconductor Junctions by Admittance Measurements,” Solid-State Electron., 17, 203 (1974). 50. C. R. Crowell,W. G. Spitzer,L. E. Howarth,and E. Labate, “AttenuationLength Measurements of Hot Electrons in Metal Films,”Phys. Rev., 127,2006(1962). 51. R. H. Fowler, “The Analysis of Photoelectric Sensitivity Curves for Clean Metals at Various Temperatures,”Phys. Rev.,38,45 (1931). 52. C. R. Crowell, S. M. Sze, and W. G. Spitzer, “Equality of the Temperature Dependence of the Gold-Silicon Surface Barrier and the Silicon Energy Gap in Au n-type Si Diodes,” Appl. Phys. Lett., 4 , 91 (1964). 53. J. 0. McCaldin, T. C. McGill, and C. A. Mead, “Schottky Barriers on Compound Semiconductors: The Role of the Anion,”J. Vac.Sci. Technol.,13, 802 (1976). 54. J. M. Andrews, “The Role of the Metal-Semiconductor Interface in Silicon Integrated Circuit Technology,”J. Vac.Sci. Technol.,11,972 (1974). 55. A. G Milnes, Semiconductor Devices and Integrated Electronics, Van Nostrand, New York, 1980. 56. Properties of Silicon, INSPEC, London, 1988. 57. Properties of GalliumArsenide, INSPEC, London, 1986.2nd Ed., 1996. 58. G. Myburg, F. D. Auret, W. E. Meyer, C. W. Louw, and M. J. van Staden, “Summary of Schottky Barrier Height Data on Epitaxially Grown n- and p-GaAs,” Thin Solid Films, 325, 181 (1998). 59. N. Newman, T. Kendelewicz, L. Bowman, and W. E. Spicer, “Electrical Study of Schottky Barrier Heights on Atomically Clean and Air-Exposed n-InP (110) Surfaces,”Appl. Phys. Lett., 46, 1176 (1985). 194 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS 60. J. M. Andrews and J. C. Phillips, “Chemical Bonding and Structure of Metal-Semiconductor Interfaces,” Phys. Rev.Lett., 35, 56 (1975). 61. G. J. van Gurp, “The Growth of Metal Silicide Layers on Silicon,” in H. R. Huff and E. Sirtl, Eds., Semiconductor Silicon 1977, Electrochemical Society, Princeton, New Jersey, 1977,p. 342. 62. I. Ohdomari, K. N. Tu, F. M. d’Heurle, T. S. Kuan, and S. Petersson, “Schottky-Barrier Height of Iridium Silicide,” Appl. Phys. Lett., 33, 1028 (1978). 63. J. L. Saltich and L. E. Terry, “Effects of Pre- and Post-Annealing Treatments on Silicon Schottky Barrier Diodes,” Proc. IEEE, 58,492 (1970). 64. A. K. Sinha, “Electrical Characteristics and Thermal Stability of Platinum Silicide-toSilicon Ohmic Contacts Metallized with Tungsten,” J. Electrochem. Soc., 120, 1767 (1973). 65. A. K. Sinha, T. E. Smith, M. H. Read, and J. M. Poate, “n-GaAs Schottky Diodes Metallized with Ti and PUTi,” Solid-state Electron., 19,489 (1976). 66. Y. Itoh and N. Hashimoto, “Reaction-Process Dependence of Barrier Height between Tungsten Silicide and n-Type Silicon,” J. Appl. Phys., 40,425 (1969). 67. R. Tung, “Epitaxial Silicide Contacts,” in R. Hull, Ed., Properties of Crystalline Silicon, INSPEC, London, 1999. 68. For general references on vacuum deposition, see L. Holland, VacuumDeposition of Thin Films, Chapman & Hall, London, 1966; A. Roth, VacuumTechnology,North-Holland, Amsterdam, 1976. 69. R. E. Honig, “Vapor Pressure Data for the Solid and Liquid Elements,” RCARev.,23,567 (1962). 70. D. T. Young and J. C. Irvin, “Millimeter Frequency Conversion Using Au-n-type GaAs Schottky Barrier Epitaxy Diode with a Novel Contacting Technique,” Proc. IEEE., 53, 2130 (1965). 71. D. Kahng and R. M. Ryder, “Small Area Semiconductor Devices,” U S . Patent 3,360,851 (1968). 72. A. Y. C. Yu and C. A. Mead, “Characteristics of Al-Si Schottky Bamer Diode,” Solid-State Electron., 13, 97 (1970). 73. N. G. Anantha and K. G. Ashar, IBMJ. Rex Dev., 15,442 (1971). 74. C. Rhee, J. L. Saltich, and R. Zwernemann, “Moat-Etched Schottky Barrier Diode Dis- playing Near Ideal I- VCharacteristics,” Solid-State Electron., 15, 1181 (1972). 75. J. L. Saltich and L. E. Clark, “Use of a Double Diffused Guard Ring to Obtain Near Ideal I- VCharacteristics in Schottky-Barrier Diodes,” Solid-state Electron., 13, 857 (1970). 76. K. J. Linden, “GaAs Schottky Mixer Diode with Integral Guard Layer Structure,” IEEE Trans. Electron Dev., ED-23,363 (1976). 77. A. Rusu, C. Bulucea, and C. Postolache, “The Metal-Overlap-Laterally-Diffused (MOLD) Schottky Diode,” Solid-state Electron., 20,499 (1977). 78. D. J. Coleman Jr., J. C, Irvin, and S. M. Sze, “GaAs Schottky Diodes withNear-Ideal Char- acteristics,” Proc. IEEE, 59, 1121 (1971). 79. K. Tada and J. L. R. Laraya, “Reduction of the Storage Time of a Transistor Using a Schottky-Barrier Diode,” Proc. IEEE, 55,2064 (1967). PROBLEMS 195 80. J. C. Irvin and N. C. Vanderwal, “Schottky-Barrier Devices,” in H. A. Watson, Ed., Microwave Semiconductor Devices and Their Circuit Applications, McGraw-Hill, New York, 1968. 81. N. C. Vanderwal, “A Microwave Schottky-Barrier Varistor Using GaAs for Low Series Resistance,” Tech. Dig. IEEE IEDM, (1967). 82. M. McColl and M. F. Millea, “Advantages of Mott Bamer Mixer Diodes,” Pmc. ZEEE, 61, 499 (1973). 83. C. Y. Chang, Y. K. Fang, and S. M. Sze, “Specific Contact Resistance of Metal-Semiconductor Barriers,” Solid-StateElectron., 14,541 (1971). 84. A. Y. C. Yu, “Electron Tunneling arid Contact Resistance of Metal-Silicon Contact Barriers,” Solid-StateElectron., 13,239 (1970). 85. C. R. Crowell and V. L. Rideout, “Normalized Thermionic-Field (T-F) Emission in MetalSemiconductor (Schottky) Barriers,” Solid-StateElectron., 12, 89 (1969). 86. K. K. Ng and R. Liu, “On the Calculation of Specific Contact Resistivity on (100) Si,” ZEEE Trans. Electron Dev.,ED-37, 1535 (1990). 87. V. L. Rideout, “A Review of the Theory and Technology for Ohmic Contacts to Group 111-V Compound Semiconductors,” Solid-StateElectron., 18, 541 (1975). 88. S. S. Li, SemiconductorPhysical Electronics, Plenum Press, New York, 1993. 89. R. H. Cox and H. Strack, “Ohmic Contacts for GaAs Devices,” Solid-State Electron., 10, 1213 (1967). 90. H. Murrmann and D. Widmann, “Current Crowding on Metal Contacts to Planar Devices,” IEEE Trans. Electron Dev., ED-16, 1022 (1969). PROBLEMS 1. Draw the band diagrams of the conduction band and the Fermi level for GaAs metal-semiconductor contacts with n-type doping levels of (a) lOI5~ m - (~b), 1017~ m - a~nd, (c) lo1*~ m - T~h.e barrier height (q4BnOis) 0.80 eV. 2. For a Au-n-Si metal-semiconductor contact with a donor concentration of 2 . 8 ~ 1 0~, ~m - ~ , what is the Schottky-barrier lowering at thermal equilibrium and the corresponding location of the lowering. The bamer height (qbBnOis)0.80 eV. 3. Derive Eq. 72. Fill in detailed steps in the derivation. 4. Find the minority current density and the injection ratio at a low-injection condition for a Au-Si Schottky-barrier diode with 4Bn= 0.80 V. The silicon is 1 a-cm, n-type with zp = 100 ps. 5. Based on the theoretical result on p. 732 in the paper by Chang/Sze [Solid-StateElectron., 13,727 (1970)], find the ideality factor for a Schottky contact with No = 10l8~ m at- 77~ K. 6. Derive Eq. 42 and find the limiting value of 4; forp, > n2 and up, >> Wn,. 7. The reverse saturation currents of a Schottky diode and a p-n junction at 300 K are 5x 1@*A and 10-l2 A, respectively. The diodes are connected in series and are driven by a constant current of 0.5 mA. Find the total voltage across the diodes. 8. (a) Find the barrier height and donor concentration of the W-GaAs Schottky bamer shown in Fig. 30. 196 CHAPTER 3. METAL-SEMICONDUCTOR CONTACTS (b) Compare the barrier height with that obtained from the saturation current density of 5 x l t 7Ncm2 shown in Fig. 25, assumeA**= 4 A/cm2-K2. (c) If there is a difference in barrier height, is the difference consistent with the Schottkybarrier lowering? 9. For a metal-n-Si contact, the barrier height obtained by photoelectric measurement is 0.65 V while the voltage intercept obtained from C-V measurement is 0.5 V. Find the doping concentration of the uniformly doped silicon substrate. 10. The capacitance of a Au-n-GaAs Schottky-barrier diode is given by the relation 1/C? = 1 . 5 7 ~ 1 -0 ~2 ~. 1 2 ~ 1 0 ~w~here C i s expressed in pF and Vis in volts. Taking the diode area to be 0.1 cm2, calculate the built-in potential, the barrier height, and the dopant concentration. 11. The forward-bias cutoff frequency for a Pd-GaAs contact made on an n-type epitaxial layer of 0.5 pm thick is 370 GHz. If the circular contact area is 1 . 9 6 ~ 1 0 c- m~ 2, find the depletion width under the forward-bias condition. 12. An ohmic contact has an area of 10-6 cm2 and is formed on an n-type silicon with No = 3x1OZ0~ m - T~h.e barrier height is 0.8 V and the electron effective mass is mi = 0.26 mo.Find the voltage drop across the contact when a forward current of 1 A flows through it. {Hint:The current across the contact can be expressed as Z = Zoexp[-C2( bBn- V)/PD] where I, is a constant and C, = 4 ms/h .} Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. Metal-Insulator-Semiconductor Capacitors 4.1 INTRODUCTION 4.2 IDEAL MIS CAPACITOR 4.3 SILICON MOS CAPACITOR 4.1 INTRODUCTION The metal-insulator-semiconductor (MIS) capacitor is the most useful device in the study of semiconductor surfaces. Since most practical problems in the reliability and stability of all semiconductor devices are intimately related to their surface conditions, an understanding of the surface physics with the help of MIS capacitors is of great importance to device operations. In this chapter we are concerned primarily with the metal-oxide-silicon (MOS) system. This system has been extensively studied because it is directly related to most silicon planar devices and integrated circuits. The MIS structure was first proposed as a voltage-controlled varistor (variable capacitor) in 1959 by Moll' and by Pfann and Garrett.2 Its characteristics were then analyzed by FrankP and Lindne~-T.~he first successful MIS structure was made of SiO, grown thermally on silicon surface by Ligenza and Spitzer in 1960.5This seminal experimental success immediately led to the first report of MOSFET by Kahng and Atalla.6 Further study on this SO2-Si system was reported by Termaq7 and Lehovec and Slobodskoy.8A comprehensive and in-depth treatment of the MOS capacitor can be found in MOSPhysics and Technologyby Nicollian and Brews.9The Si-SiO, system remains the most ideal and most practical MIS structure to date. 197 198 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS Semiconductor Ohmic contact Fig. 1 Metal-insulator-semiconductor (MIS) capacitor, in its simplest form. 4.2 IDEAL MIS CAPACITOR The metal-insulator-semiconductor (MIS) structure is shown in Fig. 1, where d is the thickness of the insulator and Vis the applied voltage. Throughout this chapter we use the convention that the voltage Vis positive when the metal plate is positively biased with respect to the semiconductor body. The energy-band diagram of an ideal MIS structure without bias is shown in Fig. 2, for both n-type andp-type semiconductors. An ideal MIS capacitor is defined as follows: (1) The only charges that can exist in the structure under any biasing conditions are those in the semiconductor and those, with an equal but opposite sign, on the metal surface adjacent to the insulator, i.e., there is no interface trap nor any kind of oxide charge; (2) There is no carrier transport through the insulator under dc biasing conditions or the resistivity of the insulator is infinite. Furthermore, for the sake of simplicity we assume the metal is chosen such that the difference between the Metal Insulator n-semiconductor (4 t "1 Metal Insulator p-semiconductor (b) Fig. 2 Energy-band diagrams of ideal MIS capacitors at equilibrium ( V = 0).(a) n-type semiconductor. (b) p-type semiconductor. 4.2 IDEAL MIS CAPACITOR 199 metal work function b,,,and the semiconductor work function is zero, or bmS= 0. The above conditions, with the help of Fig. 2, are equivalent to: (14 E ) = 4 m - ( x +EJ - b p ) = 0 forp-type (lb) bms bm-(X+ YBp 24 4 x xi where and are the electron affinities for the semiconductor and insulator respec- tively, and yBny, Bp4,n,bpare the Fermi potentials with respect to the midgap and band edges. In other words, the band is flat (flat-band condition) when there is no applied voltage. The ideal MIS capacitor theory to be considered in this section serves as a foundation for understanding practical MIS structures and to exploring the physics of semiconductor surfaces. When an ideal MIS capacitor is biased with positive or negative voltages, basi- cally three cases may exist at the semiconductor surface (Fig. 3). Consider thep-type semiconductor first (top figures). When a negative voltage (V< 0) is applied to the metal plate, the valence-band edge E , bends upward near the surface and is closer to the Fermi level (Fig. 3a). For an ideal MIS capacitor, no current flows in the structure (or dEd& = 0), so the Fermi level remains flat in the semiconductor. Since the carrier A Fig. 3 Energy-band diagrams for ideal MIS capacitors under different bias, for the conditions of: (a) accumulation, (b) depletion, and (c) inversion. Tophottom figures are forp-typeln-type semiconductor substrates. 200 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS density depends exponentially on the energy difference ( E F - Ev),this band bending causes an accumulation of majority carriers (holes) near the semiconductor surface. This is the accumulation case. When a small positive voltage ( V >0) is applied, the bands bend downward, and the majority carriers are depleted (Fig. 3b). This is the depletion case. When a larger positive voltage is applied, the bands bend even more downward so that the intrinsic level Ei at the surface crosses over the Fermi level E F (Fig. 3c). At this point the number of electrons (minority carriers) at the surface is larger than that of the holes, the surface is thus inverted and this is the inversion case. Similar results can be obtained for the n-type semiconductor. The polarity of the voltage, however, should be changed for the n'type semiconductor. 4.2.1 Surface Space-Charge Region In this section we derive the relations between the surface potential, space charge, and electric field. These relations are then used to derive the capacitance-voltage characteristics of the ideal MIS structure in the following section. Figure 4 shows a more detailed band diagram at the surface of ap-type semiconductor. The potential y,(x) is defined as the potential E,(x)lqwith respect to the bulk of the semiconductor; At the semiconductor surface, y,(O) = ys,and is called the surface potential. The electron and hole concentrations as a function of y, are given by the following relations: Insulator I 4K (' 0) 1 . Fig. 4 Energy-band diagram at the surface of a p-type semiconductor. The potential energy q y, is measured with respect to the intrinsicFermi level Eiin the bulk. The surface potential y, is positive as shown. Accumulation occurs when ys < 0. Depletion occurs when yB, > y, > 0. Inversion occurs when y, > yB,. 4.2'IDEALMIS CAPACITOR 201 -4 Y PJX) = PpoexP($) = P,,exP(-PY,) (3b) where yP is positive when the band is bent downward (as shown in Fig. 4), npoandp,, are the equilibrium densities of electrons and holes, respectively, in the bulk of the semiconductor, and P= q/kT At the surface the densities are n,(O> = np,exP(PYs). (44 P,(O) = Pp,exP(-PYs) ' (4b) From previous discussions and with the help of the above equations, the following regions of surface potential can be distinguished: w, < 0 w, = 0 Accumulation of holes (bands bending upward). Flat-band condition. tyBp> w; > 0 Depletion of holes (bands bending downward). w, = yBp Fermi-level at midgap, EF = E,(O),np(0)=p,(O) = n,. 2yBP> w, > Weak inversion [electron enhancement, n,(O) >p,(O)]. w,> 2 yBpStrong inversion [n,(O) >ppoor NA]. The potential Y,(x) as a function of distance can be obtained by using the onedimensional Poisson equation where Ax)is the total space-charge density given by A x ) = 4(NA- N i +P, - np)1 (6) N i and N; are the densities of the ionized donors and acceptors, respectively. Now, in the bulk of the semiconductor, far from the surface, charge neutrality must exist. Therefore at (vp(oo)= 0, we have d x ) = 0 and N A - N j = npo-ppo (7) The resultant Poisson equation to be solved within the depletion region is therefore Integrating Eq. 8 from the surface toward the bulklo gives the relation between the electric field (Z? = - dlv,/dx)and the potential Y,: CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS We shall use the following abbreviations: where LO is the extrinsic Debye length for holes. [Note that n,/p, = exp(-2P~-,,).] Thus the electric field is given by with positive sign for W, > 0 and negative sign for W, < 0. To determine the electric field at the surface 8,,we let W, = ly,: From this surface field, we can deduce the total space charge per unit area by applying Gauss' law: A typical variation of the space-charge density Q, as a function of the surface potential W,is shown in Fig. 5, for ap-type silicon with NA = 4 ~ 1 0~' ~m a-t ro~om temperature. Note that for negative K, Q, is positive and it correspondsto the accu- mulation region. The function F is dominated by the first term in Eq. 12, that is, Q, cc exp(ql1yv,l/2kr). For ry,= 0, we have the flat-band condition and Q, = 0. For 2y-, > r,u, > 0, Q, is negative and we have the depletion and weak-inversion cases. The function F is now dominated by the second term, that is, Q, cc ,&. For K > 2 yB,we have the strong inversion case with the function F dominated by the fourth term, that is, Q, cc exp(q~,/2kT)A. lso note that this strong inversion begins at a surface potential, ty,(strong inversion) u 2 yBp= - 4 4.2.2 Ideal MIS Capacitance Curves Figure 6a shows the band diagram of an ideal MIS structure with the band bending of the semiconductor similar to that shown in Fig. 4 but in strong inversion. The charge distribution is shown in Fig. 6b. For charge neutrality of the system, it is required that 4.2 IDEAL MIS CAPACITOR 203 Accumu EV 10-9 1 Y, -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 !4 (V) Fig. 5 Variation of space-charge density in the semiconductor as a function of the surface potential K, for ap-type silicon with NA= 4x 1015~ r n a-t~room temperature. QM = - % > kT/q, the function F (Eq. 12) can be simplified to F= fis (2 VBp > ws > k T / q ) . (25) With this, the space-charge density (Eq. 15) can be reduced to 206 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS 0 - - v 0 I/ Vmin VT - +v Applied voltage V Fig. 7 MIS C-V curves. Voltage is applied to the metal relative to the p-semiconductor. (a) Low frequency. (b) Intermediate frequency. (c) High frequency. (d) High frequency with fast sweep (deep depletion).Flat-band voltage of V - 0 is assumed. which is the familiar depletion approximation. From Eqs. 18, 19, and 26, we can express the depletion width as a function of the terminal voltages. The quadratic equation gives a solution of qND 'ox Once W, is known, C, and % are deduced. The depletion capacitance (Eq. 22) can be estimated by With further increase in positive voltage, the depletion region widens which acts as a dielectric at the semiconductor surface in series with the insulator, and the total capacitance continues to decrease. The capacitance goes through a minimum and then increases again as the inversion layer of electrons forms at the surface. The minimum capacitance and the corresponding minimum voltage are designated Cminand Vmin respectively (Fig. 7). Since Ci is fixed, Cmincan be found by the minimum value of C,. The value of % corresponding to the minimum C, can be obtained by differentiation of Eq. 22 and setting it to zero, resulting in a transcendental equation9 4.2 IDEAL MIS CAPACITOR 207 JC0~h(PVs- P w d = sinh(Pry, - Pwd - sinh(-Pwd (29) m i F ( P~ . nv p o l ~ p o ) With a known K, Cminand Vmincan be determined from Eqs. 18-22. Note that the increase of the capacitance depends on the ability of the electron concentration to follow the applied ac signal. This only happens at low frequencies where the recombination-generation rates of minority carriers (in our example, electrons) can keep up with the small-signal variation and lead to charge exchange with the inversion layer in step with the measurement signal. Unlike depletion and weak inversion, at strong inversion the incremental charge is no longer at the edge of the depletion region but at the semiconductor surface inversion layer, resulting in a large capacitance. The placement of the incremental charge at the semiconductor side is depicted in Fig. 8 for the different cases of low frequency, high frequency, and deep depletion. Experimentally, it is found that for the metal-SO2-Si system the range in which the capacitance is most frequency-dependent is between 5 Hz and 1 kHz."J2 This is related to the carrier lifetime and thermal generation rate in the silicon substrate. As a consequence, MOS curves measured at higher frequencies do not show the increase of capacitance in strong inversion, Fig. 7 curve (c). High-Frequency Capacitance. The high-frequency curve can be obtained using an approach analogous to a one-sided abruptp-n junction. l 3 3 l 4 When the semiconductor surface is depleted, the ionized acceptors in the depletion region are given by - qN, W, where W, is the depletion width. Integrating the Poisson equation yields the potential distribution in the depletion region: a a a T" ~ I Fig. 8 In strong inversion, capacitance is a function of the small-signal frequency and the quiescent sweep rate. The incremental displacement charge (black area) is shown in cases of (a) low frequency, (b) high frequency, and (c) high frequency with a fast sweep rate (deep depletion, W, > W,,,,). 208 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS where the surface potential y, is given by When the applied voltage increases, w,and W, increase. Eventually, strong inversion will occur. As shown in Fig. 5 , strong inversion begins at I+V, = 2 y B . Once strong inversion occurs, the depletion-layer width reaches a maximum. When the bands are bent down far enough that w, = 2 yB,the semiconductor is effectively shielded from further penetration of the electric field by the inversion layer and even a very small increase in band bending (corresponding to a very small increase in the depletion- layer width) results in a very large increase in the charge density within the inversion layer. Accordingly, the maximum width WDmof the depletion region under steady- state condition can be obtained from Eq. 16, d y J.- 2&,ty,(strong inv) 4~,kTln(N,ln~) WDm = qZNA (32) The relationship between W, and the impurity concentration is shown in Fig. 9 for Si and GaAs, where N is equal to NAfor p-type and No for n-type semiconductors. This phenomena of maximum depletion width is unique to the MIS structure, and it does not occur inp-n junctions or Schottky barriers. Doping concentrationN ( ~ r n - ~ ) Fig. 9 Maximum depletion-layer width versus impurity concentration of semiconductors Si and GaAs under a heavy-inversion condition. 4.2 IDEAL MIS CAPACITOR 209 Another quantity of interest is the so-called turn-on voltage or threshold voltage, V pat which strong inversion occurs. From Eq. 18 and with proper substitutions, we obtain Note that even though the slow-varying quiescent voltage puts the additional charge at the surface inversion layer, the high-frequency small signal is too fast for the minority carriers and the incremental charge is put at the edge of the depletion region, as shown in Fig. 8b. The depletion capacitance is simply given by &,IWD,with a minimum value corresponding to the maximum depletion width W, Complete ideal C-Vcurves of the metal-SO2-Si system have been computed for various oxide thicknesses and semiconductor doping densities.l5 Figure 1Oa shows typical ideal C-V curves for p-type silicon. Note that as the oxide film becomes thinner, larger variation of the capacitance is obtained. Also the curves are sharper, reducing the threshold voltage V, Figure 10b shows the dependence of w, on the applied voltage for the same systems. Similarly, modulation of I+V~is more effective with thinner oxides. The critical parameters C,, CminC, kin,V , and Vminare calculated and plotted in Fig. 11. These ideal MIS curves will be used in subsequent sections to compare with experimental results and to understand practical MIS systems. The conversion to n-type silicon is achieved simply by changing the sign of the voltage axes. Converting to other insulators requires scaling the oxide thickness with the ratio of the permittivities of SiO, and the other insulator q(Si0,) d, = d,&,(insulator) (35) where d, is the equivalent SiO, thickness to be used in these curves, di and ziare the thickness and permittivity of the new insulator. For other semiconductors, the MIS curves similar to those in Fig. 10 can be constructed by using Eqs. 24 through 33. At high frequency and with a fast sweeping ramp in the direction toward strong inversion, the semiconductor does not have enough time to come to equilibrium even with the large-signal variation. Deep depletion is said to occur when the depletion width is wider than the maximum value at equilibrium. This is the condition which CCDs are operated under when they are driven with large bias pulses, to be discussed in Section 13.6. The depletion width and the incremental charge are shown in Fig. 8c for comparison. Figure 7 curve (d) shows that the capacitance will keep on decreasing with bias, which is similar to ap-n junction or Schottky barrier. At even higher voltages, impact ionization can occur in the semiconductor, to be discussed later in con- 210 l’O F--- Si-SO, N, = 1x 1016~ r n - ~ Fig. 10 (a) Ideal MOS C- V curves for various oxide thickness. Solid lines for low frequencies. Dashed lines for high frequencies. (b) Surface potential vs. applied voltage. (After Ref. 15.) nection with the avalanche effect. Under light illumination (see Section 4.3.5), however, extra minority carriers can be generated quickly and curve (d) will collapse to curve (c). 00 Oxide thickness (nm) (b) Fig. 11 Critical parameters of ideal Si0,-Si MOS capacitors as a function of doping level and oxide thickness. (a) Flat-band capacitance (normalized). (b) Low-frequency Cmin(normalized) (c) High-frequency Ckin (normalized). (d) V ,and low-frequency Vmin. 211 00 Oxide thickness (nm) (4 Fig. 11 (Continued) 212 Oxide thickness (nm) (a 4.3 SILICON MOS CAPACITOR 213 4.3 SILICON MOS CAPACITOR Of all the MIS capacitors, the metal-oxide-silicon (MOS) capacitor is by far the most practical and important, and is used as an example here. An appealing picture of the interface is the chemical composition of the interfacial regions as a consequence of thermal o~idationI.t~consists of a single-crystal silicon followed by a monolayer of SiO,, that is, incompletely oxidized silicon, then a thin strained region of SiO,, and the remainder stoichiometric, strain-free, amorphous SiO,. (The compound SiO, is stoichiometric when x = 2 and nonstoichiometric when 2 > x > 1). For a practical MOS capacitor, interface traps and oxide charges exist that will, in one way or another, affect the ideal MOS characteristics. The basic classifications of these traps and charges are shown in Fig. 12: (1) Inter- face traps of density Di,and trapped charges Q,, which are located at the Si-SiO, interface with energy states within the silicon forbidden bandgap and which can exchange charges with silicon in a short time; Q, is also determined by the occupancy or the Fermi level so its amount is bias dependent. Interface traps can possibly be produced by excess silicon (trivalent silicon), broken Si-H bonds, excess oxygen and impurities. (2) Fixed oxide charges Qp which are located at or near the interface and are immobile under an applied electric field. (3) Oxide trapped charges Qo,,which can be created, for example, by X-ray radiation or hot-electron injection; these traps are distributed inside the oxide layer. (4) Mobile ionic charges Q,, such as sodium ions, which are mobile within the oxide under bias-temperature stress conditions. 4.3.1 Interface Traps Tamrn,l7Shockley,18and others9have studied the charge Qii,n interface traps (histor- ically also called interface states, fast states, or surface states) and have shown that Q,, exists within the forbidden gap due to the interruption of the periodic lattice structure i Metal T SiO, 4SiO, Y -Y , .Y , .Y - .V - Y. . Y . , Y . \ Interface-trapped charge (Q,) tSi I Fig. 12 Terminology for charges associated with thermally oxidized silicon. (After Ref. 16.) 214 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS at the surface of a crystal. Shockley and Pearson experimentally found the existence of Q, in their surface conductance mea~urement.M'~easurements on clean surfaces20 in an ultra-high-vacuumsystem confirm that Q ,can be very high-on the order of the density of surface atoms (= l O I 5 atoms/cm*).For the present MOS capacitors having thermally grown SiO, on Si, most of the interface-trapped charge can be neutralized by low-temperature (45OOC) hydrogen annealing. The total surface traps can be as low as 1Olocm-2, which amounts to about one interface trap per lo5surface atoms. Similar to bulk impurities, an interface trap is considered a donor if it is neutral and can become positively charged by donating (giving up) an electron. An acceptor interface trap is neutral and becomes negatively charged by accepting an electron. The distribution functions (occupancy) for the interface traps are similar to those for the bulk impurity levels as discussed in Chapter 1: 1+ (1 1 1 exp [(El - EF)/kTl for donor interface traps and for acceptor interface traps, where E, is the energy of the interface trap, and the ground-state degeneracy is 2 for donor (go) and 4 for acceptor (gA)P.resumably every interface has both kinds of traps. A convenient notation is to interpret the sum of these by an equivalent Di,distribution, with an energy level called neutral level Eo above which the states are of acceptor type, and below which are of donor type, as shown in Fig. 13. To calculate the trapped charge, it can also be assumed that at room temper- Acceptor states (Neutral when empty, -charge when full) Donor states (Neutral when full, + charge when empty) -++EF Donor states Fig. 13 Any interface-trap system consisting of both acceptor states and donor states can be interpreted by an equivalent distribution with a neutral level E, above which the states are of acceptor type and below which of donor type. When EF is above (below) E,, net charge is - (+I. t ature, the occupancy takes on the value of 0 and 1 above and below EF With these c assumptions, the interface-trapped charge can now be easily calculated by: Q . = - q Di,dE E, above E,, lt EO = + q l F DitdE EF below E,. (37) The foregoing charges are the effective net charges per unit area (i.e., C/cmz). Because interface-trap levels are distributed across the energy bandgap, they are characterized by an interface-trap density distribution: D . = -I-dQ;, lf q dE Number of traps/cm*-eV . (38) This is the concept used to determine Dit experimentally-from the change of Q, in response to the change of EF or surface potential w,. On the other hand, Eq. 38 cannot distinguish whether the interface traps are of donor type or acceptor type but only determine the magnitude of Di,. When a voltage is applied, the Fermi level moves up or down with respect to the interface-trap levels and a change of charge in the interface traps occurs. This change of charge affects the MIS capacitance and alters the ideal MIS curve. The basic equivalent circuitz1incorporating the interface-trap effect is shown in Fig. 14a. In the figure, C; and C, are the insulator capacitance and the semiconductor depletion-layer capacitance, respectively. Ci, and R, are the capacitance and resistance associated with the interface traps and, thus, are also functions of energy. The product CiP, is defined as the interface-trap lifetime q,,which determines the frequency behavior of the interface traps. The parallel branch of the equivalent circuit in Fig. 14a can be converted into a frequency-dependent capacitance Cp in parallel with a frequencydependent conductance Gp,as shown in Fig. 14b, where I ' I 1': JCD (a) (b) (c) (d) Fig. 14 ( a x b ) Equivalent circuits including interface-trapeffects, Cia,nd Ri,.(After Ref. 21.) (c)Low-frequency limit. (d) High-frequency limit. 216 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTORCAPACITORS /- and Also of particular interest are the equivalent circuits in the low-frequency and high-frequencylimits, included in Fig. 14.In the low-frequencylimit, Ri,is set to zero and C, is in parallel to Ci,.In the high-frequencylimit, the Cjf-Ribtranch is ignored or open. Physically it means that the traps are not fast enough to respond to the fast signal. The total terminal capacitance for these two cases (low-frequency C, and high-frequency CHF)are; These equations and equivalent circuits will be useful in the measurement of interface traps, to be discussed next. 4.3.2 Measurement of Interface Traps Either capacitance measurement or conductance measurement can be used to evaluate the interface-trap density, because both the input conductance and the input capacitance of the equivalent circuit contain similar information about the interface traps. It will be shown that the conductancetechnique can give more accurate results, especially for MOS capacitors with relatively low interface-trap density (=1Ol0 cm-2-eV-1).The capacitance measurement, however, can give rapid evaluation of flat-band shift and the total interface-trappedcharge. Figure 15a shows qualitatively the high-frequency and low-frequency C-Vcharacteristics with and without interface traps. A very noticeable effect of the interface traps is that the curves are stretched out in the voltage direction. This is due to the fact that extra charge has to fill the traps, so it takes more total charge or applied voltage to accomplish the same surface potential w, (or band bending). This is demonstrated more clearly in Fig. 15b where w, is plotted against the apply voltage directly, with and without interface traps. As shown later, this w,- Vcurve can be used to determine Djt.Another point to be noted is the gap in capacitance between the low-frequency and high-frequencycurves, before the point of Vminnear strong inversion.This difference is proportional to Di,. One other helpful point is that interface traps affect the total capacitance in two ways. A direct impact is through the extra circuit elements Cit and Rit. A second impact is indirectly on CD.For a fixed bias, since some charge will be needed to fill the interface traps, the remaining charge to be put in the depletion layer is reduced and 4.3 SILICON MOS CAPACITOR 217 Low frequency High frequency (b) Fig. 15 (a) Influence of interface traps on high-frequency and low-frequency C-Vcurves. (b) The stretch out of C-V curves is due to a less effective modulation of surface potential by the applied voltage K Example is on p-type semiconductor. this will reduce the surface potential w, or band bending. But since the relationship between C, and w, is fixed (Eq. 22 or 28), changing w, means changing C, also. This explains that for the high-frequency limit, even though the equivalent circuit of Fig. 14d does not contain the C, element, the high-frequency C- Vcurve in Fig. 15a is still affected by interface traps, through C,. Observing the four curves in Fig. 15a will help to understand the different capacitance methods in determining Dj,.There are basically three methods; (1) low-frequency capacitance-to compare the measured low-frequency curve with theoretical ideal curve; (2) high-frequency capacitance-to compare the measured high-frequency curve with theoretical ideal curve; and (3) high-low-frequency capacitance-to compare the measured low-frequency to high-frequency curves. Before we discuss each of these capacitance methods, we first derive some useful terms that are valid for all. First the relationship between Cj,and Dii,s derived as follows. Since dQ, = qD, dE, and dE = qdty,, we obtain 218 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS = q2Di,. (43) Next we will derive the stretch out of the ys-Vcurve in relationship to interface traps. Using the low-frequency equivalent circuits of Fig. 14c, the applied voltage is partitioned between the oxide layer and the semiconductor layer (Eq. 18). The portion of the voltage across the semiconductor w, is simply given by the voltage divider of the capacitor network, i.e., Substitution of Eq. 43 into Eq. 44 gives From this equation, Ditcan be calculated if the lu,-Vrelationship (Fig. 15b) can be obtained from the capacitance measurement. High-Frequency Capacitance Method. Terman7was the first who developed the high-frequency method. This method, as shown in the equivalent circuit of Fig. 14d, has the advantage that it does not contain the circuit element of Ci,T.he measured C, as given by Eq. 42, can give C, directly. Once C, is known, w, can be calculated from theory and the w,- V relationship is obtained. Equation 45 is then used to deter- mine Dip Low-Frequency Capacitance Method. Berglund22was the first to use integration of low-frequency capacitance to obtain the w,-V relationship, which then is used for obtaining Dijfrom Eq. 45. Starting from Eq. 44 which is based on the low-frequency equivalent circuit of Fig. 14c, Integrating Eq. 46 over two applied voltages yields IV,v2 yS(V 2 )- yS(V , ) = (1 - %)dV+ constant. (47) Equation 47 indicates that the surface potential at any applied voltage can be determined by integrating the value of (1- CLF/Ci)T. he integrand constant can be the starting point at accumulation or strong inversion where w, is known and it has weak dependence on the applied voltage. Once w, is known, C, can be calculated from Eq. 45, provided that the doping profile is known. One disadvantage of the low-fre- 4.3 SILICON MOS CAPACITOR 219 quency capacitance method is the measurement difficulty in the presence of increased dc leakage for thinner oxides. High-Low-Frequency Capacitance Method. This method combining both highfrequency and low-frequency capacitance was developed by Castagne and V a ~ a i l l e . ~ ~ The advantage of this method is that no theoretical calculation is needed for comparison, and such calculation for a nonuniform doping profile is complicated, if the profile is known at all. Starting with the equations for low-frequency and high-frequency limits (Eqs. 41 and 42), we can express Defining the capacitance gap as AC = C,, - C, and using the relationship Dij= Cit/q2,we obtain the trap density directly for each bias point. As shown in this equation, the trap density, on the first order, is proportional to the capacitance gap AC. If the energy spectrum of Dj,is to be determined, either the low-frequency capacitance integration approach or the high-frequency method can be applied to determine w,. Conductance Method. Nicollian and Goetzberger give a detailed and comprehensive discussion of the conductance method.24 Difficulty arises in the capacitance methods because the interface-trap capacitance must be extracted from the measured capacitance which consists of oxide capacitance, depletion-layer capacitance, and interface-trap capacitance. As previously mentioned, both the capacitance and conductance as functions of voltage and frequency contain identical information about interface traps. Greater inaccuracies arise in extracting this information from the measured capacitance because the difference between two capacitances must be calculated. This difficulty does not apply to the measured conductance which is directly related to the interface traps. Thus conductance measurements yield more accurate and reliable results, particularly when Dijis low as in the thermally oxidized Si02-Si system. Figure 16 shows the measured capacitance and conductance at 5 and 100 kHz. The largest capacitance spread is only 14%while the magnitude of the conductance peak varies by over one order of magnitude in this frequency range. The simplified equivalent circuit in Fig. 14b illustrates the principle of the MIS conductance technique. The impedance of the MIS capacitor is measured by a bridge across the capacitor terminals. The insulator capacitance Ci is also measured in the region of strong accumulation. The reactance of the insulator capacitance is subtracted from this impedance and the resulting impedance converted into an admit- 220 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTORCAPACITORS 1000 g 600 4 400 88 200 'ci B 100 u I" -1 -6 -5 -4 -3 -2 -1 0 Gate bias (V) Fig. 16 Comparison of MIS capacitance and conductance measurement at two frequencies, showing that conductance is much more sensitive to frequency than to capacitance. (After Ref. 24.) tance. This leaves C, in parallel with the series RitCi,network of the interface traps (Fig. 14b). The equivalent parallel conductance Gp divided by w is given by Eq. 40 which does not contain C, and depends only on the interface-trap branch of the equivalent circuit. An expression to convert the measured admittance to the conductance of the interface-trap branch is given by 9 G = wC: Gin - 'itwrit w Gi2,+ w2(Ci- C i J 2 1+ w2ri2, (50) where the last term is a repeat of Eq. 40. At a given bias, GJw can be measured as a function of frequency. A plot of G,lw versus w goes through a maximum when writ= 1, and gives 5, directly. The value of GJw at the maximum is Cij2. Thus, the equivalent parallel conductance corrected for Ci gives C,, and 5, (=R,,C,,) directly from the measured conductance. Once Cit is known, the interface-trap density is obtained by using the relation D, = Cit/q2. Typical results in a Si-SiO, systemz5show that near the midgap Di, is relatively constant, but it increases toward the conduction- and valence-band edges. Orientation dependence is particularly important. In (100) orientation Di, is about an order of magnitude smaller than that in (111). This result has been correlated with the available bonds per unit area on the silicon ~ u r f a c eT.a~bl~e 1~ s~ho~ws the properties of 4.3 SILICON MOS CAPACITOR 221 Table 1 Properties of Silicon Crystal Planes Orientation Plane area Atoms in of unit cell cell area (111) &a212 2 (110) &a2 4 ( 100) a2 2 Available bonds in cell area 3 4 2 Atoms/cm2 Available bonds/cm2 7 . 8 5 ~ 1 0 ' ~ 11.8x1Ol4 9.6~10'~ 9.6~10'~ 6.8~10'~ 6.8~10'~ silicon crystal planes oriented along (11l), (1lo), and (100) directions. It is apparent that the (111) surface has the largest number of available bonds per area, and the (100) surface has the smallest. One would also expect that the (100) surface has the lowest oxidation rate which is advantageous for thin oxides. If we assume that the origin of interface traps is due to excess silicon in the oxide, then the lower the oxidation rate the smaller the amount of the excess silicon; thus the (100) surface should have the smallest interface-trap density. Therefore, all modern silicon MOSFETs are fabricated on (100)-oriented substrates. Interface traps in the Si-SiO, system comprise of many levels. These are so closely spaced in energy that they cannot be distinguished as separate levels and actually appear as a continuum over the bandgap of the semiconductor. The equivalent circuit for an MIS capacitor with a single-level time constant (Fig. 14a) should, therefore, be interpreted as for a certain bias or trap level. Figure 17 shows the variation of the time constant 5,versus surface potential (or ws trap level) for MOS capacitors with steam-grown oxides on (100) silicon substrates, where is the average surface potential (to be discussed later). These curves can be fitted by the following expressions: where op and a,are the capture cross sections of holes and electrons respectively, and V is the average thermal velocity. These results indicate that the capture cross section is independent of energy. The capture cross sections obtained24from Fig. 17 are 5 = 4 . 3 ~ 1 0 - lc~m2 and a,= 8 . 1 ~ 1 0 -cl m~ 2, where the value of V = lo7cm/s has been used. For (111)-orientedsilicon the variation of time constant versus surface potential is similar to that of (100) and the measured capture cross sections are smaller with 0- = 2 . 2 ~ 1 0 -cl m~ 2and a,= 5 . 9 ~ 1 0 -clm~ 2. We must also consider the statistical fluctuation of surface potential due to surface charges which include the fixed oxide charges Qfand the interface-trapped charges Q,. From Eq. 5Ib, a small fluctuation in kscauses a large fluctuation in zit. Assuming that surface charges are randomly distributed in the plane of the interface, the electric field at the semiconductor surface will fluctuate over the plane of the 222 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS Upper half of bandgap n-type (100) Lower half of bandgap p-type (100) I" 16 12 8 4 q( VBn + @,)IkT 0 4 8 12 16 q( Y B p - p S ) / k T Fig. 17 Variation of trap time constant 5, vs. energy. T = 300 K. (After Ref. 24.) interface. Figure 18 shows calculated values of CAW as a function of frequency for a Si-SiO, MOS capacitor biased in depletion and weak inversion, including the effect of time-constant dispersion resulting from the interface-trap continuum and the statis- tical (Poisson) distribution of surface charges ( Q ,+ Q,>. Experimental results are also Depletion \ (statistical model) I 16 14 h LL v 1" P 0 4 10 102 103 104 105 106 f (Hz) Fig. 18 Gplw vs. frequency for a Si-SiO, MOS capacitor biased in depletion region (broad curve) and weak-inversion region (narrow curve). Circles are experimental results. Lines are theoretical calculations. (After Ref. 24.) 4.3 SILICON MOS CAPACITOR 223 shown (open and solid circles); their excellent agreement with the statistical results indicates the importance of the statistical model. The impact of charge or potential fluctuation is also implicated in Fig. 18. In depletion, the potential fluctuation broadens the frequency range but the peak frequency is unaffected, which is the most-important parameter to be extracted. On the other hand, in weak inversion, potential fluctuation has a more profound effect. This is because potential fluctuation will cause some local regions to be in depletion and conductance in those regions dominates disproportionally. So even though the Gp/ w curve is not broadened and can be characterized by a single time constant, its value is shifted by an amount depending on the statistical nature of the charge fluctuation. To circumvent this problem, both n- and p-type devices can be used in the depletionregion measurement only to get the trap spectrum over the two halves of the bandgap. 4.3.3 Oxide Charges and Work-Function Difference Oxide charges, other than that of the interface traps, include the fixed oxide charge Qr, the mobile ionic charge Q,, and the oxide trapped charge Qot, as shown in Fig. 12. These will be discussed in sequence. In general, unlike interface-trapped charges, these oxide charges are independent of bias, so they cause a parallel shift in the gate-bias direction, as indicated in Fig. 19a. The flat-band voltage shift due to any “I 1 oxide charge is given by Gauss’ law; AV = - - Cj d x~(x)& where AX)is the charge density per unit volume. The effect on the voltage shift is weighted according to the location of the charge, i.e., the closer to the oxide-semiconductor interface, the more shift it will cause. Qualitatively the influence of positive oxide charges can be explained in Figs. 19b-d. Positive charge is equivalent to an added positive gate bias for the semiconductor so it requires a more negative gate bias to achieve the same original semiconductor band bending. Notice that in the new flatband condition (Fig. 19d), the oxide field is no longer zero. The fixed oxide charge Qrhas the following properties: It is located very close to the Si-SiO, interfa~ei;t~is generally positive; its density is not greatly affected by the oxide thickness or by the type or concentration of impurities in the silicon, but it depends on oxidation and annealing conditions, and on silicon surface orientation. It has been suggested that excess silicon (trivalent silicon) or the loss of an electron from excess oxygen centers (nonbridging oxygen) near the Si-SiO, interface is the origin of fixed oxide charge. In electrical measurements, Qfcan be regarded as a charge sheet located at the Si-SiO, interface, Mobile ionic charges can move back and forth through the oxide layer, depending on biasing conditions, and thus give rise to voltage shifts. The shift usually is 224 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS Positive oxide charges \ ,1‘ and/or lower gate work function \ + + JI, EV Fig. 19 (a) High-frequency C-Vcurve (onp-semiconductor), shifted along the voltage axis due to positive oxide charges. (b) Band diagram at flat band, original. (c) With positive oxide charges and (d) new flat-band bias. enhanced at elevated temperature. In severe cases, hysteresis can be seen when the gate voltage is swept in opposite polarities. It was first demonstrated by Snow et a1.28 that alkali ions, such as sodium, in thermally grown SiO, films are mainly responsible for the instability of the oxide-passivated devices. Reliability problems in semiconductor devices operated at high temperatures and voltages may be related to trace contamination by alkali metal ions. The voltage shift is given by Eq. 52 and is represented by A Vm = - -Q m Ci (54) where Q,,, is the effective net charge of mobile ions per unit area at the Si-SiO, inter- face and the actual mobile ions Ax) is used. To prevent mobile ionic charge contamination of the oxide during device life, one can protect it with a film impervious to mobile ions such as amorphous or small-crystallite silicon nitride. For amorphous Si,N,, there is very little sodium penetration. Other sodium barrier layers include A1,0, and phosphosilicate glass. Oxide trapped charge is associated with defects in SiO,. The oxide traps are usually initially neutral and are charged by introducing electrons and holes into the oxide layer. This can occur from any current passing through the oxide layer (to be 4.3 SILICON MOS CAPACITOR 225 discussed in next section), hot-carrier injection, or by photon excitation. The shift due to the oxide trapped charge is again given by Eq. 52, where Qo, is the effective net charge per unit area at the Si-SiO, interface. The total voltage shift due to all the oxide charges is the sum A V = AVf+ AVm+ AVO, = - Qf+ Qm + Qot Ci Work-Function Difference. For the preceding discussions on ideal MIS capacitor, it has been assumed that the work-function difference for a p-type semiconductor (Fig. 2b) is zero. If the value of bmSis not zero, the experimental C-V curve will be shifted from the theoretical curve by the same amount in gate bias, as indicated in Fig. 20. This shift is in addition to the oxide charges, so the net flat-band voltage becomes Figure 21 demonstrates the correlation of flat-band voltage with metal work function determined by different means. The energy band for the Si-SiO, interface has been obtained from electron photoemission measurement^;^^ SiO, bandgap is found to be about 9 eV, and the electron affinity ( q x i )is 0.9 eV. From photoresponse versus photon energy on various metals,29the intercept on the h v axis corresponds to the metal-Si02 barrier energy q& The metal work function is given by the sum of 4Band xi (refer to Fig. 2). The metal work functions as obtained from the photoresponse and the capacitance curves are in excellent agreement. 1 Oxide Fig. 20 (a) Band diagram at flat band, q5,,s = 0. (b) With a lower gate work function, zero bias, and ( c )new flat-band bias. 226 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS 1.o 0.9 0.8 'u-0.7 0.6 0.5 0.4 h .Bc* 60 950 b 40 v rn -g 30 8 320 8c 0" 10 a 0.3 -3 -2 - 1 0 1 2 '2.0 2.5 3.0 3.5 4.0 4.5 : 3 Gate bias (V) h v (eV) (4 (b) Fig. 21 Correlation of (a) flat-band voltage from capacitance measurement and (b) barrier height from photoresponse. (After Ref. 29.) In modern integrated-circuit processing, heavily doped polysilicon has been used to replace Al as the gate electrode. For an n+-polysilicongate, the Fermi level essentially coincides with the bottom of the conduction band E , and the effective work function #m is equal to the Si electron affinity (xsi= 4.05 V). For a p+-polysilicon gate, the Fermi level coincides with the top of the valence band E , and the effective work function bmis equal to the sum of xsiand E#q (5.17 V). This is one of the advantages of using poly-Si gates in MOSFETs since the same material can give dif- ferent work functions by doping. Figure 22 shows the work-function difference as a 1.o 0.8 0.6 0.4 0.2 $0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 - 1.2 1013 1014 1015 1016 1017 1018 N (~rn-~) Fig. 22 Work-function difference &s vs. doping, for gate electrodes of degenerate polysilicon and A1 onp- and n-Si. 4.3 SILICON MOS CAPACITOR 227 function of Si doping concentration for Al, Au, p+-, and n+-polysilicon gates. By an appropriate choice of gate electrode, both n- andp-type silicon surfaces can be varied from accumulation to inversion. 4.3.4 Carrier Transport In an ideal MIS capacitor the conductance ofthe insulating film is assumedto be zero. Real insulators, however, show some degree of carrier conduction when the electric field or temperature is sufficiently high. To estimate the electric field in an insulator under biasing conditions, we obtain where giand gSare the electric fields in the insulator and the semiconductor respectively, and 5 and .cSare the corresponding permittivities. The equation also assumes negligible oxide charges and that the flat-band voltage and the semiconductor band bending y, are small compared to the applied voltage. Table 2 summarizes the basic conduction processes in insulators. It also emphasizes the voltage and temperature dependence of each process that are used often to identify the exact conduction mechanism experimentally. Tunneling is the most-common conduction mechanism through insulators under high fields. The tunnel emission is a result of quantum mechanics by which the elec- Table 2 Basic Conduction Processes in Insulators Process Expression Voltage & temperature dependence Frenkel-Poole emission Ohmic [ ] J cc gjexp -q(bB8-kAT$%&) OC Vexp[&(2a,,/i- h ) ] cc Vexp(F) Z?. -AEa, Ionic conduction Jcc ‘eTxp(-) kT Space-chargelimited vz J = - 9&;,u 8d3 cc -Vexp($] T ccvz A** = effective Richardson constant. q4B = barrier height. Zt = electric field in insulator. = insulator permittivity. M* = effective mass. d = insulator thickens. AEoc= activation energy of electrons. AE,,= activation energy of ions. V = Z,d. a = J z d . b, c, and LS are constants. 228 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS tron wave function can penetrate through a potential barrier (see Section 1.5.7). It has the strongest dependence on the applied voltage but is essentially independent of the temperature. According to Fig. 23 tunneling can be divided into direct tunneling and Fowler-Nordheimtunneling where carriers tunnel through only a partial width of the barrier.31 The Schottky emission process is similar to the process discussed in Chapter 3, where thermionic emission over the metal-insulator barrier or the insulator-semiconductor barrier is responsible for carrier transport. In Table 2, the term subtracting from 4Bis due to image-force lowering (see Section 3.2.4). A plot of In(J/T2) versus 1/Tyields a straight line with a slope determined by the net barrier height. The Frenkel-Poole e m i ~ s i o n , 3s~ho, w~ ~n in Fig. 23d, is due to emission of trapped electrons into the conduction band. The supply of electrons from the traps is through thermal excitation. For trap states with Coulomb potentials, the expression is similar to that of the Schottky emission. The barrier height, however, is the depth of the trap potential well. The barrier reduction is larger than in the case of Schottky emission by a factor of 2, since the barrier lowering is twice as large due to the immobility of the positive charge. At low voltage and high temperature, current is carried by thermally excited electrons hopping from one isolated state to the next. This mechanism yields an ohmic characteristic exponentially dependent on temperature. The ionic conduction is similar to a diffusion process. Generally, the dc ionic conductivity decreases during the time the electric field is applied because ions cannot be readily injected into or extracted from the insulator. After an initial current flow, positive and negative space charges will build up near the metal-insulator and the semiconductor-insulator interfaces, causing a distortion of the potential distribution. When the applied field is removed, large internal fields remain which cause some, but Ei- Fig. 23 Energy-band diagrams showing conduction mechanisms of (a) direct tunneling, (b) Fowler-Nordheimtunneling,(c) thermionic emission, and (d) Frenkel-Pooleemission. 4.3 SILICON MOS CAPACITOR 229 not all, ions to flow back toward their equilibrium position. Because of this, hysteresis results in Z-Vtraces. The space-charge-limited current results from carriers injected into a lightly doped semiconductor or an insulator, where no compensating charge is present. The current for the unipolar trap-free case is proportional to the square of the applied voltage. Notice that the mobility regime is relevant here (see Section 1.5.8) since mobility is typically very low in insulators. For ultra-thin insulators, tunneling increases such that the conduction approaches that of the metal-semiconductor contact (see Section 3.3.6) where the barrier is measured at the semiconductor surface instead of the insulator and the thermionic-emission current is multiplied by a tunneling factor. For a given insulator, each conduction process may dominate in certain temperature and voltage range. The processes are also not exactly independent of one another and should be carefully examined. For example, for the large space-charge effect, the tunneling characteristic is found to be very similar to the Schottky-type emission.34 Figure 24 shows plots of current density versus 1/T for three different insulators, Si3N4,A1203,and SO2.The conduction here can generally be divided into three temperature range. At high temperatures (and high fields), the current J , is due to Frenkel-Poole emission. At low temperatures, the conduction is tunneling limited (J2) which is temperature insensitive. One can also observe that the tunneling current strongly depends on the barrier height, which is related to the energy gap of the insulators. At intermediate temperatures, the current J3 is ohmic in nature. An example showing different conduction processes at different bias is shown in Fig. 25. Note that the two curves of opposite polarities are virtually identical. The slight difference (especially at low fields) is believed to be mainly due to the difference in barrier heights at the gold-nitride and nitride-silicon interfaces. In high electric fields the current varies exponentially with the square root of the field, a characteristic of Frenkel-Poole emission. At low fields, the characteristic is ohmic. It has been found that at room temperature for a given field, the characteristics of current density versus field are essentially independent of the film thickness, electrode materials, and polarity of the electrodes. These results strongly suggest that the current is bulk-controlled rather than electrode-controlled as in Schottky-barrier diodes. 4.3.5 Nonequilibrium and Avalanche Going back to the capacitance curve-(d) of Fig. 7, we have a nonequilibrium condition such that the depletion width is larger than the maximum value W, at equilibrium. This condition is called deep depletion. As the bias is swept from depletion to strong inversion, a large concentration of minority carriers is needed at the semiconductor surface. This supply of minority camers is limited by the thermal generation rate. For a fast sweep rate, the thermal generation rate cannot keep up with the demand and deep depletion occurs. This phenomenon can also be explained by the charge placement shown in Fig. 8. The energy-band diagram for deep depletion is shown in Fig. 26a. Equilibrium condition (Fig. 26b) can be restored by slowing or Fig. 24 8(106 Vicm) 0.1 0.5 1 10-7 I I I 2 3 4 5678 35-3 7.) in-141 I" - 0 I I 1 2 3 J2 (103~TZ-m) Fig. 25 Current-voltage characteristics of Au-Si3N,-Si capacitor at room temperature. (After Ref. 35.) 230 4.3 SILICON MOS CAPACITOR 231 Fig. 26 Energy-band diagrams for MOS capacitor in (a) deep depletion (nonequilibrium), (b) equilibrium, and (c) deep depletion and avalanche injection of electrons into the oxide at higher bias. stopping the voltage ramp, by raising the temperature for larger thermal generation rate, or by shining light to produce additional electron-hole pairs. When switched to equilibrium, the field is redistributed, most of which is across the oxide layer. If driven into deep depletion with a sufficiently large bias, avalanche multiplica- tion and breakdown can occur in the semiconductor side (Fig. 26c), similar to that in a p-n junction. The breakdown voltage is defined as the gate voltage that makes the ionization integral equal to unity, when integrated along a path from the semicon- ductor surface to the depletion-layer boundary. The avalanche breakdown voltage in the MOS capacitor under the deep-depletion condition has been calculated based on a two-dimensional The results are shown in Fig. 27 for different doping levels and oxide thickness. It is interesting to compare these breakdown voltages to those of p-n junctions in Fig. 16a of Chapter 2. Bear in mind that for similar fields within the semiconductor, an MOS structure takes a higher bias because of the addi- tional voltage taken up in the oxide layer. Several interesting features in Fig. 27 should be pointed out. First, the breakdown voltage VBD,as a function of doping level, has a valley before it goes up again. The decrease of VBDis the same trend as in ap-n junction due to the increased field with doping. The rise after the minimum is because at high doping levels, the higher field at the semiconductor surface at breakdown induces a larger voltage across the oxide layer, leading to a higher terminal voltage. Another point is that for lower impurity concentrations, the MOS breakdown is actu- ally smaller than those ofp-n junctions. This is due to the inclusion of the edge effect in this study. Near the perimeter of the gate electrode, the field is higher due to the two-dimensional effect which leads to a lower breakdown voltage. 232 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTORCAPACITORS 00 \ 20 nm 10 I I I I /Ill 1014 1015 10’6 1017 10’8 Substrate impurity concentration N (cm”) Fig. 27 Breakdown voltage of MOS capacitor in deep-depletion condition vs. silicon doping concentration, with oxide thickness as the parameter. Edge effect causing lower breakdown has been included. (After Ref. 38.) Because of avalanche multiplication, reliability also becomes an issue due to the injection of carriers,39shown in Fig. 26c. Carriers generated by avalanche multiplication in the surface depletion layer, electrons in this example, will have enough energy to surmount the interfacial energy barrier and enter into the oxide layer. The energy barrier for electron injection is 3.2 eV (i.e., qxsi- qxi= 4.1 - 0.9), whereas for hole injection (on n-type substrate) it is 4.7 eV {i.e., [E,(SiO,) + qxi]- [E,(Si) + qxsi]}. So electrons have a higher injection probability because of the lower energy barrier. The passage of hot electrons into the oxide layer generally create fixed charge, bulk and interface traps in the oxide.g Hot-carrier or avalanche injection is closely related to many MOS device operations. For example, in a MOSFET, channel carriers can be accelerated by the sourceto-drain electric field to have sufficient energy to surmount the Si-SiO, interfacial energy barrier. These effects are undesirable because they create a change in device characteristics during operation. On the other hand, these phenomena can be utilized in nonvolatile semiconductor memories (see Section 6.7). Another source of hot carriers is ionization radiation such as X-rafO or y - r a ~ . ~ l Ionization radiation creates electron-hole pairs in the oxide by breaking Si-0 bonds. 4.3 SILICON MOS CAPACITOR 233 The electric field applied across the oxide during radiation exposure drives the generated carriers in opposite directions. The electrons are considerably more mobile than the holes as they rapidly drift toward the positive electrode where most flow out into the external circuit; the holes drift much more slowly toward the negative electrode and some become trapped. The trapped holes constitute the radiation-induced positive oxide charge often observed. These trapped holes may also be responsible for the increased interface-trap density usually associated with ionizing r a d i a t i ~ n . ~ Under optical illumination, the main effect on the MIS capacitance curves is that the capacitance in the strong-inversion region approaches the low-frequency value as the intensity of illumination is increased. Two basic mechanisms are responsible for this effect. The first is the decrease in the time constant of minority-carrier generation in the inversion layer.12 The second is the generation of electron-hole pairs by photons, which causes a decrease of the surface potential tys under constant applied voltage. This decrease of (vsresults in a reduction of the depletion width with a corresponding increase of the capacitance. The second mechanism is dominant when the measurement frequency is high. Also under the condition of deep depletion caused by a fast gate sweep [curve-(d) in Fig. 71, the extra electron-holes pairs can supply carriers for maintaining equilibrium and curve-(d) will collapse to curve-(c). 4.3.6 Accumulation- and Inversion-Layer Thickness For an MIS capacitor, the maximum capacitance is equal to E~ld which implies that charges on both sides of the electrodes cling to the two interfaces of the insulator. While such an assumption is valid on the metal-insulator interface, detailed examination on the insulator-semiconductor interface reveals that it can lead to considerable error, especially for thin oxides. This is due to charges on the semiconductor side, either accumulation or strong-inversion charges, have a distribution as a hnction of distance from the interface. Effectively this would reduce the maximum capacitance given by qld. For the sake of simplicity, we will discuss accumulation in the following section, but the result could also be applied to the strong-inversion case. Classical Model. The charge distribution is controlled by the Poisson equation. Using Boltzmann statistics, (for accumulation typ is negative), the Poisson equation becomes The solution of the above equation is4= 234 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTORCAPACITORS The total accumulation layer thickness where y, approaches zero is equal to xLDI$? which is in the order of a few tens of nm. However, most of the carriers are confined very close to the surface. Figure 28 shows the potential and carrier distributions for two different biases. It shows that although the concentration peaks at the surface, it spreads out with an effective distance of the order of a few nm. This spread is also a function of the bias; higher bias forces the carriers to be closer to the interface. Quantum-Mechanical Model. In quantum mechanics, the wavefunction associated with the carriers is near zero at the insulator-semiconductor interface because of the high barrier of the insulator. As a consequence, the carrier concentration peaks at some finite distance from the interface. This distance is approximately 10 A. Figure 29 shows the results of the quantum-mechanical calculation. Macroscopically, this effect can be interpreted as a degradation in oxide capacitance (or thicker oxide). Ten 8, of Si is equivalent to 3 8,of SiO,, taking into account the difference in dielectric constant. This amount adds to the oxide thickness and lowers the capacitance. Also shown in the figure is the classical calculation. The quantum effect is shown to cause more pronounced degradation than the classical model. Another factor that causes further reduction of the capacitance is the polysilicon gates widely used in commercial technologies. Even if the polysilicon is degenerately doped, the depletion-layer and accumulation-layer thicknesses are still finite. 4.3.7 Dielectric Breakdown One common concern for an MOS device is r e l i a b i l i t ~ .U~n~d,e~r ~a large bias, some current will conduct through the insulator, most commonly a tunneling current. These energetic carriers cause defects in the bulk of the dielectric film. When these defects reach a critical density level, catastrophic breakdown occurs. Microscopically, a per- 0 50 40 8 30 4 20 10 - 0.02 - 0.04 h - 0.06 5 9 - 0.08 - 0.10 - 0.04 - 0.08 > v -0.12 - 0.16 - 0.12 0.20 '0 1 2 3 4 5 6 7 8 910 x (nm) (a) (b) Fig. 28 Classical calculation of potential and carrier profiles, with a surface potential I+V- of (a) 4kT/q and (b) 6kTlq. 4.3 SILICON MOS CAPACITOR 235 0.9 - * - - _ - - - - - - - - - - -} Metal gate 0.7 - - - - - Classical model Quantum model 0'51 1.5 2 2.5 3 3.5 4 5 1 Oxide thickness (nm) Fig. 29 Quantum-mechanical calculation of capacitance reduction. Also shown are results from classical model and those including depletion effect from polysilicon gate. (After Ref. 43.) colation theory is used to explain breakdown (Fig. 30). On the passage of energetic carriers, defects are generated randomly. When defects are dense enough to form a continuous chain connecting the gate to the semiconductor, a conduction path is created and catastrophic breakdown occurs. A measure to quantify reliability is time to breakdown, tBDw, hich is the total stress time until breakdown occurs. An alternate quantity is called charge to breakdown qsD, which is the total charge (integrating the current) passed through the device within tBD. Obviously tBD and q B D are both function of applied bias. An example for tBDverses oxide field for different oxide thickness is shown in Fig. 3 1. The plots of qBD would show similar shapes and trend. A few key points can be noticed in this figure. First, tBDis a function of bias. Even for a small bias, eventually the oxide will break down, taking a very long time. Conversely, a large field can be sustained for a very short time without breaking down. To search for the breakdown I Breakdown Path Metal Dielectric Semiconductor Fig. 30 Percolation theory: breakdown occurs when random defects form a chain between the gate and the semiconductor. 236 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS 6 - 15 5- h J 4- 3 3- 3 2- 1- ‘0 - -1 4 I 5 1 I 67 I 8 I I, I 9 101112 3 Zi(MV/cm) Fig. 31 Time to breakdown tBDvs. oxide field, for different oxide thickness. (After Ref. 46.) field quickly, typically a voltage ramp is applied until a large current is detected. For a common measurement, the ramping rate is typically in the order of 1 V/s. The figure shows that for this time frame, the breakdown field is around 10 MV/cm. As the oxide thickness becomes thinner, the breakdown field increases, as indicated in Fig. 3 1. More-recent results, however, show that this breakdown field would drop for thicknesses below = 4 nm, due to an increase of tunneling current.44 REFERENCES 1. J. L. Moll, “Variable Capacitancewith Large Capacity Change,” WesconConv.Rec., Pt. 3, p. 32 (1959). 2. W. G. Pfann and C. G B. Garrett, “SemiconductorVaractor Using Space-ChargeLayers,” Proc. IRE, 47,2011 (1959). 3. D. R. Frankl, “Some Effects of Material Parameters on the Design of Surface SpaceCharge Varactors,”Solid-StateElectron., 2,71 (1961). 4. R. Lindner, “Semiconductor SurfaceVaractor,” Bell Syst. Tech.J., 41, 803 (1962). 5. J. R. Ligenza and W. G Spitzer, “The Mechanisms for Silicon Oxidation in Steam and Oxygen,”J. Phys. Chem.Solids, 14, 131 (1960). 6. D. Kahng and M. M. Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” IRE-AIEE Solid-state Device Res. Con$, Carnegie Inst. of Technology, Pittsburgh, PA, 1960. 7. L. M. Terman, “An Investigation of Surface States at a Silicon/SiliconDioxide Interface Employing Metal-Oxide-Silicon Diodes,” Solid-state Electron., 5,285 (1962). 8. K. Lehovec and A. Slobodskoy, “Field-Effect Capacitance Analysis of Surface States on Silicon,”Phys. Status Solidi, 3,447 (1963). 9. E. H. Nicollian and J. R. Brews, MOSPhysics and Technologv,Wiley, New York, 1982. REFERENCES 237 10. C. G. B. Garrett and W. H. Brattain, “Physical Theory of Semiconductor Surfaces,” Phys. Rev.,99,376 (1955). 11. S. R. Hofstein and G. Warfield, “Physical Limitation on the Frequency Response of a Semiconductor Surface Inversion Layer,” Solid-state Electron., 8,321 (1965). 12. A. S. Grove, B. E. Deal, E. H. Snow, and C. T. Sah, “Investigation of Thermally Oxidized Silicon Surfaces Using Metal-Oxide-Semiconductor Structures,” Solid-state Electron., 8, 145 (1965). 13. A. S. Grove, E. H. Snow, B. E. Deal, and C. T. Sah, “Simple Physical Model for the SpaceCharge Capacitance of Metal-Oxide-Semiconductor Structures,” J. Appl. Phys., 33, 2458 (1964). 14. J. R. Brews, “A Simplified High-Frequency MOS Capacitance Formula,” Solid-state Electron., 20, 607 (1977). 15. A. Goetzberger, “Ideal MOS Curves for Silicon,” Bell Syst. Tech.J., 45, 1097 (1966). 16. B. E. Deal, “Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Silicon,” ZEEE Trans. Electron Dev., ED-27, 606 (1980). 17. I. Tamm, “Uber eine mogliche Art der Elektronenbindung an Kristalloberflachen,” Phys. Z. Sowjetunion,1,733 (1933). 18. W. Shockley, “On the Surface States Associated with a Periodic Potential,” Phys. Rev.,56, 317 (1939). 19. W. Shockley and G. L. Pearson, “Modulation of Conductance of Thin Films of Semiconductors by Surface Charges,” Phys. Rev.,74,232 (1948). 20. F. G. Allen and G. W. Gobeli, “Work Function, Photoelectric Threshold and Surface States of Atomically Clean Silicon,”Phys. Rev.,127, 150 (1962). 2 1. E. H. Nicollian and A. Goetzberger, “MOS Conductance Technique for Measuring Surface State Parameters,” Appl. Phys. Lett., 7, 216 (1965). 22. C. N. Berglund, “Surface States at Steam-Grown Silicon-Silicon Dioxide Interface,” ZEEE Trans. Electron Dev., ED-13,701 (1966). 23. R. Castagne and A. Vapaille, “Description of the Si0,-Si Interface Properties by Means of Very Low Frequency MOS Capacitance Measurements,” Surface Sci., 28, 157 (1971). 24. E. H. Nicollian and A. Goetzberger, “The Si-SiO, Interface-Electrical Properties as Determined by the MIS Conductance Technique,” Bell Syst. Tech.J., 46, 1055 (1967). 25. M. H. White and J. R. Cricchi, “Characterization of Thin-Oxide MNOS Memory Transistors,” ZEEE Trans. Electron Dev.,ED-19, 1280 (1972). 26. B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, “Characteristics of the Surface-State Charge (Q,,) of Thermally Oxidized Silicon,” J. Electrochem. SOC.1, 14,266 (1967). 27. J. R. Ligenza, “Effect of Crystal Orientation on Oxidation Rates of Silicon in High Pressure Steam,”J. Phys. Chem., 65,2011 (1961). 28. E. H. Snow, A. S. Grove, B. E. Deal, and C. T. Sah, “Ion Transport Phenomena in Insulating Films,” J. Appl. Phys., 36, 1664 (1965). 29. B. E. Deal, E. H. Snow, and C. A. Mead, “Barrier Energies in Metal-Silicon DioxideSilicon Structures,” J. Phys. Chem.Solids, 27, 1873 (1966). 30. R. Williams, “Photoemission of Electrons from Silicon into Silicon Dioxide,” Phys. Rev., 140, A569 (1965). 31 . K. L. Jensen, “Electron Emission Theory and its Application: Fowler-Nordheim Equation and Beyond,” J. Vac.Sci. Technol.B, 21, 1528 (2003). 238 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS 32. J. Frenkel, “On the Theory of Electric Breakdown of Dielectrics and Electronic Semiconductors,” Tech. Phys. USSR,5,685 (1938); “On Pre-Breakdown Phenomena in Insulators and Electronic Semiconductors,” Phys. Rev.,54,647 (1938). 33. Y. Takahashi and K. Ohnishi, “Estimation of Insulation Layer Conductance in MNOS Structure,” IEEE Trans. Electron Dev., ED-40,2006 (1993). 34. J. J. O’Dwyer, The Theory of Electrical Conduction and Breakdown in Solid Dielectrics, Clarendon, Oxford, 1973. 35. S. M. Sze, “Current Transport and Maximum Dielectric Strength of Silicon Nitride Films:” J. Appl. Phys., 38,2951 (1967). 36. W. C. Johnson, “Study of Electronic Transport and Breakdown in Thin Insulating Films,” Tech. Rep. No.7, Princeton University, 1979. 37. M. Av-Ron, M. Shatzkes, T. H. DiStefano, and I. B. Cadoff, “The Nature of Electron Tun- neling in SiO,,” in s.T. Pantelider, Ed., ThePhysics of SiO, and Its Interfaces, Pergamon, New York, 1978, p. 46. 38. A. Rusu and C. Bulucea, “Deep-Depletion Breakdown Voltage of SiO,/Si MOS Capaci- tors,” IEEE Trans. Electron Dev., ED-26, 201 (1979). 39. E. H. Nicollian, A. Goetzberger, and C. N. Berglund, “Avalanche Injection Currents and Charging Phenomena in Thermal SiO,,” Appl. Phys. Left.,15, 174 (1969). 40. D. R. Collins and C. T. Sah, “Effects of X-Ray Irradiation on the Characteristics of MOS Structures,” Appl. Phys. Lett., 8, 124 (1966). 41. E. H. Snow, A. S. Grove, and D. J. Fitzgerald, “Effect of Ionization Radiation on Oxidized Silicon Surfaces and Planar Devices,” Proc. IEEE, 55, 1168 (1967). 42. J. Colinge and C. A. Colinge, Physics of Semiconductor Devices, Kluwer, Boston, 2002. 43. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H. C. Wann, S. J. Wind, and H. Wong, “CMOS Scaling into the Nanometer Regime” Proc. IEEE, 85,486 (1997). 44. J. S. Suehle, “Ultrathin Gate Oxide Reliability: Physical Models, Statistics, and Characterization,” IEEE Trans. Electron Dev., ED-49, 958 (2002). 45. J. H. Stathis, “Physical and Predictive Models of Ultrathin Oxide Reliability in CMOS Devices and Circuits,” IEEE Trans. Device Matel: Reliab., 1,43 (2001). 46. J. S. Suehle and P. Chaparala, “Low Electric Field Breakdown of Thin SiO, Films Under Static and Dynamic Stress,” IEEE Trans. Electron Dev., ED-44, 801 (1997). PROBLEMS 1. For an ideal Si-SiO, MOS capacitor with d = 10 nm, NA = 5 ~ 1 0~’ m~ - f~in,d the applied voltage and the electric fields at the Si0,-Si interface required (a) to make the silicon surface intrinsic, and (b) to bring about a strong inversion. 2. Plot the variation of the space charge density lQ,l as a function of the surface potential IV, for an n-type silicon with No = 1OI6~ m a-t 3~00 K. Refer to Fig. 5 (p. 203). On the plot, mark the value of 2 vBa,nd the magnitude of Q, at the onset of strong inversion. 3. Derive the differential capacitance of the semiconductor depletion layer at the flat-band condition. (Eq. 23). PROBLEMS 239 4. Derive an expression for the approximated segment of an ideal MOS C-V curve in the depletion case (i.e., 0 5 V < VTin Fig. 7, p. 206). (Hint: The expression is either where y= 2$/qN,~,dz and Vis the applied voltage on the metal plate.) 5. Find the charge per unit area in the inversion region for an ideal MOS capacitor with NA= 1016~ m -d~=, 10 nm, and V, = 1.77 V. 6. For a metal-SO,-Si capacitor having NA= 10l6~ m an- d~d = 8 nm, calculate the minimum capacitance on the C-V curve under high-frequency condition. 7. An ideal Si MOS capacitor has an oxide of 5 nm and a doping of NA= lo1' ~ m - F~in.d the width of the inversion region, when the surface potential is 10% larger than the potential difference between the Fermi level and the intrinsic Fermi level. 8. Plot the number of electrons per unit area in the inversion region (NI) of a silicon MOS capacitor versus surface electric field ( E J . The substrate doping is lo1' ~ m - U~s.e log-log plot covering NI from lo9to lo1)cm-2 and Es from lo5to lo6 V/cm. Also write down the value ofN, for FZs= 2 . 5 ~ 1 V0 /~cm. 9. An ideal silicon MOS (MO-p-x-p+)capacitor has an oxide thickness of 100 nm and a special doping profile ofp-Ir-p+ where the top player is 10l6~ m a-nd~1.5 pm thick and the Ir-layer is 3 pm thick. Find the breakdown voltage of the structure under pulse condition. 10. Plot an ideal C-Vcurve for a Si-SiO, MOS capacitor at 300 K with NA= 5 ~ 1 0~' m~ - d~=, 3 nm (specify C,, CminC,, and VT).If the metal work function is 4.5 eV, qx = 4.05 eV, 7 Qf/q 10" ern-,, Q,/q = 1Olocm-2, Q,Jq = 5 ~ 1 0c'm~-2, and Q , = 0, plot the corre- sponding C-V curve (specify VFB and the new VT). 11. From the high-field portion in Fig. 25 (p. 230), evaluate the dielectric constant of the material. 12. Assume that the oxide trapped charge Q,, in an oxide layer is a charge sheet with an area density of 5x10" cm-, located at y = 5 nm from the metal-oxide interface. The thickness of the oxide layer is 10 nm. Find the change in the flat-band voltage due to Q,,. 13. Derive Eqs. 39 and 40. Find the maximum value of G/w 14. Two MOS capacitors, both have 15 nm gate oxide. One has an n+-polysilicon gate and p-type substrate, another has a p+-polysilicon gate and n-type substrate. If the threshold voltage of these two capacitors are V , ,= I VTpl = 0.5 V, and Qf=Q, = Q,, = Q, = 0, find the substrate dopings NAand No. 15. (a) Calculate the change in flat-band voltage corresponding to a uniform positive charge distribution in the oxide. The total density of ions is 1012cm-, and the oxide thickness is 0.2 pm. (b) Calculate the change in V, for the same total density of ions and same oxide thickness as in (a) except that the charge has a triangular distribution which is high near the metal and zero near the silicon. 240 CHAPTER 4. METAL-INSULATOR-SEMICONDUCTOR CAPACITORS 16. The C-Vcurve of a Si MOS capacitor is shown in the right figure. The shift is due entirely to the fixed oxide charges at the Si0,-Si interface. It has an nt-poly gate. Find the number of fixed oxide charges. 1x lo-’ F/cm2 17. Based on the plot for weak inversion region on p. 222 (Fig. 18),find the resistance associated with the interface traps. 18. An MOS capacitor has an oxide of 10 nm and a substrate doping of N, = 10l6c m 3 . The capacitor has a positive gate bias of 2 V and a surface potential of 0.91 V. When the capacitor is illuminated, an additional charge sheet of 10l2 electrons/cm2 is formed at the Si0,-Si interface. Calculate the percentage change of the high-frequency capacitance, i.e., C(under illumination) - , C(no illumination) Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. TRANSISTORS + Chapter 5 Bipolar Transistors + Chapter6 MOSFETs + Chapter 7 JFETs, MESFETs, and MODFETs Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. Bipolar Transistors 5.1 INTRODUCTION 5.2 STATIC CHARACTERISTICS 5.3 MICROWAVE CHARACTERISTICS 5.4 RELATED DEVICE STRUCTURES 5.5 HETEROJUNCTION BIPOLAR TRANSISTOR 5.1 INTRODUCTION A transistor, derived from transfer resistor, is a three-terminal device whose resistance between two terminals is controlled by the third. The bipolar transistor, one of the most-important semiconductor devices, was invented by a research team at Bell Laboratories in 1947. It has had an unprecedented impact on the electronic industry in general and on solid-state research in particular. Prior to 1947 semiconductors were only used as thermistors, photodiodes, and rectifiers, all two-terminal devices. In 1948 Bardeen and Brattain made the announcement of new experimental observation on the point-contact transistor.' In the following year Shockley's classic paper on junction diodes and transistors was published.* The theory of minority-carrier injection of p-n junctions forms the basis of the junction transistor. The first junction bipolar transistor was demonstrated in 1951.3 Since then the transistor theory has been extended to include high-frequency, high-power, and switching behaviors. Many breakthroughs have been made in transistor technology, particularly in the areas of crystal growth, epitaxy, diffusion, ion implantation, lithography, dry etch, surface passivation, planarization, and multilevel metalli~ationT.~hese breakthroughs have helped increase the power and frequency capabilities as well as the reliability of transistors. The historical development of the bipolar transistor has been detailed in Refs. 5 and 6. In addition, application of semiconductor physics, transistor theory, and transistor technology has broadened our knowledge and improved other semiconductor devices as well. 243 244 CHAPTER 5. BIPOLAR TRANSISTORS Table 1 Operation Modes ofa Bipolar Transistor Operation mode Emitter-base bias Collector-base bias Normal, Active Saturation cutoff Inverse Forward Forward Reverse Reverse Reverse Forward Reverse Forward The bipolar transistor is now a key element, for example, in some high-speed computers, in vehicles and satellites, and in modem communication and power systems. Many books have been written on bipolar transistor physics, design, and application. Among them are more-recent texts listed as Refs. 7 to 10. 5.2 STATIC CHARACTERISTICS 5.2.1 Basic Current-VoltageRelationship In this section we consider the basic dc characteristics of a bipolar transistor. Figure 1 shows the symbols and nomenclatures for n-p-n andp-n-p transistors. The arrow indicates the direction of current flow under normal operating condition, that is, forwardbiased emitter junction and reverse-biased collector junction. Other biasing conditions are summarized in Table 1. A bipolar transistor can be connected in three circuit configurations, depending on which lead is common to the input and output circuits. Figure 2 shows the common-base, common-emitter, and common-collector configurations for an n-p-n transistor. The current and voltage conventions are again given for normal operations. All signs and polarities should be inverted for a p-n-p transistor. In the following discussion we consider n-p-n transistors; the results are appli- Base Emitter Collector Base Emitter Collector (a) (b) Fig. 1 Symbols and nomenclatures of (a) n-p-n transistors and (b)p-n-p transistors. 5.2 STATIC CHARACTERISTICS 245 (a) (b) (c) Fig. 2 Three biasing configurations of n-p-n transistors in normal mode: (a) common-base, (b) common-emitter, and (c) common-collector. cable to p-n-p transistors with an appropriate change of polarities and physical parameters. Figure 3a is a schematic of an n-p-n transistor connected in the common-base configuration and biased in normal mode. Figure 3b shows a schematic doping profile for the transistor with regions of uniform impurity density. It is seen here that a typical design calls for higher doping in the emitter compared to the base, and that the collector has the lowest doping level. Figure 3c shows the corresponding band diagram under normal operating conditions. Figures 3a and b also indicate all current components biased under normal mode. These currents are explained below: ZnE: Electron diffusion current injected at emitter-base junction. ZnC: Electron diffusion current reaching the collector. IT,: (= ZnE - Znc) Loss of electron current recombining in the base. ZpE: Hole diffusion current at emitter-base junction. ZrE: Recombination current at emitter-base junction. Zco: Reverse current at collector-base junction. The basic operation of a bipolar transistor can be explained qualitatively, considering first only the major current components. When the emitter-basejunction is forward biased, the p-n junction current consists of electron and hole currents. Electrons are injected into the base, diffuse through the base and eventually collected by the collector (Fig. 3c). The base, beingp-type, presents a barrier to electrons and does not collect electrons. The hole diffusion current, on the other hand, originated from the base, manifests itself as the base current and does not affect the collector. The ratio of the collector current I, to the base current Z, is, thus, the electron to hole dif- fusion components of the base-emitter junction. However, if the injection ratio of electrons to holes is large, such as the case of an n+-p emitter-base junction by virtue of the difference in doping level, a current gain ZdZ, > 1 is realized. The static characteristics can be readily derived from thep-n junction theory discussed in Chapter 2, with proper boundary conditions. To illustrate the hndamental properties of a transistor, we assume that the current-voltage relationship of the 246 CHAPTER 5. BIPOLAR TRANSISTORS Emitter Base n+ P Collector n -Nj (c) E, Fig. 3 An n-p-n transistor biased in the normal operating conditions. (a) Connection and biases in common-base configuration. (b) Doping profiles and critical dimensions with abrupt impurity distributions.(c) Energy-banddiagram. Current components are shown in (a) and (c). Note that in (c), flow of electrons is negative current because of negative charge. emitter and collector junctions is given by the ideal diode equation? that is, the effects due to surface recombination-generation, series resistance, and high-level injection are neglected. Some of these effects will be considered later. We present the analysis in the two most-important modes-active and saturation, where the emitter-base junction is forward biased. As shown in Fig. 3b, all the potential drops occur across the junction depletion regions. In the neutral base region, from x = 0 to x = W,the injected minority-carriers distribution (electrons) is governed by the continuity equation: The general solution for the above equation is: n,(x> = npo+ C,exp(') + c,exp(') 5.2 STATIC CHARACTERISTICS 247 G, where C, and C, are constants and L, = is the electron diffusion length in the base. C, and C, are dependent on the boundary conditions of np(0) and np(W),and are given by The boundary conditions at the two edges of the neutral base region are related to the junction biases: n,(O) = n,,exp (- qi'3 With these boundary conditions, the electron distribution is known, as well as its difhsion current. The electron currents at the emitter edge InEand the collector edge I,, are given by I InE = A Eq Dnddnx x = o - AEq D'np o c o t h ( 3 { [exp(q+) - I]-sech(3[exp(%) - l]}, (7) Ln - AEqLDn nnpocosech(3{[expr$$) - 11-coth(3[expr*) I])- (*) where A, is the cross-sectional area of the emitter-base junction. These electron currents are valid for both the normal mode and saturation mode. In the normal mode, w> V,, < 0, and np( = 0, the electron currents at the two boundaries are given by I n E = AEqLDnnnpoc o t h ( 3 exp($$), (9) I,, = AEqLDnnnpocosech(f) e x p ( 2 ) . The ratio of Zn,lInE is called the base transport factor ap The difference of InEand Inc contributes to part of the base current. It can be seen that for W<< L,, Z,, is very close to InC In the limit of small W, 248 CHAPTER 5. BIPOLAR TRANSISTORS expr*) - AEqD ‘BE AEqDnn? - InEx I,, = W exp(WF NB ) and a, x 1. Equation 11 can be reduced to a simpler form InEx I,, 2AEDnQB x w2 where QB is the injected excess charge in the base, W QB = 91: [n,(x)-n,,ld~ On the other extreme, if W-+ co or WIL,>> 1, the electron current at the collectorI,, is zero and there is no communication between the emitter and the collector. The transistor action is thus lost. To improve the base transport factor, the uniform doping in the base layer is usually replaced by a distribution as shown in Fig. 4.” A transistor with such base doping distribution is called a drift transistor, since a built-in electric field enhances the electron transport in the base by drift action. The base density NB and the hole density in the base are related to the Fermi level by = N B ( x )= n,exp (“i;?)- (14) Since the Fermi level EF is flat in the neutral base, we obtain the built-in field The electron current now includes a drift component and the total current becomes .. - Emitter Base Collector Fig. 4 Typical doping profile of a Si bipolar transistor, with an impurity gradient in the base, and a heavily doped region under the collector. 5.2 STATIC CHARACTERISTICS Substituting Eq. 15 into Eq. 16 yields The steady-state solution to Eq. 17 with the boundary condition n,(W = 0 is The electron concentration at x = 0 is given by Using the relationship NB(0)npo(O=) nf ,the electron current is given by Jo The integral is the total impurity dose per area inside the neutral base, and is called the Gummel number Nb .12 For a typical silicon bipolar transistor, the Gummel number is about 1012to 1013 cm-2. It is interesting to compare Eq. 20 to Eq. 11. One notices that for the injected electron current InE, what matters is the total base dose or the Gummel number. The actual doping distribution does not affect ZnE, and its main function is to create a built-in field to increase the electron current I,, at the collector side and to improve ap The hole diffusion current injected from the base into the emitter is the main component of the base current. The equations governing the hole distribution and current are similar to that in a regular p-n junction. Assuming that WE 0.995; and the current gain is given almost entirely by the emitter efficiency. Under the condition a, N 1 Therefore, for a given emitter doping NE,the static common-emitter current gain h, is inversely proportional to the Gummel number Nb . For transistors with implanted base, the base ion dose is directly proportional to Nb ;and as the dose decreases, hFE increases.15 The current gain h, generally varies with collector current. A representative plot is shown in Fig. 6, which is obtained from Fig. 5 and using Eq. 32. At very low collector current, the contribution of the recombination current in the emitter depletion region and the surface leakage current may be large compared with the useful d i f i sion current of minority carriers across the base, so that the efficiency is low. In this regime, the current gain hFE increases with the collector current as follows: By minimizing the bulk and surface traps, hFE can be improved at low-current levels.16As the base current reaches the ideal regime, h, increases to a high plateau. For still higher collector current, the injected minority-carrier density in the base approaches the majority-carrier density there (the high-level injection condition), and the injected carriers effectively increase the base doping, which, in turn, causes the 1" 10-10 10-9 10-8 10-7 10-6 10-5 lo4 10-3 1, (A) Fig. 6 Current gain versus collector current for the transistor data in Fig. 5. 254 CHAPTER 5. BIPOLAR TRANSISTORS emitter efficiency to decrease. The detailed analysis can be obtained by solving the continuity equation and current equations with both difision and drift components. The decrease of current gain with increasing I , is referred to as the Webster effect.” As shown in Fig. 6, at high-level injection h , varies as I,-’: This high-current condition will be discussed in more detail later. Another important parameter, when the input is a voltage source as opposed to a current source, is the transconductance g,, defined as dIddVB,. From Eq. 10,since I , is exponential with VBE,the transconductance is given by g =- dIC = (&)I, ~VBE The g, is thus proportional to I,, and this is a unique characteristic of the bipolar transistor. At high I,, the large transconductance is one of its main features. The large g, on the other hand demands a low parasitic emitter resistance, since the extrinsic transconductance g,, is related to the intrinsic value g,, by It will be seen that in designing the structure, the emitter resistance should be minimized. 5.2.3 Output Characteristics In Section 5.2.2 we saw that the currents in the three terminals of a transistor are mostly diffusion currents which are related by the minority-carrier distribution in the base region. For a transistor with high emitter efficiency, we can ignore the recombination current, and the expressions for the dc emitter and collector currents reduce to terms proportional to the minority-carrier gradients (dn,ldx) at x = 0 and x = W, respectively. We can, thus, summarize the fundamental relationships of a transistor as follows: 1. The applied voltages control the boundary densities through the term exp(q VlkT). 2. The emitter and collector currents are given by the minority (electron) density gradients at the junction boundaries, that is, x = 0 and x = W. 3. The base current is the difference between the emitter and collector currents (Eq. 29). Figure 7 shows the electron distribution in the base region of an n-p-n transistor for various applied voltages. The dc characteristics can be interpreted by means of these diagrams. Figure 8 shows a representative set of output characteristics for common-base and common-emitter configurations. For the common-base configuration (Fig. 8a), the V,, = variable (+) 5.2 STATIC CHARACTERISTICS 255 V,, = fixed (+) VBc= variable (-) (a) VBE= fixed (+) V,, = variable (+) I Ic=0 Open - J 0 W 0 W (c) Fig. 7 Electron-density profile in the neutral base of an n-p-n transistor for various applied voltages. (a) (b) Normal mode. (c) Saturation mode. (d) Different emittedbase bias affects base-collectorreverse current Zc0. (f) indicates forward-biasedjunction. (-) indicates reversebiased junction. (After Ref. 18.) collector current is practically equal to the emitter current (ao= 1). The collector current remains virtually independent of VcE,even down to zero volts where the excess electrons are still extracted by the collector, as indicated by the electron profile shown in Fig. 7b. For negative V,, (positive VEc),the base-collector junction is forward biased, and the transistor is in saturation mode. The electron concentration at x = Wincreases significantly (Fig. 7c), causing the diffusion current to drop rapidly to zero. This is reflected in the negative term of Eq. 8 involving VEp The collector saturation current I,, is measured with the emitter open-circuit. This current is considerably smaller than the ordinary reverse current of a p-n junction because the presence of the emitter junction with a zero electron gradient at x = 0 (corresponding to zero emitter current) reduces the electron gradient at x = W (Fig. 7d). The current,,,Z is therefore smaller than when the emitter junction is short-circuited (VEB= 0) whose value is approximated by Eq. 25. As V,, increases to the value VEcEot,he collector current starts to increase rapidly (Fig. 8a). Generally, this increase is due to the avalanche breakdown of the collectorbase junction, and the breakdown voltage is similar to that considered in Chapter 2 forp-n junctions. For a very narrow base width or a base with relatively low doping, 256 CHAPTER 5. BIPOLAR TRANSISTORS VCB (v) “BCBO “A VCE (V) VBCEO (a) (b) Fig. 8 Output characteristics of an n-p-n transistor in (a) common-base configuration, and (b) common-emitter configuration. Breakdown voltage and Early voltage VA(currents are extrapolated to the x-axis) are indicated. the breakdown may also be caused by the punch-through effect, that is, the neutral base width is reduced to zero at a sufficient V,, and the collector depletion region is in direct contact with the emitter depletion region. At this point, the collector is effectively short-circuited to the emitter, and a large current can flow. We now consider the output characteristics of the common-emitter configuration. Figure 8b shows the output ( I , versus VcE)characteristics of a typical n-p-n transistor. Note that the current gain (AFE) is considerable and the current increases with Vcp The saturation current ZcEo, which is the collector current with zero base current (open base), is much larger than IcBo, as given by Eq. 35. Physically, the open base floats to a slightly positive potential, thereby increasing the electron concentration and its slope, as shown in Fig. 7d. As VcEincreases, the neutral base width Wdecreases, causing an increase in Po (Fig. 7b). The lack of saturation in the common-emitter output characteristic is due to the large increase of Powith VcEand is referred to as the Early effect.19The voltage V, at which the extrapolated output curves meet is called the Early voltage. For a transistor with base width WEmuch larger than the depletion region in the base, the Early voltage is given by20 ‘U %-q N B,. 0s (43) for a uniform base. For small base width, a small Early voltage is equivalent to low output resistance (dZJdVcE)which is undesirable for circuit applications. If the base width is small enough, punch-through would occur with a behavior similar to ava- 5.2 STATIC CHARACTERISTICS 257 lanche breakdown. On the other hand, since a low Gummel number is preferable to give high current gain (Eq. 38), a balance has to be struck between Early voltage and current gain. For small collector-emitter voltages, the collector current falls rapidly to zero. The voltage VCEis divided between the two junctions to give the emitter a smaller forward bias, and the collector a larger reverse bias. To maintain a constant base current, the potential across the emitter junction must remain essentially constant. Thus, when VCEis reduced below a certain value (= 1 V for the silicon transistor), the collector junction will reach zero bias. With further reduction in V,, the collector is actually forward-biased and driven into saturation mode (Fig. 7c). The collector current falls rapidly because of the decrease of the electron gradient at x = K The breakdown voltage under the open-base condition can be obtained as follows. We start with the collector-base junction breakdown voltage, which is very close to V, (open emitter). Let M b e the multiplication factor at the collector junction and be approximated by where n is a constant that has a value between 2 and 6 for silicon. Since the base is open-circuited, we have I, = I , = I. The currents ICE0 and adEare multiplied by M when they flow across the collector junction (Fig. 9), giving M( aoz+ I,,,) = I (45) I B t' T I 'CEO I G 1 1 I ICBO I i 0 VBCEO t -V VBCBO ' Fig. 9 Breakdown voltage V, and saturation current ICE, for common-base open-emitter configuration, and corresponding qualities V, and ICE, for common-emitter open-base configuration. (After Ref. 2 1.) 258 CHAPTER 5. BIPOLAR TRANSISTORS or Current I will be infinite when q M = 1, limited only by external resistances. Also, for an open-base condition, VcE = VcB since VBE is forward bias and is small. From this condition aoM= 1 and Eq. 44, the breakdown voltage VB, for the commonemitter configuration is given by The value of ,V,, is thus much smaller than the junction breakdown voltage V.,, Qualitatively this is because of positive feedback from the bipolar gain. It is apparent now why the doping profile should be like that shown in Fig. 4. The high doping in the emitter is for injection efficiency. The base doping has a nonuniform profile to improve the transport factor. It also should be reasonably high for a high Early voltage. The collector has the lowest doping for high breakdown. 5.2.4 Nonideal Effects Emitter Bandgap Narrowing. In calculating the current gain in Eq. 38, there is another dominant factor besides the Gummel number-the emitter doping concentration NE. To improve h, the emitter should be much more heavily doped than the base, that is, NE >> NB.However, as the emitter doping becomes very high, we have to consider the bandgap-narrowing effect in addition to the Auger effect; both cause reduction of h., The bandgap narrowing in heavily doped silicon has been studied based on the broadening of both the conduction band and the valence band. Empirically the bandgap reduction AEgcan be expressed as22 AEg = 18.7 In - (7 xY0 17) meV , where N is larger than 7 ~ 1 0~' m~ -F~ig.ure 10 shows a collection of experimental data from various authors, which are in good agreement with Eq. 48. The intrinsic carrier density in the emitter is now where ni is the intrinsic carrier density without the bandgap-narrowing effect. The minority-carrier concentrations in the emitter becomes 5.2 STATIC CHARACTERISTICS 259 100 A’ Doping concentration ( ~ r n - ~ ) Fig. 10 Experimental data and empirical fit for bandgap narrowing in silicon. (After Ref. 23.) It is seen here that the net effect is an increased minority-carrier concentration in the emitter. It is common then to account for this bandgap reduction by a reduced effective emitter doping In any case, the net result is an increased hole diffusion current from the base to the emitter, and the current gain is reduced according to (Eq. 38) $) h , oc 5 a exp(- AE . PnoE Kirk Effect. Under high-current condition, in modern bipolar transistors with a lightly doped epitaxial collector region, the net charge inside the collector is changed significantly. This is accompanied by the relocation of the high-field region, from the base-collector junction toward the collector n+-~ubstrate.T*~he effective base width therefore increases from W, to the extreme case of W, + W,. This high-field-reloca- tion phenomenon is referred to as the Kirk which increases the effective base Gummel number Nb and causes a reduction of h,. It is important to point out that under a high-injection condition where the currents are large enough to produce sub- stantial fields in the collector region, the classic concept of well-defined transition regions at emitter-base and base-collector junctions is no longer valid. One must solve the basic differential equations (current density, continuity, and Poisson equa- tions) numerically with boundary conditions applied only at the electric terminals. Figure 11 shows the computed results of the electric field distributions for a fixed V,, and various collector current densities. Note that as the current increases, the peak electric field moves toward the collector n+-substrate. 260 CHAPTER 5. BIPOLAR TRANSISTORS 2 -20 n Ih- 'E, - 8 Ill\ " .I1.o 0 5 10 15 Distance (pm) Fig. 11 Electric field distributions as a function of distance for various collector current densities, showing the Kirk effect. (After Ref. 24.) As indicated in Fig. 11, the current-induced base width WclBdepends on the collector doping concentration and the collector current density. At high current density, when the injected electron density is higher than the collector doping, the net charge density is changed to the extent that polarity is changed. As a result, the apparent junction is moved to inside the collector. This phenomena is indicated qualitatively in Fig. 12 For the first order, the injected electron density nc is related to the collector current density by Jc = qncv, p-base n-collector I n+ Fig. 12 Space-charge region showing base widening at high current (Kirk effect). (a) Low collector current. (b) High collector current, base width = W, + Wclp 5.2 STATIC CHARACTERISTICS 261 where it is assumed that at high field electrons are traveling with the saturation velocity v,. The net space-charge density becomes nc - N,, with a new space-charge region Ws,near the n+-substrate given by The current-induced base width is given by It is convenient to identify a critical collector current when this Kirk effect starts to set in, i.e., when WcIB= 0. Setting Eq. 54 to zero, this critical current density is given by Equation 54 can then be rewritten in the form As Jc becomes larger than JK,WclBincreases; and when Jc becomes much larger than JK, WcIBapproaches W,. Current Crowding. We had discussed the effect of emitter resistance on the transconductance. In order to minimize the emitter resistance, the emitter contact is usually made directly on top of the emitter. This forces the base contacts to be made on the sides, as shown in Fig. 13, and there is an internal base resistance under the emitter associated with this structure. At high current, this resistive voltage drop reduces the net V,, across the junction, and it is more severe toward the center of the emitter. As a result, the base current passing through the emitter area is not uniform, with a lower density toward the center. This current crowding puts some restriction on - Collector Fig. 13 Cross-section of a two-sided base contact, showing current crowding at high base current. 262 CHAPTER 5. BIPOLAR TRANSISTORS the design of the emitter strip width S. For a wide S, the center area carries little current. An effective width Sefwhich carries most of the current is estimated to be22 ssf, sinZcosZ S Z (57) where Z can be solved by ZtanZ = q-.zBRnS 8XkT R, is the base sheet resistance given by and Xis the size of emitter perpendicular to S such that the emitter area is SX.As the base current IBincreases, Z goes up and the ratio SefISis decreased. To calculate the base resistance analytically for the purpose of current crowding is difficult due to the distributed nature of the current flow. Besides, the junction I-V relationship in series has to be considered. We can only analyze the case with low current, i.e., without current crowding. It has been shown that the base resistance at high current for calculating current crowding is related to this value.22 We consider the common structure of a two-sided base contact. In the absence of current crowding, the base current for half of the structure drops linearly as a function of the lateral distance $) I B b ) = !2IB( 1- The equivalent base resistance is obtained by considering the total power of the system, JO Equations 60 and 61 yield the base resistance of This base resistance is also critical for microwave performance as discussed later. 5.3 MICROWAVE CHARACTERISTICS Bipolar transistors are attractive for high-speed applications. Not only they are capable of high-speed response, their large current drive, which is related to their high transconductance g,, is one of the main figures-of-merit for high-speed circuits. High current drive is particularly important for practical circuits where parasitic capaci- 5.3 MICROWAVE CHARACTERISTICS 263 tance, such as that due to metal runners, are more pronounced. In this section, the high-speed characteristics of bipolar transistors, both small-signal and large-signal, will be discussed. 5.3.1 Cutoff Frequency The cutoff frequencyf, is an important parameter for microwave transistors. It is defined as the frequency at which the common-emitter short-circuit current gain hfe (= dIJdIB)is unity.26This cutoff frequency can be derived for any transistor using the equivalent circuit of Fig. 14a. For any transistor having a transconductance g , and a total input capacitance C;, ,the small-signal output and input currents are given by ii, = vinmC;,. (64) (Note the dimensions we adopt for symbols: C' is total capacitance and C is capacitance per area.) By equating Eqs. 63 and 64, one obtains a general expression of In a bipolar transistor (Fig. 14), the capacitance components are represented by the sum of c;, = CLori- Cin i-C& i- CDEi- CDCi- CJ.,, (66) and these represent: Ciar: Parasitic capacitance. -B bE Fig. 14 Schematic circuits to analyze cutoff frequency. (a) A transistor having transconductance g , and total input capacitance C;, . (b) Representation of n-p-n bipolar transistor, and (c) its input capacitance components. 264 CHAPTER 5. BIPOLAR TRANSISTORS C;, : Diffusion capacitance due to electrons (into base). Cip : Diffusion capacitance due to holes (into emitter). CbE : Emitter-base depletion capacitance. Cbc : Collector-base depletion capacitance. Ci, : Space-charge capacitance in collector, due to injected electrons. The cutoff frequency can be rewritten as 1 -- 1 f T = 27TX(C’/g,) 2 r X z where z can be considered as the individual charging time or delay time associated with each capacitance C‘lg,. A few of these capacitance components, such as the depletion capacitances CbE and Cbc ,need little explanation since they are already covered in Chapter 2. We first discuss the diffusion capacitance due to electrons into the base. From Eq. 91 of Chapter 2, and using g, = qIc/kT, we obtain gm where 7 = 2 for a uniformly doped base. For a nonuniform base doping, such as the example shown in Fig. 4, this charging time can be reduced by the drift action. The factor 77 should become a larger number. If the built-in field 8 b j is a constant, this factor can be estimated by27 where go= 2Dnl,unW = 2kT/qW. For 8&/80 = 2, is about 7; thus, considerable reduction in this charging time can be achieved by a large built-in field. The shape of the base profile can be obtained in a practical transistor using a base implantation and/or diffusion processes. In particular, Gaussian and exponential profiles have been compared to a box profile, and the quantitative reduction in the base charging time are shown in Fig. 15. Similar diffusion capacitance is due to holes diffusing into the emitter. Again using Eq. 91 of Chapter 2, this charging time is given by = [AEq2WEPnoEexp(qV~~~kT) W - -NBWE W 2kT l~[AEqD,npoexp(qv B ~ / k T ) l- ~ N E D ,. (70) In a practical device, the emitter and base doping levels are quite high, and the depletion regions are within the transition region, similar to a linearly graded junction. Equation 70 can be reduced to Base resistance = 10W t k z - h - 5.3 MICROWAVE CHARACTERISTICS 265 Base width (nm) Fig. 15 Reduction of base charging time by Gaussian and exponential base profiles. (After Ref. 28.) where 6' has a value between two and five. As expected, this expression has the same form as that of Eq. 68. Finally, the space-charge capacitance C,, is due to the injected electrons into the collector depletion region. This capacitance is different from the conventional deple- tion capacitance ,C, . Conceptually, CDc is dQsJdVcEwhere the change of space charge is due to widening of the depletion width. On the other hand, C,, is dQs)dVEE where the change of space charge comes from the injected electrons, related directly to the collector current density J,, as given by Eq. 52. Figure 16 illustrates the spacecharge density with and without electron injection. Since the solution of the Poisson equation inside the space-charge region is related to the total potential VCEa,nd if this bias is fixed, we have29 N C W D , = 2 E vcE = ( N , - nc)(WD, -I-h w ~ , ) ~ , (72) 4 from which we obtain -n C = - wDC (73) NC wDC Space-charge density Q,, n-collector Fig. 16 Change of space-charge density and width in the collector due to injected electrons (dashed line). nc = X JC/PS. 266 CHAPTER 5. BIPOLAR TRANSISTORS Due to the change A WDathe injected charge density is no longer simply qncWDc,but has a reduced value of The charging time associated with C;, is thus The factor of two is counter-intuitive, especially when this charging time is often in literature referred to as transit time. An additional delay not related to Clgmcomes from an RcCbc time constant in the collector terminal, where R, is the total collector resistance. The overall cutoff frequencyf Tis then given by From this expression, the first group of delays are current dependent; they decrease with current. For high-frequency applications, a bipolar transistor should operate at high current for a highf p before other undesirable high-current effects start. It is also apparent that the transistor should have a very narrow base thickness, as well as a narrow collector depletion region. Figure 17a shows the experimental f T as a function of collector current. At low current densities,f T increases with J , as predicted by Eq. 76. In this regime the collector current is carried mainly by the drift component, so that where 8,is the built-in electric field in the collector epitaxial layer. As the current increases,f Treaches a maximum and then decreases rapidly around J,, where J1 is the current at which the largest uniform electric field gC= (f&,i + VcB)W/ , can exist, and &t is the total collector built-in potential.24Beyond this point, the current cannot be carried totally by the drift component throughout the collector epitaxial region. The current J , is given from Eq. 77 as This current value should be designed to be below that where the Kirk effect starts. It should be pointed out that as VcBincreases, the corresponding value of J , also increases. In Fig. 17b, a plot of 2 d f Tversus lIJ, can separate the current dependent parts of Eq. 76, given by the slope, from the current independent parts, given by the extrapolation to zero in llJc 5.3 MICROWAVE CHARACTERISTICS 267 J, (lo4A/cm2) 10 5 3 2 1.5 1 v Collector current density J , (A/cm-2) 1/J, (10-5 cm2/A) (4 (b) Fig. 17 (a) Cutoff frequency as a function of collector current density. (b) Plot of llf,vs. l/Jc to separate the current dependence. (Afler Ref. 30.) For high-speed devices, the term WDJ2usis a significant factor. A small collector depletion width calls for higher collector doping, and the transistor will suffer from lower breakdown voltage. There is, thus, a trade-off between f r and breakdown voltage V., In fact, it has been suggested that for a particular material system, the fr.VBcEoproduct remains a constant. For a silicon collector, which includes SiGebase HBT (heterojunction bipolar transistor), the theoretical product is around 400 GHz-V, assuming all other delays are negligible compared to wDc/2us.31 5.3.2 Small-Signal Characterization To characterize the microwave performance, scattering parameters (s parameters) are extensively used because they are easier to measure at high frequencies with matched loads, than other kinds of parameter^.^^ Figure 18 shows a general two-port network with incident waves (a,, a2)and reflected waves (bl, b2)to be used in s-parameter definitions. The linear equations describing the two-port network are where the s parameters sI1s,22,s12a,nd s21are: cjzrbzL network Fig. 18 Two-port network showing incident waves (ai, a2) and reflected waves (bi, b2)used in s-parameter definitions. 268 CHAPTER 5. BIPOLAR TRANSISTORS b ls11 - - = Input reflection coefficient with output terminated by a matched - a~ 9 = 0 load (Z, = Z, sets a2 = 0. Z, is the characteristic impedance). %I = Output reflection coefficient with input terminated by a matched s22 = a2 01= 0 load (Z, = Z, sets al = 0). 41 s21 = = Forward-transmission gain with output terminated in a matched a~ ~ z = O load. b ls12 - - = Reverse-transmission gain with input terminated in a matched - a2 = 0 load. We shall define several figures-of-merit for microwave transistors using the s-parameters. The power gain Gp is the ratio of power delivered to the load over the maximum available power to the network; where r L =z- Z,L-+ zZo,’ N G ~22-Ds;I. (83) In Eq. 80 “Re” means the real part, and the asterisk (*) denotes the complex conjugate. The stability factor K indicates if a transistor will oscillate upon applying a combination of passive load and source impedance with no external feedback. This factor is given by = %(K+J=). (85) Gptll,, ISl2 5.3 MICROWAVE CHARACTERISTICS 269 The unilateral gain is the forward power gain in a feedback amplifier with its reverse power gain set to zero by adjusting a lossless reciprocal feedback network around the transistor. Unilateral gain is independent of header reactances and common-lead configuration. This gain is defined as We shall now combine the above two-port analysis with device internal parameters. Figure 19 shows the simplified equivalent circuits for a high-frequency bipolar transistor. The device parameters have been defined previously. Ck and Cb are the total emitter and collector capacitance. The small-signal common-base current gain a is defined as a = h f b = d-I, = V&, it steers current away from Q2, thus low- ering the current through it and raising the output ECL is unique in that it pro- vides two complementary outputs. TTL. The transistor-transistor logic (TTL, Fig. 27c) has multiple input gates per transistor, so it is more suitable for dense circuits. Transistor Q1 has multiple emitter inputs and it is an AND logic. Transistor 4 2 is an emitter follower for the lower Vouj, and an inverter for the upper V,,,. The two-transistor logic is designed for speed: when Q2 is turned off from saturation, the base charge is drained quickly as collector current through Q1. IIL. Since its introduction in 1972, the integrated-injection logic (IIL or 12L,also called merged-transistor logic MTL) has been extensively used in IC logic and memory designs. It uses complementary bipolar transistors, i.e., both types of n-p-n 282 CHAPTER 5. BIPOLAR TRANSISTORS andp-n-p (Fig. 27d). Its structure incorporates a lateralp-n-p transistor, and itsp-collector is merged with the base of the vertical n-p-n transistor. The logic unit does not need a resistor. It is closely packed and does not need isolation between transistors. So, the attractive features of 12Linclude ease of layout and high packing density for large complex circuits. The p-n-p lateral transistor Q1 acts as a current source that injects current into the base of Q2. Transistor 4 2 has multiple collector output contacts. BiCMOS. In a BiCMOS technology, both bipolar transistors and complementary (n-channel and p-channel) MOSFETs are available for optimum design. Since MOSFET and bipolar transistor each has its own advantages, there are numerous logic configurations available for different optimization. 5.5 HETEROJUNCTION BIPOLAR TRANSISTOR The basic principle of current gain in the bipolar transistor originates from the injection efficiency of the emitter-base junction, i.e., for an n-p-n transistor, the ratio of electron current to hole current In/Ip.A heterojunction bipolar transistor (HBT) incorporates a heterojunction as the emitter-base junction, with a larger bandgap in the emitter.4749The injection efficiency is much improved (see Section 2.7.1), leading to a much larger current gain. However, in practical circuits, an extra-large gain is not as attractive as improving other device parameters. So long as the gain is sufficient, the extra gain can be traded off for other improvements. In a homojunction, as shown in Eq. 38, the gain is largely determined by the ratio of the emitter doping to the base doping. In a heterojunction transistor, this ratio can be relaxed, in fact to the extent that the base doping can be higher than the emitter doping, yet still maintaining a reasonable gain. Typical doping profile for an HBT is shown in Fig. 28 where the base doping is higher than the emitter doping. The high base doping brings many advantages. First the lower base resistance improvesf,,, and current crowding. Higher base Emitter Base l0”r P Collector n 10151 Depth Fig. 28 Comparison of doping profiles of homojunction and heterojunction bipolar transistors. 5.5 HETEROJUNCTION BIPOLAR TRANSISTOR 283 doping also improves the Early voltage and reduces high-current effects. The lower emitter doping also brings the advantages of reduced bandgap narrowing as well as reduced CBEFurthermore, larger emitter bandgap will provide a larger built-in potential, as will be shown later. Also, in practice, HBTs are mostly fabricated on 111-V compound semiconductors which are capable of providing a semi-insulating substrate. This reduces the parasitic capacitance and greatly improves the speed performance. We will next derive the gain of an HBT whose energy band diagram of the emitter-base heterojunction is shown in Fig. 29. From Eqs. 11 and 22, the electron and hole current densities are given by where n$ and n,'E correspond to the intrinsic concentrations in the base and emitter respectively. Remember that in ap-n junction, each current component is determined by properties of the receiving side only. That is, for electrons injected from the n-emitter, the parameters in Eq. 13 are those of the base. The same holds true for the hole current that is determined by the properties of the emitter. With this understanding in mind, a large emitter bandgap decreases the hole current, at the same time without affecting the electron current. The current gain is, thus, given by Vacuum level Vacuum level ElEF EgE n-Emitter EC EF n-Emitter A&] EC p-Base E" (a) @) Fig. 29 Energy-band diagrams of heterojunction between a larger bandgap n-type emitter and a smaller bandgap p-type base. (a) Isolated and (b) after junction formation. In (b), the extra barrier for electrons in an abrupt heterojunction is eliminated in a graded heterojunction (dashed lines). 284 CHAPTER 5. BIPOLAR TRANSISTORS provided all the other parameters such as doping concentrations are the same. It is also important to note that the extra barrier created by AE, has to be eliminated, otherwise other mechanisms which limit the current conduction will appear. This barrier can be eliminated if the composition is varied slowly within the depletion region, resulting in what is called a graded HBT. The energy-band diagrams for abrupt and graded HBTs are shown in Figs. 30a and b. Note that according to Eq. 115, the gain improvement is determined by the total change in bandgap AEg,independent of the partition between AE, and AE, Also included in Fig. 30 for comparison are the double-heterojunction bipolar transistor (DHBT) where a second heterojunction is incorporated into the base-collectionjunction, and the graded-base bipolar transistor where the bandgap varies graduallywithin the neutral base. These two structureswill be discussed in more details later. The built-in potential of the emitter-base junction can be calculated from Fig. 29 to be where N , and NcE are the valence-band effective density-of-states in the base and conduction-bandeffective density-of-statesin the emitter,respectively. Also the rela- tionship of AE, = q k B-xE)has been applied. Other equations for heterojunctioncan be found in Section 2.7.1. Emitter Base Collector Emitter Base Collector Emitter Base Collector Emitter Base Collector EC (c) (d) Fig. 30 Energy-band diagrams for (a) abrupt HBT, (b) graded HBT, (c) graded DHBT, and (d) graded-base bipolar transistor. 5.5 HETEROJUNCTION BIPOLAR TRANSISTOR 285 A typical HBT structure is shown in Fig. 3la, There are three material systems that are most common for HBT applications. These are chosen based on matching their crystal lattice as well as their energy gaps (Fig. 32 in Chapter 1). These materials are (1) GaAs-based (emitterbase = InAlAdInGaAs), (2) InP-based (emitterbase = InP/InGaAs, and (3) Si-based (emitterbase = Si/SiGe). All 111-V HBTs are grown using MBE or MOCVD for precise composition and thickness control. Si-based HBT such as the Si-SiGe heterostructure is still not mature as most of the published results are actually of the graded-base type bipolar transistor instead (see Section 5.5.2 below).50 For circuit applications, the collector capacitance is critical. A structure to minimize this capacitance is a collector-up design, shown in Fig. 31b. Since the emitterbase junction is now enlarged, one disadvantage of this design is a lower current gain. Another processing difficulty is having to etch a thicker collector compared to the emitter before stopping at the thin base layer for base contact. 5.5.1 Double-Heterojunction Bipolar Transistor One drawback of an HBT is the offset voltage in the common-emitter configuration (Fig. 32a). This comes about because in the low V,, region, i.e., saturation region, both the base-emitter and base-collector junctions are under forward bias. Since in an HBT, the base-emitter current is suppressed, the base-collector current contributes to a negative collector terminal current. This is worsened by the fact that the base-collectorjunction area is much larger than the base-emitterjunction area (Fig. 31a). This drawback can be eliminated by incorporating another heterojunction as the base-collector junction, resulting in the double-heterojunction bipolar transistor (DHBT, Fig. ~OC)a,s opposed to single HBT (SHBT). The comparison of this offset voltage from InAIAsAnGaAs DHBT and SHBT is demonstrated in Fig. 32b. Other advantages of the DHBT include higher breakdown voltage from a larger collector bandgap. Similar to a high emitter bandgap, the high-bandgap collector also reduces the injection of holes from the base to the collector in the saturation mode, thereby Semi-insulating GaAs substrate (a) (b) Fig. 31 (a) Typical structure of an HBT. (b) A special structure using collector-up to minimize the collector capacitance. 286 CHAPTER 5. BIPOLAR TRANSISTORS ,2 ft Offset 'CE (4 Fig. 32 (a) VCEoffset existing in an HBT. (b) Comparison of V,, offset between InAlAs/InGaAs single HBT and double HBT. (After Ref. 5 1.) reducing the minority charge storage. In a DHBT, the collector doping can be higher, reducing high-current effects such as Kirk effect and quasi-saturation. 5.5.2 Graded-Base Bipolar Transistor In a graded-base bipolar transistor, the composition is changed gradually within the neutral base region rather than in the junctions. The function of this design is completely different from that of the HBT. Here the composition grading creates a quasifield to assist the drift of electrons (Fig. 30d). This purpose is similar to that of the nonuniform base doping profile, discussed in Section 5.3.1, except the quasi-field created here is more effective. While the total potential variation created by the doping gradient is in the order of 2kTlq (:. 50 mV), the potential from bandgap engineering can vary by more than 100 mV. The advantages of the graded-base bipolar transistor are: higher electron current and current gain, reduced base charging time for higher fT,and increased Early voltage. The following analysis uses a SiGe graded-base bipolar transistor as an example, with Si near the emitter side and Ge, whose bandgap is smaller by AEg,near the collector side. It is further assumed that the grading is linear with distance. The net result and an useful equation is expressing the intrinsic concentration as a function of distance, n?(Si, -xGe,) AE = n ? ( S i ) e x pk(TAWL,) . From Eq. 20, the electron saturation current density J,, (voltage-independent part) is given by20 5.5 HETEROJUNCTION BIPOLAR TRANSISTOR 287 1 -- AE,/kT qDNnBn:W(SBi)[ 1 - exp(-AEJkT) ' (118) Since the hole current remains unchanged, the current and current gain are improved compared to a silicon base by a factor of Jno(SiGe) - Po(SiGe) - AE,IkT Jno(Si) Po(Si) 1 - exp(-AE,/kZ')' (119) The graded-base bipolar transistor has a higherf, from a reduced base charging time, which is given by20 Compared to a uniform base, Si or Ge, the usual term of W2,/20,, is reduced by the factor in parenthesis. Finally the Early voltage can be calculated to be Note that the improvement is by the factor in the parenthesis and is quite significant. 5.5.3 Hot-Electron Transistor A hot electron is an electron with energy more than a few kT above the Fermi energy, thus the electron is not in thermal equilibrium with the lattice. With extra kinetic energy, electrons will travel with a higher velocity giving rise to higher speed and larger current. The group velocity for hot electrons as a function of energy above the conduction band are shown in Fig 33a, which indicates that these velocities can be a few times higher that those in equilibrium. A hot-electron transistor based on an abrupt HBT is shown Fig. 33b. Many other forms of hot-electron transistors have been proposed, and are represented by the energy-band diagrams in Fig. 34. The main difference in these transistors lies in the method used to launch hot electrons into the base.53These injection mechanisms can be tunneling through a high-bandgap material,54 thermionic emission over a Schottky emitter in a metal-base t r a n ~ i s t o ro,r~o~ver a triangular barrier in the planar-doped-barrier t r a n ~ i s t o rU. ~p~to now, the speed advantage of a hot-electron transistor has not been demonstrated. It has been used as a spectrometer to study 288 CHAPTER 5. BIPOLAR TRANSISTORS h ‘0 2 v I 9 _--- Equilibrium velocities Emitter EC Base EFn EV Collector EF” ‘0 0.1 0.2 0.3 0.4 0.5 Electron energy E (eV) (4 (b) Fig. 33 (a) Electron group velocities as a function of energy above the conduction band. (After Ref. 52.) (b) Energy-band diagram of a hot-electron transistor based on an abrupt HBT. Emitter Base Collector Emitter Base Collector Emitter Base Collector (8) (b) (c) Fig. 34 Other forms of hot-electron transistors. Hot electrons from (a) tunneling through a barrier, (b) thermionic emission over a Schottky barrier, and (c) over a planar-doped barrier. properties of hot carriers as a function of their energy, which can be filtered or selectedby varying the barrier at the collector-baseheterojunction. REFERENCES 1. J. Bardeen and W. H. Brattain, “The Transistor,A Semiconductor Triode,” Phys. Rev.,74, 230 (1948). 2. W. Shockley, “The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors,” Bell Syst. Tech.J., 28,435 (1949). 3. W. Shockley, M. Sparks, and G. K. Teal, “p-n Junction Transistors,” Phys. Rev., 83, 151 (1951). REFERENCES 289 4. G. S. May and S. M. Sze, Fundamentals of Semiconductor Fabrication, Wiley, Hoboken, New Jersey, 2004. 5. W. Shockley, “The Path to the Conception of the Junction Transistor,” IEEE Trans. Electron Dev., ED-23, 597 (1976). 6. M. Riordan and L. Hoddeson, Ciystal Fire, Norton, New York, 1998. 7. D. J. Roulston, Bipolar Semiconductor Devices, McGraw-Hill, New York, 1990. 8. M. Reisch, High-Frequency Bipolar Transistors, Springer Verlag, New York, 2003. 9. W. Liu, Handbook of 111-VHeterojunction Bipolar Transistors, Wiley, New York, 1998. 10. M. F. Chang, Ed., Current Trends in Heterojunction Bipolar Transistors, World Scientific, Singapore, 1996. 11. J. L. Moll and I. M. Ross, “The Dependence of Transistor Parameters on the Distribution of Base Layer Resistivity,” Proc. IRE, 44,72 (1956). 12. H. K. Gummel, “Measurement of the Number of Impurities in the Base Layer of a Tran- sistor,” Proc. IRE, 49, 834 (1961). 13. S. K. Ghandi, Semiconductor Power Devices, Wiley, New York, 1977. 14. P. G. A. Jespers, “Measurements for Bipolar Devices,” in F. Van de Wiele, W. L. Engl, and P. G. Jespers, Eds., Process and Device Modelingfor Integrated Circuit Design, Noordhoff, Leyden, 1977. 15. R. S. Payne, R. J. Scavuzzo, K. H. Olson, J. M. Nacci, and R. A. Moline, “Fully IonImplanted Bipolar Transistors,” IEEE Trans. Electron Dev., ED-21,273 (1974). 16. W. M. Werner, “The Influence of Fixed Interface Charges on Current Gain Fallout of Planar n-p-n Transistors,” J. Electrochem. Soc., 123, 540 (1976). 17. W. M. Webster, “On the Variation of Junction-Transistor Current Amplification Factor with Emitter Current,” Proc. IRE, 42,914 (1954). 18. M. J. Morant, Introduction to Semiconductor Devices, Addison-Wesley, Reading, Mass., 1964. 19. J. M. Early, “Effects of Space-Charge Layer Widening in Junction Transistors,” Proc. IRE, 40, 1401 (1952). 20. Y. Taur and T. H. Ning, Fundamentals of Modern VLSIDevices, Cambridge University Press, Cambridge, 1998. 2 1. W. W. Gartner, Transistors, Principle, Design, and Application, D. Van Nostrand, Princeton, New Jersey, 1960. 22. J. R. Hauser, “The Effects of Distributed Base Potential on Emitter-Current Injection Density and Effective Base Resistance for Strip Transistor Geometries,” IEEE Trans. Electron Dev., ED-l1,238 (1964). 23. J. del Alamo, S. Swirhun, and R. M. Swanson, “Simultaneous Measurement of Hole Lifetime, Hole Mobility and Bandgap Narrowing in Heavily Doped n-Type Silicon,” Tech. Dig. IEEE IEDM, 290 (1985). 24. H. C. Poon, H. K. Gummel, and D. L. Scharfetter, “High Injection in Epitaxial Transistors,” IEEE Trans. Electron Dev., ED-16,455 (1969). vT) 25. C. T. Kirk, “A Theory of Transistor Cutoff Frequency Fall-Off at High Current Den- sity,” IEEE Trans. Electron Dev., ED-9, 164 (1962). 26. R. L. Pritchard, J. B. Angell, R. B. Adler, J. M. Early, and W. M. Webster, “Transistor Internal Parameters for Small-Signal Representation,” Proc. IRE, 49, 725 (1961). 290 CHAPTER 5. BIPOLAR TRANSISTORS 27. A. N. Daw, R. N. Mitra, and N. K. D. Choudhury, “Cutoff Frequency of a Drift Transistor,” Solid-StateElectron., 10,359 (1967). 28. K. Suzuki, “Optimized Base Doping Profile for Minimum Base Transit Time,” IEEE Trans. Electron Dev., ED-38,2128 (1991). 29. R. G. Meyer and R. S. Muller, “Charge-Control Analysis of the Collector-Base SpaceCharge-Region Contribution to Bipolar-Transistor Time Constant rn” IEEE Trans. Electron Dev., ED-34,450 (1987). 30. W. D. van Noort, L. K. Nanver, and J. W. Slotboom, “Arsenic-Spike Epilayer Technology Applied to Bipolar Transistors,” IEEE Trans. Electron Dex, ED-48,2500 (2001). 31. K. K. Ng, M. R. Frei, and C. A. King, “Reevaluation of the fTBVcE0limit on Si Bipolar Transistors,” IEEE Trans. Electron Dev., ED-45, 1854 (1998). 32. K. Kurokawa, “Power Waves and the Scattering Matrix,” IEEE Trans. Microwave Theoly Tech.,MTT-13, 194 (1965). 33. S. M. Sze and H. K. Gummel, “Appraisal of Semiconductor-Metal-Semiconductor Transistors,” Solid-state Electron., 9,751 (1966). 34. E. G. Nielson, “Behavior of Noise Figure in Junction Transistors,” Proc. IRE, 45, 957 (1957). 35. J. L. Moll, “Large-Signal Transient Response of Junction Transistors,” Proc. IRE,42, 1773 (1954). 36. I. R. C. Post, P. Ashburn, and G. R. Wolstenholme, “Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment,” IEEE Trans. Electron Dev., ED-39, 1717 (1992). 37. A. C. M. Wang and S. Kakihana, “Leakage and h, Degradation in Microwave Bipolar Transistors,” IEEE Trans. Electron Dev., ED-21, 667 (1 974). 38. L. C. Parrillo, R. S. Payne, T. F. Seidel, M. Robinson, G. W. Reutlinger, D. E. Post, and R. L. Field, “The Reduction of Emitter-Collector Shorts in a High-speed, All Implanted, Bipolar Technology,” Tech. Dig. IEEE IEDM, 348 (1979). 39. E. 0.Johnson, “Physical Limitations on Frequency and Power Parameters of Transistors,” IEEE Int. Conv.Rec., Pt. 5, p. 27 (1965). 40. J. G. Kassakian, M. F. Schlecht, and G C. Verghese, Principles of Power Electronics, Addison-Wesley, New York, 1991. 41. C. G. Thornton and C. D. Simmons, “A New High Current Mode of Transistor Operation,” IRE Trans. Electron Devices, ED-5,6 (1958). 42. H. A. Schafft, “Second-Breakdown-A Comprehensive Review,” Proc. IEEE, 55, 1272 (1967). 43. N. Klein, “Electrical Breakdown in Solids,” in L. Marton, Ed., Advances in Electronics and Electron Physics, Academic, New York, 1968. 44. L. Dunn and K. I. Nuttall, “An Investigation of the Voltage Sustained by Epitaxial Bipolar Transistors in Current Mode Second Breakdown,” Int. J. Electron., 45,353 (1978). 45. H. Melchior and M. J. 0. Strutt, “Secondary Breakdown in Transistors,” Proc. IEEE, 52, 439 (1964). 46. F. F. Oettinger, D. L. Blackburn, and S. Rubin, “Thermal Characterization of Power Transistors,” IEEE Trans. Electron Dev., ED-23, 831 (1976). 47. W. Shockley, “Circuit Element Utilizing Semiconductive Material,” U.S. Patent 2,569,347 (1951). PROBLEMS 291 48. H. Kroemer, “Theory of a Wide-Gap Emitter for Transistors,” Proc. IRE, 45, 1535 (1957). 49. H. Kroemer, “Heterostructure Bipolar Transistors and Integrated Circuits,” Proc. IEEE, 70, 13 (1982). 50. E. Kasper and D. J. Paul, Silicon Quantum Integrated Circuits, Springer Verlag, Heidel- berg, 2005. 5 1. T. Won, S. Iyer, S. Agarwala, and H. Morkog, “Collector Offset Voltage of Heterojunction Bipolar Transistors Grown by Molecular Beam Epitaxy,” IEEE Electron Dev. Lett., EDL10,274 (1989). 52. A. F. J. Levi, “Nonequilibrium Electron Transport in Heterojunction Bipolar Transistors,” in B. Jalali and S. J. Pearton, Eds., InP HBTs: Growth, Processing, a n d Applications, Artech House, Boston, 1995. 53. J. L. Moll, “Comparison of Hot Electrons and Related Amplifiers,” IEEE Trans. Electron Dev., ED-10,299 (1 963). 54. C. A. Mead, “Tunnel-Emission Amplifiers,” Proc. IRE, 48,359 (1960). 55. J. R. Hayes and A. F. J. Levi, “Dynamics of extreme nonequilibrium electron transport in GaAs,” IEEEJ. Quan. Electron., QE-22, 1744 (1986). PROBLEMS 1. A siliconp+-n-p transistor has impurity concentrations of 5 x lo’*, 1016,and 1015~ m in- th~e emitter, base, and collector, respectively. The base width is 1.O pm, and the device cross sectional area is 3 mm2. If VEB= 0.5 V, and VcB= 5 V (reverse), (a) calculate the neutral base width, (b) the minority carrier concentration at the emitter-base junction, and (c) the minority carrier charge in the neutral base region. 2. A silicon n+-p-nbipolar transistor has abrupt dopings of 3x1Ol6,and 5 ~ 1 0~’ ~m in- ~ the emitter, base, and collector, respectively. Find the upper limit of the base-collector voltage at which the emitter bias can no longer control the collector current (due to punchthrough or avalanche breakdown). Assume the base width (between metallurgical junctions) is 0.5 pm. 3. For a general base impurity doping N(x) in an n-p-n transistor, the electron current density is given by Eq. 17. With the boundary condition of np= 0 at x = W ,prove Eq. 18. 4. A silicon n+-p-rr-p+diode has a p-layer of 3 pm and rr-layer of 9 pm. The biasing voltage must be high enough to cause avalanche breakdown in thep-region and velocity saturation in the rr-region. Find the minimum required biasing voltage. 5. The collector current across a reverse-biased depletion region of the collector-base junction is a drift current. (a) Assuming that the carriers are at their saturation velocity, show that the concentration of the injected carriers across the base-collector depletion region is constant. (b) Sketch the electric field distribution within the collector-base junction depletion region for increasing current densities, assuming both the base and the collector are uniformly doped to NBand N,, respectively, and NB >> N,. The collector-base voltage is at a fixed value of VcB. (c) At what current density does the electric field approach a constant value? 292 CHAPTER 5. BIPOLAR TRANSISTORS 6.Derive the expression for the extrinsic transconductance(Eq. 42) degraded by an emitter resistance R,. 7. If we want to design a bipolar transistor with 25 GHz cutoff frequencyf,, what will the neutral base be? Assume Dpis 10 cm2/sand neglect the emitter and collector delays. 8. Consider a Si,,GeJSi HBT with x = 10% in the base region (and 0% in emitter and collector region). The bandgap of the base region is 9.8% smaller than that of Si. If the base current is due to emitter injection efficiency only, what is the expected change in the common-emitter current gain between 0' and 100°C? 9. A heterojunction bipolar transistor (HBT) has a bandgap of 1.62 eV for the emitter and 1.42 eV for the base. A homojunction bipolar transistor (BJT) has a bandgap of 1.42 eV for both the emitter and the base; it has an emitter doping of 10l8~ m a-nd~a base doping of 1015~ m - I~f t.he HBT has the same emitter doping and the same common-emittercurrent gain Poas the BJT, what is the lower bound of the base doping of the HBT (in atoms/cm3)? (Hint:Assume that the base-transport factor is very close to unity, and Pois mainly deter- mined by the emitter efficiency. Also assume that the difksion constant, the densities of states in the conduction band and in the valence band are the same for the emitter and base, independentof doping. In addition,the neutralbase width Wis much less than the base diffusion length and is equal to or less than the emitter difision length.) 10. Determine the velocity of electrons injected into the base region from an abrupt emitterbase heterojunction of InP/InGaAs. Assume a parabolic band for the InGaAs. Determine the angular distribution of the electron velocity within the base near the emitter. (Hint: AE, = 0.25 eV for InP/InGaAsheterojunction,and m' for InP is about 0.045mo.) Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. MOSFETs 6.1 INTRODUCTION 6.2 BASIC DEVICE CHARACTERISTICS 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS 6.5 MOSFET STRUCTURES 6.6 CIRCUIT APPLICATIONS 6.7 NONVOLATILE MEMORY DEVICES 6.8 SINGLE-ELECTRON TRANSISTOR 6.1 INTRODUCTION The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most-important device for forefront high-density integrated circuits such as microprocessors and semiconductor memories. It is also becoming an important power device. The principle of the surface field-effect transistor was first proposed in the early 1930s by Lilienfeld'-3 and HeiL4It was subsequently studied by Shockley and Pearson5 in the late 1940s. In 1960, Ligenza and Spitzer produced the first device-quality Si-SiO, MOS system using thermal oxidation.6 The basic MOSFET structure using this Si-SiO, system was proposed by Atalla.7 Subsequently the first MOSFET was reported by Kahng and Atalla in 1960.8The detailed early historical development of the MOSFET can be found in Refs. 9-10. The basic device characteristics have been initially studied by Ihantola and Moll," Sah,12and Hofstein and Heiman.I3 The tech- nology, application, and device physics have been reviewed by many book^.'^-'^ Figure 1 shows the reduction of the gate-length dimension in production ICs since 1970. This dimension has been decreasing at a steady pace and will continue to shrink in the foreseeable future. The reduction of device dimensions is driven by the require- 293 294 CHAPTER 6. MOSFETs Year Fig. 1 Minimum gate dimension in commercial integrated circuit as a function of the year of production. ment for both performance and density. The number of components per integratedcircuit chip has grown exponentially. The rate of growth is expected to slow down because of increasing technological challenge and fabrication cost. However, a complexity of 1 billion or more devices per chip had been available around 2000 using 0.1-pm technology. In this chapter we first consider the basic device characteristics of the so-called long-channel MOSFET; that is, the longitudinal field along the channel is not large enough to cause velocity saturation. In this regime, the carrier velocity is mobilitylimited, or under constant mobility. As the channel length becomes shorter, one has to consider short-channel effects due to two-dimensional potential and high-field transport such as velocity saturation and ballistic transport. Many device structures have been proposed to improve MOSFET performance. Some representative advanced structures as well as the nonvolatile semiconductor memory, basically a MOSFET with a multilayer gate structure, will be discussed. 6.1.1 Field-Effect Transistors: Family Tree The MOSFET is the main member of the family of field-effect transistors. A distinction between the field-effect transistor (FET) and the potential-effect transistor (PET) is warranted here. A transistor in general is a three-terminal device where the channel resistance between two of the contacts is controlled by the third (MOSFETs have the fourth terminal as contact to the substrate). The difference between the FET and the PET is the way the control is coupled to the channel. As shown in Fig. 2, in an FET, the channel is controlled capacitively by an electric field (hence the name fieldeffect),and in a PET, the channel’s potential is accessed directly (hence the name potentideffect).Conventionally in FETs, the channel carriers flow from the source FET Contact (source) Control 7‘(gate) Capacitor 1 Contact Channel . ” ’ *,, (drain) 6.1 INTRODUCTION 295 PET Contact I (emitter) Control (base) P I Channel Contact (collector) Fig. 2 Distinction between (a) field-effect transistor (FET) and (b) potential-effect transistor (PET). to the drain, and the control terminal is called the gate, whereas in PETs, these corresponding terminals are called the emitter, collector, and base, respectively. The bipolar transistor is a good representative of the PETs. A family tree of field-effect transistors is shown in Fig. 3 The three first-level main members are IGFET (insulated-gate FET), JFET (junction FET), and MESFET (metal-semiconductor FET). They are distinguished by the way the gate capacitor is formed. In an IGFET, the gate capacitor is an insulator. In a JFET or a MESFET, the capacitor is formed by the depletion layer of a p-n junction or a Schottky barrier, respectively. In the branch of IGFET, we further divide it into MOSFET/MISFET (metal-insulator-semiconductor FET) and HFET (heterojunction FET). In the MOSFET, specifically the insulator is a grown oxide layer, whereas in the MISFET the insulator is a deposited dielectric. In the HFET branch, the gate material is a highbandgap semiconductor layer grown as a heterojunction which acts as an insulator. Although MOSFETs have been made with various semiconductors such as Ge,I8 Si, and GaAs,I9and use various oxides and insulators such as SiO,, Si,N,, and A1,0,, the most-important system is the SO,-Si combination. Hence most of the results in this chapter are obtained from the Si0,-Si system. The other members, JFETs, MESFETs, and HFETs, will be considered in the following chapter. IGFET (insulator gate) (p-njunction gate) MOSFETNISFET (high-E,) MODFET (doped high-E,) HIGFET (undoped high-E,) MESFET (Schottky gate) Fig. 3 Family tree of field-effect transistors (FETs). 296 CHAPTER 6. MOSFETs Field-effect transistors offer many attractive features for applications in analog switching, high-input-impedance amplifiers, and microwave amplifiers, in addition to digital integrated circuits. The FETs have considerably higher input impedance than bipolar transistors, which allows the input of a FET to be more readily matched to the standard microwave system. The FET has a negative temperature coefficient at high current levels; that is, the current decreases as temperature increases. This characteristic leads to a more uniform temperature distribution over the device area and prevents the FET from thermal runaway or second breakdown, that can occur in the bipolar transistor. The device is thermally stable, even when the active area is large or when many devices are connected in parallel. Because there is no forward-biasedp-n junctions, FETs do not suffer from minority-carrier storage and, consequently, have higher large-signal switching speeds. In addition, the devices are basically square-law or linear devices; intermodulation and cross-modulation products are smaller than those of bipolar transistors. 6.1.2 Versions of Field-Effect Transistors TheFe are many ways to categorize the versions of FETs. First, according to the type of channel carriers, we have n-channel andp-channel devices. n-channels are formed by electrons and are more conductive with more positive gate bias, whilep-channels are formed by holes and are more conductive with more negative gate bias. Furthermore, it is important to describe the state of the transistor with zero gate bias. FETs are called enhancement-mode, or normally-off, if at zero gate bias the channel conductance is very low and we must apply a gate voltage to form a conductive channel. The counterpart is called depletion-mode, or normally-on, when the channel is conductive with zero gate bias and we must apply a gate voltage to turn the transistor off. These four combinations with their I- Vcharacteristics are summarized in Fig. 4. It is important also to point out the nature of the channel in more details. According to Fig. 5, a channel can be formed by a surface inversion layer or a bulk buried layer. The surface inversion channel is a two-dimensional charge sheet of thickness in the order of 5 nm. The buried channel is much thicker, comparable to the depletion width since when the transistor is turned off, the channel is totally consumed by the surface depletion layer. In the FET family, MESFETs and JFETs are always buried-channel devices, while MODFETs are surface-channel devices. MOSFETs and MISFETs can have both kinds of channels in parallel, but in practice, they are mostly surface-channel devices. These two kinds of channels offer advantages of their own. Buried channels are based on bulk conduction and, thus, are free of surface effects such as scattering and surface defects, resulting in better carrier mobility. On the other hand, the physical distance between the gate and the channel is larger and also dependent on gate bias, leading to a lower and variable transconductance. Note that for depletion-mode devices, it is common to use buried channels, but theoretically, one can achieve the same goal by choosing a gate material with a proper work function to shift the threshold voltage to a desirable value. 6.2 BASIC DEVICE CHARACTERISTICS 297 n-channel Enhancement-mode (Normally-off) n-channel Depletion-mode (Normally-on) pE-nchancneeml ent-mode (Normally-off) LVG I D K 3 : ; zDFxli;4 0 - ID! 0 -vD-r4;ID T e ~ v G vG -G ' p-channel Depletion-mode (Normally-on) -ID Fig. 4 Versions of MOSFETs; their output and transfer characteristics. 6.2 BASIC DEVICE CHARACTERISTICS The basic structure of a MOSFET is illustrated in Fig. 6. Throughout this chapter we assume the channel carriers are electrons-an n-channel device. All discussion and equations will be applicable to the counterpart p-channel devices with appropriate substitution of parameters and the reversal of polarity of the applied voltages. A common MOSFET is a four-terminal device that consists of a p-type semiconductor substrate into which two n+-regions, the source and drain, are formed, usually by ion implantation. The SiO, gate dielectric is formed by thermal oxidation of Si for a highquality Si0,-Si interface. The metal contact on the insulator is called the gate; heavily Gate Gate Depletion layer / Chahnel Chdnnel (a) (b) Fig. 5 FET channels: (a) surface inversion channel and (b) buried channel. 298 CHAPTER 6. MOSFETs . V" 2 Metal contact I I/ p-Si I/ b V,, Substrate Bias Fig. 6 Schematic diagram of a MOSFET. doped polysilicon or a combination of silicide and polysilicon is more commonly used as the gate electrode. The basic device parameters are the channel length L, which is the distance between the two metallurgical n+-pjunctions; the channel width Z; the insulator thickness d; the junction depth rj; and the substrate doping NA.In a silicon integrated circuit, a MOSFET is surrounded by a thick oxide (called the field oxide to distinguish it from the gate oxide) or a trench filled with insulator to electrically isolate it from adjacent devices. The source contact will be used as the voltage reference throughout this chapter. When ground or a low voltage is applied to the gate, the main channel is shut off, and the source-to-drain electrodes correspond to two p-n junctions connected back to back. When a sufficiently large positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n+-regions,the source and the drain are then connected by a conducting surface n-channel through which a large current can flow. The conductance of this channel can be modulated by varying the gate voltage. The back-surface contact (or substrate contact) can be at the reference voltage or reverse biased; this substrate voltage will also affect the channel conductance. 6.2.1 Inversion Charge in Channel When a voltage is applied across the source-drain contacts, the MOS structure is in a nonequilibrium condition; that is, the minority-carrier (electron in the present case) quasi-Fermi level EF,, is lowered from the equilibrium Fermi level. To show more clearly the band bending across the device, Fig. 7a shows the MOSFET turned 90". The two-dimensional, flat-band, zero-bias (VG= V, = VBs= 0) equilibrium condition is shown in Fig. 7b. The equilibrium condition but under a gate bias that causes surface inversion is shown in Fig. 7c. The nonequilibrium condition with both drain and gate biases is shown in Fig. 7d, where we note the separation of the quasi-Fermi levels of electrons EF,, and holes EFp; the EFp remains at the bulk Fermi level while 6.2 BASIC DEVICE CHARACTERISTICS 299 P Fig. 7 Two-dimensional band diagram of an n-channel MOSFET. (a) Device configuration. (b) Flat-band zero-bias equilibrium condition. (c) Equilibrium condition (V, = 0) under a positive gate bias. (d) Nonequilibrium condition under both gate and drain biases. (After Ref. 20.) EF,, is lowered toward the drain contact. Figure 7d shows that the gate voltage required for inversion at the drain is larger than the equilibrium case in which ty,(inv) = 2 yB;#in other words, the inversion-layercharge at the drain end is lowered by the drain bias. This is because the applied drain bias lowers the EFn, and an inversion # The common assumption of w, = 2 vBis for the onset of weak inversion. For strong inver- sion, w, can be larger by a few kT. l5 This can be understood from Fig. 5 of Chapter 4. 300 CHAPTER 6 . MOSFETs layer can be formed only when the surface potential meets the criteria of [EFn-Ei(0)]> q yB,where Ei(0)is the intrinsic Fermi level at x = 0. Figure 8 shows a comparison of the charge distribution and energy-band variation of an inverted p-region for the equilibrium case and the nonequilibrium case at the drain. For the equilibrium case, the surface depletion region reaches a maximum width W, at inversion. For the nonequilibrium case, the depletion-layer width is deeper than WDmand is a function of the drain bias V,. The surface potential w,b)at the drain at the onset of strong inversion is, to a good approximation, given by y,(inv) N VD+ 2 y B . (1) The characteristics of the surface space charge under the nonequilibrium condition are derived under two assumptions; (1) the majority-carrier quasi-Fermi level EFp is the same as that of the substrate and it does not vary with distance from the bulk to the surface (constant with x), and (2) the minority-carrier quasi-Fermi level EFnis lowered by the drain bias by an amount dependent on the y-position. The first assumption introduces little error when the surface is inverted, because majority carriers are then only a negligible part of the surface space charge. The second assumption is correct under the inversion condition, because minority carriers are an important part of the surface space-charge region when the surface is inverted. Based on these assumptions, the one-dimensional Poisson equation for the surface space-charge region at the drain end is given by -V Fig. 8 Comparison of charge distribution and energy-band variation of an inverted p-region in (a) equilibrium and (b) nonequilibrium at the drain end. (After Ref. 21.) where 6.2 BASIC DEVICE CHARACTERISTICS Conceptually the charge due to minority carriers within the inversion layer, is given by where xidenotes the point at which q vp(x) = EFn-E,(x) = q v,, and the fimction F is defined as (see Chapter 4) n JexP (-P vp)+ P v p - + exp (-PvD) [ exp ( Pvp)- P v pexp (PvD) - 1. (7) PPO For the practical doping ranges in silicon, the value ofx, is quite small, of the order of 3 to 30 nm. Equation 6 is the exact formulation, but can only be evaluated numerically. To get an analytical solution we follow the same approach as in Chapter 4 (Eq. 14). The surface electric field in the x-direction at the drain end is given by and the total semiconductor surface charge is then obtained from Gauss' law where the Debye length is The inversion charge per unit area Q,, after strong inversion is given by 302 CHAPTER 6. MOSFETs Qn 1 Qs - QB (11) where the depletion bulk charge is v~ Q, = - 4NAwD = -,&4N,Es( + 2 v/R). (12) From Eqs. 9, 11, and 12, the inversion charge Q, at the drain end can be simplified to This solution is still difficult to use because at strong inversion, Q, is very sensitive to the surface potential t,u, (see Fig. 5 in Chapter 4). Another shortcoming is that the relationship to the terminal bias, that is V,, is still missing. The charge-sheet model discussed in the following section is simpler and much more useful for deriving the I- Vcharacteristics of MOSFETs. Charge-Sheet Model. In the charge-sheet under strong-inversion condi- tions, the inversion layer is treated as a charge sheet with zero thickness (xi = 0). Con- sequently, this assumption implies that the potential drop across this charge sheet is also zero. These assumptions do introduce error but within an acceptable level. From Gauss’ law, the boundary conditions on both sides of the charge sheet are: Q,. ~ o x ~ o=x gscs- (14) In order to express Q,b) throughout the channel, the surface potential is generalized from Eq. 1 to v~~~)~Av~(Y)+~vBJ (15) where A rv, is the channel potential with respect to the source end; (see label in Fig. 7d) and is equal to V, at the drain end. Note that the electric fields can be expressed as: In Eq. 17, an ideal MOS system with zero work-function difference is assumed. Equation 18 is simply the maximum field at the edge of the depletion region. Combining Eqs. 14-1 8 and using Cox= EoJd we obtain lQnoi>l = [ V G - A ~ j o i ) - 2 ~ ~ l c o x - ~ 2 E ~ q N ~ [ A v / I ~ ) + 2 1 1 / B 1 ’(19) This final form will be used as the channel charge responsible for the current conduction. 6.2 BASIC DEVICE CHARACTERISTICS 303 6.2.2 Current-Voltage Characteristics We shall now derive the basic MOSFET characteristics under the following idealized conditions: (1) The gate structure corresponds to an ideal MOS capacitor as defined in Chapter 4; that is, there are no interface traps nor mobile oxide charge; ( 2 ) only drift current will be considered; (3) doping in the channel is uniform; (4) reverse leakage current is negligible; and (5) the transverse field (gXin the x-direction) in the channel is much larger than the longitudinal field (gJ,in the y-direction). This last condition corresponds to the so-called gradual-channel approximation. Note that in condition-( l ) ,the requirements of zero fixed oxide charge and work-function difference are removed, and their effects are included in a flat-band voltage VFBrequired by the gate to produce the flat-band condition. Consequently V, is replaced by V, - VFB for the inversion charge, giving leflb)l = LVG- v F B - A w i b ) - 2 ~ B l c ~ ~ - ~ 2 E ~ q N ~ [ Af ~2 (; I( /~B) ] . ( 2 0 ) Under such idealized conditions, the channel current at any y-position is given by z~b=>z l Q f l ( Y ) l u b > (21) where u(y) is the average carrier velocity. Since the current has to be continuous and constant throughout the channel, integration of Eq. 21 from 0 to L gives zl ID = Ien(y>lvb)&. (22) The carrier velocity u(y) is a function of the y-position since the longitudinal field gy(y)is a variable. Because of this, the relationship between u(y) and gV(yi)s impor- tant to evaluate Eq. 22. We first consider the case where gV(y)is low such that the mobility is constant. For shorter channel lengths, higher field causes velocity saturation and ultimately ballistic transport. These interesting effects will be discussed later. Constant Mobility. Under this assumption, substitutions of u = FZp and Eq. 20 into Eq. 22 gives Equation 23 predicts that for a given V, the drain current first increases linearly with drain voltage (the linear region), then gradually levels off (the nonlinear region), and finally approaching a saturated value (the saturation region). The basic output characteristics of an idealized MOSFET are shown in Fig. 9. The dashed line on the right indicates the locus of the drain voltage (V,,,,) at which the current reaches a maximum value Z,,. For small V,, the I , is linear with V,. Inbetween the two dashed lines, we designate this as the nonlinear region. 304 CHAPTER 6. MOSFETs Nonlinear region i / Saturation region V D (V) Fig. 9 Idealized drain characteristics (Z, vs. V,) of a MOSFET. The dashed lines separate the linear, nonlinear, and saturation regions. A qualitative discussion of the device operation can be helpful, with the aid of Fig. 10. Let us consider that a positive voltage is applied to the gate, large enough to cause an inversion at the semiconductor surface. If a small drain voltage is applied, a current will flow from the source to the drain through the conducting channel. The channel acts as a resistor, and the drain current I, is proportional to the drain voltage V,. This is the linear region. As the drain voltage increases, the current deviates from the linear relationship since the charge near the drain end is reduced by the channel potential A ~r/(,Eq. 20). It eventually reaches a point at which the inversion charge at the drain end Q,(L) is reduced to nearly zero. This location of Q, = 0 is called the pinch-off point, Fig. lob. [In reality Q,(L) is not zero for current continuity,but small because of its high field and high carrier velocity.] Beyond this drain bias, the drain current remains essentially the same, because for V, > VDsat,the pinch-off point starts to move toward the source, but the voltage at this pinch-off point remains the same ( VDSat)T. hus, the number of carriers arriving at the pinch-off point from the source, and hence the current, remains essentially the same, apart from a decrease in L to the value L' (Fig. 1Oc). This change of effective channel length will increase the drain current only when the shortened amount is a substantial fraction of the channel length. This will be considered in the section of short-channel effects. We shall now consider the current equations for the three cases of linear, nonlinear, and saturationregions. In the linear region, with a small V, using power series around VDand taking only the initial terms, Eq. 23 reduces to 6.2 BASIC DEVICE CHARACTERISTICS 305 VAS Fig. 10 MOSFET operated (a) in the linear region (low V,), (b) at onset of saturation, and (c) beyond saturation (effective channel length is reduced). where Vris the threshold voltage, one of the most-important parameters, given by The threshold voltage will be discussed in more details in the next section. Careful examination of Eq. 23 indicates that the current initially increases but then goes through a peak and then drops with V,. This drop of current is not physical, 306 CHAPTER 6. MOSFETs but it corresponds to the condition that the charge in the inversion layer at the drain end Q,(L) becomes zero. This pinch-off point occurs because the relative voltage between the gate and the semiconductor is reduced. The drain voltage and the drain current at this point are designated as V,, and losaretsp,ectively. Beyond the pinchoff point the current remains independent of V, and we have the saturation region. The value of VDsaits obtained from Eq. 20 under the condition Q,(L) = 0. The solution yields where K = ,/~,qNA/COAx.lternatively, the same solution can be obtained by setting dIddVD= 0. The saturation current ID,,t can be obtained by substituting Eq. 26 into Eq. 23: z ‘Dsat = =L&‘ox( ‘G - ‘ T I 2 . (27) Mis a function of doping concentration and oxide thickness It has a value slightly larger than unity and it approaches unity with thinner oxide and lower doping. Furthermore, a more convenient form for V,, can be expressed as The transconductance in the saturation region where Eq. 27 applies is given by It can be seen here that in this saturation region, for constant mobility, the current is a square-law function according to Eq. 27, indicated by the increasing current steps between gate bias shown in Fig. 9. Finally, the nonlinear region inbetween these two extreme cases can be described well by Equation 20 for the inversion charge is an exact expression. An approximation of the following form, taking advantage of the definition of threshold voltage, can be made: lQ,b>=l Cox[VG- v T - M A y / i b > l . (32) Substitution of this into Eq. 22 yields a general expression which is the same as Eq. 31 for the whole three regions of operation. As seen, the only slight departure from the previous results lies in the linear region. This simplified charge expression 6.2 BASIC DEVICE CHARACTERISTICS 307 is helpful to analyze the conditions under field-dependent mobility and velocity saturation which is discussed next. Velocity-Field Relationship. As technology advances and pushes for device performance and density, the channel length gets shorter and shorter. The internal longitudinal field gy in the channel also increases as a result. The general u - 8 relationship for high fields is shown in Fig. 11. Mobility p is defined as ulg. For low fields, the mobility is constant. This low-field mobility is used for the long-channel characteristics in the last section. In the extreme case of very high field, the velocity approaches a value, saturation velocity us.Inbetween the constant-mobility regime and the saturation-velocity regime, the carrier velocity can be described by23 where p,,is the low-field mobility. The value of n changes the shape of the curve, but p,,,v,, and the critical field 2Yc (= uJpn)remain the same. It has been observed that in silicon for electrons n = 2 and for holes n = 1 have the best fit. The value of usfor silicon at room temperature is around 1x lo7c d s . As the terminal voltage V, is increased from zero, current is increased because of higher field and higher velocity. Eventually the velocity reaches the maximum value of us,and the current also saturates to a constant value. Notice that this current saturation comes from a completely different mechanism than in the case of constant mobility. Here, it is due to velocity saturation of carriers, before the pinch-off condition can occur. To derive the I-V characteristics it is important to know the u - 8 relationship (Fig. 11). We find that mathematically, for Eq. 33 with n = 2, the analysis is rather complicated. Fortunately for the cases of two-piece linear approximation and Eq. 33 with n = 1, the mathematics is manageable and simple solutions can be obtained. Since these two extremes mostly cover the realistic bounds for different kinds of carriers, we will consider both assumptions. 8, Longitudinal field 8 Fig. 11 u-g relationship (Eq. 33) for n = 1 and 2, and two-piece linear approximation. The critical field gC= v, tp, where p is low-field m mobility, is also indicated. 308 CHAPTER 6. MOSFETs Field-Dependent Mobility: Two-Piece Linear Approximation. In the two-piece linear approximation, the constant-mobility model is valid up to the point when the maximum field near the drain exceeds gCC. onversely, Eq. 23 is valid up to a new VDsatvalue which occurs earlier than the constant-mobility model, so the only task is to find that point. Substituting Eq. 32 into Eq. 21 gives ID0.1) = ZcoxPn g(VG- V T -M A~ i ) . (34) Since we know the maximum field occurs at the drain, the current will saturate when the drain bias is increased to a value where g(L)= gC.Equation 34 leads to the following condition: IDsat = zcoxPn g ~ ( - vT - MVDsat) ' (35) Here we need one more equation to solve for two unknowns. Using Eqs. 32 and 22, we obtain an expression similar to Eq. 31 given as Equating Eqs. 36 and 35, we can solve for VDsaats Since VDsat here is always smaller than (V, - VT)/M(Eq. 29), the field-dependent mobility always gives a lower IDsat. Field-Dependent Mobility: Empirical Formula. Next we consider the u-g relationship of Eq. 33 with n = 1. Substituting this into Eq. 21 gives Notice that the right-hand side of the equation is similar to the constant-mobility model. Integrating the above equation from source to drain gives This equation is similar to Eq. 31 when L is replaced with L + V d g c .Furthermore, VDS,is obtained by setting dIddV, = 0, Again, once VDsaits known, ID,, can be calculated from Eq. 39. Velocity Saturation. Using either assumption described above, it is interesting and insightful to look at the extreme case of short-channel devices where velocity saturation completely limits the current flow. In such case we set u = us,and consequently Q, has to be fixed for current continuity, and is approximated to be ( V , - VT)Cox. Equation 22 then becomes 6.2 BASIC DEVICE CHARACTERISTICS 309 The transconductance becomes and it is independent of gate bias. To compare models based on constant mobility and velocity saturation, we show I-V curves of identical devices in Fig. 12. Several observations can be made. First, IDSanadt V,, are both lowered by velocity saturation, while the linear regions remain similar. The gm(which is the current difference between VGsteps) also becomes a constant, independent of V, Finally Eq. 41 shows an interesting phenomena that the saturation current no longer depends on the channel length. Experimental data confirm that such simple theory is quite satisfactory. In reality, as Fig. 11indicates, the carrier velocity never reaches exactly us.Also the lateral field is not uniform throughout the channel. It is more difficult for the lower field near the source to reach gCand that presents a bottle-neck for the maximum current. A better agreement can often be reached by adding a pre-factor with a value of = 0.5 - 1.O for Eqs. 41 and 42. Ballistic Transport. In the above section, velocity saturation is a steady-state, equilibrium phenomena at high field, when many scattering events are allowed to happen. However, in ultra-short channel lengths whose dimensions are on the order of or shorter than the mean free path, channel carriers do not suffer from scattering. They can gain energy from the field without losing it to the lattice through scattering, and can acquire a velocity much higher than the saturation velocity. This effect is called Fig. 12 Comparison of I-Vcharacteristics for (a) constant mobility and (b) velocity saturation. All other parameters are the same. 310 CHAPTER 6. MOSFETs ballistic transport (or velocity overshoot by some), introduced in Section 1.5.3. The ballistic transport is important since it points out that the current and transconductance can be higher than that of saturation velocity, giving an additional incentive for shrinking the channel length. The basic theory and insight in this topic are presented in Refs. 24-28. Computer simulations show that in these devices, the field and velocity are very nonuniform. These quantities are qualitatively shown in Fig. 13. Notice that the longitudinal field along the channel (dEJdy)varies monotonically, being the highest at the drain end. Ballisticity always starts at the drain end, where the velocity can exceed the value of saturation velocity v,. (For silicon at room temperature, v, = vth,the thermal velocity.) At positions closer to the source, the velocity decreases. In order to have current continuity, the channel potential and inversion charge must adjust themselves such that the product of velocity and charge would remain constant throughout the channel. By such argument, the bottleneck for the current flow, at the extreme of ultra-short channel length, would be at the position of maximum charge and minimum field, which means the potential maximum near the source end, indicated inFig. 13a. In analyzing the saturation current in the ballistic regime, we go back to the general equation of Eq. 22, and apply it to this maximum-potential point. We start with the generalized form I ~ s a t= ZIQnlv, (43) A .u- (b) Fig. 13 (a) Under a drain bias, the potential maximum is the bottleneck for the current flow and is used to calculate the current. (b) Average carrier velocity (y-component) as a function of the channel position. Note that ueff is between the values of uinjand vth,and rn that the maximum velocity near the drain can be higher than uini 6.2 BASIC DEVICE CHARACTERISTICS 311 where lQ,l has the maximum value at the source as CoxV( , -VT), and veffis an effective average carrier velocity that should match the final experimental saturation current. So in this simple expression, the only critical parameter is veT The maximum value of veF according to classical thermal equilibrium, is simply the thermal velocity vfh[= (2kT/m*)'/2].Close examination of the system reveals that for higher inversion charge density, the random velocity can exceed this thermal limit. This is a quantum-mechanical effect, called carrier d e g e n e r a ~ yw, ~h~ere the mean carrier energy is pushed to a higher state than the thermal energy. This higher value is called the injection velocity vinjr,elated to the Fermi energy with respect to the quantized energy Eninside the potential well where carriers reside, given by24 u. , = Fl/2[(EF-En)'kT] lnJ m * l n {1 + exp[(E,-E,)/kT]}' (44) where F I n is the Fermi-Dirac charge or EF- En,Eq. 44 is high, Eq. 44 can be simplified to 1.4.1). With a small inversion = vfh.If the inversion charge and is a function of the inversion charge or gate overdrive. Theoretical vinjas a h n c tion of the inversion charge is shown in Fig. 14. The maximum current, which is a product of Qnvinj,gives the ultimate current drive of the ballistic MOSFET and is also plotted in the same figure. The saturation current of Eq. 43 can be rewritten as Fig. 14 Injection velocity uinjas a function of inversion density. The product of uinjand inversion charge gives the maximum current. (After Ref. 24.) 312 CHAPTER 6. MOSFETs where r,, is the index of ballisticity (= ve,lvinj).In the extreme of ballistic transport, r,,= 1, and it sets the ultimate current drive for L -+0. The transconductanceis given by It is seen here that both IDsaantd gmare independent of channel length L. The index of ballisticityis also interpreted by back scatteringR of channel carriers at the drain back to the source. Furthermore, since mobility is also a consequence of scattering, there should be some relationship between r,, and the low-field mobility p,,. It has been shown that:26 where 2?(0+) is the field at a potential kT down from the maximum toward the drain. With this interpretation, some experimental data and simulation trends are nicely explained.It has been seen that at lower temperature,IDSaistincreased,and that at the same temperature, higher low-field mobility always gives higher IDseavten in the ballistic regime. Both of these can be explained through improvementof p,, in Eq. 48. It should be emphasized that in this model, at or near the maximum-potential point, the field is too low to causeballistictransport, so uinjsets the maximum current, even though a location near the drain can have ballistic transport. The high ballistic velocities near the drain cannot produce a higher current than vinjcan support, but it helps to achieve this maximum value set by vjnjby rebalancing the whole system. It is interesting to compare the VGdependence of IDsaftor different channel lengths. In the long-channel, constant-mobility regime, IDsaoct (VG- VT)2I.n the short-channel, saturation-velocityregime, IDsaotc (VG- VT).And in the limit of ballistic regime, IDscact(VG- VT)3'2. 6.2.3 Threshold Voltage We now return to the discussion of threshold voltage, first mentioned in Eq. 25. To account for the threshold shift from nonzero flat-band voltage whose main cause comes fiom fixed oxide charges @and the work-hnction difference #ms between the gate material and the semiconductor, Eq. 25 becomes Qualitatively, VTis the gate bias beyond flat-bandjust starting to induce an inversion charge sheet and is given by the sum of voltages across the semiconductor(2 vBa)nd 6.2 BASIC DEVICE CHARACTERISTICS 313 the oxide layer (last term of Eq. 25). The square-root term is the total depletion-layer charge. When a substrate bias is applied (negative for n-channel or p-substrate), the threshold voltage becomes L.ox and it is shifted by the amount of In practice it is often necessary to minimize this threshold-voltage shift due to substrate bias. In these cases, low substrate doping and thin oxide thickness are preferred. To measure the threshold voltage, we use the linear region by applying a small drain bias (V, << V,), and plot ,Z versus VGas shown in Fig. 15a. According to Eq. 2 4 , the extrapolated value at the VGaxis is equal to V T +%V,. Below the threshold voltage, ID is considered zero in the linear scale, but details can be displayed in the logarithmic scale (Fig. 15b). 40L 30 - z 2 20- 49 - 10 - l1o0?" Fig. 15 Transfer characteristics (Z, vs. V,) in the linear region (V, << VG).(a)ZDin linear scale to deduce V, Deviation from linearity at higher V, is due to lower mobility. (b) ID in loga- rithmic scale to show subthreshold swing. 314 CHAPTER 6. MOSFETs 6.2.4 Subthreshold Region When the gate bias is below the threshold and the semiconductor surface is in weak inversion or depletion, the corresponding drain current is called the subthresholdcurrent.29,3T0 he subthreshold region tells how sharply the current drops with gate bias and is particularly important for low-voltage, low-power applications, such as when the MOSFET is used as a switch in digital logic and memory applications. In weak inversion and depletion, the electron charge is small and, thus, the drift current is low. The drain current is dominated by diffusion and is derived in the same way as the collector current in a bipolar transistor with homogeneous base doping. Considering the electron-density gradient in the channel, the diffusion current is given by where N' is the electron densityper unit area, integratedover the depletionwidth. The electron density at the source end is given by I,"" "(0) = 0 4 x 1 = npoj-vs exP(PWp) dWp. (53) Since the potential distribution inside the depletion region is known, this electron density can be calculated to be31 Similar result can be obtained by assuming an effective thickness (xi)of the surface charge layer. Because of the exponential dependence of electron density on the poten- tial cup, xicorresponds to the distance in which yPdecreases by kTlq. Therefore,xi is kTlqgs where gsis the semiconductorsurface field. With this assumption,we get the (Z) same expression "(0) = x i x n ( x = O ) = np0exP(Pv/,) (55) The electron density at the drain end is lowered exponentially by the drain bias, "(L) = N'(O)eXp(-P&). (56) SubstitutingEqs. 55 and 56 into Eq. 52 gives 6.2 BASIC DEVICE CHARACTERISTICS 315 when V, >> kTlg. Equation 57 indicates that in the subthreshold region the drain current varies exponentially with ys,and for drain voltage V, larger than = 3kT/q,the current becomes independent of V,. Next, in order to relate current to the gate bias, the relationship between V, and w;. is needed. From Chapter 4 on the MOS capacitor, we have the following relationship (Eq. 33): ox This quadratic equation will not give a simple expression of ySas a function of V, But once w, is known from Eq. 58, the subthreshold current can be calculated. The parameter to quantify how sharply the transistor is turned off by the gate voltage is called the subthreshold swing S (inverse of subthreshold slope), defined as the gate-voltage change needed to induce a drain-current change of one order of magnitude. First, from Eq. 58, the relative change of V, and % is calculated to be By definition, the subthreshold swing can now be calculated: Note that w, in the square-root term in Eq. 57 is treated as a constant since it is a much weaker function compared to the exponential term. Having derived the subthreshold swing in Eq. 60, it is intuitive to explain its simple form. In the extreme of zero oxide thickness, the exponential characteristics are identical to the familiar case of the diffusion current in ap-n junction. For nonzero oxide thickness, the swing is just degraded by a factor which is a voltage divider of two capacitors in series, whose ratio is (Cox+ C,)/Cox. The voltage divider is exactly the implication of Eq. 59. One also notices that since the depletion width (and CD) varies with w,, the subthreshold swing is a weak function, but not exactly constant with V,. In the presence of a significant interface-trap density Di,i,ts associated capaci- tance Ci,(= q2Dit)is in parallel with the depletion-layer capacitance C,. Using Eq. 60 and substituting (C, + C,,) for C, (see Fig. 14 of Chapter 4), we obtain S(with Di,) = ( l n l O ) ( q ( 9 cox = S(without Di,) x Cox + CD+ Cit ‘ox + ‘D ’ If other device parameters such as doping and oxide thickness are known, by measuring the subthreshold swing, the interface-trap density can be obtained. This pro- 316 CHAPTER 6. MOSFETs vides an attractive option in measuring Di, besides using the MOS capacitor in which ac measurements have to be made. In general, dc I-Vmeasurements are much easier to make than ac capacitance and conductance, provided a three-terminal transistor structure is available (substrate contact is not critical here). For a sharp subthreshold slope (small S), it is preferable to have low channel doping, thin oxide thickness, low interface-trap density, and low-temperature operation. When a substrate bias is applied, in addition to shifting the threshold voltage, it increases the value of w,by VBpConsequently,the depletion-layer capacitance CDis reduced and therefore S is reduced. In Fig. 15a, at and near the threshold voltage, the drain current does not turn off as sharply as Eq. 24 predicts. This is due to diffhion current which is the dominant current near and below threshold, and it has been ignored so far, as one of the assumptions made at the beginning of Section 6.2.2. To consider the effect of the difision component, we refer to Fig. 7 for the nonequilibrium condition. The total drain current density including both drift and difision components is given by The drain current based on the gradual-channel approximation is The gate voltage V, is related to the surface potential w; by V,-V,, = - - +Q, Iy, cox Equation 63 reduces to Eq. 23 for gate voltages well above threshold. The latter, however, becomes inaccurate for gate voltages near and below threshold and near the pinch-off point. For a particular device with known physical dimensions and other device parameters, Eq. 63 can be calculated numerically to give accurate results for the entire range of drain voltage, from the linear region to the saturation region. 6.2.5 Mobility Behavior Because channel carriers are confined to a thin inversion layer, their drift velocity u and mobility p are expected to be influenced by the thickness of this inversion layer. When a small longitudinal field g,,is applied (parallel to the semiconductor surface), the drift velocity varies linearly with gy and the proportionality constant is the lowfield mobility. Experimental measurements on Si inversion layers show that this low- 6.2 BASIC DEVICE CHARACTERISTICS 317 field mobility, while independent of gY is a unique function of the transverse field gX that is perpendicular to the current This dependence is not directly on the oxide thickness or doping density, but through their impact of EXin the inversion layer. The measured results are shown in Fig. 16. When many devices with different oxide thicknesses and doping levels are measured, the mobility is found to correlate well with a single parameter that is related to gX.At a given temperature, mobility decreases with an increasing effective transverse field, defined as the field averaged over the electron distribution in the inversion layer, given by Physically it means an average inversion carrier experiences the fill effect of the depletion-layer charge Q, but only half of the inversion-layer charge Q,. Note that this effective mobility is valid for the current expressions in Eqs. 24 and 27, but will be slightly different from that in the g, expression (such as Eq. 30) in which constant mobility has been assumed. When the longitudinal field increases, the u- g relationship starts to deviate from linearity. This field-dependent mobility has been discussed and generally described by Eq. 33 and shown in Fig, 11. Measured electron drift velocity as a function of gY for various gXis shown in Fig. 17. Since mobility at any field is defined as the ratio of u/gYit decreases monotonically with gYEventually velocity saturation occurs and results in a value similar to that of bulk silicon. The influence of ZXon low-field 1000 700 500 h N, (cm”) 0 3.9~10’~ 0 2.0xl0’6 A 7.2~10’~ A 3.0x1017 0 7.7~10‘~ 2.4~10’~ 300 -v 5 9 200 .0- e 2 5 100 70 50 0.02 0.1 0.2 1 Effective transverse field geE(MV/cm) ND( ~ r n - ~ ) o 7.8~10’~ 0 1.6~10’~ A 5.1~10’~ A 2.7~10’~ 0 6.6~10’~ 2 Fig. 16 Electron and hole inversion-layer mobilities vs. effective transverse field, at room temperature on Si (100)surface. (AfterRef. 33.) 318 CHAPTER 6. MOSFETs 104 I Longitudinal field (Vicm) Fig. 17 Electron surface drift velocity vs. longitudinal field for various transverse fields. The slope at low longitudinal field is mobility. (After Ref. 34.) mobility from Fig. 16 is also reflected in this figure. It can be seen here also that the saturation velocity usis independent of the low-field mobility or gX. 6.2.6 Temperature Dependence Temperature affects device parameters and performance, in particular mobility, threshold voltage, and subthreshold characteristics. The effective mobility in inversion layer has a F2power dependence on temperatures around 300 K at gate biases corresponding to strong inversion.32This gives rise to higher current and transconductance at lower temperature. To derive the temperature dependence of the threshold voltage, we repeat the expression from Eq. 49: Because the work-function difference #,s and the fixed oxide charges are essentially independent of temperature, differentiating Eq. 66 with respect to temperature yields35 From the basic equations of 6.2 BASIC DEVICE CHARACTERISTICS 319 -E 'n K T3exp($), where Egois the energy gap at T = 0, we obtain Figure 18 shows the results of such calculations at room temperature as a function of substrate doping for various values of oxide thickness. Note that depending on the oxide thickness, the quantity IdV,ldT' can increase or increase with the substrate doping. As temperature decreases, the MOSFET characteristics improve, especially in the subthreshold region. Figure 19 shows the transfer characteristics of a long-channel MOSFET ( L= 9 pm) with temperature as a parameter. Note that as temperature decreases from 296 K to 77 K, the threshold voltage VTincreases from 0.25 V to about 0.5 V. This increase in Vr is similar to that shown in Fig. 18. The most-important improvement is the reduction of the subthreshold swing S, from 80 mvldecade at 296 K to 22 mVIdecade at 77 K. Thus, the improvement in the subthreshold swing at 77 K is about a factor of four. This improvement comes mainly from the kTlq term in Eq. 60. Other improvements at 77 K include higher mobility, thus, higher current and transconductance, lower power consumption, lower junction leakage current, and lower metal-line resistance. The major disadvantages are that the MOSFET must be immersed in a suitable inert coolant (e.g., liquid nitrogen), and that a low-temperature setup requires additional equipment and special care. d = lOOnm I I I IIIIII I I I IIIIII I I 111111 15 10'6 1017 10'8 N, ( ~ m - ~ ) Fig. 18 Threshold-voltage shift (dV,ldT) of a Si-SiO, system at room temperature vs. substrate doping, with oxide thickness d as a parameter. 320 CHAPTER 6. MOSFETs I" 4.2 0 0.2 0.4 0.6 0.8 1.0 vc (V) Fig. 19 Subthreshold characteristics for a long-channel MOSFET (L= 9 pm) with temperature as a parameter. (After Ref. 36.) 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE In Section 6.2 doping concentration in the channel is assumed to be constant. In practical devices, however, the doping is generally nonuniform because in modern MOSFET technology, ion implantation is used extensively to taylor the doping profile and improve the device performance for specific applications. For example, a lighter doping at deeper region reduces drain-substrate capacitance and also the substrate-bias effect. On the other hand, a lighter doping level near the Si-SiO, interface lowers the threshold voltage, reduces the field and improves mobility, and higher level at deeper region reduces punch-through between source and drain. These two general cases, namely highilow and low-high profiles, are depicted in Fig. 20, with their step-profile approximations for ease of analysis. We consider next the effect of nonuniform channel doping on device characteristics, especially on threshold voltage and depletion width which in turn affects subthreshold swing and the substrate-bias effect. Note that what is most important for determining V, is the doping profile within the depletion region. The profile outside the depletion is important for considerations of capacitance and substrate sensitivity, that is, dependence of the threshold voltage on the substrate reverse bias. With that in mind, the general equation for the threshold voltage is given by 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE 321 "T L. LX WD, wDm (c) (4 Fig. 20 Nonuniform channel doping profiles. (a) High-low profile. (b) Low-high (retrograde) profile. (c) - (d) Their approximations using step profiles. where QBis the depletion-layer charge. The limit for integration, that is the maximum depletion width W,, is needed and determined by the Poisson equation with the onset of strong inversion being the boundary condition, Note that for a nonuniform profile, the definitions of (vB and VFBbecome nontrivial and complicated. Fortunately, using the background doping of NBfor these values is found to be sufficiently accurate. This is especially true for the surface potential = 2 y- since it is a very weak function of doping level. 6.3.1 High-Low Profile To derive the threshold voltage shift due to ion implantation, we shall consider an idealized step profile as shown in Fig. 20c. The implant profile, after thermal anneal, is approximated by the step function with step depth x,, roughly equal to the sum of the projected range and the standard deviation of the original implant. For a wider x,,that is, the maximum depletion-layer width W, under heavy inversion is within x,, the surface region can be considered a uniformly doped region with a higher concentration. The threshold voltage is identical to that given by Eq. 50. If W,, > xs,the threshold voltage is obtained from Eq. 71, 322 CHAPTER 6. MOSFETs The depletion width can be obtained from Eq. 7 2 , using yy= 2 vBfor strong inver- sion: From these equations, we see that added surface doping increases VTand decreases wDm. Notice that for the same dose, the V,shift is largest with the added doping closest to the surface. For the limiting case of a delta function of dose localized at the Si-SiO, interface (x, = 0), the threshold shift is simply where D , is the total dose m x s . Such approach is called threshold adjust, which has the same effect as changing the work-function difference q$ms or changing the total fixed oxide charge. The step-profile approach described above can give first-order results for the threshold voltage. To obtain a more accurate V p we have to consider the actual doping profile, because the step width x, is not well defined for nonuniform doping. A schematic diagram for the nonuniform implanted doping N(x) is shown in Fig. 2 1. For a typical case, the threshold voltage depends on the implanted dose DI and the centroid of the dose x,. Therefore, the actual implant can be replaced by a delta-function located at x =x , as shown; "t ,I1 I Delta approximation !I I I Implanted profile , I I xc xs NB Fig. 21 Approximation of an actual ~ implanted profile by step and delta profiles. r m 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE D, = AN(x)dx, 323 $1x, = WD, xAN(x)dx. (77) With these, Eqs. 73 and 7 4 are now generalized to: It is interesting to examine the dependence of the threshold voltage shift and depletion width on the centroid x, for a given dose D,. For x, = 0, the implant is a delta hnction at the Si-SiO, interface, and Eq. 78 gives AVT = qD/CoX,which is the same as Eq, 75. As x, increases, the dose becomes less effective in changing V , and the depletion width W, decreases also at the same time. Eventually x, meets the deple- tion edge, and then W,, becomes clamped to and increases with the implant centroid x,. The condition for which x, starts to be equal to W, can be obtained from Eq. 79: where WDmios the original W, with background doping NB.Eventually, as xcmoves beyond the WDmOit,no longer has any effect on threshold voltage and depletion width. To consider the subthreshold swing and the substrate sensitivity, in Section 6.2.4 we have interpreted the subthreshold swing by comparing the gate-oxide capacitance COXto depletion capacitance C., So, once the depletion width is known, the subthreshold swing can be calculated. For the high-low profile, the added doping decreases W,, increases C, and results in a larger (less steep) subthreshold swing. The substrate sensitivity can be calculated also by substituting 2 yBwith 2 + I,U~ Vssin calculating Vr 6.3.2 Low-High Profile Analysis of the low-high profile (Fig. 20b), also called the retrograde profile, is similar to the high-low case with a AN being subtracted from the background doping. The appropriate equations for the threshold voltage and depletion width become, with just a change of signs: 324 CHAPTER 6. MOSFETs and Jm. w,, = The threshold voltage is, thus, decreased and the depletion width is increased by a dip at the surface doping. 6.3.3 Buried-Channel Device In the extreme case of the low-high profile, the surface doping can be of the opposite type of the substrate. When this happens, and if part of the surface doped layer is not hlly depleted, that is, there exists some neutral region, current can conduct through this buried layer. We call this type of device a buried-channel device.3740Figure 22a shows a cross section of such a buried-n-channel MOSFET. The gate voltage can change the surface depletion layer, thus controlling the net opening of the channel thickness and controllingthe current flow. With a large positive gate bias, the channel is hlly open, and an addition surface inversion layer can be induced at the surface, similar to a regular surface channel, resulting in two channels in parallel. The surface inversion channel has been the subject of discussion and needs no further elaboration. We now focus on the buried channel whose doping and dimensions are shown in Fig. 22b and whose energy-band diagrams are shown in Fig. 23. The net channel thickness is reduced from xs by the amounts of surfacedepletion WDs and the bottomp-n junction depletion WDnT.he surface depletion as a function of V, is the same as Eq. 27 of Chapter 4, and is repeated and modified here as (4 (b) Fig. 22 (a) Schematic of a buried-channel MOSFET under bias. (b) Its doping profile and depletion regions. 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE 325 e: (a) ........ Oxide 9% -G- 4 vbi ~ (b) Fig. 23 Energy-band diagrams of a buried-channel MOSFET, for the bias 4 vbi conditions of (a) flat band (V, = V;B ), (b) surface depletion, and (c) threshold O-dexi (c) (vG = vl'). Note that the flat-band voltage V& takes on slightly different meaning here (Fig. 23a). We refer now to the condition that the surface n-layer has flat band, as opposed to thep-substrate. The new flat-band voltage is redefined as v;B = v F B + vbi (84) where V, keeps thep-substrate as reference. The bottom depletion width is from the p-n junction theory, given by Of special interest is the threshold voltage V, at which gate bias the channel width is totally consumed by both depletion regions. Setting the condition of x s = wD,y + W D n , (86) the threshold voltage is obtained;40 L)(". '-> V, = VFB-qNDxs(& + + + 2 q E s N D N A v b i -- N A v b i , (87) 2Es cox &s cox ND+NA ND+NA 326 CHAPTER 6. MOSFETs Once the channel dimensions are known, the channel charge can be calculated easily. Depending on the gate-bias range, we can have different amounts of bulk change QB and surface inversion charge Q,. These are given as; Q = QB = (x, - WD,- W D J N D2 and VT< V G < v$B 1 (88) Q = QB+Q, -- (xs- wDn)ND+ Cox(V G - V$B>9 V>B < vG. (89) Given the channel charge, the drain current can be calculated in a way similar to those previously derived. But compared to the surface-channel devices, the buried-channel MOSFET equations are more complicated since the coupling of the gate to the channel (or net gate capacitance) is now gate-bias dependent. Qualitative I- Vcharac- teristics are shown in Fig. 24. More-exact solution of the drain current can be obtained by substituting the charge into Eq. 22. The results, divided into different regimes of V, bias, are summa- rized in Table 1. These results are based on the long-channel constant-mobility model. Current saturation due to velocity saturation can be estimated to be = Qu,K A buried-channel MOSFET is usually normally-on (depletion-mode), although theoretically it can be made as a normally-off (enhancement-mode) device, by proper choice of metal work function, for example. Also for a given ND, the threshold voltage becomes more negative with increased buried-channel depth x,. However, because there exists a maximum depletion width in an MOS system, if the doping density NO orland the buried-channel depth x, are sufficiently large, WDscan reach a maximum value without pinching off the channel. A limit on the channel profile thus exists, otherwise the transistor cannot be turned off. This condition is bound by a combination of x, and ND; E L'T< 'C LEZ 0 VD (a) conduction VT VC (b) Fig. 24 Buried-channel MOSFET (a) Output characteristics. (b) Transfer characteristics (ZD vs. V,) in linear region (small VD),showing threshold voltage V ,and flat-band voltage V,& . 6.3 NONUNIFORM DOPING AND BURIED-CHANNEL DEVICE 327 Table 1 Current Equations for Buried-Channel MOSFETs, Based on Long-Channel Constant Mobility (After Refs. 15 and 37) In the buried-channel devices, the substrate-bias effect is more direct. It can be viewed as a bottom gate. The effects are calculated in the above equations if ybiis replaced with ybi- VBs(VBsis negative). In particular, V, (Eq. 87) and W, (Eq. 8 5 ) can be shifted with a substrate bias, to the extent that the transistor can be turned on and off and between depletion-mode and enhancement-mode. We now turn to the subthreshold current of buried-channel devices. At a suffi- ciently large negative gate bias, the channel will be pinched off, that is, when x, = W, + W, (Fig. 23c). The conduction below the threshold voltage is due to the pres- ence of a region of partially depleted electrons, wherein the current is carried primarily by difision of electrons. The resulting subthreshold (sub-pinch-off) current for a buried-channel MOSFET is, thus, directly analogous to the subthreshold current for a surface-channel MOSFET. The subthreshold current will vary exponentially with the gate voltage, and the subthreshold swing S is given by the capacitive divider ratio again of Eq. 60, except now different capacitances have to be used. From Fig. 23c, the maximum electron concentration occurs at the location of x = xs- WD,. So C, of Eq. 60 should be replaced with the depletion capacitance of the substratep-njunction 328 CHAPTER 6. MOSFETs [&,l(WDn+ WDp)]a,nd Coxshould be replaced with Coxin series with the surface depletion capacitance &,/WDs.These substitutions give an expression of 39 where all depletion layers WDsW, , , ,and WDpcorrespond to the condition at threshold (V, = VT)T. he subthreshold swing is usually larger than that of conventional surfacechannel devices. The buried-channel device is expected to have higher carrier mobility than surface-channel devices since carriers are free of surface scattering and other surface effects. They are also less affected by the short-channel effects (to be discussed next) such as hot-carrier-inducedreliability problems. On the other hand, since the net distance between the gate and the channel is further away and is gate-bias dependent, the transconductance is smaller and variable. Note that if the gate is replaced by a Schottkyjunction or a p-n junction, the device become a MESFET or a JFET correspondingly, both to be discussed in the next chapter. 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS Since 1959, the beginning of the integrated-circuit era, the minimum feature length has been reduced by more than two orders of magnitude. We expect the minimum dimension will continue to shrink in the foreseeable future, as illustrated in Fig. 1. As the MOSFET dimensions shrink, they need to be designed properly to preserve the long-channel behavior as much as possible. As the channel length decreases, the depletion widths of the source and drain become comparable to the channel length and punch-through between the drain and source will eventually occur. This requires higher channel doping. A higher channel doping will increase the threshold voltage, and in order to control a reasonable threshold voltage, a thinner oxide is necessary. One sees that the device parameters are interrelated, and certain scaling rules are used to optimize the device performance. Even with the best scaling rules, as the channel length is reduced, departures from long-channel behavior are inevitable. These departures, the short-channel effects, arise as results of a two-dimensional potential distribution and high electric fields in the channel region. The potential distribution in the channel now depends on both the transverse field gX(controlled by the gate voltage and the back-substrate bias) and the longitudinal field gY(controlled by the drain bias). In other words, the potential distribution becomes two-dimensional, and the gradual-channel approximation (that is, gx>> gY)is no longer valid. This two-dimensional potential results in many forms of undesirable electrical behavior. As the electric field is increased, the channel mobility becomes field-dependent, and eventually velocity saturation occurs. (The mobility behavior was discussed in Section 6.2.5.) When the field is increased further, carrier multiplication near the drain occurs, leading to substrate current and parasitic bipolar-transistor action. High 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS 329 Table 2 MOSFET Scaling Parameter L z d 5 VT VD NA Scaling factor: Constant- 8 1/K 1 1/K 1/K 1/K 1/K K Scaling factor: Actual Limitation / / >1 >1 / ~ > 1/K >> 1 / K >> 1 / K 0, and (b) VD= 0 where W, = W, 3 WDm. (After Ref. 47.) 332 CHAPTER 6. MOSFETs and 1-D analysis is sufficient. For short-channel devices, the full effect of Q(, on the threshold voltage is reduced, because near the source and drain ends of the channel, some field lines originating from the bulk charges under the channel region terminate at the source or drain instead of the gate (Fig. 26a). Note that the horizontal depletion-layer widths ys and y , are smaller than the vertical depletion-layer widths W, and W,, respectively, because the transverse field strongly influences the potential distribution at the surface. First-order estimation of the threshold voltage can be made by considering the charge partition. The total bulk depletion charge can be estimated by the trapezoid 47 For small drain bias, we can assume that W, z W, = W,, and by straightforward trigonometric analysis (Fig. 26b), L' = ~ - 2 ( J r j 2 + 2 ~ ~ , r ~ - r ~ ) . (98) The threshold-voltage shift from long-channel behavior is then given by The negative sign means V,is lowered and the transistor is easier to turn on. To take into account the effect of the drain voltage and the substrate bias, Eq. 99 can be modified to read 48 where y , and y , are given as = d 2 ES q-(N A V/bi + VD - ~s - VBS). (101b) Note that the threshold voltage becomes a function of both L and VD.Figure 27 shows this dependence on both channel length and drain bias. 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS 333 sE b 0.2 - 0 I I 1 I I I I I 6.4.3 Channel-Length Modulation Figure 26a also shows that yDis a high-field region where carriers are swept out efficiently.ys is a transitional region where the electron concentration is higher than that in the main channel. So for consideration of the channel drift region, the effective channel length is more meaningful, given by L e y = L' = L -ys-yD. ( 102) This factor contributes to a drain-bias dependence of the effective channel length and partially accounts for the nonsaturating current with drain bias. Nevertheless, the change of channel length affects the current only linearly, whereas the barrier lowering caused by the drain bias, considered next, is much more pronounced since the current has an exponential dependence on the barrier. 6.4.4 Drain-Induced Barrier Lowering (DIBL) We have pointed out that when the source and drain depletion regions are a substantial fraction of the channel length, short-channel effects start to occur. In extreme cases when the sum of these depletion widths approaches the channel length bs+yo = L), more-serious effects will happen. This condition is commonly called punch-through. The net result is a large leakage current between the source and drain, and that this current is a strong function of the drain bias. The origin of punch-through is the lowering of the barrier near the source, commonly referred to as DIBL (drain-induced barrier lowering). When the drain is close to the source, the drain bias can influence the barrier at the source end, such that the channel carrier concentration at that location is no longer fixed. This is demonstrated by the energy bands along the semiconductor surface, shown in Fig. 28. For a longchannel device, a drain bias can change the effective channel length, but the barrier at 334 CHAPTER 6. MOSFETs Fig. 28 Energy-band diagram at the semiconductor surface from source to drain, for (a) longchannel and (b) short-channel MOSFETs, showing the DIBL effect in the latter. Dashed lines VD= 0. Solid lines VD> 0. the source end remains constant. For a short-channel device, this same barrier is no longer fixed. The lowering of the source barrier causes an injection of extra carriers, thereby increasing the current substantially. This increase of current shows up in both above-threshold and subthreshold regimes. Figure 28 shows that punch-through condition occurs at the semiconductor surface. In practical devices, it is common that the substrate concentration is reduced below the depth of the sourceldrain junction 5. A reduced substrate doping widens the depletion widths so punch-through can also happen via a path in the bulk. An example of severe punch-through characteristics above threshold is shown in Fig. 29a. For this device, at V, = 0 the sum of ys and yo is 0.26 pm which is larger than the channel length of 0.23 pm. Therefore, the depletion region of the drain junc- 104 10-5 10-6 d v ,S 10-7 10-8 10-9 I "-'"Oh -0.4 -0.2 0 0.2 vG (v) (b) Fig. 29 Drain characteristics of MOSFETs showing DIBL effect. (a) Above threshold. L = 0.23 pm. d = 25.8 nm. NA= 7 ~ 1 0~' r~n - ~(b.) Below threshold. d = 13 nm. NA = 1014~ m - ~ . (After Ref. 50.) 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS 335 tion has reached the depletion region of the sourcejunction. Over the drain bias range shown, the device is operated in punch-through condition. Under such a condition, majority carriers in the source region (electrons in this case) can be injected into the depleted channel region, where they will be swept by the field and collected at the drain. The punch-through drain voltage can be estimated by the depletion approximation to be Drain current will be dominated by the space-charge-limited current: where A is the cross-sectional area of the punch-through path. The space-chargelimited current increases with and is parallel to the inversion-layer current. The calculated points in the figure are from a 2-dimensional computer calculation incorporating the punch-through effect and field-dependent mobility effect. The DIBL effect on subthreshold current is shown in Fig. 29b, for various channel lengths. The device with a 7-pm channel length shows long-channel behavior, that is, the subthreshold drain current is independent of drain voltage when VD> 3kTlq (Eq. 57). For L = 3 pm, there is a substantial dependence of current on V,, with a corresponding shift of Vr(which is at the point of current departure of the I- Vcharacteristic from the straight line). The subthreshold swing also increases. For an even shorter channel, L = 1.5 pm, long-channel behavior is totally lost. The subthreshold swing becomes much worst and the device cannot be turned off any more. 6.4.5 Multiplication and Oxide Reliability We pointed out earlier that due to nonideal scaling, the internal electric fields in MOSFETs would increase with shorter channel lengths. In this section we discuss the anomalous currents associated with high fields, as well as their impacts. Figure 30 depicts all parasitic currents in addition to the main channel current. Note that the highest field occurs near the drain, and this is the location where most of the anomalous currents originate. First, as the channel carriers (electrons) go through the high-field region, they acquire extra energy from the field without losing it to the lattice. These energetic carriers are called hot carriers whose kinetic energy is measured above the conduction band E,. This extra energy, if larger than the Si/Si02barrier (3.1 eV), enables them to escape to the oxide layer and to the gate terminal, and gives rise to a gate current. Another major phenomenon happening in the high-field region is impact ionization which generates extra electron-hole pairs. These extra electrons go directly to the drain and add to the channel current. The path of the generated holes, however, is more diverse. A small fraction of them are driven to the gate, analogous to the hot electrons mentioned before. The majority of the generated holes flow to the substrate. For short-channel devices, some holes will go to the source. The division of these 336 CHAPTER 6. MOSFETs P vD l ! C 'BS Fig. 30 Current components of a MOSFET under high fields. paths depends on how good the substrate tie is. A perfect substrate tie (Rsub= 0) will sink all the hot holes and none of them will go to the source. As explained later, holes going to the gate or source will produce undesirable effects. An example of the MOSFET terminal currents, including the gate current and substrate current, are shown in Fig. 3 1. Note that the gate current is due to hot electrons and hot holes over the barrier and is different from carriers tunneling through the barrier. This hot-carrier gate current peaks approximatelyat Vc = V,. It is gener- ' 10-1 10-12 io-l3,!, I \ 11 2I 3I 41 5I 61 71 81 91 11 0 1 v, (V) Fig. 31 Drain current, substrate current, and gate current vs. gate voltage of a MOSFET. LIW = 03/30 pm.(After Ref. 5 1.) 6.4 DEVICE SCALING AND SHORT-CHANNEL EFFECTS 337 ally very small, and it by itself does not post a problem since it is negligible compared to the channel current. The impacts are the damages it creates. It is well known that these hot carriers create oxide charges and interface traps.52As a result, device char- acteristics change with operation time. In particular, the threshold voltage shifts, gen- erally to a higher value, and the transconductance g, degrades because of interface traps and reduced channel mobility. The subthreshold swing becomes larger because of increased interface-trap density. To reduce oxide charging, the density of water- related traps in the oxide should be minimized,53because such traps are known to capture hot carriers on their passage. In order to ensure MOSFETs’ performance over a reasonable time, it is important to quantify the device lifetime over which the device parameters do not drift outside a given range, for a given bias condition. This is part of the specification of a MOSFET technology. Figure 3 1 also shows the general characteristics of the substrate current. The sub- strate current has a unique bell shape as a function of gate bias.54It increases first with VG, reaches a maximum then decreases. This maximum occurs usually around V, Y V,/2. The maximum in I,, can be explained as follows. Assuming that the impact ionization occurs uniformly in the high-field region, the substrate current can be written as m, 1,s 1, a( 1 (105) where a is the ionization coefficient, the number of electron-hole pairs generated per unit distance, and is a strong function of the electric field; andy, is the high-field or pinch-off region. For a given V, as V, increases, both I , and VDsat increase (V,,,, Y V, - VT).When V, increases, the lateral field [= (VD - V,,,,>/y,] decreases, causing a reduction of a. Thus we have two conflicting factors. The initial increase of IBSis caused by the increase of drain current with V, and at larger V,, the decrease of I,, is due to the decrease of a. Maximum I,, occurs where the two factors balance each other. Empirically, the substrate current can be expressed as where C, and C, are constants. For a short-channel device, that is, a small source-drain separation, avalanched holes have increasing tendency to flow to the source.55This hole current constitutes a base current of a parasitic n-p-n bipolar-transistor action, where source-substratedrain is equivalent to the emitter-base-collector configuration. For every hole that goes to the source, there are many electrons injected to the substrate. These electrons will be collected by the drain and show up as additional drain current. This bipolar current gain InlIpis roughly determined by the ratio of NDINAA. nother way to look at this is that the substrate current develops a substrate voltage IBSxRsuwbhich puts the source-substratep-n junction under forward bias, thereby injecting electrons into the substrate. An additional effect is that the higher substrate potential lowers the threshold voltage for the surface channel and increases the surface-channel current. Both effects will increase the total drain current. These effects will become worst with an increase of R,, and shorter L. In the extreme case of a MOSFET without a 338 CHAPTER 6. MOSFETs substrate contact (Rsub = a)) such as an SO1 or TFT structure (Section 6.5.4), the output curves show sudden rise of I D with VD.This is referred to as kink effect in the output characteristics. In more-severe cases, the substrate current can induce source-drain breakdown from this parasitic n-p-n bipolar action. Analogous to the analysis of a bipolar breakdown (Section 5.2.3), since the source-drain distance is much shorter than the drainto substrate contact, the base can be treated as open, and the MOSFET source-drain breakdown is given by the parasitic open-base bipolar breakdown (Eq. 47 of Chapter 5 ) VBDs = v B D x ( l - anpn)lin. (107) Here VBDxis the drain-substrate p-n junction breakdown voltage, and n describes the shape of this diode breakdown characteristics. anpnis the common-base current gain, given by the product of the base transport factor aTand emitter efficiency y. Assuming y= 1, we have anpn = ~ T Y = % I - - L2 2Li (108) where L (channel length) is the effective base width, and Lnis the electron difision length in the substrate. From the above equations the breakdown voltage between source and drain is obtained for a short-channel MOSFET as Equation 109 has been used to fit the data quite well, provided that the factor n is chosen to be 5.4.55The difference in breakdown voltage for different junction curvature can be explained by the dependence of VBDxon rj, as discussed in Chapter 2. To reduce the parasitic transistor effect, the resistance of the substrate Rsub should be minimized so that the product of ZBsXRsubremains smaller than = 0.6 V. Then the breakdown voltage of a short-channel MOSFET will no longer be limited by this parasitic bipolar effect, and higher voltages and more-reliable operation can be expected. The drain-gate overlap region forms a gated-diode structure. For a thin oxide together with an abrupt junction, avalanche can occur during certain bias condition and it results in a drain leakage current going to the substrate. Such gated-diode avalanche current is called gate-induced drain leakage (GIDL) and the mechanism has been discussed in more details in Section 2.4.3. For an n-channel device, with a fixed drain bias, the normal channel current decreases with decreasing gate bias into the subthreshold regime. At some gate bias, the drain current becomes the GIDL current, and it rises again with more negative gate bias. Very often, in short-channel devices, this GIDL current already exists at V, = 0, imposing a leakage current component in their ~ f f - s t a t e . ~ ~ 6.5 MOSFET STRUCTURES 339 6.5 MOSFET STRUCTURES Up to now, Si MOSFET has been the workhorse of the electronics industry. As such, the MOSFET channel length and other dimensions have been pushed to shrink for the benefits of performance and density (see Fig. 1). While there is much discussion on what dimensions are the scaling limits,57it is certainly true that device scaling is getting increasingly difficult and has diminishing return. There are many possible reasons for hitting the end of scaling. These include: sensitivity of statistical doping fluctuations and surface charges, various forms of short-channel effects, quantum confinement in inversion layer which places a limit on gate capacitance, source/drain series resistance, etc. Most-recent data suggest that channel length below 20 nm is feasible, even with planar t e c h n o l ~ g y . ~H~ow- e~v~er, for practical applications, the scaling limit is most likely around 10 nm, even for 3-dimensional structures. Many device structures have been proposed to control short-channel effects and improve MOSFET performance. We shall now consider the MOSFET structure broken down here into separate parts: channel doping, gate stack, and sourceldrain design. This is followed by some representative device structures for ultimate performance and special purposes. 6.5.1 Channel Doping Profile Figure 32 shows the schematic of a typical high-performance MOSFET structure based on planar technology. The channel doping profile has a peak level slightly below the semiconductor surface. Such a retrograde profile is achieved with ion implantation, often of multiple doses and energies. The low concentration at the surface has the advantages of higher mobility due to reduced normal field and low threshold voltage. The high peak concentration below the surface is to control punchthrough and other short-channel effects. Lower concentration is typically below the junction depth. It reduces the junction capacitance as well as the substrate-bias effect on threshold voltage. Fig. 32 High-performance MOSFET planar structure with a retrograde channel doping profile, two-step source/drain junction, and self-aligned silicide source/drain contact. 340 CHAPTER 6. MOSFETs 6.5.2 Gate Stack The gate stack consists of the gate dielectric and the gate contact material. The gate dielectric has been exclusively SiO, right from the birth of MOSFET. In fact, the ideal Si-SiO, interface is the main factor responsible for the success of MOSFET. As the oxide thickness is scaled into the range below = 2 nm, fundamental problem of tun- neling and technological difficulty of defects start to demand alternatives. A sensible and popular solution that is actively sought after is a material with high dielectric constant, called high-K dielectric. Such a high-K dielectric can have a thicker physical thickness for the same capacitance, thus reducing its electric field and technological problem related to defects. With the value of dielectric constant considered, the common terminology used is the equivalent oxide thickness [EOT = thickness x K(SiO,)/KI. Material options being examined are A1,0,, HfO,, ZrO,, Y203,La203,Ta,O,, and TiO,. The dielectric constants for these materials range from 9 to 30, except for TiO, which is larger than 80. As seen [K(SiO,) = 3.91, the EOT can easily be extended to below 1 nm if some of the options eventually are proven to be successful.Nevertheless, readers are reminded of the quantum-mechanical effect discussed in Section 4.3.6 which puts a limit on the gate capacitance. The gate material has been polysilicon for a long time. The advantages of a poly-Si gate is its compatibility with the silicon processing, and its ability to withstand high-temperature anneal that is required after self-aligned source/drain implantation. Another important factor is that the work function can be varied by doping it into n-type and p-type. Such flexibility is crucial for a symmetric CMOS technology. One limitation of the poly-Si gate is its relatively high resistance. This does not result in penalty of dc characteristics since the gate terminates on the gate insulator. The penalty shows up in high-frequency parameters such as noise andfmax(Section 6.6.1). Another shortcoming of poly-Si gate is the finite depletion width at the oxide interface. This reduces the effective gate capacitance and becomes more severe with thinner oxides. To circumvent the problems of resistance and depletion, gate materials of silicides and metals are obvious choices. Potential candidates are TiN, TaN, W, Mo, and Nisi. 6.5.3 SourceIDrain Design Details of the source/drain structures are shown in Fig. 32. Typically the junction has two sections. The extension near the channel has shallower junction depth to minimize short-channel effects. Sometimes it is doped less heavily to reduce the lateral field for consideration of hot-carrier aging. For this purpose it is called a lightly doped drain (LDD). The deeperjunction depth away from the channel helps to minimize the series resistance. It has been pointed out that the sharpness or gradient of the sourceldrain profile is critical to minimize the series resistance.60 We refer to Fig. 33 to understand its origin. In practice the profile is never perfectly abrupt, and there exists a region of accumulation layer (of n-type) before current spreads into the bulk of the 6.5 MOSFET STRUCTURES 341 _______________-- etallurgical junction Channel Fig. 33 Detailed analysis of different components of parasitic source/drain series resistance. R,, is accumulation-layer resistance due to doping gradient. R, = spreading resistance. R,, = sheet resistance. R,, = contact resistance. (After Ref. 60.) source/drain. This accumulation-layer resistance R,, is related to the transition distance before the doping reaches a critical level. A major milestone for source/drain design is the development of the silicide contact technology which started in the early 1990s.Unlike the metal contact, the silicide can be made self-aligned to the gate, as shown in Fig. 32, thus minimizing the sheet-resistance component (Rshb) etween the contact and the channel. In this way the silicide has become the metal contact because contact resistance between metal and silicide is very small. This self-aligned silicide process has been coined salicide. The salicide process is described is follows. After the gate definition, an insulator spacer is formed on the sides of the gate. A metal layer for silicidation is deposited uniformly, which at this stage is shorting the gate and the source/drain. After a thermal reaction at low temperature (= 450°C), the metal reacts with silicon to form silicide on the sourceldrain region. Silicide formation on the gate is optional depending on whether the gate is capped with an insulation layer as part of the gate stack. Metal over the spacer region and the field region (between transistors, not shown) remains metal since there is no exposed silicon for reaction. The metal is then removed with a selective chemical that etches metal only without etching silicide, thereby removing the shorting paths. Note that the silicide/silicon interface in Fig. 32 is slightly recessed. This is due to the consumption of silicon during silicide formation. Examples for salicides are CoSi,, Nisi,, TiSi,, and PtSi. Schottky-Barrier Source/Drain. Instead of p-n junction, use of Schottky-barrier contacts for the source and drain of a MOSFET can result in some advantages in fabrication and performance. Figure 34a shows a schematic MOSFET structure with such Schottky source and drain.61For a Schottky contact, the junction depth can effectively be made zero to minimize the short-channel effects. n-p-n bipolar-transistor action is also absent for undesirable effects such as bipolar breakdown and 342 CHAPTER 6. MOSFETs Fig. 34 MOSFET with Schottky-barrier source and drain. (a) Cross-sectional view of the device. (b)4d) Band diagrams along semiconductor surface under various biases. latch-up phenomenon62 in CMOS circuits. Eliminating high-temperature implant anneal can promote better quality in the oxides and better control of geometry. In addition, this structure can be made on semiconductors such as CdS where p-n junctions cannot be easily formed. Figures 3 4 b d show the working principle of a Schottky sourceldrain. At thermal equilibrium with VG= V, = 0, the barrier height of the metal to the p-substrate for holes is q&, (e.g., 0.84 eV for an ErSi-Si contact).63When the gate voltage is above threshold to invert the surface from p-type to n-type, the barrier height between the source and the inversion layer (electrons) is q& = 0.28 eV. Note that the source contact is reverse biased under operating conditions (Fig. 34d). For a 0.28-eV barrier, the thermionic-type reverse-saturation current density is of the order of 1O3 A/cm2 at room temperature. To increase current density, metals should be chosen to give the highest majority-carrier barrier such that the minority-carrier barrier height is minimized. Additional current due to tunneling through the barrier should help to improve the supply of channel carriers. At the present, making the structure on ap-type Si substrate for n-channel MOSFET is more difficult compared to p-channel device with n-substrate, because metals and silicides that give large barrier heights on p-type silicon are less common. 2ool150 h q22 100 100- 3. v *P 50 - 5 00 00.5 / V,=I.ZV 6.5 MOSFET STRUCTURES 343 Fig. 35 I-V characteristics of 01.o n-channel MOSFET with Schottky 1.15 source/drain. (After Ref. 63.) The disadvantages of the Schottky sourceldrain are high series resistance due to the finite barrier height, and higher drain leakage current. Typical I-V curves show that current is starved at low-drain bias (Fig. 35). Also note that as shown in Fig. 34, the metal or silicide contact has to extend underneath the gate for continuity. This process is much more demanding than a junction source/drain which is done by selfaligned implantation and diffusion. Raised SourceIDrain. An advanced design is the raised sourceldrain where a heavily doped epitaxial layer is grown over the sourceldrain regions (Fig. 36a). The purpose is to minimize junction depth to control short-channel effects. Note that an extension underneath the spacer is still needed for continuity. An alternative is the recessed-channel MOSFET where the junction depth rj is zero or negative (Fig. 36b).64The drawback of the recessed-channel structure, especially for submicron devices, is the difficulty in controlling the contour and the oxide thickness at the corners where the threshold voltage is determined. Also, oxide charging may be worsened because more hot-carrier injection will occur. 6.5.4 SO1 and Thin-Film Transistor (TFT) SOI. Unlike thin-film transistor, the top silicon layer of an SO1 (silicon-on-insulator) wafer is high-quality single-crystalline material that is suitable for high-performance (a) (b) Fig. 36 Means to reduce source/drainjunction depth and series resistance. (a) Raised source/drain. (b) Recessed channel. 344 CHAPTER 6. MOSFETs and high-density integrated Many forms of SO1 structures have been dem- onstrated with different insulator materials and holding substrates. These include silicon-on-oxide, silicon-on-sapphire (SOS), silicon-on-zirconia (SOZ), and silicon- on-nothing(airgap). In SOS and SOZ technologies, a single-crystalline silicon film is epitaxially grown on a crystalline insulating substrate. In these cases, the insulators are the substrates themselves, A1,0, in SOS and ZrO, in SOZ. The difficulties in these techniques are the material quality when the film gets thinner. The first option, using oxide as an insulator and another Si wafer as the holding substrate, is by far the most popular. There are many ways to fabricate this structure. Among them SIMOX (separation by implantation of oxygen) where high-dose oxygen is implanted onto a silicon wafer followed by high-temperature anneal to form the buried SiO, layer. Another technique involves bonding of two silicon wafers one of which has an oxi- dized layer followed by thinning or removal of the majority of the top wafer until a thin silicon layer is left. One technique uses lateral epitaxial growth of silicon over an oxide layer, starting from a seed opening to the substrate. Another uses laser recrys- tallization, transforming amorphous silicon deposited onto the oxide layer into single-crystalline material, or into poly-crystalline form with large grain size. Figure 37a shows a schematic diagram of an n-channel MOSFET made on an SO1 substrate, with its typical I-Vcharacteristics shown in Fig. 37b. The kinks associated with floating body without a substrate tie are noticeable. The advantages of the SO1 substrate include improved MOSFET scaling due to its thin body. A thin body can alleviate most problem with punch-through such that the channel can be doped lightly. The subthreshold swing is known to be improved. The buried oxide layer serves as good isolation to reduce capacitance to the substrate, giving rise to higher speed. As shown in Fig. 37a, device isolation is much easier, simply by removing the surrounding thin film. This can significantly improve the circuit density. This type of isolation, as opposed to junction isolation in planar tech- nology, also eliminates latch-up phenomenon in CMOS circuits. The disadvantages of SO1 is higher wafer cost, potentially inferior material properties, the kink effect, and worse heat conduction because of the oxide layer. vc = 2.0 v / , , I 1 t 0.5 1.0 1.5 2.0 2.5 Drain voltage V, (V) (b) Fig. 37 (a) Typical structure of MOSFET on SO1 wafer, and (b) its drain characteristics. (After Ref. 66.) 6.5 MOSFET STRUCTURES 345 Thin-Film Transistor (TFT). The thin-film transistor usually refers to MOSFET as opposed to other kinds of transistors. The structure is similar to MOSFET built on SO1 with the exception that the active film is a deposited thin film and that the substrate can be of any form.67Because the semiconductor layer is formed by deposition, the amorphous material has more defects and imperfections than in single-crystalline semiconductors, resulting in more complicated transport processes in the TFT. To improve device performance, reproducibility, and reliability, the bulk and interfacetrap densities must be reduced to reasonable levels. In a TFT, the current is always very limited due to lower mobility, and leakage current is always higher due to defects. The main applications lie in the areas where a large-area or flexible substrate is required and conventional semiconductor processing is not feasible. A good example is large-area display where an array of transistors is required to control the array of lighting elements. In such applications, device performance such as current or speed is not critical. 6.5.5 Three-Dimensional Structures In device scaling, the optimum design is with MOSFET built on a body of ultra-thin layer such that the body is fully depleted under the whole bias range. A design to achieve this more efficiently is to have a surround gate structure that encloses the body layer from at least two sides. Two examples of these 3-dimensional structures are shown in Fig. 38. They can be classified according to their current-flow pattern; the horizontal t r a n ~ i s t o Pan~d ~vertical tran~istor.’W~ hile both of these are very challenging from a fabrication point of view, the horizontal scheme is more compatible with SO1 technology and more data are reported in the literature. A new set of dificulties arise from the fact that the majority or all of the channel surface is on a vertical wall, for both of these structures. This fact presents great challenges in achieving a smooth channel surface from etching and growth or deposition of gate dielectrics on these surfaces. Formation of the source/drain junction is no longer Fig. 38 Schematic 3-dimensional MOSFETs. (a) Horizontal structure. (b) Vertical structure. Note commonality of surround gate and thin body. 346 CHAPTER 6. MOSFETs trivial by means of ion implantation. Salicide formation will also be much more difficult. Whether one of these turns out to be the device choice in the hture remains to be seen. 6.5.6 Power MOSFETs In general, power MOSFETs employ thicker oxides, deeper junctions, and have vT). longer channel lengths. These generally post a penalty on device performance such as transconductance (g,) and speed Nevertheless, power applications from MOSFETs have been on the rise, for example, due to the increasing demand of cellular phones and cellular base stations which require extra-high voltage. We will present two power structures that are designed for RF power applications. DMOS. As the name implies, in the DMOS (double-diffbsed MOS) transistor shown in Fig. 39a the channel length is determined by the higher diffusion rate of the p-dopant (e.g., boron) compared to the n+-dopant (e.g., phosphorus) of the source. This technique can yield very short channels without depending on a lithographic mask. Thep-diffusion serves as channel doping and has good punch-through control. The channel is followed by a lightly doped n--drift region. This drift region is long compared to the channel, and it minimizes the peak electric field in this region by maintaining a uniform field.71Usually the drain is located at the substrate contact. The field near the drain is the same as in the drift region, so avalanche breakdown, multiplication, and oxide charging are lessened compared to conventional MOSFETs. However, the threshold voltage V, is more difficult to control in a DMOS transistor because the channel doping is no longer constant along its length.72Since V , is determined by the local doping concentration along the semiconductor surface, varying doping level leads to variations in V, as a function of distance and bias. Also the localization of punch-through control by a thin p-shield region requires a higher /t P+ Fig. 39 (a) Vertical DMOS transistor and (b) LDMOS transistor. Current path is indicated by dashed line. In LDMOS transistors, it is common to connect the source to the substrate to reduce inductance of the bonding wire. 6.6 CIRCUIT APPLICATIONS 347 doping level compared to a conventional structure and it leads to poorer turn-off behavior for DMOS transistors. LDMOS. The major difference of the LDMOS (laterally diffused MOS) transistor (Fig. 39b) from a DMOS transistor is that it has a lateral current-flow pattern. The drift region here is an implanted horizontal region. Such a horizontal arrangement enables thep+-substrate to deplete this drift region at high drain bias. Yet at low drain bias its higher doping gives lower series resistance. This drift region, thus, behaves as a nonlinear resistor. At low drain bias, its resistance is determined by llnqp. At high drain bias, this region is fdly depleted so a large voltage drop can be supported. This concept is called RESURF (reduced surface field) t e ~ h n o l o g yB. ~ec~ause of this feature, the drift region can be doped with a higher concentration compared to the DMOS transistor for a lower on-resistance. Another advantage of the LDMOS transistor is that the source can be tied internally to the substrate by a deep p-type diffusion. This avoids using a bond wire that has high inductance to the source. The LDMOS transistor can thus perform at higher speed. 6.6 CIRCUIT APPLICATIONS 6.6.1 Equivalent Circuit and Microwave Performance The MOSFET is ideally a transconductance amplifier with an infinite input resistance and a current generator at the output. In practice, however, we have other nonideal circuit elements. An equivalent circuit is shown in Fig. 40 for the common-source connection. The gate resistance R, is associated with the gate contact material over the oxide. The input resistance R, is caused by tunneling current through the thin gate insulator, and it also includes any conductance through defects. This of course is a function of the oxide thickness. For a thermally grown silicon dioxide layer, this leakage current between the gate and the channel is negligibly small; thus, the input resistance is very high, one of the main advantages of a MOSFET. For oxides below Source o RS o Source Fig. 40 Small-signal equivalent circuit of MOSFET for the common-source configuration. uG is the small signal of V, Capacitance symbolswith prime designate total capacitance in Farad as opposed to capacitance per unit area. 348 CHAPTER 6. MOSFETs a thickness of = 5 nm, the tunneling current starts to become an important factor. The gate capacitance Cb (= Cbs + CkD) is mostly due to C,, multiplied by the active channel area ZxL. In practical devices, the gate extends somewhat above the source and drain regions, and these overlap capacitances add to the total Cb . This fringing effect is also an important contribution to the feedback capacitance C b D .The drain output resistance RDs is due to the fact that the drain current does not truly saturate with the drain bias. This effect is especially pronounced for short-channel devices, as part of the short-channel effects discussed earlier. The output capacitance Cbs consists mostly of the two p-n junction capacitances connected in series through the semiconductor bulk. In the saturationregion, VDand thus RD has little effect on the drain saturation current. The Rs affects the effective gate bias, and the extrinsic transconductance is given by In analyzing the microwave performance, we follow the same procedure as in Section 5.3.1 for obtaining the cutoff frequencyf p defined as the frequency for unity current gain (ratio of drain current to gate current), fT = gm -- gm 24‘; + CLar) 2 4 z ~ C o ,+y CLar)’ (111) where Cia. is the total input parasitic capacitance. (See footnote* for a more-completef Texpression with excessive Rs and RD.) It is interesting to note that if Cia!is only due to the gate-drain and gate-source overlap regions, it has the same oxidethickness dependence as gm,andf Twould be independent of C,, or oxide thickness. In the ideal case that there is zero parasitics, it can be shown that gm f T = 2TZLC,, where zr is the transit time across the channel length. Such an ideal case is in practice impossible to achieve, but this equation gives an estimate of the upper limit off T by using u = us.Again, in this limit,f Tis also independent of oxide thickness or gm.However, gmis important in practical devices with parasitics. * In cases of very large source and drain resistances, the more-complete expression is 6.6 CIRCUIT APPLICATIONS 349 Another figure-of-merit for microwave performance is the maximum frequency of oscillationfma,, the frequency at which the unilateral gain becomes unity. It is given by So for high-frequency performance, the most-important device parameters are g,,,, R,, and all other parasitic capacitances. 6.6.2 Basic Circuit Blocks In this section we present the basic digital-circuit building blocks in both logic and memory circuits. The most-basic unit for a logic circuit is the inverter. Different configurations for MOSFET inverters are shown in Fig. 4 1. By far the most common is the CMOS (complementary MOS) inverter where both n-channel andp-channel transistors are used. This logic consumes very low dc power because when the input is either high or low, one of the transistors in series is off so that there is very little steady-state current (subthreshold current) passing through them. In fact, this is one of the main advantages and applications of MOSFETs where the insulated gate can withstand input voltage of any polarity. Such an arrangement is much more dificult with bipolar transistors or MESFETs without putting a large resistor in front of the input. In an NMOS logic (Fig. 41b), the load of thep-channel transistor is replaced with a depletion-mode n-channel transistor. The advantage is a simpler technology since ap-channel device is not required at the expense of higher dc power. This depletion-mode device with the gate tied to the source is basically a two-terminal nonlinear resistor, which is an improvement compared to a simple resistor load shown in Fig. 41c. Two basic MOSFET memory cells, for SRAM (static random-access memory) and DRAM (dynamic random-assess memory) circuits, are shown in Fig. 42. The v,, n-channel - - - - - - (a) (b) (c) Fig. 41 Versions of inverters: (a) CMOS logic. (b) NMOS logic with depletion-mode-tran- sistor load, and (c) NMOS logic with resistor load. 350 CHAPTER 6. MOSFETs p VDD 7 _-L (a) (b) Fig. 42 Basic memory cells in (a) SRAM and (b) DRAM circuits. SRAM cell has two CMOS inverters connected back to back. It is a latch and a stable cell but it requires four transistors (six including controls for word line and bit line). The DRAM cell only requires one transistor and, thus, has very high memory density. Its memory information is stored as a charge across the capacitor. Since there is finite leakage of charge in the nonideal capacitor, the cell needs to be refreshed periodically, typically at a frequency of = 100 Hz. 6.7 NONVOLATILE MEMORY DEVICES Semiconductor memory devices are classified in Fig. 43. The first division is based on their ability to maintain their states when the power is disconnected. As the names imply, a volatile memory loses the content, but a nonvolatile memory does not need voltage to maintain the Semiconductor memory Volatile /\ DRAM \ Nonvolatile (Nore/or limited Rewrite) RAM Mask- PROM EPROM Flash EEPROM programmed EEPROM ROM Fig. 43 Classification of semiconductor memories. 6.7 NONVOLATILE MEMORY DEVICES 351 Before getting into each type of nonvolatile semiconductor memory, we should first clarify the difference between a RAM and a ROM. A RAM (random-access memory) has an x-y address for each cell, which distinguishes it from other serial memories such as magnetic memory. Strictly speaking, a ROM (read-only memory) also has random-access capability since the addressing architecture is similar. In fact the read processes of the RAM and ROM are almost identical. More appropriately, a RAM is sometimes called a read-write memory. However, the nonvolatile ROM has long started to develop some extent of rewriting capability. So the main difference now between a RAM and a ROM is the ease and frequency of erasing and programming. A RAM has almost equal opportunity of rewrite and read. A ROM in general has much more frequent read than rewrite. It itself has a spectrum of rewriting capability, ranging from a pure ROM without any writing capability to a full-feature EEPROM. Because a ROM is smaller in size and more cost-effective than a RAM, it is used whenever frequent rewriting is not required. With this background, different types of nonvolatile memories are explained below: Mask-programmed ROM: The memory content is fixed by the manufacturer and is not programmable once it is fabricated. Sometimes mask-programmed ROM is simply referred to as ROM. PROM: Programmable ROM is sometimes called field-programmable ROM or fusible-link ROM. The connectivity of the array is custom programmed using the technique of fusing or antifusing. After programming, the memory works as a ROM. EPROM: In an electrically programmable ROM, programming is performed by hot-electron injection or tunneling to the floating gate, and it requires biases on both the drain and the control gate. Global erase is by exposure to a UV light or x-ray. Selective erase is not possible. Flash EEPROM: A flash EEPROM, as opposed to a full-feature EEPROM below, can be erased electrically but only by a large block of cells simultaneously. It loses byte selectivity but maintains a one-transistor cell. It is, thus, a compromise between an EPROM and a full-feature EEPROM. EEPROM: In an electrically erasable/programmable ROM, not only can it be erased electrically, but also selectively by byte address. To erase selectively, a select transistor is needed for each cell, leading to a two-transistor cell. This makes it less popular than a flash EEPROM. Nonvolatile RAM: This memory can be viewed as a nonvolatile SRAM, or EEPROM with short programming time as well as high endurance. If technology allows the aforementioned features, this would be the ideal memory. When the gate electrode of a conventional MOSFET is modified so that semipermanent charge storage inside the gate stack is possible, the new structure becomes a nonvolatile memory device. Since the first nonvolatile memory device proposed by Kahng and Sze in 1967,77various device structures have been made, and nonvolatile memory devices have been extensively used in commercial products. The two groups of nonvolatile memory devices are the floating-gate devices and the charge-trapping devices (Fig. 44). In both types of devices, charges are injected from the silicon substrate across the first insulator and stored in the floating gate or at the nitride-oxide 352 CHAPTER 6. MOSFETs (c) (4 Fig. 44 Variations of nonvolatile memory devices:Floating-gate devices as (a) FAMOS tran- sistor and (b) stacked-gatetransistor. Charge-trapping devices as (c) MNOS transistor and (d) SONOS transistor. interface. The stored charge gives rise to a threshold-voltage shift, and the device is at a high-threshold state (programmed). For a well-designed memory device, the charge retention time can be over 100 years. To return to the low-threshold state (erased), a gate voltage or other means (such as ultraviolet light) can be applied to erase the stored charge. 6.7.1 Floating-Gate Devices In a floating-gate memory device, charge is injected to the floating gate to change the threshold voltage. The two modes of programming are hot-carrier injection and Fowler-Nordheim tunneling. Figure 45a shows the mechanisms of hot-carrier injection. Near the drain, the lateral field is at its highest level. The channel carriers (electrons) acquire energy from the field and become hot carriers. When their energy is higher than the barrier of the Si/SiO, interface, they can be injected to the floating gate. At the same time, the high field also induces impact ionization. These generated secondary hot electrons can also be injected to the floating gate. The hot-carrier injection currents give rise to the equivalence of gate current in a regular MOSFET, and is shown in Fig. 31. This gate current peaks at V,, = VDwhere VFGis the potential of the floating gate. Figure 45b shows the original method of hot-carrier injection using drain-sub- strate avalanche. In this scheme, the floating-gate potential is more negative such that hot holes are injected instead.* This injection scheme is found to be less efficient and is no longer used in practice. 6.7 NONVOLATILE MEMORY DEVICES 353 (a) (b) Fig. 45 Charging of the floating gate by hot carriers. (a) Hot electrons from channel and impact ionization. (b) Hot holes from drain avalanche. Note difference in gate bias between the two figures. Besides hot-carrier injection, electrons can be injected by tunneling. In this programming mode, the electric field across the bottom oxide layer is most critical. On application of a positive voltage V, to the control gate, an electric field is established in each of the two insulators (Fig. 44b). We have, from Gauss' law, that g1= ~~g~+ Q (114) and V G = V1+ V2 = d i g , + d 2 8 2 , (115) where the subscripts 1 and 2 correspond to the bottom and top oxide layer respectively, and Q (negative) is the stored charge on the floating gate. From Eqs. 1 1 4 115 we obtain The current transport in insulators is generally a strong function of the electric field. When the transport is Fowler-Nordheim tunneling, the current density has the form J = C4g?exp(%-')g where C, and goare constants in terms of effective mass and barrier height. This type of current transport occurs in SiO, and A120, as discussed in Chapters 4 and 8. * The original devices werep-channel such that hot electrons are injected under this scheme which are relatively more efficient than hot holes. We use the same n-channel for better comparison. 354 CHAPTER 6. MOSFETs Using either hot-carrier injection or tunneling as programming mechanism, after charging, the total stored charge Q is equal to the integrated injection current since the gate is floating. This causes a shift of the threshold voltage by the amount This threshold-voltage shift can be directly measured as shown in the ID-VG plot (Fig. 46). Alternately, the threshold-voltage shift can be measured from the drain conductance. The change in V , results in a change in the channel conductance &, of the MOSFET. For small drain voltages, the channel conductance of an n-channel MOSFET is given by (119) After altering the charge on the floating gate by Q (negative charge), the go-VG plot shifts to the right by AV, To erase the stored charge, a negative bias is put on the control gate or a positive bias on the sourceldrain. The process is the reverse of the tunneling process described above, and the stored electrons tunnel out of the floating gate to the substrate. The programming and erasing sequence of a floating-gate memory can be understood with the energy-band diagrams in Fig. 47. In Fig. 47b, electron injection can be due to hot carriers over the barrier or tunneling through the barrier. Figure 47c shows that the accumulated negative charge at the floating gate raises the threshold voltage compared to its initial condition in Fig. 47a. The erase is carried out by electron tunneling from the floating gate back to the substrate (Fig. 47d). In both programming and erasing operations, it is important to modulate the floating-gate potential efficiently by the control-gate applied voltage. An important parameter in the floating-gate memory is the coupling ratio which determines the portion of the control-gate voltage that gets coupled to the floating gate capacitively. This coupling ratio is determined by the capacitance ratio Fig. 46 Drain-current characteristics of a stacked-gate n-channel memory transistor, showing the change of threshold voltage after erasing and Fig. 47 Energy-band diagrams for a stacked-gate memory transistor at different stages of operation. (a) Initial stage. (b) Charging by hot electrons or electron tunneling. (c) After charging, the floating-gate having charge Q (negative) is at higher potential and V , is increased. (d) Erasing by electron tunneling. 5 4 h L d- 3 2 10.01 0.1 1 10 Program time (ps) Fig. 48 Programming of floating- gate memory using hot-electron injec- 1 tion. (After Ref. 80.) 355 356 CHAPTER 6. MOSFETs where C; and C; are the capacitances associated with the bottom and top insulator layers, respectively. Note that in practice, the areas of the control gate and the floating gate are not necessarily the same. More often than not, the top control gate wraps around the floating gate so the top capacitor has a larger area, unlike that shown in Figs. 44 and 45. The parameters C; and C; represent their total net capacitances. The floating-gate potential is given by VFG= RCGVG. (121) In practical devices, the bottom layer has a tunnel oxide of = 80 A, while the top insulator stack typically has an equivalent oxide thickness of = 140 A. A larger top area makes up for the difference in capacitance per unit area, and the coupling ratio is typ- ically around 0.5-0.6. In device structure, the first EPROM was developed using a heavily doped poly- silicon as the floating-gate material (Fig. 44a). The device uses drain-substrate ava- lanche shown in Fig. 45b and is known as floating-gate avalanche-injection MOS (FAMOS) memory.78The polysilicon gate is embedded in oxide and is completely isolated. To inject charge into the floating gate (that is, to program), the drain junction is biased to avalanche breakdown, and holes in the avalanche plasma are injected from the drain region into the floating gate (*see footnote on p. 353). To erase the FAMOS memory, ultraviolet light or x-ray is used. Electrical erasing cannot be used because the device has no external gate. To enable electrical erase, the stacked-gate structure with double-level polysilicon gates has been in popular use (Fig. 44b).79The external control gate makes electrical erasing possible and also improves the programming efficiency. An example of the programming transient based on hot-carrier injection is shown in Fig. 48. In EEPROM circuits, it is more common to use tunneling as an injection mecha- nism for programming. A successful commercial device, called FLOTOX (floating- gate tunnel oxide) transistor, confines the tunneling process to a small area over the drain, as shown in Fig. 49. Typical programming and erasing transients for the FLOTOX transistors are shown n Fig. 50. After programming, by definition, a long retention time is required for nonvolatile memory operation. The retention time is defined as the time when the stored charge decreases to 50% of its initial value and is expressed by Fig. 49 Structure of the FLOTOX transistor which uses tunneling for both programming and erasing. (After Ref. 81.) 6.7 NONVOLATILE MEMORY DEVICES 357 8 Vc= 15 V 6 4 >h v 22 0 -T' I 1 I I I I j 10-5 10-4 i t 3 10-2 10-1 100 1 Program time (s) (a) Fig. 50 Typical programming and erasing times for FLOTOX memory device. (After Ref. 76.) where v is the dielectric relaxation frequency, and $B is the barrier height of the floating gate to oxide. The retention time is very sensitive to temperature. Typical retention times at 125°C and 170°C with $B = 1.7 V are found to be about 100 years and 1 year respectively.82 6.7.2 Charge-Trapping Devices MNOS Transistor. As a memory device, in the MNOS (metal-nitride-oxide-silicon) transistor, the silicon-nitride layer is used as an efficient material to trap electrons as current passes through the d i e l e ~ t r i cO. ~th~er insulators in place of the silicon-nitride film such as aluminum oxide, tantalum oxide, and titanium oxide have been used but are not as common. Electrons are trapped in the nitride layer close to the oxide-nitride interface. The function of the oxide is to provide a good interface to the semiconductor and to prevent back-tunneling of the injected charge for better charge retention. Its thickness has to be balanced between retention time and programming voltage and time. Figure 5 1 shows the basic band diagrams for the programming and erasing operations. In the programming process, a large positive bias is applied to the gate. Current conduction is known to be due to electrons that are emitted from the substrate to the gate. The conduction mechanisms in the two dielectric layers are very different and have to be considered in series. The current through the oxide J,, is by tunneling. Notice that electrons tunnel through the trapezoidal oxide barrier, followed by a triangular barrier in the nitride. This form of tunneling has been identified as modified 358 CHAPTER 6. MOSFETs Oxide _Gate ~= Nitride Si I= j-1Oxide F t e Nitride Si (a) (b) Fig. 51 Rewriting of MNOS memory. (a) Programming: electrons tunnel through oxide and are trapped in the nitride. (b) Erasing: holes tunnel through oxide to neutralize the trapped electrons, and tunneling of trapped electrons. Fowler-Nordheim tunneling, as opposed to Fowler-Nordheim tunneling through a single triangular barrier. It has the following form of where go,is the field in the oxide layer, and C, and C, are constants. The current through the nitride layer J, is controlled by Frenkel-Poole transport, which has the form where Z’, and E, are the electric field and permittivity in nitride, +E is the trap level below the conduction band (= 1.3 V), and C, is a constant [= 3x 10” ( Q - C ~ ) - ~ ] . It is known that at the beginning of the programming process, modified FowlerNordheim tunneling is capable of a higher current, and current conduction is limited by Frenkel-Poole transport through the nitride layer. When the negative charge starts to build up, the oxide field decreases and the modified Fowler-Nordheim tunneling starts to limit the current. The threshold voltage as a hnction of programming pulse width is shown in Fig. 52. Initially, the threshold voltage changes linearly with time, followed by a logarithmic dependence, and finally it tends to saturate. This programming speed is largely affected by the choice of oxide thickness; a thinner oxide allows 6.7 NONVOLATILE MEMORY DEVICES 359 cI -2 \ Erasing \ Fig. 52 Typical programming and erasing rates for MNOS transistor. 0 (After Ref. 83.) a shorter programming time. Programming speed has to be balanced with charge retention since too thin an oxide will allow the trapped charge to tunnel back to the silicon substrate. The total gate capacitance CGof the dual dielectrics is equal to the serial combination of their capacitances where the capacitances Cox= ~ o x / d oanxd C,, = &,,Idncorrespond to the oxide and nitride layers respectively. The amount of trapped charge density Q near the nitrideoxide interface depends on the trapping efficiency of the nitride and is proportional to the integrated Frenkel-Poole current having passed through it. The final thresholdvoltage shift is given by AVT=-Q. Cn (126) In the erasing process, a large negative bias is applied to the gate (Fig. 5 1b). Traditionally, the discharge process is believed due to the tunneling of trapped electrons back to the silicon substrate. New evidence shows that the major process is due to tun- neling of holes from the substrate to neutralize the trapped electrons. The discharge process as a function of pulse width is also shown in Fig. 52. The advantages of the MNOS transistor include reasonable speed for programming and erasing, so it is a candidate as a nonvolatile RAM device. It also has superior radiation hardness, due to minimal oxide thickness and the absence of a floating gate. The drawbacks of the MNOS transistor are large programming and erasing voltages and nonuniform threshold voltage from device to device. The passage of tun- neling current gradually increases the interface-trap density at the semiconductor surface and also causes a loss of trapping efficiency due to leakage or tunneling of trapped electrons back to the substrate. These result in a narrowing threshold voltage 360 CHAPTER 6. MOSFETs window after many cycles of programming and erasing. The major reliability problem of the MNOS transistor is the continuous loss of charge through the thin oxide. It should be pointed out that unlike a floating-gate structure, the programming current has to pass through the entire channel region, so that the trapped charge is distributed uniformly throughout the channel. In a floating-gate transistor, the charge injected to the floating gate can redistribute itself within the gate material, and injection can take place locally anywhere along the channel. SONOS Transistor. The SONOS (silicon-oxide-nitride-oxide-silicon) transistor (Fig. 44d) is sometimes called the MONOS (metal-oxide-nitride-oxide-silicon) transistor. It is similar to an h4NOS transistor except that it has an additional blocking oxide layer placed between the gate and the nitride layer, forming an ON0 (oxidenitride-oxide) stack. This top oxide layer is usually similar in thickness to the bottom oxide layer. The function of the blocking oxide is to prevent electron injection from the metal to the nitride layer during erase operation. As a result, a thinner nitride layer can be used, leading to lower programming voltage as well as better charge retention. The SONOS transistor now replaces the older MNOS configuration, but the operation principle remains the same. 6.8 SINGLE-ELECTRONTRANSISTOR With the continuing advancement of technology to nano-scale device geometry,there are new experimental observations that have not been possible before. One of them is the charge-quantizationeffect in a single-electron transistor (SET),s4first observed in 1987.85The structure of an SET is represented by the schematic circuit diagram in Fig. 53a. It has a central single-electron island that has to be extremely small. The island is connected between the source and drain via capacitors through which tunneling occurs to conduct current. The third terminal is the insulated gate and its purpose is to control the current between the source and drain, similar to the case of an FET. The opportunity to observe quantization of charge comes directly from the small dimension of the single-electron island. The minimum energy needed to transport a Source Single-electron island Drain Single-electron island - _. VG (4 (b) (c) Fig. 53 Circuit representations of (a) single-electron transistor, (b) charging a tunneling capacitor, and (c) single-electron box. 6.8 SINGLE-ELECTRON TRANSISTOR 361 single electron charge to and from the island is q2/2C,, where C, is its total capacitance, C, = Cs+CD+CG. (127) This energy also must be much larger than the thermal energy for experimental observation, requiring that 42 > 100kT. 2c, At room temperature, C, needs to be on the order of aF (lo-'* F). This necessitates a single-electron island size less than 1-2 nm. It is also interesting to note that this effect does not require the island to be made of semiconductor materials and most reported results are based on metal dots. Although for the limit of small islands such as quantum dots made out of semiconductors, since the total number of electrons within the dots (< 100)is much less than that in metal (=lo7),a second effect of quantization of energy levels can also be observed. This causes addition structures in the -,Z V, characteristics,s6 but does not contribute to the most-important features of an SET and will not be discussed here. As a matter of fact, the SET does not require any semiconductor material, but only needs metal and insulator. The capacitors between the island and the source or drain are characterized by the tunneling resistances R , and R,. These resistances need to be small (thin insulator layers) to conduct a reasonable amount of current. But they are bound in the lower limit by the Uncertainty principle that electrons have to be treated as particles being clearly on either side of the junction. This requires that (h1q2= 25.8 k a ) and they should be above N 1 Mi2 The basic I-Vcharacteristics of an SET are shown in Fig. 54. First, Fig. 54a shows that at most values of V,, there is a knee V, below which current is very much suppressed. This threshold drain voltage, caused by Coulomb blockade, is explained later. Another important feature is that this Coulomb blockade can be varied by the gate voltage. At some values of V,, the Coulomb blockade totally vanishes. Shown in Fig. 54b, the cycle can be repeated many times and is called a Coulomb-blockade oscillation. This is very different from the gate control of a regular transistor, where the current can be turned on or off monotonically. To explain these characteristics, it is best to go back to the simplest structure: a tunneling capacitor as shown in Fig. 53b. Here the capacitor is charged by a small 5 current source, so the junction voltage will increase until an electron can tunnel. VJ The basis for the Coulomb blockade is that it requires a certain minimum before there is enough energy for an electron to tunnel. The minimum energy needed is q2/2C,,which will be the change of energy of the capacitor when an electron tunnels. This is also the same as the energy gained by the electron when tunneling across the 5, capacitor of voltage giving 362 CHAPTER 6. MOSFETs ID Fig. 54 (a) I-V characteristics of SET for various VG.The Coulomb-blockade voltage can be varied by VG.(b) Drain current (logarithmic scale) as a function of VGfor various V,. Note that VGis shifted by V,. 2 29c-j = q v , . 6 So has to reach q12cJ before an electron can tunnel. This threshold voltage is the basis for the Coulomb blockade. Alternatively, one can get the same answer by considering the charging energy (Ech)for transferring Ni number of electrons, VJ where Q, is the original charge before tunneling and is equal to Cl ' The criterion for switching to a different state is that Echhas to be negative and at minimum. Next, we consider a single-electron box where an island is placed between two capacitors, the same as the situation when the source and drain of an SET is tied together (Fig. 53c). As the gate voltage is increased, the island voltage (VI)is also increased accordingly, although scaled down by a factor of CG/C,. Similar to the case above, as soon as the tunneling junction gets above a voltage of q/2C,, one electron starts to tunnel across it. Once an electron has tunneled to the center island, its potential drops by q/C,. Figure 55 shows the charging of the center island and its potential as a function of the gate voltage. It can be seen that the gate voltage at which multiple values of Ni can coexist is at This condition implies degeneracy: multiple Ni can exist without a change of energy, and one electron can tunnel freely to and from the island. One can imagine that for an 6.8 SINGLE-ELECTRON TRANSISTOR 363 Fig. 55 Charging of single-electron box as a function of V, (in q/C,), and the corresponding island voltage V,. SET, if a small bias is applied to the drain, electrons can tunnel from the source to the island freely and subsequently from the island to the drain. This corresponds to the condition of Vcwhere the Coulomb blockade disappears in an SET. Alternatively, one can derive Eq. 132 by considering the charging energy of a single-electron box, By equating Ech(Ni+ 1) = Ech(Ni)t,he condition of Eq. 132 can be reached. Another approach to understand this is to plot Echvs. charge (Niq)for different VG,as shown in Fig. 56. Remembering that Ni takes on only integer values, there are only certain values of V, where the E,, minimum takes on two values of Ni,a condition of degeneracy. This means that the system can switch between these two states easily without any energy barrier. We can now return to the SET and explain the two most-important phenomena: the Coulomb blockade and its voltage, and the Coulomb-blockade oscillations. For current to conduct from the source to drain, there are two junctions that electrons have -101234 N, Fig. 56 Ech vs. Nifor different V , to determine N , in single-electron box. It can be seen that depending on V,, the E,, minimum falls on either single or double values of Ni. 364 CHAPTER 6. MOSFETs - - * - - Source island Drain 1. A -2c1x wb\ '\ 2 0 to tunnel through, but there is only one junction that controls the current flow. Using the energy-band diagrams of Fig. 57, if the bottleneck is at the junction between the source and the single-electron island, an electron will start to tunnel if that junction voltage exceeds 4/2C,, corresponding to the criterion of giving a minimum value of V, or This blockade voltage as a function of V, is shown in Fig. 58 as the line with a negative slope of Fig. 58 Coulomb-blockade voltage VCbas a function of VGforming the Coulomb-blockade diamonds. 6.8 SINGLE-ELECTRON TRANSISTOR 365 Conversely, if the tunneling process is initiated by the island-drain junction, electrons start to flow if giving another expression of with a positive slope dVCb - ‘G dVG C,+ Cs (139) Note that since the current contours follow closely the shape of the Coulombblockade diamonds,87an SET has both positive and negative transconductance, depending on the V, range. This is a unique feature that is different from a regular transistor. From the two lines of Eqs. 135 and 138, an intercept of q/C, can be obtained which is the maximum Vcb. Alternatively, the Coulomb-blockade voltage can be obtained by setting the charging energy negative, either for the island-source junction or the island-drain junction as the current-limiting junction: These equations lead to the same conclusions as Eqs. 135 and 138, respectively. Above and below VCb,the current of an SET has been found to be described ade- quately by the orthodox theory,88which states that the tunneling rate is given by T= AEch q2RT1[ - eXp(-AEch/kT)] ’ (142) where RT is the total of (RTs+ R,) and M c h is the change of charging energy for dif- ferent N, states. One of the drawbacks of the SET is that besides V,, the drain has substantial control of the current as well. As shown in Fig. 54b, a drain bias causes a shift of V, by the amount 88 Within the Coulomb-blockade regime, the V, swing needed to change the current by one order of magnitude is calculated to be 366 CHAPTER 6. MOSFETs A V G = ( l n 1 0c)G( q2 q ‘ (144) Similarly, the V, swing needed for the same change is given by AVD=(lnlO)(-q2.k 4 (145) So to have a transistor that has more gate control than drain control requires that the ratio CGIC, be larger than 0.5. For application, the SET can perform logic. Since it can possess both positive and negative transconductance, a complementary type of logic can be employed using only one type of device, operated at different regimes. However, the small current and transconductance due to the tunneling nature limits its practicality in real circuits with parasitics. Another problem associated with SETSis the extreme sensitivity to parasitic charge surrounding the single-electron island, which is difficult to control. One potential application of the SET is nonvolatile memory, whose structure is shown in Fig. 44b except that the floating gate is miniaturized to a single-electron island. (More accurately, this memory cell employs a single-electron box or single-electron charging, but does not contain an SET.) A small number of electrons is stored or emptied in the single-electron island to control the threshold voltage of the MOSFET. The advantage is that since the charge in the floating-gate island is small and discrete, the signal of threshold voltage is quantized and the memory has multiple values. REFERENCES 1. J. E. Lilienfeld, “Method and Apparatus for Controlling Electric Currents,” U.S. Patent 1,745,175.Filed 1926. Granted 1930. 2. J. E. Lilienfeld, “Amplifier for Electric Currents,” US. Patent 1,877,140. Filed 1928. Granted 1932. 3. J. E. Lilienfeld, “Device for Controlling Electric Current,” U S . Patent 1,900,018.Filed 1928. Granted 1933. 4. 0. Heil, “Improvements in or Relating to Electrical Amplifiers and other Control Arrangements and Devices,” British Patent 439,457. Filed and granted 1935. 5 . W. Shockley and G. L. Pearson, “Modulationof Conductanceof Thin Films of Semiconductors by SurfaceCharges,”Phys. Rev.,74,232 (1948). 6. J. R. Ligenza and W. G. Spitzer, “The Mechanisms for Silicon Oxidation in Steam and Oxygen,” J. Phys. Chem. Solids, 14, 131 (1960). 7. M. M. Atalla. “Semiconductor Devices Having Dielectric Coatings,” U.S. Patent 3,206,670. Filed 1960. Granted 1965. 8. D. Kahng and M. M. Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” IRE-AIEE Solid-state Device Res. ConJ, (Carnegie Inst. of Tech., Pittsburgh, PA), 1960. 9. D. Kahng, “A HistoricalPerspectiveon the Development of MOS Transistorsand Related Devices,” ZEEE Trans. Electron Dev., ED-23,655 (1976). REFERENCES 367 10. C. T. Sah, “Evolution of the MOS Transistor-From Conception to VLSI,” Proc. IEEE, 76, 1280 (1988). 11. H. K. J. Ihantola and J. L. Moll, “Design Theory of a Surface Field-Effect Transistor,” Solid-state Electron., 7,423 (1964). 12. C. T. Sah, “Characteristics of the Metal-Oxide-Semiconductor Transistors,” IEEE Trans. Electron Dev., ED-11, 324 (1964). 13. S. R. Hofstein and F. P. Heiman, “The Silicon Insulated-Gate Field-Effect Transistor,” Proc. IEEE, 51, 1190(1963). 14. J. R. Brews, “Physics of the MOS Transistor,” in D. Kahng, Ed., Applied Solid State Science, Suppl. 2A, Academic, New York, 1981. 15. Y. Tsividis, Operation and Modeling ofthe MOS Transistor, 2nd Ed., Oxford University Press, Oxford, 1999. 16. Y. Taur and T. H. Ning, Fundamentals of Modern VLSIDevices, Cambridge University Press, Cambridge, 1998. 17. R. M. Warner, Jr. and B. L. Grung, MOSFET Theory andDesign, Oxford University Press, Oxford, 1999. 18. L. L. Chang and H. N. Yu, “The Germanium Insulated-Gate Field-Effect Transistor (FET),” Proc. IEEE, 53,316 (1965). 19. P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H. J. L. Gossmann, M. Frei, S. N. G. Chu, J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, “GaAs MOSFET with Oxide Gate Dielectric Grown by Atomic Layer Deposition,” IEEE Electron Dev. Lett., EDL-24, 209, (2003). 20. H. C. Pao and C. T. Sah, “Effects of Difision Current on Characteristics of Metal-Oxide (Insulator)-Semiconductor Transistors (MOST),” IEEE Trans. Electron Dev., ED-12, 139 (1965). 21. A. S. Grove and D. J. Fitzgerald, “Surface Effects on p-n Junctions: Characteristics of Surface Space-Charge Regions under Nonequilibrium Conditions,” Solid-state Electron., 9, 783 (1966). 22. J. R. Brews, “A Charge-Sheet Model of the MOSFET,” Solid-state Electron., 21, 345 (1 978). 23. D. M. Caughey and R. E. Thomas, “Carrier Mobilities in Silicon Empirically Related to Doping and Field,” Proc. IEEE, 55,2 192 (1967). 24. K. Natori, “Ballistic Metal-Oxide-Semiconductor Field Effect Transistor,” J. Appl. Phys., 76,4879 (1994). 25. K. Natori, “Scaling Limit of the MOS Transistor-A Ballistic MOSFET,” / E K E Trans. Electron., E84-C, 1029 (2001). 26. M. Lundstrom, “Elementary Scattering Theory of the Si MOSFET,” IEEE Electron Dev. Lett., EDL-18, 361 (1997). 27. F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. Lundstrom, “On the Performance Limits for Si MOSFET’s: A Theoretical Study,” IEEE Trans. Electron Dev., ED-47, 232 (2000). 28. M. Lundstrom, “Essential Physics of Carrier Transport in Nanoscale MOSFETs,” IEEE Trans. Electron Dev., ED-49, 133 (2002). 29. M. B. Barron, “Low Level Currents in Insulated Gate Field Effect Transistors,” Solid-state Electron., 15,293 (1972). 368 CHAPTER 6. MOSFETs 30. W. M. Gosney, “Subthreshold Drain Leakage Current in MOS Field-Effect Transistors,” ZEEE Trans. Electron Dev., ED-19,2 13 (1972). 31. G W. Taylor, “Subthreshold Conduction in MOSFET’s,” ZEEE Trans. Electron Dev., ED-25,337 (1978). 32. A. G. Sabnis and J. T. Clemens, “Characterization of the Electron Mobility in the Inverted (100) Si Surface,” Tech. Dig. IEEE IEDM, p.18, 1979. 33. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the Universality of Inversion Layer Mobility in Si MOSFET’s: Part I-Effects of Substrate Impurity Concentration,” IEEE Trans. Electron Dev., ED-41,2357 (1994). 34. J. A. Cooper, Jr. and D. F. Nelson, “High-Field Drift Velocity of Electrons at the Si-SiO, Interface as Determined by a Time-of-Flight Technique,”J. Appl. Phys., 54, 1445 (1983). 35. L. Vadasz and A. S. Grove, “Temperature Dependence of MOS Transistor Characteristics Below Saturation,”ZEEE Trans. Electron Dev., ED-13, 863 (1966). 36. F. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very Small MOSFET’s for Low-Temperature Operation,” IEEE Trans. Electron Dev., ED-24,218 (1977). 37. G Merckel, “Ion Implanted MOS Transistors-Depletion Mode Devices,” in F. Van de Wiele, W. L. Engle, and P. G. Jespers, Eds., Process and Device Modelingfor IC Design, Noordhoff, Leyden, 1977. 38. J. S. T. Huang and G. W. Taylor, “Modeling of an Ion-Implanted Silicon-Gate DepletionMode IGFET,” IEEE Trans. Electron Dev., ED-22,995 (1975). 39. T. E. Hendrikson, “A Simplified Model for Subpinchoff Condition in Depletion Mode IGFET’s,”IEEE Trans. Electron Dev., ED-25,435 (1978). 40. M. J. van der To1 and S. G. Chamberlain, “Potential and Electron Distribution Model for the Buried-ChannelMOSFET,” IEEE Trans. Electron Dev., ED-36,670 (1989). 41. R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassons, and A. R. LeBlanc, “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” ZEEE J. Solid State Circuits, SC-9,256 (1974). 42. P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The Impact of Scaling Laws on the Choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Dev. Lett., EDL-l,220 (1980). 43. J. Meindl, “Circuit Scaling Limits for Ultra Large Scale Integration,” Digest Znt. SolidState Circuits Conf,36, Feb. 1981. 44. G. Baccarani, M. R. Wordeman, and R. H. Dennard, “Generalized Scaling Theory and its Application to a 1/4 Micrometer MOSFET Design,” IEEE Trans. Electron Dev., ED-31, 452 (1984). 45. J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized Guide for MOSFET Miniaturization,”IEEE Electron Dev. Lett., EDL-1,2 (1980). 46. K. K. Ng, S. A. Eshraghi, and T. D. Stanik, “An Improved Generalized Guide for MOSFET Scaling,” ZEEE Trans. Electron Dev., ED-40, 1895 (1993). 47. L. D. Yau, “A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET’s,” Solid-state Electron., 17, 1059 (1974). 48. W. Fichtner and H. W. Potzl, “MOS Modeling by Analytical Approximations. I. Subthreshold Current and Threshold Voltage,” Znt. J. Electron., 46,33 (1979). REFERENCES 369 49. Y. Taur, G. J. Hu, R. H. Dennard, L. M. Terman, C. Y. Ting, and K. E. Petrillo, “A SelfAligned 1 pm Channel CMOS Technology with Retrograde n-well and Thin Epitaxy,” IEEE Trans. Electron Dev., ED-32,203 (1985). 50. W. Fichtner, “Scaling Calculation for MOSFET’s,” IEEE Solid State Circuits and Technology Workshopon Scaling and Microlithography, New York, Apr. 22, 1980. 51. K. K. Ng and G. W. Taylor, “Effects of Hot-Carrier Trapping in n- and p-Channel MOSFET’s,” IEEE Trans. Electron Dev, ED-30,87 1 ( 1 983). 52. T. H. Ning, C. M. Osburn, and H. N. Yu, “Effect of Electron Trapping on IGFET Characteristics,” J. Electron. Muter., 6, 65 (1 977). 53. E. H. Nicollian and C. N. Berglund, “Avalanche Injection of Electrons into Insulating SiO, Using MOS Structures,”J. Appl. Phys., 41, 3052 (1970). 54. T. Kamata, K. Tanabashi, and K. Kobayashi, “Substrate Current Due to Impact Ionization in MOSFET,” Jpn. J. Appl. Phys., 15, 1127 (1976). 55. E. Sun, J. Moll, J. Berger, and B. Alders, “Breakdown Mechanism in Short-Channel MOS Transistors,” Tech. Dig. IEEE IEDM, p. 478, 1978. 56. T. Y. Chan, A. T. Wu, P. K. KO,and C. Hu, “Effects of the Gate-to-DrainiSource Overlap on MOSFET Characteristics,” IEEE Electron Dev. Lett., EDL-8, 326 (1987). 57. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” Proc. IEEE, 89, 259 (2001). 58. B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, M. Lin, “15nm Gate Length Planar CMOS Transistor,” Tech. Dig. IEEE IEDM, p.937, 2001. 59. A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, et al., “14 nm Gate Length CMOSFETs Utilizing Low Thermal Budget Process with Poly-SiGe and Ni Salicide,” Tech.Dig. IEEE IEDM, p.639, 2002. 60. K. K. Ng and W. T. Lynch, “Analysis of the Gate-Voltage-Dependent Series Resistance of MOSFETs,” IEEE Trans. Electron Dev., ED-33,965 (1986). 61. M. P. Lepselter and S. M. Sze, “SB-IGFET: An Insulated-Gate Field-Effect Transistor Using Schottky Barrier Contacts as Source and Drain,” Proc. IEEE, 56, 1088 (1968). 62. R. R. Troutman, Latchup in CMOS Technology: The Problem and its Cure, Kluwer, Norwell, Massachusetts, 1986. 63. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. J. King, and C. Hu, “Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20nm Gate Length Regime,” Tech. Dig. IEEE IEDM, p.57,2000. 64. S. Nishimatsu, Y. Kawamoto, H. Masuda, R. Hori, and 0. Minato, “Grooved Gate MOSFET,”Jpn. J. Appl. Phys., 16; Suppl. 16-1, 179 (1977). 65. G. K. Celler and S. Cristoloveanu, “Frontiers of Silicon-on-Insulator,”J. Appl. Phys., 93, 1 (2003). 66. K. A. Jenkins, J. Y. C. Sun, and J. Gautier, “History Dependence of Output Characteristics of Silicon-on-Insulator (SOI) MOSFET’s,” IEEE Electron Dev. Lett., EDL-17,7 (1996). 67. C. R. Kagan and P. Andry, Eds., Thin-Film Transistors, Marcel Dekker, New York, 2003. 68. D. Hisamoto, T. Kaga, and E. Takeda, “Impact of the Vertical ‘DELTA’ Structure on Planar Device Technology,” IEEE Trans. Electron Dev., ED-38, 1399 (1991). 370 CHAPTER 6. MOSFETs 69. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE Electron Dev. Lett., EDL-24,263 (2003). 70. J. M. Hergenrother, G. D. Wilk, T. Nigam, F. P. Klemens, D. Monroe, P. J. Silverman, T. W. Sorsch, B. Busch, M. L. Green, M. R. Baker, et. al., “50 nm Vertical Replacement-Gate (VRG) nMOSFETs with ALD HfO, and A1,0, Gate Dielectrics,” Tech.Dig. IEEE IEDM, p.51,2001. 71. T. Masuhara and R. S. Muller, “Analytical Technique for the Design of DMOS Transistors,”Jpn. J. Appl. Phys., 16, 173 (1976). 72. M. D. Pocha, A. G. Gonzalez, and R. W. Dutton, “Threshold Voltage Controllability in Double-Diffused MOS Transistors,” IEEE Trans. Electron Dev., ED-21,778 (1 974). 73. A. W. Ludikhuize, “A Review of RESURF Technology,” Proc. 12th Int. Symp. Power Semiconductor Devices & ICs, p.1 I , 2000. 74. P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds., Flash Memories, Kluwer, Nonvell, Massachusetts, 1999. 75. C. Hu, Ed., Nonvolatile Semiconductor Memories: Technologies, Design, and Applications, IEEE Press, Piscataway, New Jersey, 1991. 76. W. D. Brown and J. E. Brewer, Eds., Nonvolatile Semiconductor Memory Technology, IEEE Press, Piscataway, New Jersey, 1998. 77. D. Kahng and S. M. Sze, “A Floating Gate and Its Application to Memory Devices,” Bell Syst. Tech.J., 46, 1283 (1967). 78. D. Frohman-Bentchkowsky, “FAMOS-A New Semiconductor Charge Storage Device,” Solid-state Electron., 17, 5 17 (1974). 79. H. Iizuka, F. Masuoka, T. Sato, and M. Ishikawa, “Electrically Alterable Avalanche- Injection-Type MOS Read-only Memory with Stacked-Gate Structures,” IEEE Trans. Electron Dev., ED-23,379 (1976). 80. S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL Flash EEPROM-Part I: Performance and Scaling,” IEEE Trans. Electron Dev., ED-49, 1296 (2002). 81. S. K. Lai and V. K. Dham, “VLSI Electrically Erasable Programmable Read Only Memory,” in N. G. Einspruch, Ed., VLSIhandbook, Academic Press, Orlando, FL, 1985. 82. Y.Nishi and H. Iizuka, “Nonvolatile Memories,” in D. Kahng, Ed., Applied Solid State Science, Suppl. 2A, Academic, New York, 1981. 83. Y. Kamigaki and S. Minami, “MNOS Nonvolatile Semiconductor Memory Technology: Present and Future,” IEICE Trans. Electron., E84-C, 713 (2001). 84. D. V. Averin and K. K. Likharev, “Coulomb Blockade of Single-Electron Tunneling, and Coherent Oscillations in Small Tunnel Junctions,”J. Low Temp.Phys., 62, 345 (1986). 85. T. A. Fulton and G. J. Dolan, “Observation of Single-Electron Charging Effects in Small Tunnel Junctions,” Phys. Rev. Lett., 59, 109 (1987). 86. M. A. Kastner, “Artificial Atoms,” Physics Todq, 24 (Jan. 1993). 87. Y. A. Pashkin, Y. Nakamura and J. S. Tsai, “Room-Temperature A1 Single-Electron Tran- sistor Made by Electron-Beam Lithography,”Appl. Phys. Lett., 76,2256 (2000). 88. K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. Takagi and A. Toriumi, “Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits,” Jpn. J. Appl. Phys., 39, 232 1 (2000). PROBLEMS 371 PROBLEMS 1. Derive Eq. 23 from Eqs. 20 and 22 (p.303). 2. For a square MOSFET (Z/L= l), I, is measured to be 18.7 pA at V, = 0.4 V and V, = 3 V. If we require a current of 1.6 mA at V, = 0.4 V and V, = 3 V, what is the minimum width Z of the device? Assume that the polysilicon gate length is 0.6 pm and the n+ source and drain each diffuses sideways 0.05 pm under the gate. 3. Consider a submicron MOSFET with L = 0.25 pm, 2 = 5 pm, N A = l o t 7~ m - ,~un,= 500 cm2/V-s, Cox= 3 . 4 5 ~ 1 0 -F~/cm2, and V, = 0.5 V, find the channel conductance for Vc= 1 V and V, = 0.1 V. 4. For a MOSFET with a channel length of 10 pm under certain biasing conditions, the channel current ID is 1 mA and the gate current is 1 pA. We want to reduce the gate current to 10% under the same biasing condition and for the same device parameters except the channel length. Find the channel length. 5. For an MOSFET with sufficient drain voltage to be in saturation (under constant-mobility condition), the current is 50 pA at V, = 1 V, and 200 pA at V, = 3 V. Find the threshold voltage. 6. (a) To avoid hot-electron effect in an n-channel MOSFET, we assume an allowed maximum field in the oxide to be 1.45x 1O6 V/cm. Find the corresponding surface potential w, in the silicon for a doping concentration of 10l8~ m - ~ . (b) For an n+-polysilicon gate, find the threshold voltage of the above MOSFET with d = 8 nm, assuming Q , = Q,= Qf=Q, = 0. 7. An n-channel MOSFET is designed to have a threshold voltage of +0.5 V and a gate oxide thickness of 15 nm. Find the channel doping to give the desired V,if n+-polysilicon is used as the gate material, and there are no oxide charge, interface-trapped charge, and mobile ions in the device. 8. To isolate devices from interacting with each other, each MOSFET is surrounded by a field oxide. If the “field transistor” associated with the field oxide must have a threshold voltage of 2 20V, calculate the minimum field-oxide thickness. N, = 10’’ ~ m - Q~f,/q= 10” ~ m - ~ , and an n+-polysilicon is used for local interconnect as the gate electrode. 9. An n-channel n+-poIysilicon-SiO,-Si MOSFET has NA = 1017~ m - Q~f,/q= 2 ~ 1 0c’m~-2, and d = 10 nm. Boron ions are implanted to increase the threshold voltage to +1 V. Find the implant dose, assume that the implanted ions form a sheet of negative charge at the Si-SiO, interface. (q$,$ = -0.98 V). 10. For an n-MOSFET with q v- of 0.5 eV, the threshold voltage change AVTis 1 V when a substrate bias Vssof -1 V is applied. What is AV, when V,, is -3 V? 11. A MOSFET (NA= 1017~ m - d~ =, 5 nm) has a threshold voltage of V, = 0.5 V, a subthreshold swing of 100 mV/decade, and a drain current of 0.1 pA at Vr. If we want to reduce the leakage current at V, = 0 to A, find the reverse substrate-source bias required to achieve the reduction. 12. The subthreshold current of an ideal MOSFET is given by ID = A(Pv~)-”2exp(Pvs)I 372 CHAPTER 6. MOSFETs where iy, is the surface potential, P = qIkT, a = & (.csl.coI)(~oJLLD,),is Debye length = A m p , and A = constant. Show that the subthreshold swing Sis given by A m , where C, = ,Cox= .cox/to,,and a >> CdCox. 13. For a MOSFET with a gate oxide of 10 nm and a substrate doping of IOl7 ~ m - f~in,d the subthreshold swing. 14. For a Si MOSFET with NA= 5 ~ 1 0~' ~m - d~ ,=10 nm, and an interface-trap density of 10" ern-,, find the subthreshold swing with a grounded substrate terminal. 15. An idealized implanted step doping profile has N, = 10l6~ m - N~B,= 1Ols~ m - a~nd, x, = 0.3 pm. Find (1) the implanted dose DI,(2) the centroid of the dose, and (3) the threshold voltage shift (d= 100nm) with respect to a uniformly doped NBcase. 16. Derive Eq. 79. 17. Refer to Fig. 21 (p. 322), assume NB = 7 . 5 ~ 1 0 ~' ~m - d~=, 35 nm, a reverse back bias of 1V, and an implanted dose DI = 6 x 10" cm-,, find the depth of the centroid at which the depletion-layer edge is clamped to the implant (in nm). 18. Find the scaled drain current per unit channel width (Id4for two n-MOSFETs, one with constant-voltage scaling and one with constant-field scaling. Assume the devices are operated under velocity-saturation condition. The initial device parameters are L = 1 pm, d = 10 nm, VD= 5 V, I&= 500 pA/pm. The scaling factor is K = 5. 19. For the constant-voltage scaling approach of MOSFET with a scaling factor ~ = 1 0f,ind the doping concentration of a scaled device if the original device has a doping of 1OIs~ m (i-n ~ ~m-~). 20. When the linear dimensions of a MOSFET are scaled down by a factor of 10 based on the constant-field scaling, (a) find the corresponding factor of the scaled switching energy, and (b) find the scaled power-delay product, assuming the product is 1 J for the original large device. 21. A composite structure of a 20 nm Ta,O, ( ~ ~ 1 =. c2~5) and a 2-nm SiO, is sandwiched between a top and bottom electrodes. Find the equivalent SiO, thickness (in nm). 22. A DRAM must operate with a minimum refresh time of 4 ms. The storage capacitor in each cell has a capacitance of 50 fF and is fully charged at 5 V. Estimate the worst-case leakage current that the dynamic capacitor node can tolerate (i.e., the charge in the capacitor has dropped to its 50% level). 23. For DRAM operation assume that we need a minimum of lo5 electrons for the MOS storage capacitor. If the capacitor has an area of 0.5 pmx0.5 pm on the wafer surface, an oxide thickness of 5 nm, and is fully charged to 2 V, what is the required minimum depth of a rectangular-trench capacitor? 24. For a floating-gate nonvolatile memory device, the lower insulator has a dielectric constant of 4 and is 10 nm thick. The insulator above the floating gate has a dielectric constant of 10 and is 100nm thick. If the current density J , = ~55'' where D= Ik7Slcm, and the current PROBLEMS 373 in the upper insulator is zero, find the threshold voltage shift for a sufficiently long time such that J , becomes negligibly small. The applied voltage on the control gate is 10 V. 25. Consider a NVSM cell whose cross section is shown. The channel width is 1 pm. Assume that the bird’s beak has the linear wedge shape illustrated. The gate oxide thickness (between substrate and FG) is 35 nm, the interpoly dielectric is an oxide of 50 nm, and the field oxide is Ill 0 0.5 1 Ill 2 2.5 3 0.6 pm. The physical gate length is 1.2 pm, the metallurgical junction lies 0.15 pm under the gate and the effective channel length is 0.7 pm. The floating gate poly is 0.3 pm thick. Calculate (a) the value of the control gate to floating gate capacitance, (b) the drain to floating gate capacitance, assume half of the channel capacitance to the source and other halfto the drain, and (c) if the floating gate to substrate capacitance is 0.14 fF,calculate the control gate to floating gate coupling ration, R, and the drain to floating gate coupling ration, R,. 26. For a silicon nonvolatile memory with a floating gate, the thickness and the dielectric con- stant for the first insulator (thermally grown SO,) are 3 nm and 3.9, and the corresponding values for the second insulator are 30 nm and 30. Estimate the stored charge/cm2 in the floating gate after a gate voltage of 5.52 V is applied for 1 ms. There is no current conduction through the second insulator, and the current in the first insulator is by Fowler-Nord- heim tunneling. *, 27. A floating-gate nonvolatile semiconductor memory has a total capacitance of 3.71 a control gate to floating gate capacitance of 2.59 fF,a drain to floating gate capacitance of 0.49 fF,a floating gate to substrate capacitance of 0.14 fF.How many electrons are needed to shift the measured threshold by 0.5 V (measured from the control gate)? 28. An EEPROM has C, = 2.59 fF,C, = C, = 0.49 fF,and C, = 0.14 fF,where they indicate the capacitances between the floating gate and the control gate, source, drain, and substrate, respectively. Assume that when the control gate and the floating gate are shorted together, the device threshold is measured to be 1.5V. If the control gate is at 12 V, and the drain is at 7 V during programming, to what potential can the floating gate be charged while the programming voltages are present? What threshold would be observed after programming under these biases for a drain bias during reading of 2 V? Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. JFETs, MESFETs, and MODFETs 7.1 INTRODUCTION 7.2 JFET AND MESFET 7.3 MODFET 7.1 INTRODUCTION In this chapter, we discuss field-effect transistors (FETs) other than the MOSFET to which we have devoted the whole chapter. Referring back to the FET family tree depicted in Fig. 3 (p. 295) of Chapter 6 , we pointed out that all FETs have a gate that is coupled to the channel through some form of a capacitor. While in a MOSFET the capacitor is formed by an oxide layer, the JFET (junction FET) and the MESFET (metal-semiconductor FET) form the capacitor by virtue of a depletion layer in a junction; the JFET from ap-n junction and the MESFET from a Schottky (metalsemiconductor) junction. In the branch of HFET (heterojunction FET), a layer of high-bandgap material is grown epitaxially over the channel, and it is used as an insulator. Bear in mind that the conductivity of a material is fundamentally related to its energy gap. An insulator is characterized by having a large energy gap. Epitaxial heterojunction produces an ideal interface. Such technique is necessary when an ideal oxide-semiconductor interface is lacking, which is practically for all semiconductors other than silicon. Under HFETs, the high-bandgap material can be doped or undoped. With high-E, material that is doped, carriers from dopants are transferred to the heterointerface and form a channel of high mobility, since the channel itself is undoped to avoid impurity scattering. This technique is called modulation doping. When applied to the gate of an FET, the result is a MODFET (modulation-doped FET) which possesses some interesting features. When the high-E, material is undoped, the resultant device is called HIGFET (heterojunction insulated-gate FET). In this case modulation doping is not present and the high-E, material is used purely as an insulator. Such a device behaves in principle the same way as a MOSFET and 374 1.2 JFET AND MESFET 375 will not be discussed further in this chapter. So the chapter primarily focuses on JFET, MESFET, and MODFET. Of the three devices, the JFET and MESFET share a similar working principle. They are both based on bulk, buried-channel conduction. Their current path is modulated by the depletion width under the gate. They are also similar to a buried-channel MOSFET, except in the latter, the gate can be forward biased to the extend that accumulation at the surface can occur such that a surface channel can be formed in parallel to the buried channel. However in the JFET and MESFET, the junctions cannot be biased beyond or even close to flat-band before excessive current flows through the gate. So the JFET and MESFET are first studied together sharing the same equations. The MODFET has a two-dimensional channel at the heterointerface and will be treated independently. 7.2 JFET AND MESFET The JFET, first proposed and analyzed by Shockley in 1952,' is basically a voltagecontrolled resistor. Based on Shockley's theoretical treatment, the first working JFET was reported by Dacey and Ross, who later also considered the effect of field-dependent m ~ b i l i t y . ~ , ~ The MESFET was proposed and first demonstrated by Mead in 1966.4Shortly after, microwave performance was reported by Hooper and Lehrer in 1967, using a GaAs epitaxial layer on semiinsulating GaAs sub~trate.~ Both JFET and MESFET have the advantage of avoiding problems related to the oxide-semiconductor interface in a MOSFET, such as interface traps and reliability issues arising from hot-electron injection and trapping. However, they have limitation on bias range allowed on the input gate. In comparison, the MESFET offers certain processing and performance advantages over the JFET. The metal gate requires only low-temperature processing compared to ap-n junction made by diffusion or implantanneal sequence. The low gate resistance and low IR drop along the channel width is a big factor in microwave performance such as noise andf,,,. The metal gate has better control in defining short channel lengths for high-speed applications. It can also serve as an efficient heat sink for power applications. On the other hand, the JFET has a more robust junction for higher breakdown and power capability. A p-n junction has a higher built-in potential which is useful towards achieving an enhancement-mode device. The higher potential also reduces the gate leakage for the same bias. The p-n junction is a more controlled structure whereas a good Schottky barrier sometimes is difficult to form on certain semiconductors such as some p-type materials. A JFET has more freedom for various gate configurations, such as a heterojunction or a buffered-layer gate, that improve certain aspects of performance. 7.2.1 I-V Characteristics Similarity between JFET and MESFET can be seen from their schematic diagrams shown in Fig. 1, using an n-type channel as an example. The transistors consist of a 376 CHAPTER 7. JFETs, MESFETs, AND MODFETs Source Gate Drain Source Metal gate Drain p- or semiinsulating substrate (a) Fig. 1 Schematic structures of (a) JFET and (b) MESFET, showing their similarity in that the net channel opening b is controlled by the depletion width W,. conductive channel provided with two ohmic contacts, one acting as the source and the other as the drain. When a positive voltage V, is applied to the drain with respect to the source, electrons flow from source to drain. Hence the source acts as the origin of the carriers and the drain as the sink. The third electrode, the gate, forms a rectifying junction and controls the net opening of the channel by varying the depletion width. The rectifying gate is ap-n junction in the JFET and is a Schottky-barrierjunction in a MESFET. The device is basically a voltage-controlled resistor, and its resistance can be controlled by varying the width of the depletion layer extending into the channel region. In Fig. 1 the basic device dimensions are the channel length L (also called the gate length), channel depth a, depletion-layer width W,, net channel opening b, and channel width Z (into the paper, not shown). The voltage polarities shown are for an n-channel FET, and the polarities will be inverted for a p-channel FET. The gate and drain voltages are measured with respect to the source, and the source electrode is generally grounded. When V, = V, = 0, the device is in equilibrium and there is no current conduction. Most JFETs and MESFETs are of depletion mode, i.e., normallyon with V , = 0, or threshold voltage V , is negative. For a given V , above the threshold voltage, the channel current increases with the drain voltage. Eventually for sufficiently large V, the current will saturate to a value IDSat. Very often for JFETs, the channel is surrounded by two gates. For Fig. la, that would be a second gate from the bottom side. The analysis we follow here is for one gate only. So this type of structure can be bisected into two halves and the final result becomes half of the total values, in both current and transconductance. The basic current-voltage characteristics of a JFET or MESFET are shown in Fig. 2, where the drain current is plotted against the drain voltage for various fixed gate voltages. We can divide the characteristic into three regions: the linear region where the drain voltage is small and I, is proportional to V,; the nonlinear region; and the saturation region where the current remains essentially constant and is independent of V,. As the gate bias becomes more negative, both the saturation current and the corresponding saturation voltage V,, decrease. The locus of IDsaVt-,,, is shown in Fig. 2. 7.2 JFET AND MESFET 377 Fig. 2 General I- Vcharacteristics of the JFET and MESFET. We shall now derive the general I-V characteristics for JFETs and MESFETs, based on the following assumptions: (1) uniform channel doping, (2) gradual-channel approximation (Ex<< EJ,(3) abrupt depletion layer, and (4) negligible gate current. We start with the channel charge distribution which is related to the channel dimensions. The channel dimensions and its potential distributions under both gate and drain biases are shown in more details in Fig. 3. These are the basis for deriving the I- Vcharacteristics. Channel-Charge Distribution. For a uniformly doped n-channel, under the gradual-channel approximation, the depletion-layer width W, varies only gradually along the channel (x-direction), and one can solve the one-dimensional Poisson equation in the y-direction; where Ey is the electric field in the y-direction. The depletion-layer width at any distance x from the source is given by the one-sided abrupt-junction depletion approximation where vbiis the built-in potential. For a JFET, the vb;is that of ap+-njunction, given by -[..- vb=i 1 kTln($)] (3) 4 For a MESFET, the vbi is determined by the Schottky barrier height 4BBonf the metal- semiconductor junction, given by 378 CHAPTER 7. JFETs, MESFETs, AND MODFETs X 7 Gate vG al n-channel Drain b Potential = I&) L c I \ I--- - Fig. 3 (a) Channel dimensions under drain and gate biases. (b) Energy-band diagram in y-direction at the source end (dashed lines) and drain end (solid lines). The potential difference A I,&)is the potential of the neutral channel [- E,(x)lq] with respect to the source. So at the drain end, A%(L) = VD.The depletion widths at the source and drain ends are given by The maximum value of gate bias applied to increase the current is limited to VG= vbi which corresponds to the condition of WD3= 0. This flat-band condition in practice is not achievable due to the excessive forward current of the gate junction. The maximum value of WDdis equal to a, and the corresponding total band bending is called the pinch-offpotential, defined as 7.2 JFET AND MESFET 379 The channel charge density, which is responsible for the current conduction, is proportional to the net channel opening, given by = q N D ( a - wD>. (8) The channel current is simply given by the charge multiplied by its velocity u, ID(X> = zQn(X>u(X>. (9) Since the current has to be continuous throughout the channel, it is independent of position. Integrating Eq. 9 from source to drain yields Flz, = - Q,(X>U(X)dx. This is the basic equation used to derive the I- Vrelationship. Equation 10 requires knowledge of the carrier velocity under an applied field, so the u - g relationship is critical. In the following analysis, we use different assumptions for such relationship. Referring again to Fig. 2, we find that current saturation can originate from two very different mechanisms. The first is due to channel pinch-off when the net channel is totally pinched off by the depletion width. This is called longchannel behavior, and found to be modelled well simply by a constant mobility, i.e. u = pg. The second possible mechanism, especially true for short-channel devices, is that the field is high enough such that mobility is no longer constant and eventual the velocity rises to a constant value called saturation velocity. This occurs before the channel is pinched off. These effects are considered in the following subsections. Constant Mobility. With constant mobility, the relationship u = pEXis assumed to hold without limit. Using this relationship and that gX= dAK/dx, Eq. 10 after carrying out the integration gives where is the full channel conductance when W, = 0. In the linear region, V, << VGand V, << cl/bj, Eq. 11 is reduced to iq) ZDlin = Gi( 1- V, (13) where ohmic characteristics are observed. Equation 13 can be further simplified by Taylor's expansion around VG= Vrto 380 CHAPTER 7. JFETs, MESFETs, AND MODFETs with ' T = vbi- v P V,is the gate threshold voltage around which the transistor is turned on and off. When the drain bias continues to increase, the current according to Eq. 11 goes through the nonlinear region. It reaches a peak and actually drops beyond that point. The drop of current is not physical, but it corresponds to a pinch-off condition when W,, = a. The V, at the onset of this condition can be shown to occur at vDsat = V P - V b i + vG = vG- vT . (16) Once that is known, the current in the saturation region can be found by substituting VDsaitnto Eq. 11: It is seen here that ZDsat is limited to a maximum of G i v - 3 ,a condition that cannot be reached in reality due to excessive gate current. The transconductance is given by Qualitatively, for drain bias higher than VDsath, e pinch-off point starts to migrate toward the source. However, the potential at the pinch-off point remains to be VDsat, independent of V,. The field within the drift region thus remains fairly constant, giving rise to current saturation. Practical devices show that ZDsat does not saturate completely with V,. This is due to the reduction in the effective channel length, which is measured between the source and the pinch-off point. Equation 17 can also be simplified using Taylor's expansion around VG= V,: (19) and It is seen here that the forms of Eqs. 14, 19, and 20 are similar to that of MOSFET only near the threshold, i.e., VG= V,. This stems from the fact that the gate capaci- tance (or depletion width) is gate-bias dependent in JFET and MESFET, while that in the MOSFET (gate dielectric) is fixed. In other words, in a MOSFET the channel charge is linearly dependent on VG,while that is not true for a JFET or MESFET (Eq. 8). 7.2 JFET AND MESFET 381 One major difference of a bulk three-dimensional channel, as in JFET and MESFET, from a charge-sheet two-dimensional channel, as in MOSFET and MODFET, is that the current is controlled by the net channel opening. Because of this, it is possible that the current is expressed in terms of physical dimensions. This can offer a look from another angle and perhaps helps to understand the problem. Using the relationship Equation 10 leads to -- Zpq2N$a3 6E~L [3(u3- 24:) - 2(Uj - u ; ) ] , where the normalized dimensionless units are defined as /v. u d = - -w=Dad u s = -wDs = - a Equation 22 can also be transformed directly from Eq. 11. In the linear region for small VDt,his equation can be shown to reduce to IDlin = Gj(1 -uS)VD. (25) Current saturation is determined when the channel is pinched off. Setting ud = 1, the saturation current is given by Zpq2N$a3 ( 1 - 321: + 2u:) 'Dsat = 6eSL Consequently, the transconductance is given by = Gi(1 - u s ) . (27) Velocity-Field Relationship. For long-channel devices, the field is low enough that the carrier velocity is treated as being proportional to the field, i.e., constant mobility. For FETs with short channels, significant discrepancies are encountered between experiment and basic theory. One main reason for the discrepancies is the higher internal field for short channels. Figure 4 shows the qualitative dependence of the drift velocity versus electric field for silicon. At low fields the drift velocity increases linearly with the field, and the slope corresponds to a constant mobility ( p= d8).At 382 CHAPTER 7. JFETs, MESFETs, AND MODFETs A '- Constant mobility a -.cx- 0 m 5 6 Fig. 4 Drift velocity vs. electric field for Si and semiconductors that rn do not have a transferred-electron gc Longitudinal field gx effect. higher fields, the carrier velocity deviates from a linear dependence. It becomes lower than simple extrapolation from the low-field slope, and eventually saturates to a value called saturation velocity us.So for short-channel devices, these effects have to be taken into account. For silicon the drift velocity approaches its saturation value of lo7cm/s at fields above 5 x lo4V/cm. For some semiconductors such as GaAs and InP, the drift velocity first reaches a peak value and then decreases toward a saturation velocity of about 6-8x 1O6 c d s . This negative-resistance phenomenon is due to the transferred-electron effect. Its u-Z? relationship is too complicated to yield an analytical result and is not considered in this chapter. In this section, we will examine two simple u-E relationships. The first is the twopiece linear approximation shown in Fig. 4. The second is an empirical formula which has a smooth transition between the constant-mobility regime to the saturationvelocity regime, given as where Ex= dAr,u,/duis the longitudinal field in the channel. As seen, both relationships contain an important parameter, the critical field gC. Field-Dependent Mobility: Two-Piece Linear Approximation. We first discuss velocity saturation based on the two-piece linear approximation. Note that in this model, the constant-mobility results (i.e., Eq. 11) are valid up to the point where the maximum field, which is at the drain end, reaches the critical field Ec. Once at that VDsat,which is lower than the VDsatof the constant-mobility model, the current saturates at a new and lowered ZDsat. So the main task is to calculate this new VDsat. We start with Eq. 9 (and substitute u = p g ) which contains the relationship between field and current. Setting g = gCand ZD = IDsawte,have 7.2 JFET AND MESFET 383 Equating this to Eq. 11, a transcendental equation for VDsaits obtained ,/< g C L= VDsat- [ 2 / ( 3 f i P ) l [ ( ( Y b j + ' D S a t - V ( ? > 3 ' 2 - ( ( Y b i - (Ybi + 'Dsat - V G ) / (YP VG)3/21 ' (30) Visual examination of this equation indicates that current saturates as VDapproaches g J , or V d L= gc.Once VDsaits known, ZDsat can be calculated from Eq. 11 of the constant-mobility model. One also finds that since VDsaits lower than the value from the constant-mobility model, current saturation occurs before the channel is pinched off. Field-Dependent Mobility: Empirical Formula. We next derive the current equation based on the empirical v( Z ) formula given in the form of Eq. 28. Substituting u into Eq. 9 and integrating from x = 0 to L , we obtain p ( l +;)CA = [ Z Q n P W ' (31) Notice that the right-hand side is similar to the constant-mobility model in Eq. 10 which results in Eq. 11. The left-hand side gives a value of ZD(L + VdgC)A. fter the integration Eq. 3 1 yields Comparing this to Eq. 11, this new result gives a current that is reduced by a factor of (1 + V d g J ) from that of the constant-mobility model. In order to obtain VDsatw, e seek the current peak from Eq. 32 by setting d Z d d V D = 0. This yields a transcendental equation for VDsaats Solutions of VDsaftrom the above equation have been calculated and plotted in Fig. 5, for various values of gJ,. The top curve (8$= a)becomes the limit of the constantmobility model. Note that with decreasing E J , the saturation of drain current is reached at smaller values of drain voltage. To obtain the saturation drain current, the solutions for IfDsat can be used in Eq. 32, which is done by substituting some terms from Eq. 33 into Eq. 32: 384 CHAPTER 7. JFETs, MESFETs, AND MODFETs 1.o 0.8 0.6 0.2 0 (vbi - vG)/vP Fig. 5 Solution of VDSatfrom Eq. 33, for various values of I,@EJ. (After Ref. 6.) where udm is the value of u d evaluated at VDsatT. he transconductance in the saturation region can then be obtained from taking derivatives of both Eqs. 33 and 34 (readers are reminded that VDsaits also a function of VG): zp dIDsat - Gi (Jvbi+ 'Dsat - ' G - W gm = - 1+ (V D / g C L ) 1G -- Gi(Udm - us) . (35) 1 + (v/p/':,')(u2m -u,') This expression reduces to Eq. 27 of the constant-mobility model for 8J = 00 and udm = 1. Having gone through the three models of u - 8 relationships, it is informative to compare their results on the I- Vcharacteristics. Here we use an example of one I- V vp curve for a fixed VG(= 0 ) ,and the other parameters are; = 4 V, vbi = 1 V, and Z5$ = 2 V. The results are shown in Fig. 6 . The values of the VDsaftor the constant mobility, two-piece liner approximation, and the empirical formula are 3 V, 1.3 V, and 1.9 V respectively.Note that the curve for the two-piece-linear model lies on the constant-mobility curve until VDsatT. he lowest current of the three curves corresponds to the empirical formula of Eq. 29 since at any field, the velocity is the lowest among the three models as shown in Fig. 4. Constant mobility Y / 2-piece linear approximation Empirical formula 7.2 JFET AND MESFET 385 Ill1 ,111 0 1 2 3 4 5) v, (V) Fig. 6 I-V curves for a fixed V , (= 0) for three models of u - g relationship. Velocity Saturation. One limiting case is the saturation-velocity model7 which is expected to be valid in the limit of very short gates where L << Vdg:,.In this assumption, the carriers travel with usin the whole region under the gate, and are totally independent of the low-field mobility. Starting from Eq. 9, the saturation current is simply given by 'Dsat = z e n u s = Zq(a- R ~ ~ s ) N D ~ s . (36) The maximum current for the devices is thus ZqaNDvswhich is reduced from that of the constant-mobility model given by GiyFJ3.The choice of depletion width at the source W,, rather than at the drain is apparent as we discuss details of the carrierdensity and velocity profiles in the next section (Dipole-Layer Formation). This equation shows an interesting feature that the saturation current is now totally independent of the channel length. The transconductance is given by Since &,IWDSis the gate-source capacitance C,(,, this equation reduces to the familiar FET equation g m = ZCGSVS. (38) This equation also has the interesting feature that g, is constant and totally independent of gate bias as well as channel length. Olutput characteristics of constant mobility and velocity saturation are compared in Fig. 7. Note that the saturation current and saturation voltage are lower under velocity saturation, but the linear regions remain similar. The constant g , under velocity saturation is indicated by the equal spacing of the I- V curves under different V, . As shown, this velocity-saturation limit provides very simple derivations and results, thus giving a good insight of the short-channel limit. In fact, the simple formulae can fit quite well to the state-of-the-art shortchannel devices. 386 CHAPTER 7. JFETs, MESFETs, AND MODFETs Fig. 7 A qualitative comparison ofI-Vcurves under models of (a) constant mobility and (b) velocity saturation. Even though velocity saturation sets a limit on the maximum carrier speed in a field-effect transistor, there are two special effects that enable higher speed at part of the channel where the local field is high. The first is related to the material properties, such as in GaAs and InP, which display a transferred-electron effect. According to the u-2?relationship shown in Fig. 20a (p. 38) in Chapter 1, at moderately high fields, the drift velocity is actually higher than the saturation velocity. To include this negativeresistance effect in modeling the I- V characteristics analytically would be very difficult. The second effect is present in ultra-short devices when their channel lengths are comparable to or smaller than the mean free path of scattering. Readers are referred to the discussion of ballistic effect in Chapter 1 (p. 37). For very short gates, the electrons may not have enough time or distance to reach equilibrium transport in the highfield region of the channel.8 In such cases, the electrons enter the high-field region and are accelerated to a higher velocity before relaxing to the equilibrium value. Carriers can thus overshoot to more than twice the steady-state velocity and then relax to the equilibrium condition after traveling a certain distance. The overshoot will shorten the electron transit time. This overshoot is expected to improve high-frequency response, especially for the GaAs FET. This phenomenon is related indirectly to low-field mobility since they are both determined by scattering. A material with higher mobility can have more ballistic effect for the same channel length. Dipole-Layer Formation. An interesting phenomenon occurs that is associated with velocity saturation and when biased beyond V,,,,. This stems from the fact that as drain bias increases beyond VDsat, the depletion layer continues to grow and meanwhile the net channel opening is reduced. In order to maintain the same saturation current, the carriers concentration in the narrower channel has to rise above the doping level in order to maintain the same current since velocity is fixed at us.This is explained in more details as follows. 7.2 JFET AND MESFET 387 Below the saturation drain bias VDsat, the potential along the channel increases from zero at the source to V, at the drain. Thus, the gate contact becomes increasingly reverse-biased with respect to the channel, and the depletion width becomes wider as we proceed from source to drain. The resulting decrease in channel opening b must be compensated by an increase in electric field and electron velocity to maintain a constant current throughout the channel. As VDis increased further to VDsat,the electrons reach the saturation velocity at the drain end of the gate (Fig. 8a). The channel is constricted to the smallest cross section b, under the gate. The electric field reaches the critical value tZc at this point, and ,Z starts to saturate. The electron density n(x), however, remains equal to the doping density No as long as the field does not exceed the critical value gC. The condition of V, > VDsatis displayed in Fig. 8b. The saturation current is given by = Zqvsn(x)b(x). (39) If the drain voltage is increased beyond VDsat,the depletion region widens toward the drain. The point x l , where the electrons reach the saturation velocity and the channel width is b,, moves toward the source. Note that there are three locations of interest; xi x2 x3 Fig. 8 (a) Schematic cross-section showing condition at V, = VDSaatnd under velocity satu- ration. (b) Dipole-layer formation when operated with VD> VDsats, howing electric-field and carrier-concentration profiles through the quasi-neutral channel. (After Ref. 9.) 388 CHAPTER 7. JFETs, MESFETs, AND MODFETs x, and x2 are locations where the channel opening is b,, and x, and x3 are locations where 2? = gCT. his also means that in the region x, to x2the channel is narrower than b,, and in the region x, to x3,carriers travel with v,. Since the velocity is saturated, in the region x, to x2the change in channel width must be compensated by a change in carrier density to maintain constant current. According to Eq. 39, an electron accumulation layer ( n > No) must form in this region, where the channel opening is smaller than b,. At x, the channel opening is again b,, and the negative space charge changes to a positive space charge ( n < No) to preserve constant current. Between x, and x3the electron velocity remains saturated but the channel width is larger than b,. So by virtue of the same Eq. 39, carrier concentration is lower than No in order to keep the saturation current constant. Therefore, the drain voltage applied in excess of VDs,,forms a dipole layer in a channel that extends beyond the drain end of the gate. Breakdown. For drain voltages beyond VDsath, e drain current is assumed to remain essentially the same as the saturation current. As the drain voltage increases further, breakdown occurs where the current rises sharply with the drain bias. This breakdown occurs at the gate edge toward the drain side where the field is the highest. Analysis of the breakdown condition in an FET is inherently more complicated than in a bipolar transistor because it is a two-dimensional situation as opposed to onedimensional. The fundamental mechanism responsible for breakdown is impact ionization. Since impact ionization is a strong function of the electric field, the maximum field is often regarded as the first-order criterion for breakdown. Using a simple one-dimensional analysis in the x-direction, and treating the gate-drain structure as a reversebiased diode, the drain breakdown voltage VDBis similar to that of the gate-junction breakdown and is linearly dependent on the relative voltage of the drain to the gate; where VBthe breakdown voltage of the gate diode and is a function of channel doping level, among other factors. The general breakdown behavior of Eq. 40 is shown in Fig. 9a. It is shown that for higher VG,the drain breakdown voltage becomes higher by the same amount. Such characteristics general hold true for silicon JFETs. But for MESFETs on GaAs, the breakdown mechanisms are much more complicated. They generally have lower breakdown values and the dependence of V, no longer follows Eq. 40 but has a opposite trend, as shown in Fig. 9b. These additional effects will be discussed next. Unlike a MOSFET where the heavily doped source and drain overlap the gate at the gate edges, the JFETs and MESFETs have a gap between the gate and the source/drain contacts (or heavily doped regions under the contacts). For breakdown consideration, this gate-drain distance L , is critical. In this gap the doping level is the same as the channel. If surface traps are present in this gate-drain spacing, they can deplete part of the channel doping and affect the field distribution. In certain cases they can improve the breakdown voltage. Two-dimensional simulations in Fig. 10 displays the field distribution as a function of surface potential created by surface traps. Without surface traps (i.e., w, = 0), the field is highest at the gate edge where 7.2 JFET AND MESFET 389 6tvG I Fig. 9 Experimental data showing drain breakdown voltage (a) increases with V, in Si JFETs but (b) decreases with V, in GaAs MESFETs. breakdown occurs. In this particular example, with a surface potential of 0.65 V, the field at the gate edge is reduced, thereby increasing the breakdown voltage. Using a one-dimensional analysis, the field at the gate edge can be shown to belo where Nil is the surface-trap density. (This equation implies that L G D is larger than the I-D depletion width so that with Nil = 0, 8 ( L )and V, are independent of LGD.) For an increased surface potential of 1.O V, the field at the drain contact is increased, since the area under the curve is the total applied voltage and it has to be conserved. If the field at the drain contact is increased to a critical value, breakdown can occur there, thereby lowering the breakdown voltage again. Since GaAs lacks a common Distance from gate to drain (km) Fig. 10 Electric-field distribution in gate-drain spacing as a function of surface potential ysdue to surface traps. VD= 4 V. V , = 0. (After Ref. 10.) 390 CHAPTER 7. JFETs, MESFETs, AND MODFETs passivation layer such as SiO, for silicon, the breakdown in GaAs MESFETs are less controllable and have different breakdown behavior compared to Si JFETs. One factor for a reduced breakdown voltage in MESFETs is due to tunneling current associated with the Schottky-barrier gate contact." At high fields, this tunneling current is from thermionic-field emission which has a temperature dependence. The gate current can initiate avalanche multiplication and induces lower drain breakdown voltage. With higher channel current, the internal node is at a higher temperature which triggers an earlier gate-current-initiated avalanche breakdown. This can be responsible for lower V, at higher V, in Fig. 9b. Another factor is that GaAs MESFETs usually have higher current and transconductance than Si devices due to higher mobility. The higher channel current can initiate avalanche at a lower voltage, or produce the temperature effects which trigger earlier breakdown as discussed. The breakdown voltage can be improved by extending the region between the gate and the drain. Furthermore, to maximize its function, the field distribution should be made as uniform as possible. One technique is to introduce a doping gradient in the lateral direction. Another, called RESURF (reduced surface field),', is to have ap-layer underneath such that at high drain bias, this n-layer is fully depleted. 7.2.2 Arbitrary Doping and Enhancement Mode Arbitrary Doping Profile. For an arbitrary doping profile in the channel region,13 the net potential variation inside the depletion width is related to the doping as given by Eq. 40 of Chapter 2, The maximum value for the upper limit of the integral occurs at WD= a, and the corresponding quantity is the pinch-off potential as defined previously, given by We next consider the current-voltage characteristics and the transconductance. We shall define an integral form of the total charge density up to the position y , as which will be used to simplify the equations that follow. The drain current based on Eq. 9 would have to be modified to be 7.2 JFET AND MESFET 391 Bear in mind that both v and W, vary with x along the channel under a drain bias. Integrating both sides of this equation from x = 0 to L gives B I ID& = ZDL = Z v[Q(u)- Q( WD)]dX. (464 or v[Q(a)-Q(W~)ld. (46b) Equation 46b is the basic equation for calculating the drain current. In the linear region, the drift velocity is always in the constant-mobility regime due to the small field or drain bias. Substituting v = p g = $A %Id,we obtain In the saturation region, we first consider the case where saturation is caused by pinch-off (W,, = a ) as opposed to velocity saturation. Starting again with Eq. 46b and changing the variable to W, with Eq. 21, the drain current is (48) Using the relationship similar to Eq. 21, (49) the transconductance is given by differentiating Eq. 48 = QLI Q ( a ) - Q ( w ~ , ) l (50) which shows that g, is equal to the conductance of the rectangular section of the semiconductor extending from y = WDsto a. For short-channel devices where velocity saturation determines current saturation, the drain current is simply given by 392 CHAPTER 7. JFETs, MESFETs, AND MODFETs The transconductance is given by which is identical to Eq. 37. In real applications, it is often preferable to have good linearity, i.e., constant g,, meaning IDsatchanges linearly with V,. Linearity of the transfer characteristics is approached by those profiles in which the depletiondepth WD(V,) changes very little as a function of the gate voltage. The transfer characteristics for various doping profiles are shown in Fig. 11. Note that both types of nonuniform dopings achieve linearity as the appropriate variable parameter is taken to its limit, which has a delta doping at x = a. The results shown are quite different from the constant-mobility case, in which the doping profile has little effect on the transfer characteristics. Although Eq. 53 implies a reduction ofg, for lower gate voltage, the importantquantityg,/cG, remains unaffected, where ,C, is the gate-source capacitance. This is because C, = &,/WD,and Eq. 53 gives 2 d = Zv, = constant. (54) cGS Experimental results have confirmedthat FETs with graded channel doping14or step dopings15have improved linearity. Enhancement-Mode Devices. Buried-channel FETs are usually normally-on devices. The basic current-voltage characteristics of normally-on and normally-off devices are similar, except for the value of the threshold voltage. Figure 12 compares these two modes of operation. The main difference is the shift of threshold voltage along the V,-axis. The normally-off device has no current conduction at VG = 0, and when V, > V, the current starts to flow. For high-speed low-power applications,the normally-off (or enhancement-mode) device is very attractive.A normally-off device is one that does not have a conductive channel at VG = 0; that is, the built-in potential ybiof the gatejunction is suficient to totally deplete the channel region. Mathematically, normally-off device has a positive V , implying from Eq. 15 Uniform doping, N,, NrJ 4 v p = 4- ND,a2 2 8. 7.2 JFET AND MESFET 393 Fig. 11 ,Z expressions and transfer characteristics for various doping profiles. Velocity-saturation model is assumed. (After Ref. 7.) Since the built-in potential vbhjas a limit comparable to the energy gap, it imposes a limit on the channel doping and channel width, both of which affect the maximum current the device can provide. For a uniformly doped channel that is saturationvelocity limited, the maximum current is given by I D < ZqN,av,. (56) This current limit would be obtained if the applied gate bias were equal to the built-in potential, an impractical biasing condition which will cause excessive gate current. 7.2.3 Microwave Performance Small-Signal Equivalent Circuit. Field-effect transistors, especially GaAs MESFETs, are useful for low-noise amplification, high-efficiency power generation, and high-speed logic applications. We shall first consider the small-signal equivalent circuit of a MESFET or JFET. A small-signal lumped-element circuit for operation in the saturation region in common-source configuration is shown in Fig. 13. In the - v, 0 VT (a) (b) Fig. 12 Comparison of I-Vcharacteristics for (a) normally-on (depletion-mode) FET and (b) normally-off (enhancement-mode) FET. ==CLOT + I ICbLJ "G== I G' S Source o ==CDs (a) o Source Fig. 13 (a) Small-signal equivalent circuit of MESFET and JFET. uG is small-signal VG. Capacitance symbol with prime designates total capacitance in farad as opposed to capacitance per unit area. (b) Origin of circuit elements is related to physical structures. 394 7.2 JFET AND MESFET 395 intrinsic FET, the elements C;, + C;, are the total gate-channel capacitance (= C; ); R,, is the channel resistance; R,, is the output resistance which reflects the nonsaturating drain current with drain bias. The extrinsic (parasitic) elements include the source and drain series resistances R, and R,, the gate resistance R , the parasitic input capacitance CAar and output (drain-source) capacitance Cbs . The leakage current in the gate-to-channel junction can be expressed as where n is the diode ideality factor (1 < n < 2) and Z,is the saturation current. The input resistance is given by As I , approaches zero, the input resistance at room temperature is about 250 MR for I, = A. It becomes even higher for negative gate bias (negative ZG). The FET obviously has a very high input resistance, even though it is not as ideal as in a MOSFET which has an insulating gate. The source and drain series resistances, which cannot be modulated by the gate voltage, will introduce an ZR drop between the gate and the source and drain contacts. These ZR drops will reduce the drain conductance as well as the transconductance. The internal effective voltages V, and V, should then be replaced by [VD-~D(R,+RD)] and ( V , - Z g s ) , respectively. In the linear region, the resistances R, and R, are in series, adding to the total measured drain-source resistance (Rs+RD+R,h). In the saturation region, the drain resistance R, will cause an increase of the drain voltage at which current saturation occurs. Beyond that voltage V, > VDsat,the magnitude of V, has no effect on the drain current. By the same token, the measured transconductance in the saturation region is affected only by the source resistance. Thus R, has no hrther effect on gm,and the measured extrinsic transconductance is equal to Cutoff Frequency. For a measure of the high-speed capability, the cutoff frequency fT and the maximum frequency of oscillationf,,, are commonly used. The f , is defined as the frequency of unity gain, at which the small-signal input gate current is equal to the drain current of the intrinsic FET. Thef,,, is the maximum frequency at which the device can provide power gain. Thef, is a more appropriate figure-of-merit for digital circuits where speed is the primary concern, andfmaxis more relevant for analog-circuit applications. Based on unity gain, one can use the derivation discussed in Section 5.3.1 (p. 263) for an expression 396 CHAPTER 7. JFETs, MESFETs, AND MODFETs Here Ci, is the total input capacitance (Fig. 13), and Cb is the sum of Cbs and CbD. For an ideal case of zero input parasitics (CAar= 0), we obtain This equation has the physical meaning that f Tis related to the ratio Llv which happens to be the transit time for a carrier to travel from source to drain. The drift velocity v is equal to the saturation velocity v, for short channels, and for a 1-pm gate length, the transit time is of the order of 10ps (lo-" s). In practice, the parasitic input capacitance Ciur is a fraction of Cb ,s0fTis slightly below its theoretical maximum value. Equation 60 is an approximation ignoring some of the parasitics. A more-complete equation accounting for source and drain resistances and the gate-drain capacitance is given by Note that g,,, is the intrinsic value but not gmxas in Eq. 59. The speed limitations of FETs are also dependent on device geometry and mate- rial properties. In the device geometry, the most-important parameter is the gate length L. Decreasing L will decrease the total gate capacitance [ Cb cc (2x L ) 3 and increase the transconductance (before velocity saturation); consequently,f, improves. As for the carrier transport, since the internal field varies in magnitude along the channel, drift velocities in all field strength are critical. These include the low-field mobility, saturation velocity in high field, and for some materials, peak velocity in medium field in the presence of the transferred-electron effect. In Si and GaAs, electrons have a higher low-field mobility than holes have. Therefore only n-channel FETs are used in microwave applications. The low-field mobility in GaAs is about five times higher than that of silicon, therefore the frequency f Tis expected to be higher in GaAs. For the same gate length, InP is expected to have even higherf, than GaAs because of its higher peak velocity. In any case, for these materials, FETs with gate lengths 0.5 pm or less will havef, in excess of 30 GHz. Maximum Frequency of Oscillation. Thef,,, is defined as the frequency at which ""y?) the unilateral gain is unity. The unilateral gain U goes down as square of frequency, 2, with r1is the input-to-output resistance ratio, 7.2 JFET AND MESFET = RG+ Rch+ RS Yl RDS and the channel resistance R,, is given byI6 R,, = -1 (3a3+ 15a2+ l O a + 2 ) ( 1 - a) gm 10(l+a)(l+2a)2 a is a measure of the drain bias with respect to VDsat, a = 1-- VD ‘Dsat ( vD vDsat>. So for the saturation region, a = 0 and R, = 1/5gm.The z3 is a time constant Z3 2 z R G C ~ D . For small r , , Eq. 64 reduces to the more-familiar form The unilateral gain will decrease at 6 dB/octave as the frequency increases. At fmax, unity power gain is reached. To maximize f,,,, the frequencyf Tand the resistance ratio RchlRDSmust be optimized in the intrinsic FET. In addition, the extrinsic resistances RG and Rs and the feedback capacitance C k D must also be minimized. Power-Frequency Limitations. For power applications, both high voltage and high current are required. These, however, demand device designs that are in conflict with one another, and in addition, they also compromise the speed, so a trade-off has to be considered. For high current, the total channel dose (NDXa)has to be high. To maintain high breakdown voltage, No cannot be too high and L cannot be too small. For a highfT, L has to be minimized and as a consequence, ND has to increase. The last con- straint comes about because of the following. For a gate electrode to have adequate control of the current transport across the channel, the gate length must be somewhat larger than the channel depth,I7 that is L - 2 Z. a So to reduce L,the channel depth a has to be reduced at the same time, which implies a higher doping level to maintain a reasonable current. Because of this, some scaling rules have been proposed. These include constant LND scaling, constant L”2ND scaling.I8 and constant L2ND~ca1ing.I~n practical Si and GaAs MESFETs, the highest doping level is about 5 x 1017~ m b-eca~use of breakdown phenomena. Using the simple velocity-saturation estimate of IDsaJZ= qNDuvs,and vs of 1x lo7 c d s , to maintain a current of 3 A/cm, this doping level limits the minimum gate length to about 0.1 pm, with a corresponding maximumf, of the order of 100 GHz. In high-power operation, the device temperature increases. This increase causes a reduction of the mobility20 and saturation velocity, since the mobility varies as 398 CHAPTER 7. JFETs, MESFETs, AND MODFETs [T(K)]-2 and velocity as [T(K)]-'.Therefore, the FET has negative temperature coefficient and will be thermally stable under high-power operation. The state-of-the-art power-frequency performance of GaAs FETs is shown in Fig. 14. A higher frequency range can be reached with MODFETs, at the expense of lower power. With further miniaturization to submicron dimensions, and with improved designs and reduction of parasitics, FETs of higher powers operated at higher frequencies can be made. Also with semiconductor materials of higher bandgaps such as Sic and GaN, the curve can be shifted upward. For GaN devices, the curve can be higher by more than tenfold in power.22 Noise Behavior. The MESFET and JFET are low-noise devices, because only majority carriers participate in their operations, and these carriers transport through the channel in the bulk and free of surface or interface scattering. However, in practical devices, extrinsic resistances are unavoidable, and these parasitic resistances are mainly responsible for the noise behavior. The equivalent circuit used for noise analysis is shown in Fig. 15. Noise sources i,: ind, eng,and ensrepresent the induced gate noise, induced drain noise, thermal noises of the gate resistance R, and source resistance R,, respectively. The e, and Z, are the signal source voltage and source impedance. The circuit within the dashed lines corresponds to the intrinsic FET. The noise figure is defined as the ratio of the total noise power to the noise power generated from the source impedance alone. So the noise figure depends also on the circuitry external to the device. There is an important parameter called the minimum noisefigure which is obtained with both the source impedance and load impedance being optimized for noise performance. This minimum noise figure for a practical device has been obtained from the equivalent circuit to be:24 100: EI 10, ag .: 0.1; \M\FET . .. ',MODFET I I 1 I I1111 10 I I I I IIIL 1 I0 Frequency (GHz) Fig. 14 State-of-the-art performance of power vs. frequency for GaAs FETs. Higher frequency range can be reached with MODFETs. (After Ref. 21 .) 7.2 JFET AND MESFET 399 r------ Intrinsic FET I 7 Drain0 mR,' Fig. 15 Equivalent circuit of an FET for noise analysis. (After Ref. 23.) where C, is a constant of value 2.5 s1F. Clearly for low-noise performance, one should minimize the parasitic gate resistance and source resistance. At a given frequency, the noise decreases with decreasing gate length (C& K L x z ) . We should be reminded that R, (see Fig. 13b) and g, are proportional to the device width 2,while Rs is inversely proportional to 2.This leads to decreasing noise with decreasing channel width. The graded-channel FET (Fig. 11) has been found to yield less noise (1 to 3 dB lower) than uniformly doped devices having the same geometry.' This difference in noise is related to g,. The reduction of g , (but not g,lC& forf T )for a gradedchannel FET gives superior noise performance. 7.2.4 Device Structures The schematic diagrams of high-performance MESFETs are shown in Fig. 16. The MESFET structures fall into two major categories: the ion-implanted planar structure and the recessed-channel (or recessed-gate) structure. All devices have a semiinsulating (SI) substrate for compound semiconductors such as GaAs. In the ion-implanted planar process (Fig. 16a), the active region is created by ion implantation to over-compensate the deep-level impurities in the SI-substrate. Naturally the active device is isolated vertically and horizontally by the semiinsulating material. To minimize the source and drain parasitic resistance, the deeper n+-implantations should be as close to the gate as possible. This is done by various self-aligned processes. In a gate-priority self-aligned process, the gate is formed first, and the source/drain ion implantation is self-aligned to the gate. In this process, since ion implantation requires high-temperature anneal for activation, the gate has to made of materials that can withstand high-temperature processing. Examples are Ti-W alloy, WSi,, and TaSi,. The second approach is ohmic-priority where the sourceldrain 400 CHAPTER 7. JFETs, MESFETs, AND MODFETs T-gate Source Gate Drain Source Drain (4 (b) Fig. 16 Basic MESFET structures: (a) Ion-implantedplanar structure. (b) Recessed-channel (or recessed-gate) structure. Inset shows a T-gate (or mushroom-gate) that can be used in both configurations. implantation and anneal are done before the gate formation. Such process relaxes the previous requirement on the gate material. In the recessed-channel process (Fig. 16b), the active layers are grown epitaxially over the SI-substrate. An intrinsic buffer layer is first grown and followed by an active channel layer. The buffer layer serves to eliminate defects duplicating from the semiinsulating substrate. Finally an epitaxial n+-layer is grown over the active n-channel to reduce the source and drain contact resistance. This n+-layer is selectively removed in the region between the source and the drain for gate formation. Sometimes, this etching process is monitored by measuring the current between source and drain for a more-precise control of the final channel current. One of the advantages of this recessed-channel structure is that the surface is further away from the n-channel layer so that surface effects such as transient response25and other reliability problems are minimized. One disadvantage of this scheme is the additional steps required for isolation which could be a mesa etching process (as shown) or an isolation implantation that converts the semiconductor into high-resistivity material. For superior microwave performance, the gate can be made into the shape of a T-gate or mushroom-gate as shown in the inset of Fig. 16. The shorter dimension at the bottom of the gate is the electrical channel length and it serves to optimizef, and g,, while the wider top portion reduces the gate resistance for an improvedf,, and noise figure. The JFET structures are similar to those of the MESFET, with the additional step of ap-n junction formed underneath the gate contact by ion implantation. JFETs are more suitable for power applications and seldom used in state-of-the-art high-frequency applications. Part of the reason is that the channel length from ap-n junction is more different to control and miniaturize compared to a metal gate. One common inherent shortcoming of both the MESFET and JFET is that the heavily doped source and drain regions cannot overlap the gate as in the case of a MOSFET (see Fig. 6 on 7.3 MODFET 401 p. 298). If they encroach the gate underneath, a short or leaky path would be formed between the gate and the source or drain. Because of this, the source and drain series resistance is higher than that in a MOSFET. 7.3 MODFET The modulation-doped field-effect transistor (MODFET) is also known as the highelectron-mobility transistor (HEMT), two-dimensional electron-gas field-effect transistor (TEGFET), and selectively doped heterojunction transistor (SDHT). Sometimes it is simply referred to by the generic name HFET (heterojunction field-effect transistor). The unique feature of the MODFET is the heterostructure, in which the wide-energy-gap material is doped and carriers diffuse to the undoped narrowbandgap layer at which heterointerface the channel is formed. The net result of this modulation doping is that channel carriers in the undoped heterointerface are spatially separated from the doped region and have high mobilities because there is no impurity scattering. Carrier transport parallel to the layers of a superlattice was first considered by Esaki and Tsu in 1969.26The development of MBE and MOCVD technologies in the 1970s made heterostructures, quantum wells, and superlattices practical and more accessible. Dingle et al. first demonstrated enhanced mobility in the AlGaAdGaAs modulation-doped superlattice in 1 9 7 St~orm~er~et al. subsequently reported similar effect using a single AlGaAs/GaAs heterojunction in 1979.28These studies were made on two-terminal devices without the control gate. This effect was applied to the field-effect transistor by Mimura et al. in 1980,29,3a0nd later by Delagebeaudeuf et al. in the same year.31Since then, the MODFET has been the subject of major research activities and has matured to commercial products as an alternative to MESFETs in high-speed circuits. For in-depth treatment of the MODFET, readers are referred to Refs. 32-35. The main advantage of modulation doping is the superior mobility. This phenomenon is demonstrated in Fig. 17 which compares mobilities in the bulk, relevant for MESFETs and JFETs, to that in the modulation-doped channel. It is seen here that since in a MESFET or JFET the channel has to be doped to a reasonably high level (> 1OI7 ~ m - ~th) e, modulation-doped channel has much higher mobilities at all temperatures. It is also interesting to compare the modulation-doped channel, which usually has an unintentional doping below 1014~ m - t~o ,lowly doped bulk samples, since in this case their impurity concentrations are similar. The bulk mobility as a function of temperature shows a peak but drops at both high temperature and low temperature (see Section 1.5.1 on p. 28). The decrease of bulk mobility with increase of temperature is due to phonon scattering. At low temperatures, the bulk mobility is limited by impurity scattering. It depends, as expected, on the doping level, and it also decreases with a decrease of temperature. In the modulation-doped channel, its mobility at temperatures above = 80 K is comparable to the value of a lowly doped bulk sample. However, mobility is much enhanced at lower temperatures. The mod- 402 CHAPTER 7. JFETs, MESFETs, AND MODFETs Fig. 17 Comparison of low-field electron mobility of modulation-doped 2-D channel to bulk GaAs at different doping levels. (After Ref. 36.) ulation-doped channel does not suffer from impurity scattering which dominates at low temperatures. This benefit stems from the screening effect of a two-dimensional electron gas, where its conduction path is confined to a small cross-section which is smaller than 10 nm with high volume density.33 7.3.1 Basic Device Structure The most-common heterojunctions for the MODFETs are the AlGaAs/GaAs, AlGaAdInGaAs, and InAlAs/InGaAs heterointerfaces. A basic MODFET structure based on the AlGaAs/GaAs system is shown in Fig. 18. It is seen here that the barrier layer AlGaAs under the gate is doped, while the channel layer GaAs is undoped. This electron gas SI-GaAs - Fig. 18 Typical structure of MODFET, using the basic AlGaAdGaAs system. 7.3 MODFET 403 is the principle of modulation doping such that carriers from the doped barrier layer are transferred to reside at the heterointerface and are away from the doped region to avoid impurity scattering. The doped barrier layer is typically around 30-nm thick. Very often, a &doped charge sheet is used within the barrier layer and placed close to the channel interface, instead of uniform doping. The top layer of n+-GaAs is for better source and drain ohmic contacts. These contacts are made from alloys containing Ge, such as AuGe. The sourceldrain deeper n+-regionsare formed either by ion implantation or introduced during the alloying step. Similar to MESFETs, the metal gate is sometimes made into the shape of a T-gate to reduce the gate resistance. Most MODFETs reported are n-channel devices for higher electron mobility. 7.3.2 I-VCharacteristics Based on the principle of modulation doping, the impurities within the barrier layer are completely ionized and carriers depleted away. Referring to the energy-band diagrams of Fig. 19, the potential variation within the depleted region is given by (see Section 2.2.3 on p. 88) for a general doping profile. For uniform doping, this built-in potential becomes VP = q2NEDY,z (73) For a planar-doped charge sheet nsh located at a distance of y , from the gate, this expression yields Metal AlGaAs (a) (b) Fig. 19 Energy-band diagrams for an enhancement-mode MODFET at (a) equilibrium and (b) onset of threshold. 404 CHAPTER 7. JFETs, MESFETs, AND MODFETs V P = q- nsky1 (74) 5 The advantage here, compared to the uniformly doped AlGaAs layer, is the reduction of traps that are believed to be responsible for the anomalous behavior of current collapse at low temperature. The close proximity of dopants to the channel also gives a lower threshold voltage. Like any other field-effect transistor, an important parameter is the threshold voltage, the gate bias at which the channel starts to form between the source and drain. From Fig. 19b, first-order approximation shows that this occurs when the Fermi level EF at the GaAs surface coincides with the conduction-band edge E,. This corresponds to the bias condition of: It can be seen here that by choosing the doping profile and barrier height vBnV,Tcan be varied between positive and negative values. The example shown in Fig. 19 has a positive VDand the transistor is called an enhancement-mode (normally-off) device, as opposed to a depletion-mode (normally-on) device. Once the threshold voltage is known, the rest of the analysis in deriving the I-V characteristics are similar to that for the MOSFETs. In getting to the final results here we skip some of the intermediate steps, and readers are referred to the MOSFET chapter for more-detailed derivations if necessary. With gate voltage larger than the threshold voltage, the charge sheet in the channel induced by the gate is capacitively coupled and is given by where c, = - ES (77) Yo+ AY and Ay is the channel thickness of the two-dimensional electron gas, estimated to be around 8 nm. When a drain bias is applied, the channel has a variable potential with distance and its value with respect to the source is designated as Adx).It varies along the channel from 0 at the source to V, at the drain. The channel charge as a function of position becomes The channel current at any location is given by ID(x>= ZQn(x>4x>. (79) Since the current is constant through out the channel, integrating the above equation from source to drain gives 7.3 MODFET 405 As for the other FETs, we derive the current equations with different assumptions on the velocity-field relationships. Constant Mobility. With constant mobility, the drift velocity is simply given by 4 x ) = P,,aX> Substituting Eq. 81 into Eq. 80 and with proper change of variable, we obtain The output characteristics for an enhancement-mode MODFET are shown in Fig. 20. In the linear region where V, << (V,VT), Eq. 82 is reduced to an ohmic relationship, At high V, Q,(L) at the drain is reduced to zero (Eq. 78), corresponding to the pinchoff condition, and current saturates with VD.This gives a saturation drain bias of VDsat = ' G - ' T (84) and a saturation drain current of From the above equation, the transconductance can be obtained, Fig. 20 Output characteristics of an enhancement-mode MODFET. 406 CHAPTER 7. JFETs, MESFETs, AND MODFETs (86) Field-Dependent Mobility. In state-of-the-art devices, current becomes saturated with VDbefore the pinch-off condition occurs, due to the fact that carrier drift velocity no longer is linearly proportional to the electric field. In other words, in high fields, the mobility becomes field dependent. For devices with high mobilities such as MODFETs, this phenomenon is more severe. Figure 21 shows the electron velocityfield relationship where a two-piece linear approximation is also shown with a critical field gCL. ow-field electron mobilities reported for the AlGaAdGaAs heterointerface are typically = 1O4 cm2/V-sat 300 K, = 2x 1O5 cm2/V-sat 77 K, and = 2x 1O6 cm2/V-s at 4 K. The mobility enhancement at low temperatures in a MODFET is very pronounced as discussed before. But the improvement of vsat low temperatures is much less, ranging from 30 to 100%. High mobility also implies low gC,and the drain bias needed to drive the device towards velocity saturation is reduced. From the MOSFET equations, we set M = 1 (p. 306) since the channel doping is very light. Equations 36 and 37 in the MOSFET chapter (Chapter 6 )become Velocity Saturation. In the case of short-channel devices, complete velocity saturation is approached and simpler equations can be used. The saturation current in this regime becomes with the transconductance of g =-d'Dsat dVG = ZC,V,. A 'z B "s +0 z 4 ij D gc Longitudinal field gx Fig. 21 u - 8 relationship for the channel charge. Transfer-electroneffect is shown for materials such as GaAs. Two-piece linear approximation is indicated. 7.3 MODFET 407 Notice that in this extreme case I,, is independent of L and gmis independent of L and V,. At large V,, the gm,as indicated in Fig. 20, starts to decrease. The AlGaAs/GaAs heterointerface can confine a maximum carrier density Q,/q of = 1x lo1, ern-,. Above this V, (1x1012q/Co= 0.8 V), charge is induced within the AlGaAs layer, whose mobility is much lower. 7.3.3 Equivalent Circuit and Microwave Performance For discussions on small-signal equivalent circuit, f7,f,,,, and noise, we can follow the analysis either in MOSFET or MESFETIJFET in the earlier part of this chapter. From the equivalent circuit, in the presence of parasitic source resistance, the extrinsic transconductance is degraded by The cutoff frequencyfT and the maximum frequency of oscillation f,,, are given by, = f m a x (93) The minimum noise figure is given as33 where C, = 1.6 sIF, a lower noise figure compared to the corresponding value of 2.5 s/F for GaAs MESFETs (Eq. 71). Note that since C& is proportional to L , devices with shorter channels have better noise performance. The speed of MODFETs is higher than that of MESFETs, due to the higher mobilities. Even though the saturation velocities of these devices are comparable, higher mobility pushes the device toward the performance limit of complete velocity saturation. So for the same channel length, higher mobility always gives somewhat higher current and transconductance. Some examples of analog applications are low-noise small-signal amplifiers, power amplifiers, oscillators, and mixers. For digital applications, there are high-speed logic and RAM circuits. MODFET also has superior noise performance compared to other FETs. This improved noise property comes from higher current and transconductance. Compared to the MESFET, the MODFET can support higher gate bias due to the additional barrier of the AlGaAs layer. It also has better scaling capability since it does not have the restriction associated with the channel depth (Lla 2 n,Eq. 70). Another advantage is lower-voltage operation because of the low gCneeded to drive 408 CHAPTER 7. JFETs, MESFETs, AND MODFETs the device into velocity saturation. One drawback of the MODFET is the limit of maximum charge-sheet density at the heterointerface which limits the maximum current drive. We have pointed out before that the difference between a MODFET and a HIGFET is the presence of dopants in the barrier layer. It is interesting then to see the advantage of introducing these dopants in the barrier layer. Figure 22 compares the energy-band diagrams of these two devices. The comparison is made at the condition of equal channel charge or channel current, at whatever gate bias necessary. Note that at such condition, the region from the channel to the right side of the devices are identical. The difference lies in the barrier layer and to its left. One can observe that the doping in the barrier layer has two main functions. First, the threshold voltage is lowered. Second, the built-in potential within the barrier layer I,+ increases the total barrier for carrier confinement. This higher barrier enables a higher gate bias before excessive gate current takes place. 7.3.4 Advanced Device Structures The major development effort for MODFETs has been on a channel material that can further improve the electron mobility. Instead of GaAs, In,Ga,-& has been pursued due to its smaller effective mass. Additional advantages include a larger AE, because of the smaller bandgap. Its higher satellite band has less transfer-electron effect that degrades the mobility. These advantages are found to be directly related to the indium contents: the higher the percentage, the higher the performance. Introduction of indium in InGaAs causes lattice mismatch to the GaAs substrate (see Fig. 32 on p. 56). However, growth of good-quality heteroepitaxial layer is still possible provided the epitaxial-layer thickness is under the so-called critical thickness (see discussion on p. 57), in which condition the epitaxial layer is under strain. Such technique yields a pseudomorphic InGaAs channel layer and the device is called pseudomorphic MODFET (P-MODFET or P-HEMT). Figure 23 summarizes the Doped barrier 2 - ~ electron gas Undoped barrier 2-r) electron gas (a) (b) Fig. 22 Comparison of (a) doped barrier layer (as in MODFET) and (b) undoped barrier layer (as in HIGFET), for the same amount of channel charge. 7.3 MODFET 409 MODFET P-MODFET M-MODFET AlGaAs t - = iGaAs substrate I InAlAs I AlGaAs GaAs substrate I InAlAs I InAlGaAs buffer u GaAs substrate r I~~~ nGaA..s (In = 53%) InP substrate = InGaAs (In = 53 - 80%) InP substrate (a) (b) (c) Fig. 23 Structures of (a) conventional unstrained MODFETs on GaAs and InP substrates, (b) pseudomorphic MODFETs (P-MODFETs), and (c) metamorphic MODFET (M-MODFET). Indium concentrations are indicated. In% range for conventional MODFETs and P-MODFETs, on both GaAs and InP substrates. On GaAs substrate, P-MODFETs can accommodate a maximum of 35% indium. On InP substrate, an unstrained conventional MODFET starts with 53% In, and its P-MODFETs can contain as high as 80% In. So MODFET performance on InP substrate is always higher. The penalty is the higher cost of the InP substrate. In addition, an InP substrate is more susceptible to breakage during processing, and the wafer size is also smaller. These contribute to even higher cost. In general, P-MODFETs are sensitive to changes in strain during processing. Thermal budget has to be minimized to prevent relaxation of the pseudomorphic layer and introduction of dislocations that reduce the carrier mobility. Yet another approach, depicted in Fig. 23c, is the latest innovation to obtain high In% on GaAs substrate. In this scheme, a thick buffer layer of graded composition is grown on the GaAs substrate. This thick buffer layer serves to transform the lattice constant gradually, from that of the GaAs substrate to whatever required for the subsequent growth of the InGaAs channel layer. In doing so, all the dislocations are contained within the buffer layer. The InGaAs channel layer is unstrained and dislocation-free. Such technique has permitted indium as high as 80%. The resultant MODFET is called metamorphic MODFET (M-MODFET). Another material system for MODFET that has attracted increased interest recently is based on the AlGaN/GaN heterojunction. GaN has high energy gap (3.4 eV) and is attractive for power applications because of a low ionization coefficient and thus high breakdown ~oltage.~O’ne interesting feature of the AlGaN/GaN system is the additional carriers coming from the effects of spontaneous polarization and piezoelectric polarization, apart from the modulation doping, resulting in higher 410 CHAPTER 7. JFETs, MESFETs, AND MODFETs current capability. In some cases, the AlGaN barrier layer is undoped and excess carrier concentration relies on these polarization effects. To conclude this section, we show some variations in device structures that have certain advantages. Figure. 24a shows the inverted MODFET structure where the gate is placed over the channel layer rather than the barrier layer which is now grown over the substrate directly. In modulation doping, the high-E, layer thickness determines the built-in potential I,+ (Eq. 72) and preferably cannot be too thin. The channel layer does not have this restriction and can be thinner than the barrier layer. This gives a higher gate capacitance and thus higher transconductance and fT. Another advantage is improved source and drain contact resistance since the contacts do not have to go through the high-E, layer. The quantum-well MODFET, sometimes called a double-heterojunction MODFET, is shown in Fig. 24b. Because there are two parallel heterointerfaces, the maximum charge sheet and current are doubled. Another advantage is that the channel is sandwiched by two barriers, and the carriers have better confinement. Multiple-quantum-well structures also have been fabricated based on this principle. In the superlattice MODFET, the superlattice is used as the barrier layer (Fig. 24c). Within the superlattice, the narrow-Eg layers are doped while the wider-E, layers are undoped. This structure eliminates traps in the AlGaAs layer, and also the parallel conduction path within this doped AlGaAs layer. 2-D electron gas Source 2-D electron gas Gate Drain n-AIGaAs Source SI-GaAs (a) Gate Drain n-GaAd i-AlGaAs swerlattice SI-GaAs (b) SI-GaAs (c) Fig. 24 Some variations of MODFET structures: (a) Inverted MODFET. (b) Quantum-well MODFET. (c) SuperlatticeMODFET. REFERENCES 411 REFERENCES 1. W. Shockley, “A Unipolar Field-Effect Transistor,” Proc. IRE,40, 1365 (1952). 2. G. C. Dacey and I. M. Ross, “Unipolar Field-Effect Transistor,” Proc. IRE,41,970 (1953). 3. G. C. Dacey and I. M. Ross, “The Field-Effect Transistor,” Bell Syst. Tech. J., 34, 1149 (1955). 4. C. A. Mead, “Schottky Barrier Gate Field-Effect Transistor,” Proc. IEEE, 54,307 (1966). 5. W. W. Hooper and W. I. Lehrer, “An Epitaxial GaAs Field-Effect Transistor,” Proc. IEEE, 55, 1237 (1967). 6. K. Lehovec and R. Zuleez, “Voltage-Current Characteristics of GaAs JFETs in the Hot Electron Range,” Solid-State Electron., 13, 1415 (1970). 7. R. E. Williams and D. W. Shaw, “Graded Channel FET’s Improved Linearity and Noise Figure,” IEEE Trans. Electron Dev., ED-25, 600 (1978). 8. J. Ruch, “Electron Dynamics in Short Channel Field Effect Transistors,” ZEEE Trans. Electron Dev., ED-19,652 (1972). 9. K. Lehovec and R. Miller, “Field Distribution in Junction Field Effect Transistors at Large Drain Voltages,”IEEE Trans. Electron Dev., ED-22,273 (1975). 10. H. Mizuta, K. Yamaguchi, and S. Takahashi, “Surface Potential Effect on Gate-Drain Ava- lanche Breakdown in GaAs MESFET’s,” IEEE Trans. Electron Dev., ED-34,2027 (1987). 11. R. J. Trew and U. K. Mishra, “Gate Breakdown in MESFET’s and HEMT’s,” IEEE Elec- tron Dev. Lett., EDL-12, 524 (1991). 12. A. W. Ludikhuize, “A Review of RESURF Technology,” Proc. 12th Int. Symp. Power Semiconductor Devices & ICs, p. 11, 2000. 13. R. R. Bockemuehl, “Analysis of Field-Effect Transistors with Arbitrary Charge Distribu- tion,” IEEE Trans. Electron Dev., ED-l0,31 (1963). 14. R. E. Williams and D. W. Shaw, “GaAs FETs with Graded Channel Doping Profiles,” Electron. Lett., 13, 408 (1977). 15. R. A. Pucel, “Profile Design for Distortion Reduction in Microwave Field-Effect Transis- tors,” Electron. Lett., 14, 204 (1978). 16. W, Liu, Fundamentals of Ill- V Devices: HBTS, MESFETs, and HFETS/HEMTs,Wiley, New York, 1999. 17. T. J. Maloney and J. Frey, “Frequency Limits of GaAs and InP Field-Effect Transistors at 300 K and 77 K with Typical Active Layer Doping,” IEEE Trans. Electron Dev., ED-23, 519 (1976). 18. K. Yokoyama, M. Tomizawa, and A. Yoshii, “Scaled Performance for Submicron GaAs MESFET’s,” IEEE Electron Dev. Lett., EDL-6,536 (1985). 19. M. F. Abusaid and J. R. Hauser, “Calculations of High-speed Performance for Submicrometer Ion-Implanted GaAs MESFET Devices,” ZEEE Trans. Electron Dev., ED-33, 913 (1986). 20. L. J. Sevin, Field Effect Transistors, McGraw-Hill, New York, 1965. 2 1. R. J. Trew, “Sic and GaN Transistors-Is There One Winner for Microwave Power Applications?” Proc. IEEE, 90, 1032 (2002). 412 CHAPTER 7. JFETs, MESFETs, AND MODFETs 22. J. Shealy, J. Smart, M. Poulton, R. Sadler, D. Grider, S. Gibb, B. Hosse, B. Sousa, D. Halchin, V. Steel, et al., “Gallium Nitride (GaN) HEMT’s: Progress and Potential for Commercial Applications,” IEEE GaAsIntegrated Circuits symp., p. 243,2002. 23. R. A. Pucel, H. A. Haus, and H. Statz, “Signal and Noise Properties of GaAs Microwave Field-Effect Transistors,” in L. Martin, Ed., Advances in Electronics and Electron Physics, Vol. 38, Academic, New York, p. 195, 1975. 24. H. Fukui, “Optimal Noise Figure of Microwave GaAs MESFETs,” IEEE Trans. Electron Dev., ED-26, 1032 (1979). 25. S. C. Binari, P. B. Klein, and T. E. Kazior, “Trapping Effects in GaN and S i c Microwave FETs,” Proc. IEEE, 90, 1048 (2002). 26. L. Esaki and R. Tsu, “Superlattice and Negative Conductivity in Semiconductors,” IBM Research, RC 2418, March 1969. 27. R. Dingle, H. L. Stormer, A. C. Gossard, and W. Wiegmann, “Electron Mobilities in Modulation-Doped Semiconductor Heterojunction Superlattices,” Appl. Phys. Lett., 33, 665 (1978). 28. H. L. Stormer, R. Dingle, A. C. Gossard, W. Wiegmann, and M. D. Sturge, “Two-Dimensional Electron Gas at a Semiconductor-Semiconductor Interface,” Solid State Commun., 29, 705 (1979). 29. T. Mimura, S. Hiyamizu, T. Fuji, and K. Nanbu, “A New Field-Effect Transistor with Selectively Doped GaAsln-AIxGal,As Heterojunctions,” Jpn. J. Appl. Phys., 19, L225 (1980). 30. T. Mimura, “The Early History of the High Electron Mobility Transistor (HEMT),” IEEE Trans. Microwave Theory Tech., 50,780 (2002). 3 1. D. Delagebeaudeuf, P. Delescluse, P. Etienne, M. Laviron, J. Chaplart, and N. T. Linh, “Two-Dimensional Electron Gas M.E.S.F.E.T. Structure,” Electron. Lett., 16,667 (1980). 32. H. Daembkes, Ed., Modulation-Doped Field-Effect Transistors: Principle, Design and Technology,IEEE Press, Piscataway, New Jersey, 1991. 33. H. Morkoc, H. Unlu, and G. Ji, Principles and Technology of MODFEE: Principles, Design and Technology,vols. 1 and 2, Wiley, New York, 1991. 34. C. Y. Chang and F. Kai, GaAs High-speed Devices, Wiley, New York, 1994. 35. M. Golio and D. M. Kingsriter, Eds, R F and Microwave Semiconductor Devices Hand- book, CRC Press, Boca Raton, Florida, 2002. 36. P. H. Ladbrooke, “GaAs MESFETs and High Mobility Transistors (HEMT),” in H. Thomas, D. V. Morgan, B. Thomas, J. E. Aubrey, and G. B. Morgan, Eds., Gallium Arsenidefor Devices and Integrated Circuits, Peregrinus, London, 1986. 37. U. K. Mishra, P. Parikh, and Y. F. Wu, “AlGaN/GaN HEMTs-An Overview of Device Operation and Applications,” Proc. IEEE, 90, 1022 (2002). PROBLEMS 1. For a JFET with a power-law doping N =ND2xwnhere ND2and n are constants. Find IDvs. Vcand g, when n -+ co. PROBLEMS 413 2. An n-channel GaAs MESFET has been fabricated on semiinsulating substrate. It has a uniformly doped channel of N, = IOI7 ~ m - w~it,h bBB=n0.9 V, u = 0.2 pm, L = 1 pm, and Z = 10 pm. (a) Is this an enhancement- or depletion-mode device? (b) Find the threshold voltage. (c) Find the saturation current at V , = 0 (for constant mobility of 5,000 cm2N-s). 3. Derive Eq. 19 by substituting vbi in Eq. 15 to Eq. 17. 4. Design a GaAs MESFET with a maximum transconductance of 200 mS/mm and a drain saturation current ZDSatof 200 d m m at zero gate-source bias. Assume,,Z = ,6(V, - VT)2 and p- zp&,/2aL, p = 5,000 cm2N-s, L = 1 pm, and vbi = 0.6 v. 5. Show that (a) for a MESFET the measured drain conductance in the linear region is given by [/,g 1+(R,+R,)g,,], and (b) the measured transconductance in the saturation region is given by gm/(l+Rgm)where R, and R, are the source and drain resistance, respectively. 6. An InP MESFET has N, = 2xIOi7~ m -L~=; 1.5 pm, L/u = 5, and Z = 75 pm. Assume us= 6 ~ 1 c0d~s , vbi = 0.7 V. Using the saturated-velocity model, find the cutoff frequency for V , = -1 V and VD= 0.2 V (at which the channel near the drain is just pinched of€). 7. For very-large-scale integrated circuits, the maximum allowed power per MESFET gate is 0.5 mW. Assume a clock frequency of 5 GHz and a node capacitor of 32 fF,find the upper limit of VDD(in volts). 8. An InP MESFET has No = lOI7~ m -L~=, 1.5 pm, a = 0.3 pm, Z = 75 pm. Assume us= 6 ~ 1 c0m~/s, vbj = 0.7 V, applied gate voltage = -1 V, and &, = 1 2 . 4 ~F~ro. m the saturationvelocity model, find the cutoff frequency. 9. Find the thickness of the undoped spacer layer d,, such that the two-dimensional electron gas concentration of an AIGaAdGaAs heterojunction is 1 . 2 5 l~o1*cm-2 at zero gate bias. Assume that in the n-AIGaAs, the first 50 nm is doped to 1x 10I8~ m - a~nd, the remaining layer of thickness d, is undoped. The Schottky bamer height is 0.89 V, AE,/q = 0.23 V, and the dielectric constant of AlGaAs is 12.3. 10. (a) Find the threshold voltages of a conventional and a delta-doped heterostructure AIGaAs-GaAs FETs. (b) Evaluate the variations of these threshold voltages for two-monolayer fluctuations in AlGaAs layer thickness. Assuming that one monolayer = 3 8, in AIGaAs, the Schottky bamer height is 0.9 V, the conduction-band discontinuity is 0.3 eV, the uniform doping in the conventional HEFT is l0l8 ~ m w-ith~ a thickness of 40 nm, the delta doping is located 40 nm from the metalsemiconductor interface, with a sheet charge density of 1 . 51~0l2cm-2, and the dielectric permittivity for AlGaAs is assumed to be 10-l2 F/cm. 11. In an AlGaAsiGaAs MODFET, the n-type Al,,,Ga,,,As layer is doped to 1OI8~ m - a~nd, has a thickness of 50 nm. Assume an undoped spacer layer of 2 nm, a barrier height of 0.85 eV, and a conduction-band discontinuity of 0.22 eV. The dielectric constant for the ternary is 12.2. Find the two-dimensional electron concentration at the source for V, = 0. 12. Consider an AIGaAs/GaAs MODFET with a 50-nm AlGaAs and 10-nmundoped AlGaAs spacer. Assume the threshold voltage is -1.3 V, No = 5 ~ 1 0~’ m~ - A~E,,= 0.25 eV, the channel width is 8 nm, and the dielectric constant is 12.3. Calculate the Schottky barrier height and the 2-D electron gas concentration at V, = 0. Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. NEGATIVE-RESISTANCE AND POWER DEVICES + Chapter8 Tunnel Devices + Chapter9 IMPATT Diodes + Chapter 10 Transferred-Electron and Real-Space-Transfer Devices + Chapter 11 Thyristors and Power Devices Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. Tunnel Devices 8.1 INTRODUCTION 8.2 TUNNEL DIODE 8.3 RELATED TUNNEL DEVICES 8.4 RESONANT-TUNNELING DIODE 8.1 INTRODUCTION In this chapter we consider devices based on quantum-mechanical tunneling. In the classical sense, carriers having energy smaller than some potential barrier height are confined or stopped by the barrier completely. In quantum mechanics, the wave nature of carriers are considered, and the wave does not terminate abruptly at the boundary of the barrier. As a result, not only can the carriers have finite probability of existence inside the barrier, they can leak through the barrier if the barrier width is thin enough. This leads to the concept of tunneling probability and tunneling current. Basic tunneling phenomenon has been discussed in Section 1.5.7 where tunneling probability is introduced. The tunneling process and devices based on this phenomenon have some interesting properties. First, the tunneling phenomenon is a majority-carrier effect, and the tunneling time of carriers through the potential energy barrier is not governed by the conventional transit time concept ( z = W h ,where W is the barrier width and u is the carrier velocity), but rather by the quantum transition probability per unit time which is proportional to exp[-2(k(O))W], where ( 4 0 ) )is the average value of momentum encountered in the tunneling path corresponding to an incident carrier with zero transverse momentum and energy equal to the Fermi energy. Reciprocation gives the tunneling time proportional to exp[2(k(O))w. This tunneling time is very short, permitting the use of tunnel devices well into the millimeter-wave region. Secondly, since the tunneling probability depends on the available states of both the originating 41 7 418 CHAPTER 8. TUNNEL DEVICES side and the receiving side, tunneling current is not monotonically dependent on the bias, and negative differential resistance can result. A perceived drawback of tunnel devices might be the low current density allowed, but in fact tunnel devices can have substantial current densities exceeding 1.5 mA/pm2 in SiGe interband tunnel diodes2 and 4.5 mA/pm2 in InP-based resonant-tunneling diode^.^ For this reason, investigation of integrated tunnel diode and transistor circuits has continued, especially to enable power reduction through the use of more efficient circuit top~logies.~ In this chapter, the two main tunnel devices considered are the tunnel diode and the resonant-tunneling diode. Originally when it was first discovered, the tunnel diode seemed to have great potential. Time has shown that its application in the real market has been very limited. This is due to the difficulty in fabrication and reproducibility, especially if incorporated in integrated circuits because abrupt and high doping profiles are called for. The tunnel diode is now being replaced by the Gunn diode and the IMPATT diode as oscillators, and by FETs as switching elements. The more recent resonant-tunneling diode brings up another form of tunneling that is fundamentally interesting. The phenomenon of resonant tunneling has also been incorporated in many other devices and one example will be given at the end of the chapter. 8.2 TUNNEL DIODE The tunnel diode was discovered by L. Esaki in 1958 and is often called the Esaki diode.5As part of his Ph.D. dissertation work, Esaki was studying heavily doped germanium p-n junctions for application in high-speed bipolar transistors in which a narrow and heavily doped base was r e q ~ i r e d . ~H-e~discovered an anomalous currentvoltage characteristic in the forward direction, that is, a negative-differential-resistance region (negative dlldV)over part of the forward characteristics. Esaki explained this anomalous characteristic by the quantum tunneling concept and obtained reasonable agreement between the tunneling theory and the experimental results. Subsequently tunnel diodes were demonstrated by researchers on other semiconductor materials, such as GaAsgand InSb9 in 1960, Siloand InAs" in 1961, and GaSbI2 and InP13 in 1962. A tunnel diode consists of a simple p-n junction in which bothp- and n-sides are degenerate (i.e., very heavily doped with impurities) and in sharp transition. Figure 1 shows a schematic energy diagram of a tunnel diode in thermal equilibrium. Because of the high dopings the Fermi levels are located within the allowed bands. The amount of degeneracy, VA and Vl,, is typically a few kT/q, and the depletion-layer width is of the order of 10 nm or less, which is considerably narrower than the con- ventional p-n junction. [In this chapter we use VI, and % (= -V, and -Vp) to give positive values and to be consistent with notations in other chapters.] Figure 2a shows typical static current-voltage characteristics of a tunnel diode. In the reverse direction (p-side negative bias with respect to n-side) the current increases monotonically. In the forward direction the current first increases to a maximum 8.2 TUNNELDIODE 419 Fig. 1 Energy-band diagram of tunnel diode in thermal equilibrium. Vp and V;, are degeneracies on the p-side and n-side respectively. value (peak current or Zp)at a peak voltage V,, then decreases to a minimum value I , at a valley voltage V,. For voltages much larger than V,, the current increases exponentially with the voltage. The static characteristics are the result of three current components: band-to-band tunneling current, excess current, and diffusion current (Fig. 2b). We first discuss qualitatively the tunneling processes at absolute zero temperature, using the simplified band structure in Fig. 3 which shows band alignment of the p - and n-sides when a bias is a~p1ied.Tl~he corresponding current is also designated Diffusion / j"/,' Excess '4' * 0 V Fig. 2 (a) Static current-voltage characteristics of a typical tunnel diode. ,Z and V, are the peak current and peak voltage. Zvand Vvare the valley current and valley voltage. (b) The total static characteristics are broken down into three current components. 420 CHAPTER 8. TUNNEL DEVICES LEC Fig. 3 Simplified energy-band diagrams of tunnel diode at (a) thermal equilibrium, zero bias; (b) forward bias Vsuch that peak current is obtained; (c)forward bias approaching valley current; (d) forward bias with diffusion current and no tunneling current; and (e)reverse bias with increasing tunneling current. (After Ref. 14.) by the dot on the I-V curve. Note that the Fermi levels are within the allowed bands of the semiconductor, and at thermal equilibrium (Fig. 3a) the Fermi level is constant across the junction. Above the Fermi level there are no filled states (electrons) on either side of the junction, and below the Fermi level there are no empty states (holes) available on either side of the junction. Hence, the net tunneling currents at zero applied voltage is zero. When a voltage is applied, the electrons may tunnel from the conduction band to the valence band, or vice versa. The necessary conditions for tunneling are: ( 1 ) occupied energy states exist on the side from which the electron tunnels; (2) unoccupied energy states exist at the same energy level on the side to which the electron can tunnel; (3) the tunneling potential barrier height is low and the barrier width is small enough that there is a finite tunneling probability; and (4) the momentum is conserved in the tunneling process. When a forward bias is applied (Fig. 3b), there exists a common band of energies in which there are filled states on the n-side and unoccupied states on thep-side. The electrons can thus tunnel from the n-side to thep-side and energy is conserved. When the forward voltage is further increased, this band of common energies decreases (Fig. 3c). If forward voltage is applied such that the bands are uncrossed, that is, the edge of the n-type conduction band is exactly opposite to the top of thep-type valence band, there are no available states opposite to filled states. Thus at this point and 8.2 TUNNELDIODE 421 onward the tunneling current can no longer flow. With still further increase of the voltage the normal diffusion current and excess current start to dominate (Fig. 3d). One thus expects that as the forward voltage increases from zero, the tunneling current increases from zero to a maximum Zp and then decreases to zero when V= Vl, + VA,where Vis the applied forward voltage, Vl, the amount of degeneracy on the n-side [ Vl, = (EFn- Ec)/q], and VA is the amount of degeneracy on thep-side [ V; = (E, - E,,)/q], as shown in Fig. 1. The decreasing current after the peak gives rise to the negative differential resistance. The Fermi levels for degenerate semiconductors are inside the conduction band or valance band, and they are given by (see Section 1.4.1);15 where mdeand mdhare density-of-state effective masses for electrons and holes. Figure 3e shows electron tunneling from the valence band into the conduction band when a reverse bias is applied. In this direction, the tunneling current increases with bias indefinitely, and there is no negative differential resistance. The tunneling process can be either direct or indirect, and these are demonstrated in Fig. 4 where the E-k relationships are superimposed on the classical turning points of the tunnel junction. Figure 4a shows direct tunneling when the electrons can tunnel from the vicinity of the conduction-band minimum to the vicinity of the valence-band maximum, and at the same time without a change of momentum (in k-space). For direct tunneling to occur, the conduction-band minimum and the valence-band maximum must have the same momentum. This condition can be fulfilled by semiconductors that have a direct bandgap, such as GaAs and GaSb. This condition can also be fulfilled by semiconductors with indirect bandgap, such as Si and Ge, when the applied voltage is sufficiently large that electrons tunnel from the higher direct conduction-band minimum (rpoint) rather than from the lower satellite minimum. l6 Indirect tunneling occurs in semiconductors of indirect bandgap, i.e., the conduction-band minimum does not align at the same momentum as the valence-band maximum (Fig. 4b) in the E-k relationship. To conserve momentum, the difference in momentum between the conduction-band minimum and the valence-band maximum must be supplied by scattering agents such as phonons or impurities. For phononassisted tunneling, both their energy and momentum must be conserved; that is, the sum of the phonon energy and the initial electron energy is equal to the final electron energy after it has tunneled, and the sum of the initial electron momentum and the phonon momentum (hk,) is equal to the final electron momentum after it has tunneled. In general, the probability for indirect tunneling is much lower than the probability for direct tunneling when direct tunneling is possible. Also, indirect tunneling involving several phonons has a much lower probability than that with only a single phonon. 422 CHAPTER 8. TUNNEL DEVICES /I\ I L-+\k Fig. 4 Direct and indirect tunneling processes demonstrated by E-k relationship superimposed on the classical turning points (x = 0 and x2)of the tunnel junction. (a) Direct tunneling process with kmin= k,,,,,. (b) Indirect tunneling process with kminf kma. 8.2.1 Tunneling Probability and Tunneling Current In this section we focus on the component of the tunneling current. When the electric field in a semiconductor is sufftciently high, on the order of lo6Vlcm, a finite probability exists for interband quantum tunneling, i.e., direct transition of electrons from the conduction band into the valence band, or vice versa. The tunneling probability T, (see Section 1.5.7) can be given by the WKB (Wentzel-Kramers-Brillouin) appr~ximationl~ r,= exp[-L[lx(xlldi] (2) where (k(x)(is the absolute value of the wave vector of the carrier inside the barrier, and x = 0 and x2 are the classical boundaries shown in Fig. 4. 8.2 TUNNELDIODE 423 The tunneling of an electron through a forbidden band is formally the same as a particle tunneling through a potential barrier. Examination of Fig. 4 indicates that the tunnel barrier is of the triangular shape that is shown explicitly in Fig. 5. We start with the general equation for the E-k relationship k(x) = ~ ~ ( P E - E , ) (3) where PE is the potential energy. For tunneling consideration, the incoming electron has an PE equal to the bottom of the energy gap. The value inside the square root is thus negative and k is imaginary. Furthermore, the varying conduction-band edge E, can be expressed in terms of the electric field 2?.The wave vector inside the triangular barrier is given by k ( x ) =)-/ (4) Substituting Eq. 4 into Eq. 2 yields ( 4 5 9 Since for a triangular barrier with a uniform field, x2 = E$gq, we have the result T,= exp - From the result it is clear that to obtain large tunneling probability, both the effective mass and the bandgap should be small and the electric field should be large. We next proceed to calculate the tunneling current and shall present the first-order approach using the density of states in the conduction band and valence band. We shall also assume direct tunneling where the momentum is conserved in direct bandgap. At thermal equilibrium, the tunneling current from the conduction band to the empty states of the valence band and the current I, from the valence Potential C (4 (b) Fig. 5 (a) Tunneling in a tunnel diode can be analyzed by (b) a triangular potential barrier. 424 CHAPTER 8. TUNNEL DEVICES band to the empty states of the conduction band should be balanced. Expressions for Zc+, and I, are formulated as follows: I 1, + v = Cl F,(E)Nc(E)T,[ 1 - F d E ) I N V ( W E9 (74 i I,, c = Cl FdE)Nv(E)T,[1 -Fc(E)INc(E)dE, (7b) where C, is a constant, the tunneling probability Tt is assumed to be equal for both directions, FJE) and FLE) are the Fermi-Dirac distribution functions, and Nc(E)and N,(E) are the density of states in the conduction band and valence band, respectively. When the junction is forward biased, the net tunneling current I, is given by clIEcn 4 = I,, v-Iv+c = VP [Fc(E)-F,(E)I T,NC(E)N”(E)dE. (8) Note that the limits of integration are from E, of the n-side (E,) to E , of the p-side (E,,,). Rigorous manipulation of Eq. 8 leads to the following result** where the integral D is ID = [F,(E)-F,(E)] and the average electric field is given by where lybiis the built-in potential. In Eq. 10, E, is the smaller of El and E2 (Fig. 4a), and E is given by zmg E = &9f@ ‘ For a Ge tunnel diode, the appropriate effective mass in Eq. 9 is given by19 m* = 2(-+1-;) 1 -1 (13) me mlh for tunneling from the light-hole band to the (000) conduction band, where mTh is the light-hole mass (= 0.044mJ and mi is the (000) conduction-band mass (= 0.036mJ. For tunneling in the (100) direction to the (111) minima, the effective mass is given by 8.2 TUNNELDIODE 425 where m; = 1.6m0and mf = 0.082m0are the longitudinal and transverse masses of the (111) minima. The exponents in Eq. 9 differ, however, by only 5% in these two cases. The quantity D, Eq. 10, is an overlap integral which modulates the shape of the I-V curve. It has the dimensions of energy and it depends on the temperature and the degeneracy V; and V' At T = 0 K, both Fc and F, are step functions. Figure 6 shows the quantity Dp:in relative scale versus the forward voltage for the case Vl, > . The drop of D to zero corresponds to the valley voltage and it occurs at vv = v; + v;. The prefactor in Eq. 9 gives an idea on the magnitude of the tunneling current. Figure 7 plots the peak current calculated from Eq. 9 for several Ge tunnel diodes, together with experimental values that show very good agreement. It is difficult to get the whole I- Vcharacteristics of the tunneling current because the analytical solution of Eq. 9 is complicated. However, the tunneling current has been found to fit an empirical formula quite well, given in the form of; where Ipand V, are the peak current and peak voltage as defined in Fig. 2. Knowing the peak current, the critical parameter remaining is the peak voltage. This peak voltage can be obtained by a different approach. In this approach, we find the carrier profiles of the electrons in the conduction band in the n-side, and holes in the valence band in the p-side. Under bias, when the peaks of these two profiles line up at the same energy, this is the peak voltage for the peak tunneling current. This concept is demonstrated in Fig. 8. The carrier profile is given by the product of occupancy and density of states. For electrons and holes, they are given by; n(E) = FC(EW,(E)? (17a) P(E) = [1 -F,(E)INv. (17b) For degenerate n-type semiconductor, the electron profile can be written as20 A m ) n(E) = 8z ( m*)3/2 h3{ 1 + exp [( E -E,)/kT] } The energy for the peak concentration can be obtained by differentiating Eq. 18 with respect to E. The resultant equations cannot be solved explicitly, but it has been shown that with good approximation, the energy for maximum electron density occurs at the energy level of 2o A similar approach and result can be obtained for thep-side; Fig. 6 Integral D (relative scale) vs. forward voltage for 0 v; + v', direct tunneling with small $.? and Vl, > V; . (After Ref. 18.) n+-side 426 Fig. 7 Peak tunneling current density vs. effective doping concentration of Ge tunnel diodes. The dashed line is calculated from Eq. 9. (After Refs. 20 and 21.) Fig. 8 Density profiles for electrons and holes in n-type and p-type degenerate semiconductors. Em, and E, are their peak energies. 8.2 TUNNELDIODE 427 Em, = E F p 4+VT' . The peak voltage is simply the bias necessary to align these two peak energies, given by Vp = (Emp-Emn)/q -- v;+ V' 3. Figure 9 shows the position of the peak voltage as a function of the degeneracy Vk and V i for Ge tunnel diodes. Note that the peak voltage shifts toward higher values as the doping increases. The experimental values of Vpagree reasonably well with Eq. 20. Up to now we have not considered the requirement of the conservation of momentum. This could have two effects both of which will reduce the tunneling probability and tunneling current. The first effect is indirect tunneling for indirect bandgap materials where the change of momentum in k-space has to be compensated by some scattering effects, such as phonon scattering and impurity scattering. For phonon-assisted indirect tunneling, the tunneling probability is reduced by a multi- plier to Eq. 6, except that in Eq. 6, Eg is to be replaced by Eg+ Ep where Ep is the phonon energy.18,22The expression for the tunneling current is similar in form to Eq. 9 but its magnitude is much lower. So the readers are reminded that for indirect tunneling, the equations presented in this chapter have to be modified. The second effect associated with momentum is its vector direction in relationship to the direction of tunneling. In previous discussion all the kinetic energy is assumed to be in the direction of tunneling. In reality, we have to divide the total energy into 0 Fig. 9 Variation of peak voltage of Ge tunnel diodes as a function of the sum V; + VL. (After Refs. 20 and 2 1.) 428 CHAPTER 8. TUNNEL DEVICES Ex and E,, where EL is the energy associated with momentum perpendicular to the direction of tunneling (or the transverse momentum) and Ex is the energy associated with momentum in the tunneling direction; E = E x + E , = h<2+k-2, h2kf 2mx 2m; where the subscripts x and Idesignate their components in the parallel and perpen- dicular directions to the tunneling. Considering that only the component Ex contributes to the tunneling process, the tunneling probability is reduced by the amount of E , ,to the value of In other words, perpendicular energy further reduces the transmission by the factor of the second exponential term, a measure of the transverse momentum. 8.2.2 Current-Voltage Characteristics As shown in Fig. 2b, the static I-Vcharacteristic is the result of three current components: the tunneling current, the excess current, and the diffusion current. For an ideal tunnel diode, the tunneling current decreases to zero at biases where V2 ( v', + V i); for larger biases only normal diode currents caused by forward injection of minority carriers flow. In practice, however, the actual current at such biases is considerably in excess of the normal diode current, hence the term excess current. The excess current is mainly due to carrier tunneling by way of energy states within the forbidden gap. The excess current is derived with the help of Fig. 10, where some examples of possible tunneling routes are shown.1° An electron could drop down from C to an empty level at B, from which it could tunnel to D (route CBD).Alternatively, the electron starting at C in the conduction band might tunnel to an appropriate local level at n v' P Fig. 10 Band diagram illustrating mechanisms of tunneling via states in the forbidden gap for the excess current. (After Ref. 10.) 8.2 TUNNELDIODE 429 A, from which it could then drop down to the valence band D (route CAD).A third variant is a route such as CABD,where the electron dissipates its excess energy in a process that could be called impurity-band conduction between A and B. A fourth route that should also be included is a staircase from C to D. It consists of a series of tunneling transitions between local levels together with a series of vertical steps in which the electron loses energy by transferring from one level to another, a process made possible when the concentration of intermediate levels is sufficiently high. The first route CBD can be regarded as the basic mechanism, while the other routes are simply more-complicated modifications. Let the junction be at a forward bias K and consider an electron making a tun- neling transition from B to D. The energy E, through which it must tunnel is given by E,=Eg+q(Vi+ VA)-qV = q ( v b i - v> (23) where vbj is the built-in potential. The tunneling probability T,for the electron on the level at B can be given by an expression the same as Eq. 6 ( TI = exp - 4 5 2 ' 2 ) except here Eg is replaced by Ex and the appropriate mass m: should be used. Furthermore, let the volume density of the occupied levels at B be 0,. Then the excess current density will be given by J, = C,D, T, where C, is a constant. It is assumed that the excess current will vary predominantly with the parameters in the exponent of TIrather than with those in the factor 0,. Substituting Eqs. 23,24, 11 into Eq. 25 yields the expression for the excess current:I0 J,=C,D,exP{-C,[E,+q(Vi+ VA)-qVJ) (26) where C, is another constant. Equation 26 predicts that the excess current will increase with the volume density of bandgap levels (through D,), and also increase exponentially with the applied voltage V(provided that qV << Eg). Equation 26 can also be rewritten as2, J, = J,exp[C,(V- Vv)l (27) where Jvis the valley current density at the valley voltage V , and C4 is the prefactor in the exponent. Experimental results of In(J,) versus V for common tunnel diodes exhibit linear relationships in good agreement with Eq. 27. Note that there is no negative differential resistance in this type of tunneling. The difhsion current is the familiar minority-carrier injection current in p-n junctions: Jd = J0[exp($ - 11 430 CHAPTER 8. TUNNEL DEVICES where J, is the saturation current density given in Chapter 2 (Eq. 64). The complete static current-voltage characteristic is the sum of the three current components: J = J ,. + J.r. + J .d. JPV +J,exp[C4( V - V,)] +Joexp(c) kT . Each component dominates the current in some voltage range. The tunneling current’s contribution to the total current is significant for V < V, the excess current’s contribution is significant for V - V , and the contribution of the diffusion current is significant for V> V , Figure 11 shows a comparison of the typical current-voltage characteristics of Ge, GaSb, and GaAs tunnel diodes at room temperature. The current ratios of IJIVare 8:1 for Ge, 12:1 for GaSb,24and 28: 1 for G ~ A sT.u~nn~el diodes have been made in many other semiconductors, such as Si with a current ratio of about 4:1.26 The ultimate limitation on the ratio depends on (1) the peak current, which depends on the dopings, effective tunneling mass, and the bandgap; and (2) the valley current, which depends on the distribution and concentration of energy levels in the forbidden gap. So the ratio for a given semiconductor can be increased by increasing the doping concentrations on both n- and p-sides, increasing the sharpness of their profiles, and minimizing defect densities. We shall briefly consider the I- Vcharacteristics resulting from the effects of temperature, electron bombardment, and pressure. The temperature variation of the peak current can be explained by the change of the integral D and Eg in Eq. 9. At high concentrations the temperature effect on D is small, and the negative value of dE$dT is primarily responsible for the change in tunneling probability. As a result, the peak current increases with temperature. In the more-lightly doped tunnel diodes, the decrease of D with temperature dominates, and the temperature coefficient is nega- 0 0.2 0.4 0.6 0.8 1 .o Forward voltage (V) Fig. 11 Typical I-Vcharacteristics of Ge, GaSb, and GaAs tunnel diodes at 300 K. 8.2 TUNNELDIODE 431 tive. For typical Ge tunnel diodes, the variation of the peak current over a temperature range of -50 to 100°C is about The valley current generally increases with increasing temperature, because the bandgap reduces with temperature. After electron bombardment, the major effect is the increase in excess current caused by increased volume density of the energy levels in the bandgap.28The increased excess current can be annealed out gradually. Similar results can be observed for other types of radiation, such as yrays. Physical stress on the device causes the excess current in Ge and Si tunnel diodes to increase.29The changes are found to be reversible. This effect arises from deep-lying states associated with the strain-induced defects in the depletion region. For GaSb, however, both I, and I , decrease with increasing hydrostatic pressure,30which can be explained by an increase in the bandgap and a reduction in the degeneracy of VA and Vk with increasing pressure. 8.2.3 Device Performance Originally, most tunnel diodes are made using one of the following techniques. (1) Ball alloy: A small metal alloy pellet containing the counter dopant of high-solid solubility is alloyed to the surface of a semiconductor substrate with high doping, in a precisely controlled temperature-time cycle under inert or hydrogen gas (e.g., the arsenic in an arsenic-doped tin ball forms the n+-region on the surface of ap+-Gesubstrate). (2) Pulse bond: The contact and the junction are made simultaneously when the junction is pulse-formed between the semiconductor substrate and the metal alloy containing the counter dopant. (3) Planar processes:31Planar tunnel diode fabrication uses planar technology, including solution growth, diffusion, and controlled alloy. More-recent techniques are based on low-temperature epitaxial growth where the dopants are incorporated during the growth of the semiconductor layer. These include MBE (molecular-beam epitaxy) and MOCVD (metal-organic chemical vapor deposition). These techniques yield higher peak-to-valley ratios because of higher and sharper doping profiles for higher peak tunneling current, as well as lower defect densities for lower excess current. Figure 12 shows the basic equivalent circuit, which consists of four elements: the series inductance L,, the series resistance R,, the diode capacitance Cp and the negative diode resistance -R. The series resistance R, includes the on-chip interconnects and external wire resistance, the ohmic contacts, and the spreading resistance in the wafer substrate, which is given by p/2dwhere p i s the resistivity of the semiconductor and d is the diameter of the diode area. The series inductance L, is due to interconnects, wire bond, and external wires. We shall see that these parasitic elements establish important limits on the performance of the tunnel diode. To consider the intrinsic diode capacitance and negative resistance, we refer to typical dc current-voltage characteristics in Fig. 13a. Figure 13b shows the conductance plot (dZ/dV)versus bias. At the peak and valley voltages the conductance becomes zero. The diode capacitance is usually measured at the valley voltage, and is designated by Cj. The differential resistance, defined as (dZ/dV)-l,is plotted in Fig. 13c. The absolute value of the negative resistance at the inflection point, which Interconnect, lead, and contact - Fig. 12 Equivalent circuit of tunnel diode. 0' II 1 I I I I I (4 I I I IVV I 0 0.2 0.4 0.6 0.8 1.o V(vo1ts) Fig. 13 (a) Intrinsic current-voltage characteristics of a GaAs tunnel diode at 300 K. (b) Differential conductance G = dZ/dVvs. K At peak and valley currents, G = 0. (c) Differential resistance (dlld0-I vs. where Rminis the minimum negative resistance and Rmnfis the resistance corresponding to the minimum noise figure. 432 8.2 TUNNELDIODE 433 is the minimum negative resistance in the region, is designated by RminT, his resistance can be approximated by where Vpand Zp are the peak voltage and peak current, respectively. The total input impedance Z,, of the equivalent circuit of Fig. 12 is given by [ 1 [ -wCjR2 Z,, = R,+ + j wL,+ 1 + (-wR R C ~ ) ~ 1+(wRC~)~ From Eq. 31 we see that the resistive (real) part of the impedance will be zero at a certain frequency, and the reactive (imaginary) part of the impedance will also be zero at another frequency. We denote these frequencies by the resistive cutoff frequencyf, and the reactive cutoff frequencyf,, respectively. These frequencies are given by (33) Since R is bias dependant, so are the cutoff frequencies. These resistive and reactive cutoff frequencies specified at the bias of Rminare =L7 xo - 2 7 ~LsCj (RminCj)25 f,. (35) Since at that bias, the value of R is at its minimum (Rmin),Aisothe maximum resistive cutoff frequency at which the diode no longer exhibits net negative resistance; and&n is the minimum reactive cutoff frequency (or the self-resonant frequency) at which the diode reactance is zero. It follows that the diode would oscillate ifffi >LoI.n most applications where the diode is operated into the negative-resistance region, it is desirable to havef,, >ffi andf, >>fo,fobeing the operating frequency. Equations 34 and 35 show that to fulfill the requirement thatL0 > f f i ,the series inductance L, must be low. The switching speed of a tunnel diode is determined by the current available for charging the junction capacitance and the average RC product. Since R, the negative resistance, is inversely proportional to the peak current, a large tunneling current is required for fast switching. A figure of merit for tunnel diodes is the speed index, which is defined as the ratio of the peak current to the capacitance at the valley voltage, IpIcJ. Figure 14 shows the speed index and the peak current versus depletionlayer width of Ge tunnel diodes at 300 K. We see that a narrow depletion width or large effective doping is needed to obtain a large speed index. 434 CHAPTER 8. TUNNEL DEVICES Depletion-layer width W(nm) Fig. 14 Average value of the speed index (=I&,) and peak current density vs. depletionlayer width of Ge tunnel diodes at 300 K. (After Ref. 31.) Another important quantity associated with the equivalent circuit is the noise figure, which is given as where IRIJmi,is the minimum value of the negative resistance-current product on the current-voltage characteristic. Figure 13 indicates the corresponding value of R (designated by Rmnf).The product qlRI/,,/2kT is called the noise constant and is a material constant. Typical values of the noise constant at room temperature are 1.2 for Ge, 2.4 for GaAs, and 0.9 for GaSb. The noise figure for Ge tunnel diodes is about 5-6 dB at around 10 GHz. In addition to its microwave and digital applications, the tunnel diode is a useful device for the study of fundamental physical parameters. The diode can be used in tunneling spectroscopy, a technique that uses tunneling electrons of known energy distribution as a spectroscopic probe instead of photons of known frequency in optical spectroscopy. Tunneling spectroscopy has been used to study electron energy states in solids and to observe the excitation of modes. For example, from the shape of the I-Vcharacteristics of a Si tunnel diode at low temperature, the phonon-assisted tunneling processes can be identified.32Similar observations are made in group 111-V semiconductor junctions with the plots of the conductance (dlldV)versus bias at 4.2 K for Gap, InAs, and InSb.33,34 8.3 RELATED TUNNEL DEVICES 435 8.3 RELATED TUNNEL DEVICES 8.3.1 Backward Diode In connection with the tunnel diode, when the doping concentration on the p-side or n-side is nearly or not quite degenerate, the current in the reverse direction for small bias, as shown in Fig. 15, is larger than the current in the forward direction-hence the name backward diode. At thermal equilibrium, the Fermi level in the backward diode is very close to the band edges. When a small reverse bias (p-side negative with respect to n-side) is applied, the energy-band diagram is similar to Fig. 3e except that there is no degeneracy on both sides. Under reverse bias, electrons can readily tunnel from the valence band into the conduction band and give rise to a tunneling current, given by Eq. 9, which can be written in the form J = c,exp(-) I VI (37) c6 where C, and c6 are positive quantities and are slowly varying functions of the applied voltage L! Equation 37 indicates that the reverse current increases approximately exponentially with the voltage. The backward diode can be used for rectification of small signals, and microwave detection and mixing.35Similar to the tunnel diode, the backward diode has a good frequency response because there is no minority-carrier storage.36 In addition, the current-voltage characteristic is insensitive to temperature and to radiation effects, and the backward diode has very low l l f n o i ~ e . ~ ’ For nonlinear applications such as high-speed switching, a device figure of merit is y, the ratio of the second derivative to the first derivative of the current-voltage characteristics. It is also referred to as the curvature y’ d2IldP ~ dIldV ‘ (4 (b) Fig. 15 Comparison of (a) tunnel diode with negative resistance and (b) backward diode without negative resistance. 436 CHAPTER 8. TUNNEL DEVICES The value of y is a measure of the degree of nonlinearity normalized to the operating admittance level. For a regular forward-biased p-n junction or Schottky barrier the value of yis simply given by qlnkT. Thus yvaries inversely with T.At room temperature, y for an ideal p-n junction (n = 1) is about 40 V-' independent of bias. For a reverse-biasedp-n junction, however, the value of yis very small at low voltages and increases linearly with the avalanche multiplication factor near breakdown voltage.39 Although the reverse breakdown characteristic could in theory give a value of y greater than 40 V-', because of the statistical distribution of impurities and the effect of space-charge resistance, much lower values of yare expected. For a backward diode the value of y can be obtained from Eq. 16and is given bfo where m* is the average effective mass of the carriers Clearly, the curvature coefficient y depends on the impurity concentrations on both sides of the junction and the effective masses. In contrast to Schottky barriers, the value of y is relatively insensitive to temperature variation because the parameters in Eq. 39 are slowly varying functions of temperature. Figure 16 shows a comparison between theoretical and experimental values of y for Ge backward diodes. The solid lines are computed from Eq. 39 using mz = 0.22~1,and m i = 0.39m0. The agreement is generally good over the doping range considered, and y can exceed 40 V-'. -"" I Theory I - o 0 Experiment 10 I I I I Illll 2 5 1019 I I I I I IIL 2 5 1020 No or N, ( ~ r n - ~ ) Fig. 16 Curvature coefficient vs. N, (for a fixed No = 2 x l O I 9 ~ r n - ~or)No (for a fixed N, = 1019~ r n - ~i)n,Ge at 300 K and V = 0. (After Ref. 40.) 8.3 RELATED TUNNEL DEVICES 437 8.3.2 MIS Tunnel Devices For a metal-insulator-semiconductor (MIS) structure, the current-voltage characteristics critically depend on the insulator thickness. If the insulator layer is sufficiently thick (greater than = 7 nm for the Si-SiO, system), carrier transport through the insu- lator layer is negligible and the MIS structure represents a conventional MIS capacitor (discussed in Chapter 4). On the other hand, if the insulator layer is very thin (less than 1 nm), little impediment is met by carriers transporting between the metal and the semiconductor, and the behavior resembles a Schottky-barrier diode. Inbetween these two oxide thicknesses, there exist also different tunneling mechanisms. We will examine in more details, in particular, Fowler-Nordheim tunneling (Fig. 17a), direct tunneling (Fig. 17b), MIS tunnel diode with ultra-thin oxide (Fig. 17c), and finally negative resistance resulting from MIS tunnel diode on degenerate substrate. Fowler-Nordheim Tunneling. Fowler-Nordheim (F-N) tunneling is characterized by (1) the barrier has a triangular shape, and (2) tunneling through only part of the insulator layer. It is shown in Fig. 17a that with a higher field, a narrower barrier is in effect. After tunneling through this triangular barrier, the rest of the insulator does not impede the current flow. So the total insulator layer only affects the current indirectly by affecting the field. The F-N current has the form similar to Eq. 9 and is given as41 Insulator Semiconductor Metal (b) (c) Fig. 17 Tunneling mechanism depends on oxide thickness range. (a) In thicker oxides (> 5 nm) Fowler-Nordheim tunneling through a triangular barrier and only part of the insulator layer. (b) Direct tunneling through whole insulator layer. (c) MIS tunnel diode ( d < 30 A) is characterized by nonequilibrium (EFnf EFp)and tunneling by both types of carriers. 438 CHAPTER 8. TUNNEL DEVICES where for thermal oxides, the constants are C, = 9 . 6 3 ~ 1 0 A- ~/V2 and C, = 2 . 7 7 ~ 1 V0 ~lcm. The commonality between this equation and Eq. 9 is the triangular barrier. But in F-N tunneling, in the WKB approximation, the band structure in the insulator layer, including the effective mass, has to be used instead. Note that the insulator thickness is not in the formula but only the field. The transition between F-N tunneling and direct tunneling is demonstrated in Fig. 18. Direct tunneling occurs at thinner oxides and lower fields. The oxide thickness for transition between F-N tunneling and direct tunneling can be approximated by d = &/8.For electron tunneling, = 3.1 V, and 8 for medium tunneling current is around 6 MVIcm. This gives an oxide thickness of = 5 nm. Direct Tunneling. Direct tunneling occurs below o 5 nm and with such a thin insulator, other phenomena such as quantum effects cannot be ignored. In quantum mechanics, the peak carrier concentration of the inversion layer is at a finite distance from the semiconductor-insulator interface, so the effective insulator thickness is increased. Furthermore, the inversion layer is a quantum well and carriers are at quantized energy levels above the conduction-band edge. With these quantum effects, a simple expression for direct current is not accurate. Simulated results are shown in Fig. 19. It can be seen that the tunneling current is very sensitive to the oxide thickness. Another factor to consider is that in practical devices such as MOSFETs, the top electrode on oxide is a heavily doped poly-Si layer instead of metal. Such a contact Fowler-Nordheim tunneling 1 2 3 4 5 6 7 8 91011121314 5 Electric field 8 (MV/cm) Fig. 18 Tunneling current vs. field for different oxide thicknesses. For thicker oxides FowlerNordheim tunneling dominates and is independent of thickness. Direct tunneling occurs in thinner oxides at low fields. (After Ref. 42.) - Simulation '03- Measurement 8.3 RELATED TUNNEL DEVICES 439 Gate voltage (V) Fig. 19 Direct tunneling current taking quantum effects into account. (After Ref. 43.) has a small depletion layer at the oxide interface which also increases the effective insulator thickness. MIS Tunnel Diode. The tunneling current is given by an expression similar to that of Eq. 8. Using a WKB approximation and assuming the conservation of energy E and transverse momentum k,, the tunneling current density along the x-direction between two conducting regions through a forbidden region can be written as44 J = L4 nI2IhT l [ F , ( E ) - F2(E)]dk!dE where F , and F2 are the Fermi distribution hnctions in the two conducting regions, and TIis the tunneling probability. For the MIS diode under consideration, the constant energy surface in k-space for electrons in the semiconductor is, in general, considerably smaller than that in the metal. As a result, the tunneling of electrons from the semiconductor to the metal is always assumed to be allowable. If it is further assumed that the energy bands of the solids involved are parabolic with an isotropic electron mass m*,Eq. 42 can be reduced to where E , and E are the transverse and total kinetic energy of electrons in the semiconductor. The limits of integration for E, are zero and E; the limits for E are simply the two Fermi levels. The tunneling probability for a rectangular barrier with an effective barrier height q@Tand width d, Fig. 17c, can be obtained from Eq. 2:45 440 CHAPTER 8. TUNNEL DEVICES ( Tt= exp -2 d Jm A T ) = ~ x P ( -aTd@T) (44) where a, (= 2 m / h ) approachesunity if the effective mass in the insulator equals the free electron mass, and 4Tis in volts and d i n 8. The tunneling current can be evaluated by substituting Eq. 44 into Eq. 43 and integrating over the energy range, ~ i e l d i n g ~ ~ . ~ ~ where A* = 4 r m ; qk2/h3is the effective Richardson constant and 4Bthe Schottky barrier height. Equation 45 is identical to the standard thermionic-emission equation for Schottky barriers except for the added term e x p ( - q d m , ) , which is the tun- neling probability. Here a constant of [2(2m*/A2)]*is/2omitted which has the value of 1.01 eV-’/,A-l. It is thus clear from Eq. 45 that for 4Tof the order of 1 V and d > 50 8,the tunneling probability is about exp(-50) = lo-,,, and the current is indeed negligibly small. As d andor 4, decrease, the current increases rapidly toward the thermionic-emission current level. Figure 20 shows the forward I- Vcharacteris- tics of four Au-Si0,-Si tunnel diodes of different insulator-layer thicknesses. For d = 10 8,the current follows the standard Schottky-diode behavior with an ideality factor 7 close to 1. As the insulator thickness increases, the current decreases rapidly and the ideality factor begins to depart from unity. The expression for 7 has been pre- sented in Section 3.3.6. One of the most-important parameters for this MIS tunnel diode is the metal-insu- lator barrier height, which has a profound effect on the I-V characteristic^.^'-^^ Figure 2 1 shows the schematic energy-band diagrams at thermal equilibrium for MIS tunnel diodes onp-type substrates with two metal-to-insulator barrier heights. For the low-barrier case (bmi= 3.2 V for the A1-SiO, system) the surface of thep-type silicon is inverted at equilibrium. Whereas in the high-barrier case (bmj= 4.2 V for the / 2’ Au-Si contacts Fig. 20 Measured current- 10-81 AI 1 0-9 N, = 1016 cm-3 voltage characteristics of MIS A = 7 . 8 x 1 t 3 cm2 tunnel diodes having different 0.2 0.4 0.6 I oxide thicknesses. (After Voltage (V) Ref. 46.) 8.3 RELATED TUNNEL DEVICES 441 Fig. 21 Energy-band diagrams for MIS tunnel diodes on nondegenerate substrates (p-type) with (a) low metal-insulator barrier and (b) high metal-insulator barrier. (After Ref. 47.) Au-SiO, system) the surface is in accumulation of holes. Two main tunneling current components exist: Jcr carriers from the conduction band to the metal, andJ,,, from the valence band to the metal. Both currents are given by expressions similar to Eq. 42. Figure 22 shows the theoretical I-V curves for the two diodes. For the low-barrier case, Fig. 22a, under small forward and reverse biases, the dominant current is the minority-carrier (electron) current Jet, due to the abundance of electrons. As the forward bias (positive voltage on semiconductor) increases, the current also increases monotonically. At a given bias, the current increases rapidly with decreasing insulator thickness. This is because the current is limited by the tunneling probability, Eq. 44, Bias on semiconductor (V) -1 0 1 Bias on semiconductor (V) (a) (b) Fig. 22 Current-voltage characteristics of MIS tunnel diodes having: (a) low barrier #mL, (b) high barrier. T = 300 K. NA= 7 ~ 1 0~' m~ - (~A.fter Ref. 47.) 442 CHAPTER 8. TUNNEL DEVICES which varies exponentially with the insulator thickness. At reverse bias, the current is virtually independent of the insulator thickness for d < 30 A, because the current is now limited by the rate of supply of minority carriers (electrons) through the semiconductor, and the current is similar to the saturation current in a reverse-biased p-n junction. Figure 22a also shows the experimental result for d = 23.5 A. Note that the current-voltage characteristics are similar to the rectification nature of ap-n junction. For the high-barrier case, Fig. 22b, under forward bias, the dominant current is the majority-carrier (hole) tunneling current from the valence band to the metal, and the current increases exponentially with decreasing insulator thickness. Under reverse bias the current does not become independent of the insulator thickness as in Fig. 22a. Instead, the current increases rapidly with decreasing insulator thickness, because for majority-carrier transport the current is limited in both directions by the tunneling probability, not by the rate of carrier supply. So for high-barrier cases, the tunneling currents are higher, especially in reverse bias. MIS Tunnel Diode On Degenerate Semiconductor. We discuss here that negative resistance can be observed from MIS tunnel diode on degenerately doped semiconductor. Figure 23 shows simplified band diagrams for MIS tunnel diodes with p++and n++-semiconductorsubstrates, including interface traps. The band bending and image force on the semiconductor side and potential drops across the oxide layer at equilibrium are omitted for simplicity. Consider the p++-typesemiconductor first. Applying a positive voltage to the metal (Fig. 23b) causes electrons to tunnel from the valence band to the metal. The tunneling current in this bias polarity (Fig. 23b) increases monotonically with the increasing energy range between the Fermi levels and does not result in negative resistance; it further increases with the decreasing effective insulator barrier height h. Applying a small negative voltage to the metal (Fig. 23c) results in electrons tunneling from the metal to the unoccupied semiconductor valence band. According to Fig. 23d, for electrons tunneling from the metal to the unoccupied states of the valence band, an increase of the reverse voltage -V implies an increase in the effective barrier height q4p thus resulting in a drop of current with increase of bias, i.e., negative resistance. Another current component results from electrons in the metal with higher energies tunneling simultaneously into the empty interface traps and momentarily recombining with holes in the valence band. Since the effective insulator barrier decreases with bias, this current component always has a positive differential resistance. Finally further increase of the bias results in a third, very fast-growing tunneling current component from the metal into the conduction band of the semiconductor (Fig. 23e). Next consider the n++-typesemiconductors. As shown in Fig. 23f, the effective insulator barriers for the n++-typeare expected to be smaller than those of thep++-type samples; hence, in general, for a given bias, there will be larger tunneling currents. For a negative bias on the metal, electrons tunnel from the metal into the empty states of the semiconductor conduction band, resulting in a large, rapidly increasing current (Fig. 23g). A small positive voltage on the metal leads to increasing electron tunneling from the conduction band ofthe semiconductor into the metal (Fig. 23h). Ifthe 8.3 RELATED TUNNEL DEVICES 443 nM I S(n++) c J Fig. 23 Simplified band diagrams of MIS tunnel diodes on degenerate substrates, including interface traps. Top and bottom rows are forp++-and n++-substratesrespectively. Vis positive bias on the metal. (After Ref. 49.) interface traps are filled with conduction electrons by recombination, a further increase in bias (Fig. 23i) gives rise to a second current component caused by the tunneling of electrons from the interface traps into the metal. This current component increases with increasing bias since the effective insulator barrier decreases. For a larger voltage (Fig. 23j) additional tunneling from the valence band to the metal is possible, but its influence on the total I- V characteristic is comparatively small because of the relatively high oxide barrier. Thus, the band structure of the semiconductor has a much smaller influence on the tunneling characteristics of the n++-type compared to p++-typestructures. Note the interesting result that unlike p"-substrate, there is no negative resistance observed on n++-substrate. The negative resistance on p++-semiconductorhas been obtained in MIS tunnel diodes of A1-A1,03-SnTe.50The SnTe is a highly dopedp-type with a concentration of 8 x lozo~ m - t~he; Al,03 is about 5-nm thick. Figure 24 shows the measured current-voltage characteristics at three different temperatures, where the negative resistance occurs between 0.6 to 0.8 V. These results are in good agreement with theoretical prediction44based on Eq. 43. 444 CHAPTER 8. TUNNEL DEVICES 1.4 1.2 - 1.o 4 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 v (V) Fig. 24 MIS tunnel diode (A1-A1,O3-SnTe) I- Vcharacteristics 1.O showing negative resistance. (After Ref. 50.) 8.3.3 MIS Switch Diode The MIS switch (MISS) diode is a four-layer structure as shown in Fig. 25a. It is basically an MIS tunnel diode in series with ap-n junction. This diode was found to display a current-controlled negative resistance, Fig. 25b, similar to a Shockley diode (Chapter 1l).51When a negative bias is applied to the top metal contact (or positive V,,p+-region is assumed to be grounded), the I- Vcharacteristic shows a high-impedance or of-state. At a sufficiently high voltage, the switching voltage V,, the device suddenly switches to a low-voltage high-current on-state. The switching is initiated either by the extension of the surface depletion region to that of the pf-n junction (punch-through), or by avalanche in the surface n - l a ~ e rT.h~e~initial device was built (4 (b) Fig. 25 (a) MIS switch diode, a four-layer structure. (b) Current-voltage characteristics show current-controlledS-type negative resistance. 8.3 RELATED TUNNEL DEVICES 445 on a Si wafer and employed SiO, as the tunnel insulator. Later, similar behaviors were obtained from other insulators (e.g., Si,N,) and thick polycrystalline silicon. The I-Vcharacteristics shown in Fig. 25b can be explained qualitatively with the energy-band diagrams shown in Fig. 26. With negative anode-to-cathode voltage (-VAK)t,he MIS tunnel diode is under forward bias and thep-n junction under reverse bias. The current is limited by generation within the depletion region (W,) of the p-n junction, given by where z is the minority-carrier lifetime and y+bj the built-in potential of thep-n junction. Under this bias condition, no switching occurs. With positive VAKt,he MIS tunnel diode is under reverse bias and thep-n junction under forward bias (Fig. 26c). In the low-current off-state, current is dominated by generation in the surface depletion region, given by the same expression except that y+bi is replaced in this case by the barrier height bBat equilibrium. The thermally gen- erated electrons approach the p-n junction and recombine with holes in the depletion region of the forward-biased p-n junction. This implies that the current through the p-n junction is dominantly recombination, rather than diffusion, due to the low current level passing through it. The electrons tunneling from metal to semiconductor is the reverse current of an MIS tunnel diode and it is small in the off-state. But this current will be shown later to be large and becomes the dominant current in the onstate. The switching criterion of the MISS depends critically on the supply of holes toward the tunneling insulator. When this hole current is semiconductor-limited (generation) it is small. In this condition, the semiconductor surface is in deep depletion, and an inversion layer of holes at the surface is not formed. If an additional supply of holes from other sources is available, the tunneling current is not sufficient to drain the holes, so it becomes tunneling-limited and a hole inversion layer is formed. The collapse of the surface potential (surface band bending) increases the voltage across the insulator V, and increases the Jntin two respects. First, the barrier height bBis reduced, and second, bTis also reduced. The latter is equivalent to a higher electric field across the insulator. The large current passes through the p-n junction and the current mechanism in the p-n junction changes from recombination to diffusion. An electron current J, can inject a much larger hole current since NA >> ND, by a factor of a 1/( 1 - f i , where yis the injection efficiency of thep-n junction (ratio of hole current to total current). The total hole current tunneling through the insulator becomes Jpt = J n1 ( F ) . (47) The MIS tunnel diode and the p-n junction pair creates regenerative feedback and results in negative differential resistance. The regenerative feedback can also be viewed as a result of two current gains: a gain of electron current from hole current in an MIS tunnel diode, as originally pro- n J- w,+ w,,=xn 0--* -J,t EFm Zmm\ \b 1 'EF" - qv / EFP (0 446 8.3 RELATED TUNNEL DEVICES 447 posed,53and a gain of hole current from electron current in the p+-n junction. To achieve current gain in an MIS tunnel diode, the precise insulator thickness is critical, and it has to be in the range of 20-40 A for the case of silicon dioxide. Oxides thinner than 20 8, cannot confine holes at the surface to support an inversion layer and to decrease &, and current is always semiconductor-limited. Oxides thicker than 50 A do not allow deep depletion, and current is always tunneling-limited. In practice, the current initiated by generation is not large enough to trigger switching. The two most-common additional sources are from punch-through and avalanche. In the punch-through condition shown in Fig. 26e, the depletion region of the MIS diode merges with that of the p-n junction. The potential barrier for holes is reduced and a large hole current is injected. The switching voltage in this punchthrough mode is given by where W, is the depletion region of thep-n junction. Before the punch-through condition, if the electric field near the surface is high enough, avalanche multiplication occurs and also gives rise to a large hole current toward the surface (Fig. 26d). The switching voltage in this mode is similar to the avalanche breakdown voltage of a p-n junction. Avalanche-mode switching domi- nates in structures with high doping concentrations in the n-layer, usually higher than 10'7 cm-3. The energy-band diagram in Fig. 26f shows an MISS after it is switched to the high-current on-state. Note that neither punch-through nor avalanche could be sus- tained after switching. The conduction-band edge at the surface is below EFm (4B= 0), and Jntcontrols the on-current. The holding voltage can be approximated by v h =vj+V J . (49) 5is the voltage across the insulator, and is approximately equal to the original barrier VJ height 4Bat equilibrium (= 0.5-0.9 V). The forward bias on the p-n junction is around 0.7 V, giving a holding voltage of = 1.5 V. Besides the aforementioned punch-through and avalanche, two other sources of hole current are also possible. One is by a third terminal contact, and another by optical generation. The three-terminal MISS is sometimes called an MIS thyristor. With either a minority- or majority-carrier injector, the function is the same-to increase the hole current flowing toward the insulator. While the minority-carrier injector injects holes directly, the majority-carrier injector controls the potential of the n-layer, and hole current is injected from the p+-substrate. In either structure, with a positive gate current flowing into the device, a lower switching voltage results. Alter- nately when the MISS is exposed to a light source, Jp is generated optically and the switching voltage is reduced. For a fixed VAKl,ight can induce turn-on and the device becomes a light-triggered switch. As mentioned previously, the oxide thickness is a key parameter in the switching behavior. As shown in Fig. 27, for thicker oxides (d 2 50 A) the tunneling impedance is too high to meet the switching requirement. For very thin oxides (d < 15 A) the 448 CHAPTER 8. TUNNEL DEVICES p+-njunction can be turned hlly on prior to the development of the deep depletion mode; thus the device displays a p-n junction characteristic. Switching behavior is observed only for the intermediate thicknesses (15 A < d < 40 A). Attractive features of the MIS switch diode include high switching speed (1 ns or less), and high sensitivity of the switching voltage Vsto light or current injection. The MISS can be applied in digital logic, and shift registers have been demonstrated. Other applications include memories such as SRAM, microwave generation when incorporated in a relaxation oscillator circuit, and as a light-triggered switch for alarm systems. The limitation of the MISS is its relatively high holding voltage and dimculty in reproducing a uniformly thin tunneling insulator. 8.3.4 MIM Tunnel Diode A metal-insulator-metal (MIM) tunnel diode is a thin-film device in which the electrons from the first metal can tunnel into the insulator film and be collected by the second metal. It displays nonlinear I- Vcharacteristics but negative resistance is not present. The nonlinear I-V nature is sometimes used for microwave detection as a mixer. Figures 28a and b show the basic energy-band diagrams of a MIM diode with similar metal electrodes. Since all of the voltage applied is dropped across the insulator, the tunneling current through the insulator is, from Eq. 42, At 0 K, Equation 50 simplifies to54 Fig. 27 Calculated I-Vcharacteristic of MIS switch diodes for different values of oxide thickness. Device constants arex, = 10 pm, No = lOI4 ~ m - a~nd, z= 3 . 5 ~ 1 0 -s.~(After Ref. 52.) 8.3 RELATED TUNNEL DEVICES 449 - (4 (b) (c) Fig. 28 Energy-band diagrams of MIM structures. (a) Symmetrical MIM under equilibrium. (b) Under bias, V > W. (c) Asymmetrical MIM. J = J,[$exp(-C&) - ($+ v ) e x p ( - C F V ] (51) where -4 is the average barrier height above the Fermi level, and d’ is the reduced effective barrier width. Equation 51 can be interpreted as a current density J o $ e x p F ) flowing from electrode-1 to electrode-2 and another Jo( $ + V)exp(-C i +V ) flowing from electrode-2 to electrode- 1. We now apply Eq. 51 to the ideal symmetrical MIM structure. By ideal we mean that the temperature effect, the image-force effect, and the field-penetration effect in metal electrodes are neglected. For 0 I V140, d’ = d, and $ = @o- V/2, the current density is given by 4 For larger voltage, V > 40,we have d’ = d4dV and = &/2. The current density is then where 450 CHAPTER 8. TUNNEL DEVICES and = V/dis the field in the insulator. For higher voltage such that V> &,, the second term in Eq. 55 can be neglected, and we have the well-known Fowler-Nordheim tunneling equation (Eq. 41). For an ideal asymmetrical MIM structure with different barrier heights q41 and h 4 (Fig. 28c), in the low-voltage range 0 < V < il,the quantities 8 = d and = ( A + h - V)/2 are independent of the polarities. Thus the J-V characteristics are also 4 independent of the polarity. At higher voltages, V > 41,the average barrier height and the effective tunneling distance 8 become polarity-dependent. Therefore, the currents for different polarities are different. The MIM tunnel diodes have been used to study the energy-momentum relation in the forbidden gap of large-bandgap s e r n i c o n d ~ c t o r sA. ~n~M~I~M~tunnel structure is formed using the single-crystal specimen, for example GaSe (E, = 2.0 eV, d < 10 nm), sandwiched between two metal electrodes. Using one set of J-V curves, one can obtain the energy-momentum (E-k)relationship using Eqs. 42 and 50. Once the E-k relationship is obtained, one can calculate, using no adjustable parameters, the tunneling currents for all other thicknesses. 8.3.5 Hot-Electron Transistors Over the years, many attempts have been made to invent or discover new solidstate devices capable of achieving better performance than bipolar transistors or MOSFETs. Among the most interesting candidates are the hot-electron transistors (HETs). In a hot-electron transistor, carriers injected from the emitter have high potential or kinetic energy in the base. Since a hot carrier has higher velocity, HETs are expected to have higher intrinsic speed, higher current, and higher transconductance. In this section, we discuss HETs based on tunnel emitter-basejunctions. These devices are sometimes referred to as tunneling hot-electron transfer amplifier (THETA). The first THETA was reported by Mead in 1960, using an MOMOM (metaloxide-metal-oxide-metal) structure, sometimes called an MIMIM (metal-insulatormetal-insulator-metal) structure (Fig. 29a).57,58In this structure both the emitter and collector barriers are formed by oxides. The metal base had to be thin and was typically between 10 and 30 nm. The current gain of such a structure could be greatly improved by replacing the MOM collector junction by a metal-semiconductor junction (Fig. 29b),59resulting in an MOMS (metal-oxide-metal-semiconductor),or an MIMS (metal-insulator-metal-semiconductor)structure. This MIMS structure, however, has a lower maximum oscillation frequency than the bipolar transistor mainly because of its longer emitter charging time (caused by larger emitter capacitance) and smaller common-base current gain (caused by hot-electron scattering in the base region). Still another variation is to use ap-n junction in the collector (Fig. 29~).~IOn this MOp-n (or MIp-n) structure the semiconductor is the base material, as opposed to metal, and thus has less scattering in the base. Since all the above structures use the same emitter injection mechanism of tunneling, they suffer from the same problem of low current gain and poor control of the barrier thickness. There has been a renewed interest in the THETA since Heiblum in 8.3 RELATED TUNNEL DEVICES 451 n Fig. 29 Variations of tunnel-emitter hot-electron transistors and their energy-band diagrams under forward conditions. (a) MIMIM. (b) MIMS. (c) MIp-n. (d) Heterojunction THETA. 1981 suggested using a wide-energy-gap semiconductor as the tunneling barrier and a degenerately doped narrow-energy-gap semiconductor as the emitter, base, and collector.61This idea was especially timely after the rapid development of epitaxial techniques such as MBE and MOCVD in the 1970s. The first heterojunction THETA was reported in 1984,62,63followed by works reported in 1985.64-66 For the heterojunction structure (Fig. 29d), the AlGaAsIGaAs system is the most common, but other materials, such as InGaAsIInAlAs, InGaAsIInP, InAsIAlGaAsSb, and InGaAdInAlGaAs, have been reported. The narrow-energy-gap materials for the emitter, base, and collector are typically heavily doped while the wide-energy-gap layers are undoped. The barrier thickness for the tunneling emitter is in the range of 7-50 nm, while the barrier layer for the collector is much thicker, ranging from 100 to 250 nm. The base width ranges from 10 to 100 nm. A thin base improves the transfer ratio but is harder to contact without shorting to the collector layer. The collector-base junction is often graded in composition to reduce quantum-mechanical reflection. For the discussion of the working principle, the heterojunction THETA is assumed since it is of the greatest interest. Under normal operating conditions, the 452 CHAPTER 8. TUNNEL DEVICES emitter is negatively biased (for the doping type shown) with respect to the base, and the collector is positively biased (Fig. 29d). Since the barrier created by the heterojunction is low, typically in the range 0.2-0.4 eV, it is necessary to operate the THETA at low temperatures to reduce the thermionic-emissioncurrent over the barrier. Electrons are injected from the emitter to the n+-base, making the THETA a majority-carrier device. The emitter-base current is a tunneling current through the barrier, either by direct tunneling or by Fowler-Nordheim tunneling. The electrons injected at the base have a maximum kinetic energy (above E,) of = q ( V B E - Vn> (57) (V, is negative for a degenerate semiconductor). As electrons traverse the base, energy is lost through some scatteringevents. At the base-collectorjunction, carriers with energy above the barrier qq& will result in collector current, while the rest will contribute to undesirable base current. The base transport factor a, can be broken down into different components as I, = aTIE = aBa,,acIE . (58) a,, due to scattering in the base layer, is given by where Wand Amare the base width and its mean free path. Reported values for A, range from 70 to 280 nm. Amis also known to be dependent on the electron energy. When the energy is too high, Amstarts to decrease. In the case of an MOM emitter, because the oxide barrier is much higher, a large VBE is required to inject a specific current level. A higher VBE,unfortunately, increases the electron energy and reduces A,,. This is the factor that requires the oxide thickness in the MOM barrier to be small (= 15 A).61To improve a,, the base thickness must be minimized, but this results in excessive base resistance. It has been suggestedthat an induced base67or modulation doping for the base layer be used so that it can be thin (= 10 nm) and yet conductive. The second factor a,, is due to quantum-mechanical reflection at the base-collector band-edge discontinuity.For an abruptjunction, it is given by68 Composition grading for the collector barrier would improve the reflection loss. ac is the collector efficiency due to scattering in the wide-energy-gap material. To have a high p(common-emitter current gain) value, aTshould be close to unity since p= - a T 1- aT' 8.3 RELATED TUNNEL DEVICES 453 Fig. 30 Common-base output characteristics of a heterojunction THETA. (After Ref. 70.) /?values as high as 40 have been reported.69An example of the output characteristics of a THETA is shown in Fig. 30. The THETA offers a potential for high-speed operation due to ballistic transport through the base and the absence of minority-carrier storage. The requirement for lower-temperature operation is a concern that it may limit the application. The THETA has been used as a research tool to study the properties of hot carriers. A specific function is a spectrometer to measure the energy spectrum of the tunneled hot electrons in the base. In this operation, the collector is biased positively with respect to the base to vary the effective collector barrier (Fig. 3 la). When the incremental collector current is plotted against the effective collector barrier height, the energy spectrum of the hot electrons is obtained. It can be seen from Fig. 3 1b that for each VBEt,he energy (related to V,) at the peak of the distribution increases with VBE. n VBE= 329 mV Collector L0 -300 (a) (b) Fig. 31 (a) Energy-band diagram of THETA as a spectrometer. The collector voltage is negative with respect to the base to vary the effective collector barrier height. (b) Hot-electron energy spectrum. (After Ref. 70.) 454 CHAPTER 8. TUNNEL DEVICES 8.4 RESONANT-TUNNELING DIODE The negative differential resistance (NDR) of a resonant-tunneling diode (sometimes called a double-barrier diode) was predicted by Tsu and Esaki in 1973,71following their pioneering work on superlattices in the late 1960s and early 1970s. The structure and characteristics of this diode were first demonstrated by Chang et al. in 1974.72 Following the much-improved results reported by numerous authors in the early 1980s, research interest escalated, partially due to the maturing MBE and MOCVD technologies. In 1985, room-temperature NDR in this structure was r e p ~ r t e d . ~ ~ - ~ ~ A resonant-tunneling diode requires band-edge discontinuity at the conduction band or valence band to form a quantum well and thus necessitates heteroepitaxy. The most-popular material combination used is GaAdAlGaAs (Fig. 32), followed by GaInAs/AlInAs. The middle quantum-well thickness is typically around 5 nm, and the barrier layers range from 1.5 to 5 nm. Symmetry of the barrier layers is not required, so their thicknesses can be different. The well and barrier layers are all undoped, and they are sandwiched between heavily doped, narrow-bandgap materials, which usually are the same as the well layer. Not shown in Fig. 32 are thin layers of undoped spacers (z 1.5 nm GaAs) adjacent to the barrier layers to ensure that dopants do not diffuse to the barrier layers. Quantum mechanics prescribes that in a quantum well of width W,the conduction band (or valence band) is split into discrete subbands, and the bottom of each subband is given by - E,-Ecw = h2n2 , n = 1 , 2 , 3,... 8m* P where E , designatesE , in the well. Notice that this equation assumes infinite barrier height and can only serve to give a qualitative picture. In practice, the barrier (AE,) lies in the range of 0.2-0.5 eV, giving quantized levels of z 0.1 eV above E,. Under 5- Quantum well Fig. 32 Structure of resonant-tunneling diode using GaAdAlGaAs heterostructure as an example. The energy-band diagram shows the formation of a quantum well and quantized levels. 8.4 RESONANT-TUNNELING DIODE 455 bias conditions, carriers can tunnel from one electrode to the other via energy states within the well. Resonant tunneling is a unique phenomenon when tunneling is through double barriers via quantized states.75Recall the case of tunneling through a single barrier, the tunneling probability is a monotonic increasing function with energy of the incoming particle. In resonant tunneling, the wavefunctions of the Schrodinger equation have to be solved simultaneously in the three regions-emitter, well, and collector. Because of the quantized states within the well, the tunneling probability exhibit peaks when the energy of the incoming particle coincides with one of the quantized levels, as shown in Fig. 33. In this coherent-tunneling picture, if the incoming energy does not coincide with any of the quantized levels, the tunneling probably is a product of the individual probability between the well and the emitter TE, and that between the well and the collector Tc, T ( E ) = TETC. (63) However, when the incoming energy matches one of the quantized levels, the wavefunction builds up within the well similar to a Fabry-Perot resonator, and the transmission probability becomes76 T(E=E,) = TE TC (TE + TC)2 For a symmetric structure, TE= Tc, and T = 1. Away from this resonance, the value given by Eq. 63 quickly drops by many orders of magnitude, giving the shape shown in Fig. 33. The resonant-tunneling current is given by &,r J = N(E)T(E)dE J where the number of available electrons for tunneling (per unit area) from the emitter can be shown to be75 m% E- U L_ W L I 1 1 104 1 Transmission coefficient T(E) Fig. 33 Transmission coefficient of electron with energy E through a double barrier via coherent resonant tunneling. Transmission peaks occur when E aligns with En.(After Ref. 75.) 456 CHAPTER 8. TUNNEL DEVICES In a resonant-tunneling diode, the variable energy of the incoming electrons is provided by external bias such that the emitter energy is raised with respect to the well and the collector. The incoming energy distribution of tunneling electrons integrated over the sharp resonant-tunneling peaks of Fig. 33 would seem to predict sharp current peaks and very high peak-to-valley ratios, which are not observed in real devices, even at low temperatures. The reason for this is two-fold. First, the resonant transmission peaks are exponentially narrow, on the order of A E = hlz,where zis the lifetime of an electron in the subband En with respect to tunneling out and AE is the broadening of the energy level En.75Additionally there exist nonideal effects such as impurity scattering, inelastic phonon scattering, phonon-assisted tunneling, and thermionic emission over the barrier. These effects lead to much larger valley current that diminishes the peak-to-valley ratio. As it turns out, a model of sequential tunneling, rather than coherent tunneling, can explain the experimental data quite well.77In the sequential-tunneling picture, the tunneling from emitter into the well, and that from the well to the collector, can be treated as uncorrelated events. This simpler picture can give better insight into the observed experimental data and is used below. The I-V characteristics of a resonant-tunneling diode are shown qualitatively in Fig. 34. One notes not only the negative resistance, but also that it can be repeated, with multiple current peaks and valleys. This feature is not present in a conventional p+-n+tunnel diode. The energy-band diagrams under biases that correspond to the different regions of the I-Vcurve are shown in Fig. 35. The peak current corresponds to the bias condition that Ec of the emitter electrode is in line with each quantized level. We next explain the origin of such negative resistance. In the model of sequential tunneling, tunneling of carriers out of the well to the collector is much less constrained, and tunneling of carriers from the emitter into the well is the determining mechanism for the current flow. This requires available empty states at the same energy level (conservation of energy) and with the same lateral momentum (conservation of momentum) of the available electrons in the emitter as within the well. Since the parallel (to tunneling direction) momentum k, in a quantum well is quantized which gives rise to quantized level En (i.e., h2k,2/2m* = h2n2/8m*W),the energy of carriers in each subband is a function of the lateral momentum kL only, given by E , = En+-h.2kf 2m* From Eq. 67 it should be noted that the energy of carriers is quantized only for the bottom of the subband, but the energy above En is continuous. The free-electron energy in the emitting electrode is, on the other hand, given by E = E c + -h2k2 = E,+-+h-2.k,2 h2kf 2m* 2m* 2m* 8.4 RESONANT-TUNNELING DIODE 457 A J Barrier Barrier Fig. 34 I-V characteristics of resonant-tun- neling diode with multiple current peaks and valleys at low but finite temperature. The e V labels (a)> 1wherep= ,/2m*(E,-E)lh2? Note: The transmission coefficient is defined as (CIA)2where A and Care the amplitudes for the incident and the transmitted wave hnction, respectively. 2. The I-V characteristics of a specially designed GaSb tunnel diode can be expressed by Eq. 29, with J p = lo3A/cm2, Vp= 0.1 V, Jo = 10-5 A/cm2, and J , = 0. The tunnel diode has a cross-sectional area of cm2. Find the largest negative differential resistance and the corresponding voltage. 3. A GaSb tunnel diode has a lead inductance of 0.1 nH, a series resistance of 4 Q a junction capacitance of 77 fF,and a negative resistance of -20 SZ Find the frequency at which the real part of the input impedance becomes zero. 4. Find the speed index for the GaAs tunnel diode shown in Fig. 13. The device area is lo-' cm2,the diode is doped to 1020~ m o-n b~oth sides, the degeneracies on both sides are 30 mV. (Hint:Use abrupt junction approximation.) 5. Molecular beam epitaxy interfaces are typically abrupt to within one or two monolayers (one monolayer = 2.8 8, in GaInAs), due to terrace formation in the growth plane. Estimate the energy level broadening for the ground and first excited electron states of a 15-nm GaInAs quantum well bound by thick AlInAs barriers. (Hint:Assume the case of two monolayer thickness fluctuation and an infinite deep QW. TITB The electron effective mass in GaInAs is 0.0427m0). 6. Derive the transmission coefficient for a symmetric double-barrier resonant-tunneling diode, assuming that the effective AB_CD- - -EFGH mass is constant throughout the double- 10 barrier structure. The points A-H are adjacent to the potential steps and set boundary conditions for solution. x1 x2 x3 x4 PLBI Lw 1L.J 7. Find the lowest four resonant energy levels for a symmetric double-barrier structure with L, = 2 nm, L , = 2 nm, E, = 3.1 eV, and m' = 0.42m0. 8. Solve the finite-potential-well problem to find the bound energy levels En < E, and wavefunctionsX,(z) as a function of well width L, barrier height Eo and particle mass m* for the symmetric quantum well. Find the number of levels contained in a potential well with L = 10 nm and E, = 300 meV if the particle mass m' = 0.067m0,where mo is the free-electron mass. These parameters correspond approximately to electrons confined in a GaAs quantum well by AI,,35Ga,,,,As heterostructure barriers. 9. Estimate the energy broadening AE, and AE2for the lowest two levels in a model symmetric double-barrier potential resulting from tunneling out of the well (figure in Prob. 6). PROBLEMS 465 The parameters are well width L = 10 nm, barrier thickness L , = 7 nm, barrier E, = 300 meV, and m* = 0.067m0. To find the lifetimes, consider the electron to be a semiclassical particle bouncing back and forth inside the confining double-barrier potential with a tunneling probability of escaping from the well given by Eq. 64. 10. A symmetric GaAslAlAs RTD has a barrier width of 1.5 nm and a well width of 3.39 nm. When this RTD is inserted in the base of an HBT with an emitter flux centered on the first excited level of the RTD. Find the cutoff frequency of the HBT with the inserted RTD, if the originalf, was 100 GHz. [Hint:The transit time across the RT structure is given by (dlv,) + (2fiK)where d is the width of the RT structure, U, is the electron group velocity (lo7c d s ) , and is the resonant width (20 mev).] Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. IMPATT Diodes 9.1 INTRODUCTION 9.2 STATIC CHARACTERISTICS 9.3 DYNAMIC CHARACTERISTICS 9.4 POWER AND EFFICIENCY 9.5 NOISE BEHAVIOR 9.6 DEVICE DESIGN AND PERFORMANCE 9.7 BARITT DIODE 9.8 TUNNETT DIODE 9.1 INTRODUCTION The IMPATT (impact-ionization avalanche transit-time) diodes employ both impactionization and transit-time properties of semiconductor structures to produce dynamic negative resistance at microwave frequencies. Note that this negative resistance is different from, for example, that of the tunnel diode whose I-V curve has a negative dZ/dVregion. Instead, the negative resistance comes from tipe domain in which the ac current and voltage components are out of phase ( V .Z = negative). There are two delays that cause the current to lag behind the voltage. One is the avalanche delay caused by the finite buildup time of the avalanche current; the other is the transit-time delay from the finite time for the carriers to cross the drift region. When these two delays add up to half-cycle period, the diode dynamic resistance is negative at the corresponding frequency. The negative resistance arising from transit time in semiconductor diodes was first considered by Shockley in 1954, but based on a different injection mechanism-a forward-biasp-n junction current.' In 1958, Read proposed a diode structure consisting of an avalanche region as the injection mechanism, situated at one end of a relatively high-resistance region serving as the transit-time drift space for the gen- 466 9.2 STATIC CHARACTERISTICS 467 erated charge carriers (i.e., p+-n-i-n+or nf-p-i-pf).2 The experimental observation of the IMPATT oscillation was first reported by Johnston, DeLoach, and Cohen in 1965 from a regularp-n junction silicon diode, mounted in a microwave cavity and biased into reverse avalanche b r e a k d ~ w n .O~s,c~illation based on the Read diode was reported by Lee et al. later in the same year.5 The small-signal theory developed by Misawa6 and by Gilden and Hines7 has confirmed that a negative resistance of the IMPATT nature can be obtained from ap-n junction diode or a metal-semiconductor contact with any doping profile. The IMPATT diode is now one of the most powerful solid-state sources of microwave frequency. At the present time, the IMPATT diode can generate the highest cw power output at millimeter-wave frequencies of all solid-state devices, from 30 GHz to above 300 GHz. But there are two noteworthy difficulties in IMPATT circuit applications: (1) The noise is high and sensitive to operating conditions; and ( 2 )large reactances are present, which are strongly dependent on oscillation amplitude and it requires unusual care in circuit design to avoid detuning or even burnout of the diode.8 9.2 STATIC CHARACTERISTICS An IMPATT diode consists of a high-field avalanche region plus a drift region. The basic members of the IMPATT diode family are shown in Fig. 1. These are the Read diode, the one-sided abrupt p-n junction, the p-i-n diode (Misawa diode), the twosided (double-drift) diode, the hi-lo and lo-hi-lo diodes (modified Read diodes). We shall now consider their static characteristics, such as the field distribution, breakdown voltage, and space-charge effect. Consider Fig. l a first which shows the doping profile, electric-field distribution, and ionization integrand at breakdown condition for an idealized Read diode (p+-n-i-n+or its dual n+-p-i-p+).The middle n- and i-regions are totally depleted, indicated by the shaded area. The ionization integrand is given by I WD ( a )= anexp[-i ( a n -aP)&’ an>ap (1) where a,, and apare the ionization rates of electrons and holes, respectively, and W, is the depletion width. The avalanche breakdown condition as discussed in Chapter 2 is given by 6(a)&= 1 Because of the strong dependence of a o n an electric field, we note that the avalanche region is highly localized, that is, most of the multiplication processes occur in a narrow region near the highest field between 0 and x,, where X, is defined as the width of the avalanche region (to be discussed later). The voltage drop across the ava- p + n i(or v) n+ I P+I n n+ 2 n+ (d) (e) (f) Fig. 1 Doping profile, electric-fielddistribution,and ionization integrand for (a) Read diode; (b) one-sided abrupt diode; (c)p-i-ndiode; (d) double-drift diode; (e) hi-lo structure; and (0 lo-hi-lo structure. 468 9.2 STATIC CHARACTERISTICS 469 lanche region x, is defined as V,. It will be shown that both x, and V, have a profound effect on the optimum current density and the maximum efficiency of an IMPATT diode. The layer outside the avalanche region (x, I x I W,) is called the drift region. There are two limiting cases of the Read doping profiles. As the N,-region becomes zero, we have a one-sided abruptp+njunction. Figure l b describes the structure of a one-sided abrupt p-n junction. The avalanche region is highly localized near the junction. On the other hand, when the N,-region becomes zero instead we have a p-i-n diode (Fig. l ~ )T.he~p-i-n diode has a uniform field across the intrinsic layer under low-current conditions. The avalanche region corresponds to the full intrinsic layer width. Figure Id describes the structure of a two-sided abruptp-n junction. The avalanche region is located near the center of the depletion layer. The slight asymmetry of the integrand ( a )with respect to the location of the maximum field is because of the large difference between a,, and ap in Si. If a,, = apas in the case of Gap, (a)reduces to ( a ) = an = ap (3) and the avalanche region is symmetrical with respect to x = 0. Figure l e shows a modified Read diode, the hi-lo structure, in which the doping N2 is larger than that for a Read diode.9Figure If shows another modified Read diode, the lo-hi-lo structure, in which a clump of charge is located at x = b. Since a nearly uniform high-field region exists from x = 0 to x = b, the value of the maximum field can be much lower than that for a hi-lo diode. 9.2.1 Breakdown Voltage The breakdown voltage for the one-sided abrupt junction has been considered in Chapter 2 . We can use the same method as outlined in that chapter to calculate the breakdown voltages of other diodes. Even though the breakdown is ultimately determined by the ionization integrand, it is helpful and simpler to predict breakdown based on the maximum field that has been calculated at breakdown condition. Notice that in some of the structures in Fig. 1 (a, c, f), the maximum depletion is terminated by the lightly doped width and there is a discontinuity of field near the n+-terminal. In all others, the depletion-width edge is determined mostly by the doping and the field drops to zero at the depletion edge. For the one-sided (Fig. lb) and two-sided symmetrical abrupt junctions (Fig. Id), the breakdown voltages are given respectively by v - -1gmw, = - "" B-2 29N (1-sided) , v - - -1g m w , = -"" B-2 9N (2-sided), where Ernis the maximum field, which occurs at x = 0. The maximum fields at break- down for Si and (100)-oriented GaAs two-sided (symmetrical) abrupt junctions, together with the one-sided abrupt junctions, are shown in Fig. 2. Once the doping is known, the breakdown voltage can be calculated from Eq. 4a or 4b, using the 470 CHAPTER 9. IMPATT DIODES Fig. 2 Maximum electric field at breakdown vs. doping for Si and GaAs one-sided and twosided abrupt junctions. (After Refs. 10 and 11.) maximum field value from Fig. 2. The applied reverse voltage at breakdown is equal to (V, - iybi)w, here Vbi is the built-in potential, in the case of symmetrical abrupt junction given by 2(kT/q)ln(N/ni). Usually Vbi is negligible for practical IMPATT diodes. For the Read diode, the breakdown voltage is given by The depletion width is limited by the thickness of the n--layer. For the hi-lo diode, the breakdown and depletion width are given by The maximum field at breakdown for a Read diode or a hi-lo diode with a given Nl is found to be essentially the same (within 1%) as the value of the one-sided abrupt junction with the same N,, provided that the avalanche width xA is smaller than b.12 Therefore, the breakdown voltages can be calculated from Eqs. 5 and 6 using the maximum field value of Fig. 2. For the lo-hi-lo diode with a narrow fully depleted clump of charge, the breakdown voltage is given by 9.2 STATIC CHARACTERISTICS 471 where Q is the impurity density per area (number/cm2) in the clump. Since the maximum field is nearly constant for 0 I x I b, ( a )is equal to llb at breakdown. The maximum field gmcan be calculated from the field-dependent ionization coefficient. 9.2.2 Avalanche Region and Drift Region The avalanche region of an ideal p-i-n diode is the fill intrinsic-layer width. For the Read diode and p-n junctions, however, the region of carrier multiplication is restricted to a narrow region close to the metallurgical junction. The contribution to the integral in Eq. 2 decreases rapidly as x departs from the metallurgical junction. r'2 Thus a reasonable definition of the avalanche-region width xA is obtained by taking the distance over which 95% of the contribution to the integral is obtained, that is, r ( a ) h or (a)& = 0.95. (9) -xA/2 Figure 3 shows the avalanche widths as a function of the doping for Si and GaAs diodes." Also shown are the depletion widths of Si and GaAs symmetrical two-sided junctions. For a given doping, the Si n+-pjunction has a narrower avalanche width than that inp+-njunction because of the difference in ionization rates (a,> a$. For a Read diode or a hi-lo diode, the avalanche region will be the same as a one-sided 100 h 5v &Q 10 3 '5 .E- c e 81 0 2 75 A 5 s 0.1 -9 m P 0.01 1015 10'6 1017 1 18 Doping N ( ~ r n - ~ ) Fig. 3 Avalanche region widths xA for Si and GaAs junctions. Also shown are depletion widths W, of Si and GaAs symmetrical 2-sidedjunctions.(After Ref. 11.) 472 CHAPTER 9. IMPATT DIODES abrupt junction with the same doping N , . For a lo-hi-lo diode, the avalanche region width is equal to the distance between the metallurgical junction and the charge clump X, = b. The drift region is the depletion layer excluding the avalanche region, or x, Ix IW,. The most-important parameter in the drift region is the carrier drift velocity. To obtain consistent and predictable carrier transit time across the drift region, the electric field in this region should be high enough that the generated carriers can travel at their saturationvelocities us.For silicon the electric field should be larger than lo4V/cm. For GaAs, the field can be much smaller (= lo3V/cm) due to its high carrier mobilities. Forp-i-n diodes, this requirementis fulfilledautomatically,because at breakdown the field (which is approximatelyconstant over the full intrinsic width) is much larger than the required field for velocity saturation.For a Read diode the minimum field in the drift region is given by Clearly, from the previous discussion, a Read diode can be designed so that gmiins sufficiently large. For abrupt junctions, since the field drops to zero at the depletion edge, some regions always have fields smaller than the minimum required field. The low-field region, however, constitutes only a small percent of the total depletion region. For example, for a Si pf-n junction with 10l6~ m b-ac~kground doping, the maximum field at breakdown is 4 ~ 1 V0/c~m. The ratio of the low-field region (for a field less than lo4V/cm) to the total depletion layer is 104/4x105= 2.5%. For a GaAs p+-n junction with the same doping, the low-field region is less than 0.2%. Thus, the low-field region has negligible effect on the total carrier transit time across the depletion layer. 9.2.3 Temperature and Space-Charge Effects The breakdown voltages and the maximum electric fields discussed previously are calculated for room temperature under isothermal conditions, free of space-charge effects (from high-level injection), and in the absence of oscillation. Under operating conditions, however, the IMPATT diode is biased well into avalanche breakdown, and the current density is usually very high. This results in a considerabletemperature rise in the junction and a large space-charge effect. The ionization rates of electrons and holes decrease with increasing temperature.13Thus for an IMPATT diode with a given dopingprofile, the breakdown voltage will increase with increasing temperature. As the dc power (product of reverse voltage and reverse current) increases, both the junction temperature and the breakdown voltage increase. Eventually, the diode fails to operate, mainly because of permanent damage that results from excessive heating in localized spots. Thus, the rising temperatureof the junction imposes a severe limit on device operation.To prevent the temperature rise, one must use a suitable heat sink. This will be considered in Section 9.4.4. 9.2 STATIC CHARACTERISTICS 473 The space-charge effect causes a change of electric field in the depletion region due to extra space charge. This effect gives rise to a positive dc differential resistance for abrupt junctions and a negative dc differential resistance forp-i-n diodes.14 Consider first a one-sidedp+-n-n+abrupt junction as shown in Fig. 4a. When the applied voltage is equal to the breakdown voltage VB,the electric field g(x) has its maximum absolute value gm at x = 0. If we assume that the electrons travel at their saturation velocity usacross the depletion region, the space-charge-limited current is given by I = AgAnv, (11) where An is the high-level injected carrier density and A the area. The disturbance Ag(x) in the electric field due to the space charge is obtained from Eq. 11 and the Poisson equation: V(vo1ts) V(v0lts) (a) (b) Fig. 4 Doping profile, field, and current-voltagecharacteristics of (a)p+-n-n+and (b)p+-v-n+ diodes. Area = lo4 cm2. (After Ref. 14.) 474 CHAPTER 9. IMPATT DIODES If we assume that all the carriers are generated within the avalanche width xA,the disturbance in voltage caused by the carriers in the drift region (W, -xA)is obtained by integrating AE(x) over this drift region: The total applied voltage is, thus, increased by this amount to maintain the same current. The space-charge resistanceI5 is obtained from Eq. 13: For our example shown in Fig. 4a, the space-charge resistance is about 20 0 For a p-i-n or a p - v-n diode, the situation is different from that of a p+-njunction. When the applied reverse voltage is just large enough to cause avalanche breakdown, the reverse current is small. The space-charge effect can be neglected and the electric field is essentially uniform across the depletion layer. As the current increases, more electrons are generated near the p+-vboundary and more holes are generated near the v-n+boundary (by impact ionization as the electric field has double peaks, Fig. 4b). These charges will cause a reduction of the field in the center of the v-region that decreases the total terminal voltage. This reduction results in a negative differential dc resistance for thep- v-n diode, as shown in Fig. 4b. 9.3 DYNAMIC CHARACTERISTICS 9.3.1 Injection Phase Delay and Transit-Time Effect We consider first the injection phase delay and transit-time effect of an idealized device,16whose structure is shown in Fig. 5 where we move the x-origin to the right of the avalanche region (plane of charge injection). The terminal voltage and the avalanche generation rate are also shown in relation to each other. The terminal voltage, of angular frequency has a mean value at the verge of avalanche breakdown V,. In the positive cycle, avalanche multiplication begins. The generation rate of carriers, however, as shown, is not in unison with the voltage or field. This is because the generation rate is not only a function of the field but also of the number of existing carriers. After the field passes the peak value, the generation rate continues to grow until the field is below the critical value. This phase lag is approximately nand is called the injection phase delay. Assume that an avalanche charge pulse is injected at x = 0, in Fig. 5, with a given phase angle delay @withrespect to the terminal voltage. Also assume that the applied dc voltage across the diode causes the carriers to travel at the saturation velocity v, in the drift region, 0 I x I W,. The ac conduction current density J , is also a function of location x, and its magnitude is related to the total ac current density by: Drift region Injection 9.3 DYNAMIC CHARACTERISTICS 475 !----- 0 Injection plane (a) Fig. 5 (a) Idealized IMPATT diode with carrier injection at x = 0 and a drift region with saturation velocity. (b) Terminal voltage and avalanche generation rate in time domain. The avalanche lags the voltage by I$ = n. The total ac current anywhere in the drift region is given by the sum of the conduction current and the displacement current: J ( x ) = J,(X) +J&) where k (x) is the ac field. From Eqs. 15 and 16 we obtain Integrating Eq. 17 gives the ac impedance where CDis the depletion capacitance per unit area &,/WD,and 0 is the transit angle e = -W. WD (19) US By taking the real and the imaginary parts of Eq. 18, we obtain 476 CHAPTER 9. IMPATT DIODES We consider next the influence of the injection phase # on the ac resistance R,,, based on Eq. 20. When # equals zero (no phase delay), the resistance is proportional to (1 - cosB)/B, which is always greater or equal to zero, as shown in Fig. 6a; that is, there is no negative resistance. Therefore, the transit-time effect alone cannot give rise to negative resistance. However, for any nonzero #, the resistance is negative for certain transit angles. For example, at # = nf2, the largest negative resistance occurs near B= 3nf2, as shown in Fig. 6b. For # = z,the same occurs near 8= z,as shown in Fig. 6c. This corresponds to the IMPATT operation, in which the buildup of the injection current due to impact avalanche introduces a phase delay of about z,and the transit time in the drift region gives an additional zdelay. The foregoing considerations have confirmed the importance of the injection delay. The problem of finding active transit-time devices has been reduced to finding a means to delay the injection of conduction current into the drift region. From Fig. 6 we observe that the sum of the injection phase and the optimum transit angle, 4 + eopt, ; 1-case 0.2 0 sin B :::[\ 00..64 0.4 0.2 - 0 -0.2 - 1 -0.4 (=0 e ( = _n 2 -c )e -0.4 -0.6 (= n -0.8 -1.0 Fig. 6 AC resistance vs. transit angle for three different injection phase delays. (a) 4 = 0. (b) 4 = d2. (c) 4 = z. 9.3 DYNAMIC CHARACTERISTICS 477 is approximately equal to 2n. As 4 increases from zero, the magnitude of the negative resistance becomes larger. 9.3.2 Small-Signal Analysis The small-signal analysis was first considered by Read and developed further by Gilden and H i n e ~F.o~r simplicitywe assume that a,,= ap= a, and that the saturation velocities of holes and electrons are equal. Figure 7a shows the model of a Read diode. According to the discussion in Section 9.2, we have divided the diode into three regions: (1) the avalanche region, which is assumed to be thin so that spacecharge and signal delay can be neglected; ( 2 ) the drift region, where no carriers are Avalanche Inactive Inductive I I Fig. 7 (a) Model of Read diode with avalanche, drift, and inactive regions, and (b) its equivalent circuit. For small transit angle ,6, (c) equivalent circuit and (d) plots of real and imaginary parts of impedance vs. angular frequency w (After Ref. 7.) 478 CHAPTER 9. IMPATT DIODES generated, and all carriers entering from the avalanche region travel at their saturation velocities; and (3) an inactive region that adds undesirable parasitic resistance. The two active regions interact with each other, because the ac electric field is continuous across the boundary between them. We shall use a “0” subscript to indicate dc quantities, and “-” to indicate small-signal ac quantities. For quantities includins both dc and ac components, no “0” subscript or “-” will be added. We first define JAas the avalanche current density, which is the ac conduction (particle) current in the avalanche region, and J 5s the total ac current density. With our assumption of a thin avalanche region, JAis presumed to enter the drift region without-delay. With the assumption of a saturation velocity vs,the ac conduction current Jc(x) in the drift region propagates as an unattenuated wave (with only phase change) at this drift velocity, where y= j,/j is the complex fraction relating the avalanche current to the total cur- rent. At any x-location, the total alternating cjrrent J equals the sum of the conduc- tion current j cand the displacement current J d .This sum is constant, independent of position x. Equation 17 is rewritten as (putting 4 = 0): Integrating k (x) gives the voltage across the drift region in terms of j . The coeffi- cient y is derived in the analysis that follows. Avalanche Region. Consider first the avalanche region. Under the dc condition, the direct current Jo (=Jpo+J,,) is related to the thermally generated reverse saturation current J, (=J,, + J,,) by Jo = JS (24) 1- (a)dx. At breakdown, J, approaches infinity and the integral is equal to unity. In the dc case the integral cannot be greater than unity. This is not necessarily so for a rapidly varying field. The differential equation for the current as a function of time will now be derived. Under the conditions that (1) electrons and holes have equal ionization rates and equal saturation velocities, and (2) the drift current components are much larger than the diffusion component, the basic device equations in the one-dimensional case can be written as follows: J = J,,+ J, = qv,(n +p ) , current-density equation, (25) 9.3 DYNAMIC CHARACTERISTICS 479 a_n at = -I -aJn qax + av,( n +p ) , continuity equations, (264 GL? = -1% + a v , ( n + p ) . at qax The second terms on the right-hand side of Eqs. 26a and 26b correspond to the generation rate of the electron-hole pairs by avalanche multiplication. This generation rate is so large compared to the rate of thermal generation that the latter can be neglected. Adding Eqs. 26a and 26b and integrating from x = 0 to X, gives zAdd-tJ = -(J,-J,,)I XA 0 where ,z =x,/v, is the transit time across the multiplication region. The boundary conditions are that the electron current at x = 0 consists entirely of the reverse saturation current J,,. Thus at x = 0, the boundary condition is J,-J, = - 2 J , , + J = -2J,,+J. (28a) At x = x, the hole current consists of the reverse saturation current Jpsgenerated in the space-charge region, so we have J,-J,, = 2 J p - J = 2J,,-J. (28b) With these boundary conditions, Eq. 27 becomes In the dc case, J is the direct current J,, so that Eq. 29 reduces to Eq. 24. a a We now simplify Eq. 29 by substituting in place of a, where is an average value of a obtained by evaluating the integral over the extent of the avalanche region. We obtain (by neglecting the term J,) Furthermore the small-signal assumptions are now made: where a‘ = adaz?and the substitution a = a’&, has been employed. Substituting the expressions above into Eq. 30, neglecting products of higher-order terms, leads to the expression for the ac component of the avalanche conduction current, 480 CHAPTER 9. IMPATT DIODES - - The displacement current in the avalanche region is simply given by JAd = jU&,EA. (36) The above are the two components of the totjal circuit current in the avalanche region. For a given field, the avalanche current JA is reactive and varies inversely with was in an inductor. The other component,JAd, is also reactive and varies directly with w as in a capacitor. Thus the avalanche region behaves as an LC parallel circuit. The equivalent circuit is shown in Fig. 7b, where the inductance and capacitance are given as (where A is the diode area) The resonant frequency of this combination is given by 2 a'v,J, (39) A thin avalanche region, therefore, behaves as an antiresonant circuit with a resonant frequency proportional to the square root of the direct current density J,. The impedance of the avalanche region has the simple form The factor ycan be expressed as I y& J = 1 J 1 -(w2/w:) Drift Region. Combining Eqs. 41 and 23 and integrating over the drift length (WD-xA)gives an expression for the ac voltage across this region as, where ed is the transit angle of the drift space and 9.3 DYNAMIC CHARACTERISTICS 481 We may also define C, =A€,/( W, -xA) as the capacitance of the drift region. From 1 '1 Eq. 42-we obtain the impedance for the drift region, 1 i-cose 1 sin @d 1 - ( d / U , ? ) ( 6 d d ) ] + m c D [ 1 - ( d / w z ) ( T )- = R,,+jX (45) where R,, and Xare the resistance and reactance, respectively. At low frequencies and with 4 = 0, it can be seen that Eq. 45 reduces to Eqs. 20 and 21. The real part (resis- tance) will be negative for all frequencies above w,, except for nulls at 6d = 2nxinteger. The resistance is positive for frequencies below w,., and approaches a finite value at zero frequency: The low-frequency small-signal resistance is a consequence of the space charge in the finite thickness of the drift region, and the expression above is identical to Eq. 14 derived previously. Total Impedance. The total impedance is the sum of the impedances of the avalanche region, drift region, and passive resistance R, of the inactive region: The real part is the dynamic resistance and it changes sign from positive to negative as w becomes larger than w,.. Equation 47 has been cast in a form that can be simplified directly for the case of small transit angle Bd. For 8, < d 4 , Eq. 47 reduces to where C, = EJ/ W, corresponding to the total depletion capacitance. The equivalent circuit and frequency dependence of the real and imaginary parts of the impedance are shown in Fig. 7c and d, respectively. In Eq. 48, note again that the first term is the active resistance, which becomes negative for w > w,.,The second term is reactive and corresponds to a parallel resonant circuit that includes the diode capacitance and a shunt inductor. The reactance is inductive for w < w, and capacitive for w > w,. In other words, the resistance becomes negative at the frequency where the reactive component changes sign. 482 CHAPTER 9. IMPATT DIODES 9.4 POWER AND EFFICIENCY 9.4.1 Large-Signal Operation Under large-signal operation, a high-field avalanche region exists at the p+-njunction of a Read diode (Fig. la), where electron-hole pairs are generated; and a constantfield drift region exists in the low-doped v-region. The generated holes quickly enter the p+-region and the generated electrons are injected into the drift region, where they do work that produces external power. As discussed before, the ac variation of the injected charge lags the ac voltage by about n,as injection delay 4 shown in Fig. 8. The injected carriers then enter the drift region, where they traverse at saturation velocity, introducing the transit-time delay. The induced external current is also shown. Comparing the ac voltage and the external current clearly shows that the diode exhibits a negative resistance at its terminals. For large-signal operation, the terminal current is mostly a result of the charge generated by avalanche multiplication and its movement. When the electron packet (of charge density Qava)traverses toward the n+-region (anode) with a saturation velocity, an external current is induced. The terminal conduction current can be obtained by calculating the induced charge partitioned at the anode or cathode. Consider for example, the charge density at the anode QAwhich is a function of the location of Q, and it is given by The peak conduction current is thus given by I I I I I I I 1 Fig. 8 Large-signal operation of IMPATT diode, showing terminal voltage, avalanche gener- ation rate, and terminal current. 4 = injection delay. 8= transit-time delay. 9.4 POWER AND EFFICIENCY 483 For maximum power efficiency, this current should drop near the end of the voltage cycle before the voltage rises above the mean value. Since the duration of the current pulse corresponds to the transit time of the charge packet and is equal to half cycle, the frequency of operation is optimized at For practical oscillators the biasing circuits are shown in Fig. 9, and the currentsource bias scheme is more common than the voltage-source. The external resonator circuit has a resonant frequency matching that of Eq. 51. Note that the terminal ac voltage across the IMPATT diode in the preceding discussions can be generated from a dc biasing circuit, the basic function of an oscillator. With a dc bias, any noise generated internally would be amplified because of positive feedback, until a stabilized ac waveform is established with the above current magnitude and frequency. Figure 8 shows that positive ac current coincides with the negative ac voltage, a phase shift of z r.This is the origin of dynamic negative resistance, or negative power absorbed by the device. Note that for the terminal current waveform, the start of the current pulse is determined by the injection delay, while the end is determined by the transit delay. The capability of power generation from a transit-time device should not be confused with the phase difference also introduced in the ac characteristics of a capacitor or inductor. The phase difference in these passive devices between its terminal voltage and current is d2. So for half of the cycle, power absorbed by the device is negative but is positive for the other half cycle. These cancel each other exactly and the net power is zero. 9.4.2 Power-Frequency Limitation-Electronic Because of the inherent limitations of semiconductor materials and the attainable impedance levels in microwave circuitry, the maximum output power at a given fie- Resonator Resonator IMPATT Load (a) (b) Fig. 9 Biasing circuits for IMPATT-diodeoscillators, with (a) current source and (b) voltage source. 484 CHAPTER 9. IMPATT DIODES quency of a single diode is limited. The limitations on semiconductor materials are (1) the critical electric field 2?, at which the avalanche breakdown occurs, and (2) the saturation velocity us, which is the maximum attainable velocity in the semiconductor. The maximum voltage that can be applied across a semiconductor sample is limited by the breakdown voltage, which, for a maximum, uniform avalanche region, is given by V, = Z?, W,. The maximum current that can be carried by the semiconductor sample is also limited by the avalanche-breakdownprocess, because the avalanched charge in the drift region causes a disturbance in the electric field. With the maximum avalanched charge Q,, given by 8 ,(G~au~ss' law), the maximum current density is given by Therefore, the upper limit on the power density is given by the product of V, and J,: P, = V,J, = 2?; &pS. (53) Combining with Eq. 51, Eq. 53 can be rewritten as where X,is the reactance (2zfC,)-'. In practical high-speed oscillator circuits,X, is found to be fixed due to interaction with some minimum external circuit impedance and the avalanche region that has been neglected. Equation 54 thus predicts that the maximum power that an IMPATT diode can be designed for decreases as 1/J?. This electronic limit is expected to be dominant above the millimeter-wave frequencies (> 30 GHz) for Si and GaAs. For a practical operating junction temperature of 150" to 200"C, 2?, in Si is about 10% smaller than that in GaAs. On the other hand, usin Si is almost twice as large as in GaAs. Therefore,in the electronic-limited range (i.e., above millimeter-wave frequencies), the Si IMPATT diode is expected to have a power output about three times as large compared to that of GaAs, operated at the same frequency." In the submillimeter-wave region, the uniform-field Misawa diodes are expected to be preferred because the device has a broad negative-resistanceband and the transit-time effects do not play the dominating role in producing negative resistance as they do in Read diodes.I8 Under pulsed conditions where thermal effects can be ignored (i.e., short pulses), the peak power capabilityis determinedby electronic limits (i,e.,P cc l/J?) at all frequencies. 9.4.3 Limitation on Efficiency For efficient operation of an IMPATT diode, as carriers move through the drift region, as large a charge pulse Q, as possible must be generated in the avalanche region without reducing the electric field in the drift region below that required for velocity saturation.The motion of Q,, through the drift region results in an ac voltage ampli- 9.4 POWER AND EFFICIENCY 485 tude mV,, where m is the modulation factor ( mI 1) and V, is the average voltage developed across the drift region. At the optimum frequency (= vJ2WD),the motion of QUv, also results in an alternating particle current that has a phase delay of 4 with the ac voltage across the diode. If the average of the particle current is J,, the particle current swing is at most from zero to W,. For a square waveform of particle current and a sinusoidal variation of drift voltage, both with magnitude and phase as described above, the microwave power generating efficiency 17 is 19,20 4 7' ac power output dc power input -- ( 2Jo/4( Jo( VA+ mV D V,) I) COS where VAand V, are the dc voltage drops across the avalanche region and the drift region respectively and their sum is the total applied dc voltage. The angle 4 is the injection phase delay of the particle current. Under ideal conditions, 4 is n and Icosq5 = 1. For double-drift diodes, the voltage V, is replaced by 2V,. The ac power contribution from the avalanche region is neglected because the avalanche-region voltage is inductively reactive relative to the particle current. The displacement current is capacitivelyreactive relativeto the diode voltage and, therefore, contributes no average ac power. Equation 55 clearly shows that to improve the efficiency one must increase the ac voltage modulation factor m,optimizethe phase delay angle toward n,and reduce the VA/VDratio. However, V, must be sufficiently large to initiate the avalanche process rapidly; below a certain optimum value of VAlV,, the efficiency falls off toward zero.19 If the drifting carriers are velocity saturated at very low field, m could approach unity and no deleterious consequence would result. In n-type GaAs, the velocity is effectively saturated near 8x lo3V/cm, which is much smaller than the field value for n-type Si, 1: 2x104V/cm. Hence, much larger ac voltage swings can be expected in n-GaAs; these larger voltage swings, in turn, result in higher efficiency in n-GaAs.21 To estimate the optimum value of VAIVD,we first get V, = (8,)(W,-X,) = - ( us (56) 2f where (8,)is the average field in the drift region. For 100% current modulation, J, = Jdc= J,,, and a maximum charge Q,, = m.cs(8,)determines the current density: J O = Q,vJ = ( 8D>f. (57) For an ionization coefficient having a field dependence of a cc 86where 6 is a con- stant, the value of a' can be obtained as 486 CHAPTER 9. IMPATT DIODES Assume that the transit-time frequency (Eq. 51) is about 20% larger than the resonant frequency (Eq. 39), combining Eqs. 56 through 58 yields 2o For the relatively low frequency of N 10 GHz, the optimum value of VAW, for GaAs is 0.65 with m = 1, while for Si the optimum value is about I. 1 with m = 1/2. A plot of the efficiency versus VA/VDis shown in Fig. 10. The maximum efficiency is obtained using the optimum values discussed above. The expected maximum efficiency is about 15% for single-drift (SD) Si diodes, 2 1% for doubledrift (DD) Si diodes, and 38% for single-drift GaAs diodes. The foregoing estimates are consistent with experimental results. At higher frequencies, the optimum ratio VA/VDtends to increase; this increase results in a reduction of the maximum efficiency. The experimental results for n-GaAs single-drift diodes are also in agreement with the foregoing discussion.22 In practical IMPATT diodes, many other factors reduce the efficiency. These factors include the space-charge effect, reverse saturation current, series resistance, skin effect, saturation of ionization rate, tunneling, intrinsic avalanche response time, minority-carrier storage, and thermal effect. The space-charge effect is shown in Fig. 11.23 The generated electrons will depress the field (Fig. 1la). The reduction in field may turn off the avalanche process prematurely and reduce the 180" phase delay provided by the avalanche. As the electrons drift to the right (Fig. 1lb), the space charge may also cause the field to the left of the carrier pulse to drop below that required for velocity saturation. This drop, in turn, will change the terminal current waveforms and reduce the power generated at the transit-time frequency. 7" 30 - I h E 20- ,I P 10 - a* 5.0 4 I I Fig. 10 Efficiency vs. ratio V,lV, for Si and GaAs diodes. SD, DD = single, double drift. Dashed lines are estimated linear extrapolation from peak to zero. (After Ref. 20.) 9.4 POWER AND EFFICIENCY 487 x., Y.-/ - ./Break :down field - - Electrons + + Holes / With charge \I Distance -* Distance Fig. 11 Instantaneous field and charge distributions in a Read diode. (a) Avalanching just completed, charge beginning to move across diode. (b) Charge transit nearly completed. Note the strong effect ofthe space charge in depressing the electric field. (After Ref. 23.) A high reversed saturation current causes the avalanche to build up too soon, reducing the avalanche phase delay and thus the The minority injection from a poor ohmic contact will also increase the reverse saturation current and thus reduce the efficiency. Near the end of the drift region, the field is smaller. The carriers travel in the mobility regime at a reduced speed from the saturation velocity.25The unswept layer gives rise to a series resistance that reduces the terminal negative resistance. Note, however, that the effect on n-GaAs is much smaller, because GaAs has much higher low-field mobility. As the operating frequency of an IMPATT diode is increased into the millimeter- wave region, the current will be confined to flow within a skin depth 6 o f the surface of the substrate. The skin effect is shown in Fig. 12.26Thus, the effective resistance of the substrate is increased, giving rise to a voltage drop across the radius of the diode (Fig. 12b). This voltage drop will cause nonuniform current distribution in the diode and a high effective series resistance, both of which reduce efficiency. However, advanced fabrication technologies have effectively eliminated this issue of skin effect, and it only plays a minor role in some upside-down mounted devices. For very-high-frequency operation, the depletion width has to be quite narrow (Eq. 51) and the field required for impact ionization becomes higher in order to satisfy the integral criterion of Eq. 2. There are two major effects at such high fields. The first effect is that the ionization rate will vary slowly at high field, broadening the 488 CHAPTER 9. IMPATT DIODES (a) (b) Fig. 12 Skin effect in IMPATT diode. (a) Current flow confined to a surface lamina of thickness S, causing nonuniformity and resistive loss. (b) Calculated voltage drop in the substrate at 100 GHz for several diode diameters D. (After Ref. 26.) injected current pulse2' and changing the terminal current waveforms so that the effi- ciency is reduced. The second effect is the tunneling current, which may be dominant. Since it is in phase with the field, the 180" avalanche phase delay is absent. Another factor that limits performance at submillimeter waves is the finite delay by which the ionization rate lags the electric field. For Si this intrinsic avalanche response time ziis less than s. Since this time is very small compared to the transit time in the submillimeter-wave region, Si IMPATT diodes are expected to be efficient up to 300 GHz or higher frequencies. For GaAs, however, 5 is found to be an order of magnitude longer than that of Si.28Such a long zj may limit the GaAs IMPATT operation to frequencies below 100 GHz. Minority-carrier storage effects in p+-n (or n'-p) diodes arising from back difh- sion of the generated electrons (or holes) from the active layer into the neutralp+- (or n+-) region can occur and will degrade the efficiency. This minority carrier will be stored in the neutral region while the remaining carriers are in transit and will diffuse back into the active region at a later time in the cycle, causing a premature avalanche which destroys the current-voltage phase relationship. 9.4.4 Power-Frequency Limitation-Thermal At lower frequencies, the cw performance of an IMPATT diode is limited primarily by thermal considerations, that is, by the power that can be dissipated in a semiconductor chip. A typical device mounting arrangement is that the IMPATT diode is bonded upside down onto the substrate of good thermal conductivity, such that the heat source is closest to the heat sink. If the contacts to the top diode surface have multiple layers of metals, the total thermal resistance is given by the series combination of 29 9.5 NOISE BEHAVIOR 489 where d, and K, are each layer thickness and its thermal conductivity of metal layers on the diode surface, while zh, Kh, and R, are each layer thickness, its thermal conductivity, and the contact radius (close to the device) of the heat sink. For a single-layered semi-infinite heat sink, zhlRhapproaches infinity and the second term reduces to the familiar expression of llm,R,. Copper and diamond are two common heat-sink materials. Since diamond has a thermal conductivity three times that of copper, there is a trade-off between performance and cost. The power P which can be dissipated in the diode must equal the heat power that can be transmitted to the heat sink. Therefore, P equals ATIR, where AT is the temperature difference between the junction and the heat sink. If the reactance X , = 2?&D is maintained constant ( f a l / c D ) and the major contribution to the thermal resistance is from the semiconductor (assuming that d, z WDR, T = W ~ A K , ) , we obtain for a given temperature increase AT Under such conditions, the cw power output will decrease as 1/J: Therefore, under cw conditions, at lower frequencies we have thermal limitation (P a l/j) and at higher frequencies we have electronic limitation ( P a 11J2). The corner frequency at which the power drops rapidly for a given semiconductor depends on the maximum allowed temperature rise, the minimum attainable circuit impedance, and the product of g,,, and v,. Burnout from Filament Formation. Burnout may occur not only if the diode is overheated, but also, more insidiously, if the carrier current fails to be uniformly distributed over the diode area and is instead concentrated into filaments of locally high intensity. Such untoward behavior can often result when the diode has a dc negative conductance because, then, the local region of greatest current density also has the lowest breakdown voltage. For this reason, p-i-n diodes are prone to easy burnout. The moving carrier space charge in the drift region tends to prevent low-frequency negative resistance and therefore helps to prevent filamentary burnout. Diodes that have positive dc resistance at low currents may develop negative dc resistance and burnout at high currents. 9.5 NOISE BEHAVIOR The noise in an IMPATT diode arises mainly from the statistical nature of the generation rates of electron-hole pairs in the avalanche region. Since the noise sets a lower limit to the microwave signals to be amplified, it is important to consider the noise theory of the IMPATT diode. 490 CHAPTER 9. IMPATT DIODES For amplification, the IMPATT diode can be inserted into a resonator that is coupled to a transmission line.30The line is coupled to separate input and output by means of a circulator, as shown in Fig. 13a. Figure 13b shows the equivalent circuit upon which the small-signal analysis is based. We shall now introduce two useful expressions for the noise performance: the noise$gui-e and the noise measure. The noise figure NF is defined as N F = 1 + output noise power from amplifier (power gain) x (kToB,) where Gpis the amplifier power gain, R, is the load resistance, To=room temperature (290 K), B , is the noise bandwidth, and (I:) is the mean-square noise current caused by the diode and induced in the loop of Fig. 13b. The noise measure M i s defined as Input Circulator Input Circulator Fig. 13 (a) IMPATT diode inserted into a resonator. (b) Equivalent circuit. (After Ref. 30.) 9.5 NOISE BEHAVIOR 491 where G is the negative conductance, -Zreatlhe real part of the diode impedance, and (q)the mean-square noise voltage. Note that both the noise figure and the noise measure depend on the mean-square noise current (or the mean-square noise voltage). It will be shown that for frequencies above the resonant frequency&, the noise in the diode decreases, but so does the negative resistance. In this situation the appropriate quantity for assessing the performance of the diode as an amplifier is the noise measure, whose minimum value (minimum noise measure) is of special interest. The noise figure for a high-gain amplifier is given by30 where z, and VAare, respectively, the time and voltage drop across the avalanche region; and u,.is the resonant frequency given in Eq. 39. The expression above is <= obtained under the simplified assumptions that the avalanche region is narrow and that the ionization coefficients of holes and electrons are equal. For 6 (for Si) and V, = 3 V, the noise figure atf= 10 GHz (w= u,)is predicted to be 11,000 or 40.5 dB. With realistic ionization coefficients (anf apfor Si) and an arbitrary doping pro- file, the low-frequency expression for the mean-square noise voltage is given by3 where a'= daldg:.Figure 14 shows ( ?)/Bl as a function of frequency for a silicon IMPATT diode with A = 10" cm2, WD= 5 pm, and xA = 1 pm. At low frequencies, c ) note that the noise voltage ( is inversely proportional to the direct current, Eq. 65. Po c ) Near the resonant frequency (which varies as ), ( reaches a maximum and then decreases roughly as the fourth power of frequency. Noise can therefore be reduced somewhat by operating well above the resonant frequency and keeping the Frequency (GHz) Fig. 14 Mean-square noise voltage over bandwidth vs. frequency for a Si IMPATT diode. (After Ref. 3 1 .) 492 CHAPTER 9. IMPATT DIODES Table 1 Noise Measure of IMPATT Diodes Semiconductor Ge Small-signal noise measure (dB) 30 Large-signal oscillator noise measure (dB) 40 Si GaAs 40 25 55 35 current low. These conditions conflict with conditions favoring high power and eficiency, so that trade-offs are necessary to optimize for particular applications. Figure 15 shows typical theoretical and experimental results of the noise measure in a GaAs IMPATT diode. At the transit-time frequency (6 GHz), the noise measure is about 32 dB. The minimum noise measure of 22 dB, however, is obtained at about twice the transit-time frequency. One important feature of the GaAs noise measure is that it is substantially lower than that for Si IMPATT diodes. Table 1 compares the noise measures of Ge, Si, and GaAs IMPATT diodes. The amplifier and oscillator noises in the table are for a lossless circuit at a frequency that corresponds to maximum oscillator efficiency without harmonic tuning. More-recent result gives a lower noise measure of 22 dB at 60 G H z . ~ ~ The main reason for the low-noise behavior in GaAs is that for a given field the electron and hole ionization rates are essentially the same, whereas in Si they are quite different. From the avalanche multiplication integral, it can be shown that to obtain a large multiplication factor Mthe average distance of ionization l/(a) is about equal to X, (the avalanche width) if a,, = ap,but is about x,/ln(M) if a;,>> ap.So, for a given xA,considerably more ionization events must occur in Si, resulting in higher noise. 45 40 h % 35 zf .* 30 2 25 I 1 1 I 2 4 6 8 10 Frequency (GHz) Fig. 15 Noise measure for GaAs IMPATT diodes. Transit-time frequency = 6 GHz. (After Ref. 32.) 9.6 DEVICE DESIGN AND PERFORMANCE 493 Figure 16 shows the relation between power output and noise measure for some Si and GaAs 6-GHz IMPATT diodes.34The power level is expressed with respect to a reference power of 1 mW, that is, the power is given by 10log(Px 103)dBm, where P is in watts. The diodes were evaluated in a single-tuned coaxial resonator circuit in which the load resistance presented to the resonator was incrementally varied by using interchangeable impedance transformers. At a maximum power output, the noise measure is relatively poor, A lower noise measure can be realized at the expense of a slightly reduced power output. Note again that at a given power level (say 1 W or 30 dBm), the GaAs IMPATT diode is about 10 dB quieter than a Si IMPATT diode. 9.6 DEVICE DESIGN AND PERFORMANCE From the small-signal theory, we can obtain approximate relations for various device parameters as a function of operating frequency. Ignoring the small avalanche region x, the resistance expression in Eq. 47 can be rewritten as where Bd is the transit angle equal to ~W,lv,. For fixed ulu,, for - R to be invariant it is required from Eq. 66 that both WDIA (prefactor) and B, be constant. Since the depletion width W, is inversely proportional to the operating frequency (Eq. 51), the device area A , which is proportional to w',,is thus proportional to w2.Also, from the avalanche breakdown equation, Eq. 2, it can be shown that the ionization rate ( a ) and its field derivative (a')are inversely proportional to the depletion-layer width 35 I 13.0 t23 lo.2 2ok 30 3b 38 42 46 5k'1 Noise measure (dB) Fig. 16 Power output vs. noise measure for a phase-locked oscillator. Locking power was held constant at 4 dBm. Contours of constant load impedance Z and constant diode current I are shown. (After Ref. 34.) 494 CHAPTER 9. IMPATT DIODES W., Combining the relation a' oc VW, with Eq. 39 yields the following result for the dc current density: These frequency scaling relations are summarized in Table 2 and are useful as a guide for extrapolating performance and design to new frequencies. The power-output limitations have been considered in Section 9.4. The efficiency is expected to be only weakly dependent on frequency at low frequencies. However, at millimeter-wave regions the operating current density is high (ocnand the area is small ( a f - 2 ) ,so that the device operating temperature will be high. This high temperature, in turn, will cause the reverse-saturation current to increase and the efficiency to decrease. In addition, the skin effect, tunneling, and other effects associated with high frequency and high field will also degrade the efficiency performance. Hence, as the frequency increases, the efficiency is expected to decrease eventually. Figure 17 shows the dependence of the threshold current density, that is, the minimum current density to produce oscillation, on the frequency. Note that the threshold current density increases approximately as the square of the frequency, in agreement with the general behavior of the resonant frequency. To demonstrate the importance of the transit-time effect, Fig. 18 shows the optimum depletion-layer width versus the frequency for Si and GaAs IMPATT diodes. The depletion-layer width, as expected, varies inversely with the frequency. Interestingly, at frequencies above 1 0 0 GHz, the depletion-layer width is less than 0.5 pm. This very narrow width gives some indication of the difficulty inherent in fabricating a modified Read diode or a double-drift diode at these high frequencies. The highest p0wer.f product is obtained from double-drift diodes. Figure 19 compares the performance of double-drift and single-drift diodes at 50 GHz. The double-drift 50-GHz Si IMPATT diode made by ion implantation shows an output cw power over 1 W with a maximum efficiency of 14%. This result can be compared with a similar single-drift diode that delivers about 0.5 W with an efficiency of 10%. The superiority of the double-drift diodes results from the fact that both holes and electrons produced by the avalanche are allowed to do work against the radio-fre- Table 2 Frequency Scaling (Approximate)for IMPATT Diodes Parameters ~~~ Frequency dependence Junction area A Bias-current density J, Depletion-layer width W, Breakdown voltage VB Power output Po,; Thermal limitation Efficiencv n Electronic limitation f -2 ff-' f-I f-' f -2 Constant 9.6 DEVICE DESIGN AND PERFORMANCE 495 Threshold wavelength (cm) 1 0.1 I I I F , I I IIIIII 111 10 30 100 5 10 Threshold frequency (GHz) Fig. 17 Dependence of threshold frequency on direct current density. (After Ref. 35.) quency (RF) field by traversing the drift regions. In the single-drift diodes only one type of carrier is so utilized. As a result, a larger terminal voltage can be applied. A summary of the state-of-the-art IMPATT performance is given in Fig. 20. Also shown are results for BARITT diodes to be discussed in Section 9.7. At lower frequencies, the power output is thermal-limited and varies asf-'; at higher frequencies (> 50 GHz) the power is electronic-limited and varies asf 2 . GaAs IMPATT diodes typically show better power performance at low frequencies below N 60 GHz. Figure 20 clearly shows that the IMPATT diode is one of the most powerful solidstate sources for the generation of microwaves. The IMPATT diodes can generate higher cw power output in the millimeter-wave frequencies than any other solid-state - -~ W, oc l/f(single drift) L -\ \ 1 !sh lo- v 1 Fig. 18 Depletion width vs. fre- quency for Si and GaAs IMPATT )O diodes. (After Refs. 36 and 37.) 496 CHAPTER 9. IMPATT DIODES 14 12 -E 10 6 .B- 8 0 Fig. 19 Efficiency of single- $6 drift vs. double-drift Si IMPATT diodes at 50 GHz. 4 Range of efficiency for four 2' A ' 6 ' diodes of each type. (After ' 1 0 ' ~ ~ ' 1 ~ ' ~ 6 ' l k 'Re2f. 3b8.) Current density J (kA/cm*) device. For pulsed operations, the power can even be higher than that shown in Fig. 20. Recently, materials other than Si and GaAs have been examined. For example, comparedto Si, Sic has a ten times higher breakdown field, a thermal conductivity of three times, and a saturation velocity of two times.40These factors contribute to an expected power output of more than 350 times higher than Si. The disadvantage is a 10 - r 0 IMPATTGaAs A0.5 A 0.2 A0.36 0 0.35 I 073 0.06 <0.03 I I IIIII I 50 70 100 200 Frequency (GHz) < 0.01 0 1 4 Fig. 20 State-of-the-art IMPATT (and BARITT) performances. The number against each experimental point indicates the efficiency in percentage. (After Ref. 39.) 9.7 BARITTDIODE 497 higher noise measure. High-bandgap GaN also offers similar advantages, as well as operation at higher temperat~re.~In, terms of structure, by incorporating a heterojunction at the injecting junction, GaN is expected to yield reduced leakage current, improved RF eficiency, and lower noise.42 9.7 BARITT DIODE Another transit-time device is the BARITT (barrier-injection transit-time) diode. The mechanisms responsible for the microwave oscillation are the thermionic injection and diffusion of minority carriers across the forward-biased barrier. Because there is no avalanche delay time, the BARITT diode is expected to operate at lower efficiency and lower power than the IMPATT diode. On the other hand, the noise associated with carrier injection across the barrier is smaller than the avalanche noise in an IMPATT diode. The low-noise property and the stability of the device make the BARITT diode suited for low-power applications, such as local oscillators. The BARITT operation was first reported by Coleman and Sze in 1971 using a metalsemiconductor-metal reach-through diode.43 Similar structures were proposed in 1968 by Ruegg based on large-signal analysis and by Wright using space-chargelimited transport mechanism^.^^,^^ 9.7.1 Current Transport The BARITT diode is basically a back-to-back pair of diodes biased into reachthrough condition (Fig. 2 1). The two diodes can be p-n junctions or metal-semiconductor contacts, or combination of the two. We consider first the current transport in a symmetrical metal-semiconductor-metal (MSM) structure46with uniformly doped n-type semiconductor (Fig. 2 1b). With bias, the depletion-layer widths are where W,,and W,, are the depletion widths in the n-layer for the forward- and reverse-biased barriers, respectively; V ,and V, are the fraction of the applied voltage vbj developed across the respective junctions, NO is the ionized impurity density; and is the built-in potential. Under these conditions, the current is the sum of the reverse saturation current (of a Schottky diode with a barrier height q&J, generation-recombination current, and surface leakage current. As the voltage increases, the reverse-biased depletion region will eventually reach through to the forward-biased depletion region (Fig. 2 1c). The corresponding voltage is called the reach-through voltage VRTT.his voltage can be obtained from the condi- n: tion W,,+ W,, = which is the length of the n-region: 498 CHAPTER 9. IMPATT DIODES P 4 ybi EF n EV Fig. 21 Energy-band diagrams of BARITT diodes having (a)p-njunctions and (b) M-S contacts, under thermal equilibrium. MSM structure at (c) punch-through and (d) flat-band conditions. If the voltage is increased further, the energy band at the positively biased contact (leR) can become flat. The electric field is zero at x = 0 when ybi= V,;this condition is the flat-band condition (Fig. 21d). The corresponding voltage is defined as the flatband voltage VFB: 9.7 BARITTDIODE 499 For a given length and with high doping levels, the applied voltage is limited by the avalanche breakdown voltage before reaching VFB. The dc bias for a BARITT diode under microwave oscillation is generally between VRT and VFB. For applied voltage in this range ( V R T< V< VFB), the relation between the applied voltage and the forward-biased barrier height is The reach-through point X , as shown in Fig. 21c is given by X-R--- VFB- V 2vFB After reach-through, the hole current of thermionic emission over the hole barrier 4Bp becomes the dominant current: where A; is the effective Richardson constant for holes (refer to Chapter 3). From Eq. 71 we obtain for V 2 V R T , Therefore, beyond reach-through the current will increase exponentially with applied voltage. At current levels high enough for the injected carrier density to be comparable to the background ionized-impurity density, the mobile carriers will influence the field distribution in the drift region. This is the space-charge effect. If all the mobile holes traverse the n-region with the saturation velocity us,and if J > g u y D ,the Poisson equation becomes e iE = = ~ ( N D + - L ; ) gJ- . (75) dx E, E, %Us Integrating twice (with boundary conditions E = 0, V= 0, at x = 0) yields47 The current transport mechanisms of the reach-through p+-n-p+ structure is similar to that of the MSM structure. The only difference is that in Eqs. 73 and 74, the factor exp(-q4,,lkr) should be absent when the carriers are injected over a forward- biased p+-n that is, For a PtSi-Si barrier, the hole barrier height q 4 B p is equal to 0.2 eV. Hence at 300 K for a given voltage above reach-through, the current for the p+-n-p+device will be 500 CHAPTER 9. IMPATT DIODES about 3000 times larger than that for the MSM device. The value o f A * pat room temperature is about lo7A/cm2. Therefore, under normal operation, the onset of the space-charge effect will occur long before the flat-band condition. Atypical I-Vcharacteristic is shown in Fig. 22 for a Sipc-n-pi with a background doping of 5 ~ 1 0~' ~m a-nd~a thickness of 8.5 pm. The flat-band voltage is 29 V and reach-through voltage is about 2 1 V. We note that the current first increases exponentially and then becomes linearly dependent on voltage. The experimental results and theoretical calculation from Eqs. 76 and 77 are in good agreement. For efficient BARITT operation, the current must increase very rapidly with voltage. The linear I- V relationship due to the space-charge effect will degrade device performance. The optimum current density is usually substantially lower than J = qvflD. 9.7.2 Small-Signal Behaviors We will show that the BARITT diode has small-signal negative resistance; therefore, the diode can have self-starting oscillation. Consider a p+-n-p+structure. When it is biased above the reach-through voltage, the electric-field profile is shown in Fig. 23a. The point xR corresponds to the potential maximum for hole injection, given by Eq. 72. The point a separates the low-field region from the saturation-velocity region, that is, for it: > gS,v = us,as shown in Fig. 23b. Under low-injection conditions, The transit time in the drift region (xR < x < W)is given by:49 ' Space-charge-limited current 103 f Thermionic injection current ' - ' ' _ - - - _Theory Experirnenl i p+-n-p+ No = 5x 1014~ m - ~ W = 8.5 prn 1l 00-2I 1 10' 1 02 v (volts) , Fig. 22 Current-voltage char- ~ acteristics of a Si p+-n-p+reach- lo3 through diode. (After Ref. 47.) A iegion 9.7 BARITTDIODE 501 ' 'Low-field Saturation-velocity region region Fig. 23 (a) Field distribution and (b) carrier drift velocity in the drift region of a BARITT diode. (After Ref. 48.) To derive the small-signal impedance, we shall follow an approach similar to that used in Section 9.3.2 and introduce the time-varying quantity as the sum of a timeindependent term (dc component) and a small ac term: ~ ( t=) J , + JexpGwt), (80) ~ ( t=) V,+ WiiexpGwt). (81) Substituting the foregoing expressions into Eq. 77 yields the linearized ac injected hole current density: -- J = og where o i s the injection conductance per unit area and is given by 502 CHAPTER 9. IMPATT DIODES J, is the current density given by Eq. 77, in which Vis replaced by V,. The injection conductance increases with the applied voltage, reaches a maximum, and then decreases rapidly when V, approaches VFBT, he bias voltage corresponding to the maximum m a n be derived from Eqs. 77 and 83: V,(for max a ) = VFE- (84) Since the ac electric field is continuous across the boundary of the injeckion and the drift regions, these two regions will interact with each other. We define J as the total alternating current density and J 1 as th_einjection current density. We assume that the injection region is thin enough that J1 enters the drift region without delay. The alternating conduction current density in the drift region is then given by J,(x) = J1exp[-jw> p2. The population ratio between the upper and lower valleys with an energy difference of AE is where R is the density-of-state ratio given by R = available states in all upper valleys available states in lower valley (4) 10.2 TRANSFERRED-ELECTRON DEVICE 513 The MI and M2are the numbers of equivalent lower and upper valleys, respectively. For GaAs, M , = 1and there are eight upper valleys in the L-direction, but they happen to be near the edge of the first Brillouin zone, and therefore M2= 4. Using the effective masses m ; = 0.067m0and m; = 0.55m0R, is found to be 94 for GaAs. The electron temperature T, is higher than the lattice temperature T since the elec- tric field accelerates the electrons and increases their kinetic energy. The electron temperature is determined through the concept of energy relaxation time re: where z,is assumed to be of the order of from Eq. 3, we obtain from Eq. 5, s. Substituting v from Eq. 2 and n2/nl We can compute T, as a function of the electric field for a given T and from Eqs. 2 and 3 the velocity-field characteristic can be written as (7) The general v-g curves as obtained from Eqs. 6 and 7 are shown in Fig. 2 for GaAs with three lattice temperatures. Also shown is the upper-valley population fraction P (= n21n)as a function of the field. Fig. 2 Calculated velocity-field characteristics for GaAs at three lattice temperatures based on a two-valley model having a single electron temperature. 514 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES From the v - 8 curves in Fig. 2, the I-V characteristics of the device duplicate exactly the same shapes. As seen, a region of negative differential resistance exists. However, what is unique in a TED is the origin of this NDR, which is the field dependence of drift velocity, as opposed to other mechanisms in a tunnel diode or a realspace-transfer diode. This field-dependent velocity leads to an interesting internal instability that forms the charge domains observed by Gunn as current pulses. Domain formation will be discussed in the next section. Here it is more appropriate to introduce the concept of differential mobility &, defined as This is different from the conventional low-field mobility ( p= v / 8 ) that we use in field-effect transistors. So by definition, the low-field mobility is independent of the field, which is not necessarily the case for differential mobility. In practical operating TEDs, the higher valley has lower mobility and the carriers residing there are driven into velocity saturation under a large field. The average velocity from Eq. 2 can then be modified to v = n,p1 8+ nzv, n1+ n2 = p18- P(p,g-us). (9) The differential mobility is given by pd = - dv = p l - P ) + ( v , - dP d8 1( P1 With some mathematical manipulation it can be shown that ,ud is negative under the operation condition of zd P > 1 - P 8-(vs/p1). (11) The simple models discussed above show the following points: (a) there is a welldefined threshold field (gT)for the onset of NDR (or negative differential mobility); (b) the threshold field increases with the lattice temperature; and (c) the negative mobility can be destroyed by having the lattice temperature too high or the energy dif- ference AE too small. Therefore, certain requirements must be met for the electron- transfer mechanism to give rise to bulk NDR: (1) The lattice temperature must be low enough that, in the absence of a bias electric field, most electrons are in the lower con- duction-band minimum, or kT < AE.( 2 )In the lower conduction-band minimum, the electrons must have high mobility, small effective mass, and low density of states; whereas in the upper satellite valleys, the electrons must have low mobility, large effective mass, and high density of states. (3) The energy separation between the two valleys must be smaller than the semiconductor bandgap so that avalanche breakdown does not set in before electrons are transferred into the upper valleys. Of the semiconductors satisfying these conditions, n-type GaAs and n-type InP are the most widely studied and used. The transferred-electron effect, however, has 10.2 TRANSFERRED-ELECTRON DEVICE 515 been observed in many other semiconductors, including Ge, some binary, ternary, and quaternary compounds (see Table l).1231*91T9he transferred-electron effect is observed in InAs and InSb under hydrostatic pressures that are applied to decrease the energy difference AE,which under normal pressures is greater than the energy gap. Of particular interest are the GaInSb ternary 111-V compounds for potential lowpower, high-speed applications because of their low threshold fields and high velocities. For semiconductors with large valley energy separations (e.g., Al,,,251no,75As with AE = 1.12 eV and Gao,61no,,Aswith AE = 0.72 eV) the negative resistance may become dominated by the central r-valley:20Monte Carlo calculations have shown that for these semiconductors, the presence of the upper valleys is not required for a negative-resistance effect but that polar optical scattering acting in a nonparabolic central valley alone gives rise to a peak velocity and negative-resistance effect. The measured room-temperature velocity-field characteristics for GaAs and InP are shown in Fig. 3. The analysis based on high-field carrier transport studies are in good agreement with the experimental r e s ~ l t s . ~T~h,e*th~reshold field gTdefining the onset of NDR is approximately 3.2 kV/cm for GaAs and 10.5 kV/cm for InP. The peak velocity up is about 2 . 2 I~O7 cm/s for high-purity GaAs and 2 . 5 l~o7 cm/s for high-purity InP. The maximum negative differential mobility is about -2400 cm2/V-s for GaAs and -2000 cm2/V-s for InP. The measured relative threshold field g:,(T)/gT(3O0K) and the relative peak velocity vp(T)/vp(300K) in GaAs as a h n c tion of lattice temperature are shown in Fig. 4. The simple model (Fig. 2) is in qualitative agreement with the experimental results. Table 1 Semiconductor Materials Related to Transferred-Electron Effect at 300 K Semiconductor GaAs InP Ge a CdTe I d sb InSb ZnSe Ga0.5In0.5Sb Ga0.3In0.7Sb 1*s0.2p0.8 Ga0.,31~.87AS0.37Po.63 EE(eV) 1.42 1.35 0.74 1.50 0.36 0.28 2.60 0.36 0.24 1.10 l.05 a At 77 K. (100)- or (1 10)-oriented. Under 14-kbarpressure. At 77 K under 8-kbar pressure. Valley Separation Between r-L r-L L-r r-L r-L r-L r-L r-L r-L r-L - AE (eV) 0.3 1 0.53 0.18 0.5 1 1.28 0.41 - 0.36 - 0.95 - ET(kV/cm) up(lo7c d s ) 3.2 2.2 10.5 2.5 2.3 1.4 11.0 1.5 1.6 3.6 0.6 5.0 38.0 1.5 0.6 2.5 0.6 2.9 5.7 2.7 5.5-8.6 1.2 516 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES T = 300 K I I I I I 5 10 15 20 25 30 35 FZ(kV/cm) Fig. 3 Measured velocity-field characteristicsfor GaAs and InP. (After Refs. 16 and 21.) 10.2.2 Domain Formation Unlike other various physical causes giving rise to negative differential resistance, a semiconductor exhibiting bulk negative differential mobility is inherently unstable, because a random fluctuationof carrier density at any point in the semiconductorproduces a momentary space charge that grows exponentially in time. The concept of domain formation and Gunn oscillation is demonstrated qualitatively in Fig. 5. The instability in a TED starts with a dipole which consists of excess electrons (negative 1.? 1 .: gh 1.1 0 .3 aQ 1.c aQ 0.5 0.8 I I 1 j0 200 250 300 T (K) Fig. 4 Measured peak velocity (relative to 300 K) and threshold field (relative to 300 K) in GaAs vs. temperature. (After Ref. 24.) 10.2 TRANSFERRED-ELECTRON DEVICE 517 3Drift direction (a) 11 n0 Drift directi; t (d) Fig. 5 Demonstration of domain formation. (a) u - 8 relationship and some critical points. (b) A small dipole grows to (c) a mature domain. (d) Terminal-current (Gunn) oscillation. Between t , and tz,matured domain is annihilated at the anode and another is formed near the cathode. charge) and depleted electrons (positive charge) as shown in Fig. 5b. The dipole may arise from many possibilities, such as doping inhomogeneity, material defect, or random noise. This dipole sets up a higher field for the electrons at that location. This higher field, according to Fig. 5a, slows these electrons down relative to the rest outside the dipole. As a result, the region of excess electrons will grow because the trailing electrons behind the dipole are arriving with a higher velocity. By the same token, the region of depleted electrons (positive charge) also grows because electrons ahead of the dipole leave with a higher velocity. As the dipole grows, the field at that location also increases, but only at the expense of the field everywhere else outside the dipole. The field inside the dipole is 518 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES always above go,and its carrier velocity decreases monotonically with field. The field outside the domain is lower than go,and its carrier velocity goes through the peak value and then decreases as the field is lowered. When the field outside the dipole decreases to a certain value, the velocities of electrons inside and outside the dipole are the same (Fig. 5c). At this point the dipole ceases to grow and is said to mature to a domain, usually still near the cathode. The domain then transits from near the cathode to the anode. The terminal-current waveform is shown in Fig. 5d. At t2,a domain is formed. At t,, the domain reaches the anode and before another domain is formed, the electric field throughout jumps to go.During the formation of a domain ( t , - t2),the field outsidethe dipole passes through the value of gTwhere the peak velocity occurs. This causes a current peak. The current pulse width corresponds to the interval between the annihilation of the domain at the anode and the formation of a new domain. The period T corresponds to the transit time of the domain from cathode to anode. We now treat the domain formation formally. The one-dimensional continuity equation is given by* If there is a small local fluctuation of the majority carriers from the uniform equilibrium concentration no, the locally created space-charge density is ( n - no).The Poisson equation and the current-density equation are J = -g- q D - dn p dx’ where p is the resistivity and D the diffusion constant. Differentiating Eq. 14 with respect to x and inserting the Poisson equation yields -1-dJ -- n---n 0 D-d2n qdx PE, dx2 Substituting this expression into Eq. 12 gives Equation 16 can be solved by separation of variables. For the spatial response, Eq. 16 has the solution * To avoid excessive minus signs, a positive charge will be assigned to electrons and all oper- ations are modified accordingly throughout this chapter. 10.2 TRANSFERRED-ELECTRON DEVICE 519 n - n o = ( n - n O ) l x = o e xLPD( ~ ) where LD is the Debye length, given by which determines the distance over which a small unbalanced charge decays. For the temporal response, Eq. 16 has the solution: n-no = (n-n exp(2), O)I,,O ZR where ,z is the dielectric relaxation time given by - zR=pEs = ES z- ES qpdn qpdnO which represents the time constant for the decay of the space charge to neutrality if the differential mobility pd is positive. However, if the semiconductor exhibits a negative differential mobility, any charge imbalance will grow with a time constant equal to I zJ,, instead of decay. Formation of a strong space-charge instability is dependent on the condition that enough charge is available in the semiconductor and the device is long enough that the necessary amount of space charge can be built up within the transit time of the electrons. These requirements set up a criterion for the various modes of operation. In Eq. 19, we have shown that for a device with negative differential mobility, the space charge grows exponentially with a time constant of I zRI = Es/qn0lpdu,lI.f this relation- ship remained valid throughout the entire transit time of the space-charge layer, the maximum growth factor would be exp(L/vd)zRI),where v, is the average driA velocity of the space-charge layer. For large space-charge growth, this growth factor must be greater than unity, making Lhdl z,l> 1, or For n-type GaAs and InP, the right-hand side of Eq. 2 1 is about 10l2cm-2. TEDs with n& products smaller than 10l2cm-2 exhibit a stable field distribution without current oscillation. Hence, an important boundary separating the various modes of operation is the (carrier concentration) x (device length) product, n& = 10l2cm-2. Domain maturity. The dipole layers will become stable in the sense that they propagate with a particular velocity but do not change in form and size with time. We will assume that the electron drift velocity follows the static velocity-field characteristic shown in Fig. 5a. The equations that determine the behavior of the electron system are the Poisson equation, Eq. 13, and the total current-density equation J = qn v( ' 8) - q d D(8 ax ) n+ E 8 s -d. 8 t 520 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES This equation is similar to Eq. 14 except for the addition of the third term, which corresponds to the displacement-currentcomponent. The solutions sought represent a high-field domain that propagates without change of shape, with a domain velocity ud. Outside the domain, the carrier concentration and fields are at constant values given by n = noand 8= g r ,respectively.For this type of solution, both 8 and n should be functions of the single variable, x' =x - udt.Note that n is a double-valued function of field. The domain consists of an accumulation layer where n > no,followed by a depletion layer where n < no.The carrier concentration n equals no at two field values, that is, 8= E r , outside the domain and at 8= gd,the peak domain field. Assume that the value of the outside field gr is known. (Later it will be shownthat 8,.is easily determined.) The current outside the domain consists only of conduction current (given later). Noting that and where ud is the domain velocity which is the average of carrier velocities inside the domain. One may rewrite Eqs: 13 and 22 as and dm= n [ u (8)- Ud] - no(ur- Ud). dx' We can eliminatethe variablex' from these equationsby dividing Eq. 26 by Eq. 25 to obtain a differential equation for [D(8)n]as a function of the electric field: In general, Eq. 27 can only be solved by numerical However, the problem may be simplified greatly by assuming that the diffusion term is independent of the electric field, D ( 8 )= D. Using this approximation, the solution to Eq. 27 is given by (This solution may be verified by differentiation.) Note that, when 8= gr or gd,one has n = no(Fig. 5c) and the left side of Eq. 28 vanishes; therefore, the integral on the right side of the equation must vanish when 8= gd.However, the integration from 8to 8 d can represent either the integration 10.2 TRANSFERRED-ELECTRON DEVICE 521 over the depletion region when n < noor the integration over the accumulation region where n > no.Since the first term in the integral is independent of n, whereas the contribution from the second term is different in the two cases, one must have u, = u d , so that the integral vanishes for both integration over the depletion region and over the accumulation region. Then for 8= g d , Eq. 28 reduces to This equation is satisfied by requiring that the two shaded regions in Fig. 6 have equal areas. By using this rule, the equal-area rule,25the value of the peak domain field g d can be determined if the value of the outside field g,is known. The dashed curve in Fig. 6 is a plot of gdOamgainst u, as determined by the equal-area rule. As a function of bias (or go)i,t begins at the peak of the velocity-field characteristic at the threshold field g PFor outside field (Z?,) values resulting in low-field velocities u( 27,)less than the saturation velocity u,, the equal-area rule can no longer be satisfied and stable domain propagation cannot be supported. If the field dependence of the diffusion factor in Eq. 27 is included in the equation, one must use numerical techniques to obtain solutions. These solutions show that for a given value of outside field 8,there is at most one value of domain excess velocity, defined as ( u d - u,), for which solutions exist. In other words, only one stable dipole domain configuration exists for each value of g r . Now consider some characteristics of a high-field domain. When the domain is not in contact with either electrode, the device terminal current is determined by the outside field g,and is given as JO = qfiou(g:,). (30) Therefore, for a given carrier concentration no,the outside field fixes the value of J. It is convenient to define the excess voltage on the high-field domain, with outside field 8,,by J-m The computer solutions of Eq. 3 1 for different values of carrier concentration and outside field are shown in Fig. 7. These curves may be used to determine the outside Fig. 6 Velocity vs. field showing the equal-area rule for domain formation. Dashed curve is the locus of u, vs. g d for different domain formation as the bias is varied. 522 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES Field outside domain Zr (kV/cm) Fig. 7 Excess voltage vs. field for various carrier concentrations. The dashed line is the device line. (After Ref. 27.) field gr in a particular diode of length L , doping concentration no,and bias voltage K by noting that the following relation must hold simultaneously with Eq. 3 1: vex= v-L g r . (32) The straight line defined by this equation is called the device line and is shown in Fig. 7 as a dashed line for the particular values L = 25 pm and V= 10 V. If VIL> g T , the threshold field, the intercept of the device line, and the solutions of Eq. 3 1 uniquely determine g r ,which in turn specifies the current. The slope of the device line is fixed by L; however, the intercept defining gr may be varied by adjusting the bias voltage K Figure 8 shows a plot of the domain width versus domain excess voltage.27Note that for a given V,,the domain is narrower for higher doping concentrations. In the limit of zero diffusion, the domain has a triangular shape because when 8 in Eq. 28 lies between 8,a.nd gd, the right side of the equation approaches infinity as D approaches zero; therefore, the left-hand side must also approach infinity. This requirement implies that n + 0 in the depletion region and n -+00 in the accumula- tion region. The electric field will vary linearly from gdto grand the domain width is & d = L(gd-gr). (33) 4no The domain excess voltage is then given by 10.2 TRANSFERRED-ELECTRONDEVICE 523 60 50 -$ 20 .aa- 10 0 10 20 30 40 Excess voltage V,(V) Fig. 8 Domain width vs. domain 50 excess voltage for various doping levels. (After Ref. 27.) Experimentally, only triangular domains have been obtained in GaAs and InP TEDs. When the high-field domain reaches the anode, the current in the external circuit increases and the fields in the diode readjust themselves, nucleating a new domain. Then the frequency of the current oscillations depends on, among other things, the velocity of the domain across the sample, vd;if v, increases, the frequency increases, and vice versa. The dependence of vd on the bias voltage can easily be determined. When the dipole reaches the anode, the field throughout the sample jumps to a higher value above the threshold field and a new domain is nucleated at the cathode. Figure 9 demonstrates a simulated time-dependent behavior of a domain in a GaAs 0 Distance Fig. 9 Numerical simulation of the time-dependent behavior of domain formation and transit. The sample length is 100 pm with doping of 5 x l O I 4 ~ m - E~a.ch successive instant of time is 24 ps. (After Ref. 28.) l. 524 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES device 100-pm long having a doping of 5 ~ 1 0~' ~m (n-& ~= 5 ~ 1 0c'm~-2). The time between successive vertical displays of 8(x,t) is 16z,, where ,z is the low-field dielectric relaxation time, Eq. 20 (z, = 1.5 ps for this device). It is seen here that at any time, only one domain can exist. The terminal current waveform is shown in Fig. 5d. At t,, the domain reaches the anode. The current pulse then reaches a peak value given by Jp = qnoup. (35) The period of the current pulses is given by the domain transit time (L/ud).This current oscillation is the first transferred-electron effect observed by Gunn.' 10.2.3 Modes of Operation Since Gunn first observed microwave oscillation in GaAs and InP TEDs in 1963, various modes of operation have been studied. A TED possesses the properties of negative differential resistance based on its I- V characteristics, so the operation can utilize these properties in the same ways as other NDR devices. The additional feature of Gunn current oscillation association with domains can also be used whose frequency is related to the domain transit time. Five major factors affect or determine the modes of operation: (1) doping concentration and doping uniformity in the device, ( 2 ) length ofthe active region, (3) cathode contact property, (4) operating voltage, and (5) type of circuit connected. Different modes of operation will be discussed next. Ideal Uniform-Field Mode. Under the idealized condition that no internal space charge (domain) has built up and the entire device has a uniform electric field, the current-voltage relationship for a TED can be obtained by scaling the velocity-field characteristics. In this mode of operation, the TED is used as a regular NDR device. Since the operation is not related to the domains, the operating frequency is not restricted to the domain transit time. We consider the simplest voltage waveform of a square wave, as shown in Fig. 10. We shall define two normalization parameters: PE a =IdIT and VOWTF.rom the nature of the waveform assumed, the average dc current I, is given by The dc power supplied by the device is and the total RF power available to the load is Therefore, the conversion efficiency from dc to RF is 10.2 TRANSFERRED-ELECTRON DEVICE 525 IC I I . Time V I I Fig. 10 Idealized square waveforms for the uniform-field mode. V, and I, are mid-points of ac components. (After Ref. 29.) From Eq. 39, we find that maximum efficiency is obtained with a dc bias voltage as high as possible + a)and with a current peak-to-valley ratio l l a as large as pos- sible. The maximum efficiency yields an ideal value of 30% for GaAs ( l / a= 2.2) and 45% for InP ( l / a= 3.5). These efficiencies should be independent of operating frequency as long as the frequency is lower than the reciprocal of the energy relaxation time and the intervalley scattering time. Experimentally, such high efficiencies have never been obtained and the fre- quency of operation is generally related to the transit-time frequency,f= ud/L. The reasons are: (1) the bias voltage is limited by avalanche breakdown; ( 2 ) a spacecharge layer usually forms, giving rise to a nonuniform field, and (3) the ideal current and voltage waveforms are difficult to achieve in a resonant circuit. Transit-Time Dipole-Layer Mode. When the n& product is greater than lo1*cm-2, the space-charge perturbations in the material increase exponentially in space and time to form mature dipole layers that propagate to the anode. The dipole is usually formed near the cathode contact, since the largest doping fluctuation and spacecharge perturbation exists there. The cyclic formation and subsequent disappearance at the anode of the fully developed dipole layers are what give rise to the experimentally observed Gunn oscillations. When a TED with overcritical n& product is connected in a parallel resonant circuit, such as a high+ microwave cavity, the transit-time dipole-layer mode can be obtained. In this mode, the high-field domain is nucleated at the cathode and travels the full length of the sample to the anode. Each time a domain is absorbed at the anode, the current in the external circuit increases; therefore, for samples in which the width of the domain is considerably smaller than the length of the sample, the current waveform tends to be spiky rather than the desired sinusoidal form. To obtain a more 526 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES sinusoidal current waveform, one may either minimize the length of the sample (which increases the frequency in this mode) or increase the width of the domain. Figure 8 shows that the domain width increases with decreasing doping level no. In general, more-sinusoidal waveforms may be obtained by decreasing the n& product, as long as it exceeds the critical value. Figure 11 shows a sequence of field distributions across a 35-pm sample during one RF cycle, together with the current waveform.30The n& product is 2 . 1 ~ 1 0c'm~ -2 and the current waveform is very close to sinusoidal for this device. Theoretical studies show that the efficiency of the transittime mode is greatest when the n& product is one to several times l o i 2cm-2, so that the domain fills about half the sample length and the current waveform is almost a sine wave. The maximum dc-to-RF conversion efficiency for this mode is 10%. The efficiency can be improved if the current waveform is close to a square wave. This waveform can be produced by adjusting the voltage to be below the threshold at the instant the dipole disappears at the anode. The formation of a new dipole is delayed until the voltage rises above threshold. However, for this delayed domain mode, the tuning procedure is extremely complicated. Quenched Dipole-Layer Mode. A TED in a resonant circuit can operate at frequencies higher than the transit-time frequency if the high-field dipole layer is quenched before it reaches the anode. In the transit-time dipole-layer mode of operation, most of the voltage across the device is dropped across the high-field dipole layer itself. 2---l L C 1Olo 10 20 I 30 Distance (pm) (a) I 1Olo 10 20 30 0 200 400 600 800 Distance (pm) Time (ps) (c) (d) Fig. 11 Transit-time dipole-layer mode with design for efficiency. Note the large relative domain width and near-sinusoidal current waveform. The GaAs sample has n,L = 2.1x 10l2cm-2 andfL = 0 . 9 l~o7cm/s. (After Ref. 30.) 10.2 TRANSFERRED-ELECTRON DEVICE 527 Therefore, as the resonant circuit reduces the bias voltage, the width of the dipole layer is reduced (Fig. 8). The dipole-layer width continues to decrease as the bias voltage decreases until at some point the accumulation layer and the depletion layer neutralize each other. The bias voltage at which this occurs is designated V,. Dipolelayer quenching occurs when the bias voltage across the device is reduced below V,. When the bias voltage swings back above threshold, a new dipole layer is nucleated, and the process repeats. Therefore, the oscillations occur at the frequency of the resonant circuit rather than the transit-time frequency. Figure 12 shows an example of the quenched dipole-layer mode.28The device has identical length and doping as that of Fig. 9. The dipole layer is quenched at a distance of about L/3 from the cathode, and the operating frequency is about three times higher than the transit-time dipole-layer mode shown in Fig. 9. The upper frequency limit for this mode is determined by the speed of quenching, which in turn is determined by two time constants. The first is the positive dielectric relaxation time and the second is an RC time constant; R being the positive resistance in those regions of the diode not occupied by dipoles and C the capacitance of all the dipoles in series. The first condition gives a minimum critical nolfratio of about lo4 s - ~ m f-o~r n-type GaAs and InP.31,32The second time constant depends on the number of dipoles and sample length. The efficiency of quenched dipole-layer oscillators can theoretically reach 13%.33 In the quenched dipole-layer mode of operation, it has been found both t h e ~ r e t i c a l l yan~d~e~perimentallyth~a~t for samples in which the resonant frequency of the circuit is several times the transit-time frequency (i.e.,fL > 2x107 c d s ) , and the frequency of operation is of the order of the dielectric relaxation frequency (i.e., now= &,/qlpdla, s given in Eq. 40), multiple high-field dipole layers usually form. This is due to that one dipole does not have enough time to readjust and absorb the voltage of the other dipoles. 0 Distance Fig. 12 Numerical simulation of TED in quenched dipole-layer L mode. (After Ref. 28.) 528 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES Accumulation-Layer Mode. The main difference of the accumulation-layer mode from the dipolar-layer mode is that in a lightly doped or short sample (n& < 10l2cm-2), it exhibits only accumulation of electrons without a depleted region of positive charge. The consequence is that the field profile becomes a step function around the charge packet, as opposed to the peak shown in Fig. 5c. When a uniform field is applied to such a device, the accumulation-layer dynamics can be understood in a simplified manner, as shown in Fig. 13. At time t,, an accumulation layer (i.e., excess electrons) is injected from the cathode so that the field distribution splits into two parts, as illustrated at time t2. The velocities on both sides of the accumulation layer have been altered in the direction shown in Fig. 13a. Since the terminal voltage is assumed to be constant, the area under each electric-field curve of Fig. 13c should be equal. As the accumulation layer propagates toward the anode, this p 3 Behind space charge , Preceding space charge -.- '4 I '4 ~ I I ;at hode F Anode Cathode Anode x Fig. 13 Accumulation-layer transit mode under time-invariant terminal voltage. (After Ref. 35.) 10.2 TRANSFERRED-ELECTRON DEVICE 529 equality can only be maintained if the velocities on both sides of the accumulation layer fall, as dictated by the velocity-field curve and indicated at times t,, t4, and t,. Eventually, the accumulation layer reaches the anode at time t6, and disappears there. The field near the cathode rises through the threshold, another accumulation layer is injected, and the process repeats. The smooth current waveform is shown in Fig. 13d. In this particular example, the accumulation charge continues to grow throughout the device length. A TED with subcritical n& product (i.e., n& < 10l2cm-2) can exhibit negative resistance in a band of frequencies near the electron transit-time frequency and its harmonics. It can be operated as a stable arn~lifier.W,~hen it is connected to a parallel resonant circuit with a load resistor of the order of lOR,, where R, is the low-field resistance of the TED, it will oscillate in the transit-time accumulation-layer mode. Figure 14 shows the electric field versus distance at three different times during one RF cycle.,O Also shown is the terminal current waveform. The voltage is always above the threshold value ( V > V ,= Z?,L). These waveforms are far from ideal; the eficiency for this particular waveform is only 5%. More favorable waveforms with about 10% eficiency can be obtained if the TED is connected to a series resistor and inductor. In this example, the space charge ceases to grow as it drifts to the anode. Limited-Space-Charge Accumulation (LSA) Mode. In the model of the LSA mode of ~ p e r a t i o n , ~th'e electric field across the device rises from below the 105~ - n vE 1 0- 3 ~ v - h- - t = tl 105t n - m -- t = t2 Distance (pm) Time (ps) (c) (4 Fig. 14 (a)-(c) Electric field vs. distance at three intervals of time during one RF cycle in accumulation-layer mode. (d) Terminal-current waveform in a resonant circuit for GaAs TED with no= 2x1OI4 ~ r n - ~ , f l1=. 4 ~ 1 0cm~/s, and ndf= 5 x lo4 s - ~ r n -(~A. fter Ref. 30.) 530 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES threshold and falls back again so quickly that it is assumed the space-charge distribution associated with high-field dipole layers does not have sufficient time to form. Only the primary accumulation layer forms near the cathode; and the rest of the device remains fairly homogeneous, provided that doping fluctuations are sufficiently small to prevent the formation of dipole layers. Under these conditions, a large portion of the device exhibits a uniform field, which yields efficient power generation at the circuit-controlled frequency. The higher the frequency, the shorter the distance the space-charge layer travels, leaving most of the device biased in the negativemobility range. The conditions for this mode of operation are derived from two requirements: the space charge should not have enough time to grow to an appre- ciable size and the accumulation layer must be quenched completely during one RF cycle. Thus, the negative ,z, Eq. 20, should be larger than the RF period whereas the positive ,z should be smaller. These requirements lead to the condition3* where pd+is the positive differential mobility at low field, and pd- an average negative differential mobility above the threshold field. For GaAs and InP the two limiting ratios are 104 < n-0 < 105 s - ~ m - ~ . f It is interesting to note that the quenched multiple dipole-layer mode also occurs in some range of no/fratios if doping fluctuations are present. The LSA device is suited for generating short pulses of high-peak power because devices with overlengths (nontransit-time mode) can be used for which heat extraction becomes difficult. However, the maximum operating frequency of LSA devices is much lower than that of transit-time devices. This lower frequency is caused by the slow energy relaxation of electrons in the lower valley, leading to increased quenching times. Computer simulations indicate that a minimum time of about 20 ps is required to stay below the threshold voltage for cyclic operation in GaAs; the corresponding upper-frequency limit is about 20 G H z . ~ ~FJo*r InP a higher upper frequency is expected. 10.2.4 Device Performances Cathode Contacts. The TEDs require extremely pure and uniform materials with a minimum of deep donor levels and traps, especially if quenching of space charge is involved in the operation. The first TEDs were fabricated from bulk GaAs and InP with alloyed ohmic contacts. Modern TEDs almost always use epitaxial layers on n+-substratesdeposited by advanced epitaxy techniques such as molecular-beam epitaxy. Typical donor concentrations range from 1014to 10I6~ m - a~nd, typical device lengths range from a few microns to several hundred microns. The TED chips are mounted in microwave packages. These packages, as well as related heat sinks, are similar to those for IMPATT diodes. 10.2 TRANSFERRED-ELECTRON DEVICE 531 To improve device performance, injection-limited cathode contacts have been used instead of the n+-ohmic contacts.3941By using an injecting-limited contact, the threshold field for the cathode current can be adjusted to a value approximately equal to the threshold field ET for the onset of NDR. Thus a uniform electric field can result. For ohmic contacts, the accumulation or dipole layer grows within some distance from the cathode due to finite heating time of the lower-valley electrons. This dead zone may be as large as 1 pm, which imposes a constraint on the minimum device length and hence on the maximum operating frequency. In an injecting-limited contact, hot electrons are injected from the cathode, reducing the length of the dead zone. Because the transit-time effect can be minimized, the device can exhibit a fiequency-independent negative conductance shunted by its parallel-plate capacitance. If an inductance and a sufficiently large conductance are connected to this device, it can be expected to oscillate in a uniform-field mode at the resonant frequency. The theoretical efficiency can then be derived as in Section 10.2.3. Two classes of injecting-limited contacts have been studied; one is a Schottky barrier with low barrier height, the other is a two-zone cathode structure. Figure 15 compares these contacts with an ohmic contact. For an ohmic contact (Fig. 15a)there is always a low-field region near the cathode, and the field is nonuniform across the device length. For a Schottky barrier under reverse bias, a reasonably uniform field can be obtained (Fig. 15b).42The reverse current is given by (see Chapter 3) JR = A"Pexp(-) -9 4 B kT n+ Cathode n+ Metal Anode Cathode n+ Metal f n+ Anode Cathode n+ Anode Fig. 15 Three cathode contact schemes: (a) ohmic contact, (b) Schottky-barrier contact, and (c) two-zone Schottky-barrier contact. 532 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES where A**is the effective Richardson constant and qjBis the barrier height. For current densities in the range lo2to lo4 A/cm2,the corresponding barrier height is about 0.15 to 0.3 eV. A Schottky barrier with a low barrier height is not simple to realize in 111-V semiconductors and it suffers from a rather limited temperature range because the injected current varies exponentially with temperature (Eq. 42). The two-zone cathode contact consists of a high-field zone and an n+-zone (Fig. 1 5 ~ )T.h~is ~configuration is similar to that of a lo-hi-lo IMPATT diode (see Chapter 9). Electrons are heated in the high-field zone and subsequently injected into the active region having a uniform field. This structure has been successhlly used over a wide temperature range. Power-Frequency Performance and Noise. The transfer of energy from the field to electrons and the scattering of electrons between lower and upper valleys take finite times. These finite times lead to an upper frequency limit corresponding to the scattering and energy relaxation frequencies. Figure 16 shows the time responses of the lower-valley and upper-valley velocities, the upper-valley population fraction, and the average velocity when the electric field is suddenly lowered from 6 kV/cm to Fig. 16 Response of electrons in upper valley (u2,n2)and lower valley (u,, n l )to an electric field stepped from 6 to 5 kV/cm. (After Ref. 44.) 10.2 TRANSFERRED-ELECTRON DEVICE 533 5 kV/cm. Note that the velocity v2of the upper valley follows almost instantaneously with the field. However, the velocity v1of the lower valley has a slow response with a time constant of about 2 ps. This response indicates the weak scattering of hot electrons in the lower valley. In addition, the slow decay of n2 corresponds to the slow scattering from the upper valley to the lower valley. The response of the average velocity u is thus due partly to the recovery of u1and partly to the intervalley transfer. Because of the finite response times, the TED has an estimated upper-frequency limit around 500 GHz. Under transit-time conditions, the frequency of operation is inversely proportional to the device length, that is,f = v/L.The power-frequency relationship is given by cf where and z?$ are the RF voltage and the corresponding field, respectively and R, is the load impedance. Therefore, the output power is expected to fall as llf'. The state-of-the-art microwave power versus frequency is shown in Fig. 17 for cw GaAs and InP TEDs. The numbers near the data points indicate conversion efficiencies. A""" I- :", 0.11301 , I , , 100 ;<0.09 I L0 Frequency (GHz) Fig. 17 Output microwave power vs. frequency for cw-operated GaAs and InP TEDs. Numbers next to symbols denote dc-to-RF conversion efficiencies in percentage. (After Ref. 45.) 534 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES Note that the power generally varies as l/P, as given by Eq. 43. The superior performance of InP is apparent, especially for higher frequencies. Generally the cw power is lower than that of an IMPATT diode. On the other hand, the applied voltage for TEDs at a given frequency can be considerably lower than that in an IMPATT diode (by a factor of about 2 to 5) and TEDs have better noise performance. The TEDs have two types of noise: amplitude deviations (AM noise) and frequency deviations (FM noise), both caused by thermal velocity fluctuations of the electrons. The AM noise is generally small because the amplitude is relatively stable, owing to the strong nonlinearity of the velocity-field characteristic. The FM noise has a mean-frequency deviation given bf6 wheref, is the carrier frequency, Q, the external quality factor, Po the power output, and B the measured bandwidth. The modulation-frequency-dependent equivalent noise temperature Teqis given by where the average negative differential mobility pd- depends on the voltage swing. Since the ratio D/lpd-l is smaller in InP than in GaAs, the noise is expected to be lower in InP. Functional Devices. Thus far we have considered the transferred-electron effect and its application to microwave oscillators and amplifiers. TEDs can also be used for high-speed digital and analog operations. We shall consider a TED with nonuniform cross-sectional area or/and nonuniform doping profile, and a three-terminal TED. The theory of high-field domains in one dimension can be used to analyze nonuniformly shaped oscillators, if one assumes very thin high-field domains and considers phenomena in practically uniform regions in their neighborhood. These assumptions are valid if n& >> 10l2cm-2 and the variations of the cross-sectional area and doping are gradual. Using the theory presented in the preceding section, it can be shown that there exists a value of domain excess voltage V,above which the outside electric field 8,r.emains constant with time. The value of the average velocity outside the domain correspondingto 8,is u,, as shown in Fig. 5a. Such saturated domains move in the oscillator with a constant velocity u, . The current density associated with a mature domain is given by Eq. 30. For TEDs with nonuniform doping density N(x) and cross-sectional area A(x), however, Eq. 30 can be generalized to ' ( t ) = qN(x)A(x)~(8,) (46) where x is measured from the cathode and x = u, t. If a high-field domain is nucleated from the cathode at time t = 0, then at time t the domain is at x(t) = u, t using the foregoing assumptions. Figure 18 shows the waveform of a bulk-effect oscillator for a sample of nonuniform shape shown.47The experimental current waveform is indeed similar to the Domain 10.2 TRANSFERRED-ELECTRON DEVICE 535 1 I 0 I 5 I 10 I 15 1 20 I 25 * Time (ns) (b) Fig. 18 (a) A TED with nonuniform cross-section and (b) its current waveform. Labels in (b) correspond to the location of domain at the specific time. (After Ref. 47.) shape of the sample, apart from the known current spikes when the domains reach the anode. The time scale is marked with letters A, B, B', and C which correspond to the instants of time when the domain is located at these points. The phenomenon that terminal-current waveform follows that of Eq. 46 can be explained qualitatively as follows. Since the current of the device must be constant at all location, when the domain enters a region of lower doping or smaller cross section, the field of the domain becomes larger in order to maintain similar velocity. A higher domain field (or excess voltage V,)means the field outside the domain E,. is lowered. As a consequence, the terminal current is lowered since the field outside the domain determines the current. Until now, only two-terminal devices have been considered. The current waveform of a TED may be controlled by adding one or more electrodes along the length of the device. Figure 19a shows the structure of such a device with the electrode located at point B. The expected current waveform is shown in Fig. 19b. This waveform can be explained as follows. (The saturated domain theory described previously is used here again.) When the domain leaves the cathode at time t = 0, the cathode t B C t (4 (b) Fig. 19 (a) Circuit of TED controlled-current step generator, and (b) its cathode current waveform. In (b), letters in time scale indicate location of domain. (After Ref. 47.) 536 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES current Z,(t) is equal to the current of the saturated domain (Aqnou,), and remains at this value until the domain reaches the electrode at B. At that time the cathode current becomes the sum of the saturated domain current and Zg, the current flowing through the resistor. The current Zgis equal to the voltage sustained by the sample between B and C with a domain present, divided by the resistor value. The cathode current then remains at ZJt) = Aqn,u,+Zg (47) until the domain is absorbed at the anode, at which time the current spikes briefly. 10.3 REAL-SPACE-TRANSFER DEVICES 10.3.1 Real-Space-Transfer Diode The concept of the real-space-transfer (RST) diode to obtain negative differential resistance (NDR) was conceived by G r i b n i k o ~in~1~972 and by Hess et al. in 1979.49 The first experimental evidence of the negative resistance from a RST diode was shown by Keever et al. in 1981.50 The requirement of a real-space-transfer diode is a heterostructure whose two materials have different mobilities. In addition, for an n-channel device, the material having lower mobility must also have a higher conduction-band edge E,. A good example is the GaAsJAlGaAs heterostructure. The real-space-transfer effect51is similar to the transferred-electron effect and it is sometimes difficult to separate them experimentally. The transferred-electron effect is due to the properties of a single, homogeneous material. When carriers are excited by a high applied field to a satellite band in the energy-momentum space, the mobility is lower and the current is reduced, resulting in NDR. In real-space transfer, transfer of carriers is between two materials (in real space) rather than two energy bands (in momentum space). In low fields, electrons (in an n-channel device) are confined to material (GaAs) with low E, and higher mobility. The energy-band diagram under high field is shown in Fig. 20. Carriers in the GaAs channel acquire enough energy from the field to overcome the conduction-band discontinuity and flow to the adjacent material (AlGaAs) of lower mobility. This carrier transfer can be considered as thermionic emission, with the electron temperature replacing the lattice temperature. Thus, a higher field results in a smaller current, the definition of NDR. Experimental I- V characteristics are shown in Fig. 2 1. The critical field for this real-space transfer has been shown to be between 2 and 3 kVJcm, while that for the transferredelectron effect is typically 3.5 kV/cm for GaAs. One has to bear in mind that these critical fields are obtained from two different types of channels (heterointerface vs. bulk) and cannot be used alone to separate the effects. Another property of real-space transfer is that there is better control with factors such as conduction-band discontinuity, mobility ratio, and film thicknesses, so that device characteristics can be varied and optimized. The RST effect produces I- Vcharacteristics very similar to that of the transferred-electron effect. To achieve an efficient RST diode, a proper choice of heterojunction with optimum band-edge discontinuity, together with a high satellite GaAs Energy xA 10.3 REAL-SPACE-TRANSFER DEVICES 537 Fig. 20 Energy-band diagram showing the conduction-band edge E, of the RST diode under bias. Electrons in the main GaAs channel acquire energy from the field to overcome the barrier to spill over to the AlGaAs layer. valley to avoid the transferred-electron effect (or the absence of a satellite valley), are desirable. The modeling of the RST diode is complicated, and there are no simple equations derived explicitly for the exact I- V characteristics. Qualitatively, the following expressions can be used to get some insight into the origin of the negative resistance. Assume that the total carrier density per unit area is N,, distributed between the GaAs channel layer of thickness L , (n,,)and AlGaAs layer L, (ns2): n,, + ns2 = N , . (48) This also implies that carriers can move between the two layers easily, other than having to overcome the barrier AEc when going from the GaAs channel of lower energy to that of higher-energy AlGaAs. The ratio of the carrier densities of the two 300°K KCA 0 2 Field (4kV/cm) 6 8 Fig. 21 Current-voltage (or -field) characteristics of a RST diode, based on GaAdAlGaAs heterostructure. (After Ref. 50.) 538 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES layers is related by the energy of the hot carriers, measured by the electron tempera- ture T, in relation to the barrier A E ~ 2= 312 -AEc exp(K). (49) ns 1 The electron temperature is related to the field by where z, is the energy relaxation time and Tothe lattice (room) temperature. The fraction of carriers excited to the AlGaAs layer is defined as F ( 8 ) = -ns2 NS and is a function of the applied field. It starts at zero at low field and approaches the ratio of L2/(L1+ L2)at high fields. The total drift current is given by J = 4nslPlE +APS2P28 = 4 g N s [ P l - (PI - P2)FI ' The differential resistance is given by dJ (53) and it can be shown to be negative for a proper choice of p,, ,L+, F, and dFld8. In the GaAsIAlGaAs modulation-doped system, pl = 8,000 cm2fV-s and p2 is less than 500 cm2N-s at room temperature. Experimental data show that the current peak-tovalley ratio is not very high, with a maximum value around 1.5. Computer simulations show that a ratio of more than 2 can be achieved. One of the advantages of the RST diode is high-speed operation. The response time is limited by the movement of carriers across the heterointerface between the two materials, and is much faster than in a traditional diode where the transit time of carriers between the cathode and anode is the dominating factor. 10.3.2 Real-Space-Transfer Transistor The real-space-transfer (RST) transistor is a three-terminal version of a RST diode. In an RST transistor, the third terminal contacts the material of higher conduction band to extract the emitted hot carriers and also to control the transverse field for efficient carrier transfer. The RST transistor was proposed as a negative-resistancejieldeffect transistor (NERFET) by Kastalsky and Luryi in 1983,52and was subsequently realized in a GaAs/AlGaAs modulation-doped heterostructure by Kastalsky et al. in 1984.53 Typical structure of an RST transistor is shown in Fig. 22, which also indicates the carrier movement and the energy band perpendicular to the heterojunction. As seen, the hot carriers emitted over the barrier are collected by the third terminal and con- 10.3 REAL-SPACE-TRANSFER DEVICES 539 pxI,fi . . . i-AIGaAs Semi-Insulating GaAs I Fig. 22 (a) Schematic structure of a real-space-transfer transistor and (b) its energy-band diagram perpendicularto the channel. tribute to another terminal current. For this reason, this third terminal has been called the collector. So unlike the RST diode, the mobility in the barrier layer is not relevant. The channel current now decreases because the total carrier density is reduced. This decrease of current is due to density modulation, rather than mobility modulation as in the RST diode. The current at the source is similar to the channel current of an FET such as a MOSFET or MODFET. The collector is analogous to the gate, which can modulate the channel carrier density and current, with the additional function of depleting the channel hot carriers after they are emitted over the barrier. In this respect, the drop of the channel current results from the increase of collector current. The sum of the drain current and the collector current is thus the same as the total channel current of an insulated-gate FET. The I-Vcharacteristics for an RST transistor are shown in Fig. 23. At low VD,the source-drain current is a standard FET current. The collector current is low and its terminal modulates the channel current as an insulated gate. At higher V,, carriers start to become more and more energetic and begin to spill over the collector barrier. The h 0 1 2 3 4 Drain bias V, (V) Drain bias V, (V) (b) Fig. 23 Terminal currents of a real-space-transfer transistor. (a) Drain current and (b) collector current vs. drain bias. (After Ref. 54.) 540 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES collector current is a hot-electron current and it increases with the longitudinal field, or VD.This current usually occurs in the saturation region in which the field is nonuniform and has a higher local peak near the drain. Kirchhoffs current law requires that I, = ID+IC. (54) The drain current has to drop when ,Z rises, giving a negative differential resistance (NDR) dVddl,. The device is thus a variable NDR device whose characteristics are controlled by the collector terminal. A maximum peak-to-valley ratio of the drain current of more than 340,000 at room temperature has been observed.55 We now analyze qualitatively the collector current to gain some understanding of the RST transistor operation. The change of ID is related to the collector current by where W is the channel width dimension. The collector current is due to thermionic emission of hot electrons. A simple analysis is to assume that the hot carriers have a Maxwellian distribution with a mean electron temperature T, that is higher than the room or lattice temperature To.This thermionic-emission current is given by E:) ( Jc(x) = qvn(x)exp - - with electron velocity v = is. (57) AE, is the barrier height due to the conduction-band discontinuity shown in Fig. 22b. The electron temperature is related directly to the high local field near the drain, and it has been shown empirically to be proportional to the square of drain bias.56Since the drain current is a drift current, ZD(x) = wdn(x)qv, (58) where d is the channel thickness. Solving the differential equations of Eqs. 55, 56, and 58 shows that the electron concentration n(x), assuming a uniform field, decays exponentially from source to drain. The total collector current is the integral of Eq. 56 throughout the channel length L. A more rigorous derivation gives the following similar expression from the thermionic-emission theory:57 where A**is the effective Richardson constant (see Chapter 3) and V(x)is the channel potential. The increase of V, has the following effects on the device: (1) channel carriers are increased, (2) the field within AlGaAs for efficient collection of hot carriers is increased, and ( 3 ) Teis decreased due to a redistribution of a more uniform field in the 10.3 REAL-SPACE-TRANSFER DEVICES 541 channel. These effects have important and sometimes opposite impacts on the hotelectron current. Figure 23 shows three distinct regions according to different values of V,. At low V,, carriers do not have enough energy from the longitudinal field to surmount the barrier. The channel is modulated by the collector, and characteristics are similar to the linear region of an FET. The most interesting region is with medium V, corresponding to the saturation region of an FET. However, NDR can be observed only for high values of V,. At low V, the transverse field is not high enough for an efficient collection of the carriers within the AlGaAs layer. This is compounded by the space-charge effect, which further reduces the transverse field. The voltage built up by the space-charge effect in the barrier film is given by where I is the AlGaAs thickness. A quick estimate shows that AV can be as high as 2 V.j8 Another interesting feature in this regime is that both positive and negative transconductance (dZddV,) coexist. Positive transconductance is due to the increase of channel carriers and also the decrease of T, and I , with Vc Negative transconductance is due to the increase of transverse field and I , with Vc Finally, the third region is at high V,, where leakage starts between the drain and the collector. The intrinsic speed of a RST transistor is limited by two time constants, the energy relaxation time to establish T, and the time-of-flight within the high-field region near the drain. The latter is transit time over a very short distance, unlike in an FET, where the total distance is from source to drain. Both of these time constants are around 1 ps. Consequently, the RST transistor is proposed to be a very fast device with an ultimate speed, for a well-scaled device, around 100 GHz. A cutoff frequency higher than 70 GHz has been dem0n~trated.j~ It has been proposed to use the collector current as the main output current, as charge-injection transistor (CHINT), and the drain as the input.60There is no difference between a regular RST transistor and the CHINT in structure. Since the Z, is limited by a barrier, its operation is closer to that of a potential-effect transistor (like bipolar transistor) than to an FET. For this reason, the source and drain terminals are analogous to the emitter and base terminals respectively, of a bipolar transistor. The transistor current I , is determined by the electron temperature T, created by V,. Operation of a CHINT can be compared to a vacuum diode whose cathode filament is heated resistively by a current.60It can be shown that the transconductance (61) can be quite high. A maximum g, of N 1.1 S/mm has been obtained.j9 In the CHINT operation, the NDR is not important. A three-terminal RST transistor has the following advantages: (1) control of variable NDR, ( 2 ) high peak-to-valley current ratio, ( 3 ) high-speed operation (since emitted carriers are drained away and will not return to the main channel), (4) high 542 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES transconductanceg,, and (5) the potential of being a functional device (single device capable of performing functions). Velocity-ModulationTransistor. The velocity-modulation transistor (VMT) was proposed in 1982 as a ultrahigh-speed device.61It represents a new class of fieldeffect transistors in which the source-drain current is not modulated by the amount of carriers or charge induced by the gate (densitymodulation). Rather, the modulation of current is due to a change in carrier velocity (velocity modulation or mobility modulation), with the unique feature that the total number of carriers remains constant. This can be accomplished by the real-space transfer of channel carriers between two parallel adjacent channels of different mobilities. The main advantage of the velocitymodulation transistor is the intrinsic device speed. For a conventional FET, when a gate bias is applied abruptly to turn the transistor on, the charge induced by the gate comes from the source. By the same token, the off-state requires the charge to dissipate through the drain. The intrinsic speed of a standard FET is thus limited by the transit time between the source and the drain. In the VMT, the change of state is accomplished by transferring charges between two channels that can be much closer than the channel length between the source and drain. Computer simulations show that the response time can be as short as 0.2 ps. So the requirement for a short channel length for speed is removed. Unfortunately, the concept has not yet been demonstrated experimentally.To take full advantage of the VMT, the gate voltage has to be within a range such that the total charge in the channels is conserved. This is not trivial to demonstrate experimentally because similar output characteristics can be achieved by conventional FET action where higher gate voltage induces an extra channel charge. Independent measurements, such as Hall measurement, are required to confirm a VMT action. It should be pointed out that for short-channel devices, the carrier velocity approaches a saturation velocity at high fields. In this operation regime, the difference in mobility is less meaningful than the difference in the saturation velocity of the two channels. This difference in saturation velocity, in practice, is usually much less than that in mobility. This drawback limits the current drive of the device. REFERENCES 1. J. B. Gunn, “Microwave Oscillation of Current in 111-V Semiconductors,” Solid State Commun., 1, 88 (1963). 2. B. Gunn, “Instabilities of Current in 111-V Semiconductors,” ZBMJ. Res. Dev., 8, 141 (1964). 3. H. Kroemer, “Theory of the Gunn Effect,” Proc. IEEE, 52, 1736 (1964). 4. B. K. Ridley and T. B. Watkins, “The Possibility of Negative Resistance Effects in Semi- conductors,” Proc. Phys. SOC.Lond., 78,293 (1961). 5. B. K. Ridley, “Anatomy of the Transferred-Electron Effect in 111-V Semiconductors,” J. Appl. Phys., 48, 754 (1977). 6. C. Hilsum, “Transferred Electron Amplifiers and Oscillators,” Proc. IRE, 50, 185 (1962). REFERENCES 543 7. C. Hilsum, “Historical Background of Hot Electron Physics,” Solid-State Electron., 21, 5 (1978). 8. A. R. Hutson, A. Jayaraman, A. G. Chynoweth, A. S. Coriell, and W. L. Feldmann, “Mechanism of the Gunn Effect from a Pressure Experiment,” Phys. Rev. Lett., 14,639 (1965). 9. J. W. Allen, M. Shyam, Y. S. Chen, and G L. Pearson, “Microwave Oscillations in GaAs,,P, Alloys,” Appl. Phys. Lett., 7, 78 (1965). 10. J. E. Carroll, Hot Electron Microwave Generators, Edward Arnold, London, 1970. 1 1 . P. J. Bulman, G. S. Hobson, and B. S. Taylor, Transferred Electron Devices, Academic, New York, 1972. 12. B. G. Bosch and R. W. H. Engelmann, Gunn-EffectElectronics, Wiley, New York, 1975. 13. H. W. Thim, “Solid State Microwave Sources,” in C. Hilsum, Ed., Handbook on Semicon- ductors, Vol. 4, Device Physics, North-Holland, Amsterdam, 1980. 14. M. Shur, GaAs Devices and Circuits, Plenum, New York, 1987. 15. D. E. Aspnes, “GaAs Lower Conduction Band Minimum: Ordering and Properties;” Phys. Rev., 14,5331 (1976). 16. H. D. Rees and K. W. Gray, “Indium Phosphide: A Semiconductor for Microwave Devices,” SolidState Electron Devices, 1, 1 (1976). 17. D. E. McCumber and A. G. Chynoweth, “Theory of Negative Conductance Application and Gunn Instabilities in ‘Two-Valley’ Semiconductors,” IEEE Trans. Electron Dev., ED-13,4 (1966). 18. K. Sakai, T. Ikoma, and Y. Adachi, “Velocity-Field Characteristics of Ga,In,,Sb Calculated by the Monte Car10 Method,” Electron. Lett., 10,402 (1974). 19. R. E. Hayes and R. M. Raymond, “Observation of the Transferred-Electron Effect in GaInAsP,” Appl. Phys. Lett., 31, 300 (1977). 20. J. R. Hauser, T. H. Glisson, and M. A. Littlejohn, “Negative Resistance and Peak Velocity in the Central (000) Valley of 111-V Semiconductors,” Solid-State Electron., 22,’487 (1979). 21. J. G. Ruch and G. S. Kino, “Measurement of the Velocity-Field Characteristics of Gallium Arsenide,” Appl. Phys. Lett., 10,40 (1967). 22. P. N. Butcher and W. Fawcett, “Calculation of the Velocity-Field Characteristics for Gallium Arsenide,” Phys. Lett., 21,489 (1966). 23. M. A. Littlejohn, J. R. Hauser, and T. H. Glisson, “Velocity-Field Characteristics of GaAs with T-L-XConduction-Band Ordering,” J. Appl. Phys., 48,4587 (1977). 24. I. Mojzes, B. Podor, and I. Balogh, “On the Temperature Dependence of Peak Electron Velocity and Threshold Field Measured on GaAs Gunn Diodes,” Phys. Status Solidi, 39, K123 (1977). 25. P. N. Butcher, “Theory of Stable Domain Propagation in the G u m Effect,” Phys. Lett., 19, 546 (1965). 26. P. N. Butcher, W. Fawcett, and C. Hilsum, “A Simple Analysis of Stable Domain Propagation in the Gunn Effect,” BI:J. Appl. Phys., 17, 841 (1966). 27. J. A. Copeland, “Electrostatic Domains in Two-Valley Semiconductors,” IEEE Trans. Electron Dev., ED-13, 187 (1 966). 28. M. Shaw, H. L. Grubin, and P. R. Solomon, The Gunn-Hilsum Effect, Academic, New York, 1979. 544 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES 29. G S. Kino and I. Kuru, “High-Efficiency Operation of a Gunn Oscillator in the Domain Mode,” IEEE Trans. Electron Dev., ED-16,735 (1969). 30. H. W. Thim, “Computer Study of Bulk GaAs Devices with Random One-Dimensional Doping Fluctuations,” J.Appl. Phys., 39,3897 (1968). 31. J. A. Copeland, “A New Mode of Operation for Bulk Negative Resistance Oscillators,” Proc. IEEE, 54, 1479 (1966). 32. J. A. Copeland, “LSA Oscillator Diode Theory,”J. Appl. Phys., 38,3096 (1967). 33. M. R. Barber, “High Power Quenched Gunn Oscillators,” Proc. ZEEE, 56, 752 (1968). 34. H. W. Thim and M. R. Barber, “Observation of Multiple High-Field Domains in n-GaAs,” Proc. ZEEE, 56, 110 (1968). 35. G. S. Hobson, The Gunn Effect, Clarendon, Oxford, 1974. 36. H. W. Thim and W. Haydl, “Microwave Amplifier Circuit Consideration,” in M. J. Howes and D. V. Morgan, Eds., Microwave Devices, Wiley, New York, 1976, Chap. 6. 37. D. Jones and H. D. Rees, “Electron-Relaxation Effects in Transferred-Electron Devices Revealed by New Simulation Method,” Electron. Lett., 8, 363 (1972). 38. H. Kroemer, “Hot Electron Relaxation Effects in Devices,” Solid-State Electron., 21, 61 (1978). 39. H. Kroemer, “The Gunn Effect under Imperfect Cathode Boundary Condition,” IEEE Trans. Electron Dev., ED-15, 819 (1968). 40. M. M. Atalla and J. L. Moll, “Emitter Controlled Negative Resistance in GaAs,” Solid- State Electron., 12, 619 (1969). 41. S. P. Yu, W. Tantrapom, and J. D. Young, “Transit-Time Negative Conductance in GaAs Bulk-Effect Diodes,” ZEEE Trans. Electron Dev., ED-18, 88 (1971). 42. D. J. Colliver, L. D. Irving, J. E. Pattison, and H. D. Rees, “High-Efficiency InP Trans- ferred-Electron Oscillators,” Electron. Lett., 10, 221 (1974). 43. K. W. Gray, J. E. Pattison, J. E. Rees, B. A. Prew, R. C. Clarke, and L. D. Irving, “InP Microwave Oscillator with 2-Zone Cathodes,” Electron. Lett., 11,402 (1975). 44. H. D. Rees, “Time Response of the High-Field Electron Distribution Function in GaAs,” IBMJ. Rex Dev., 13,537 (1969). 45. H. Eisele and R. Kamoua, “Submillimeter-Wave InP Gunn Devices,” ZEEE Trans. Micro- wave Theory Tech.,52,2371 (2004). 46. A. Ataman and W. Harth, “Intrinsic FM Noise of Gunn Oscillators,” ZEEE Trans. Electron Dev., ED-20, 12 (1973). 47. M. Shoji, “Functional Bulk Semiconductor Oscillators,” IEEE Trans. Electron Dev., ED-14, 535 (1967). 48. Z. S. Gribnikov, “Negative Differential Conductivity in a Multilayer Heterostructure,” Soviet Phys.-Semiconductors, 6, 1204 (1973). Translated from Fizika i TeknikaPoluprovodnikov,6, 1380(1972). 49. K. Hess, H. Morkoc, H. Shichijo, and B. G Streetman, “Negative Differential Resistance Through Real-Space Electron Transfer,” Appl. Phys. Lett., 35,469 (1979). 50. M. Keever, H. Shichijo, K. Hess, S. Banerjee, L. Witkowski, H. Morkoc, and B. G. Streetman, “Measurements of Hot-Electron Conduction and Real-Space Transfer in GaAsAl,Ga,_& Heterojunction Layers,” Appl. Phys. Lett., 38, 36 (1981). PROBLEMS 545 51. Z. S. Gribnikov, K. Hess, and G. A. Kosinovsky, “Nonlocal and Nonlinear Transport in Semiconductors: Real-Space Transfer Effects,” J. Appl. Phys., 77, 1337 (1995). 52. A. Kastalsky and S. Luryi, “Novel Real-Space Hot-Electron Transfer Devices,” ZEEE Electron Dev. Lett., EDL-4, 334 (1983). 53. A. Kastalsky, S. Luryi, A. C. Gossard, and R. Hendel, “A Field-Effect Transistor with a Negative Differential Resistance,” ZEEE Electron Dev. Lett., EDL-5, 57 (1984). 54. P. M. Mensz, S. Luryi, A. Y.Cho, D. L. Sivco, and F. Ren, “Real-Space Transfer in ThreeTerminal InGaAs/InAlAs/InGaAs Heterostructure Devices,” Appl. Phys. Lett., 56, 2563 (1 990). 55. C. L. Wu, W. C. Hsu, H. M. Shieh, and M. S. Tsai, “A Novel &Doped GaAdInGaAs RealSpace Transfer Transistor with High Peak-to-Valley Ratio and High Current Driving Capability,” IEEE Electron Dev. Lett., EDL-16, 112 (1995). 56. S. Luryi, “Hot-Electron transistors,” in S. M. Sze, Ed., High-speed Semiconductor Devices, Wiley, New York, 1990. 57. E. J. Martinez, M. S. Shur, and F. L. Schuermeyer, “Gate Current Model for the Hot-Electron Regime of Operation in Heterostructure Field Effect Transistors,” ZEEE Trans. Electron Dev., ED-45,2108 (1998). 58. S. Luryi and A. Kastalsky, “Hot Electron Injection Devices,” Superlattices and Microstructures, 1, 389 (1985). 59. G. L. Belenky, P. A. Garbinski, P. R. Smith, S. Luryi, A. Y. Cho, R. A. Hamm, and D. L. Sivco, “Microwave Performance of Top-Collector Charge Injection Transistors on InP Substrates,” Semicond.Sci. Technol.,9, 1215(1994). 60. S. Luryi, A. Kastalsky, A. C. Gossard, and R. H. Hendel, “Charge Injection Transistor Based on Real-Space Hot-Electron Transfer,” ZEEE Trans. Electron Dev., ED-31, 832 (1984). 61. H. Sakaki, “Velocity-Modulation Transistor (VMTFA New Field-Effect Transistor Concept,”Jpn. J. Appl. Phys., 21, L381 (1982). PROBLEMS 1. An InP TED is 0.5 pm long with a cross sectional area of 10“ cm2 and is operated in the transit-time mode. (a) Find the minimum electron density norequired for transit-time mode. (b) Find the time between current pulses. (c) Calculate the power dissipated in the device, if it is biased at one half the threshold. 2. For an InP TED operated in the transit-time dipole-layer mode, the device length is 20 pm, and the doping is no= lOI5~ m - I~ft.he current density is 3.2 kA/cm2when the dipole is not in contact with the electrodes, find the domain excess voltage, assuming triangular domain. 3. (a) Find the effective density of states in the upper valley N,,, of the GaAs conduction band. The upper-valley effective mass is 1.2mo. (b) The ratio of electron concentrations between the upper and lower valleys is given by (Nc,//~~L)exp(-AE/~Tw,)h,ere NcLis the effective density of states in the lower valley, AE = 0.31 eV is the energy difference, and T,is the effective electron temperature. Find the ratio at T, = 100 K. 546 CHAPTER 10. TRANSFERRED-ELECTRON AND REAL-SPACE-TRANSFER DEVICES (c) When electrons gain kinetic energies from the electric field, T, increases. Find the concentration ratio for T, = 1500K. 4. In a transferred-electron device, if a domain is suddenly quenched during transit so that the excess domain voltage is changed from V,, to zero in a time that is short compared to the transit time, the change in total current through the device during this time, integrated with respect to time, should give a measure of the charge stored in the domain, Q,. Relate this charge Q, to the domain excess voltage V,, for a triangle electric field distribution, i.e., the field increases linearly from gr to gdomover a distance xA for the accumulation layer and decreases linearly from gdOtm o grover a distance X, for the depletion layer (assuming that the charge in each layer is uniform). 5. Consider a simple model of RST that neglects the electric field associated with transferred electrons. Assume a periodic multilayer structure as shown with narrow-gap layers of thickness d, and wide-gap layers of thickness d2.The effective masses and mobilities in the layers are m, and m2,and p , and ,L+ respectively, with p , > h.Take the rate of energy loss to the lattice proportional to (T,- T)/z per electron, where z is the same for both layers. Further, assume that the effective electron temperature T, is the same for both layers, so that no energy is transferred on average as electrons jump between layers. The total density of electrons is fixed, n = n, + n2 is constant. (a) Derive the energy balance equation. (b) Express the ratio n , h 2 in terms of T, and the barrier height 4. (c) Derive the current-field characteristics in a parametric form 5F, = Z?( T,), J = J( T,) and plot J( g)for a few values of the parameters. What is necessary to achieve high -u-II-LT" ME" NDR in the source-drain current-field characteristic? 6. In a RST device, the collector current can be expressed as I, = Aexp(-dkT,), where A is a constant, q5 the barrier height, and T, the electron temperature. Assume (T,- T)/T=BV,m,, where T is the lattice temperate, B and m are constants, and VsDis the applied voltage between source and drain. (a) Show that cD (b) Show that when T, >> T, a plat offversus is a straight line. 7. A real-space-transfer device has hot-electron injection curves shown in Figs. 21 and 22 (pp. 439-440, High Speed Semiconductor Devices. Sze, Ed., Wiley, 1990). Estimate the barrier height 4 in eV for Vsub= 0.25 V and V,, = - 0.448 V. 8. A real-space-transfer transistor (Fig. 22) has an intrinsic layer (i-AlGaAs) of 0.1 pm in thickness. If the energy relaxation time is 1 ps, and the transit velocity of carriers across the i-region is lo7cm/s, estimate the cutoff frequency of the device. 9. For a CHINT logic shown, prepare a truth table and show that this a an exclusive NOR logic, i.e., the output voltage will be high only when both source and drain are at the same voltage level. PROBLEMS 547 10. A conventional CHINT has an n-type emitter channel and an n-type collector (2nd conducting layer). By replacing the n-type collector with a p-type collector, we can realize a novel light emitting device. We can construct such a device with the following lattice- matched layers: 1 pm p-type AlInAs ( 3 x lo1*~ m w-ith~Eg= 1.5 eV), 50 nm p-type GaInAs (1017),200 nm undoped AlInAs barrier, 50 nm n-type GaInAs (lo1’), and 2.5 nm AlInAs n-type (lOI9). Draw the band diagram of the structure from the top 2.5 nm AlInAs layer to the bottom 1 pm AlInAs layer at thermal equilibrium (AEc= 0.53 eV, AE,= 0.22 eV). Mark all bandgap energies and layer thicknesses on the diagram. Find the wave- length of the emitted light. Physics of Semiconductor Devices, 3rd Edition by S . M. Sze and Kwok K. Ng Copyright 0John Wiley & Sons, Inc. 11 Thyristors and Power Devices 11.1 INTRODUCTION 11.2 THYRISTOR CHARACTERISTICS 11.3 THYRISTOR VARIATIONS 11.4 OTHER POWER DEVICES 11.1 INTRODUCTION Power semiconductor devices can be generally grouped into two functions. The first as a switch is to control the power delivered to the load. In this case, only the two extreme states are critical. The on-state ideally should be a short whereas the off-state an open. The second fkction as a power amplij?eris to amplify an ac signal. For this function, the current gain (in a potential-effect transistor) or the transconductance (in a field-effect transistor) is important. For power applications, both types of devices are required to sustain high voltages and high currents. A good example for a switch is a thyristor which possesses S-type negative differential resistance. Because of the snap-back action and its associated nonlinear effects, the thyristor cannot be used as a power amplifier. On the other hand, a power transistor with smooth I- Vcharacteristics can also be used as a switch. Most devices discussed in this chapter are related to thyristors, and they function only as efficient switching devices. The only devices that can be used for both functions are insulated-gate bipolar transistor (IGBT) and staticinduction devices discussed near the end of the chapter. This chapter only covers power devices whose working principles are different from previous chapters. Power devices based on transistors such as MOSFET, JFET, MESFET, MODFET, bipolar transistor, etc., are commonly used in power applications. Their device principles, however, do not require additional treatment. The main differences for those devices in power applications mainly lie in their structures, which usually have larger dimensions, better heat sinks, and sometimes made on different semiconductor materials. 548 11.2 THYRISTOR CHARACTERISTICS 549 More-suitable semiconductor materials for power devices are compared in Table 1, which lists their most-important parameters. A high-bandgap material usually has low ionization coefficients, giving rise to low impact ionization and high breakdown voltage. Mobility and saturation velocity are for speed consideration. High thermal conductivity enhances heat conduction and increases the power level. Of the materials shown, S i c and GaN have the best combination. The only drawback is their immature technologies in that the materials are not very reliable or reproducible, and the cost is very high. 11.2 THYRISTOR CHARACTERISTICS The name thyristor applies to a general family of semiconductor devices that exhibit bistable characteristics and can be switched between a high-impedance, low-current off-state and a low-impedance, high-current on-state. Also, the operations of thyristors are intimately related to the bipolar-transistor action in which both electrons and holes interact with each other in the transport processes. The name thyristor is derived from vacuum tube gas thyratron, since the electrical characteristics are similar in many respects. Following Shockley's concept of the hook collector in 1950,' Ebers developed a two-transistor analogue to explain the characteristics of a basic thyristor, a multilayered p-n-p-n device.2 The detailed device principles and the first working two-terminal p-n-p-n devices were reported by Moll et al. in 1956.3 This work has since served as the basis in the study of thyristors. Subsequently, the control of switching using a third terminal was examined by Mackintosh? and by Aldrich and Holonyaks in 1958. Because of their two stable states (on and off>and low power dissipations in these states, thyristors have found unique usefulness in applications ranging from speed control in home appliances to switching and power conversion in high-voltage transmission lines. Thyristors are now available with current ratings from a few mA to over 5 kA and voltage ratings extending above 10 kV. Comprehensive treatments on the operation and fabrication technology of thyristor can be found in Refs. 6-10. Table 1 Comparison of Semiconductor Materials for Power Applications Property Bandgap (eV) Dielectric constant Breakdown field (V/cm) Saturation velocity ( c d s ) Peak velocity ( c d s ) Electron mobility (cm2/V-s) Thermal conductivity (W/cm-"C) * Modulation-doped channel. Si GaAs SiC(4H) 1.12 1.42 3.0 11.9 12.9 10 ~ 3 x 1 0 5 =4x105 =4X1O6 1x10' 0 . 7 ~ 1 0 ~ 2x107 1x107 2x107 2x107 1350 6000 800 1.5 0.46 4.9 GaN 3.4 10.4 ~4x10~ 1.5~10' >2~107 1000* 1.7 550 CHAPTER 11. THYRISTORS AND POWER DEVICES The basic thyristor structure is shown schematically in Fig. la. It is a four-layer p-n-p-n device having threep-n junctions, J1, J2, and 53, in series. Its typical doping profile is shown in Fig. lb. Note that the nl-layer (n-base) is much wider than other regions, and it has the lowest doping level for high breakdown voltage. The contact electrode to the outerp-layer is called the anode and that to the outer n-layer is called the cathode. The gate electrode, also referred to as the base, is connected to the inner p-layer (p-base). The three-terminal device is commonly called the semiconductorcontrolled rectifier (SCR) or simply the thyristor. Without the gate electrode, the device is operated as a two-terminalp-n-p-n switch, or Shockley diode. The basic current-voltage characteristics of a thyristor that have a number of complex regions are shown in Fig. 2. In region 0-1 the device is in the forward blocking or offtate with very high impedance. Forward breakover (or switching) occurs at dVAK/dI=A0, where