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Stellaris® LM3S8962_Microcontroller

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标签: LM3S8962

LM3S8962

LM3S8962开发板支持串口ISP下载程序,无需仿真器也可以进行快速开发(提供源程序) 。

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TEXAS INSTRUMENTSPRODUCTION DATA Stellaris LM3S8962 Microcontroller DATA SHEET DSLM3S89629102 Copyright 20072011 Texas Instruments Incorporated Copyright Copyright 20072011 Texas Instruments Incorporated All rights reserved Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others PRODUCTION DATA information is current as......

TEXAS INSTRUMENTS-PRODUCTION DATA Stellaris® LM3S8962 Microcontroller DATA SHEET DS-LM3S8962-9102 Copyright © 2007-2011 Texas Instruments Incorporated Copyright Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 Texas Instruments-Production Data January 09, 2011 Stellaris® LM3S8962 Microcontroller Table of Contents Revision History ............................................................................................................................. 26 About This Document .................................................................................................................... 32 Audience .............................................................................................................................................. 32 About This Manual ................................................................................................................................ 32 Related Documents ............................................................................................................................... 32 Documentation Conventions .................................................................................................................. 33 Architectural Overview .......................................................................................... 35 1 Product Features .......................................................................................................... 35 1.1 Target Applications ........................................................................................................ 44 1.2 High-Level Block Diagram ............................................................................................. 45 1.3 Functional Overview ...................................................................................................... 47 1.4 1.4.1 ARM Cortex™-M3 ......................................................................................................... 47 1.4.2 Motor Control Peripherals .............................................................................................. 48 Analog Peripherals ........................................................................................................ 49 1.4.3 Serial Communications Peripherals ................................................................................ 49 1.4.4 1.4.5 System Peripherals ....................................................................................................... 51 1.4.6 Memory Peripherals ...................................................................................................... 52 1.4.7 Additional Features ....................................................................................................... 52 1.4.8 Hardware Details .......................................................................................................... 53 The Cortex-M3 Processor ...................................................................................... 54 2 2.1 Block Diagram .............................................................................................................. 55 Overview ...................................................................................................................... 56 2.2 System-Level Interface .................................................................................................. 56 2.2.1 2.2.2 Integrated Configurable Debug ...................................................................................... 56 2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 57 2.2.4 Cortex-M3 System Component Details ........................................................................... 57 Programming Model ...................................................................................................... 58 2.3 2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 58 2.3.2 Stacks .......................................................................................................................... 58 2.3.3 Register Map ................................................................................................................ 59 2.3.4 Register Descriptions .................................................................................................... 60 2.3.5 Exceptions and Interrupts .............................................................................................. 73 2.3.6 Data Types ................................................................................................................... 73 2.4 Memory Model .............................................................................................................. 73 2.4.1 Memory Regions, Types and Attributes ........................................................................... 75 2.4.2 Memory System Ordering of Memory Accesses .............................................................. 75 Behavior of Memory Accesses ....................................................................................... 75 2.4.3 Software Ordering of Memory Accesses ......................................................................... 76 2.4.4 2.4.5 Bit-Banding ................................................................................................................... 77 2.4.6 Data Storage ................................................................................................................ 79 Synchronization Primitives ............................................................................................. 80 2.4.7 Exception Model ........................................................................................................... 81 2.5 Exception States ........................................................................................................... 82 2.5.1 2.5.2 Exception Types ............................................................................................................ 82 Exception Handlers ....................................................................................................... 85 2.5.3 January 09, 2011 Texas Instruments-Production Data 3 Table of Contents Vector Table .................................................................................................................. 85 2.5.4 Exception Priorities ....................................................................................................... 86 2.5.5 Interrupt Priority Grouping .............................................................................................. 87 2.5.6 Exception Entry and Return ........................................................................................... 87 2.5.7 Fault Handling .............................................................................................................. 89 2.6 Fault Types ................................................................................................................... 89 2.6.1 Fault Escalation and Hard Faults .................................................................................... 90 2.6.2 Fault Status Registers and Fault Address Registers ........................................................ 91 2.6.3 Lockup ......................................................................................................................... 91 2.6.4 Power Management ...................................................................................................... 91 2.7 2.7.1 Entering Sleep Modes ................................................................................................... 92 2.7.2 Wake Up from Sleep Mode ............................................................................................ 92 2.8 Instruction Set Summary ............................................................................................... 93 Cortex-M3 Peripherals ........................................................................................... 96 3 Functional Description ................................................................................................... 96 3.1 3.1.1 System Timer (SysTick) ................................................................................................. 96 3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 97 3.1.3 System Control Block (SCB) .......................................................................................... 99 3.1.4 Memory Protection Unit (MPU) ....................................................................................... 99 3.2 Register Map .............................................................................................................. 104 System Timer (SysTick) Register Descriptions .............................................................. 106 3.3 NVIC Register Descriptions .......................................................................................... 110 3.4 System Control Block (SCB) Register Descriptions ........................................................ 123 3.5 3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 150 JTAG Interface ...................................................................................................... 160 4 Block Diagram ............................................................................................................ 161 4.1 Functional Description ................................................................................................. 161 4.2 4.2.1 JTAG Interface Pins ..................................................................................................... 161 JTAG TAP Controller ................................................................................................... 163 4.2.2 4.2.3 Shift Registers ............................................................................................................ 164 4.2.4 Operational Considerations .......................................................................................... 164 4.3 Initialization and Configuration ..................................................................................... 167 Register Descriptions .................................................................................................. 167 4.4 4.4.1 Instruction Register (IR) ............................................................................................... 167 4.4.2 Data Registers ............................................................................................................ 169 System Control ..................................................................................................... 172 5 5.1 Functional Description ................................................................................................. 172 5.1.1 Device Identification .................................................................................................... 172 5.1.2 Reset Control .............................................................................................................. 172 5.1.3 Power Control ............................................................................................................. 176 5.1.4 Clock Control .............................................................................................................. 177 System Control ........................................................................................................... 182 5.1.5 5.2 Initialization and Configuration ..................................................................................... 183 Register Map .............................................................................................................. 184 5.3 Register Descriptions .................................................................................................. 185 5.4 6 Hibernation Module .............................................................................................. 238 Block Diagram ............................................................................................................ 239 6.1 4 Texas Instruments-Production Data January 09, 2011 Stellaris® LM3S8962 Microcontroller Functional Description ................................................................................................. 239 6.2 6.2.1 Register Access Timing ............................................................................................... 239 6.2.2 Clock Source .............................................................................................................. 240 6.2.3 Battery Management ................................................................................................... 241 6.2.4 Real-Time Clock .......................................................................................................... 242 6.2.5 Non-Volatile Memory ................................................................................................... 242 Power Control ............................................................................................................. 242 6.2.6 Initiating Hibernate ...................................................................................................... 243 6.2.7 6.2.8 Interrupts and Status ................................................................................................... 243 Initialization and Configuration ..................................................................................... 243 6.3 6.3.1 Initialization ................................................................................................................. 244 6.3.2 RTC Match Functionality (No Hibernation) .................................................................... 244 6.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 244 6.3.4 External Wake-Up from Hibernation .............................................................................. 244 6.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 245 Register Map .............................................................................................................. 245 6.4 6.5 Register Descriptions .................................................................................................. 245 Internal Memory ................................................................................................... 258 7 Block Diagram ............................................................................................................ 258 7.1 7.2 Functional Description ................................................................................................. 258 SRAM Memory ............................................................................................................ 258 7.2.1 Flash Memory ............................................................................................................. 259 7.2.2 Flash Memory Initialization and Configuration ............................................................... 260 7.3 7.3.1 Flash Programming ..................................................................................................... 260 7.3.2 Nonvolatile Register Programming ............................................................................... 261 Register Map .............................................................................................................. 262 7.4 Flash Register Descriptions (Flash Control Offset) ......................................................... 263 7.5 7.6 Flash Register Descriptions (System Control Offset) ...................................................... 271 General-Purpose Input/Outputs (GPIOs) ........................................................... 284 8 8.1 Functional Description ................................................................................................. 284 8.1.1 Data Control ............................................................................................................... 285 8.1.2 Interrupt Control .......................................................................................................... 286 8.1.3 Mode Control .............................................................................................................. 287 8.1.4 Commit Control ........................................................................................................... 287 8.1.5 Pad Control ................................................................................................................. 287 Identification ............................................................................................................... 288 8.1.6 Initialization and Configuration ..................................................................................... 288 8.2 Register Map .............................................................................................................. 289 8.3 8.4 Register Descriptions .................................................................................................. 291 General-Purpose Timers ...................................................................................... 326 9 Block Diagram ............................................................................................................ 327 9.1 9.2 Functional Description ................................................................................................. 328 9.2.1 GPTM Reset Conditions .............................................................................................. 328 32-Bit Timer Operating Modes ...................................................................................... 328 9.2.2 16-Bit Timer Operating Modes ...................................................................................... 329 9.2.3 Initialization and Configuration ..................................................................................... 333 9.3 9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 333 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 334 9.3.2 January 09, 2011 Texas Instruments-Production Data 5
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