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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 1 (1) 1 Introduction to Microelectronics Over the past five decades, microelectronics has revolutionized our lives. While beyond the realm of possibility a few decades ago, cellphones, digital cameras, laptop computers, and many other electronic products have now become an integral part of our daily affairs. Learning microelectronics can be fun. As we learn how each device operates, how devices comprise circuits that perform interesting and useful functions, and how circuits form sophisticated systems, we begin to see the beauty of microelectronics and appreciate the reasons for its explosive growth. This chapter gives an overview of microelectronics so as to provide a context for the material presented in this book. We introduce examples of microelectronic systems and identify important circuit “functions” that they employ. We also provide a review of basic circuit theory to refresh the reader’s memory. 1.1 Electronics versus Microelectronics The general area of electronics began about a century ago and proved instrumental in the radio and radar communications used during the two world wars. Early systems incorporated “vacuum tubes,” amplifying devices that operated with the flow of electrons between plates in a vacuum chamber. However, the finite lifetime and the large size of vacuum tubes motivated researchers to seek an electronic device with better properties. The first transistor was invented in the 1940s and rapidly displaced vacuum tubes. It exhibited a very long (in principle, infinite) lifetime and occupied a much smaller volume (e.g., less than 1 cm3 in packaged form) than vacuum tubes did. But it was not until 1960s that the field of microelectronics, i.e., the science of integrating many transistors on one chip, began. Early “integrated circuits” (ICs) contained only a handful of devices, but advances in the technology soon made it possible to dramatically increase the complexity of “microchips.” Example 1.1 Today’s microprocessors contain about 100 million transistors in a chip area of approximately  3 cm 3 cm. (The chip is a few hundred microns thick.) Suppose integrated circuits were not invented and we attempted to build a processor using 100 million “discrete” transistors. If each   device occupies a volume of 3 mm 3 mm 3 mm, determine the minimum volume for the processor. What other issues would arise in such an implementation? Solution  The minimum volume is given by 27 mm3 108, i.e., a cube 1.4 m on each side! Of course, the 1 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 2 (1) 2 Chap. 1 Introduction to Microelectronics wires connecting the transistors would increase the volume substantially. In addition to occupying a large volume, this discrete processor would be extremely slow; the signals would need to travel on wires as long as 1.4 m! Furthermore, if each discrete transistor costs 1 cent and weighs 1 g, each processor unit would be priced at one million dollars and weigh 100 tons! Exercise How much power would such a system consume if each transistor dissipates 10 W? This book deals with mostly microelectronics while providing sufficient foundation for general (perhaps discrete) electronic systems as well. 1.2 Examples of Electronic Systems At this point, we introduce two examples of microelectronic systems and identify some of the important building blocks that we should study in basic electronics. 1.2.1 Cellular Telephone Cellular telephones were developed in the 1980s and rapidly became popular in the 1990s. Today’s cellphones contain a great deal of sophisticated analog and digital electronics that lie well beyond the scope of this book. But our objective here is to see how the concepts described in this book prove relevant to the operation of a cellphone. Suppose you are speaking with a friend on your cellphone. Your voice is converted to an electric signal by a microphone and, after some processing, transmitted by the antenna. The signal produced by your antenna is picked up by the your friend’s receiver and, after some processing, applied to the speaker [Fig. 1.1(a)]. What goes on in these black boxes? Why are they needed? Transmitter (TX) Receiver (RX) Microphone Speaker ? ? (a) (b) Figure 1.1 (a) Simplified view of a cellphone, (b) further simplification of transmit and receive paths. Let us attempt to omit the black boxes and construct the simple system shown in Fig. 1.1(b). How well does this system work? We make two observations. First, our voice contains frequencies from 20 Hz to 20 kHz (called the “voice band”). Second, for an antenna to operate efficiently, i.e., to convert most of the electrical signal to electromagnetic radiation, its dimension must be a significant fraction (e.g., 25) of the wavelength. Unfortunately, a frequency range of 20 Hz to 20 kHz translates to a wavelength1 of 1:5  107 m to 1:5  104 m, requiring gigantic antennas for each cellphone. Conversely, to obtain a reasonable antenna length, e.g., 5 cm, the wavelength must be around 20 cm and the frequency around 1.5 GHz. 1Recall that the wavelength is equal to the (light) velocity divided by the frequency. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 3 (1) Sec. 1.2 Examples of Electronic Systems 3 How do we “convert” the voice band to a gigahertz center frequency? One possible approach is to multiply the voice signal, xt, by a sinusoid, A cos2fct [Fig. 1.2(a)]. Since multiplication in the time domain corresponds to convolution in the frequency domain, and since the spectrum Voice Signal x (t ) A cos( 2π f C t ) Output Waveform t t t Voice Spectrum X (f ) 0 (a) Spectrum of Cosine f −fC 0 +fC f Output Spectrum −fC 0 +fC f −20 kHz +20 kHz (b) Figure 1.2 (a) Multiplication of a voice signal by a sinusoid, (b) equivalent operation in the frequency domain.  of the sinusoid consists of two impulses at fc, the voice spectrum is simply shifted (translated)  to at 1 fc [Fig. 1.2(b)]. Thus, GHz. This operation is if fc = 1 GHz, the output an example of “amplitude occupies a bandwidth modulation.”2 of 40 kHz centered We therefore postulate that the black box in the transmitter of Fig. 1.1(a) contains a multiplier,3 as depicted in Fig. 1.3(a). But two other issues arise. First, the cellphone must deliver Power Amplifier A cos( 2π f C t ) Oscillator (a) (b) Figure 1.3 (a) Simple transmitter, (b) more complete transmitter. a relatively large voltage swing (e.g., 20 Vpp) to the antenna so that the radiated power can reach across distances of several kilometers, thereby requiring a “power amplifier” between the mul- tiplier and the antenna. Second, the sinusoid, A cos 2fct, must be produced by an “oscillator.” We thus arrive at the transmitter architecture shown in Fig. 1.3(b). Let us now turn our attention to the receive path of the cellphone, beginning with the sim- ple realization illustrated in Fig. 1.1(b). Unfortunately, This topology fails to operate with the principle of modulation: if the signal received by the antenna resides around a gigahertz center frequency, the audio speaker cannot produce meaningful information. In other words, a means of 2Cellphones in fact use other types of modulation to translate the voice band to higher frequencies. 3Also called a “mixer” in high-frequency electronics. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 4 (1) 4 Chap. 1 Introduction to Microelectronics translating the spectrum back to zero center frequency is necessary. For example, as depicted in Fig. 1.4(a), multiplication by a sinusoid, A cos2fct, translates the spectrum to left and right by Output Spectrum Received Spectrum Spectrum of Cosine −fC 0 +fC f −fC 0 +fC f (a) −2f C 0 +2 f C f Low−Pass Filter Low−Noise Amplifier Amplifier Low−Pass Filter oscillator oscillator (b) (c) Figure 1.4 (a) Translation of modulated signal to zero center frequency, (b) simple receiver, (b) more complete receiver.  fc, restoring the original voice band. The newly-generated components at 2fc can be removed by a low-pass filter. We thus arrive at the receiver topology shown in Fig. 1.4(b). Our receiver design is still incomplete. The signal received by the antenna can be as low as a few tens of microvolts whereas the speaker may require swings of several tens or hundreds of millivolts. That is, the receiver must provide a great deal of amplification (“gain”) between the antenna and the speaker. Furthermore, since multipliers typically suffer from a high “noise” and hence corrupt the received signal, a “low-noise amplifier” must precede the multiplier. The overall architecture is depicted in Fig. 1.4(c). Today’s cellphones are much more sophisticated than the topologies developed above. For example, the voice signal in the transmitter and the receiver is applied to a digital signal processor (DSP) to improve the quality and efficiency of the communication. Nonetheless, our study reveals some of the fundamental building blocks of cellphones, e.g., amplifiers, oscillators, and filters, with the last two also utilizing amplification. We therefore devote a great deal of effort to the analysis and design of amplifiers. Having seen the necessity of amplifiers, oscillators, and multipliers in both transmit and receive paths of a cellphone, the reader may wonder if “this is old stuff” and rather trivial compared to the state of the art. Interestingly, these building blocks still remain among the most challenging circuits in communication systems. This is because the design entails critical trade-offs between speed (gigahertz center frequencies), noise, power dissipation (i.e., battery lifetime), weight, cost (i.e., price of a cellphone), and many other parameters. In the competitive world of cellphone manufacturing, a given design is never “good enough” and the engineers are forced to further push the above trade-offs in each new generation of the product. 1.2.2 Digital Camera Another consumer product that, by virtue of “going electronic,” has dramatically changed our habits and routines is the digital camera. With traditional cameras, we received no immediate BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 5 (1) Sec. 1.2 Examples of Electronic Systems 5 feedback on the quality of the picture that was taken, we were very careful in selecting and shooting scenes to avoid wasting frames, we needed to carry bulky rolls of film, and we would obtain the final result only in printed form. With digital cameras, on the other hand, we have resolved these issues and enjoy many other features that only electronic processing can provide, e.g., transmission of pictures through cellphones or ability to retouch or alter pictures by computers. In this section, we study the operation of the digital camera. The “front end” of the camera must convert light to electricity, a task performed by an array (matrix) of “pixels.”4 Each pixel consists of an electronic device (a “photodiode” that produces a current proportional to the intensity of the light that it receives. As illustrated in Fig. 1.5(a), this current flows through a capacitance, CL, for a certain period of time, thereby developing a 2500 Columns Amplifier 2500 Rows Light I Diode CL Vout Photodiode Signal Processing (a) (b) (c) Figure 1.5 (a) Operation of a photodiode, (b) array of pixels in a digital camera, (c) one column of the array. proportional voltage across it. Each pixel thus provides a voltage proportional to the “local” light density. Now consider a camera with, say, 6.25-million pixels arranged in a 2500  2500 array [Fig. 1.5(b)]. How is the output voltage of each pixel sensed and processed? If each pixel contains its own electronic circuitry, the overall array occupies a very large area, raising the cost and the power dissipation considerably. We must therefore “time-share” the signal processing circuits among pixels. To this end, we follow the circuit of Fig. 1.5(a) with a simple, compact amplifier and a switch (within the pixel) [Fig. 1.5(c)]. Now, we connect a wire to the outputs of all 2500 pixels in a “column,” turn on only one switch at a time, and apply the corresponding voltage to the “signal processing” block outside the column. The overall array consists of 2500 of such columns, with each column employing a dedicated signal processing block. Example 1.2 A digital camera is focused on a chess board. Sketch the voltage produced by one column as a function of time. 4The term “pixel” is an abbreviation of “picture cell.” BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 6 (1) 6 Chap. 1 Introduction to Microelectronics Solution The pixels in each column receive light only from the white squares [Fig. 1.6(a)]. Thus, the Vcolumn Vcolumn t (a) (b) (c) Figure 1.6 (a) Chess board captured by a digital camera, (b) voltage waveform of one column. column voltage alternates between a maximum for such pixels and zero for those receiving no light. The resulting waveform is shown in Fig. 1.6(b). Exercise Plot the voltage if the first and second squares in each row have the same color. What does each signal processing block do? Since the voltage produced by each pixel is an analog signal and can assume all values within a range, we must first “digitize” it by means of an “analog-to-digital converter” (ADC). A 6.25 megapixel array must thus incorporate 2500 ADCs. Since ADCs are relatively complex circuits, we may time-share one ADC between every two columns (Fig. 1.7), but requiring that the ADC operate twice as fast (why?). In the extreme case, ADC Figure 1.7 Sharing one ADC between two columns of a pixel array. we may employ a single, very fast ADC for all 2500 columns. In practice, the optimum choice lies between these two extremes. Once in the digital domain, the “video” signal collected by the camera can be manipulated extensively. For example, to “zoom in,” the digital signal processor (DSP) simply considers only BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 7 (1) Sec. 1.3 Basic Concepts 7 a section of the array, discarding the information from the remaining pixels. Also, to reduce the required memory size, the processor “compresses” the video signal. The digital camera exemplifies the extensive use of both analog and digital microelectronics. The analog functions include amplification, switching operations, and analog-to-digital conversion, and the digital functions consist of subsequent signal processing and storage. 1.2.3 Analog versus Digital Amplifiers and ADCs are examples of “analog” functions, circuits that must process each point on a waveform (e.g., a voice signal) with great care to avoid effects such as noise and “distortion.” By contrast, “digital” circuits deal with binary levels (ONEs and ZEROs) and, evidently, contain no analog functions. The reader may then say, “I have no intention of working for a cellphone or camera manufacturer and, therefore, need not learn about analog circuits.” In fact, with digital communications, digital signal processors, and every other function becoming digital, is there any future for analog design? Well, some of the assumptions in the above statements are incorrect. First, not every function can be realized digitally. The architectures of Figs. 1.3 and 1.4 must employ low-noise and power amplifiers, oscillators, and multipliers regardless of whether the actual communication is in analog or digital form. For example, a 20-V signal (analog or digital) received by the antenna cannot be directly applied to a digital gate. Similarly, the video signal collectively captured by the pixels in a digital camera must be processed with low noise and distortion before it appears in the digital domain. Second, digital circuits require analog expertise as the speed increases. Figure 1.8 exemplifies this point by illustrating two binary data waveforms, one at 100 Mb/s and another at 1 Gb/s. The finite risetime and falltime of the latter raises many issues in the operation of gates, flipflops, and other digital circuits, necessitating great attention to each point on the waveform. 10 ns x 1 (t ) 1 ns t x 2 (t ) t Figure 1.8 Data waveforms at 100 Mb/s and 1 Gb/s. 1.3 Basic Concepts Analysis of microelectronic circuits draws upon many concepts that are taught in basic courses on signals and systems and circuit theory. This section provides a brief review of these concepts so as to refresh the reader’s memory and establish the terminology used throughout this book. The reader may first glance through this section to determine which topics need a review or simply return to this material as it becomes necessary later. 1.3.1 Analog and Digital Signals An electric signal is a waveform that carries information. Signals that occur in nature can assume all values in a given range. Called “analog,” such signals include voice, video, seismic, and music This section serves as a review and can be skipped in classroom teaching. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 8 (1) 8 Chap. 1 Introduction to Microelectronics waveforms. Shown in Fig. 1.9(a), an analog voltage waveform swings through a “continuum” of V (t V ( t + Noise ( ( t t (a) (b) Figure 1.9 (a) Analog signal , (b) effect of noise on analog signal. values and provides information at each instant of time. While occurring all around us, analog signals are difficult to “process” due to sensitivities to such circuit imperfections as “noise” and “distortion.”5 As an example, Figure 1.9(b) illus- trates the effect of noise. Furthermore, analog signals are difficult to “store” because they require “analog memories” (e.g., capacitors). By contrast, a digital signal assumes only a finite number of values at only certain points in time. Depicted in Fig. 1.10(a) is a “binary” waveform, which remains at only one of two levels for ( ( V (t ONE V ( t + Noise ZERO TT t (a) t (b) Figure 1.10 (a) Digital signal, (b) effect of noise on digital signal. each period, T . So long as the two voltages corresponding to ONEs and ZEROs differ sufficiently, logical circuits sensing such a signal process it correctly—even if noise or distortion create some corruption [Fig. 1.10(b)]. We therefore consider digital signals more “robust” than their analog counterparts. The storage of binary signals (in a digital memory) is also much simpler. The foregoing observations favor processing of signals in the digital domain, suggesting that inherently analog information must be converted to digital form as early as possible. Indeed, complex microelectronic systems such as digital cameras, camcorders, and compact disk (CD) recorders perform some analog processing, “analog-to-digital conversion,” and digital processing (Fig. 1.11), with the first two functions playing a critical role in the quality of the signal. Analog Signal Analog Processing Analog−to−Digital Conversion Digital Processing and Storage Figure 1.11 Signal processing in a typical system. It is worth noting that many digital binary signals must be viewed and processed as analog waveforms. Consider, for example, the information stored on a hard disk in a computer. Upon retrieval, the “digital” data appears as a distorted waveform with only a few millivolts of amplitude 5Distortion arises if the output is not a linear function of input. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 9 (1) Sec. 1.3 Basic Concepts 9 (Fig. 1.12). Such a small separation between ONEs and ZEROs proves inadequate if this signal Hard Disk ~3 mV t Figure 1.12 Signal picked up from a hard disk in a computer. is to drive a logical gate, demanding a great deal of amplification and other analog processing before the data reaches a robust digital form. 1.3.2 Analog Circuits Today’s microelectronic systems incorporate many analog functions. As exemplified by the cell- phone and the digital camera studied above, analog circuits often limit the performance of the overall system. The most commonly-used analog function is amplification. The signal received by a cellphone or picked up by a microphone proves too small to be processed further. An amplifier is therefore necessary to raise the signal swing to acceptable levels. The performance of an amplifier is characterized by a number of parameters, e.g., gain, speed, and power dissipation. We study these aspects of amplification in great detail later in this book, but it is instructive to briefly review some of these concepts here. A voltage amplifier produces an output swing greater than the input swing. The voltage gain, Av, is defined as Av = vout vin : (1.1) In some cases, we prefer to express the gain in decibels (dB): Av jdB = 20 log vout vin : (1.2) For example, a voltage gain of 10 translates to 20 dB. The gain of typical amplifiers falls in the range of 101 to 105. Example 1.3 A cellphone receives a signal level of 20 V, but it must deliver a swing of 50 mV to the speaker that reproduces the voice. Calculate the required voltage gain in decibels. Solution We have Av = 20 log 50 mV 20 V (1.3)  68 dB: (1.4) Exercise What is the output swing if the gain is 50 dB? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 10 (1) 10 Chap. 1 Introduction to Microelectronics In order to operate properly and provide gain, an amplifier must draw power from a voltage source, e.g., a battery or a charger. Called the “power supply,” this source is typically denoted by VCC or VDD [Fig. 1.13(a)]. In complex circuits, we may simplify the notation to that shown in Amplifier Vin Vout VCC Vin VCC Vout Vin Vout Ground (a) (b) (c) Figure 1.13 (a) General amplifier symbol along with its power supply, (b) simplified diagram of (a), (b) amplifier with supply rails omitted. Fig. 1.13(b), where the “ground” terminal signifies a reference point with zero potential. If the amplifier is simply denoted by a triangle, we may even omit the supply terminals [Fig. 1.13(c)], with the understanding that they are present. Typical amplifiers operate with supply voltages in the range of 1 V to 10 V. What limits the speed of amplifiers? We expect that various capacitances in the circuit begin to manifest themselves at high frequencies, thereby lowering the gain. In other words, as depicted in Fig. 1.14, the gain rolls off at sufficiently high frequencies, limiting the (usable) “bandwidth” High−Frequency Roll−off Amplifier Gain Figure 1.14 Roll-off an amplifier’s gain at high frequencies. Frequency of the circuit. Amplifiers (and other analog circuits) suffer from trade-offs between gain, speed and power dissipation. Today’s microelectronic amplifiers achieve bandwidths as large as tens of gigahertz. What other analog functions are frequently used? A critical operation is “filtering.” For example, an electrocardiograph measuring a patient’s heart activities also picks up the 60-Hz (or 50-Hz) electrical line voltage because the patient’s body acts as an antenna. Thus, a filter must suppress this “interferer” to allow meaningful measurement of the heart. 1.3.3 Digital Circuits More than 80 of the microelectronics industry deals with digital circuits. Examples include microprocessors, static and dynamic memories, and digital signal processors. Recall from basic logic design that gates form “combinational” circuits, and latches and flipflops constitute “sequential” machines. The complexity, speed, and power dissipation of these building blocks play a central role in the overall system performance. In digital microelectronics, we study the design of the internal circuits of gates, flipflops, and other components. For example, we construct a circuit using devices such as transistors to BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 11 (1) Sec. 1.3 Basic Concepts 11 realize the NOT and NOR functions shown in Fig. 1.15. Based on these implementations, we NOT Gate A Y =A NOR Gate A Y =A +B B Figure 1.15 NOT and NOR gates. then determine various properties of each circuit. For example, what limits the speed of a gate? How much power does a gate consume while running at a certain speed? How robustly does a gate operate in the presence of nonidealities such as noise (Fig. 1.16)? ? Figure 1.16 Response of a gate to a noisy input. Example 1.4 Consider the circuit shown in Fig. 1.17, where switch S1 is controlled by the digital input. That RL A S 1 Vout VDD Figure 1.17 is, if A is high, S1 is on and vice versa. Prove that the circuit provides the NOT function. Solution If A is high, S1 is on, forcing Vout to zero. On the other hand, if A is low, S1 remains off, drawing no current from RL. As a result, the voltage drop across RL is zero and hence Vout = VDD; i.e., the output is high. We thus observe that, for both logical states at the input, the output assumes the opposite state. Exercise Determine the logical function if S1 and RL are swapped and Vout is sensed across RL. The above example indicates that switches can perform logical operations. In fact, early digital circuits did employ mechanical switches (relays), but suffered from a very limited speed (a few kilohertz). It was only after “transistors” were invented and their ability to act as switches was recognized that digital circuits consisting of millions of gates and operating at high speeds (several gigahertz) became possible. 1.3.4 Basic Circuit Theorems Of the numerous analysis techniques taught in circuit theory courses, some prove particularly important to our study of microelectronics. This section provides a review of such concepts. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 12 (1) 12 Chap. 1 Introduction to Microelectronics I1 In I2 Ij Figure 1.18 Illustration of KCL. Kirchoff’s Laws The Kirchoff Current Law (KCL) states that the sum of all currents flowing into a node is zero (Fig. 1.18): X Ij = 0: (1.5) j KCL in fact results from conservation of charge: a nonzero sum would mean that either some of the charge flowing into node X vanishes or this node produces charge. The Kirchoff Voltage Law (KVL) states that the sum of voltage drops around any closed loop in a circuit is zero [Fig. 1.19(a)]: 2 V2 1 V1 V3 3 V4 4 V2 2 1 V1 V3 3 V4 4 (a) (b) Figure 1.19 (a) Illustration of KVL, (b) slightly different view of the circuit . X Vj = 0; (1.6) j where Vj denotes the voltage drop across element number j. KVL arises from the conservation of the “electromotive force.” In the example illustrated in Fig. 1.19(a), we may sum the voltages in in V1 the loop to zero: Fig. 1.19(b), we = V2 +V3 +V4. NcVao1nte+stahVya2tV+t1heiVsp3eo+qlaurVaitl4ieto=s aths0se.igAsnulemtedrtnooaf tVtihv2ee, lVvy3,o,altadanogdpetsVin4agcinrtohFseisgme. l1oe.dm1i9fie(nebtd)s view shown 2, 3, and 4: are different from those in Fig. 1.19(a). In solving circuits, we may not know a priori the correct polarities of the currents and voltages. Nonetheless, we can simply assign arbitrary polarities, write KCLs and KVLs, and solve the equations to obtain the actual polarities and values. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 13 (1) Sec. 1.3 Basic Concepts 13 Example 1.5 The topology depicted in Fig. 1.20 represents the equivalent circuit of an amplifier. The dependent current source i1 is equal to a constant, gm,6 multiplied by the voltage drop across Figure 1.20 v in rπ vπ i1 g m vπ RL v out RL v out r. Determine the voltage gain of the amplifier, vout=vin. Solution We must compute vout in terms of vin, i.e., we must eliminate v from the equations. Writing a KVL in the “input loop,” we have vin = v; (1.7) and hence gmv = gmvin. A KCL at the output node yields gmv + vout RL = 0: (1.8) It follows that vout vin = ,gmRL: (1.9) Note that the circuit amplifies the input if gmRL 1. Unimportant in most cases, the negative sign simply means the circuit “inverts” the signal. Exercise Repeat the above example if r ! infty. Example 1.6 Figure 1.21 shows another amplifier topology. Compute the gain. r π vπ i1 gmvπ RL v out v in Figure 1.21 g 6What is the dimension of m? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 14 (1) 14 Chap. 1 Introduction to Microelectronics Solution Noting that r in fact appears in parallel with vin, we write a KVL across these two components: vin = ,v: (1.10) The KCL at the output node is similar to (1.8). Thus, vout vin = gmRL: Interestingly, this type of amplifier does not invert the signal. (1.11) Exercise Repeat the above example if r ! infty. Example 1.7 A third amplifier topology is shown in Fig. 1.22. Determine the voltage gain. v in r π vπ i1 gmvπ RE v out Figure 1.22 Solution We first write a KVL around the loop consisting of vin, r, and RE: vin = v + vout: (1.12) That is, v = vin , node, and the current vvoouutt.=RNeExtfl,onwostinoguttohfatitt,hweecwurrrietentas v=r KCL: and gmv flow into the output v r + gmv = vout RE : (1.13) Substituting vin , vout fovrinv gr1ive+s gm = vout 1 RE + 1 r + gm ; (1.14) and hence vout vin = 1 R1E r+ + gm 1 r + gm (1.15) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 15 (1) Sec. 1.3 Basic Concepts 15 = r 1 + + gmrRE 1 + gmrRE : (1.16) Note that the voltage gain always remains below unity. Would such an amplifier prove useful at all? In fact, this topology exhibits some important properties that make it a versatile building block. Exercise Repeat the above example if r ! infty. The above three examples relate to three amplifier topologies that are studied extensively in Chapter 5. Thevenin and Norton Equivalents While Kirchoff’s laws can always be utilized to solve any circuit, the Thevenin and Norton theorems can both simplify the algebra and, more importantly, provide additional insight into the operation of a circuit. Thevenin’s theorem states that a (linear) one-port network can be replaced with an equivalent circuit consisting of one voltage source in series with one impedance. Illustrated in Fig. 1.23(a), the term “port” refers to any two nodes whose voltage difference is of interest. The equivalent v X Vj iX Port j Z Thev Z Thev v Thev (a) (b) Figure 1.23 (a) Thevenin equivalent circuit, (b) computation of equivalent impedance. voltage, vT hev, is obtained by leaving the port open and computing the voltage created by the actual circuit at this port. The equivalent impedance, ZT hev, is determined by setting all indepen- dent voltage and current sources in the circuit to zero and calculating the impedance between the two nodes. We also call ZT hev the impedance “seen” when “looking” into the output port [Fig. 1.23(b)]. The impedance is computed by applying a voltage source across the port and obtaining the resulting current. A few examples illustrate these principles. Example 1.8 Suppose the input voltage source and the amplifier shown in Fig. 1.20 are placed in a box and only the output port is of interest [Fig. 1.24(a)]. Determine the Thevenin equivalent of the circuit. Solution We must compute the open-circuit output voltage and the impedance seen when looking into the BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 16 (1) 16 Chap. 1 Introduction to Microelectronics iX v in r π vπ i 1 gmvπ R L v out v in = 0 r π vπ i 1 gmvπ R L vX RL − g R m Lv in (a) Figure 1.24 (b) (c) output port. The Thevenin voltage is obtained from Fig. 1.24(a) and Eq. (1.9): vThev = vout = ,gmRLvin: (1.17) (1.18) To calculate ZT hev, we set vin to zero, apply a voltage source, vX , across the output port, and determine the current drawn from the voltage source, iX. As shown in Fig. 1.24(b), setting vin ibtonottzHhheeortoewcrimmrdceoiunaiwantlsbeserosecofpalulrvaseceiatnihrtgeeditcetiiperwedcniuttdhiotsaogofrsnohFutoihngred.t ,v1cvoi.2rlct4au=(gibte).0?aAcWalrnsoeods,msgnrmuostve,twathg=haaotisn0teh.eevTliahcmleuuirencriaeirstncetnuvsoitottu.khrFnucoosewrrtguenmdnauvatcpeerlrisyeo,tmrosi.ianRicnLes and iX = vX RL : (1.19) That is, RThev = RL: (1.20) Figure 1.24(c) depicts the Thevenin equivalent of the input voltage source and the amplifier. In this case, we call RT hev (= RL) the “output impedance” of the circuit. Exercise Repeat the above example if r ! 1. With the Thevenin equivalent of a circuit available, we can readily analyze its behavior in the presence of a subsequent stage or “load.” Example 1.9 The amplifier of Fig. 1.20 must drive a speaker having an impedance of Rsp. Determine the voltage delivered to the speaker. Solution Shown in Fig. 1.25(a) is the overall circuit arrangement that must solve. Replacing the section in the dashed box with its Thevenin equivalent from Fig. 1.24(c), we greatly simplify the circuit [Fig. 1.25(b)], and write vout = ,gmRLvin Rsp Rsp + RL (1.21) = ,gmvinRLjjRsp: (1.22) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 17 (1) Sec. 1.3 Basic Concepts 17 RL v in r π vπ i1 gmvπ RL v out Rsp − g mR Lv in v out Rsp (a) (b) Figure 1.25 Exercise Repeat the above example if r ! 1. Example 1.10 Determine the Thevenin equivalent of the circuit shown in Fig. 1.22 if the output port is of interest. Solution The open-circuit output voltage is simply obtained from (1.16): vT hev = r 1 + + gmrRL 1 + gmrRL vin: (1.23) To calculate the Thevenin impedance, we set vin to zero and apply a voltage source across the output port as depicted in Fig. 1.26. To eliminate v, we recognize that the two terminals of r rπ vπ i1 g m vπ iX RL vX vX RL Figure 1.26 are tied to those of vX and hence v = ,vX: (1.24) We now write a KCL at the output node. The currents v=r, gmv, and iX flow into this node and the current vX =RL flows out of it. Consequently, v r + gmv + iX = vX RL ; (1.25) or 1 r + gm ,vX  + iX = vX RL : (1.26) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 18 (1) 18 That is, Chap. 1 Introduction to Microelectronics RT hev = vX iX (1.27) = r + rRL 1 + gmrRL : (1.28) Exercise What happens if RL = 1? Norton’s theorem states that a (linear) one-port network can be represented by one current source in parallel with one impedance (Fig. 1.27). The equivalent current, iNor, is obtained by Port j Z Nor i Nor Figure 1.27 Norton’s theorem. shorting the port of interest and computing the current that flows through it. The equivalent impedance, ZNor, circuit to zero and is determined by setting all independent voltage and current calculating the impedance seen at the port. Of course, ZNor = sources ZT hev . in the Example 1.11 Determine the Norton equivalent of the circuit shown in Fig. 1.20 if the output port is of interest. Solution As depicted in Fig. 1.28(a), we short the output port and seek the value of iNor. Since the voltage i Nor v in rπ vπ i1 g m vπ RL Short Circuit gv m in RL (a) (b) Figure 1.28 across RL is now forced to zero, this resistor carries no current. A KCL at the output node thus yields iNor = ,gmv (1.29) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 19 (1) Sec. 1.4 Chapter Summary 19 = ,gmvin: (1.30) , Also, from Example 1.8, RNor (= as shown in Fig. 1.28(b). To check through RL produces a voltage of RT hev = RL. The Norton equivalent therefore emerges the validity of this model, we observe that the gmRLvin, the same as the output voltage of flow of iNor the original circuit. Exercise Repeat the above example if a resistor of value R1 is added between the top terminal of vin and the output node. Example 1.12 Determine the Norton equivalent of the circuit shown in Fig. 1.22 if the output port is interest. Solution Shorting the output port as illustrated in Fig. 1.29(a), we note that RL carries no current. Thus, v in r π vπ i1 gmvπ RL i Nor ( 1 rπ + g m ) vin r π RL r π + (1+ gr m π ) R L (a) (b) Figure 1.29 iNor = v r + gmv: (1.31) Also, vin = v (why?), yielding iNor = 1 r + gm vin: (1.32) With the aid of RT hev found in Example 1.10, we construct the Norton equivalent depicted in Fig. 1.29(b). Exercise What happens if r = infty? 1.4 Chapter Summary Electronic functions appear in many devices, including cellphones, digital cameras, laptop computers, etc. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 20 (1) 20 Chap. 1 Introduction to Microelectronics Amplification is an essential operation in many analog and digital systems. Analog circuits process signals that can assume various values at any time. By contrast, digital circuits deal with signals having only two levels and switching between these values at known points in time. Despite the “digital revolution,” analog circuits find wide application in most of today’s electronic systems. The voltage gain of an amplifier is defined as vout=vin and sometimes expressed in decibels (dB) as 20 logvout=vin. Kirchoff’s current law (KCL) states that the sum of all currents flowing into any node is zero. Kirchoff’s voltage law (KVL) states that the sum of all voltages around any loop is zero. Norton’s theorem allows simplifying a one-port circuit to a current source in parallel with an impedance. Similarly, Thevenin’s theorem reduces a one-port circuit to a voltage source in series with an impedance. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 21 (1) 2 Basic Physics of Semiconductors Microelectronic circuits are based on complex semiconductor structures that have been under active research for the past six decades. While this book deals with the analysis and design of circuits, we should emphasize at the outset that a good understanding of devices is essential to our work. The situation is similar to many other engineering problems, e.g., one cannot design a high-performance automobile without a detailed knowledge of the engine and its limitations. Nonetheless, we do face a dilemma. Our treatment of device physics must contain enough depth to provide adequate understanding, but must also be sufficiently brief to allow quick entry into circuits. This chapter accomplishes this task. Our ultimate objective in this chapter is to study a fundamentally-important and versatile device called the “diode.” However, just as we need to eat our broccoli before having desert, we must develop a basic understanding of “semiconductor” materials and their current conduction mechanisms before attacking diodes. In this chapter, we begin with the concept of semiconductors and study the movement of charge (i.e., the flow of current) in them. Next, we deal with the the “pn junction,” which also serves as diode, and formulate its behavior. Our ultimate goal is to represent the device by a circuit model (consisting of resistors, voltage or current sources, capacitors, etc.), so that a circuit using such a device can be analyzed easily. The outline is shown below. Semiconductors Charge Carriers Doping Transport of Carriers PN Junction Structure Reverse and Forward Bias Conditions I/V Characteristics Circuit Models It is important to note that the task of developing accurate models proves critical for all microelectronic devices. The electronics industry continues to place greater demands on circuits, calling for aggressive designs that push semiconductor devices to their limits. Thus, a good un- derstanding of the internal operation of devices is necessary.1 1As design managers often say, “If you do not push the devices and circuits to their limit but your competitor does, then you lose to your competitor.” 21 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 22 (1) 22 Chap. 2 Basic Physics of Semiconductors 2.1 Semiconductor Materials and Their Properties Since this section introduces a multitude of concepts, it is useful to bear a general outline in mind: Charge Carriers in Solids Crystal Structure Bandgap Energy Holes Figure 2.1 Outline of this section. Modification of Carrier Densities Intrinsic Semiconductors Extrinsic Semiconductors Doping Transport of Carriers Diffusion Drift This outline represents a logical thought process: (a) we identify charge carriers in solids and formulate their role in current flow; (b) we examine means of modifying the density of charge carriers to create desired current flow properties; (c) we determine current flow mechanisms. These steps naturally lead to the computation of the current/voltage (I/V) characteristics of actual diodes in the next section. 2.1.1 Charge Carriers in Solids Recall from basic chemistry that the electrons in an atom orbit the nucleus in different “shells.” The atom’s chemical activity is determined by the electrons in the outermost shell, called “valence” electrons, and how complete this shell is. For example, neon exhibits a complete outermost shell (with eight electrons) and hence no tendency for chemical reactions. On the other hand, sodium has only one valence electron, ready to relinquish it, and chloride has seven valence electrons, eager to receive one more. Both elements are therefore highly reactive. The above principles suggest that atoms having approximately four valence electrons fall somewhere between inert gases and highly volatile elements, possibly displaying interesting chemical and physical properties. Shown in Fig. 2.2 is a section of the periodic table contain- III IV V Boron (B) Aluminum (Al) Galium (Ga) Carbon (C) Silicon (Si) Germanium (Ge) Phosphorous (P) Arsenic (As) Figure 2.2 Section of the periodic table. ing a number of elements with three to five valence electrons. As the most popular material in microelectronics, silicon merits a detailed analysis.2 2Silicon is obtained from sand after a great deal of processing. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 23 (1) Sec. 2.1 Semiconductor Materials and Their Properties 23 Covalent Bonds A silicon atom residing in isolation contains four valence electrons [Fig. 2.3(a)], requiring another four to complete its outermost shell. If processed properly, the sili- Covalent Bond Si Si Si Si Si Si Si Si Si Si e Si Si Si Si Si Free Electron (a) (b) (c) Figure 2.3 (a) Silicon atom, (b) covalent bonds between atoms, (c) free electron released by thermal energy. con material can form a “crystal” wherein each atom is surrounded by exactly four others [Fig. 2.3(b)]. As a result, each atom shares one valence electron with its neighbors, thereby completing its own shell and those of the neighbors. The “bond” thus formed between atoms is called a “covalent bond” to emphasize the sharing of valence electrons. The uniform crystal depicted in Fig. 2.3(b) plays a crucial role in semiconductor devices. But, does it carry current in response to a voltage? At temperatures near absolute zero, the valence electrons are confined to their respective covalent bonds, refusing to move freely. In other words, ! the silicon crystal behaves as an insulator for T 0K. However, at higher temperatures, elec- trons gain thermal energy, occasionally breaking away from the bonds and acting as free charge carriers [Fig. 2.3(c)] until they fall into another incomplete bond. We will hereafter use the term “electrons” to refer to free electrons. Holes When freed from a covalent bond, an electron leaves a “void” behind because the bond is now incomplete. Called a “hole,” such a void can readily absorb a free electron if one becomes available. Thus, we say an “electron-hole pair” is generated when an electron is freed, and an “electron-hole recombination” occurs when an electron “falls” into a hole. Why do we bother with the concept of the hole? After all, it is the free electron that actually moves in the crystal. To appreciate the usefulness of holes, consider the time evolution illustrated in Fig. 2.4. Suppose covalent bond number 1 contains a hole after losing an electron some time t = t1 t = t2 t = t3 1 Si Si Si Si Si Si Si Hole Si Si Si Si Si Si 2 Si Si Si 3 Si Si Si Si Si Figure 2.4 Movement of electron through crystal. before t = t1. At t = hole in bond number t2, an electron 1. Similarly, at breaks t = t3, away from bond number 2 and recombines with an electron leaves bond number 3 and falls into the the hole in bond number 2. Looking at the three “snapshots,” we can say one electron has traveled from right to left, or, alternatively, one hole has moved from left to right. This view of current flow by holes proves extremely useful in the analysis of semiconductor devices. Bandgap Energy We must now answer two important questions. First, does any thermal energy create free electrons (and holes) in silicon? No, in fact, a minimum energy is required to BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 24 (1) 24 Chap. 2 Basic Physics of Semiconductors dislodge an electron from a minimum is a fundamental covalent property bond. of the Called the “bandgap energy” and denoted material. For silicon, Eg = 1:12 eV.3 by Eg , this The second question relates to the conductivity of the material and is as follows. How many free electrons are created at a given temperature? From our observations thus far, we postulate that the number of electrons depends on both Eg and T : a greater Eg translates to fewer electrons, but a higher T yields more electrons. To simplify future derivations, we consider the density (or concentration) of electrons, i.e., the number of electrons per unit volume, ni, and write for silicon: ni = 5:2  1015T 3=2 exp ,Eg 2kT electrons=cm3 (2.1) where k = 1:38  10,23 J/K is called the Boltzmann constant. The derivation can be found in books on semiconductor smaller ni. Also, as T ! physics, 0, so do eT.g3=.,2[a1n].dAexspex,pEecgt=ed2, kmTate,ritahlesrehbayvibnrginagilnarggneri Eg exhibit a toward zero. The exponential dependence of ni upon Eg reveals the effect of the bandgap energy on the conductivity of the material. Insulators display a high Eg; for example, Eg = 2:5 eV for dia- mond. Conductors, on the other hand, have a small bandgap. Finally, semiconductors exhibit a moderate Eg, typically ranging from 1 eV to 1.5 eV. Example 2.1 Determine the density of electrons in silicon at T = 300 K (room temperature) and T = 600 K. Solution Since Eg = 1:12 eV= 1:792  10,19 J, we have niT = 300 K = 1:08  1010 electrons=cm3 (2.2) niT = 600 K = 1:54  1015 electrons=cm3: (2.3) Since for each free electron, a hole is left behind, the density of holes is also given by (2.2) and (2.3). Exercise Repeat the above exercise for a material having a bandgap of 1.5 eV. hasT5hen1i 0v2a2luaetsoombst=aicnmed3,inwtehereacboogvneizeextahmatploenmlyayonaeppinea5r quite high, but, noting  1012 atoms benefit that silicon from a free electron at room temperature. In other words, silicon still seems a very poor conductor. But, do not despair! We next introduce a means of making silicon more useful. 2.1.2 Modification of Carrier Densities Intrinsic and Extrinsic Semiconductors The “pure” type of silicon studied thus far is an example of “intrinsic semiconductors,” suffering from a very high resistance. Fortunately, it is possible to modify the resistivity of silicon by replacing some of the atoms in the crystal with atoms of another material. In an intrinsic semiconductor, the electron density, n= ni, is equal :  V. 3The unit Note that 1 eV (electron eV= 1 6 1v0o,lt)19reJp.resents the energy necessary to move one electron across a potential difference of 1 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 25 (1) Sec. 2.1 Semiconductor Materials and Their Properties 25 to the hole density, p. Thus, np = n2i : (2.4) We return to this equation later. Recall from Fig. 2.2 that phosphorus (P) contains five valence electrons. What happens if some P atoms are introduced in a silicon crystal? As illustrated in Fig. 2.5, each P atom shares Si Si Si P e Si Si Si Figure 2.5 Loosely-attached electon with phosphorus doping. four electrons with the neighboring silicon atoms, leaving the fifth electron “unattached.” This electron is free to move, serving as a charge carrier. Thus, if N phosphorus atoms are uniformly introduced in each cubic centimeter of a silicon crystal, then the density of free electrons rises by the same amount. The controlled addition of an “impurity” such as phosphorus to an intrinsic semiconductor is called “doping,” and phosphorus itself a “dopant.” Providing many more free electrons than in the intrinsic state, the doped silicon crystal is now called “extrinsic,” more specifically, an “n-type” semiconductor to emphasize the abundance of free electrons. As remarked earlier, the electron and hole densities in an intrinsic semiconductor are equal. But, how about these densities in a doped material? It can be proved that even in this case, np = n2i ; (2.5) where n and p respectively denote the electron and hole densities in the extrinsic semiconductor. The quantity ni represents the densities in the intrinsic semiconductor (hence the subscript i) and is therefore independent of the doping level [e.g., Eq. (2.1) for silicon]. Example 2.2 The above result seems quite strange. How can np remain constant while we add more donor atoms and increase n? Solution Equation (2.5) reveals that p must fall below its intrinsic level as more n-type dopants are added to the crystal. This occurs because many of the new electrons donated by the dopant “recombine” with the holes that were created in the intrinsic material. Exercise Why can we not say that n + p should remain constant? Example 2.3 A piece of crystalline silicon is doped uniformly with phosphorus atoms. The doping density is BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 26 (1) 26 Chap. 2 Basic Physics of Semiconductors 1016 atoms/cm3. Determine the electron and hole densities in this material at the room tempera- ture. Solution The addition of 1016 P atoms introduces the same number of free electrons per cubic centimeter. Since this electron density exceeds that calculated in Example 2.1 by six orders of magnitude, we can assume n = 1016 electrons=cm3 (2.6) It follows from (2.2) and (2.5) that p = n2i n (2.7) = 1:17  104 holes=cm3 (2.8) Note that the hole density has dropped below the intrinsic level by six orders of magnitude. Thus, if a voltage is applied across this piece of silicon, the resulting current predominantly consists of electrons. Exercise At what doping level does the hole density drop by three orders of magnitude? This example justifies the reason for calling electrons the “majority carriers” and holes the “minority carriers” in an n-type semiconductor. We may naturally wonder if it is possible to construct a “p-type” semiconductor, thereby exchanging the roles of electrons and holes. Indeed, if we can dope silicon with an atom that provides an insufficient number of electrons, then we may obtain many incomplete covalent bonds. For example, the table in Fig. 2.2 suggests that a boron (B) atom—with three valence electrons—can form only three complete covalent bonds in a silicon crystal (Fig. 2.6). As a result, the fourth bond contains a hole, ready to absorb Si Si Si B Si Si Si Figure 2.6 Available hole with boron doping. a free electron. In other words, N boron atoms contribute N boron holes to the conduction of current in silicon. The structure in Fig. 2.6 therefore exemplifies a p-type semiconductor, providing holes as majority carriers. The boron atom is called an “acceptor” dopant. Let us formulate our results thus far. If an intrinsic semiconductor is doped with a density of ND ( ni) donor atoms per cubic centimeter, then the mobile charge densities are given by Majority Carriers : n  ND (2.9) Minority Carriers : p  n2i ND : (2.10) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 27 (1) Sec. 2.1 Semiconductor Materials and Their Properties 27 Similarly, for a density of NA ( ni) acceptor atoms per cubic centimeter: Majority Carriers : p  NA (2.11) Minority Carriers : n  n2i NA : (2.12) Since typical doping densities fall in the range of 1015 to 1018 atoms=cm3, the above expressions are quite accurate. Example 2.4 Is it possible to use other elements of Fig. 2.2 as semiconductors and dopants? Solution Yes, for example, some early diodes and transistors were based on germanium (Ge) rather than silicon. Also, arsenic (As) is another common dopant. Exercise Can carbon be used for this purpose? Figure 2.7 summarizes the concepts introduced in this section, illustrating the types of charge carriers and their densities in semiconductors. Intrinsic Semiconductor Si Covalent Bond Si Si Valence Electron Extrinsic Semiconductor Silicon Crystal ND Donors/cm3 Si Si Si P e Si Si n−Type Dopant (Donor) Si Free Majority Carrier Figure 2.7 Summary of charge carriers in silicon. Silicon Crystal NA Acceptors/cm3 Si Si Si B Si Si Free Majority Carrier Si p−Type Dopant (Acceptor) 2.1.3 Transport of Carriers Having studied charge carriers and the concept of doping, we are ready to examine the movement of charge in semiconductors, i.e., the mechanisms leading to the flow of current. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 28 (1) 28 Chap. 2 Basic Physics of Semiconductors Drift We know from basic physics and Ohm’s law that a material can conduct current in re- sponse to a potential difference and hence an electric field.4 The field accelerates the charge carriers in the material, forcing some to flow from one end to the other. Movement of charge carriers due to an electric field is called “drift.”5 Semiconductors behave in a similar manner. As shown in Fig. 2.8, the charge carriers are E Figure 2.8 Drift in a semiconductor. accelerated by the field and accidentally collide with the atoms in the crystal, eventually reaching the other end and flowing into the battery. The acceleration due to the field and the collision with the crystal counteract, leading to a constant velocity for the carriers.6 We expect the velocity, v, to be proportional to the electric field strength, E: v E; (2.13) and hence v = E; (2.14) where  is called the “mobility” and usually expressed in cm2=V  s. For example in silicon, the mobility of electrons, n = 1350 cm2=V  s, and that of holes, p = 480 cm2=V  s. Of course, since electrons move in a direction opposite to the electric field, we must express the velocity vector as v!e= ,n E! : (2.15) For holes, on the other hand, v!h= p E! : (2.16) Example 2.5 A uniform piece of n-type of silicon that is 1 m long senses a voltage of 1 V. Determine the velocity of the electrons. Solution Since the material is uniform, we have E = V=L, where L is the length. Thus, E = 10; 000 1V0/c7mcman=dsh=en7c:e4vps=tocnrEoss=th1e:315-m1le0n7gctmh./s. In other words, electrons take 1 m=1:35  V , R Edx V E to 4Recall distance: that ab the = potenatial b (voltage) . difference, , is equal to the negative integral of the electric field, , with respect 5The convention for direction of current assumes flow of positive charge from a positive voltage to a negative voltage. A B B A Thus, if electrons flow from point to point , the current is considered to have a direction from to . 6This phenomenon is analogous to the “terminal velocity” that a sky diver with a parachute (hopefully, open) experiences. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 29 (1) Sec. 2.1 Semiconductor Materials and Their Properties 29 Exercise What happens if the mobility is halved?  With the tron carries velocity of carriers known, a negative charge equal to q how is = 1:6 the10c,ur1r9enCt. calculated? We Equivalently, a first hole note that carries a an elecpositive cbhararhgaevoinfgthaefrseaemeelevcatrluoen.dNeonwsitsyuopfpnos(eFaigv. o2l.t9a)g.eAVss1uims ianpgptlhieedealeccrotrsosnas uniform semiconductor move with a velocity of v meters t = t1 L W h t = t1+ 1 s x1 x x1 x V1 V1 Figure 2.9 Current flow in terms of charge density. v t m/s, = t1 considering + 1 second, a cross section of the we note that the total bchararagtexin=vxm1 eatnedrstpakasinsegstwthoe “snapshots” at t cross section in = t1 and 1 second. In other words, the current is equal to the total charge enclosed in v meters of the bar’s length. Since the bar has a width of W , we have: I = ,v  W  h  n  q; (2.17) where v  W  h represents the volume, n  q denotes the charge density in coulombs, and the negative sign accounts for the fact that electrons carry negative charge. , Let us now reduce Eq. (2.17) to a more convenient form. Since for electrons, v = nE, and  since W h is the cross section area of the bar, we write Jn = nE  n  q; (2.18) awrheae,reanJdnisdeexnporteessstehdein“cAu=rrcemnt2.dWenesimtya,”y i.e., the loosely current passing say, “the current through is equal a to unit cross section the charge velocity times the charge density,” with the understanding that “current” in fact refers to current density, and negative or positive signs are taken into account properly. In the presence of both electrons and holes, Eq. (2.18) is modified to Jtot = nE  n  q + pE  p  q (2.19) = qnn + ppE: (2.20) This equation gives the drift current density in response to an electric field E in a semiconductor having uniform electron and hole densities. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 30 (1) 30 Chap. 2 Basic Physics of Semiconductors Example 2.6 In an experiment, it is desired to obtain equal electron and hole drift currents. How should the carrier densities be chosen? Solution We must impose nn = pp; (2.21) and hence We also recall that np = n2i . Thus, n p = p n : np==rrnpnpnnii: (2.22) (2.23) (2.24) For example, in silicon, n=p = 1350=480 = 2:81, yielding p = 1:68ni (2.25) n = 0:596ni: (2.26) Since p and n are of the same order as ni, equal electron and hole drift currents can occur for only a very semiconductors lightly having doped material. This typical doping levels ocfon1fi01rm5-s10o1u8raetaormliesr=cnmot3io. n of majority carriers in Exercise How should the carrier densities be chosen so that the electron drift current is twice the hole drift current? Velocity Saturation We have thus far assumed that the mobility of carriers in semicon- ductors is independent of the electric field and the velocity rises linearly with E according to v = E. In reality, if the electric field approaches sufficiently high levels, v no longer follows E linearly. This is because the carriers collide with the lattice so frequently and the time between the collisions is so short that they cannot accelerate much. As a result, v varies “sublinearly” at high electric fields, eventually reaching a saturated level, vsat (Fig. 2.10). Called “velocity saturation,” this effect manifests itself in some modern transistors, limiting the performance of circuits. In order to represent velocity saturation, we must modify v = E accordingly. A simple approach is to view the slope, , as a field-dependent parameter. The expression for  must This section can be skipped in a first reading. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 31 (1) Sec. 2.1 Semiconductor Materials and Their Properties 31 Velocity vsat µ2 µ1 E Figure 2.10 Velocity saturation. therefore gradually fall toward zero as E rises, but approach a constant value for small E; i.e.,  = 1 0 + bE ; (2.27) where 0 is the “low-field” mobility and b a proportionality factor. We may consider  as the “effective” mobility at an electric field E. Thus, v = 1 0 + bE E: (2.28) Since for E ! 1, v ! vsat, we have vsat = 0 b ; (2.29) and hence b = 0=vsat. In other words, v = 1 0 + 0E vsat E: (2.30) Example 2.7 A uniform piece of semiconductor 0.2 m long sustains a voltage of 1 V. If the low-field mobility is equal to 1350 cm2=V  s and the saturation velocity of the carriers 107 cm/s, determine the effective mobility. Also, calculate the maximum allowable voltage such that the effective mobility is only 10% lower than 0. Solution We have E = V L = 50 kV=cm: (2.31) (2.32) It follows that  = = 0 1+ 0 0E vsat 7:75 = 174 cm2=V  s: (2.33) (2.34) (2.35) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 32 (1) 32 Chap. 2 Basic Physics of Semiconductors If the mobility must remain within 10% of its low-field value, then 0:90 = 1 0 + 0E vsat ; (2.36) and hence E = 1 9 vsat 0 = 823 V=cm: (2.37) (2.38) 1A0d,e4vcicmeof=le1n6g:t5hm0.V2.m experiences such a field if it sustains a voltage of 823 V=cm0:2 This example suggests that modern (submicron) devices incur substantial velocity saturation because they operate with voltages much greater than 16.5 mV. Exercise At what voltage does the mobility fall by 20%? Diffusion In addition to drift, another mechanism can lead to current flow. Suppose a drop of ink falls into a glass of water. Introducing a high local concentration of ink molecules, the drop begins to “diffuse,” that is, the ink molecules tend to flow from a region of high concentration to regions of low concentration. This mechanism is called “diffusion.” A similar phenomenon occurs if charge carriers are “dropped” (injected) into a semiconductor so as to create a nonuniform density. Even in the absence of an electric field, the carriers move toward regions of low concentration, thereby carrying an electric current so long as the nonuniformity is sustained. Diffusion is therefore distinctly different from drift. Figure 2.11 conceptually illustrates the process of diffusion. A source on the left continues to inject charge carriers into the semiconductor, a nonuniform charge profile is created along the x-axis, and the carriers continue to “roll down” the profile. Injection of Carriers Semiconductor Material Figure 2.11 Diffusion in a semiconductor. Nonuniform Concentration The reader may raise several questions at this point. What serves as the source of carriers in Fig. 2.11? Where do the charge carriers go after they roll down to the end of the profile at the far right? And, most importantly, why should we care?! Well, patience is a virtue and we will answer these questions in the next section. Example 2.8 A source injects charge carriers into a semiconductor bar as shown in Fig. 2.12. Explain how the current flows. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 33 (1) Sec. 2.1 Semiconductor Materials and Their Properties 33 Injection of Carriers 0 x Figure 2.12 Injection of carriers into a semiconductor. Solution In this case, two symmetric profiles may develop in both positive and negative directions along the x-axis, leading to current flow from the source toward the two ends of the bar. Exercise Is KCL still satisfied at the point of injection? Our qualitative study of diffusion suggests that the more nonuniform the concentration, the larger the current. More specifically, we can write: I dn dx ; (2.39) where n denotes the carrier concentration at a given point along the x-axis. We call dn=dx the concentration “gradient” with respect to x, assuming current flow only in the x direction. If each carrier has a charge equal to q, and the semiconductor has a cross section area of A, Eq. (2.39) can be written as I Aq dn dx : (2.40) Thus, I = AqDn dn dx ; (2.41) ewxhaemreplDe,ninisinatprirnospiocrstiiloincoalni,tyDfnac=tor3c4acllmed2=thse(f“odrifefluescitornoncso)n, satnadntD” apn=d expressed 12 cm2=s in cm2=s. For (for holes). As with the convention used for the drift current, we normalize the diffusion current to the cross section area, obtaining the current density as Jn = qDn dn dx : (2.42) Similarly, a gradient in hole concentration yields: Jp = ,qDp dp dx : (2.43) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 34 (1) 34 Chap. 2 Basic Physics of Semiconductors With both electron and hole concentration gradients present, the total current density is given by Jtot = q Dn dn dx , Dp dp dx : (2.44) Example 2.9 Consider the scenario depicted in Fig. 2.11 again. Suppose the electron concentration is equal to N at x = 0 and falls linearly to zero at x = L (Fig. 2.13). Determine the diffusion current. N Injection 0 Figure 2.13 Current resulting from a linear diffusion profile. Lx Solution We have Jn = qDn dn dx (2.45) = ,qDn  N L : (2.46) The current is constant along the x-axis; i.e., all of the electrons entering the material at x = 0 successfully reach the point at x = L. While obvious, this observation prepares us for the next example. Exercise Repeat the above example for holes. Example 2.10 Repeat the above example but assume an exponential gradient (Fig. 2.14): N Injection 0 Figure 2.14 Current resulting from an exponential diffusion profile. Lx nx = N exp ,x Ld ; (2.47) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 35 (1) P N Sec. 2.2 Junction 35 where Ld is a constant.7 Solution We have Jn = qDn dn dx (2.48) = ,qDnN Ld exp ,x Ld : (2.49) Interestingly, the current is not constant along the x-axis. That is, some electrons vanish while traveling from x = 0 to the right. What happens to these electrons? Does this example violate the law of conservation of charge? These are important questions and will be answered in the next section. Exercise At what value of x does the current density drop to 1% its maximum value? Einstein Relation Our study of drift and diffusion has introduced a factor for each: n (or p) and Dn (or Dp), respectively. It can be proved that  and D are related as: D  = kT q : (2.50) Called the “Einstein Relation,” this result is proved in semiconductor physics texts, e.g., [1]. Note that kT=q  26 mV at T = 300 K. Figure 2.15 summarizes the charge transport mechanisms studied in this section. Drift Current E Diffusion Current Jn qn µn E Jp qp µp E Figure 2.15 Summary of drift and diffusion mechanisms. = = Jn = q Dn dn dx dp Jp q Dp dx −= 2.2 P N Junction We begin our study of semiconductor devices with the pn junction for three reasons. (1) The device finds application in many electronic systems, e.g., in adapters that charge the batteries of cellphones. (2) The pn junction is among the simplest semiconductor devices, thus providing a L 7The factor d is necessary to convert the exponent to a dimensionless quantity. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 36 (1) 36 Chap. 2 Basic Physics of Semiconductors good entry point into the study of the operation of such complex structures as transistors. (3) The pn junction also serves as part of transistors. We also use the term “diode” to refer to pn junctions. We have thus far seen that doping produces free electrons or holes in a semiconductor, and an electric field or a concentration gradient leads to the movement of these charge carriers. An interesting situation arises if we introduce n-type and p-type dopants into two adjacent sections of a piece of semiconductor. Depicted in Fig. 2.16 and called a “pn junction,” this structure plays a fundamental role in many semiconductor devices. The p and n sides are called the “anode” and n p Si Si Pe Si Si Figure 2.16 PN junction. Si Si B Si Si (a) Cathode Anode (b) the ”cathode,” respectively. In this section, we study the properties and I/V characteristics of pn junctions. The following outline shows our thought process, indicating that our objective is to develop circuit models that can be used in analysis and design. PN Junction in Equilibrium Depletion Region Built−in Potential PN Junction Under Reverse Bias Junction Capacitance PN Junction Under Forward Bias I/V Characteristics Figure 2.17 Outline of concepts to be studied. 2.2.1 P N Junction in Equilibrium Let us first study the pn junction with no external connections, i.e., the terminals are open and no voltage is applied across the device. We say the junction is in “equilibrium.” While seemingly of no practical value, this condition provides insights that prove useful in understanding the operation under nonequilibrium as well. We begin by examining the interface between the n and p sections, recognizing that one side contains a large excess of holes and the other, a large excess of electrons. The sharp concentration gradient for both electrons and holes across the junction leads to two large diffusion currents: electrons flow from the n side to the p side, and holes flow in the opposite direction. Since we must deal with both electron and hole concentrations on each side of the junction, we introduce the notations shown in Fig. 2.18. Example 2.11 A pn junction employs the following doping levels: NA = 1016 cm,3 and ND = 51015 cm,3. Determine the hole and electron concentrations on the two sides. Solution From Eqs. (2.11) and (2.12), we express the concentrations of holes and electrons on the p side BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 37 (1) P N Sec. 2.2 Junction 37 Figure 2.18 . Majority Carriers Minority Carriers n nn pn p pp np Majority Carriers Minority Carriers nn : Concentration of electrons on n side pn : Concentration of holes on n side pp : Concentration of holes on p side np : Concentration of electrons on p side respectively as: pp  NA = 1016 cm,3 np  n2i NA = 1:08  1010 cm,32 1016 cm,3  1:1  104 cm,3: Similarly, the concentrations on the n side are given by nn  ND = 5  1015 cm,3 pn  n2i ND = 1:08  1010 cm,32 5  1015 cm,3 = 2:3  104 cm,3: (2.51) (2.52) (2.53) (2.54) (2.55) (2.56) (2.57) (2.58) (2.59) (2.60) Note that the majority carrier concentration on each side is many orders of magnitude higher than the minority carrier concentration on either side. Exercise Repeat the above example if ND drops by a factor of four. The diffusion currents transport a great deal of charge from each side to the other, but they must eventually decay to zero. This is because, if the terminals are left open (equilibrium condition), the device cannot carry a net current indefinitely. We must now answer an important question: what stops the diffusion currents? We may postulate that the currents stop after enough free carriers have moved across the junction so as to equalize the concentrations on the two sides. However, another effect dominates the situation and stops the diffusion currents well before this point is reached. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 38 (1) 38 Chap. 2 Basic Physics of Semiconductors To understand this effect, we recognize that for every electron that departs from the n side, a positive ion is left behind, i.e., the junction evolves with time as conceptually shown in Fig. 2.19. In this illustration, the junction is suddenly formed at t = 0, and the diffusion currents continue to expose more ions as time progresses. Consequently, the immediate vicinity of the junction is depleted of free carriers and hence called the “depletion region.” t=0 n p −−−− ++++ −− − − − − −− − −− − − − + + + ++ + + + + ++ + + + − −− − −− − − − − −− − + + + + ++ + ++ + + + + −−−−−+++++ t = t1 n p −−− − − − −− − − − − −− − − − − −− − −− − −−−− + + + + + − − − − − +++ + + + ++ + + + + ++ + + + + ++ + ++ + ++++ Free Free Electrons Holes Positive Negative Donor Acceptor Ions Ions pn Figure 2.19 Evolution of charge concentrations in a junction. t= n p −−− − − − −− − −− − − −− − − − − −− −−− + + + + + + + + + + − − − − − − − − − − +++ + ++ + ++ + + + ++ + + + + ++ + +++ Depletion Region Now recall from basic physics that a particle or object carrying a net (nonzero) charge creates an electric field around it. Thus, with the formation of the depletion region, an electric field emerges as shown in Fig. 2.20.8 Interestingly, the field tends to force positive charge flow from pn Figure 2.20 Electric field in a junction. n E p −−− − − − −− − − − − − − − − −− − − − −−− + + + + + + + + + + − − − − − − − − − − +++ + ++ + + + + ++ + + + ++ + ++ + +++ left to right whereas the concentration gradients necessitate the flow of holes from right to left (and electrons from left to right). We therefore surmise that the junction reaches equilibrium once the electric field is strong enough to completely stop the diffusion currents. Alternatively, we can say, in equilibrium, the drift currents resulting from the electric field exactly cancel the diffusion currents due to the gradients. Example 2.12 In the junction shown in Fig. 2.21, the depletion region has a width of b on the n side and a on the p side. Sketch the electric field as a function of x. Solution Beginning at x ,b, we note that the absence of net charge yields E = 0. At x ,b, each positive donor ion contributes to the electric field, i.e., the magnitude of E rises as x approaches zero. As we pass x = 0, the negative acceptor atoms begin to contribute negatively to the field, i.e., E falls. At x = a, the negative and positive charge exactly cancel each other and E = 0. 8The direction of the electric field is determined by placing a small positive test charge in the region and watching how it moves: away from positive charge and toward negative charge. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 39 (1) P N Sec. 2.2 Junction 39 n E p −−− −−− − − − −N − − D − − − − −−− −−− + + + + + + + + + + − − − − − − − − − − +++ +++ + + + NA ++ + + + + +++ +++ −b 0 a x E −b 0 a x pn Figure 2.21 Electric field profile in a junction. Exercise Noting that potential voltage is negative integral of electric field with respect to distance, plot the potential as a function of x. From our observation regarding the drift and diffusion currents under equilibrium, we may be tempted to write: jIdrift;p + Idrift;nj = jIdi ;p + Idi ;nj; (2.61) where the subscripts p and n refer to holes and electrons, respectively, and each current term contains the proper polarity. This condition, however, allows an unrealistic phenomenon: if the number of the electrons flowing from the n side to the p side is equal to that of the holes going from the p side to the n side, then each side of this equation is zero while electrons continue to accumulate on the p side and holes on the n side. We must therefore impose the equilibrium condition on each carrier: jIdrift;pj = jIdi ;pj jIdrift;nj = jIdi ;nj: (2.62) (2.63) Built-in Potential The existence of an electric field within the depletion region suggests that the junction may exhibit a “built-in potential.” In fact, using (2.62) or (2.63), we can compute this potential. Since the electric field E = ,dV =dx, and since (2.62) can be written as qppE = qDp dp dx ; (2.64) we have ,pp dV dx = Dp dp dx : Dividing both sides by p and taking the integral, we obtain ,p Z x2 x1 dV = Dp Z pp pn dpp ; (2.65) (2.66) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 40 (1) 40 Chap. 2 Basic Physics of Semiconductors n nn pn p pp np x1 x2 x pn Figure 2.22 Carrier profiles in a junction. where pn and pp are the hole concentrations at x1 and x2, respectively (Fig. 2.22). Thus, V x2  , V x1 = , Dp p ln pp pn : (2.67) The right side represents the voltage difference developed across the depletion region and will be denoted by V0. Also, from Einstein’s relation, Eq. (2.50), we can replace Dp=p with kT =q: jV0j = kT q ln pp pn : (2.68) Exercise Writing Eq. (2.64) for electron drift and diffusion currents, and carrying out the integration, derive an equation for V0 in terms of nn and np. Finally, using (2.11) and (2.10) for pp and pn yields V0 = kT q ln NAND n2i : (2.69) Expressing the built-in potential in terms of junction parameters, this equation plays a central role in many semiconductor devices. Example 2.13 A silicon pn junction employs NA = built-in potential at room temperature 2  1016 cm,3 (T = 300 K). and ND = 4  1016 cm,3. Determine the Solution Recall from Example 2.1 that niT = 300 K = 1:08  1010 cm,3. Thus, V0  26 mV ln 2  1016  4  1016 1:08  10102 (2.70)  768 mV: (2.71) Exercise By what factor should ND be changed to lower V0 by 20 mV? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 41 (1) P N Sec. 2.2 Junction 41 Example 2.14 Equation change if (2.69) NA or NreDveaislsintchraetaVse0dibsyaowneeaokrdfeurnocftimonagonfittuhdee?doping levels. How much does V0 Solution We can write V0 = VT ln 10NA  n2i ND , VT ln NA  ND n2i (2.72) = VT ln 10 (2.73)  60 mV at T = 300 K: (2.74) Exercise How much does V0 change if NA or ND is increased by a factor of three? An interesting question may arise at this point. The junction carries no net current (because its terminals remain open), but it sustains a voltage. How is that possible? We observe that the builtin potential is developed to oppose the flow of diffusion currents (and is, in fact, sometimes called the “potential barrier.”). This phenomenon is in contrast to the behavior of a uniform conducting material, which exhibits no tendency for diffusion and hence no need to create a built-in voltage. 2.2.2 P N Junction Under Reverse Bias Having analyzed the pn junction in equilibrium, we can now study its behavior under more interesting and useful conditions. Let us begin by applying an external voltage across the device as shown in Fig. 2.23, where the voltage source makes the n side more positive than the p side. We say the junction is under “reverse bias” to emphasize the connection of the positive voltage to the n terminal. Used as a noun or a verb, the term “bias” indicates operation under some “desirable” conditions. We will study the concept of biasing extensively in this and following chapters. We wish to reexamine the results obtained in equilibrium for the case of reverse bias. Let uSsinficrestunddeeterremqiunielibwrhiuemth,eE!r thisedeixretecrtnedalfvroomltatghee enhances the built-in electric field or opposes it. n side to the p side, VR enhances the field. But, a higher electric field can be sustained only if a larger amount of fixed charge is provided, requiring that more acceptor and donor ions be exposed and, therefore, the depletion region be widened. What happens to the diffusion and drift currents? Since the external voltage has strengthened the field, the barrier rises even higher than that in equilibrium, thus prohibiting the flow of current. In other words, the junction carries a negligible current under reverse bias.9 With no current conduction, a reverse-biased pn junction does not seem particularly useful. However, an important observation will prove otherwise. We note that in Fig. 2.23, as VB increases, more positive charge appears on the n side and more negative charge on the p side. 9As explained in Section 2.2.3, the current is not exactly zero. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 42 (1) 42 Chap. 2 Basic Physics of Semiconductors n p − − − − −− − − − + + + + − − − − + + + ++ + ++ + − − − −− − − − − −−−−−− + + + + + + − − − − − − + ++ + + + + ++ ++++++ n p −−−− + + + − − − ++++ − − − − −− +++ +++ −−− −−− + + + ++ + − − − −− − +++ +++ −−− −−− + + + + ++ VR Figure 2.23 PN junction under reverse bias. Thus, the device operates as a capacitor [Fig. 2.24(a)]. In essence, we can view the conductive n and p sections as the two plates of the capacitor. We also assume the charge in the depletion region equivalently resides on each plate. n VR1 p −−−−−− + + − − ++++++ − −− − −− − − − + + + + − − − − + + + ++ + + + + −− − − − − −− − + + + + − − − − + + + + ++ + + + −−− +++ − + n VR2 p − −− − − − +++ +++ −−− −−− ++ + + + + −− − − − − −−−− +++ +++ +++ −−− −−− −−− + ++ + + + ++++ −− + −−− +++ VR1 (a) Figure 2.24 Reduction of junction capacitance with reverse bias. VR2 (more negative than VR1 ) (b) The reader may still not find the device interesting. After all, since any two parallel plates can form a capacitor, the use of a pn junction for this purpose is not justified. But, reverse-biased pn junctions exhibit a unique property that becomes useful in circuit design. Returning to Fig. 2.23, we recognize that, as VR increases, so does the width of the depletion region. That is, the conceptual diagram of Fig. 2.24(a) can be drawn as in Fig. 2.24(b) for increasing values of VR, revealing that the capacitance of the structure decreases as the two plates move away from each other. The junction therefore displays a voltage-dependent capacitance. It can be proved that the capacitance of the junction per unit area is equal to Cj = r1C,j0VVR0 ; (2.75) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 43 (1) P N Sec. 2.2 Junction 43 wpohteernetiCalj[0Edqe.n(2o.t6es9)t]h.e(TchapisaecqituaantcieoncoarsrseusmpoensdViRngistonezgearotivbeiafsor(VreRve=rse0b)iaans.d) TVh0eisvathlueeboufilCt-jin0 is in turn given by Cj0 r = siq 2 NAND NA + ND 1 V0 ; (2.76) where Plotted si in represents Fig. 2.25, the Cj dielectric constant of silicon and is indeed decreases as VR increases. equal to 11:7  8:85  10,14 F/cm.10 Cj 0 VR Figure 2.25 Junction capacitance under reverse bias. Example 2.15 A pn junction capacitance of is doped with NA the device with (a) = 2  1016 VR = 0 and cm,3 VR = and ND 1 V. = 9  1015 cm,3. Determine the Solution We first obtain the built-in potential: V0 = VT ln NAND n2i = 0:73 V: (2.77) (2.78) Thus, for VR = 0 and q = 1:6  10,19 C, we have Cj0 = r siq NAND 2 NA + ND  1 V0 = 2:65  10,8 F=cm2: (2.79) (2.80) In microelectronics, we deal with very small devices and may rewrite this result as Cj0 = 0:265 fF=m2; where 1 fF (femtofarad) = 10,15 F. For VR = 1 V, Cj = r1C+j0VVR0 = 0:172 fF=m2: (2.81) (2.82) (2.83) :  10The dielectric and a dimensionless constant of materials is factor (e.g., 11.7), and usually written in the form 0 the dielectric constant of r 0, where vacuum (8 r is 85 th1e0“,r1e4latFiv/cem” )d.ielectric constant BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 44 (1) 44 Chap. 2 Basic Physics of Semiconductors Exercise Repeat the above example if the donor concentration on the N side is doubled. Compare the results in the two cases. The variation of the capacitance with the applied voltage makes the device a “nonlinear” capacitor because it does not satisfy Q = CV . Nonetheless, as demonstrated by the following example, a voltage-dependent capacitor leads to interesting circuit topologies. Example 2.16 A cellphone incorporates a 2-GHz oscillator whose frequency is defined by the resonance fre- quency of an LC tank (Fig. 2.26). If the tank capacitance is realized as the pn junction of Example 2.15, calculate the change in the oscillation frequency while the reverse voltage goes from 0 to 2 V. Assume the circuit operates at 2 GHz at a reverse voltage of 0 V, and the junction area is 2000 m2. Oscillator C L VR Figure 2.26 Variable capacitor used to tune an oscillator. Solution , Recall from basic circuit theory that the capacitor are equal and opposite: jthLe!traensk=“resojnCat!erse”sif,t1h.eTihmupse, dthaencreessoonfatnhceeifnrdeuqcuteonrcaynids equal to fres = 1 2 pL1 C : (2.84) At VR = 0, Cj = 0:265 fF/m2, yielding a total device capacitance of Cj;totVR = 0 = 0:265 fF=m2  2000 m2 (2.85) = 530 fF: (2.86) Setting fres to 2 GHz, we obtain L = 11:9 nH: (2.87) If VR goes to 2 V, Cj;totVR = 2 V = r1C+j00:273  2000 m2 (2.88) = 274 fF: (2.89) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 45 (1) P N Sec. 2.2 Junction 45 Using this value along with L = 11:9 nH in Eq. (2.84), we have fresVR = 2 V = 2:79 GHz: (2.90) An oscillator whose frequency can be varied by an external voltage (VR in this case) is called a “voltage-controlled oscillator” and used extensively in cellphones, microprocessors, personal computers, etc. Exercise Some wireless systems operate at 5.2 GHz. Repeat the above example for this frequency, assuming the junction area is still 2000 m2 but the inductor value is scaled to reach 5.2 GHz. In summary, a reverse-biased pn junction carries a negligible current but exhibits a voltage- dependent capacitance. Note that we have tacitly developed a circuit model for the device under this condition: a simple capacitance whose value is given by Eq. (2.75). Another interesting application of reverse-biased diodes is in digital cameras (Chapter 1). If light of sufficient energy is applied to a pn junction, electrons are dislodged from their covalent bonds and hence electron-hole pairs are created. With a reverse bias, the electrons are attracted to the positive battery terminal and the holes to the negative battery terminal. As a result, a current flows through the diode that is proportional to the light intensity. We say the pn junction operates as a “photodiode.” 2.2.3 P N Junction Under Forward Bias Our objective in this section is to show that the pn junction carries a current if the p side is raised to a more positive voltage than the n side (Fig. 2.27). This condition is called “forward bias.” We also wish to compute the resulting current in terms of the applied voltage and the junction parameters, ultimately arriving at a circuit model. n −−−−−−− − − − − −− − −− − + + + − − − −− − − − − −− + + p − − − +++++++ + + + + ++ + ++ + − − + + + ++ + + + + ++ VF Figure 2.27 PN junction under forward bias. From our study of the device in equilibrium and reverse bias, we note that the potential barrier developed in the depletion region determines the device’s desire to conduct. In forward bias, the external voltage, VF , tends to create a field directed from the p side toward the n side—opposite to the built-in field that was developed to stop the diffusion currents. We therefore surmise that VF in fact lowers the potential barrier by weakening the field, thus allowing greater diffusion currents. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 46 (1) 46 Chap. 2 Basic Physics of Semiconductors To derive the I/V characteristic in forward bias, we begin with Eq. (2.68) for the built-in voltage and rewrite it as pn;e = pp;e exp V0 VT ; (2.91) where the subscript e emphasizes equilibrium conditions [Fig. 2.28(a)] and VT = kT =q is called n nn,e pn,e p pp,e np,e n nn,f pn,f pn,e p pp,f np,f np,f VF (a) (b) Figure 2.28 Carrier profiles (a) in equilibrium and (b) under forward bias. the “thermal voltage” ( 26 mV at T = 300 K). In forward bias, the potential barrier is lowered by an amount equal to the applied voltage: pn;f = exp Vpp0;f, VF VT : (2.92) where the subscript f denotes forward bias. Since the exponential denominator drops consider- ably, we In other expect words, pn;f to be much higher than pn;e the minority carrier concentration (it on can the pbesipdreovriesdesthraatpipdpl;yf  pp;e with the  NA). forward bias voltage while the majority carrier concentration remains relatively constant. This statement applies to the n side as well. Figure 2.28(b) illustrates the results of our analysis thus far. As the junction goes from equi- ldiibfrfiuusmiontocfuorrrwenatrsd.1b1iaWs,encpananedxpprnesisncthreeacsheadnrgaemiantitchaellhyo, lleeacdoinncgetnotraatpioronpoonrttihoenanl change in side as: the pn = pn;f , pn;e = exp Vpp0;f, VF VT , pp;e exp V0 VT  NA exp V0 VT exp VF VT , 1: Similarly, for the electron concentration on the p side: (2.93) (2.94) (2.95) np  ND exp V0 VT exp VF VT , 1: (2.96) 11The width of the depletion region actually decreases in forward bias but we neglect this effect here. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 47 (1) P N Sec. 2.2 Junction 47 Note that Eq. (2.69) indicates that expV0=VT  = NAND=n2i . The increase in the minority carrier concentration suggests that the diffusion currents must rise by a proportional amount above their equilibrium value, i.e., Itot NA exp V0 VT exp VF VT , 1 + ND exp V0 VT exp VF VT , 1: (2.97) Indeed, it can be proved that [1] Itot = ISexp VF VT , 1; where IS is called the “reverse saturation current” and given by (2.98) IS = Aqn2i  Dn NALn + Dp NDLp : (2.99) In this equation, A is the cross section area of the device, and Ln and Lp are electron and hole “diffusion lengths,” respectively. Diffusion lengths are typically in the range of tens of microm- eters. Note that the first and second terms in the parentheses correspond to the flow of electrons and holes, respectively. Example 2.17 aDnedteLrmp i=ne3I0Sfmor. the junction of Example 2.13 at T = 300K if A = 100 m2, Ln = 20 m, Solution Using q = 1:6  10,19 C, Dp = 12 cm2=s, we have ni = 1:08  1010 electrons=cm3 [Eq. (2.2)], Dn = 34 cm2=s, and IS = 1:77  10,17 A: (2.100) aSsintcoeyIiSeldisaexutsreefmulealymsomunaltl(,eth.ge.,e1xpmoAne)nftoiarlItteortm. in Eq. (2.98) must assume very large values so Exercise What junction area is necessary to raise IS to 10,15 A. An interesting question that arises here is: are the minority carrier concentrations constant along the x-axis? Depicted in Fig. 2.29(a), such a scenario would suggest that electrons continue to flow from the n side to the p side, but exhibit no tendency to go beyond x = x2 because of the lack of a gradient. A similar situation exists for holes, implying that the charge carriers do not flow deep into the p and n sides and hence no net current results! Thus, the minority carrier concentrations must vary as shown in Fig. 2.29(b) so that diffusion can occur. This observation reminds us of Example 2.10 and the question raised in conjunction with it: if the minority carrier concentration falls with x, what happens to the carriers and how can the current remain constant along the x-axis? Interestingly, as the electrons enter the p side and roll down the gradient, they gradually recombine with the holes, which are abundant in this region. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 48 (1) 48 Chap. 2 Basic Physics of Semiconductors Electron Flow n nn,f −− ++ pn,f + + −− Hole Flow p pp,f np,f x1 x2 x Electron Flow n Hole Flow p nn,f −− ++ pp,f + pn,f+ + + + − − − − np,f − x1 x2 x VF VF (a) (b) Figure 2.29 (a) Constant and (b) variable majority carrier profiles ioutside the depletion region. Similarly, the holes entering the n side recombine with the electrons. Thus, in the immediate vicinity of the depletion region, the current consists of mostly minority carriers, but towards the far contacts, it is primarily comprised of majority carriers (Fig. 2.30). At each point along the x-axis, the two components add up to Itot. n p − − − − − − − − − + + + + + + + + + + − − − − − − − − − − + + + + + + + + + + − x VF Figure 2.30 Minority and majority carrier currents. 2.2.4 I/V Characteristics Let us summarize our thoughts thus far. In forward bias, the external voltage opposes the built-in potential, raising the diffusion currents substantially. In reverse bias, on the other hand, the applied voltage enhances the field, prohibiting current flow. We hereafter write the junction equation as: ID = ISexp VD VT , 1; (2.101) where ID and VD denote the diode current and voltage, respectively. As expected, VD = 0 yields tIeDrm=g0ro. (wWs hraypiisdtlhyisaenxdpIeDcted?)ISAesxVpDVbDec=oVmTes. positive and exceeds several VT , the We hereafter assume expVD=VT  exponential 1 in the forward bias region. It can and jVDj be proved that Eq. reaches several VT (2.101) also holds in , then expVD=VT  reverse 1 and bias, i.e., for negative VD . If VD 0 ID  ,IS: (2.102) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 49 (1) P N Sec. 2.2 Junction 49 F“riegvuerrese2.s3a1tupralotitosnthceurorevnetr.a”lEl xI/aVmcphlear2a.c1t7eriinsdtiiccaotfesththeajtuInSctiisotny,priecvaellaylivnegrywshmyaIllS. is called the We therefore Reverse Bias Forward Bias ID I S exp VD VT −IS VD pn Figure 2.31 I-V characteristic of a junction. view the current under reverse bias as “leakage.” Note that IS and hence the junction current are proportional to the device cross section area [Eq. (2.99)]. For example, two identical devices placed in parallel (Fig. 2.32) behave as a single junction with twice the IS. A 2A n p n p A VF Figure 2.32 Equivalence of parallel devices to a larger device. n p VF Example 2.18 Each junction in Fig. 2.32 employs the doping levels described in Example 2.13. Determine the forward bias current of the composite device for VD = 300 mV and 800 mV at T = 300 K. Solution From Example 2.17, IS = 1:77  10,17 A for each junction. Thus, the total current is equal to ID;totVD = 300 mV = 2IS exp VD VT , 1 = 3:63 pA: (2.103) (2.104) Similarly, for VD = 800 mV: ID;totVD = 800 mV = 82 A: (2.105) Exercise How many of these diodes must be placed in parallel to obtain a current of 100 A with a BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 50 (1) 50 voltage of 750 mV. Chap. 2 Basic Physics of Semiconductors Example 2.19 A diode operates in the forward bias region with a typical current level [i.e., ImDuchchIaSngexepinVVDD=VisTre]q.uSiruepdp?ose we wish to increase the current by a factor of 10. How Solution Let us first express the diode voltage as a function of its current: VD = VT ln ID IS : We define I1 = 10ID and seek the corresponding voltage, VD1: VD1 = VT ln 10ID IS = VT ln ID IS + VT ln 10 = VD + VT ln 10: (2.106) (2.107) (2.108) (2.109) Thus, the diode voltage increase in the current. must rise by We say the dVeTvilcne1e0xhib6i0tsmaV60(a-mt TV/=de3c0ad0eKc)htaoraacccteormismtico,dmateeaanitnengfVolDd changes by 60 mV for a decade (tenfold) change in ID. More generally, an n-fold change in ID translates to a change of VT ln n in VD. Exercise By what factor does the current change if the voltages changes by 120 mV? Example 2.20 The cross section area of a diode operating in the forward bias region is increased by a factor of 10. VD (a) Determine the change in if ID is maintained constant. ID if VD is Assume ID maintained constant.  IS expVD=VT . (b) Determine the change in Solution (a) Since IS A, the new current is given by ID1 = 10IS exp VD VT = 10ID: (2.110) (2.111) (b) From the above example, VD1 = VT ln ID 10IS = VT ln ID IS , VT ln 10: (2.112) (2.113) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 51 (1) P N Sec. 2.2 Junction 51 Thus, a tenfold increase in the device area lowers the voltage by 60 mV if ID remains constant. Exercise A diode in forward bias with ID  IS expVD=VT  undergoes two simultaneous changes: the current is raised by a factor of m and the area is increased by a factor of n. Determine the change in the device voltage. Constant-Voltage Model The exponential I/V characteristic of the diode results in nonlinear equations, making the analysis of circuits quite difficult. Fortunately, the above examples imply that the diode voltage is a relatively weak function of the device current and cross section area. With typical current levels and areas, VD falls in the range of 700 - 800 mV. For this reason, we often approximate the forward bias voltage by a constant value of 800 mV (like an ideal battery), tc2eo.n3nd3ss(iadt)eorweinxitgchethethdeedVteDuvr;inocn-eobfnuevlcloayultosafegfewifdeVeaDnsostuemd8e0b0ythmeVDVfo.;orTwnh.aeNrdroe-btseuialtsthienadtgdtchihoeadcreaucorrtpeeernirtsatgtiecoseisassitloalunisnitdfiraentaietldyvioansltFaViggDe. source. Neglecting the leakage current in reverse bias, we derive the circuit model shown in Fig. 2.33(b). We say the junction operates as an open circuit if VD VD;on and as a constant voltage source if we attempt to increase VD beyond VD;on. While not essential, the voltage source placed in series with the switch in the off condition helps simplify the analysis of circuits: we can say that in the transition from off to on, only the switch turns on and the battery always resides in series with the switch. ID VD,on VD (a) Figure 2.33 Constant-voltage diode model. Reverse Bias Forward Bias (b) VD,on VD,on A number of questions may cross the reader’s mind at this point. First, why do we subject the diode to such a seemingly inaccurate approximation? Second, if we indeed intend to use this simple approximation, why did we study the physics of semiconductors and pn junctions in such detail? The developments in this chapter are representative of our treatment of all semiconductor de- vices: we carefully analyze the structure and physics of the device to understand its operation; we construct a “physics-based” circuit model; and we seek to approximate the resulting model, thus arriving at progressively simpler representations. Device models having different levels of complexity (and, inevitably, different levels of accuracy) prove essential to the analysis and design of circuits. Simple models allow a quick, intuitive understanding of the operation of a complex circuit, while more accurate models reveal the true performance. Example 2.21 Consider the circuit of exponential model with IFSig=. 21.304,.16CAalcaunldat(eb)IXa for VX = 3 V constant-voltage and VX = 1 V using (a) an model with VD;on = 800 mV. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 52 (1) 52 Chap. 2 Basic Physics of Semiconductors IX R1= 1 kΩ VX D1 VD Figure 2.34 Simple circuit using a diode. Solution (a) Noting that ID = IX , we have VX = IXR1 + VD VD = VT ln IIXS : (2.114) (2.115) This equation must IX from IXR1 = be solved VX , VD by iteration: we guess a value for , determine the new value of VD VD, compute the corresponding from VD = VT lnIX=IS and iterate. Let us guess VD = 750 mV and hence IX = VX , VD R1 = 3 V , 0:75 1k V = 2:25 mA: (2.116) (2.117) (2.118) Thus, VD = VT ln IX IS = 799 mV: (2.119) (2.120) With this new value of VD, we can obtain a more accurate value for IX : IX = 3 V , 1 0:799 V k = 2:201 mA: (2.121) (2.122) We note that the value of IX rapidly converges. Following the same procedure for VX = 1 V, we have IX = 1 V , 0:75 1k V = 0:25 mA; (2.123) (2.124) which yields VD = 0:742 V and hence IX = 0:258 mA. (b) A constant-voltage model readily gives IX = 2:2 mA for VX = 3 V IX = 0:2 mA for VX = 1 V: (2.125) (2.126) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 53 (1) Sec. 2.3 Reverse Breakdown 53 The value of IX incurs some error, but it is obtained with much less computational effort than that in part (a). Exercise Repeat the above example if the cross section area of the diode is increased by a factor of 10. 2.3 Reverse Breakdown Recall from Fig. 2.31 that the pn junction carries only a small, relatively constant current in re- verse bias. However, as the reverse voltage across the device increases, eventually “breakdown” occurs and a sudden, enormous current is observed. Figure 2.35 plots the device I/V characteristic, displaying this effect. ID VBD VD Breakdown Figure 2.35 Reverse breakdown characteristic. The breakdown resulting from a high voltage (and hence a high electric field) can occur in any material. A common example is lightning, in which case the electric field in the air reaches such a high level as to ionize the oxygen molecules, thus lowering the resistance of the air and creating a tremendous current. The breakdown phenomenon in pn junctions occurs by one of two possible mechanisms: “Zener effect” and “avalanche effect.” 2.3.1 Zener Breakdown The depletion region in a pn junction contains atoms that have lost an electron or a hole and, therefore, provide no loosely-connected carriers. However, a high electric field in this region may impart enough energy to the remaining covalent electrons to tear them from their bonds [Fig. 2.36(a)]. Once freed, the electrons are accelerated by the field and swept to the n side of the junction. This effect occurs at a field strength of about 106 V/cm (1 V/m). In order to create such high fields with reasonable voltages, a narrow depletion region is required, which from Eq. (2.76) translates to high doping levels on both sides of the junction (why?). Called the “Zener effect,” this type of breakdown appears for reverse bias voltages on the order of 3-8 V. This section can be skipped in a first reading. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 54 (1) 54 n E p Si Si Si Si Si e e Si e Si e Si Si Si Chap. 2 Basic Physics of Semiconductors n E p e e e e e e e e e VR VR (a) (b) Figure 2.36 (a) Release of electrons due to high electric field, (b) avalanche effect. 2.3.2 Avalanche Breakdown Junctions with moderate or low doping levels ( 1015 cm3) generally exhibit no Zener break- down. But, as the reverse bias voltage across such devices increases, an avalanche effect takes place. Even though the leakage current is very small, each carrier entering the depletion region experiences a very high electric field and hence a large acceleration, thus gaining enough energy to break the electrons from their covalent bonds. Called “impact ionization,” this phenomenon can lead to avalanche: each electron freed by the impact may itself speed up so much in the field as to collide with another atom with sufficient energy, thereby freeing one more covalent-bond electron. Now, these two electrons may again acquire energy and cause more ionizing collisions, rapidly raising the number of free carriers. An interesting contrast between Zener and avalanche phenomena is that they display opposite  temperature coefficients (TCs): VBD avalanche effect. The two TCs cancel has a negative TC each other for VBD for Zener effect 3:5 V. For this and positive TC for reason, Zener diodes with 3.5-V rating find application in some voltage regulators. The Zener and avalanche breakdown effects do not damage the diodes if the resulting cur- rent remains below a certain limit given by the doping levels and the geometry of the junction. Both the breakdown voltage and the maximum allowable reverse current are specified by diode manufacturers. 2.4 Chapter Summary Silicon contains four atoms in its last orbital. It also contains a small number of free electrons at room temperature. When an electron is freed from a covalent bond, a “hole” is left behind. The bandgap energy is the minimum energy required to dislodge an electron from its covalent bond. To increase the number of free carriers, semiconductors are “doped” with certain impuri- ties. For example, addition of phosphorous to silicon increases the number of free electrons because phosphorous contains five electrons in its last orbital. For doped or undoped semiconductors, n  ND and hence p  n2i =ND. np = n2i . For example, in an n-type material, Charge carriers move in semiconductors via two mechanisms: drift and diffusion. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 55 (1) Sec. 2.4 Chapter Summary 55 The drift current density is proportional to the electric field and the mobility of the carriers and is given by Jtot = qnn + ppE. The diffusion current density is proportional to the gradient of the carrier concentration and given by Jtot = qDndn=dx , Dpdp=dx. A pn junction is a piece of semiconductor that receives n-type doping in one section and p-type doping in an adjacent section. The pn junction can be considered in three modes: equilibrium, reverse bias, and forward bias. Upon formation of the pn junction, sharp gradients of carrier densities across the junction result in a high current of electrons and holes. As the carriers cross, they leave ionized atoms behind, and a “depletion resgion” is formed. The electric field created in the depletion region eventually stops the current flow. This condition is called equilibrium. The electric field in the depletion results in a built-in potential across the region equal to kT=q lnNAND=n2i , typically in the range of 700 to 800 mV. Under reverse bias, the junction carries negligible current and operates as a capacitor. The capacitance itself is a function of the voltage applied across the device. Under forward bias, the junction carries a current that is an exponential function of the applie voltage: IS expVF =VT  , 1 . Since the exponential model often makes the analysis of circuits difficult, a constantvoltage model may be used in some cases to estimate the circuit’s response with less mathematical labor. Under a high reverse bias voltage, pn junctions break down, conducting a very high cur- rent. Depending on the structure and doping levels of the device, “Zener” or “avalanche” breakdown may occur. Problems 1. The intrinsic carrier concentration of germanium (GE) is expressed as ni = 1:66  1015T 3=2 exp ,Eg 2kT cm,3; (2.127) where Eg = 0:66 eV. (a) Calculate ni at 300 K and 600 K and compare the results with those obtained in Example 2.1 for Si. (b) 5 D10et1e6rmcmin,e3t.he electron and hole concentrations if Ge is doped with P at a density of 2. An n-type piece of silicon experiences an electric field equal to 0.1 V/m. (a) Calculate the velocity of electrons and holes in this material. (b) What doping level is necessary to provide a current density of 1 mA/m2 under these conditions? Assume the hole current is negligible. 3. A n-type piece of silicon with a length of 0:1 m and a cross section area of 0:05 m0:05 m sustains a (a) If the doping level is 1017 vcomlt,ag3,ecdailfcfuerlaetnecethoeft1otVal. current flowing through the device at T = 300 K. (b) Repeat (a) for T = 400 K assuming for simplicity that mobility does not change with temperature. (This is not a good assumption.) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 56 (1) 56 Chap. 2 Basic Physics of Semiconductors 4. From the data in Problem p = 1900 cm2=V  s. 1, repeat Problem 3 for Ge. Assume n = 3900 cm2=V  s and 5. Figure 2.37 shows a p-type bar of silicon that is subjected to electron injection from the left Electrons 5 x 1016 2 x 1016 Holes Figure 2.37 0 2 µm x and hole injection from the right. Determine the total current flowing through the device if the cross section area is equal to 1 m  1 m. 6. In Example 2.9, compute the total number of electrons “stored” in the material from x = 0 to x = L. Assume the cross section area of the bar is equal to a. 1 7. Repeat Problem 6 for Example 2.10 but for x = 0 to x = . Compare the results for linear and exponential profiles. 8. Repeat Problem 7 if the electron and hole profiles are “sharp” exponentials, i.e., they fall to negligible values at x = 2 m and x = 0, respectively (Fig. 2.38). 5 x 1016 2 x 1016 Electrons Holes Figure 2.38 0 2 µm x 9. How do you explain the phenomenon of drift to a high school student? 10. A junction employs ND = 5  1017 cm,3 and NA = 4  1016 cm,3 . (a) Determine the majority and minority carrier concentrations on both sides. (b) Calculate the built-in potential at T = 250 K, 300 K, and 350 K. Explain the trend. 11. Due to a 3  1016 cmma,n3u,faccatlucurilnagteetrhreorb,utihlte-inp-psoidteenotifalaapt nT junction has = 300 K. not been doped. If ND = 12. A pn junction with ND = 3  1016 cm,3 and NA = 2  1015 cm,3 experiences a reverse bias voltage of 1.6 V. (a) Determine the junction capacitance per unit area. (b) By what factor should NA be increased to double the junction capacitance? 13. An oscillator application requires a variable capacitance with the characteristic shown in Fig. 2.39. Determine the required ND if NA = 1017/cm2. 14. Consider a pn junction in forward bias. (a) To obtain a current of 1 mA with a voltage of 750 mV, how should IS be chosen? (b) If the diode cross section area is now doubled, what voltage yields a current of 1 mA? 15. Figure 2.40 shows two diodes with reverse saturation currents of IS1 and IS2 placed in paral- lel. (a) Prove that the parallel combination operates as an exponential device. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 57 (1) Sec. 2.4 Chapter Summary 57 Cj (fF/µ m2 ) Figure 2.39 −1.5 −0.5 2.2 1.3 0 VR (V) I tot VB D1 D2 Figure 2.40 (b) If the total current is Itot, determine the current carried by each diode. 16. Two identical pn junctions are placed in series. (a) Prove that this combination can be viewed as a single two-terminal device having an exponential characteristic. (b) For a tenfold change in the current, how much voltage change does such a device require? 17. Figure 2.41 shows two diodes with reverse saturation currents of IS1 and IS2 placed in series. D1 D1 IB VD1 VD2 VB Figure 2.41 Calculate IB, VD1, and VD2 in terms of VB, IS1, and IS2. 18. In the circuit of change in VB? Problem 17, we wish to increase IB by a factor of 10. What is the required 19. Consider the circuit shown in Fig. 2.42, where IS = 2  10,15 A. Calculate VD1 and IX for IX R1 2 kΩ VX D1 Figure 2.42 VX = 0:5 V, 0.8 V, 1 V, and 1.2 V. Note that VD1 changes little for VX  0:8 V. 20. In the circuit VD1 and IX of Fig. for VX 2=.420,:8thVe carnodss1s.e2cVtio. nCaormeapaorfeDth1eisreinsuclrtesawseidthbtyhaosfaecotobrtaoifn1ed0.iDn ePtreorbmleinme 19. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 58 (1) 58 Chap. 2 Basic Physics of Semiconductors 21. Suppose required IDS1. in Fig. 2.42 must sustain a voltage of 850 mV for VX = 2 V. Calculate the 22. For 2 w10h,at16vaAlu. e of VX in Fig. 2.42, does R1 sustain a voltage equal to VX =2? Assume IS = 23. We have received the circuit shown in Fig. 2.43 and wish to determine R1 and IS. We note IX R1 VX D1 Figure 2.43 that VX = 1 V ! IX = 0:2 mA and VX = 2 V ! IX = 0:5 mA. Calculate R1 and IS. 24. Figure 2.44 depicts a parallel resistor-diode combination. If for IX = 1 mA, 2 mA, and 4 mA. IS = 3  10,16 A, calculate VD1 IX R1 1 kΩ D1 Figure 2.44 25. In the circuit of Fig. 2.44, Determine the required IS. we wish D1 to carry a current of 0.5 mA for IX = 1:3 mA. 26. For 3 w10h,a1t 6vAal.ue of IX in Fig. 2.44, does R1 carry a current equal to IX =2? Assume IS = 27. We have received the circuit shown in Fig. 2.45 and wish to determine R1 and IS. Measure- I X VX R 1 D1 Figure 2.45 ments indicate R1 and IS. that IX = 1 mA ! VX = 1:2 V and IX = 2 mA ! VX = 1:8 V. Calculate 28. The circuit illustrated in Fig. 2.46 employs two identical diodes with IS = 5  10,16 A. D1 IX R1 2 kΩ D2 Figure 2.46 Calculate the voltage across R1 for IX = 2 mA. 29. In the circuit of Fig. 2.47, determine the value of R1 such that this resistor carries 0.5 mA. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 59 (1) Sec. 2.4 Chapter Summary 59 D1 I X 1 mA R 1 D2 Figure 2.47 Assume IS = 5  10,16 A for each diode. 30. Sketch VX as a function of IX for the circuit shown in Fig. 2.48. Assume (a) a constant- voltage model, (b) an exponential model. I X VX R 1 D1 Figure 2.48 SPICE Problems In the following problems, assume IS = 5  10,16 A. 31. For the circuit shown in Fig. 2.49, plot Vout as a function of Iin. Assume Iin varies from 0 to 2mA. I in D1 Vout Figure 2.49 32. Repeat Iin are Problem 31 the currents for the circuit depicted in Fig. 2.50, flowing through D1 and R1 equal? where R1 = 1k . At what value of I in D1 R1 Vout Figure 2.50 33. Using SPICE, determine the value of R1 in Fig. 2.50 such that D1 carries 1 mA if Iin = 2 mA. 34. In V ttohe+c2irVcu. iAt towf Fhiagt.v2a.l5u1e,oRf 1Vi=n 500 . are the vPololttagVeoudtroaps saafcurnocstsioRn1oafnVdinDi1f Vin varies equal? from ,2 R1 Vout Vin D1 Figure 2.51 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 60 (1) 60 Chap. 2 Basic Physics of Semiconductors 35. In the Vin circuit of Fig. 2.51, use SPICE to select the 2 V. We say the circuit “limits” the output. value of R1 such that Vout 0:7 V for References 1. B. Streetman and S. Banerjee, Solid-State Electronic Device, fifth edition, Prentice-Hall, 1999. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 61 (1) 3 Diode Models and Circuits Having studied the physics of diodes in Chapter 2, we now rise to the next level of abstraction and deal with diodes as circuit elements, ultimately arriving at interesting and real-life applications. This chapter also prepares us for understanding transistors as circuit elements in subsequent chapters. We proceed as follows: Diodes as Circuit Elements Ideal Diode Circuit Characteristics Actual Diode Applications Regulators Rectifiers Limiting and Clamping Circuits 3.1 Ideal Diode 3.1.1 Initial Thoughts In order to appreciate the need for diodes, let us briefly study the design of a cellphone charger. The charger converts the line ac voltage at 110 V1 and 60 Hz2 to a dc voltage of 3.5 V. As shown in Fig. 3.1(a), this is accomplished by first stepping down the ac voltage by means of a transformer to about 4 V and subsequently converting the ac voltage to a dc quantity.3 The same principle applies to adaptors that power other electronic devices. How does the black box in Fig. 3.1(a) perform this conversion? As depicted in Fig. 3.1(b), the output of the transformer exhibits a zero dc content because the negative and positive half cycles enclose equal areas, leading to a zero average. Now suppose this waveform is applied to a mysterious device that passes the positive half cycles but blocks the negative ones. The result displays a positive average and some ac components, which can be removed by a low-pass filter (Section 3.5.1). The waveform conversion in Fig. 3.1(b) points to the need for a device that discriminates between positive and negative voltages, passing only one and blocking the other. A simple resistor cannot serve in this role because it is linear. That is, Ohm’s law, V = IR, implies that if the voltage across a resistor goes from positive to negative, so does the current through it. We must p 1This value refers to the root-mean-square (rms) voltage. The peak value is therefore equal to 110 2. 2The line ac voltage in most countries is at 220 V and 50 Hz. 3The actual operation of adaptors is somewhat different. 61 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 62 (1) 62 Chap. 3 Diode Models and Circuits Vline 60 Hz 110 2 t V1 60 Hz 42 t V1 Block Box Vout 3.5 V t (a) V1 42 ? Equal Positive and Negative Areas t t Positive Areas (b) Figure 3.1 (a) Charger circuit, (b) elimination of negative half cycles. therefore seek a device that behaves as a short for positive voltages and as an open for negative voltages. Figure 3.2 summarizes the result of our thought process thus far. The mysterious device generates an output equal to the input for positive half cycles and equal to zero for negative half cycles. Note that the device is nonlinear because it does not satisfy y = x; if x ! ,x, y 6! ,y. y (t ) t x (t ) t Figure 3.2 Conceptual operation of a diode. 3.1.2 Ideal Diode The mysterious device mentioned above is called an “ideal diode.” Shown in Fig. 3.3(a), the diode is a two-terminal device, with the triangular head denoting the allowable direction of current flow and the vertical bar representing the blocking behavior for currents in the opposite direction. The corresponding terminals are called the “anode” and the “cathode,” respectively. Forward and Reverse Bias To serve as the mysterious device in the charger example of Fig. 3.3(a), the diode must turn “on” if Vanode Vcathode and “off” if Vanode Vcathode [Fig. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 63 (1) Sec. 3.1 Ideal Diode 63 D1 Anode Cathode Forward Bias IX Reverse Bias (a) Pipe Hinge Forward Bias (b) Reverse Bias Valve Stopper (c) Figure 3.3 (a) Diode symbol, (b) equivalent circuit, (c) water pipe analogy. 3.3(b)]. Defining Vanode , Vcathode exceed zero and “reverse-biased” if = VD VD0, .w4e say the diode is “forward-biased” if VD tends to A water pipe analogy proves useful here. Consider the pipe shown in Fig. 3.3(c), where a valve (a plate) is hinged on the top and faces a stopper on the bottom. If water pressure is applied from the left, the valve rises, allowing a current. On the other hand, if water pressure is applied from the right, the stopper keeps the valve shut. Example 3.1 As with other two-terminal devices, diodes can be placed in series (or in parallel). Determine which one of the configurations in Fig. 3.4 can conduct current. D1 D2 A C B D1 D2 A C B D1 D2 A C B (a) (b) (c) Figure 3.4 Series combinations of diodes. Solution fItonroFAmi,gA.an3td.o4(DBa)2,t,otfhrCeomabnuoBtdnetosotoCifn.DtTh1ehaurnsed,venDros2ecpudorirrienenct tttioocanthn.eIflnsoaFwmigei.nd3ie.r4iet(chbte)iro, nDd,i1raelscltotoiwopnisn.cgButryhreethnfletoflwsoawmofefcrtuoormkreeBnnt, the topology of Fig. 3.4(c) behaves as an open for any voltage. Of course, none of these circuits appears particularly useful at this point, but they help us become comfortable with diodes. Exercise Determine all possible series combinations of three diodes and study their conduction properties. 4In our drawings, we sometimes place more positive nodes higher to provide a visual picture of the circuit’s operation. The diodes in Fig. 3.3(b) are drawn according to this convention. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 64 (1) 64 Chap. 3 Diode Models and Circuits I/V Characteristics In studying electronic devices, it is often helpful to accompany equations with graphical visualizations. A common type of plot is that of the current/voltage (I/V) characteristic, i.e., the current that flows through the device as a function of the voltage across it. Since an ideal diode behaves as a short or an open, we first construct the I/V characteristics for two special cases of Ohm’s law: R = 0  I = V R = 1 (3.1) R = 1  I = V R = 0: (3.2) The results are illustrated in Fig. 3.5(a). For an ideal diode, we combine the positive-voltage , region of teristic in the first with the negative-voltage Fig. 3.5(b). Here, VD = Vanode region of the second, Vcathode, and ID is arriving defined at as the the ID=VD current characflowing into the anode and out of the cathode. ID I R= 0 I R= Reverse Bias Forward Bias V V VD (a) (b) Figure 3.5 I/V characteristics of (a) zero and infinite resistors, (b) ideal diode. Example 3.2 We said that an ideal diode turns on for positive anode-cathode voltages. But the characteristic in Fig. 3.5(b) does not appear to show any ID values for VD 0. How do we interpret this plot? Solution This characteristic indicates that as VD exceeds zero by a very small amount, then the diode turns on and conducts infinite current if the circuit surrounding the diode can provide such a current. Thus, in circuits containing only finite currents, a forward-biased ideal diode sustains a zero voltage—similar to a short circuit. Exercise How is the characteristic modified if we place a 1- resistor in series with the diode? Example 3.3 Plot the I/V characteristic for the “antiparallel” diodes shown in Fig. 3.6(a). Solution If VA leading to0,IAD1=is1o.nTahnedrDes2ulitsisofifll,uysiteraldteindginIAFig=. 1. If VA 3.6(b). The 0, D1 is off, but D2 is antiparallel combination on, again therefore acts as a short for all voltages. Seemingly a useless circuit, this topology becomes much more interesting with actual diodes (Section 3.5.3). BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 65 (1) Sec. 3.1 Ideal Diode 65 IA VA D1 D2 IA VA (a) (b) Figure 3.6 (a) Antiparallel diodes, (b) resulting I/V characteristic. Exercise Repeat the above example if a 1-V battery is placed is series with the parallel combination of the diodes. Example 3.4 Plot the I/V characteristic for the diode-resistor combination of Fig. 3.7(a). IA VA D1 R1 IA D1 R1 IA R1 R1 R1 D1 (a) (b) (c) IA 1 R1 VA (d) IA D1 VA R1 (e) D Figure 3.7 (a) Diode-resistor series combination, (b) equivalent circuit under forward bias, (c) equivalent circuit under reverse bias, (d) I/V characteristic, (e) equivalent circuit if 1 is on. Solution We surmise that, if VA 0, an ideal diode. On the other the diode is hand, if VA on [Fig. 0, D1 3.7(b)] and IA is probably off [=FigV.A3=.7R(1c)b]eacnaduIseDV=D10.=Fi0guforer 3.7(d) plots the resulting I/V characteristic. The above observations are based on guesswork. Let us study the circuit more rigorously. We taiobdnhsrieoisgFsdAudiioimnegsme..weVsTp3ADilRh.ti7heu11r(ssieVis,st)sAehhf,sooaiafrntnatVDbdath0oAni1e,vfdecpVtsauozeArrs0eernt,iriuie-osDflos,anwn1taieitenpgrctegoauermeitnrtniarhdvaetcase?inhnt,ttWssoatfhoorecfeofoiofmsadrngawiIflonaiAatididscrn;etdIciii.niAanbesgtv.ih,o=aorotsfekhfds0.teeehu.Tpelatotocr.dotcIiuioftoosafDndlafibec1n.yruomiDrscdrooeeothen,nnsevtt,riflDtavohdaole1aliwictcdtitsuiniirotrfgcynrnuot.ooihmtSfneiutsrdhfpioregipesrfihodgantsunuitectoyeiefoslodVsner,Aftootls.efotBthmthuua0eestt BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 66 (1) 66 Chap. 3 Diode Models and Circuits VRA1 the oisrit0gh,ienDrael1foairssessuetmiqllupoatilfoft,nob. zeIenhraoovt,ihnseugrgawgseoasrntdinso,gpDethn1acttiurVrcnDus1ito=annfdVoAyr iaeanlndydinVhgAeInAce=0I.D01. The voltage drop across = 1 and contradicting Exercise Repeat the above analysis if the terminals of the diode are swapped. The acts as above example leads to two important an open for negative voltages and as a points. First, the resistor of value Rse1rifeosrcpoomsibtiinveatvioonltoagf eDs.1SaencdonRd1, in the analysis of circuits, we can assume an arbitrary state (on or off) for each diode and proceed with the computation of voltages and currents; if the assumptions are incorrect, the final result contradicts the original assumptions. Of course, it is helpful to first examine the circuit carefully and make an intuitive guess. Example 3.5 Why are we interested in I/V characteristics rather than V/I characteristics? Solution In the analysis of circuits, we often prefer to consider the voltage to be the “cause” and the current, the “effect.” This is because in typical circuits, voltage polarities can be predicted more readily and intuitively than current polarities. Also, devices such as transistors fundamentally produce current in response to voltage. Exercise Plot the V/I characteristic of an ideal diode. Example 3.6 In the circuit of Fig. 3.8, each input can assume a value of either zero or +3 V. Determine the response observed at the output. D1 VA VB D2 Vout RL Figure 3.8 OR gate realized by diodes. Solution iIVTmfohVumutAse,tdo=ViaVotu+Betl3y==Vfa,0Vc.aiAnTndhg=iVsaBac+so=s3nuflmV0i,.cpttIth:fioeDunnn1iwcseeetnrhtfsaeouirrrnecm,feowissreeea tvchaoanlttaDagse1suiomsf fe+orb3woVtahrdaD-tb1tihaaesneodduaDtpn2udtaDwre2h,efroreervwaesarDsrde2--bbsiihaassoeerddts., incorrect. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 67 (1) Sec. 3.1 Ideal Diode 67 VAT=he0saynmdmVeBtry=o+f t3heV.cTirhcueict iwrciuthitroepspereacttetsoaVs Aa and VB suggests that Vout logical OR gate and was in = VB = fact used +3 V if in early digital computers. Exercise Construct a three-input OR gate. Example 3.7 Is an ideal diode on or off if VD = 0? Solution An ideal diode experiencing a zero voltage must carry a zero current (why?). However, this does not mean it acts as an open circuit. After all, a piece of wire experiencing a zero voltage behaves similarly. Thus, the state of an ideal diode with VD = 0 is somewhat arbitrary and ambiguous. In practice, we consider slightly positive or negative voltages to determine the response of a diode circuit. Exercise Repeat the above example if a 1- resistor is placed in series with the diode. Input/Output Characteristics Electronic circuits process an input and generate a corresponding output. It is therefore instructive to construct the input/output characteristics of a circuit by varying the input across an allowable range and plotting the resulting output. An example, consider the circuit depicted in Fig. 3.9(a), where the output is defined as the voltage across D1. If Vin 0, D1 is reverse biased, reducing the circuit to that in Fig. 3.9(b). Since no current flows through R1, we have Vout = Vin. If Vin 0, then D1 is forward biased, shorting the output and forcing Vout = 0 [Fig. 3.9(c)]. Figure 3.9(d) illustrates the overall input/output characteristic. 3.1.3 Application Examples Recall from Fig. 3.2 that we arrived at the concept of the ideal diode as a means of converting xt to yt. Let us now design a circuit that performs this function. We may naturally construct the circuit as shown in Fig. 3.10(a). Unfortunately, however, the cathode of the diode is “floating,” the output current is always equal to zero, and the state of the diode is ambiguous. We therefore modify the circuit as depicted in Fig. 3.10(b) and analyze its response to a sinusoidal input [Fig. 3.10(c)]. Since R1 has a tendency to maintain the cathode of D1 near zero, as Vin rises, D1 is forward biased, shorting the output to the input. This state holds for the positive half cycle. When Vin falls below zero, D1 turns off and R1 ensures that Vout = 0 because IDR1 = 0.5 The circuit of Fig. 3.10(b) is called a “rectifier.” It is instructive to plot the input/output characteristic of the circuit as well. Noting that if Vin 0, D1 is off and Vout = 0, and if Vin 0, D1 is on and Vout = Vin, we obtain the R 5Note that without 1, the output voltage is not defined because a floating node can assume any potential. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 68 (1) 68 Chap. 3 Diode Models and Circuits Vin < 0 Vin > 0 R1 R1 R1 Vin D1 Vout Vin Vout Vin Vout (a) (b) (c) Vout Vin 1 (d) Figure 3.9 (a) Resistor-diode circuit, (b) equivalent circuit for negative input, (c) equivalent circuit for positive input, (d) input/output characteristic. behavior shown Vout 6! ,Vout. in Fig. 3.10(d). The rectifier is a nonlinear circuit because if Vin ! ,Vin then Example 3.8 Is it a coincidence that the characteristics in Figs. 3.7(d) and 3.10(d) look similar? Solution No, we recognize that the output Thus, the two plots differ by only voltage in Fig. 3.10(b) is simply a scaling factor equal to R1. equal to IA R1 in Fig. 3.7(a). Exercise Construct the characteristic if the terminals of D1 are swapped. We now determine the time average (dc value) of the output waveform in Fig. 3.10(c) to farreriqvueeantcaynionthraedriianntserpeesrtisnegcoapnpdliacnadtiTont.hSeuppeproiosed.VTinhe=n,Vinp sin the !t, where first cycle != after 2=T denotes the t = 0, we have Vout = Vp sin !t for 0  t  T 2 (3.3) =0 for T 2  t  T (3.4) To compute the average, we obtain the area under Vout and normalize the result to the period: Vout;avg = = 1 T 1 T ZT Z0T=V2outtdt 0 Vp sin !tdt (3.5) (3.6) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 69 (1) Sec. 3.1 Ideal Diode 69 D1 D1 Vin Vout Vin R1 Vout (a) (b) Vin t Vout Vin R1 Vout Vin R1 Rectified Half Cycles 1 Vin 0 T T 3T 2T t 2 2 (d) (c) Figure 3.10 (a) A diode operating as a rectifier, (b) complete rectifier, (c) input and output waveforms, (d) input/output characteristic. = 1 T  Vp ! , cos !t T0 =2 (3.7) = Vp  : (3.8) Thus, the average is proportional to Vp, an expected result because a larger input amplitude yields a greater area under the rectified half cycles. The above observation reveals that the average value of a rectified output can serve as a mea- sure of the “strength” (amplitude) of the input. That is, a rectifier can operate as a “signal strength indicator.” For example, since cellphones receive varying levels of signal depending on the user’s location and environment, they require an indicator to determine how much the signal must be amplified. Example 3.9 A cellphone receives a 1.8-GHz signal with a peak amplitude ranging from 2 V to 10 mV. If the signal is applied to a rectifier, what is the corresponding range of the output average? Solution The rectified output exhibits an average value ranging from 2 V= = 0:637 V to 10 mV/ = 3:18 mV. Exercise Do the above results change if a 1- resistor is placed in series with the diode? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 70 (1) 70 Chap. 3 Diode Models and Circuits In our effort toward understanding the role of diodes, we examine another circuit that will eventually (in Section 3.5.3) lead to some important applications. First, consider the topology in Fig. 3.11(a), where a 1-V battery is placed in series with an ideal diode. How does this circuit behave? If bias. Even to forward iVf 1V1 bias 0, the cathode voltage is higher than the anode voltage, placing D1 in reverse is slightly greater than zero, e.g., equal to 0.9 V, the anode is not positive enough D1. Thus, V1 must approach +1 V for D1 to turn on. Shown in Fig. 3.11(a), the I/V characteristic of the diode-battery combination resembles that of a diode, but shifted to the right by 1 V. I1 V1 D1 VB 1V I1 +1 V V1 (a) R1 Vin Vin D1 Vout Vout Vout t Vin 1 t R1 Vin Vin D1 VB 1 V Vout Vout (b) + Vp t − Vp +1V t − Vp Vout +1 V +1 V Vin 1 (c) Figure 3.11 (a) Diode-battery circuit, (b) resistor-diode circuit, (c) addition of series battery to (b). Now, let Vout = Vin. us examine the circuit in Fig. For Vin 0, D1 acts a short, 3.11(b). and Vout Here, for = 0. The Vin circuit 0, D1 remains off, yielding therefore does not allow the output to exceed zero, as illustrated in the output waveform and the input/output characteristic. But suppose we seek a circuit that must not allow the output to exceed +1 V (rather than zero). How should the circuit of Fig. 3.11(b) be modified? In this case, D1 must turn on only when Vout approaches +1 V, implying that a 1-V battery must be inserted in series with the diode. Depicted  in Fig. 3.11(c), the modification indeed guarantees Vout +1 V for any input level. We say the circuit “clips” or “limits” at +1 V. “Limiters” prove useful in many applications and are described in Section 3.5.3. Example 3.10 Sketch the time average of Vout in Fig. 3.11(c) for a sinusoidal input as the battery voltage, VB, BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 71 (1) Sec. 3.1 Ideal Diode 71 varies from ,1 to +1. Solution cItehfyqacVunlaBelVatiBosn.dvVFeBroreyrm[FnVaieBiggn.as=3toi.v1f0ef2,,(iatDnh)e]1t.haiFesvopearrolaw,sgiaVteiyvprseeoahncaVhlbefBesccy,acuVls0epe,,=DVyii1nelt.duiFrnni,gnsaVaolnlpfyf.,aIavfntoesrrthoaVgimsBeecgaprsoeeaiV,ntpetth,riennthootahulnetipm,nuiettVgianpavgtebivrouaectgchleeuasrilsssf and the average is equal to zero. Figure 3.12(b) sketches this behavior. VB < − Vp − Vp >I B R2 VCC RC Small Enough to Avoid Saturation Y IC X IB Q1 R E VRE >> Variations in VX and VBE Figure 5.21 Summary of robust bias conditions. Design Procedure It is possible to prescribe a design procedure for the bias topology of Fig. 5.21 that serves most applications: (1) decide on a collector bias current that yields proper esVVmsBBtaaEEbll,l-=icsshihgoVnIoTa1slelnpaaIrvIaCaBml=u.eIeDtSefero;ster(sr4Vum)cRihcnEheaodsogbsmeyICRsaRmn1Edaal,rln-eds.;iggR(.n2,2a)2ls0bog0aasamiensdVtrooe; nq(p3utrh)iorecveamiedlxceepunetlthacset,teetndhVeevXcaveras=islauateriVoyBonvfsEaRol+ufCeRIioC1sf,RbRVoEXu2 ,nwaadinnetdhdd by a maximum that places Q1 at the edge of saturation. The following example illustrates these concepts. Example 5.11 Design VCC = the 2:5 circuit of Fig. 5.21 so as V, = 100, and IS = 5 to  1p0ro,v1i7dAe a. Wtrahnastciosntdhuecmtaanxciemoufm1=to5le2rablefovar lQue1.oAf RssCum? e Solution AREgImC of 52 = 200 ,1 mV, translates to a we obtain RE collector = 400 current of 0.5 . To establish mA VX a=ndVaBVEB+E of 778 REIC mV. Assuming = 978 mV, we must have R2 R1 + R2 VCC = VBE + REIC ; (5.63) where the base current is neglected. For the base current IB = 5 A to be negligible, VCC R1 + R2 IB ; (5.64) e.g., by a factor of 10. Thus, R1 + R2 = 50 k , which in conjunction with (5.63) yields R1 = 30:45 k (5.65) R2 = 19:55 k : (5.66) How large can RC be? Since the collector voltage is equal to VCC , RCIC, we pose the following constraint to ensure active mode operation: VCC , RCIC VX; (5.67) that is, RCIC 1:522 V: (5.68) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 193 (1) Sec. 5.2 Operating Point Analysis and Design 193 Consequently, RC 3:044 k : (5.69) If RC exceeds this value, the collector voltage falls below the base voltage. As mentioned in Chapter 4, the transistor can tolerate soft saturation, i.e., up to about 400 mV of base-collector forward bias. greater value Thus, in for RC. low-voltage applications, we may allow VY  VX , 400 mV and hence a Exercise Repeat the above example if the power budget is only 1 mW and the transconductance of Q1 is not given. The two rules depicted in Fig. 5.21 to lower sensitivities do impose some trade-offs. Specif- ically, an overly conservative much greater than IB, then R1 design faces the + R2 and hence following R1 and R2 issues: (1) if we wish I1 to are quite small, leading to a be much low input impedance; (2) if we choose a very large VRE, then VX (= VBE + VRE) must be high, thereby limiting the minimum value of the collector voltage to avoid saturation. Let us return to the above example and study these issues. Example 5.12 Repeat Example 5.11 but assuming VRE = 500 mV and I1  100IB. Solution The collector current and base-emitter voltage remain unchanged. The value of RE is now given by 500 mV=0:5 mA = 1 k . Also, VX = VBE + REIC = 1:278 V and (5.63) still holds. We rewrite (5.64) as VCC R1 + R2  100IB; (5.70) obtaining R1 + R2 = 5 k . It follows that R1 = 1:45 k R2 = 3:55 k : (5.71) (5.72) Since the base voltage has risen to 1.278 V, the collector voltage must exceed this value to avoid saturation, leading to RC VCC , VX IC 1:044 k : (5.73) (5.74) AsmsasleleernvianluSeescotifoRn 15.a3n.1d,Rth2ehreerdeutchtaionnininERxaCmtprlaen5sl.a1t1esinttoroadluocweearlvoowltiangpeugt aiminp. eAdlasnoc,et,hleoamduincgh the preceding stage. We compute the exact input impedance of this circuit in Section 5.3.1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 194 (1) 194 Chap. 5 Bipolar Amplifiers Exercise Repeat the above example if VRE is limited to 100 mV. 5.2.4 Self-Biased Stage Another biasing scheme commonly used in discrete and integrated circuits is shown in Fig. 5.22. Called “self-biased” because the base current and voltage are provided from the collector, this stage exhibits many interesting and useful attributes. RB IB X VCC RC Y IC Q1 Figure 5.22 Self-biased stage. Let us begin the analysis of the circuit with the observation that the base voltage is always , prloarmwopeeerterttryhsa.gnFuotahrreaenxctaoemellsepcltetho,aritfvQRo1lCtaogipnee:crrVaetXaesse=sininVthdYeefiancittIievBleyR,mBQo.1dAreermreesaguianlrtsdolienfssstheoleff-abdcietaivsviiecnegre,agtnhiodisnc,iimarcpcuroiitrttipacana-lt advantage over the circuit of Fig. 5.21. We now determine the collector bias current by assuming IB equal to IC, thereby yielding IC ; i.e., RC carries a current VY = VCC , RCIC: (5.75) Also, VY = RBIB + VBE = RBIC + VBE: (5.76) (5.77) Equating the right hand sides of (5.75) and (5.77) gives IC = VCC RC , + VBE RB : (5.78) As usual, we begin with an initial guess for VBE, compute IC, and utilize VBE = VT lnIC=IS to improve the accuracy of our calculations. Example 5.13 Determine the VCC = 2:5 V, collector IS = 5  1cu0r,re17ntAa,nadndvolta=ge10o0f.QR1epineaFt itgh.e5c.a2l2cuilfaRtioCns=fo1r RkC , RB = =2k . 10 k , BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 195 (1) Sec. 5.2 Operating Point Analysis and Design 195 Solution Assuming VBE = 0:8 V, we have from (5.78): IC = 1:545 mA; (5.79) and hence VBE = VT lnIC=IS = 807:6 mV, concluding that the initial guess for VBE and VthYeIvf=aRlRuCeB=oIfB2I+Ck given by it are reasonably accurate. We also V,BtEhen w0i:t9h5V5BVE. = 0:8 V, Eq. (5.78) gives note that RBIB = 154:5 mV and IC = 0:810 mA: (5.80) wT(5oi.t8hc0hV)eCicskCatc,hceeVpvBatalEibdliient.ySthoienf ctnheueRminBeirItaiBtaolr=gouf8e1(s5sm,.7wV8e,),VwtYhreite9-V0mB:8VE81e=rVro.VrTislnneIgCli=gIibSle = 791 mV. Compared and the value of IC in Exercise What happens if the base resistance is doubled? Equation (5.78) and the above example suggest two important guidelines for the design of the , self-biased stage: (1) VCC VBE must be much greater than the uncertainties in the value of VBE; (2) RC must be much greater than RB= to lower sensitivity to . In fact, if RC RB= , then IC  VCC , VBE RC ; (5.81) and VY = VCC , ICRC  VBE. This result serves as a quick estimate of the transistor bias conditions. Design Procedure Equation (5.78) together with the condition RC basic expressions for the design of the circuit. With the required value of signal considerations, we choose RC = 10RB= and rewrite (5.78) as IC RB= provides the known from small- IC = VCC , VBE 1:1RC ; (5.82) where VBE = VT lnIC=IS. That is, RC = VCC , VBE 1:1IC RB = RC 10 : (5.83) (5.84) The choice of RB also depends on small-signal requirements and may deviate from this value, but it must remain substantially lower than RC. Example 5.14 Design IS = 5 the10s,e1lf6-bAiaasnedd stage of Fig. = 100. 5.22 for gm = 1=13  and VCC = 1:8 V. Assume BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 196 (1) 196 Chap. 5 Bipolar Amplifiers Solution Since gm = IC=VT = 1=13 , we have IC = 2 mA, VBE = 754 mV, and RC  VCC , VBE 1:1IC  475 : (5.85) (5.86) Also, RB = RC 10 = 4:75 k : (5.87) (5.88) Note that RBIB = 95 mV, yielding a collector voltage of 754 mV + 95 mV = 849 mV. Exercise Repeat the above design with a supply voltage of 2.5 V. Figure 5.23 summarizes the biasing principles studied in this section. RB RC R1 RC Q1 Q1 R2 Sensitive to β Sensitive to Resistor Errors Figure 5.23 Summary of biasing techniques. R1 RC I1 Q1 R 2 R E VRE RB RC Always in Q 1 Active Mode 5.2.5 Biasing of PNP Transistors The dc bias topologies studied thus far incorporate npn transistors. Circuits using pnp devices follow the same analysis and design procedures while requiring attention to voltage and current polarities. We illustrate these points with the aid of some examples. Example 5.15 Calculate allowable the collector value of RC and voltage of Q1 in the circuit of for operation in the active mode. Fig. 5.24 and determine the maximum Solution The topology is the same as that in Fig. 5.13 and we have, IBRB + VEB = VCC: (5.89) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 197 (1) Sec. 5.2 Operating Point Analysis and Design 197 IB VEB VCC X Q1 RB Y IC RC Figure 5.24 Simple biasing of pnp stage. That is, IB = VCC , VEB RB (5.90) and IC = VCC , VEB RB : (5.91) The circuit suffers from sensitivity to . If RC is increased, VY saturation. The transistor rises, enters tshautusraaptipornoaacthViYng=VXVX(=, i.VeC.,C , VEB ) and bringing Q1 closer to ICRC;max = VCC , VEB (5.92) and hence RC;max = VCC , VEB IC = RB : (5.93) (5.94) From as the acnoontdhietiropnefrospr eecdtgiveeo, fsisnactuerVatXion=, oIbBtaRinBinagnRd BVY== RICC;RmCax, .we have IB RB = IC RC;max Exercise For a given RC, what value of RB places the device at the edge of saturation? Example 5.16 Determine the collector current and voltage of Q1 in the circuit of Fig. 5.25(a). Solution As a general case, we assume IB is significant and construct the Thevenin equivalent of the voltage divider as depicted in Fig. 5.25(b): VT hev = R1 R1 + R2 VCC RThev = R1jjR2: (5.95) (5.96) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 198 (1) 198 Chap. 5 Bipolar Amplifiers VCC R2 I1 I B VEB X Q1 R1 Y IC RC VThev R Thev VCC I B VEB X Q1 Y IC RC (a) (b) V Figure 5.25 (a) PNP stage with resistive divider biasing, (b) Thevenin equivalent of divider and CC. Adding the voltage drop across RT hev and VEB to VT hev yields VThev + IBRThev + VEB = VCC; (5.97) that is, IB = VCC , VT hev RT hev , VEB = R2 R1 + R2 VCC RT hev , VEB : (5.98) (5.99) It follows that IC = R2 R1 + R2 VCC RT hev , VEB : (5.100) As in Example 5.9, some iteration between IC and VEB may be necessary. Equation (5.100) indicates that if IB is significant, then the transistor bias heavily depends on . On the other hand, if IB I1, we equate the voltage drop across R2 to VEB, thereby obtaining the collector current: IC = IS exRp1 R+R2R1R2+V2RCC2 = VEB VCC VT : (5.101) (5.102) Note that this result is identical to Eq. (5.30). Exercise What is the maximum value of RC is Q1 must remain in soft saturation? Example 5.17 Assuming a negligible base current, calculate the collector current and voltage of Q1 in the BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 199 (1) Sec. 5.2 Operating Point Analysis and Design 199 circuit of Fig. 5.26. What is the maximum allowable value of RC for Q1 to operate in the forward active region? VCC R2 R E VRE I1 I B VEB X Q1 R1 Y IC RC Figure 5.26 PNP stage with degeneration resistor. Solution With IB the drop I1, across we RE have VX = , we obtain VCC R1=R1 + R2. Adding to VX the emitter-base voltage and VX + VEB + REIE = VCC (5.103) and hence IE = 1 RE R2 R1 + R2 VCC , VEB : (5.104)  sIUtBrsaiIn=ingghaItrICfrCoi=vrwin,agwrdaIeEtac(p,a5pnw.r1oev0ae4ccr)aih,fnywisctethoohemraaevpsceusoutwgemnraiipztttneieoentnwhaaItvBKtahVleuLevoIff1lroto.armgVeVEdCBroCpantaodcrgoirtsoesruaRntde2,iiEsf qen.qeu(c5ae.ls1ts0oa3rVy).E. BBAu+ltsoIa,EmwRoiEtrhe, i.e., VCC R2 R1 + R2 = VEB + IERE; (5.105) which yields the same result as in (5.104). The maximum allowable value of RC is obtained by equating the base and collector voltages: VCC R1 R1 + R2 =  RC;maxIC RC;max RE R2 R1 + R2 VCC , VEB : (5.106) (5.107) It follows that RC;max = RE VCC R1 R1 + R2  1 R2 R1 + R2 VCC : , VEB (5.108) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 200 (1) 200 Exercise Repeat the above example if R2 = 1. Chap. 5 Bipolar Amplifiers Example 5.18 Determine the collector current and voltage of Q1 in the self-biased circuit of Fig. 5.27. Figure 5.27 Self-biased pnp stage. VEB VCC X Q1 IB Y IC RB RC Solution We must Since write 1 a KVL from VCC and hence IC tIhBro,uRghCthcearermieisttaerc-buarrseenjtunapctpiroonxoimf Qat1e,lyReBq,uaanldtoRCICt,ocgrreoautinndg. VY = RCIC. Moreover, VX = RBIB + VY = RBIB + RCIC, yielding VCC = VEB + VX = = VEB VEB + + R BRIBB + ICR C + RC IC : (5.109) (5.110) (5.111) Thus, IC = VCC RB , VEB + RC ; (5.112) a result similar to mine a new value Eq. (5.78). As usual, we begin with a for VEB, etc. Note that, since the base guess for is higher VEB than ,thceomcoplluetcetoIrCv, oalntadgdee, tQer1- always remains in the active mode. Exercise How far is Q1 from saturation? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 201 (1) Sec. 5.3 Bipolar Amplifier Topologies 201 5.3 Bipolar Amplifier Topologies Following our detailed study of biasing, we can now delve into different amplifier topologies and examine their small-signal properties.6 Since the bipolar transistor contains three terminals, we may surmise that three possibilities exist for applying the input signal to the device, as conceptually illustrated in Figs. 5.28(a)(c). Similarly, the output signal can be sensed from any of the terminals (with respect to ground) [Figs. 5.28(d)-(f)], leading to nine possible combinations of input and output networks and hence nine amplifier topologies. v in v in v in (a) (b) (c) v out v out (d) (e) Figure 5.28 Possible input and output connections to a bipolar transistor. v out (f) However, as seen in Chapter 4, bipolar transistors operating in the active mode respond to base-emitter voltage variations by varying their collector current. This property rules out the input connection shown in Fig. 5.28(c) because Also, the topology in Fig. 5.28(f) proves here Vin does of no value as not affect the Vout is not a base or emitter function of the voltages. collector current. The number of possibilities therefore falls to four. But we note that the input and output connections in Figs. 5.28(b) and (e) remain incompatible because Vout would be sensed at the input node (the emitter) and the circuit would provide no function. The above observations reveal three possible amplifier topologies. We study each carefully, seeking to compute its gain and input and output impedances. In all cases, the bipolar transistors operate in the active mode. The reader is encouraged to review Examples (5.2)-(5.4) and the three resulting rules illustrated in Fig. 5.7 before proceeding further. 5.3.1 Common-Emitter Topology Our initial thoughts in Section 4.1 pointed to the circuit of Fig. 4.1(b) and hence the topology of Fig. 4.25 as an amplifier. If the input signal is applied to the base [Fig. 5.28(a)] and the output signal is sensed at the collector [Fig. 5.28(d)], the circuit is called a “common-emitter” (CE) stage (Fig. 5.29). We have encountered and analyzed this circuit in different contexts without giving it a name. The term “common-emitter” is used because the emitter terminal is grounded and hence appears in common to the input and output ports. Nevertheless, we identify the stage based on the input and output connections (to the base and from the collector, respectively) so as to avoid confusion in more complex topologies. 6While beyond the scope of this book, the large-signal behavior of amplifiers also becomes important in many applications. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 202 (1) 202 Chap. 5 Bipolar Amplifiers VCC RC Vout Q 1 Output Sensed at Collector Vin Figure 5.29 Common-emitter stage. Input Applied to Base We deal with the CE amplifier in two phases: (a) analysis of the CE core to understand its fundamental properties, and (b) analysis of the CE stage including the bias circuitry as a more realistic case. Analysis of CE Core Recall from the definition of transconductance in Section 4.4.3 that a small increment of V applied to gmV and hence the voltage drop tahcerobsassRe oCfbQy1gimnFiVg.R5C.2.9Ininocrrdeearsteos the collector current by examine the amplifying properties of the CE stage, we construct the small-signal equivalent of the circuit, shown in Fig. 5.30. As explained in Chapter 4, the supply voltage node, VCC, acts as an ac ground because its value remains constant with time. We neglect the Early effect for now. v in rπ vπ gm vπ v − out RC v out RC Figure 5.30 Small-signal model of CE stage. Let us first compute the small-signal voltage gain Av = vout=vin. Beginning from the output port and writing a KCL at the collector node, we have , vout RC = gmv; (5.113) and v = vin. It follows that Av = ,gmRC: (5.114) Equation (5.114) embodies two interesting and important properties of the CE stage. First, the small-signal gain is negative because raising the base voltage and hence the collector current in Fig. 5.29 lowers Vout. Second, Av is proportional to gm (i.e., the collector bias current) and the collector resistor, RC. Interestingly, the voltage gain of the stage is limited by the supply voltage. A higher collector bias current exceed VCC .oIrn afalcatr,gdeer nRotCingdetmheanddcsdarogpreaactreorssvoRltCagwe itdhroVpRaCcraonsds wRrCit,inbgutgmthi=s dIrCop=VcTan, nwoet express (5.114) as jAvj = IC RC VT (5.115) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 203 (1) Sec. 5.3 Bipolar Amplifier Topologies 203 = VRC VT : (5.116) Since VRC VCC, jAvj VCC VT : (5.117) Furthermore, the transistor itself requires a minimum collector-emitter voltage of about VBE to remain in the active region, lowering the limit to jAvj VCC , VT VBE : (5.118) Example 5.19 Design a CE core with VCC = 1:8 V and a power budget, P , of 1 mW while achieving maximum voltage gain. Solution Since P = IC  VCC = 1 mW, we have IC = 0:556 mA. The value of RC that places Q1 at the edge of saturation is given by VCC , RCIC = VBE; (5.119) which, along with VBE  800 mV, yields RC  VCC , VBE IC  1:8 k : (5.120) (5.121) The voltage gain is therefore equal to Av = ,gmRC = ,38:5: (5.122) (5.123) Under this condition, an input signal drives the transistor into saturation. As illustrated in Fig. 5.31(a), for half oaf2e-amcVh pcpycinlep.uNt reevseurltthseilnesas,7s7o-mloVnpgpaosuQtp1urt,efmoarwinasridn-bsioafstinsagtuthreatbioanse(-VcBolClecto4r 0ju0nmctVio)n, the circuit amplifies properly. A more aggressive design may allow Q1 to operate in soft saturation, e.g., VCE  400 mV and hence RC  VCC , 400 IC mV  2:52 k : (5.124) (5.125) In this case, the maximum voltage gain is given by Av = ,53:9: (5.126) Of course, the circuit can now tolerate only very small voltage swings at the output. For example, a 2-mVpp input signal gives rise to a 107.8-mVpp output, driving Q1 into heavy saturation [Fig. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 204 (1) 204 Chap. 5 Bipolar Amplifiers 800 mV 2 mVpp t VCC RC 800 mV Q1 77 mVpp t (a) 800 mV 2 mVpp VCC RC 400 mV Q1 t (b) Figure 5.31 CE stage (a) with some signal levels, (b) in saturation. 107.8 mVpp t 5.31(b)]. We say the circuit suffers from a trade-off between voltage gain and voltage “headroom.” Exercise Repeat the above example if VCC = 2:5 V and compare the results. Let us now calculate the I/O impedances of the CE stage. Using the equivalent circuit depicted in Fig. 5.32(a), we write Rin = vX iX = r: (5.127) (5.128) Thus, the input impedance is simply equal to =gm = VT =IC and decreases as the collector bias increases. iX iX vX rπ vπ g m vπ RC rπ vπ g m v π RC vX (a) (b) Figure 5.32 (a) Input and (b) output impedance calculation of CE stage. The output impedance is obtained from Fig. 5.32(b), where the input voltage source is set to zero (replaced with a short). Since v = 0, the dependent current source also vanishes, leaving BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 205 (1) Sec. 5.3 Bipolar Amplifier Topologies 205 RC as the only component seen by vX . In other words, Rout = vX iX = RC: (5.129) (5.130) , The output impedance therefore trades with the voltage gain, gmRC. Figure 5.33 summarizes the trade-offs in the performance of the CE topology along with the parameters that create such trade-offs. For example, for a given value of output impedance, RC is fixed and the voltage gain can be increased by increasing IC, thereby lowering both the voltage headroom and the input impedance. Voltage Headroom (Swings) Voltage g m Gain RC Figure 5.33 CE stage trade-offs. Input Impedance β gm Output Impedance RC Example 5.20 A CE stage must achieve an input impedance of Rin and an output impedance of Rout. What is the voltage gain of the circuit? Solution Since Rin = r = =gm and Rout = RC, we have Av = ,gmRC =, Rout Rin : (5.131) (5.132) Interestingly, if the I/O impedances are specified, then the voltage gain is automatically set. We will develop other circuits in this book that avoid this “coupling” of design specifications. Exercise What happens to this result if the supply voltage is halved? Inclusion of Early Effect Equation (5.114) suggests that the voltage gain of the CE stage ! 1 can be increased indefinitely 4.4.5, this trend appears valid if if VRCCC is also while gm remains constant. Mentioned in Section raised to ensure the transistor remains in the active mode. From an intuitive point of view, a given change in the input voltage and hence the collector current gives rise to an increasingly larger output swing as RC increases. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 206 (1) 206 Chap. 5 Bipolar Amplifiers In reality, however, the Early effect limits the voltage gain even if RC approaches infinity. Since achieving a high gain proves critical in circuits such as operational amplifiers, we must reexamine the above derivations in the presence of the Early effect. Figure 5.34 depicts the small-signal equivalent circuit of the CE stage including the transistor output resistance. Note that rO appears in parallel with RC, allowing us to rewrite (5.114) as Av = ,gmRCjjrO: (5.133) We also recognize that the input impedance remains equal to r whereas the output impedance falls to Rout = RCjjrO: (5.134) v in rπ vπ gm vπ v out rO RC Figure 5.34 CE stage including Early effect. Example 5.21 The circuit of Fig. 5.29 is biased with a collector current of 1 mA and RC = 1 k . If = 100 and VA = 10 V, determine the small-signal voltage gain and the I/O impedances. Solution We have gm = IC VT = 26 ,1 (5.135) (5.136) and rO = VA IC = 10 k : (5.137) (5.138) Thus, Av = ,gmRCjjrO  35: (As a comparison, if VA = 1, then Av  38.) For the I/O impedances, we write Rin = r = gm = 2:6 k (5.139) (5.140) (5.141) (5.142) (5.143) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 207 (1) Sec. 5.3 Bipolar Amplifier Topologies and Rout = RCjjrO = 0:91 k : 207 (5.144) (5.145) Exercise Calculate the gain if VA = 5 V. ! 1 Let us determine the gain of a CE stage as RC . Equation (5.133) gives Av = ,gmrO: (5.146) Called the “intrinsic gain” of the transistor to emphasize that no external device loads the circuit, gmrO represents the maximum voltage gain provided by a single transistor, playing a fundamental role in high-gain amplifiers. We now substitute gm = IC=VT and rO = VA=IC in Eq. (5.133), thereby arriving at jAvj = VA VT : (5.147) Interestingly, the intrinsic gain of a bipolar transistor is independent of the bias current. In modern integrated bipolar transistors, VA falls in the vicinity of 5 V, yielding a gain of nearly 200.7 In this book, we assume gmrO 1 (and hence rO 1=gm) for all transistors. Another parameter of the CE stage that may prove relevant in some applications is the “current gain,” defined as AI = iout iin ; (5.148) where iout denotes the current delivered to the load and iin the current flowing to the input. We rarely deal with this parameter for voltage amplifiers, but note that AI = for the stage shown in Fig. 5.29 because the entire collector current is delivered to RC. CE Stage With Emitter Degeneration In many applications, the CE core of Fig. 5.29 is modified as shown in Fig. 5.35(a), where a resistor RE appears in series with the emitter. Called “emitter degeneration,” this technique improves the “linearity” of the circuit and provides many other interesting properties that are studied in more advanced courses. As with the CE core, we intend to determine the voltage gain and I/O impedances of the circuit, assuming Q1 is biased properly. Before delving into a make some qualitative observations. Suppose the input signal detailed analysis, it is instructive to raises the base voltage by V [Fig. 6 5.35(b)]. If a collector RE were zero, current change then the base-emitter of gmV . But with voltage would also increase by RE = 0, some fraction of V V , producing appears across RE, thus leaving a voltage change across the BE junction that is less than V . Consequently, the collector current change is also less than gmV . We therefore expect that the voltage gain of 7But other second-order effects limit the actual gain to about 50. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 208 (1) 208 Chap. 5 Bipolar Amplifiers VCC RC Vout Vin Q1 ∆V VCC RC Vout Q1 RE RE (a) (b) Figure 5.35 (a) CE stage with degeneration, (b) effect of input voltage change. the degenerated stage is lower than that of the CE core with no degeneration. While undesirable, the reduction in gain is incurred to improve other aspects of the performance. bsia=rsagHebmolcewu=prraroebrpnoetu.rtatTyltshh.ouAesic,cnhoepammuntigmtietmoesrnpbdemyedigaslenetansckseeer?tahiStsiaiotnnoncgceimnotcnhrceelVaucs=doeelsle,thtchyatoeiterRlidnciipunnurgr=teianmrntpci+hendapRnaungtEcei,emibsoupflteetadshssaenethcCxaepEnlgasgirtnemaeagdtee,bVrea,tlhodthawene-, Rin = r +  + 1RE. We now quantify the foregoing observations by analyzing the small-signal behavior of the circuit. Depicted in Fig. 5.36 is the small-signal equivalent circuit, where VCC is replaced with an ac ground and the Early effect is neglected. Note that v appears across r and not from the base to ground. To determine vout=vin, we first write a KCL at the output node, v out v in rπ vπ gm vπ RC RE Figure 5.36 Small-signal model of CE stage with emitter degeneration. gmv = , vout RC ; (5.149) obtaining v = , vout gmRC : (5.150) We also recognize that two currents flow through RE: one originating from r equal to v=r and another equal to gmv. Thus, the voltage drop across RE is given by vRE = v r + gmv RE: (5.151) Since the voltage drop across r and RE must add up to vin, we have vin = = v v + + vRvE r + gmv RE (5.152) (5.153) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 209 (1) Sec. 5.3 Bipolar Amplifier Topologies = v  1 + 1 r + gm  RE : 209 (5.154) Substituting for v from (5.150) and rearranging the terms, we arrive at vout vin = , 1 + r1gm+RCgm RE : (5.155) As predicted earlier, the magnitude of the voltage 1, we can assume gm 1=r and hence gain is lower than gmRC for RE 6= 0. With Av = , 1 gmRC + gmRE : (5.156) Thus, the gain falls by a factor of 1 + gmRE. To arrive at an interesting interpretation of Eq. (5.156), we divide the numerator and denomi- nator by gm, Av = , RC 1 gm + RE : (5.157) It is helpful to memorize this result as “the gain of the degenerated CE stage is equal to the total load resistance seen at the collector (to ground) divided by 1=gm plus the total resistance placed in series with the emitter.” (In verbal descriptions, we often ignore the negative sign in the gain, with the understanding that it must be included.) This and similar interpretations throughout this book greatly simplify the analysis of amplifiers—often obviating the need for drawing smallsignal circuits. Example 5.22 Determine the voltage gain of the stage shown in Fig. 5.37(a). VCC RC VCC RC v out v in Q1 RE r π2 VCC Q2 v out v in Q1 RE r π2 (a) (b) Figure 5.37 (a) CE stage example, (b) simplified circuit. Solution jWius nesceitndisoeenndtoifafytQitths2e.ccToihlrlceeucliattotatre.srTaehCxihsEitbrsaittansgsaeisnbtoiemrcaipsuesddeeagtnheceneeionrafptruetd2isb(yaapstpwilloliueddstertvoaitctehedesi:bnRaFsEeigoa.nf5dQ.7t1)h,aelnebadadtsihene-geomtuoittpttheuert simplified model depicted in Fig. 5.37(b). The total resistance placed in series with the emitter is BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 210 (1) 210 Chap. 5 Bipolar Amplifiers therefore equal to REjjr2, yielding Av = , 1 gm1 RC + REjjr2 : (5.158) Without the above observations, we would need Q2 and solve a system of several equations. to draw the small-signal model of both Q1 and Exercise Repeat the above example if a resistor is placed in series with the emitter of Q2. Example 5.23 Calculate the voltage gain of the circuit in Fig. 5.38(a). VCC RC v out v in Q1 RE VCC Q2 VCC RC v out v in Q1 r π2 RE (a) (b) Figure 5.38 (a) CE stage example, (b) simplified circuit. Solution The topology is a CE stage degenerated by RE, but the load resistance between the collector of Q1 and ac ground consists of RC and the base-emitter junction of Q2. Modeling the latter by jj r2, we reduce the circuit to that shown in Fig. 5.38(b), where the total load resistance seen at the collector of Q1 is equal to RC r2. The voltage gain is thus given by Av = , RC jjr2 1 gm1 + RE : (5.159) Exercise Repeat the above example if a resistor is placed in series with the emitter of Q2. To compute the input impedance of the degenerated CE stage, we redraw the small-signal model as in Fig. 5.39(a) and is equal to iX + gmriX = ca1lc+ulateiXvX, c=rieXa.tiSnigncaevvolta=gerdrioXp, tohfeRcEurr1en+t flowiXin.gStuhmromuginhgRvE and vRE and equating the result to vX , we have BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 211 (1) Sec. 5.3 Bipolar Amplifier Topologies iX vX rπ vπ gm vπ v out RC P vRE RE 211 iX vX rπ R in (β +1) RE (a) (b) Figure 5.39 (a) Input impedance of degenerated CE stage, (b) equivalent circuit. vX = riX + RE1 + iX; (5.160) and hence Rin = vX iX = r +  + 1RE: (5.161) (5.162) As predicted by our qualitative reasoning, emitter degeneration increases the input impedance [Fig. 5.39(b)]. Why is Rin not simply equal to r + RE? This would hold only if r and RE were exactly in series, i.e., if the two carried equal currents, but in the circuit of Fig. 5.39(a), the collector current, gmv, also flows into node P . Does the factor + 1 bear any intuitive meaning? We observe that the flow of both base ttcahhnuredrorcuecungorthlrleoeanfcrttoeodnsrrilasyctwuoirnXrreefnwqrotuhsmaitllhevtroXporuoigsdh+umcRe1inrEegRlyraEeisv.Xuol.lttsIangineotadhreloarprwgoeofrvdosl,t+athge1etdieXrsotRpv,Eoltaacg+reos1ssoiuRXrEcRe—,Ev,aXsev,ifesuniXptphflloioeuwsghas The above observation is articulated as follows: any impedance tied between the emitter and ground is multiplied by + 1 when “seen from the base.” The expression “seen from the base” means the impedance measured between the base and ground. We also calculate the output impedance of the stage with the aid of the equivalent shown in Fig. 5.40, where the input voltage is set to zero. Equation (5.153) applies to this circuit as well: iX rπ vπ g m vπ RC vX P vRE RE (a) Figure 5.40 Output impedance of degenerated stage. vin = 0 = v + v r + gmv RE; yielding v = 0 and hence gmv = 0. Thus, all of iX flows through RC, and Rout = vX iX = RC; (5.163) (5.164) (5.165) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 212 (1) 212 Chap. 5 Bipolar Amplifiers revealing that emitter degeneration does not alter the output impedance if the Early effect is neglected. Example 5.24 A CE stage is biased at a collector current of 1 mA. If the circuit provides a voltage gain of 20 with no emitter degeneration and 10 with degeneration, determine RC, RE, and the I/O impedances. Assume = 100. Solution For Av = 20 in the absence of degeneration, we require gmRC = 20; which, together with gm = IC=VT = 26 ,1, yields (5.166) RC = 520 : (5.167) Since degeneration lowers the gain by a factor of two, 1 + gmRE = 2; (5.168) i.e., RE = 1 gm = 26 : (5.169) (5.170) The input impedance is given by Rin = r +  + 1RE = gm +  + 1RE  2r because 1 and RE = 1=gm in this example. Thus, Rin = 5200 . Finally, Rout = RC = 520 : (5.171) (5.172) (5.173) (5.174) (5.175) Exercise What bias current would result in a gain of 5 with such emitter and collector resistor values? Example 5.25 Compute the voltage gain and I/O impedances of the circuit depicted in Fig. 5.41. Assume a very large value for C1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 213 (1) Sec. 5.3 Bipolar Amplifier Topologies 213 Figure 5.41 CE stage example. VCC RC Vout Vin Q1 RE Constant C1 Solution If C1 is very large, it acts as a short circuit for the signal frequencies of interest. Also, the constant current source is replaced with an open circuit in the small-signal equivalent circuit. Thus, the stage reduces to that in Fig. 5.35(a) and Eqs. (5.157), (5.162), (5.165) apply. Exercise Repeat the above example if we tie another capacitor from the base to ground. The degenerated CE stage can be analyzed from a different perspective to provide more in- sight. Let us place the transistor and the emitter resistor in a black box having still three terminals [Fig. 5.42(a)]. For small-signal operation, we can view the box as a new transistor (or “active” device) and model its behavior by new values of transconductance and impedances. Denoted by Gm to avoid confusion with gm of Q1, the equivalent transconductance is obtained from Fig. 5.42(b). Since Eq. (5.154) still holds, we have i out v in Q1 RE v in rπ vπ i out gmvπ RE (a) (b) Figure 5.42 (a) Degenerated bipolar transistor viewed as a black box, (b) small-signal equivalent. and hence iout = gmv = gm 1 + r,1vi+n gmRE ; Gm = iout vin (5.176) (5.177) (5.178) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 214 (1) 214 Chap. 5 Bipolar Amplifiers  1 gm + gmRE : (5.179) , For example, the voltage gain of the stage with a load resistance of RD is given by GmRD. An interesting property of the degenerated CE stage is that its voltage gain becomes relatively ! , independent of the transistor transconductance and hence bias current if gmRE 1. From Eq. (5.157), we note that Av RC=RE under this condition. As studied in Problem 40, this trend in fact represents the “linearizing” effect of emitter degeneration. As a more general case, we now consider a degenerated CE stage containing a resistance in series with circuit, but the base [Fig. 5.43(a)]. often proves inevitable. AFosrseexeanmbpelleo,wR, BRBmaoynlryepdreegsreandtetshethoeuptpeurftorremsiasntacnecoefotfhae microphone connected to the input of the amplifier. VCC RC v out v in RB A Q1 v in RB A rπ RE (β +1) RE (a) (b) Figure 5.43 (a) CE stage with base resistance, (b) equivalent circuit. To analyze the small-signal behavior of this stage, we can adopt one of two approaches: (a) draw the small-signal model of the entire circuit and solve the resulting equations, or (b) recog- nize that the signal at node A is simply an attenuated version of vin and write vout vin = vA vin  vout vA : (5.180) Hbaesree,ovf AQ=1v,iannddevnooutte=svtAhereepfrfeescetnotfs voltage division the voltage gain between from the RB base and the impedance seen at the of Q1 to the output, as already obtained in Eqs. (5.155) and (5.157). We leave the former approach for Problem 44 and continue with the latter here. Let us first compute vA=vin with the aid of Eq. (5.162) and the model depicted in Fig. 5.39(b), as illustrated in Fig. 5.43(b). The resulting voltage divider yields vA vin = r r +  + + + 1RE 1RE + RB : (5.181) Combining (5.155) and (5.157), we arrive at the overall gain as vout vin = r r +  + 1RE +  + 1RE + RB  1 + ,r1gm+RgCm RE = r r +  + + + 1RE 1RE + RB  r ,gmrRC + 1 + RE = r +  , + RC 1RE + RB : (5.182) (5.183) (5.184) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 215 (1) Sec. 5.3 Bipolar Amplifier Topologies 215 To obtain a more intuitive expression, we divide the numerator and the denominator by : Av  1 gm + ,RC RE + RB : +1 (5.185) Compared to (5.157), this result contains only one additional term in the denominator equal to the base resistance divided by + 1. The above results reveal that resistances in series with the emitter and the base have similar effects on the voltage gain, but RB is scaled down by + 1. The significance of this observation becomes clear later. For the stage of Fig. 5.43(a), we can define two different input impedances, one seen at the base of Q1 and another at the left terminal of RB (Fig. 5.44). The former is equal to VCC RC v out RB Q1 R in2 R in1 RE Figure 5.44 Input impedances seen at different nodes. Rin1 = r +  + 1RE (5.186) and the latter, Rin2 = RB + r +  + 1RE: (5.187) In practice, Rin1 proves more relevant and useful. We also note that the output impedance of the circuit remains equal to Rout = RC (5.188) even with RB 6= 0. This is studied in Problem 45. Example 5.26 A microphone having an output resistance of 1 k generates a peak signal level of 2 mV. Design a CE stage with a bias current of 1 mA that amplifies this signal to 40 mV. Assume RE = 4=gm and = 100. Solution The following quantities are obtained: RB = 1 k , gm = 26 ,1, jAvj = 20, and RE = 104 . From Eq. (5.185), RC = jAv j 1 gm + RE + RB +1 (5.189)  2:8 k : (5.190) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 216 (1) 216 Chap. 5 Bipolar Amplifiers Exercise Repeat the above example if the microphone output resistance is doubled. Example 5.27 Determine the voltage gain and I/O impedances of the circuit shown in Fig. 5.45(a). Assume a very large value for C1 and neglect the Early effect. VCC RC v out v in RB Q1 R1 R2 C1 v in RB RC Q1 v out R1 I1 R2 (a) (b) Figure 5.45 (a) CE stage example, (b) simplified circuit. Solution Replacing C1 with a short circuit, I1 with an open circuit, and VCC with ac ground, we arrive at the simplified model in Fig. 5.45(b), where R1 and RC appear in parallel and R2 acts as an emitter degeneration resistor. Equations (5.185)-(5.188) are therefore written respectively as Av = ,RCjjR1 1 gm + R2 + RB +1 Rin = RB + r +  + 1R2 Rout = RCjjR1: (5.191) (5.192) (5.193) Exercise What happens if a very large capacitor is tied from the emitter of Q1 to ground? Effect of Transistor Output Resistance The analysis of the degenerated CE stage has thus far neglected the Early effect. Somewhat beyond the scope of this book, the derivation of the circuit properties in the presence of this effect is outlined in Problem 48 for the interested reader. We nonetheless explore one aspect of the circuit, namely, the output resistance, as it provides the foundation for many other topologies studied later. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 217 (1) Sec. 5.3 Bipolar Amplifier Topologies 217 Our objective is to determine the output impedance seen looking into the collector of a degen- eiFfriagVt.Ae5d.=4tr6a1(nbs)i(,swgtorhoryu[?Fn).idgTi.no5gi.t4nh6cel(uaind)]pe.uRthteetecEramlalriflnryaolem.fAfFecicgto,.mw5.me7dothrnaamwt Ritshtoaeuktsem=haerlrlOe-siiisfgntRoaElwer=qitue0ivR.aAoleulsntot=,cRirrcoOuuti+t=aRs1Ein. Since gmv flows note that RE and from the output node r appear in parallel, into and P , resistors the current flrOowainndgRthEroaurgehnRotEinjjrseriiesse. qWuealretoadiiXly. Thus, R out iX Vin Q1 RE rπ vπ g m vπ rO vX P iX RE (a) (b) Figure 5.46 (a) Output impedance of degenerated stage, (b) equivalent circuit. v = ,iXREjjr; (5.194) where the negative sign arises because the that this rO carries voltage to a current of iX that across RE (,=g,mvv) and and positive side of hence sustains a v is at voltage ground. We also recognize of iX , gmvrO. Adding equating the result to vX , we obtain vX = iX , gmvrO , v = iX + gmiXREjjr rO + iXREjjr: (5.195) (5.196) It follows that Rout = 1 + gmREjjr rO + REjjr = rO + gmrO + 1REjjr: (5.197) (5.198) Recall from (5.146) that the intrinsic gain of the transistor, gmrO 1, and hence Rout  rO + gmrOREjjr  rO 1 + gmREjjr : (5.199) (5.200) Interestingly, by a factor of emitter degeneration 1 + gmREjjr. raises the output impedance from rO to the above value, i.e., The reader may wonder if the increase in the output resistance is desirable or undesirable. The “boosting” of output resistance as a result of degeneration proves extremely useful in circuit design, conferring amplifiers with a higher gain as well as creating more ideal current sources. These concepts are studied in Chapter 9. It RE is instructive to examine (5.200) r, we have REjjr ! r and for two special cases RE r and RE r. For Rout  rO1 + gmr  rO; (5.201) (5.202) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 218 (1) 218 Chap. 5 Bipolar Amplifiers because 1. Thus, the maximum resistance seen at the collector of a bipolar transistor is equFaolrtoRErO —if the degeneration r, we have REjjr impedance becomes ! RE and much larger than r. Rout  1 + gmRErO: (5.203) Thus, the output resistance is boosted by a factor of 1 + gmRE. In the analysis of circuits, we sometimes draw the transistor output resistance explicitly to emphasize its significance contain another rO. (Fig. 5.47). This representation, of course, assumes Q1 itself does not R out Q1 Vin rO RE r Figure 5.47 Stage with explicit depiction of O. Example 5.28 We wish to design a current source having a value of 1 mA and an output resistance of 20 k . The available bipolar transistor exhibits = 100 and VA = 10 V. Determine the minimum required value of emitter degeneration resistance. Solution Since rO = VA=IC = 10 k , degeneration must raise the output resistance by a factor of two. We postulate that the condition RE r holds and write 1 + gmRE = 2: (5.204) That is, Note that indeed r = =gm RE. RE = 1 gm = 26 : (5.205) (5.206) Exercise What is the output impedance if RE is doubled? Example 5.29 Calculate the output resistance of the circuit shown in Fig. 5.48(a) if C1 is very large. Solution Replacing Vb and C1 with an ac ground and I1 with an open circuit, we arrive at the simplified BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 219 (1) Sec. 5.3 Bipolar Amplifier Topologies R out R out 219 R out1 Q1 R1 Vb R2 C1 I1 Q1 R1 R2 Q1 R2 (a) (b) (c) Figure 5.48 (a) CE stage example, (b) simplified circuit, (c) resistance seen at the collector. model in collector oFfigQ. 15,.4w8e(bi)g.nSoirnecRe 1Rf1orapthpeeamrsoimnepnat,rarleledlucwinitgh the the resistance seen looking into the circuit to that in Fig. 5.48(c). In analogy with Fig. 5.40, we rewrite Eq. (5.200) as Rout1 = 1 + gmR2jjr rO: (5.207) Returning to Fig. 5.48(b), we have Rout = Rout1jjR1 = f 1 + gmR2jjr rOg jjR1: (5.208) (5.209) Exercise What is the output resistance if a very large capacitor is tied between the emitter of Q1 and ground? The procedure of progressively simplifying a circuit until it resembles a known topology proves extremely critical in our work. Called “analysis by inspection,” this method obviates the need for complex small-signal models and lengthy calculations. The reader is encouraged to attempt the above example using the small-signal model of the overall circuit to appreciate the efficiency and insight provided by our intuitive approach. Example 5.30 Determine the output resistance of the stage shown in Fig. 5.49(a). Solution Recall from Fig. 5.7 that the impedance seen at the collector is equal to rO if the base and emitter are (ac) grounded. Thus, Q2 can be replaced with rO2 [Fig. 5.49(b)]. From another perspective, Q2Nisowre,durOce2d to rO2 because its plays the role of base-emitter voltage is fixed by emitter degeneration resistance Vb1, for Qyi1e.ldIinngaanazleorgoygmw2itvh2F.ig. 5.40(a), we rewrite Eq. (5.200) as Rout = 1 + gm1rO2jjr1 rO1: (5.210) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 220 (1) 220 Chap. 5 Bipolar Amplifiers R out R out Q1 Vb2 Q2 Vb1 Q1 r O2 (a) (b) Figure 5.49 (a) CE stage example, (b) simplified circuit. Called a “cascode” circuit, this topology is studied and utilized extensively in Chapter 9. Exercise Repeat the above example for a “stack” of three transistors. CE Stage with Biasing Having learned the small-signal properties of the common-emitter amplifier and its variants, we now study a more general case wherein the circuit contains a bias network as well. We begin with simple biasing schemes described in Section 5.2 and progressively add complexity (and more robust performance) to the circuit. Let us begin with an example. Example 5.31 A student familiar with the CE stage and basic biasing constructs the circuit shown in Fig. 5.50 to amplify the signal produced by a microphone. Unfortunately, Q1 carries no current, failing to amplify. Explain the cause of this problem. VCC = 2.5 V 100 k Ω RB RC 1 kΩ X Vout Q1 Figure 5.50 Microphone amplifier. Solution Many microphones exhibit a small low-frequency resistance (e.g., 100 ). If used in this circuit, such a microphone creates a low resistance from the base of Q1 to ground, forming a voltage divider with RB and providing a very low base voltage. For example, a microphone resistance of 100 yields VX = 100 100 k+ 100  2:5 V  2:5 mV: (5.211) (5.212) Thus, the microphone low-frequency resistance disrupts the bias of the amplifier. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 221 (1) Sec. 5.3 Bipolar Amplifier Topologies 221 Exercise Does the circuit operate better if RB is halved? How should the circuit of Fig. 5.50 be fixed? Since only the signal generated by the micro- phone is of interest, a series capacitor can be inserted as depicted in Fig. 5.51 so as to isolate the dc biasing pendent of the of the amplifier from the microphone. resistance of the microphone because CT1hactairsr,ietshenobibaisapsociunrtreonftQ. T1hreemvaaliunesoinf dCe1- is chosen so that it provides a relatively low impedance (almost a short circuit) for the frequen- cies of interest. We say C1 is a “coupling” capacitor and the input of this stage is “ac-coupled” or “capacitively-coupled.” Many circuits employ capacitors to isolate the bias conditions from “undesirable” effects. More examples clarify this point later. VCC = 2.5 V 100 k Ω C1 RB RC 1 kΩ X Vout Q1 Figure 5.51 Capacitive coupling at the input of microphone amplifier. The foregoing observation suggests that the methodology illustrated in Fig. 5.9 must include an additional rule: replace all capacitors with an open circuit for dc analysis and a short circuit for small-signal analysis. Let us begin with the stage depicted in Fig. 5.52(a). For bias calculations, the signal source is set to zero and C1 is opened, leading to Fig. 5.52(b). From Section 5.2.1, we have VCC RB RC Y X Vout Q1 C1 VCC RB RC Y X Q1 v out X Q1 RC v in RB (c) (a) (b) Q1 RC RB R in2 R in1 (d) Q1 RB RC R out (e) Figure 5.52 (a) Capacitive coupling at the input of a CE stage, (b) simplified stage for bias calculation, (c) simplified stage for small-signal calculation, (d) simplified circuit for input impedance calculation, (e) simplified circuit for output impedance calculation. IC = VCC , VBE RB ; (5.213) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 222 (1) 222 Chap. 5 Bipolar Amplifiers VY = VCC , RC VCC , VBE RB : (5.214) To avoid saturation, VY  VBE. With the bias current known, the small-signal parameters gm, r, and rO can be calculated. We now turn our attention to small-signal analysis, considering the simplified circuit of Fig. 5.52(c). Here, C1 is replaced with a short and VCC with ac ground, but Q1 is maintained as a symbol. We attempt to solve the circuit by inspection: if unsuccessful, we will resort to using a small-signal model for Q1 and writing KVLs and KCLs. , IscnootuleTlrercheceest;otiicrn.ieigrs.cl,yugv,iiXvtReoBn=f bhFvyaiigsnv.noru5oet.g5e=af2vrf(Xdeccl)et=srosensoetfghmmtehbRevleovCslat,latwuhgeeeeoahCftaERvneoBcdo.erSeXinilcslueostlthoreantgveodalstianvgieFnigrgae.imn5a.f2irn9os,maenxthciedepebatalsfevoortolRtathgBee. vout vin = ,gmRC: (5.215) If VA 1, then vout vin = ,gmRCjjrO: (5.216) However, the input impedance is affected by RB [Fig. 5.52(d)]. Recall from Fig. 5.7 that the impedance seen looking into the base, Rin1, is equal to r if the emitter is grounded. Here, RB simply appears in parallel with Rin1, yielding Rin2 = rjjRB: (5.217) Thus, the bias resistor lowers the input impedance. Nevertheless, as shown in Problem 51, this effect is usually negligible. To determine the output impedance, we set the input source to zero [Fig. 5.52(e)]. Comparing this circuit with that in Fig. 5.32(b), we recognize that Rout remains unchanged: Rout = RCjjrO: (5.218) becIanussuembomthartye,rtmheinbailassorfeRsiBstoarr,eRshBo,rnteedgltiogigbrloyuinmdp. acts the performance of the stage shown in Fig. 5.52(a). Example 5.32 Having learned about ac coupling, the student in Example 5.31 modifies the design to that shown in Fig. 5.53 and attempts to drive a speaker. Unfortunately, the circuit still fails. Explain why. 100 k Ω RB RC VCC = 2.5 V 1 kΩ X Q1 C1 Figure 5.53 Amplifier with direct connection of speaker. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 223 (1) Sec. 5.3 Bipolar Amplifier Topologies 223 Solution Typical speakers incorporate a solenoid (inductor) to actuate a membrane. The solenoid exhibits a very low dc resistance, e.g., less than 1 . Thus, the speaker in Fig. 5.53 shorts the collector to ground, driving Q1 into deep saturation. Exercise Does the circuit operate better if the speaker is tied between the output node and VCC? Example 5.33 The student applies ac coupling to the output as well [Fig. 5.54(a)] and measures the quiescent  points to ensure proper biasing. The collector bias voltage is 1.5 V, the active region. However, the student still observes no gain in the icnidrcicuaitt.in(ag)tIhfaItSQ=1 o5pera1t0e,s 1in7 100 k Ω RB RC VCC = 2.5 V 1 kΩ X Q1 C2 C1 v out Q 1 R C 1 kΩ R sp 8 Ω v in 100 k Ω RB (a) (b) Figure 5.54 (a) Amplifier with capacitive coupling at the input and output, (b) simplified small-signal model. 1 A and VA = , compute the of the transistor. (b) Explain why the circuit provides no gain. Solution (a) A collector voltage of 1.5 V translates to a voltage drop of 1 V across RC and hence a collector current of 1 mA. Thus, VBE = VT ln IC IS = 796 mV: (5.219) (5.220) It follows that IB = VCC , VBE RB = 17 A; (5.221) (5.222) and = IC=IB = 58:8. (b) Speakers typically exhibit a low impedance in the audio frequency range, e.g., 8 . Draw- ing the ac equivalent as in Fig. 5.54(b), we note that the total resistance seen at the collector node is equal to 1 k jj8 , yielding a gain of jAvj = gmRCjjRS = 0:31 (5.223) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 224 (1) 224 Chap. 5 Bipolar Amplifiers Exercise Repeat the above example for RC = 500 . The design in Fig. 5.54(a) exemplifies an improper interface between an amplifier and a load: the output impedance is so much higher than the load impedance that the connection of the load to the amplifier drops the gain drastically. How can we remedy the problem of loading here? Since the voltage gain is proportional to gm, we can bias Q1 at a much higher current to raise the gain. This is studied in Problem 53. Alternatively, we can interpose a “buffer” stage between the CE amplifier and the speaker (Section 5.3.3). Let us now consider the biasing scheme shown in Fig. 5.15 and repeated in Fig. 5.55(a). To determine the bias conditions, we set the signal source to zero and open the capacitor(s). Equations (5.38)-(5.41) can then be used. For small-signal analysis, the simplified circuit in Fig. , jj 5.55(b) reveals a resemblance to that in Fig. 5.52(b), except that both R1 and R2 appear in parallel with the input. Thus, the voltage gain is still equal to gmRC rO and the input impedance is given by VCC R1 RC v out Q1 v in C1 R2 Q1 RC v in R1 R2 (a) (b) Figure 5.55 (a) Biased stage with capacitive coupling, (b) simplified circuit. Rin = rjjR1jjR2: (5.224) The output resistance is equal to RCjjrO. We next study the more robust biasing scheme of Fig. 5.19, repeated in Fig. 5.56(a) along with Eqs. an input coupling capacitor. The bias point is determined by opening C1 and (5.52) and (5.53). With the collector current known, the small-signal parameters following of Q1 can be computed. We also construct the simplified ac circuit shown in Fig. 5.56(b), noting that the voltage gain is not affected by R1 and R2 and remains equal to Av = ,RC 1 gm + RE ; (5.225) where Early effect is neglected. On the other hand, the input impedance is lowered to: Rin = r +  + 1RE jjR1jjR2; (5.226) whereas the output impedance remains equal to RC if VA = 1. As explained in Section 5.2.3, the use of emitter degeneration can effectively stabilize the bias point despite variations in and IS. However, as evident from (5.225), degeneration also lowers BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 225 (1) Sec. 5.3 Bipolar Amplifier Topologies 225 VCC R1 RC v out v in C1 R2 Q1 RE Q1 RC v in R1 R2 RE (a) (b) Figure 5.56 (a) Degenerated stage with capacitive coupling, (b) simplified circuit. the gain. Is it possible to apply degeneration to biasing but not to the signal? Illustrated in Fig. 5.57 is such a topology, where C2 is large enough to act as a short circuit for signal frequencies of interest. We can therefore write VCC R1 RC v in C1 R2 Q1 RE C2 Figure 5.57 Use of capacitor to eliminate degeneration. Av = ,gmRC (5.227) and Rin = rjjR1jjR2 Rout = RC: (5.228) (5.229) Example 5.34 Design the stage of Fig. 5.57 across RE = 400 mV, voltage impedance 2 k . Assume to satisfy the following conditions: IC = 1 mA, voltage g=ain10=0,2I0Sin=th5eau1d0i,o1f6r,eqanudenVcCyCra=ng2e:(52V0.Hz to 20 kHz), drop input Solution With IC = 1 mA  IE, the value of RE is equal to 400 . For the voltage gain to remain 2un6aff.e8cOtecdcbuyrridneggaetn2er0aHtiozn, t,htheemmaxaixmimumumimimpepdeadnacnecemoufsCt r1emmauisnt bbeelomwucrohusgmhalylle0r:1than11==ggmm = = 2:6 : 1 C2!  1 10  1 gm for ! = 2  20 Hz: (5.230) C R 8A common mistake here is to make the impedance of 1 much less than E . BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 226 (1) 226 Chap. 5 Bipolar Amplifiers Thus, C2  6120 F: (5.231) (This value is unrealistically large, requiring modification of the design.) We also have jAvj = gmRC = 20; (5.232) obtaining RC = 512 : (5.233) Since the voltage across RE is equal to 400 mV and VBE = VT lnIC=IS = 736 mV, we have VX = 1:14 V. Also, with a base current of 10 A, the current flowing through R1 and R2 must exceed 100 A to lower sensitivity to : VCC R1 + R2 10IB (5.234) and hence R1 + R2 25 k : (5.235) Under this condition, VX  R2 R1 + R2 VCC = 1:14 V; (5.236) yielding R2 = 11:4 k R1 = 13:6 k : (5.237) (5.238) We must now check to verify that this choice of R1 and R2 satisfies the condition Rin 2 k . That is, Rin = rjjR1jjR2 = 1:85 k : (5.239) (5.240) Uctoannfoa. lrFltoouwrnaeatxeaslmmy,apRlllee1,riacfnutdhrriResnc2tutlrhorwreoneutrgisthhsReet1intaopnu5dtIRBim2=ptehd5aa0nn1c0AeIeBaxn,cdaetswtsheivesectliyoll.stnToeogfrlceercmetaeItdiBnygitnmhteohrpeercosabelncleusmiltai,vtiwiotyne of VX , VCC R1 + R2 5IB (5.241) and R1 + R2 50 k : (5.242) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 227 (1) Sec. 5.3 Bipolar Amplifier Topologies Consequently, giving R2 = 22:4 k R1 = 27:2 k ; Rin = 2:14 k : 227 (5.243) (5.244) (5.245) Exercise Redesign the above stage for a gain of 10 and compare the results. We conclude our study of the CE stage with a brief look at the more general case depicted in Fig. 5.58(a), where the input signal source exhibits a finite resistance and the output is tied to a load RL. The biasing remains identical to that of Fig. 5.56(a), but RS and RL lower the voltage gain vout=vin. The simplified ac circuit division between RS and the impedance of Fig. seen at 5.58(b) node X ,reRv1ejajlRs 2Vjijnris+attenu+at1edRbEy the voltage , i.e., R1 RS C1 v in R2 VCC RC C2 Q1 RE v out RL RS X v out Q1 RC RL v in R1 R2 RE (b) (a) v out RS X Q1 RC RL v in R1 R2 RE (b) Figure 5.58 (a) General CE stage, (b) simplified circuit, (c) Thevenin model of input network. vX vin = R1jjR2jj r +  R1jjR2jj r +  + + 1RE 1RE + RS : The voltage gain from vin to the output is given by vout vin = vX vin  vout vX = , R1jjR2jj R1jjR2jj r r + +  + + 1RE 1RE + RS RCjjRL 1 gm + RE : (5.246) (5.247) (5.248) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 228 (1) 228 Chap. 5 Bipolar Amplifiers As expected, lower values of R1 and R2 reduce the gain. The above computation views the input network as a voltage divider. Alternatively, we can uti- lize a Thevenin in Fig. 5.58(c), equivalent the idea is to to include replace the effect of vin, RS and RRS1j,jRR21,wanitdh RvT2hoenv the voltage and RThev gain. : Illustrated vT hev = R1jjR2 R1jjR2 + RS vin RThev = RSjjR1jjR2: (5.249) (5.250) The resulting circuit resembles that in Fig. 5.43(a) and follows Eq. (5.185): Av =, 1 gm RCjjRL + RE + RT hev +1  R1jjR2 R1jjR2 + RS ; (5.251) where the second fraction on the right accounts for the voltage attenuation given by Eq. (5.249). The reader is encouraged to prove that (5.248) and (5.251) are identical. The two approaches described above exemplify analysis techniques used to solve circuits and gain insight. Neither requires drawing the small-signal model of the transistor because the reduced circuits can be “mapped” into known topologies. Figure 5.59 summarizes the concepts studied in this section. RC A v = − gmRC Headroom Gain R in R out RC rO A v = − gm (RC rO ) A v , R in R out RE R1 C1 R2 RC RE C2 Q1 RC R1 R2 Figure 5.59 Summary of concepts studied thus far. 5.3.2 Common-Base Topology Following our extensive study of the CE stage, we now turn our attention to the “common-base“ (CB) topology. Nearly all of the concepts described for the CE configuration apply here as well. We therefore follow the same train of thought, but at a slightly faster pace. Given the amplification capabilities of the CE stage, the reader may wonder why we study other amplifier topologies. As we will see, other configurations provide different circuit properties that are preferable to those of the CE stage in some applications. The reader is encouraged to review Examples 5.2-5.4, their resulting rules illustrated in Fig. 5.7, and the possible topologies in Fig. 5.28 before proceeding further. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 229 (1) Sec. 5.3 Bipolar Amplifier Topologies 229 Figure 5.60 shows the CB stage. The input is applied to the emitter and the output is sensed at the collector. Biased at a proper voltage, the base acts as ac ground and hence as a node “common” to the input and output ports. As with the CE stage, we first study the core and subsequently add the biasing elements. Figure 5.60 Common-base stage. RC Q1 VCC Vout Output Sensed at Collector Vb v in Input Applied to Emitter Analysis of CB Core How does the CB stage of Fig. 5.61(a) respond to an input signal?9 If Vin goes up by a amount because the small amount V , the base-emitter base voltage is fixed. Consequently, vthoeltacgoelleocftoQr1cudrercernetafsaelslsbbyythgemsamVe, allowing Vout to rise by gmV RC. We therefore surmise that the small-signal voltage gain is equal to VCC RC Vout g m ∆V R C Q1 Vb Vin ∆V rπ vπ v in g m v π v out RC (a) (b) Figure 5.61 (a) Response of CB stage to small input change, (b) small-signal model. Av = gmRC: (5.252) Interestingly, this expression is identical to the gain of the CE topology. Unlike the CE stage, however, Vout. this circuit exhibits a positive gain because an increase in Vin leads to an increase in Let us confirm the above results with the aid of the small-signal equivalent depicted in Fig. 5.61(b), where the Early effect is neglected. Beginning with the output node, we equate the current flowing through RC to gmv: , vout RC = gmv; (5.253) Q 9Note that the topologies of Figs. 5.60-5.61(a) are identical even though 1 is drawn differently. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 230 (1) 230 Chap. 5 Bipolar Amplifiers obtaining v = ,vout=gmRC. Considering the input node next, we recognize that v = ,vin. It follows that vout vin = gmRC: (5.254) As with the CE stage, the CB topology suffers from trade-offs between the gain, the voltage headroom, and the I/O impedances. We first examine the circuit’s headroom limitations. How  isrnehgpoiuuotlndbrytehqaebuboirauestse8V0vB0oElmtagVe,0,aVanndbd,tihVneBFoCiugt.pu50t.6(m1fo(uars)tnbrpeenmcdaheionvsiehcnieg?sh)R.eTrehcthaualsln, tVohbratmeqtuhuseatlortepomerVaabitn.ioFhnoigrihneextrhatemhaapncletti,hvieef the dc level of the input is zero (Fig. 5.62), then the output must not fall below approximately , 800 mV, i.e., the voltage drop across RC cannot exceed VCC VBE. Similar to the CE stage limitation, this condition translates to VCC RC VCC − VBE ~0V ~800 mV 800 mV Vb 0 t Vin Figure 5.62 Voltage headroom in CB stage. Av = IC VT  RC = VCC , VT VBE : (5.255) (5.256) Example 5.35 The voltage produced by an electronic thermometer is equal to 600 mV at room temperature. Design a CB gain. Assume stage to sense the thermometer VCC = 1:8 V, IC = 0:2 mA, IS =vol5tage10a,nd17aAm,palnifdy the change = 100. with maximum Solution Illustrated in Fig. 5.63(a), the circuit must operate properly with an input level of 600 mV. Thus, Vb = VBE + 600 mV = VT lnIC=IS + 600 mV = 1:354 V. To avoid saturation, the collector voltage must not fall below the base voltage, thereby allowing a maximum voltage drop across RC equal to 1:8 V , 1:354 V = 0:446 V. We can then write Av = gmRC = IC RC VT = 17:2: (5.257) (5.258) (5.259) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 231 (1) Sec. 5.3 Bipolar Amplifier Topologies RC Q1 VCC Vout Vb Vin 600 mV 231 RC Q1 Vout IB Vin 600 mV VCC R1 I1 R2 Thermometer (b) (a) Figure 5.63 (a) CB stage sensing an input, (b) bias network for base. The gain reader is remains encouraged to repeat the relatively independent of tphreobbilaesmcwurirtehnIt.C10= 0:4 mA to verify that the maximum We must now generate Vb. A simple Fig. 5.63(b). To lower sensitivity to , Thus, R1 + R2 = 90 k . Also, approach is to we choose I1 employ  10IB a resistive  20 A divider as depicted in  VCC=R1 + R2. Vb  R2 R1 + R2 VCC (5.260) and hence R2 = 67:7 k R1 = 22:3 k : (5.261) (5.262) Exercise Repeat the above example if the thermometer voltage is 300 mV. Let us now compute the I/O impedances of the CB topology so as to understand its capabil- ities in interfacing with preceding and following stages. The rules illustrated in Fig. 5.7 prove extremely useful here, obviating the need for small-signal equivalent circuits. Shown in Fig. 5.64(a), the simplified ac circuit reveals that Rin is simply the impedance seen looking into the emitter with the base at ac ground. From the rules in Fig. 5.7, we have Rin = 1 gm (5.263) 1 IifCV=A = 1 mA . The input impedance (in sharp contrast to the of the CB stage is therefore corresponding value for a CE relatively low, stage, =gm). e.g., 26 for 10This example serves only as an illustration of the CB stage. A CE stage may prove more suited to sensing a thermometer voltage. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 232 (1) 232 Chap. 5 Bipolar Amplifiers VCC RC VCC RC Q1 ac R in IX Q1 Vb VX ∆V (a) (b) Figure 5.64 (a) Input impedance of CB stage, (b) response to a small change in input. The input impedance of the CB stage can also be determined intuitively [Fig. 5.64(b)]. Sup- pose a voltage source VX tied to the emitter of Q1 changes by a small amount V . The base- emitter voltage therefore changes by the same amount, leading to a change in the collector current equal to gmV . Since the collector current flows through the input source, the current supplied by VX also changes by gmV . Consequently, Rin = VX =IX = 1=gm. Does an amplifier with a low input impedance find any practical use? Yes, indeed. For exam- ple, many stand-alone high-frequency amplifiers are designed with an input resistance of 50 to provide “impedance matching” between modules in a cascade and the transmission lines (traces on a printed-circuit board) connecting the modules (Fig. 5.65).11 50−Ω Transmission Line 50−Ω Transmission Line Figure 5.65 System using transmission lines. 50 Ω 50 Ω The output impedance of the CB stage is computed with the aid of Fig. 5.66, where the input voltage seen at source is set to zero. We note that Rout = Rout1jjRC, where Rout1 the collector with the emitter grounded. From the rules of Fig. 5.7, we is the impedance have Rout1 = rO and hence rO Figure 5.66 Output impedance of CB stage. Q1 R out1 ac RC R out Rout = rOjjRC (5.264) 11If the input impedance of each stage is not matched to the characteristic impedance of the preceding transmission line, then “reflections” occur, corrupting the signal or at least creating dependence on the length of the lines. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 233 (1) Sec. 5.3 Bipolar Amplifier Topologies 233 or Rout = RC if VA = 1: (5.265) Example 5.36 A common-base amplifier is designed for an input impedance of Rin and an output impedance of Rout. Neglecting the Early effect, determine the voltage gain of the circuit. Solution Since Rin = 1=gm and Rout = RC, we have Av = Rout Rin : (5.266) Exercise Compare this value with that obtained for the CE stage. From Eqs. (5.256) and (5.266), we conclude that the CB stage exhibits a set of trade-offs similar to those depicted in Fig. 5.33 for the CE amplifier. It is instructive to study the behavior of the CB topology in the presence of a finite source resistance. Shown in Fig. 5.67, such a circuit suffers from signal attenuation from the input to node X, thereby providing a smaller voltage gain. More specifically, since the impedance seen looking into the emitter of Q1 (with the base grounded) is equal to 1=gm (for VA = 1), we have VCC RC v out RS Q1 X v in 1 gm v in Figure 5.67 CB stage with source resistance. RS X 1 gm 1 vX = RS gm + 1 gm vin = 1 + 1 gmRS vin: (5.267) (5.268) We also recall from Eq. (5.254) that the gain from the emitter to the output is given by vout vX = gmRC: (5.269) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 234 (1) 234 Chap. 5 Bipolar Amplifiers It follows that vout vin = 1 gmRC + gmRS = RC 1 gm + RS ; (5.270) (5.271) a result identical to that of the CE stage (except for a negative sign) if RS is viewed as an emitter degeneration resistor. Example 5.37 A common-base stage is designed to amplify an RF signal received by a 50- antenna. Determine the required bias current if the input impedance of the amplifier must “match” the impedance of the antenna. What is the voltage gain if the CB stage also drives a 50- load? Assume VA = 1. Solution Figure 5.68 depicts the amplifier12 and the equivalent circuit with the antenna modeled by a Antenna RC Q1 VCC v out VB RC Antenna RS Q1 VCC v out VB v in Figure 5.68 (a) CB stage sensing a signal received by an antenna, (b) equivalent circuit. voltage source, vin, and a resistance, RS = 50 . For impedance matching, it is necessary that the input impedance of the CB core, 1=gm, be equal to RS, and hence IC = gmVT = 0:52 mA: (5.272) (5.273) If RC itself is replaced by a 50- load, then Eq. (5.271) reveals that Av = RC 1 gm + RS = 12: (5.274) (5.275) The circuit is therefore not suited to driving a 50- load directly. 12The dots denote the need for biasing circuitry, as described later in this section. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 235 (1) Sec. 5.3 Bipolar Amplifier Topologies 235 Exercise What is the voltage gain if a 50- resistor is also tied from the emitter of Q1 to ground? Another interesting point of contrast between the CE and CB stages relates to their cur- rent gains. The CB stage displays a current gain of unity because the current flowing into the emitter simply emerges from the collector (if the base current is neglected). On the other hand, as mentioned in Section 5.3.1, AI = for the CE stage. In fact, in the above example, iin = vin=RS + 1=gm, which upon flowing through RC, yields vout It is thus not surprising that the voltage gain does not exceed 0.5 if RC =  RC vin =RS RS. + 1=gm. As with the CE stage, we may desire to analyze the CB topology in the general case: with 1 emitter degeneration, VA , and a resistance in series with the base [Fig. 5.69(a)]. Outlined in Problem 64, this analysis is somewhat beyond the scope of this book. Nevertheless, it is in- VCC RC v out rO RE VB Q1 RB rO RE Q1 R out1 RC R out2 v in (a) (b) Figure 5.69 (a) General CB stage, (b) output impedance seen at different nodes. 1 structive to consider a special case where RB = 0 but VA , and we wish to compute the output impedance. As illustrated in Fig. 5.69(b), Rout is equal to RC in parallel with the impedance seen looking into the collector, Rout1. But Rout1 is identical to the output resistance of an emitter-degenerated common emitter stage, i.e., Fig. 5.46, and hence given by Eq. (5.197): Rout1 = 1 + gmREjjr rO + REjjr: (5.276) It follows that Rout = RCjj f 1 + gmREjjr rO + REjjrg : (5.277) The reader may have recognized that the output impedance of the CB stage is equal to that of the CE stage. Is this true in general? Recall that the output impedance is determined by setting the input source to zero. In other words, when calculating Rout, we have no knowledge of the input terminal of the circuit, as illustrated in Fig. 5.70 for CE and CB stages. It is therefore no coincidence that the output impedances are identical if the same assumptions are made for both circuits (e.g., identical values of VA and emitter degeneration). Example 5.38 Old wisdom says “the output impedance of the CB stage is substantially higher than that of the CE stage.” This injected into the 5.71(a)]. On the bocaltahsieemrwhhisainljedu,tshtiieffiaceodclolbenycsttotahrnevt otcelutsartrgseenilitlsuivsstardrariteaedwd,nIinCfroFemxigh.itbh5ie.t7se1am. sIiltfoteapre,cIeoCqnusdtaailsntptolacryuO,sr1rem[nFuticgihs. less dependence on the collector voltage. Explain why these tests do not represent practical situations. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 236 (1) 236 Chap. 5 Bipolar Amplifiers VCC RC Q1 v out v in RE VCC RC Q1 RE R out VCC RC v out Vb Q1 v in RE VCC RC Q1 R out RE (a) (b) Figure 5.70 (a) CE stage and (b) CB stage simplified for output impedance calculation. VCC IC IC IB Q1 V1 (a) IC IC VB Q1 V1 IE V1 V1 (b) Open rπ vπ g m vπ rO R out rπ vπ g m vπ rO R out Open (c) (d) Figure 5.71 (a) Resistance seens at collector with emitter grounded, (b) resistance seen at collector with an ideal current source in emitter, (c) small-signal model of (a), (d) small-signal model of (b). Solution The principal issue in these tests relates to the use of current sources to drive each stage. From a small-signal point of view, the two circuits reduce to those depicted in Figs. 5.71(c) and (d), with current sources IB and IE replaced with open circuits because they are constant. In Fig. 5.71(c), the current through r is zero, yielding gmv = 0 and hence Rout = rO. On the other hand, Fig. 5.71(d) resembles an emitter-degenerated stage (Fig. 5.46) with an infinite emitter resistance, exhibiting an output resistance of Rout = 1 + gmREjjr rO + REjjr = 1 + gmrrO + r  rO + r; (5.278) (5.279) (5.280) which is, of course, much greater than rO. In practice, however, each stage may be driven by a voltage source having a finite impedance, making the above comparison irrelevant. Exercise Repeat the above example if a resistor of value R1 is inserted in series with the emitter. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 237 (1) Sec. 5.3 Bipolar Amplifier Topologies 237 1 Another special case of the topology shown in Fig. 5.69(a) occurs if VA = but RB 0. Since this case does not reduce to any of the configurations studied earlier, we employ the small- avsthinged=nvraholelmtn=acgoe,edevavltosunh=too=dwe,gnmPviro:nutFR=iCgg.m5=.R72C,tv.ooTustthu=edycuRirtCrsebn.etMhflauovwlitoiiprn.lgyAitnshgruotshuuigashl,curwrere(wnatnribdteyRgRBmB)v+is = ,vout=RC then equal to r, we obtain RB rπ vπ P v in RE gm vπ v out RC Figure 5.72 CB stage with base resistance. We also write a KCL at P : vP = , ,vout RC RB + r = vout RC RB + r: v r + gmv = vP , vin RE ; (5.281) (5.282) (5.283) that is, 1 r + gm ,vout gmRC = vout RC RB + RE r , vin : (5.284) It follows that vout vin =  + RC 1RE + RB + r : Dividing the numerator and denominator by + 1, we have vout vin  RE + RC RB +1 + 1 gm : (5.285) (5.286) As expected, the gain is positive. Furthermore, this expression is identical to that in (5.185) for the CE stage. Figure 5.73 illustrates the results, revealing that, except for a negative sign, the two stages exhibit equal gains. deliberately. As explained later Note that RB in this section, degrades RB may the gain and is not added to the arise from the biasing network. circuit Let us now determine the input impedance of the CB stage in the presence of a resistance in 1 series with the base, still assuming VA = . From the small-signal equivalent circuit shown in BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 238 (1) 238 Chap. 5 Bipolar Amplifiers VCC RC RB v out Q1 v in RE RB v in VCC RC v out Q1 RE Figure 5.73 Comparison of CE and CB stages with base resistance. Fig. 5.74, we recognize that r and RB form a voltage divider, thereby producing13 RB rπ vπ g m v π v out RC vX iX Figure 5.74 Input impedance of CB stage with base resistance. v = , r r + RB vX : (5.287) Moreover, KCL at the input node gives v r + gmv = ,iX: (5.288) Thus, 1 r + gm ,r r + RB vX = ,iX (5.289) and vX iX = r + RB +1  1 gm + RB +1 : (5.290) (5.291) Note that Rin = 1=gm if RB = 0, an expected result from the rules illustrated in Fig. 5.7. Interestingly, the base resistance is divided by + 1 when “seen” from the emitter. This is in contrast to the case of emitter degeneration, where the emitter resistance is multiplied by + 1 13 Alternatively, across r. the current through r + RB is equal to vX =r + RB , yielding a voltage of ,rvX =r + RB  BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 239 (1) Sec. 5.3 Bipolar Amplifier Topologies 239 when seen from the base. Figure 5.75 summarizes the two cases. Interestingly, these results remain independent of RC if VA = 1. RB VA = Q1 VA = Q1 1 gm + RB β +1 r π + (β+1) RE RE Figure 5.75 Impedance seen at the emitter or base of a transistor. Example 5.39 1 Determine the impedance identical and VA = . seen at the emitter of Q2 in Fig. 5.76(a) if the two transistors are VCC VCC RB Q1 RC v out g1m1+ RB β +1 RC v out Q2 Q2 Figure 5.76 R eq RX (a) (a) Example of CB stage, (b) simplified circuit. RX (b) Solution The circuit tance equal Req, which etomtphlaotysseQen2aatsthaeceommimtteorno-bf aQse1.dTehvuicse,,wbeutmwuistthfiirtsstboabsteaitnietdhetoeqaufiivnaitleensterreiessisrteasnicse- from Eq. (5.291) is simply equal to Req = 1 gm1 + RB +1 : (5.292) Reducing the circuit to that shown in Fig. 5.76(b), we have RX = 1 gm2 + = 1 gm2 + Req + 1 + 1 1 1 gm1 + RB +1 : (5.293) (5.294) Exercise What happens if a resistor of value R1 is placed in series with the collector of Q1? CB Stage with Biasing Having learned the small-signal properties of the CB core, we now extend our analysis to the circuit including biasing. An example proves instructive at this point. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 240 (1) 240 Chap. 5 Bipolar Amplifiers Example 5.40 The student in Example 5.31 decides to incorporate ac coupling at the input of a CB stage to ensure the bias is not affected by the signal source, drawing the design as shown in Fig. 5.77. Explain why this circuit does not work. VCC RC Vout Q1 Vb Vin C1 Figure 5.77 CB stage lacking bias current. Solution Unfortunately, the design provides no dc path for the emitter current of Q1, forcing a zero bias current and hence a zero transconductance. The situation is similar to the CE counterpart in Example 5.5, where no base current can be supported. Exercise In what region does Q1 operate if Vb = VCC? Example 5.41 Somewhat embarrassed, the student quickly connects the emitter to ground so that VBE = Vb and a reasonable collector current can be established (Fig. 5.78). Explain why “haste makes waste.” VCC RC v out Q1 Vb v in C1 Figure 5.78 CB stage with emitter shorted to ground. Solution As with Example 5.6, the student has shorted the signal to ac ground. That is, the emitter voltage is equal to zero regardless of the value of vin, yielding vout = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 241 (1) Sec. 5.3 Bipolar Amplifier Topologies 241 Exercise Does the circuit operate better if Vb is raised? The above examples imply that the emitter can remain neither open nor shorted to ground, thereby requiring some bias element. path for the bias current at the cost of consists of two parallel components: (Sl1oh)wo1we=rnginmign,tFsheiegein.n5lpo.7uo9tki(iman)gpies“duaapnn”ecxiena.tmWo ptehleree,ecwmohgienttrieezreR(twEhiatpthrRothvineidbneaosswae at ac ground) and (2) RE, seen looking “down.” Thus, VCC RC VCC RC v out v out 1 Q1 gm Vb Q1 X Vb v in C1 RE RE v in R S C1 RE R in (a) (b) Figure 5.79 (a) CB stage with biasing, (b) inclusion of source resistance. Rin = 1 gm jjRE: (5.295) As with the input biasing network in the CE stage (Fig. 5.58), the reduction in Rin manifests itself if the source voltage exhibits a finite output resistance. Depicted in Fig. 5.79(b), such a circuit attenuates the signal, lowering the overall voltage gain. Following the analysis illustrated in Fig. 5.67, we can write vX vin = Rin Rin + RS = 1 gm 1 gm jjRE jjRE + RS = 1 + 1 + 1 gmRE RS : (5.296) (5.297) (5.298) Since vout=vX = gmRC, vout vin = 1 + 1 + 1 gmRERS  gmRC : (5.299) As usual, we have preferred solution by inspection over drawing the small-signal equivalent. The reader may see a contradiction in our thoughts: on the one hand, we view the low input impedance of the CB stage a useful property; on the other hand, we consider the reduction of the input impedance due to RE undesirable. To resolve this apparent contradiction, we must distinguish between the two components 1=gm and RE, noting that the latter shunts the input BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 242 (1) 242 Chap. 5 Bipolar Amplifiers VCC RC v out i in Q1 i2 Vb v in R S C1 i1 RE Figure 5.80 Small-signal input current components in a CB stage. source current to ground, thus “wasting” the signal. As shown in Fig. 5.80, iin splits two ways, with only i2 reaching RC remains constant, then i2 and also contributing to the output signal. If falls.14 Thus, reduction of Rin due RE to decreases while 1=gm RE is undesirable. By contrast, if 1=gm decreases while RE remains constant, then i2 rises. For RE to affect the input impedance negligibly, we must have RE 1 gm (5.300) and hence ICRE VT : (5.301) TusheaHdtoiisnw, tthihseetCdhcEe vbsotaalstgaeeg.veSodlhtroaogwpena, ciVnrboF,ssiggRe.n5Ee.r8ma1teu(adts)?,bsWeucemhucaacnhtogeprmoelapotlgeoyrytmhaaunrsetVseiTsnt.sivueredIi1viderIsBimtoilamrintoimthizaet sensitivity to , yielding VCC VCC VCC RC Q1 C1 RE R1 IB I1 Vb R2 RC Q1 RE R Thev VThev RC R1 Q1 R2 CB RE (a) (b) (c) Figure 5.81 (a) CB stage with base bias network, (b) use of Thevenin equivalent, (c) effect of bypass capacitor. Vb  R2 R1 + R2 VCC : (5.302) However, recall from Eq. (5.286) that a resistance in series with the base reduces the voltage gain of the CB stage. Substituting a Thevenin equivalent for R1 and R2 as depicted in Fig. 5.81(b), 14In the extreme case, RE = 0 (Example 5.41) and i2 = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 243 (1) Sec. 5.3 Bipolar Amplifier Topologies 243 we recognize that a resistance of RT hev = R1jjR2 now appears in series with the base. For this reason, a “bypass capacitor” is often tied from the base to ground, acting as a short circuit at frequencies of interest [Fig. 5.81(c)]. Example 5.42 Design IS = 5 a C1B0,s1ta6gAe,(FViAg.=5.182,) for a voltage gain of 10 and = 100, and VCC = 2:5 V. an input impedance of 50 . Assume VCC RC Vout R1 C1 Q1 Vin Vb R2 CB RE I C RE Figure 5.82 Example of CB stage with biasing. Solution We RE begin by . Thus, selecting RE and hence 1=gm, e.g., RE = 500 , to minimize the undesirable effect of Rin  1 gm = 50 (5.303) IC = 0:52 mA: (5.304) If the base is bypassed to ground Av = gmRC; (5.305) yielding RC = 500 : (5.306)  We now determine the base bias resistors. Since the voltage drop across RE is equal to 500 0:52 mA = 260 mV and VBE = VT lnIC=IS = 899 mV, we have Vb = IERE + VBE = 1:16 V: (5.307) (5.308) Selecting the current through R1 and R2 to be 10IB = 52 A, we write Vb  R2 R1 + R2 VCC : VCC R1 + R2 = 52 A: (5.309) (5.310) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 244 (1) 244 Chap. 5 Bipolar Amplifiers It follows that R1 = 25:8 k R2 = 22:3 k : (5.311) (5.312) The last step in the design is to compute the required values of C1 and CB according to the signal frequency. For example, if the amplifier is used at the receiver front end of a 900-MHz ciTadnpeehlgpuslrplesiahr,cdiaoieattnssitoieiow,nmntsih.ptsheCeudiotcmhanhnespaceeeseqdm,cuajeeinCtlntlc1eptel!rhsyoj,oo,nfffo1eCQr,s,m!11w,au=enCstdm12rCaepymBlacaymhisno9uo0amss0teurboMcjelCheHs1luse!zfismfijs:,cit1ilheaa=nrnttloy11=sR=gmgmSmali=ln=a2tF50t0ihgtio.s5.ef.nrI6ens7quhuraieegnnnhdce-ypgE.elqAirg.fpoi(bpr5lmee.2aagr7nia1nci)nge. C1 = 20gm ! = 71 pF: (5.313) (5.314) Since RB= the + impedance of CB 1 in Eq. (5.286), appears in we require series that with the base and plays a role similar to the term 1 +1 1 CB ! = 1 20 1 gm (5.315) and hence CB = 0:7 pF: (5.316) (A common mistake is to make than with respect to 1=gm.) the impedance of CB negligible with respect to R1jjR2 rather Exercise Design the above circuit for an input impedance of 100 . 5.3.3 Emitter Follower Another important circuit topology is the emitter follower (also called the “common-collector” stage). The reader is encouraged to review Examples 5.2 - 5.3, rules illustrated in Fig. 5.7, and the possible topologies in Fig. 5.28 before proceeding further. For the sake of brevity, we may also use the term “follower” to refer to emitter followers in this chapter. Shown in Fig. 5.83, the emitter follower senses the input at the base of the transistor and produces the output at the emitter. The collector is tied to VCC and hence ac ground. We first study the core and subsequently add the biasing elements. VaEconimndlleihrtcitestenoerscr eFabnaoydlhaloiegsmwmhieeatrtrlelVrCaocmouutror.eruFennrtotHsm.oTVwaihnnedo,othhtehiesgerhtphbeeearrsfeseomp-leeliomcttwteiivtreteerc,ruiinrvfroFwelintegat.gat5rsea.s8nou4sfml(Qaaet),e1rfseotetsronpedoaxsnagdtmroetpoailntaeec,rcrVehdaoarsuonetpg,iersaaiccnirsooiVnnsissgntaR?tnhEItef, then VBE must rise and so must IE, requiring that Vout go up. Since Vout changes in the same BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 245 (1) Sec. 5.3 Bipolar Amplifier Topologies 245 Vin Input Applied to Base VCC Output Sensed Q1 at Emitter Vout RE Figure 5.83 Emitter follower. direction as Vin, we expect the voltage gain to be positive. Note that Vout is always lower than Vin by an amount equal to VBE, and the circuit is said to provide “level shift.” VCC Vin Q1 Vout RE Vin1 + ∆V in Vin1 VBE1 Vout1 Vout1 + ∆Vout VBE2 (a) (b) Figure 5.84 (a) Emitter follower sensing an input change, (b) response of the circuit. Another interesting and important observation here is than the change in Vin. Suppose Vin increases from Vin1 that the to Vin1 +chanVgieninanVdouVtouctanfrnoomt bVeoluatr1gteor Vout1 + Vout [Fig. 5.84(b)]. If the output changes by a greater amount than the input, Vout Vin, then VBE2 must be less than VBE1. But this means the emitter current also decreases and so does IERE = Vout, Vin, implying that the fcoolnlotrwaedricetxinhgibtihtseaavssoultmagpetiognainthlaetssVothuatnhuans iitnyc.1r5eased. Thus, Vout The reader may wonder if an amplifier with a subunity gain has any practical value. As ex- plained later, the input and output impedances of the emitter follower make it a particularly useful circuit for some applications. 1 Let us now derive the small-signal properties of the follower, first assuming VA = . Shown in Fig. 5.85, the equivalent circuit yields v in rπ vπ g m vπ v out RE Figure 5.85 Small-signal model of emitter follower. and hence v r + gmv = vout RE v = r + 1  vout RE : 15In an extreme case described in Example 5.43, the gain becomes equal to unity. (5.317) (5.318) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 246 (1) 246 Chap. 5 Bipolar Amplifiers We also have vin = v + vout: Substituting for v from (5.318), we obtain vout vin = 1+ 1 r + 1  1 RE  RE RE + 1 gm : (5.319) (5.320) (5.321) The voltage gain is therefore positive and less than unity. Example 5.43 In integrated circuits, the follower is typically realized as shown in Fig. 5.86. Determine the 1 voltage gain if the current source is ideal and VA = . VCC Vin Q1 Vout I1 Figure 5.86 Follower with current source. Solution Since the emitter resistor is replaced with an ideal current source, the value of RE in Eq. (5.321) must tend to infinity, yielding Av = 1: (5.322) This result can also be derived intuitively. A that VBE = VT lnIC=IS remain constant. constant current Writing Vout = Vsoinur,ceVflBoEw,inwgethrercoouggnhiQze1threaqt uVioruest exactly follows Vin if VBE is constant. Exercise Repeat the above example if a resistor of value R1 is placed in series with the collector. Equation (5.321) suggests that the emitter follower acts as a voltage divider, a perspective that can be reinforced by an alternative analysis. Suppose, as shown in Fig. 5.87(a), we wish to 1 model vin and output voltage Thus, vThev = and is equal to p1Qvr=io1ngd.mbuTy.cheTaedhTTebhhyceeivvQrece1nuniii[ntnFoeirgfeq.sFui5siivg.t8aa.7nl5e(c.nb8et)7.i]s(,Taaoh)sbetthiafTeiQnhreee1fdvoeobrnpeyiernsreeavdttouteislcnteagwsgtiethtoheistRihngaEpitvuse=thntoobwzyen(rtEhionex[aFFomiipggep..nl55e-..c885i77.r4c((c3du)))i]t., confirming operation as a voltage divider. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 247 (1) Sec. 5.3 Bipolar Amplifier Topologies 247 VCC Q1 v in v out RE VCC Q1 v in v out = v in (a) (b) VCC Q1 v Thev = v in RThev = 1 gm v out RE R Thev (c) (d) Figure 5.87 (a) Emitter follower stage, (b) Thevenin voltage , (c) Thevenin resistance, (d) simplified circuit. Example 5.44 1 Determine the voltage gain of a follower driven by a finite source impedance of RS [Fig. 5.88(a)] if VA = . VCC VCC RS RS Q1 Q1 v in v out RE R Thev (a) (b) v Thev = v in 1 gm + RS β+ 1 v out RE (c) Figure 5.88 (a) Follower with source impedance, (b) Thevenin resistance seen at emitter, (c) simplified circuit. Solution We model voltage is as RS= +evqinu1,alR+tSo1,v=aignnmd. .FQFu1irgtbhuyereram5To.8hr8ee(,vcte)hnedineTpehiqceutvsievtnhailenenerqte.usTiisvhtaaelnercneeat dc[Feirricgcu.ait5n,.r8seh8vo(ebwa)l]tihnisagtgtthihvaeetnopbeyn(-5ci.2rc9u1i)t vout vin = RE + RE RS +1 + 1 gm : (5.323) This result can also be obtained by solving the small-signal equivalent circuit of the follower. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 248 (1) 248 Chap. 5 Bipolar Amplifiers Exercise What happens if RE = 1? In order to appreciate the usefulness of emitter followers, let us compute their input and output impedances. In the equivalent circuit of Fig. 5.89(a), we have iXr = v. Also, the current iX and gmv flow voltages across rthraonudghRRE Ean, dpreoqduuactiinngg a voltage the result drop to vX equal to iX , we have + gmvRE. Adding the iX VCC VCC RC 0 vX rπ vπ g m v π Q1 Q1 RE R in RE R in RE (a) (b) Figure 5.89 (a) Input impedance of emitter follower, (b) equivalence of CE and follower stages. vX = v + iX + gmvRE = iXr + iX + gmiXrRE; (5.324) (5.325) and hence vX iX = r + 1 + RE : (5.326) This expression is identical to that in Eq. (5.162) derived for a degenerated CE stage. This is, of course, no coincidence. Since the input impedance of the CE topology is independent of the 1 collector resistor (for VA = ), its value remains unchanged if RC = 0, which is the case for an emitter follower [Fig. 5.89(b)]. The key observation here is that the follower “transforms” the load resistor, RE, to a much larger value, thereby serving as an efficient “buffer.” This concept can be illustrated by an exam- ple. Example 5.45 A CE stage exhibits a voltage gain of 20 and an output resistance of 1 k . Determine the voltage gain of the CE amplifier if (a) The stage drives an 8- speaker directly. (b) An emitter follower biased at a current of 5 mA is interposed between the CE stage and the speaker. Assume = 100, VA = 1, and the follower is biased with an ideal current source. Solution (a) As depicted in Fig. 5.90(a), the equivalent resistance seen at the collector is now given by t2h0eparRalClejlj8com=bRinCati=on0o:1f5R9.CTahnedvtohletagspeegaakienr impedance, Rsp, reducing the therefore degrades drastically. gain from 20 to BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 249 (1) Sec. 5.3 Bipolar Amplifier Topologies 249 VCC 1 kΩ RC R sp Q1 C1 v in VCC 1 kΩ RC Q2 Q1 R sp v in R in1 I 1 C1 (a) (b) Figure 5.90 (a) CE stage and (b) two-stage circuit driving a speaker. (b) From the arrangement in Fig. 5.90(b), we note that Rin1 = r2 +  + 1Rsp = 1058 : (5.327) (5.328) Thus, the voltage gain of the CE stage drops from 20 to 20  RCjjRin1=RC = 10:28, a substantial improvement over case (a). Exercise Repeat the above example if the emitter follower is biased at a current of 10 mA. We now calculate the output impedance of the follower, assuming the circuit is driven by a source impedance RS [Fig. 5.91(a)]. Interestingly, we need not resort to a small-signal model here as Rout can be obtained by inspection. As illustrated in Fig. 5.91(b), the output resistance can be viewed as the parallel combination of two components: one seen looking “up” into the emitter and 1 + 1=gm, another looking and hence “down” into RE. From Fig. 5.88, the former is equal to RS= + VCC RS Q1 RE R out VCC RS Q1 1 gm + RS β+ 1 RE RE (a) (b) Figure 5.91 (a) Output impedance of a follower, (b) components of output resistance. Rout = RS +1 + 1 gm jjRE: (5.329) This result can also be derived from the Thevenin equivalent shown in Fig. 5.88(c) by setting vin to zero. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 250 (1) 250 Chap. 5 Bipolar Amplifiers Equation (5.329) reveals another important attribute of the follower: the circuit transforms the source impedance, RS, to a much lower value, thereby providing higher “driving” capability. We say the follower operates as a good “voltage buffer” because it displays a high input impedance (like a voltmeter) and a low output impedance (like a voltage source). Effect of Transistor Output Resistance Our analysis of the follower has thus far neglected the Early effect. Fortunately, the results obtained above can be readily modified to reflect this nonideality. Figure 5.92 illustrates a key point that facilitates the analysis: in small-signal operation, rO appears in parallel with RE. We can therefore rewrite Eqs. (5.323), (5.326) and (5.329) as VCC RS rO v in Q1 RE RS v in Q1 RE rO Figure 5.92 Follower including transistor output resistance. Av = REjjrO REjjrO + RS +1 + 1 gm Rin Rout = = r  + RS + 1 + + 1g1mR EjjjjRrOEjjrO: (5.330) (5.331) (5.332) Example 5.46 Determine the small-signal properties of an emitter follower using an ideal current source (as in Example 5.43) but with a finite source impedance RS. Solution Since RE = 1, we have Av = rO + rO RS +1 + 1 gm Rin Rout = = r + RS + 1 + + 1g1mrO jjrO: (5.333) (5.334) (5.335) Also, gmrO 1, and hence Av  rO rO + RS +1 Rin   + 1rO: (5.336) (5.337) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 251 (1) Sec. 5.3 Bipolar Amplifier Topologies 251 We note that Av approaches unity if RS  + 1rO, a condition typically valid. Exercise How are the results modified if RE 1? The buffering capability of followers is sometimes attributed to their “current gain.” Since a base current iB results in an emitter current of  + 1iB, we can say that for a current iL delivered to the load, the follower draws only iL= + 1 from the source voltage (Fig. 5.93). Thus, vX sees the load impedance multiplied by  + 1. iL β+ 1 VCC Q1 i L vX Load Figure 5.93 Current amplification in a follower. Emitter Follower with Biasing The biasing of emitter followers entails defining both the base voltage and the collector (emitter) current. Figure 5.94(a) depicts an example similar to the scheme illustrated R2 is chosen to be in Fig. 5.19 for the CE stage. As usual, much greater than the base current. the current flowing through R1 and VCC VCC R1 RB IB v in C1 R2 X Q1 Vout RE v in C1 X Q1 Y Vout RE (a) (b) Figure 5.94 Biasing a follower by means of (a) resistive divider, (b) single base resistor. It is interesting to note that, unlike the CE topology, the emitter follower can operate with a base voltage near VCC. This is because the collector is tied to VCC, allowing the same voltage for tihneFbiga.s5e.w94it(hbo),uwt dhreirveinRgBQI1B into saturation. For this reason, followers are often biased as shown is chosen much less than the voltage drop across RE, thus lowering the sensitivity to . The following example illustrates this point. Example 5.47 The and follower of Fig. voltages if IS = 55.941(b0),e1m6 pAl,oys=RB10=0, a1n0dkVCCand=R2E:5 = V. 1k . What Calculate the bias current happens if drops to 50? Solution To determine the bias current, we follow the iterative procedure described in Section 5.2.3. Writ- BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 252 (1) 252 Chap. 5 Bipolar Amplifiers ing a KVL through RB, the base-emitter junction, and RE gives RBIC + VBE + REIC = VCC; (5.338) which, with VBE  800 mV, leads to IC = 1:545 mA: (5.339) It follows that VBE = VT lnIC=IS = 748 mV. Using this value in Eq. (5.338), we have IC = 1:593 mA; (5.340) a value close to that in (5.339) and hence relatively accurate. Under this condition, IBRB = 159 mV whereas REIC = 1:593 V. Since IBRB REIC , we expect that variation of and hence IBRB negligibly affects the for IE =vo=lt1a:g55e09,3dIrVoBpR,aBc0r:io1ss5ds9oRuVEbl=ea1dndk(he=3n1c8e1:mt4h3Ve4)em,mrAeitd,teuirmcianpngldytihcnoeglldtehrcaottpoaratccwuroorrsfesonlRdtsE.chAbasynag1e5ro9inumghVl.eesaTtdihmsattaotiesa,, 10 change in the collector current. The reader is encouraged to repeat the above iterations with = 50 and determine the exact current. Exercise If RB is doubled, is the circuit more or less sensitive to the variation in ? As manifested by Eq. (5.338), the topologies of Fig. 5.94 suffer from supply-dependent biasing. In integrated circuits, this issue is resolved by replacing the emitter resistor with a constant current source (Fig. 5.95). Now, since IEE is constant, so are VBE and RBIB. Thus, if VCC rises, so do VX and VY , but the bias current remains constant. RB v in C1 VCC Q1 C2 RL Figure 5.95 Capacitive coupling at input and output of a follower. 5.4 Summary and Additional Examples This chapter has created a foundation for amplifier design, emphasizing that a proper bias point must be established to define the small-signal properties of each circuit. Depicted in Fig. 5.96, the three amplifier topologies studied here exhibit different gains and I/O impedances, each serving a specific application. CE and CB stages can provide a voltage gain greater than unity and their input and output impedances are independent of the load and source impedances, respectively (if BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 253 (1) Sec. 5.4 Summary and Additional Examples 253 CE Stage VCC RC Vout Vin Q1 CB Stage VCC RC Vout Q1 Vin Vb Follower VCC Vin Q1 Vout RE Figure 5.96 Summary of bipolar amplifier topologies. 1 VA = ). On the other hand, followers display a voltage gain of at most unity but their terminal impedances depend on the load and source impedances. In this section, we consider a number of challenging examples, seeking to improve our circuit analysis techniques. As usual, our emphasis is on solution by inspection and hence intuitive understanding of the circuits. We assume various capacitors used in each circuit have a negligible impedance at the signal frequencies of interest. Example 5.48 1 Assuming VA = , determine the voltage gain of the circuit shown in Fig. 5.97(a). C1 R1 R2 VCC RC v out R2 RC RS v out R Thev v out Q1 RC R2 v in RS Q1 RE v in Q1 R1 RE v Thev RE (a) (b) (c) Figure 5.97 (a) Example of CE stage, (b) equivalent circuit with C1 shorted, (c) simplified circuit . Solution The and gsriomupnldifi, eadndacR2mboedtewl eiesndceoplilcetcetdorinanFdigg.ro5u.9n7d(.bR),eprelavceianlginvginth, aRtSR, 1anadppRe1arwsibthetawTehenevbeansine equivalent [Fig. 5.97(c)], we have vT hev = R1 R1 + RS vin RThev = R1jjRS: (5.341) (5.342) The resulting circuit resembles that in Fig. 5.43(a) and satisfies Eq. (5.185): vout vT hev = , R2jjRC RT hev +1 + 1 gm + : RE (5.343) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 254 (1) 254 Chap. 5 Bipolar Amplifiers Substituting for vT hev and RT hev gives vout vin = , R2jjRC R1jjRS +1 + 1 gm + RE  R1 R1 + RS : (5.344) Exercise What happens if a very large capacitor is added from the emitter of Q1 to ground? Example 5.49 1 Assuming VA = , compute the voltage gain of the circuit shown in Fig. 5.98(a). VCC RC C1 v in RS R1 v out Q1 C2 R2 I1 v in RS R1 Q1 R2 v out RC (a) (b) Figure 5.98 (a) Example of CE stage, (b) simplified circuit. Solution tAosr.sAhoswinntihnetahbeosviemepxliafimepdlde,iawgerarmepolafcFeigv.in5,.9R8S(b, )a,nRd2Ra1ppweiathrsaaTs haenveemniintteerqudievgaelnenertaatniodnurteilsiizse- Eq. (5.185): vout vin = , RT hev +1 RC + 1 gm + R2 (5.345) and hence vout vin = , RSjjR1 +1 RC + 1 gm + R2  R1 R1 + RS : (5.346) Exercise What happens if C2 is tied from the emitter of Q1 to ground? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 255 (1) Sec. 5.4 Summary and Additional Examples 255 Example 5.50 1 Assuming VA = , compute the voltage gain and input impedance of the circuit shown in Fig. 5.99(a). v out v in VCC RC VCC Q1 Q2 VB R1 I1 R eq v out v in RC Q1 R eq (a) (b) Figure 5.99 (a) Example of CE stage, (b) simplified circuit. Solution The circuit resembles a CE stage (why?) degenerated by the impedance seen at the emitter of Q2, Req. Recall from Fig. 5.75 that Req = R1 + 1 + 1 gm2 : (5.347) The simplified model in Fig. 5.99(b) thus yields Av = ,RC 1 gm1 + Req = 1 gm1 + ,RC R1 +1 + 1: gm2 (5.348) (5.349) The input impedance is also obtained from Fig. 5.75: Rin = r1 +  + 1Req = r1 + R1 + r2: (5.350) (5.351) Exercise Repeat the above example if R1 is placed in series with the emitter of Q2. Example 5.51 1 Calculate the voltage gain of the circuit in Fig. 5.100(a) if VA = . BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 256 (1) 256 Chap. 5 Bipolar Amplifiers RC v out VCC R1 C1 Q1 v in RS R2 CB Q1 v in RS v out RC R1 (b) (a) Figure 5.100 (a) Example of CB stage, (b) simplified circuit. Solution jj Since the both ends base [Fig. i5s.1a0t 0a(cb)g]r.oTuhnedv, oRlt1agaeppgeaainrsisingipvaernalbleyl(w5.i2th71R),CbuatnwdiRth2RiCs shorted to ground on replaced by RC R1: Av = RC jjR1 RS + 1 gm : (5.352) Exercise What happens if RC is replaced by an ideal currents source? Example 5.52 1 Determine the input impedance of the circuit shown in Fig. 5.101(a) if VA = . RC v out Q1 Q2 RB R eq RE VCC RC Q1 R eq R in R in (a) (b) Figure 5.101 (a) Example of CB stage, (b) simplified circuit. Solution In this circuit, Q1 with its base [Fig. e.g., the topology operates as a common-base device (why?) but with a resistance Req in series 5.101(b)]. To obtain Req, we recognize that in Fig. 5.91(a), concluding that Req can be Q2 resembles viewed as the an emitter follower, output resistance of such a stage, as given by Eq. (5.329): Req = RB +1 + 1 gm2 jjRE: (5.353) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 257 (1) Sec. 5.4 Summary and Additional Examples 257 Now, from Fig. 5.101(b), we observe that Rin contains two components: one equal to the resistance in series with the base, Req, divided by + 1, and another equal to 1=gm1: Rin = = Req +1 1 +1 + gm1R1B +1 + 1 gm2 jjRE  + 1 gm1 : (5.354) (5.355) The reader is encouraged to obtain Rin through a complete small-signal analysis and compare the required “manual labor” to the above algebra. Exercise What happens if the current gain of Q2 goes to infinity? Example 5.53 Compute the voltage gain and the output impedance of the circuit depicted in Fig. 5.102(a) with VA 1. VCC RS Q1 v in R1 X v out C2 R2 RE RS v in R1 rO Q1 v out RE R2 (a) (b) v Thev R Thev Q1 v out RE R2 rO (c) Figure 5.102 (a) Example of emitter follower, (b) circuit with C1 shorted, (c) simplified circuit. Solution Noting that X is at ac ground, we construct the simplified circuit shown in Fig. 5.102(b), where the output resistance of Q1 is explicitly drawn. Replacing vin, RS, and R1 with their Thevenin equivalent and recognizing that RE, R2, and rO appear in parallel [Fig. 5.102(c)], we employ Eq. (5.330) and write vout vT hev = REjjR2jjrO REjjR2jjrO + 1 gm + RT hev +1 (5.356) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 258 (1) 258 Chap. 5 Bipolar Amplifiers and hence vout vin = REjjR2jjrO REjjR2jjrO + 1 gm + RSjjR1 +1  R1 R1 + RS : For the output resistance, we refer to Eq. (5.332): Rout = = RRTS++hjjeR1v11++g1gm1m jjjjRREEjjjjRR22jjjjrrOO: (5.357) (5.358) (5.359) Exercise What happens if RS = 0? Example 5.54 Determine the voltage gain and I/O impedances of the topology shown in Fig. 5.103(a). Assume VA = 1 and equal ’s for npn and pnp transistors. VCC Q1 R B2 R eq2 R eq2 v in R eq1 R B1 RC v out Q3 RE Q2 RC v out v in Q3 RE R eq1 (a) (b) Figure 5.103 (a) Example of CE stage, (b) simplified circuit. Solution We identify the stage as a CE amplifier with emitter degeneration and a composite collector rlthoeaseiidsr.teaAmnscietttheoerf.fiRSrisBnt1cs,etewRpe,eqhw1aevdereenfprorotemesseFnthitget.hi5me.r7po5eldeaonfcQe s2eaenndloQo3kibnyg the impedances into the emitter that they create at of Q2 with a base Req1 = RB1 +1 + 1 gm2 : (5.360) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 259 (1) Sec. 5.5 Chapter Summary Similarly, Req2 = RB2 +1 + 1 gm1 ; leading to the simplified circuit shown in Fig. 5.103(b). It follows that Av = , RC Req1 + + Req2 1 gm3 + RE = , RC + RB2 +1 RB1 +1 + 1 gm2 + +gm1g3m1+1 : RE Also, Rin = r3 +  = r3 +  + + 11 RREE++ReRq+1B11 + 1 gm2 ; and Rout = RC + Req2 = RC + RB2 +1 + 1 gm1 : Exercise What happens if RB2 ! 1? 259 (5.361) (5.362) (5.363) (5.364) (5.365) (5.366) (5.367) 5.5 Chapter Summary In addition to gain, the input and output impedances of amplifiers determine the ease with which various stages can be cascaded. Voltage amplifiers must ideally provide a high input impedance (so that they can sense a voltage without disturbing the node) and a low output impedance (so that they can drive a load without reduction in gain). The impedances seen looking into the base, collector, and emitter of a bipolar transistor are equal to r (with emitter grounded), rO (with emitter grounded), and 1=gm (with base grounded), respectively. IrnO,orthdeertrtaonosibsttaoirnmthuestrebqeu“irbeidassemd,a”lli-.sei.g, ncaalrrbyipaoclaerrtadienviccoellpeacrtaomr ceuterrrsenstuacnhdaospgemra,terin, atnhde active region. Signals simply perturb these conditions. Biasing techniques establish the required base-emitter and base-collector voltages while providing the base current. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 260 (1) 260 Chap. 5 Bipolar Amplifiers With a single bipolar transistor, only three amplifier topologies are possible: common-emitter and common-base stages and emitter followers. The CE stage provides a moderate voltage gain, a moderate input impedance, and a moderate output impedance. Emitter degeneration improves the linearity but lowers the voltage gain. Emitter degeneration raises the output impedance of CE stages considerably. The CB stage provides a moderate voltage gain, a low input impedance, and a moderate output impedance. The voltage gain expressions for CE and CB stages are similar but for a sign. The emitter follower provides a voltage gain less than unity, a high input impedance, and a low output impedance, serving as a good voltage buffer. Problems 1. An antenna can be modeled as a Thevenin equivalent having a sinusoidal voltage source V0 cos !t resistance and RL an output resistance and plot the result as Ra ofuutn.cDtioenteormf RinLe.the average power delivered to a load 2. Determine the small-signal input resistance of the circuits shown in Fig. 5.104. Assume all diodes are forward-biased. (Recall from Chapter 3 that each diode behaves as a linear D1 D1 R in R1 (a) Figure 5.104 R in R1 D2 (b) R in R1 D2 D1 (c) resistance if the voltage and current changes are small.) 1 3. Compute the input resistance of the circuits depicted in Fig. 5.105. Assume VA = . R1 R2 R in VCC Q1 VCC Q1 R1 R in VCC Q1 VCC Q1 R in R in Q2 Q2 (a) (b) (c) (d) Figure 5.105 4. Compute the output resistance of the circuits depicted in Fig. 5.106. 1 5. Determine the input impedance of the circuits depicted in Fig. 5.107. Assume VA = . 6. Compute the output impedance of the circuits shown in Fig. 5.108. 7. Compute the bias point of the circuits depicted in Fig. 5.109. Assume = 100, IS = BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 261 (1) Sec. 5.5 Chapter Summary VB Q1 R1 R out VB R out RB Q1 (a) (b) Figure 5.106 R out Q1 Q2 (c) 261 R out VCC Q1 Q2 (d) R in R 1 VCC Q1 (a) VCC Ideal Q1 R in VB R1 (b) VCC Q1 R in Q2 VB R1 (c) Figure 5.107 VCC Q2 Q1 R in (d) VCC Q2 R in Q1 (e) VCC Q1 RC R out R out Q1 Q2 VB (a) (b) Figure 5.108 6  10,16 A, and VA = 1. 8. Construct the small-signal equivalent of each of the circuits in Problem 7. 9. Calculate the bias point of the circuits shown in Fig. 5.110. Assume A, and VA = 1. = 100, IS = 510,16 10. Construct the small-signal equivalent of each of the circuits in Problem 9. 11. Consider the circuit shown in Fig. 5.111, where = 100, IS = 6  10,16 A, and VA = 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 262 (1) 262 100 k Ω VCC = 2.5 V 500 Ω 100 k Ω Chap. 5 Bipolar Amplifiers VCC = 2.5 V 1 kΩ 100 k Ω VCC = 2.5 V 1 kΩ Q1 Q1 Q1 0.5 V Q2 (a) (b) (c) Figure 5.109 34 k Ω VCC = 2.5 V 3 kΩ 9 kΩ VCC = 2.5 V 500 Ω 12 k Ω VCC = 2.5 V 1 kΩ Q1 16 k Ω Q1 16 k Ω Q2 13 k Ω Q1 0.5 V (a) (b) (c) Figure 5.110 RB 3 kΩ VCC = 2.5 V 2 kΩ Q1 Figure 5.111 (a) (b) WWihtahttihsethvealmueinfoimunudminvaRluBe,ohfoRwBmtuhcaht guarantees operation in the base-collector forward bias active mode? is sustained if rises to 200? 12. In the circuit of Fig. 5.112, = 100 and VA = 1. 50 k Ω VCC = 2.5 V 3 kΩ Q1 30 k Ω Figure 5.112 (a) If the collector current of Q1 is equal to 0.5 mA, calculate the value of IS. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 263 (1) Sec. 5.5 Chapter Summary 263 (b) If Q1 is biased at the edge of saturation, calculate the value of IS. 13. The circuit of Fig. 5.113 must be designed for an input impedance of greater than 10 k and VCC = 2.5 V R1 5 kΩ Q1 R2 Figure 5.113 amginmimoufmatalleloawsta1b=le2v6a0lues.oIffR1 =and10R02,.IS = 2  10,17 A, and VA = 1, determine the 14. Repeat Problem 13 for a gm of at least 1=26 . Explain why no solution exists. 15. We wish to design the CE stage depicted in Fig. 5.114 for a gain (= gmRC) of A0 with an VCC R1 RC Q1 R2 Figure 5.114 1 output VA = impedance . of R0. What is the maximum achievable input impedance here? Assume 16. The circuit of Fig. 5.115 is designed for a collector current of 0.25 mA. Assume IS = VCC = 2.5 V R1 RC 3 kΩ 10 k Ω R2 Q1 RE = 200 Ω Figure 5.115 6  10,16 A, = 100, and VA = 1. (a) (b) Determine the required What is the error in IC value if RE of R1. deviates from its nominal value by 5? 17. In of the Q1 icnirtchueitaoctfivFeigm. o5d.1e1. 6A,sdseutmeremin=e t1h0e0m, IaSxi=mu1m0,v1a7luAe,oafnRd 2VAtha=t guarantees 1. operation 18. Consider the circuit and VA = 1. shown in Fig. 5.117, where IS1 = 2IS2 = 510,16 A, 1= 2 = 100, (a) Determine the collector currents of Q1 and Q2. (b) Construct the small-signal equivalent circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 264 (1) 264 Figure 5.116 Chap. 5 Bipolar Amplifiers 30 k Ω VCC = 2.5 V RC 2 kΩ Q1 R2 RE = 100 Ω 13 k Ω R1 R C 1 kΩ VCC = 2.5 V Q1 Q2 12 k Ω R2 R E 400 Ω Figure 5.117 19. In the circuit VA = 1. depicted in Fig. 5.118, IS1 = IS2 = 4  10,16 A, 1= 2 = 100, and VCC = 2.5 V 9 kΩ 100 Ω Q1 16 k Ω Q2 Figure 5.118 (a) Determine the operating point of the transistor. (b) Draw the small-signal equivalent circuit. 20. The circuit of Fig. 5.119 must be biased with a collector current of 1 mA. Compute the VCC = 2.5 V 1 kΩ RB R p 100 Ω Q1 Figure 5.119 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 265 (1) Sec. 5.5 Chapter Summary 265 required value of RB if IS = 3  10,16 A, = 100, and VA = 1. 21. In the circuit of Fig. 5.120, VX = 1:1 V. If = 100 and VA = 1, what is the value of IS? 10 kΩ VCC = 2.5 V 300 Ω X Q1 Figure 5.120 22. Consider the circuit shown in Fig. 5.121, where IS = 6  10,16 A, Calculate the operating point of Q1. VCC = 2.5 V 20 kΩ 500 Ω = 100, and VA = 1. Q1 400 Ω Figure 5.121 23. Due to a lector of manufacturing error, a Q1 in Fig. 5.122. What ipsatrhaesimticinriemsiusmtora,llRowP ,abhlaesvaaplupeeaorfedRBin series with the colif the base-collector VCC = 2.5 V 1 kΩ RB R p 500 Ω Q1 Figure 5.122 forward bias must not exceed 200 mV? Assume IS = 3  10,16 A, = 100, and VA = 1. 24. In the circuit of Fig. 5.123, IS = 8  10,16 A, = 100, and VA = 1. VCC = 2.5 V 10 k Ω 1 kΩ Q1 40 k Ω Figure 5.123 (a) Determine the operating point of Q1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 266 (1) 266 Chap. 5 Bipolar Amplifiers (b) Draw the small-signal equivalent circuit. 25. In the circuit of Fig. 5.124, IS1 = IS2 = 3  10,16 A, = 100, and VA = 1. 200 Ω VCC = 2.5 V Q1 Q2 VB 500 Ω Figure 5.124 (a) Calculate VB such that Q1 carries a collector current of 1 mA. (b) Construct the small-signal equivalent circuit. 26. Determine the bias point of each circuit shown in Fig. 5.125. Assume npn = 2 pnp = 100, 60 k Ω VCC = 2.5 V Q1 200 Ω VCC = 2.5 V Q1 Q2 300 Ω 80 kΩ (a) (b) Figure 5.125 IS = 9  10,16 A, and VA = 1. 27. Construct the small-signal model of the circuits in Problem 26. 28. Calculate the bias point of the circuits shown in Fig. 5.126. Assume npn = 2 pnp = 100, 32 kΩ 18 kΩ VCC = 2.5 V Q1 100 Ω Q1 Q2 VCC = 2.5 V 32 kΩ 1 kΩ 18 kΩ Figure 5.126 (a) (b) IS = 9  10,16 A, and VA = 1. 29. Draw the small-signal model of the circuits in Problem 28. 30. We have chosen RB in Fig. 5.127 to place Q1 at the edge of saturation. But the actual value  of this resistor can vary by  1 collector junction at these two 5. Determine the extremes. Assume fo=rw5a0r,dI-Sor=re8vers1e0-,bi1a6sAac, raonsds the VA base- =. 31. Calculate the value of RE in Fig. 5.128 such that Q1 sustains a reverse bias of 300 mV BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 267 (1) Sec. 5.5 Chapter Summary 267 5 kΩ RB VCC = 2.5 V Q1 1 kΩ Figure 5.127 10 k Ω 10 k Ω VCC = 2.5 V RE Q1 5 kΩ Figure 5.128 across its base-collector junction. Assume happens if the value of RE is halved? = 50, IS = 8  10,16 A, and VA = 1. What 32. If = 80 and VA = 1, what value of IS yields a collector current of 1 mA in Fig. 5.129? VCC = 2.5 V Q1 20 kΩ 1.6 k Ω Figure 5.129 33. The topology depicted in Fig. 5.130(a) is called a “VBE multiplier.”(The npn counterpart has a similar topology.) Constructing the circuit shown in Fig. 5.130(b), determine the collector- VCC Figure 5.130 R1 Q1 R2 (a) R1 Q1 R2 R3 (b) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 268 (1) 268 Chap. 5 Bipolar Amplifiers emitter voltage of Q1 if the base current is negligible. (The npn counterpart can also be used.) 34. We wish to design the CE stage of Fig. 5.131 for a voltage gain of 20. What is the minimum VCC = 2.5 V 50 k Ω Vout V in Q1 Figure 5.131 allowable supply VBE = 0:8 V. voltage if Q1 must remain in the active mode? Assume VA = 1 and 35. The circuit of Fig. 5.132 must be designed for maximum voltage gain while maintaining Q1 VCC RC 1 kΩ Vout Vin Q1 Figure 5.132 in the active mode. If VA = 10 V and VBE = 0:8 V, calculate the required bias current. 36. The CE stage of Fig. 5.133 employs an ideal current source as the load. If the voltage gain VCC Ideal Vout Vin Q1 Figure 5.133 is equal to 50 and the output impedance equal to 10 k , determine the bias current of the transistor. 37. Suppose the bipolar transistor in Fig. 5.134 exhibits the following hypothetical characteris- VCC RC 1 kΩ Vout Vin Q1 Figure 5.134 tic: IC = IS exp VBE 2VT ; and no Early effect. Compute the voltage gain for a bias current of 1 mA. (5.368) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 269 (1) Sec. 5.5 Chapter Summary 269 38. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.135. Assume 1 VA = . Transistor Q2 in Figs. 5.135(d) and (e) operates in soft saturation. VCC Q2 Vout Vin Q1 VCC Q2 R1 Vout Vin Q1 VCC Q2 RC Vout Vin Q1 (a) Vin (b) VCC Q2 RC Vout Q1 Vin (c) VCC Q2 RC Vout Q1 (d) (e) Figure 5.135 39. Repeat Problem 38 with VA 1. 40. CnfgomooltlnReoswEithdieanisrtggnEtmowqm.oa(inn5cda.a1lslh5eye7sn,e)cqdfeuoearttelhtrethmoevi3ong;leat(iabntgh)eeogfgmraeaRilnadEteivvgiaesernyncehoirfamantIiegCndealcCilhnyEaetnshqgteuaeagsgleaw.tioniWt7hir.fitTthIienhCgesivmggamnoriareel=slcebovIyneCsl1.t=a0VFn%Tot r:,gtaw(hainee) in the second case translates to greater circuit linearity. 41. Express the voltage gain of the stage depicted in Fig. 5.136 in terms of the collector bias VCC RC Vout Vin Q1 RE Figure 5.136 current, IC, are equal to 2an0dVTVTan. dIf5VVAT = 1, what is the , respectively? gain if the dc voltage drops across RC and RE  1 42. We wish to design the degenerated stage of Fig. 5.137 for a voltage gain of 10 operating IS = 5 a1t0t,he16eAd,gaenodf saturation. Calculate the bias current and the value of RC VA = . Calculate the input impedance of the circuit. if with Q1 = 100, 43. Repeat Problem 42 for a voltage gain of 100. Explain why no solution exists. What is the maximum gain that can be achieved in this stage? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 270 (1) 270 Figure 5.137 Chap. 5 Bipolar Amplifiers VCC = 2.5 V RC Vout Vin Q1 200 Ω 44. Construct the small-signal model of the CE stage shown in Fig. 5.43(a) and calculate the voltage gain. Assume VA = 1. 45. Construct the small-signal model of the CE stage shown in Fig. 5.43(a) and prove that the output impedance is equal to RC if the Early effect is neglected. 46. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.138. Assume VA = 1. VCC Q2 R1 Vout Vin Q1 RE VCC RC Vout Vin Q1 Q2 VCC RC Vout Vin Q1 Q2 (b) (c) (a) RB Vin VCC RC Vout Q1 Q2 RB Vin RC Vout Q1 VCC Q2 VB (e) (d) Figure 5.138 47. Compute the voltage gain the I/O impedances of the circuits depicted in Fig. 5.139. Assume VA = 1. 48. Using a small-signal equivalent circuit, compute the output impedance of a degenerated CE stage with VA 1. Assume 1. 49. Calculate the output impedance of the circuits shown in Fig. 5.140. Assume 1. 50. Compare the output impedances of the circuits illustrated in Fig. 5.141. Assume 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 271 (1) Sec. 5.5 Chapter Summary VCC RE Vin Q1 Vout RC Q2 VCC RE Vin Q1 Vin RC Vout Q2 VCC Q3 Q1 Vout RC Q2 (a) (b) (c) Figure 5.139 R out Q1 Q2 (a) Figure 5.140 R out VCC Q1 Q2 RB I1 (b) 271 Vin VCC Q2 VCC RE Q1 Vout RC (d) R out VCC Q1 Q2 R1 (c) VCC Q1 Q2 VCC Q1 Q2 Figure 5.141 R out (a) R out (b) 51. Writing r = VT =IC, expand Eq. (5.217) and prove that the result remains close to r if IBRB VT (which is valid because VCC and VBE typically differ by about 0.5 V or higher.) 52. CAa, lcu=lat1e0v0o,uatn=dviVnAfo=r each of the circuits depicted in Fig. 1. Also, assume the capacitors are 5.142. Assume very large. IS = 8  10,16 53. Repeat Example 5.33 with RB = 25k and RC = 250 . Is the gain greater than unity? 54. The common-base stage of Fig. 5.143 is biased with a collector current of 2 mA. Assume VA = 1. (a) Calculate the voltage gain and I/O impedances of the circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 272 (1) 272 Chap. 5 Bipolar Amplifiers 100 k Ω Vin C1 VCC = 2.5 V 1 kΩ 50 k Ω Vout Q1 100 Ω Vin 1 kΩ C1 C2 VCC = 2.5 V 1 kΩ 14 k Ω Vout Q1 2 kΩ C1 V in 1 kΩ 11 k Ω VCC = 2.5 V R C 10 k Ω Vout Q1 500 Ω C2 2 kΩ (a) (b) (c) Figure 5.142 Figure 5.143 VCC R C 500 Ω Vout Q1 Vb V in (b) How should VB and RC be chosen to maximize the voltage gain with a bias current of 2 mA? 1 55. Determine the voltage gain of the circuits shown in Fig. 5.144. Assume VA = . VCC VCC VCC Q2 RC Vout Q1 Vb Vin (a) Figure 5.144 Vin Vb VCC Q1 Vout Q2 (b) Q3 RC Q1 Vin RE Vout Vb Vin (c) Q3 RC Q1 Vout Vb R S RE (d) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 273 (1) Sec. 5.5 Chapter Summary 1 56. Compute the input impedance of the stages depicted in Fig. 5.145. Assume VA = . VCC VCC VCC R1 Q2 Q1 R1 R2 Q1 Q2 Vb R1 R2 Q1 Q2 R1 R2 Q1 R in R in R in R in (a) (b) Figure 5.145 (c) (d) 273 VCC Q2 57. Calculate the voltage gain and I/O impedances of the CB stage shown in Fig. 5.146. Assume VA 1. VCC ideal Figure 5.146 Q1 Vin Vout Vb 58. Consider the CB stage depicted in Fig. 5.147, where = 100, IS = 8  10,16 A, VA = 1, and CB is very large. VCC = 2.5 V 1 kΩ 13 k Ω Vout Q1 Vin CB 12 k Ω 400 Ω Figure 5.147 (a) Determine the operating point of Q1. (b) Calculate the voltage gain and I/O impedances of the circuit. 59. Repeat Problem 58 for CB = 0. 1 60. Compute the voltage gain and I/O impedances of the and CB is very large. stage shown in Fig. 5.148 if VA = 61. Calculate the voltage gain and the I/O impedances of the stage depicted in Fig. 5.149 if VA = 1 and CB is very large. 1 62. Calculate the voltage gain of the circuit shown in Fig. 5.150 if VA . 63. The circuit of Fig. between vout1=vin a5n.1d5v1ouptr2o=vviidne.sAtwssoumouetpVuAts=. If1I.S1 = 2IS2, determine the relationship BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 274 (1) 274 Chap. 5 Bipolar Amplifiers Figure 5.148 Q2 V out Q1 Vin VCC R1 CB R2 Figure 5.149 Figure 5.150 Figure 5.151 ideal Vout Q1 Vin VCC R1 CB R2 VCC ideal Vout Q1 Vb Vin RS VCC Vout1 RC RC Vout2 Q1 Q2 Vin Vb 64. Using a small-signal model, determine the voltage gain of a CB stage with emitter degener- 1 ation, a base resistance, and VA . Assume 1. 65. For RE = 100 to 0.8. Assume in Fig. 5.152, VA = 1. determine the bias current of Q1 such that the gain is equal 66. The circuit of Fig. 5.152 must provide an input impedance of greater than 10 k with a 1 minimum VA = . gain of 0.9. Calculate the required bias current and RE. Assume = 100 and 67. A microphone having an output impedance RS = 200 drives an emitter follower as shown BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 275 (1) Sec. 5.5 Chapter Summary 275 VCC = 2.5 V Vin Q1 Vout RE Figure 5.152 in Fig. 5.153. Determine the bias current such that the output impedance does not exceed 5 VCC = 2.5 V RS Vin Q1 I1 R out Figure 5.153 . Assume = 100 and VA = 1. 68. Compute the voltage gain and I/O impedances of the circuits shown in Fig. 5.154. Assume VA = 1. VCC VCC VCC Vin Q1 Vout Vb Q2 Vin Q1 Vout Q2 Vin RS Q1 Vout Q2 (a) (b) (c) VCC Vin Q1 Vout RE Q2 VCC Vin Q1 RE Vout Q2 (d) (e) Figure 5.154 69. FVemiCgCiuttr.eeNr 5ofo.t1el5lot5hwadeterIpEdirc1itvsinagI“CQD12a.r=lAinsIgsBtuo2mn=epVaIiACr,2”==w1.heraenQd 1theplcaoylsleactroorlseosfoQm1ewanhdatQsi2mairleartiteod an to (a) (b) If If the the emitter base of oQf1Qis2 is grounded, determine grounded, calculate the the impedance seen at impedance seen at the tehmeibttaesreooffQQ21. . (c) Compute the current gain of the pair, defined as IC1 + IC2=IB1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 276 (1) 276 Chap. 5 Bipolar Amplifiers Q1 Q2 Figure 5.155 70. In the emitter follower shown in Fig. 5.156, Q2 serves as a current source for the input device VCC Vin Q1 R CS Vb Q2 RE Figure 5.156 Q1. (a) Calculate the output impedance of the current source, (b) Replace Q2 and RE with the impedance obtained in RCS. (a) and compute the voltage gain and I/O impedances of the circuit.  71. Determine the voltage gain of the follower depicted in Fig. 5.157. Assume IS = 7 10,16 10 k Ω V in C1 VCC = 2.5 V Q1 C2 1 kΩ Vout 100 Ω Figure 5.157 A, = 100, and VA = 5 V. (But for bias calculations, assume VA = 1.) Also, assume the capacitors are very large. 72. Figure 5.158 illustrates a cascade of an emitter follower and a common-emitter stage. As- VCC RC Vin Q1 X Vout Q2 RE Figure 5.158 sume VA 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 277 (1) Sec. 5.5 Chapter Summary 277 (a) Calculate the input and output impedances of the circuit. (b) Determine the voltage gain, vout=vin = vX=vinvout=vX. 73. Figure 5.159 shows a cascade of an emitter follower and a common-base stage. Assume VCC Vin Q1 RC Vout X Q2 Vb RE Figure 5.159 VA = 1. (a) Calculate the I/O impedances of the circuit. (b) Calculate the voltage gain, vout=vin = vX=vinvout=vX. Design Problems In the following problems, unless otherwise stated, assume and VA = 1. = 100, IS = 6  10,16 A, 74. Design the CE stage shown in Fig. 5.160 for a voltage gain of 10, and input impedance of Figure 5.160 RB Vin CB VCC = 2.5 V RC Vout Q1 greater than 5 k , and an output impedance of 1 k . If the lowest signal frequency of interest is 200 Hz, estimate the minimum allowable value of CB. 75. We wish to design the CE stage of Fig. 5.161 for maximum voltage gain but with an output RB Vin VCC = 2.5 V RC Vout Q1 Figure 5.161 impedance no greater than 500 . Allowing the transistor to experience at most 400 mV of base-collector forward bias, design the stage. 76. The stage depicted in Fig. 5.161 must achieve maximum input impedance but with a voltage gain of at least 20 and an output impedance of 1 k . Design the stage. 77. The CE stage of Fig. 5.161 must be designed for minimum supply voltage but with a voltage gain of 15 and an output impedance of 2 k . If the transistor is allowed to sustain a basecollector forward bias of 400 mV, design the stage and calculate the required supply voltage. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 278 (1) 278 Chap. 5 Bipolar Amplifiers 78. We wish to design the CE stage of Fig. 5.161 for minimum power dissipation. If the voltage gain must be equal to A0, determine the trade-off between the power dissipation and the output impedance of the circuit. 79. Design the CE stage of Fig. 5.161 for a power budget of 1 mW and a voltage gain of 20. 80. Design the degenerated CE stage of Fig. 5.162 for a voltage gain of 5 and an output VCC = 2.5 V R1 Vin R2 RC Vout Q1 RE Figure 5.162 impedance of 500 . Assume RE sustains a voltage drop of 300 mV and the current flowing through R1 is approximately 10 times the base current. 81. The stage of Fig. 5.162 must be designed for maximum voltage gain but an output impedance of no greater than 1 k . Design the circuit, assuming that RE sustains 200 mV, and the current flowing through R1 is approximately 10 times the base current, and Q1 experiences a maximum base-collector forward bias of 400 mV. 82. Design the stage of Fig. 5.162 for a power budget of 5 mW, a voltage gain of 5, and a voltage drop of 200 mV across RE. Assume the current flowing through R1 is approximately 10 times the base current. 83. Design the common-base stage shown in Fig. 5.163 for a voltage gain of 20 and an input VCC = 2.5 V R1 CB R2 RC Vout Q1 Vin RE Figure 5.163 impedance of 50 . Assume a voltage drop of 10VT = 260 mV across RE so that this resistor does not affect the input impedance significantly. Also, assume the current flowing through R1 is approximately 10 times the base current, and the lowest frequency of interest is 200 Hz. 84. The CB amplifier of Fig. 5.163 must achieve a voltage gain of 8 with an output impedance of 500 . Design the circuit with the same assumptions as those in Problem 83. 85. We wish to design the CB stage of Fig. 5.163 for an output impedance of 200 and a voltage gain of 20. What is the minimum required power dissipation? Make the the same assumptions as those in Problem 83. 86. Design the CB amplifier of Fig. 5.163 for a power budget of 5 mW and a voltage gain of 10. Make the same assumptions as those in Problem 83. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 279 (1) Sec. 5.5 Chapter Summary 279 87. Design the CB stage of Fig. 5.163 for the minimum supply voltage if an input impedance of 50 and a voltage gain of 20 are required. Make the same assumptions as those in Problem 83. 88. Design the emitter follower shown in Fig. 5.164 for a voltage gain of 0.85 and an input R1 Vin VCC = 2.5 V Q1 RL Vout Figure 5.164 impedance of greater than 10 k . Assume RL = 200 . 89. The follower of Fig. 5.164 must consume 5 mW of power while achieving a voltage gain of 0.9. What is the minimum load resistance, RL, that it can drive? 90. The follower shown in Fig. 5.165 must drive a load resistance, RL = 50 , with a voltage R1 Vin C1 VCC = 2.5 V Q1 C2 RE RL Vout Figure 5.165 gain of 0.8. Design the circuit assuming that the lowest frequency of interest is 100 MHz. (Hint: select the voltage drop across RE to be much greater than VT so that this resistor does not affect the voltage gain significantly.) SPICE Problems In the IS;pnp f=oll8owi1n0g,p1r6obAl,empsn, pas=su5m0e, VIAS;;npnpnp = 5  10,16 = 3:5 V. A, npn = 100, VA;npn = 5 V, 91. The common-emitter shown in Fig. 5.166 must amplify signals in the range of 1 MHz to 100 MHz. VCC = 2.5 V 100 k Ω 1 kΩ Vin P Vout Q1 C1 C2 500 Ω Figure 5.166 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 280 (1) 280 Chap. 5 Bipolar Amplifiers (a) Using the .op command, determine the bias conditions of Q1 and verify that it operates in the active region. j j j j  (T((aViptcbdtFsPh))).1im=PsWRD0VlaeuoeMiixnnntttheisnHmuroVimtrzrnuhoe.ugVmiesn(toOap=teu(hnrVinttao.h=ieeatpneV.cC,eaivprfnaa1oapsnvlradraauacorClleotyufas2upcosenaihsf=sosc,bCiftsay1ic2Cohtsanosho2uFfoooiafcn)rsfoc.htsefutecrotntreihhrtrdqaceoautuifvnetrihttaenw(lesaccuitoys)ge.a,tfa)oloodilrnfrefitsrConeeefr1vqsmteeuhsrrieuenianecleccshviitrweahtcslheuiutaoiehittfnsaVpioVntiufnPt1teC0=riameV2nMs,idptne.Hea.gddz.aj,iuns1sc0ote:ni9Fotl9s,yf1vat2hatnle1Fu,cebMaieurnclHndoutwzii1lt. 92. Predicting an output impedance of about 1 k for the stage shown in Fig. 5.166, a student constructs the circuit value. Unfortunately, depicted VN =VX in Fig. 5.167, where VX represents is far from 0.5. Explain why. an ac source with zero dc VCC = 2.5 V 100 k Ω 1 kΩ IX N C1 Q1 1 kΩ VX C2 500 Ω Figure 5.167 93. Consider the self biased stage shown in Fig. 5.168. 10 kΩ V in C1 P VCC = 2.5 V 1 kΩ Vout Q1 Figure 5.168 (a) (b) Determine Select the the bias conditions of value of C1 such that Q1. it operates as nearly a short circuit (e.g., jVP =Vinj  0:99) at 10 MHz. (c) Compute the voltage gain of the circuit at 10 MHz. (d) Determine the input impedance of the circuit at 10 MHz. (e) Suppose the supply voltage is provided by an aging battery. How much can VCC fall while the gain of the circuit degrades by only 5? 94. Repeat Problem 93 for the stage illustrated in Fig. 5.169. Which one of the two circuits is less sensitive to supply variations? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 281 (1) Sec. 5.5 Chapter Summary 281 Figure 5.169 1 kΩ Vin C1 10 kΩ VCC = 2.5 V 1 kΩ Vout Q1 95. The amplifier shown in Fig. 5.170 employs an emitter follower to drive a 50- load at a frequency of 100 MHz. 2 kΩ Vin C1 2 kΩ 600 Ω X Q1 RE1 C2 VCC = 2.5 V Q2 C3 200 Ω Vout 50Ω Figure 5.170 (a) (b) Determine Determine the the value of RE1 such that Q2 minimum acceptable value carries a bias current of 2 of C1, C2, and C3 if each mA. one is to degrade the gain by less than 1. (c) What is the signal attenuation of the emitter follower? Does the overall gain increase if RG2 is reduced to 100 ? Why? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 282 (1) 6 Physics of MOS Transistors Today’s field of microelectronics is dominated by a type of device called the metal-oxidesemiconductor field-effect transistor (MOSFET). Conceived in the 1930s but first realized in the 1960s, MOSFETs (also called MOS devices) offer unique properties that have led to the revolution of the semiconductor industry. This revolution has culminated in microprocessors having 100 million transistors, memory chips containing billions of transistors, and sophisticated communication circuits providing tremendous signal processing capability. Our treatment of MOS devices and circuits follows the same procedure as that taken in Chap- ters 2 and 3 for pn junctions. In this chapter, we analyze the structure and operation of MOSFETs, seeking models that prove useful in circuit design. In Chapter 7, we utilize the models to study MOS amplifier topologies. Figure 6 illustrates the sequence of concepts covered in this chapter. Operation of MOSFETs MOS Structure Operation in Triode Region Operation in Saturation I/V Characteristics MOS Device Models Large−Signal Model Small−Signal Model PMOS Devices Structure Models 6.1 Structure of MOSFET Recall from Chapter 5 that any voltage-controlled current source can provide signal amplification. MOSFETs also behave as such controlled sources but their characteristics are different from those of bipolar transistors. In order to arrive at the structure of the MOSFET, we begin with a simple geometry consisting of a conductive (e.g., metal) plate, an insulator (“dielectric”), and a doped piece of silicon. Illustrated in Fig. 6.1(a), such a structure operates as a capacitor because the p-type silicon is somewhat conductive, “mirroring” any charge deposited on the top plate. What happens if a potential difference is applied as shown in Fig. 6.1(b)? As positive charge is placed on the top plate, it attracts negative charge, e.g., electrons, from the piece of silicon. (Even though doped with acceptors, the p-type silicon does contain a small number of electrons.) We therefore observe that a “channel” of free electrons may be created at the interface between the insulator and the piece of silicon, potentially serving as a good conductive path if the electron density is sufficiently high. The key point here is that the density of electrons in the channel varies with V1, as evident from Q = CV , where C denotes the capacitance between the two plates. 282 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 283 (1) Sec. 6.1 Structure of MOSFET 283 Conductive Plate Insulator V1 V1 p−Type Silicon Channel of Electrons V2 (a) (b) (c) Figure 6.1 (a) Hypothetical semiconductor device, (b) operation as a capacitor, (c) current flow as a result of potential difference. in The Fig. dependence of the electron 6.1(c), we allow a current density to flow upon from Vle1ftletoadrsigtohtanthirnotuegrehsttihnegspilriocpoenrtmy:aitfe,raisald, eVp1icctaend control the current by adjusting the resistivity of the channel. (Note that the current prefers to take the path of least resistance, thus flowing primarily through the channel rather than through the entire body of silicon.) This will serve our objective of building a voltage-controlled current source. Equation Q = CV suggests that, to achieve a strong control of Q by V , the value of C must be maximized, for example, by reducing the thickness of the dielectric layer separating the two plates.1 The ability of silicon fabrication technology to produce extremely thin but uniform di- electric layers (with thicknesses below 20 A today) has proven essential to the rapid advancement of microelectronic devices. The foregoing thoughts lead to the MOSFET structure shown in Fig. 6.2(a) as a candidate for an amplifying device. Called the “gate” (G), the top conductive plate resides on a thin dielectric (insulator) layer, which itself is deposited on the underlying p-type silicon “substrate.” To allow current flow through the silicon material, two contacts are attached to the substrate through two heavily-doped n-type regions because direct connection of metal to the substrate would not pro- duce a good “ohmic” contact.2 These two terminals are called “source” (S) and “drain” (D) to indicate that the former can provide charge carriers and the latter can absorb them. Figure 6.2(a) reveals that the device is symmetric with respect to S and D; i.e., depending on the voltages ap- plied to the device, either of these two terminals can drain the charge carriers from the other. As explained in Section 6.2, with n-type source/drain and p-type substrate, this transistor operates with electrons rather than holes and is therefore called an n-type MOS (NMOS) device. (The p-type counterpart is studied in Section 6.4.) We draw the device as shown in Fig. 6.2(b) for simplicity. Figure 6.2(c) depicts the circuit symbol for an NMOS transistor, wherein the arrow signifies the source terminal. Before delving into the operation of the MOSFET, let us consider the types of materials used in the device. The gate plate must serve as a good conductor and was in fact realized by metal (aluminum) in the early generations of MOS technology. However, it was discovered that non- crystaline silicon (“polysilicon” or simply “poly”) with heavy doping (for low resistivity) exhibits better fabrication and physical properties. Thus, today’s MOSFETs employ polysilicon gates. The dielectric layer sandwiched between the gate and the substrate plays a critical role in the performance of transistors and is created by growing silicon dioxide (or simply “oxide”) on top A=t 1The capacitance between two plates is given by , where is the “dielectric constant” (also called the “permi- A t tivity”), is the area of each plate, and is the dielectric thickness. 2Used to distinguish it from other types of contacts such as diodes, the term “ohmic” contact emphasizes bi- directional current flow—as in a resistor. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 284 (1) 284 Chap. 6 Physics of MOS Transistors Source Conductive Gate Plate Drain n+ n+ p −substrate G S n+ p −substrate Insulator (a) D n+ G S D (b) (c) Figure 6.2 (a) Structure of MOSFET, (b) side view, (c) circuit symbol. of the silicon area. The n+ regions are sometimes called source/drain “diffusion,” referring to a fabrication method used in early days of microelectronics. We should also remark that these regions in fact form diodes with the p-type substrate (Fig. 6.3). As explained later, proper opera- tion of the transistor requires that these junctions remain reverse-biased. Thus, only the depletion region capacitance associated with the two diodes must be taken into account. Figure 6.3 shows some of the device dimensions in today’s state-of-the-art MOS technologies. The oxide thickness is denoted by tox. Polysilicon Oxide S/D Diffusion n+ tox = 18 A n+ p −substrate Length 90 nm Figure 6.3 Typical dimensions of today’s MOSFETs. Oxide−Silicon Interface 6.2 Operation of MOSFET This section deals with a multitude of concepts related to MOSFETs. The outline is shown in Fig. 6.4. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 285 (1) Sec. 6.2 Operation of MOSFET 285 Qualitative Analysis I/V Characteristics Formation of Channel MOSFET as Resistor Channel Pinch−off I/V Characteristics Channel Charge Density Dain Current Triode and Saturation Regions Figure 6.4 Outline of concepts to be studied. Analog Properties Transconductance Channel−Length Modulation Other Properties Body Effect Subthreshold Conduction Velocity Saturation 6.2.1 Qualitative Analysis Our study of the simple structures shown in Figs. 6.1 and 6.2 suggests that the MOSFET may conduct current between the source and drain if a channel of electrons is created by making the gate voltage sufficiently positive. Moreover, we expect that the magnitude of the current can be controlled by the gate voltage. Our analysis will indeed confirm these conjectures while revealing other subtle effects in the device. Note that the gate terminal draws no (low-frequency) current as it is insulated from the channel by the oxide. Since the MOSFET contains three terminals,3 we may face many combinations of terminal voltages and currents. Fortunately, with the (low-frequency) gate current being zero, the only current of interest is that flowing between the source and the drain. We must study the dependence of this current upon the gate voltage (e.g., for a constant drain voltage) and upon the drain voltage (e.g., for a constant gate voltage). These concepts become clearer below. Let us first consider the arrangement shown in Fig. 6.5(a), where the source and drain are grounded and the gate voltage is varied. This circuit does not appear particularly useful but it gives us a great deal of insight. Recall from Fig. 6.1(b) that, as VG rises, the positive charge on the gate must be mirrored by negative charge in the substrate. While we stated in Section 6.1 that electrons are attracted to the interface, in reality, another phenomenon precedes the formation of the channel. As VG increases from zero, the positive charge on the gate repels the holes in the substrate, thereby exposing negative ions and creating a depletion region [Fig. 6.5(b)].4 Note that the device still acts as a capacitor—positive charge on the gate is mirrored by negative charge in the substrate—but no channel of mobile charge is created yet. Thus, no current can flow from the source to the drain. We say the MOSFET is off. Can the source-substrate and drain-substrate junctions carry current in this mode? To avoid this effect, the substrate itself is also tied to zero, ensuring that these diodes are not forwardbiased. For simplicity, we do not show this connection in the diagrams. What happens as VG increases? To mirror the charge on the gate, more negative ions are exposed and the depletion region under the oxide becomes deeper. Does this mean the transistor never turns on?! Fortunately, if VG becomes sufficiently positive, free electrons are attracted to the oxide-silicon interface, forming a conductive channel [Fig. 6.5(c)]. We say the MOSFET is on. The gate potential at which the channel begins to appear is called the “threshold voltage,” VT H , and falls in the range of 300 mV to 500 mV. Note that the electrons are readily provided by the n+ source and drain regions, and need not be supplied by the substrate. It is interesting to recognize that the gate terminal of the MOSFET draws no (low-frequency) current. Resting on top of the oxide, the gate remains insulated from other terminals and simply operates as a plate of a capacitor. MOSFET as a Variable Resistor The conductive channel between S and D can be viewed as a resistor. Furthermore, since the density of electrons in the channel must increase as VG 3The substrate acts as a fourth terminal, but we ignore that for now. pn 4Note that this depletion region contains only one immobile charge polarity, whereas the depletion region in a junction consists of two areas of negative and positive ions on the two sides of the junction. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 286 (1) 286 Chap. 6 Physics of MOS Transistors VG VG n+ n+ p −substrate (a) VG VG n+ n+ n+ n+ p −substrate (b) Depletion Region p −substrate Free Electrons Negative Ions (c) Figure 6.5 (a) MOSFET with gate voltage, (b) formation of depletion region, (c) formation of channel. becomes more positive (why?), the value of this resistor changes with the gate voltage. Conceptually illustrated in Fig. 6.6, such a voltage-dependent resistor proves extremely useful in analog and digital circuits. G S D Figure 6.6 MOSFET viewed as a voltage-dependent resistor. Example 6.1 In the vicinity of a wireless base station, the signal received by a cellphone may become very strong, possibly “saturating” the circuits and prohibiting proper operation. Devise a variable-gain circuit that lowers the signal level as the cellphone approaches the base station. Solution A MOSFET can form a voltage-controlled attenuator along with a resistor as shown in Fig. 6.7. Since Vcont v in RM Figure 6.7 Use of MOSFET to adjust signal levels. v out R1 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 287 (1) Sec. 6.2 Operation of MOSFET 287 vout vin = R1 RM + R1 ; (6.1) the output signal becomes smaller as Vcont falls because the density of electrons in the channel decreases and RM rises. MOSFETs are commonly utilized as voltage-dependent resistors in “variable-gain amplifiers.” Exercise What happens to RM if the channel length is doubled? In the arrangement of Fig. 6.5(c), no current flows between S and D because the two terminals are at the same potential. We now raise the drain voltage as shown in Fig. 6.8(a) and examine the drain current (= source current). If VG VT H , no channel exists, the device is off, and ID = 0 regardless of the value of VD. On the other hand, if VG VT H , then ID 0 [Fig. 6.8(b)]. In fact, the source-drain path may act as a simple resistor, yielding the ID-VD characteristic shown in Fig. 6.8(c). The slope of the characteristic is equal to 1=Ron, where Ron denotes the “on-resistance” of the transistor.5 VG n+ p −substrate ID n+ VG VD ID VD (a) ID ID VD VG VTH VG (b) ID ID VD VG ID VG3 VG2 VG1 −1 R on VD VD (c) (d) Figure 6.8 (d) ID-VD (a) MOSFET characteristics with gate and drain voltages, for various gate voltages . (b) ID-VG characteristic, (c) ID-VD characteristic, Our brief treatment of the MOS I/V characteristics thus far points to two different views of the operation: in Fig. 6.8(b), VG is varied while VD remains constant whereas in Fig. 6.8(c), VD is varied while VG remains constant. Each view provides valuable insight into the operation of the transistor. 5The term “on-resistance” always refers to that between the source and drain as no resistance exists between the gate and other terminals. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 288 (1) 288 Chap. 6 Physics of MOS Transistors How does the characteristic of Fig. 6.8(b) change if VG increases? The higher density of electrons in the channel lowers the on-resistance, yielding a greater slope. Depicted in Fig. 6.8(d), the resulting characteristics strengthen the notion of voltage-dependent resistance. Recall from Chapter 2 that charge flow in semiconductors occurs by diffusion or drift. How about the transport mechanism in a MOSFET? Since the voltage source tied to the drain creates an electric field along the channel, the current results from the drift of charge. The ID-VG and ID-VD characteristics shown in Figs. 6.8(b) and (c), respectively, play a cen- tral role in our understanding of MOS devices. The following example reinforces the concepts studied thus far. Example 6.2 Sketch the ID-VG and ID-VD characteristics for (a) different channel lengths, and (b) different oxide thicknesses. Solution As the channel length increases, so does the on-resistance.6 Thus, for VG VT H , the drain current begins with lesser values as the channel length increases [Fig. 6.9(a)]. Similarly, ID exhibits a smaller slope as a function of VD [Fig. 6.9(b)]. It is therefore desirable to minimize the channel length so as to achieve large drain currents—an important trend in the MOS technology development. ID ID VTH VG (a) ID VD (b) ID VTH VG VD (c) (d) Fchiganunreel6l.e9ngt(has),I(Dc)-VIGD-cVhGaracchtearriascttiecrsisfotircsdiffoferrdeniftfecrheanntnoexl ildenegtthhisc,k(nbe)sIsDes-,V(Dd) characteristics for different ID-VD characteristics for different oxide thicknesses. How does the oxide thickness, tox, affect the I-V characteristics? As itance between the gate and the silicon substrate decreases. Thus, from Qtox=inCcrVea,swese, the capacnote that a given voltage results in less charge on the gate and hence a lower electron density in the channel. Consequently, the device suffers from a higher on-resistance, producing less drain current for a given gate voltage [Fig. 6.9(c)] or drain voltage [Fig. 6.9(d)]. For this reason, the semiconductor industry has continued to reduce the gate oxide thickness. Exercise The current conduction in the channel is in the form of drift. If the mobility falls at high 6Recall that the resistance of a conductor is proportional to the length. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 289 (1) Sec. 6.2 Operation of MOSFET 289 temperatures, what can we say about the on-resistance as the temperature goes up? While both the length and the oxide thickness affect the performance of MOSFETs, only the former is under the circuit designer’s control, i.e., it can be specified in the “layout” of the transistor. The latter, on the other hand, is defined during fabrication and remains constant for all transistors in a given generation of the technology. Another MOS parameter controlled by circuit designers is the width of the transistor, the dimension perpendicular to the length [Fig. 6.10(a)]. We therefore observe that “lateral” dimen- sions such as L and W can be chosen by circuit designers whereas “vertical” dimensions such as tox cannot. t ox W n+ n+ L (a) ID W ID W S G D VTH VG VD (b) (c) Figure 6.10 acteristics for (a) Dimensions different values of of a MOSFET (W and L are under circuit designer’s W , (c) equivalence to devices in parallel. control.), (b) ID char- How does the gate width impact the I-V characteristics? As W increases, so does the width of the channel, thus lowering the resistance between the source and the drain7 and yielding the trends depicted in Fig. 6.10(b). From another perspective, a wider device can be viewed as two narrower transistors in parallel, producing a high drain current [Fig. 6.10(c)]. We may then surmise that W must be maximized, but we must also note that the total gate capacitance increases with W , possibly limiting the speed of the circuit. Thus, the width of each device in the circuit must be chosen carefully. Channel Pinch-Off Our qualitative study of the MOSFET thus far implies that the device acts as a voltage-dependent resistor if the gate voltage exceeds VT H . In reality, however, the transistor operates as a current source if the drain voltage is sufficiently positive. To understand this effect, we make two observations: (1) to form a channel, the potential difference between the gate and the oxide-silicon interface must exceed VT H ; (2) if the drain voltage remains higher than the source voltage, then the voltage at each point along the channel with respect to ground increases as we go from the source towards the drain. Illustrated in Fig. 6.11(a), this effect arises from the gradual voltage drop along the channel resistance. Since the gate voltage is constant (because the gate is conductive but carries no current in any direction), and since the potential at the oxide-silicon interface rises from the source to the drain, the potential difference between 7Recall that the resistance of a conductor is inversely proportional to the cross section area, which itself is equal to the product of the width and thickness of the conductor. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 290 (1) 290 Chap. 6 Physics of MOS Transistors the gate and the oxide-silicon interface decreases along the x-axis [Fig. 6.11(b)]. The density of electrons in the channel follows the same trend, falling to a minimum at x = L. VG VD n+ n+ ID x Potential Difference = V G < VG = VG−VD V (x ) Gate−Substrate Potential Difference VG x L VD −VG x L (a) (b) Figure 6.11 (a) Channel potential variation, (b) gate-substrate voltage difference along the channel. From these observations, we conclude that, if the drain voltage is high enough to produce VG , VD  VT H , then the channel ceases to exist near the drain. We say the gate-substrate potential difference is not sufficient at x = L to attract electrons and the channel is “pinched off” [Fig. 6.12(a)]. to What VD hVapGp,ensViTfHVDatrixse=s evLe,nthheigvhoelrtathgaendVifGfe,renVcTeHb?etSwineceen V x now goes from 0 at x the gate and the substrate =0 falls tLo1VaTnHd at L. some Does point L1 this mean L the [Fig. 6.12(b)]. The device transistor cannot conduct therefore contains no channel between current? No, the device still conducts: as illustrated in Fig. 6.12(c), once the electrons reach the end of the channel, they experience the high electric field in the depletion region surrounding the drain junction and are rapidly swept to the drain terminal. Nonetheless, as shown in the next section, the drain voltage no longer affects the current significantly, and the MOSFET acts as a constant current source—similar to a bipolar transistor in the forward active region. Note that the source-substrate and drain-substrate junctions carry no current. 6.2.2 Derivation of I/V Characteristics With the foregoing qualitative study, we can now formulate the behavior of MOSFETs in terms of their terminal voltages. Channel Charge Density Our derivations require an expression for the channel charge (i.e., free electrons) per unit length, also called the “charge density.” From Q = CV , we note that if C is the gate capacitance per unit length and V the voltage difference between the gate and the channel, then Q is the desired charge density. Denoting the gate capacitance per unit area bftroyarnCVsioGsxtSo(re[xFpirVge.Ts6sHe.1d. 3(i(Hnae)F]r.e/mMaf2toerore,rowfvFee/r,dwmene2o)ht,eawvbeeoVtwhr=ittheeVCgGaS=te,aWnVdTCHdoxrabiteoncaavucoscletoaungnoetsmfwooribttihhleerecwshpiadergtchte of the exists to the source.) It follows that Q = W CoxVGS , VTH: (6.2) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 291 (1) Sec. 6.2 Operation of MOSFET 291 VG n+ n+ Electrons ID VD VG >V TH VD VG n+ ID n+ VD VG V TH VD (a) VG ID VD n+ n+ E n+ x 0 L1 L (b) (c) Figure 6.12 (a) Pinchoff, (b) variation of length with drain voltage, (c) detailed operation near the drain. W n+ n+ Figure 6.13 Illustration of capacitance per unit length. Note that Q is expressed in coulomb/meter. Now recall from Fig. 6.11(a) that the channel voltage varies along the length of the transistor, and the charge density falls as we go from the source to the drain. Thus, Eq. (6.2) is valid only near the source terminal, where the channel potential remains close to zero. As shown in Fig. 6.14, we denote the channel potential at x by V x and write Qx = W Cox VGS , V x , VTH ; (6.3) noting that V x goes from zero to VD if the channel is not pinched off. Drain Current What is the relationship between the mobile charge density and the current? Consider a bar of semiconductor having a uniform charge density (per unit length) equal to Q and carrying a current I (Fig. 6.15). Note from Chapter 2 that (1) I is given by the total charge that passes through the cross section of the bar in one second, and (2) if the carriers move with a velocity of v m/s, then the charge enclosed in v meters along the bar passes through the cross BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 292 (1) 292 Chap. 6 Physics of MOS Transistors VG n+ V(x ) ID VD n+ x 0 dx L Figure 6.14 Device illustration for calculation of drain current.  section in one second. Since the charge enclosed in v meters is equal to Q v, we have v t = t1 t = t1+ 1 s meters L W h x1 x x1 x V1 V1 Figure 6.15 Relationship between charge velocity and current. I = Q  v; (6.4) As explained in Chapter 2, v = ,nE; (6.5) = +n dV dx ; (6.6) where dV =dx denotes the derivative of the voltage at a given point. Combining (6.3), (6.4), and (6.6), we obtain ID = W Cox VGS , V x , VT H n dV x dx : (6.7) IvnatreWyreshsuitclienhgittlhyias,tpstiohnsecsepibrIloDedtuomcstuoosltfvreVeGtmhSeai,anbcVoovnexsdtai,fnfteVraeTlnoHtnigaalntehdqeducaVht=iaodnnxnteoilso(iwbntdhaeyipn?e)Vn, dVxenxtinofatenxrd.mdsVo=fdIxD must (and the reader is encouraged to do that), our immediate need is to find an expression for ID in terms of the terminal voltages. To this end, we write Z x=L x=0 IDdx = Z V x=VDS V x=0 nCoxW VGS , V x , VT H dV: (6.8) That is, ID = 1 2 nCox W L 2VGS , VTHVDS , VD2S : (6.9) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 293 (1) Sec. 6.2 Operation of MOSFET 293 We now examine this important equation from different perspectives to gain more insight. First, the linear dependence of ID upon n, Cox, and W=L is to be expected: a higher mobility yields a greater current for a given drain-source voltage; a higher gate oxide capacitance leads to a larger electron density in the channel for a given gate-source voltage; and a larger W=L (called the device “aspect ratio”) is equivalent to placing more transistors in parallel [Fig. 6.10(c)]. Second, for a constant VGS, ID varies parabolically with VDS (Fig. 6.16), reaching a maximum of ID 1 2 µ n C ox W L (VGS 2 V TH − (− Figure 6.16 Parabolic ID-VDS characteristic. VGS VTH VDS ID;max = 1 2 nCox W L VGS , VT H 2 (6.10) at VDS (rather = VGS , VTH. It is common than 27.8) to emphasize the to write W=L as the choice of W and L. ratio of two values e.g., 5 m=0:18 m While only the ratio appears in many MOS equations, the individual values of W and L also become critical in most cases. For exam- ple, if both W and L are doubled, the ratio remains unchanged but the gate capacitance increases. Example 6.3 Plot the ID-VDS characteristics for different values of VGS. Solution As VGS increases, so do ID;max and exhibit maxima that follow a parabolic VshGaSpe,thVeTmHse. lIvlelussbtreactaeudseinIDFi;gm.a6x.17,VthGeSc,harVaTcHteri2s.tics ID Parabola I D,max4 VGS3 I D,max3 I D,max2 VGS2 VGS1 VDS VGS1 VTH VGS2 VTH VGS3 VTH − − − Figure 6.17 MOS characteristics for different gate-source voltages. Exercise What happens to the above plots if tox is halved? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 294 (1) 294 Chap. 6 Physics of MOS Transistors , be The nonlinear relationship modeled as a simple linear rbeestiwsteoer.nHIoDwaenvder,ViDf SVDreSveals2thVaGtSthe transistor cannot generally VT H , Eq. (6.9) reduces to: ID  nCox W L VGS , VT H VDS ; (6.11) exhibiting a linear ID-VDS behavior for a given VGS. In fact, the equivalent on-resistance is given by VDS=ID: Ron = nCox W L 1 VGS , VT H  : (6.12) From another perspective, at small VDS (near the origin), the parabolas in Fig. 6.17 can be approximated by straight lines having different slopes (Fig. 6.18). ID VGS3 ID VGS2 VGS1 VDS Figure 6.18 Detailed characteristics for small VDS. VGS3 VGS2 VGS1 VDS As predicted in Section 6.2.1, (6.12) suggests that the on-resistance can be controlled by the gate-source voltage. In particular, for VGS = VT H , Ron = 1, i.e., the device can operate as an electronic switch. Example 6.4 A cordless telephone incorporates a single antenna for reception and transmission. Explain how the system must be configured. Solution The system is designed such that the phone receives for half of the time and transmits for the other half. Thus, the antenna is alternately connected to the receiver and the transmitter in regular intervals, e.g., every 20 ms (Fig. 6.19). An electronic antenna switch is therefore necessary here.8 Receiver Receiver Transmitter Figure 6.19 Role of antenna switch in a cordless phone. 8Some cellphones operate in the same manner. Transmitter BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 295 (1) Sec. 6.2 Operation of MOSFET 295 Exercise Some systems employ two antennas, each of which receives and transmits signals. How many switches are needed? In most applications, it is desirable to achieve a low on-resistance for MOS switches. The circuit designer must therefore maximize W=L and VGS. The following example illustrates this point. Example 6.5 In the cordless phone of Example 6.4, the switch connecting the transmitter to the antenna must negligibly attenuate the signal, e.g., by no more than 10. If VDD = 1:8 V, nCox = 100 A=V2, and VT H = 0:4 V, determine the minimum required aspect ratio of the switch. Assume the antenna can be modeled as a 50- resistor. Solution As depicted in Fig. 6.20, we wish to ensure R on Vout R on Vin 50 Ω Rant Transmitter Figure 6.20 Signal degradation due to on-resistance of antenna switch. Vout Vin  0:9 (6.13) and hence Ron  5:6 : (6.14) Setting VGS to the maximum value, VDD, we obtain from Eq. (6.12), W L  1276: (6.15) (Since wide transistors introduce substantial capacitance in the signal path, this choice of W=L may still attenuate high-frequency signals.) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 296 (1) 296 Chap. 6 Physics of MOS Transistors Exercise What W=L is necessary if VDD drops to 1.2 V? Triode and Saturation Regions Equation (6.9) expresses the drain current in terms of the , device terminal voltages, implying that the current begins to fall for VDS say the device parabola). We operates also use in the “triode region”9 the term “deep triode if VDS region” forVVGDSS VT2HV(tGhSe VGS , VTH. rising section of , VTH , where We the the transistor operates as a resistor. , In reality, the drain current reaches “saturation,” that is, becomes constant for VDS VGS , VT H (Fig. 6.21). To understand why, recall from Fig. 6.12 that the channel experiences pinch-off if VDS = VGS VT H . Thus, further increase in VDS simply shifts the pinch-off point slightly toward the drain. Also, recall that Eqs. (6.7) and (6.8) are valid only where channel charge exists. It follows that the integration in (6.8) must encompass only the channel, i.e., from x = 0 to x = L1 in Fig. 6.12(b), and be modified to ID 1 2 µn C ox W L (VGS 2 V TH Triode Region Saturation Region − (− VGS VTH VDS Figure 6.21 Overall MOS characteristic. Z x=L1 x=0 IDdx = Z V x=VGS,VTH V x=0 nCoxW VGS , V x , VT H dV: (6.16) Note that the upper limits correspond to the channel pinch-off point. In particular, the integral on the right hand side is evaluated up to VGS , VT H rather than VDS. Consequently, ID = 1 2 nCox W L1 VGS , VT H 2 ; (6.17)  a result independent of , the “overdrive voltage,” VthDeSquaanndtiitdyenVtGicSal toVTIDH;mpalaxysina(k6e.1y0r)oilfe we assume L1 in MOS circuits. are sometimes called “square-law” devices to emphasize the relationship between L. Called MOSFETs ID and the overdrive. For the sake of brevity, we hereafter denote L1 with L. The I-V characteristic of Fig. 6.21 resembles that of bipolar devices, with the triode and saturation regions in MOSFETs appearing similar to saturation and forward active regions in bipolar transistors, respectively. It is unfortunate that the term “saturation” refers to completely different regions in MOS and bipolar I-V characteristics. 9Also called the “linear region.” BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 297 (1) Sec. 6.2 Operation of MOSFET 297 We employ the conceptual illustration in Fig. 6.22 to determine the region of operation. Note that the gate-drain potential difference suits this purpose and we need not compute the gatesource and gate-drain voltages separately. VTH = − (− ID 1 2 µn C ox W L (VGS 2 V TH > VTH Triode Region Saturation Region Saturated M1 VGS VTH VDS (a) (b) Figure 6.22 Illustration of triode and saturation regions based on the gate and drain voltages. Exhibiting a “flat” current in the saturation region, a MOSFET can operate as a current source , having a value given by (6.17). Furthermore, the square-law dependence of ID upon VGS VT H suggests that the device can act as a voltage-controlled current source. Example 6.6 Calculate the bias current of M1 in Fig. 6.23. Assume nCox = 100 A=V2 and VTH = 0:4 V. If the gate voltage increases by 10 mV, what is the change in the drain voltage? VDD = 1.8 V RD 5 kΩ ID X M1 W 2 1V L 0.18 Figure 6.23 Simple MOS circuit. Solution It is unclear a priori Since VGS = 1 V, in which region M1 operates. Let us assume M1 is saturated and proceed. ID = 1 2 nCox W L VGS , VT H 2 (6.18) = 200 A: (6.19) We must check our assumption by calculating the drain potential: VX = VDD , RDID = 0:8 V: (6.20) (6.21) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 298 (1) 298 Chap. 6 Physics of MOS Transistors The drain voltage is lower than the gate voltage, but by less than VT H . The illustration in Fig. 6.22 therefore indicates that M1 indeed operates in saturation. If the gate voltage increases to 1.01 V, then ID = 206:7 A; (6.22) lowering VX to VX = 0:766 V: (6.23) Fortunately, M1 is still saturated. The 34-mV change in VX reveals that the circuit can amplify the input. Exercise What choice of RD places the transistor at the edge of the triode region? It is instructive to identify several points of contrast between bipolar and MOS devices. (1) A bipolar transistor with VBE = VCE resides at the edge of the active region whereas a MOSFET approaches the edge of saturation if its drain voltage falls below its gate voltage by VT H . (2) Bipolar devices exhibit an exponential IC-VBE characteristic while MOSFETs display a square- law dependence. That is, the former provide a greater transconductance than the latter (for a given bias current). (3) In bipolar circuits, most transistors have the same dimensions and hence the same IS, whereas in MOS circuits, the aspect ratio of each device may be chosen differently to satisfy the design requirements. (4) The gate of MOSFETs draws no bias current.10 Example 6.7 Determine the value of W=L in Fig. the drain voltage change for a 1-mV 6.23 that change at pthlaecgeastMe. A1 sastuthmeeeVdTgHe of saturation = 0:4 V. and calculate Solution With VGS = +1 V, the drain voltage must fall to VGS , VTH = 0:6 V for M1 to enter the triode region. That is, ID = VDD , VDS RD = 240 A: (6.24) (6.25) Since ID scales linearly with W=L, W L jmax = 240 200 A A  2 0:18 = 02::148: If VGS increases by 1 mV, (6.26) (6.27) ID = 248:04 A; (6.28) 10New generations of MOSFETs suffer from gate “leakage” current, but we neglect this effect here. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 299 (1) Sec. 6.2 Operation of MOSFET changing VX by VX = ID  RD = 4:02 mV: The voltage gain is thus equal to 4.02 in this case. Exercise Repeat the above example if RD is doubled. 299 (6.29) (6.30) Example 6.8 Calculate the maximum allowable gate voltage in Fig. 6.24 if M1 must remain saturated. VDD = 1.8 V RD 5 kΩ ID X VGS M1 W 2 = L 0.18 Figure 6.24 Simple MOS circuit. Solution At the edge of saturation, VGS , VTH = VDS = VDD , RDID: Substituting for ID from (6.17) gives VGS , VT H = VDD , RD 2 nCox W L VGS , VT H 2; (6.31) and hence q VGS , VTH = ,1 + 1 + 2RDVDD RDnCox WL nCox WL : (6.32) Thus, VGS = ,1 + q 1 + 2RDVDD nCox WL RDnCox WL + VTH: (6.33) Exercise Calculate the value of VGS if munCox = 100 A=V2 and VTH = 0:4 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 300 (1) 300 Chap. 6 Physics of MOS Transistors 6.2.3 Channel-Length Modulation In our study of the pinch-off effect, we observed that the point at which the channel vanishes in FifnaicgFt.im6g..o16v2.e2(bs5),tovthwairsaierpdshwtehnietohmsVoeuDnrSocentoyasiseotlhmdeseaderlxaatirengnevtr.odCltraaalgilneedcinu“crcrrheeananstneases.lV-IlnDenSogtithnhecmrrewoadosuerdslasbt,ieotchnae”uvasaenldIuDeilloufstL1ra=1tLeind1 in Eq. (6.17). Similar to the Early effect in bipolar devices, channel-length modulation results in a finite output impedance given by the inverse of the ID-VDS slope in Fig. 6.25. ID 1 2 µn C ox W L (VGS 2 V TH − (− VGS VTH VDS Figure 6.25 Variation of ID in saturation region. To account for channel-length modulation, we assume L is constant, but multiply the right hand side of (6.17) by a corrective term: ID = 1 2 nCox W L VGS , VT H 2 1 + VDS ; (6.34) where  is called the “channel-length modulation coefficient.” While only an approximation, this linear dependence of ID upon VDS still provides a great deal of insight into the circuit design implications of channel-length modulation. Unlike the Early effect in bipolar devices (Chapter 4), the amount of channel-length modula- tion is under the circuit designer’s control. This is because  is inversely proportional to L: for a longer channel, the relative change in L (and hence in ID) for a given change in VDS is smaller (Fig. 6.26).11 (By contrast, the base width of bipolar devices cannot be adjusted by the circuit designer, yielding a constant Early voltage for all transistors in a given technology.) L1 ID L2 ID VDS VDS Figure 6.26 Channel-length modulation. Example 6.9 A MOSFET change in ID carries if VDS a drain rises to current of 1 V and  1 mA = 0:1 Vw,it1h. VDS = What is 0:5 V in saturation. Determine the device output impedance? the  11Since different MOSFETs in a circuit may be sized for different ’s, we do not define a quantity similar to the Early voltage here. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 301 (1) Sec. 6.2 Operation of MOSFET 301 Solution We write ID1 = 1 2 nCox W L VGS , VT H 21 + VDS1 ID2 = 1 2 nCox W L VGS , VT H 21 + VDS2 and hence ID2 = ID1 1 1 + + VDS2 VDS1 : With ID1 = 1 mA, VDS1 = 0:5 V, VDS2 = 1 V, and  = 0:1 V,1, ID2 = 1:048 mA: The change in ID is therefore equal to 48 A, yielding an output impedance of rO = VDS ID = 10:42 k : (6.35) (6.36) (6.37) (6.38) (6.39) (6.40) Exercise Does W affect the above results? The above example reveals that channel-length modulation limits the output impedance of MOS current sources. The same effect was observed for bipolar current sources in Chapters 4 and 5. Example 6.10 Assuming  1=L, calculate ID and rO in Example 6.9 if both W and L are doubled. Solution In Eqs. (6.35) and (6.36), W=L remains unchanged but  drops to 0.05 V,1. Thus, ID2 = ID1 1 1 + + VDS2 VDS1 = 1:024 mA: (6.41) (6.42) That is, ID = 24 A and rO = 20:84 k : (6.43) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 302 (1) 302 Chap. 6 Physics of MOS Transistors Exercise What output impedance is achieved if W and L are quadrupled and ID is halved. 6.2.4 MOS Transconductance As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: gm = @ID @VGS : (6.44) This quantity serves as a measure of the “strength” of the device: a higher value corresponds to a greater change in the drain current for a given change in VGS. Using Eq. (6.17) for the saturation region, we have gm = nCox W L VGS , VT H ; (6.45) concluding that (1) gm linearly proportional to is linearly VGS , VT proportional to W=L for a H for a given W=L. Also, given VGS , VTH, substituting for VGS and (2) , VTH gm is from (6.17), we obtain gm = r 2nCox W L ID: (6.46) p That is, a given W(1=) Lgm. Misopreroovpeorr,tidoivniadlitnog W=L for a given ID, (6.45) by (6.17) gives and (2) gm is proportional to pID for gm = 2ID VGS , VT H ; (6.47) prervoepaolritnigonthaal tto(1V)GgSm is , linearly proportional VTH for a given ID. to ID for a given VGS Summarized in Table ,VTH, and (2) gm is inversely 6.1, these dependencies prove critical in understanding performance trends of MOS devices and have no counterpart in bipolar transistors.12. Among these three expressions for gm, (6.46) is more frequently used because ID may be predetermined by power dissipation requirements. Example 6.11 For a MOSFET operating in saturation, how do gm and VGS , VT H change if both W=L and ID are doubled? Solution Equation (6.46) indicates that gm is also doubled. Moreover, Eq. (6.17) suggests that the over- drive remains constant. These results can be understood intuitively if we view the doubling of W=L and ID as shown in Fig. 6.27. Indeed, if VGS remains constant and the width of the device is doubled, it is as if two transistors carrying equal currents are placed in parallel, thereby doubling the transconductance. The reader can show that this trend applies to any type of transistor. g = I =V 12There is some resemblance between the second column and the behavior of m C T . If the bipolar transistor V I g width is increased while BE remains constant, then both C and m increase linearly. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 303 (1) Sec. 6.2 Operation of MOSFET 303 W L Constant VGS VTH Variable W L Variable VGS VTH Constant − − g m ID g m VGS VTH − g m ID g W mL Table 6.1 Various dependencies of gm. − − W L Variable VGS VTH Constant g W m L g 1 m VGS VTH VGS VGS VDS VDS Figure 6.27 Equivalence of a wide MOSFET to two in parallel. Exercise How do gm and VGS , VTH change if only W and ID are doubled? 6.2.5 Velocity Saturation Recall from Section 2.1.3 that at high electric fields, carrier mobility degrades, eventually lead- ing to a constant velocity. Owing to their very short channels (e.g., 0.1 m), modern MOS devices experience velocity saturation even with drain-source voltages as low as 1 V. As a result, the I/V characteristics no longer follow the square-law behavior. Let us examine the derivations in Section 6.2.2 under velocity saturation conditions. Denoting the saturated velocity by vsat, we have ID = vsat  Q (6.48) = vsat  W CoxVGS , VTH: (6.49) Interestingly, ID now exhibits a linear dependence on VGS , VT H and no dependence on L.13 This section can be skipped in a first reading. L V 13Of course, if is increased substantially, while DS remains constant, then the device experiences less velocity saturation and (6.49) is not accurate. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 304 (1) 304 Chap. 6 Physics of MOS Transistors We also recognize that gm = @ID @VGS = vsatW Cox; a quantity independent of L and ID. (6.50) (6.51) 6.2.6 Other Second-Order Effects Body Effect In our study of MOSFETs, we have assumed that both the source and the substrate (also called the “bulk” or the “body”) are tied to ground. However, this condition need not hold in all circuits. For example, if the source terminal rises to a positive voltage while the substrate is at zero, then the source-substrate junction remains reverse-biased and the device still operates properly. Figure 6.28 illustrates this case. The source terminal is tied to a potential VS with respect to ground while the substrate is grounded through a p+ contact.14 The dashed line added to the transistor symbol indicates the substrate terminal. We denote the voltage difference between the source and the substrate (the bulk) by VSB. Substrate Contact VS VG p+ n+ p −substrate Figure 6.28 Body effect. VD n+ VD VG VS An interesting phenomenon occurs as the source-substrate potential difference departs from zero: the threshold voltage of the device changes. In particular, as the source becomes more positive with respect to the substrate, VT H increases. Called “body effect,” this phenomenon is formulated as VTH = VTH0 + pj2 F + VSBj , pj2 F j; (6.52) p where VT H0 denotes the threshold voltage with VSB = 0 (as studied earlier), and and F are technology-dependent parameters having typical values of 0.4 V and 0.4 V, respectively. Example 6.12 In the circuit of Fig. 6.28, assume VS = 0:5 V, VG = VD = 1:4 V, nCox = 100 A=V2, W=L = 50, and VTH0 = 0:6 V. Determine the drain current if  = 0. Solution Since the source-body voltage, VSB = 0:5 V, Eq. (6.52) and the typical values for and F yield VTH = 0:698 V: (6.53) p 14The + island is necessary to achieve an “ohmic” contact with low resistance. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 305 (1) Sec. 6.3 MOS Device Models Also, with VG = VD, the device operates in saturation (why?) and hence ID = 1 2 nCox W L VG , VS , VT H 2 = 102 A: 305 (6.54) (6.55) Exercise Sktech the drain current as a function of VS as VS goes from zero to 1 V. Body effect manifests itself in some analog and digital circuits and is studied in more advanced texts. We neglect body effect in this book. Subthreshold Conduction The derivation of the MOS I/V characteristic has assumed that the transistor abruptly gradual effect, and the turns on as VGS device conducts a rsemacahllecsuVrrTeHnt. eIvnenrefaolritVy,GfSormaVtTioHn. oCfatlhleedc“hsaunbntehlreissha- old conduction,” this effect has become a critical issue in modern MOS devices and is studied in more advanced texts. 6.3 MOS Device Models With our study of MOS I/V characteristics in the previous section, we now develop models that can be used in circuit analysis and design. 6.3.1 Large-Signal Model For arbitrary voltage and current levels, we must resort to Eqs. (6.9) and (6.34) to express the device behavior: ID = 1 2 nCox W L 2VGS , VTHVDS , VD2S Triode Region (6.56) ID = 1 2 nCox W L VGS , VTH21 + VDS Saturation Region (6.57) In the saturation region, the transistor acts as a voltage-controlled current source, lending itself , to the model shown in Fig. 6.29(a). Note that ID does depend on VDS and is therefore not an ideal current source. For VDS VGS VT H , the model must reflect the triode region, but it can still incorporate a voltage-controlled current source as depicted in Fig. 6.29(b). Finally, if VDS 2VGS , VT H , the transistor can be viewed as a voltage-controlled resistor [Fig. 6.29(c)]. In all three cases, the gate remains an open circuit to represent the zero gate current. Example 6.13 Sketch  = 0. the drain current of M1 in Fig. 6.30(a) versus V1 as V1 varies from zero to VDD. Assume Solution Noting that the device operates in saturation (why?), we write ID = 1 2 nCox W L VGS , VT H 2 (6.58) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 306 (1) (− 306 Chap. 6 Physics of MOS Transistors (− −< < VGS VTH VDS VGS VTH G D ID 1 2 µn C ox W L (VGS (− VTH 2 (1+ λVDS ) S −> < (a) VGS VTH VDS VGS VTH G D ID 1 2 µ n C ox W L [ 2 (VGS VTH VDS + VD2S ] S (b) < VGS VTH VDS 2 (VGS VTH (− >> G D R on = 1 µ n C ox W L (VGS V TH S (c) Figure 6.29 MOS models for (a) saturation region, (b) triode region, (c) deep triode region. VDD ID M1 V1 − VDD VTH V1 (a) (b) Figure 6.30 (a) Simple MOS circuit, (b) variation of ID with V1. = 1 2 nCox W L VDD , V1 , VT H 2 : (6.59) At so dVo1es=ID0., current thus vIVfaGrViS1es=raesaVcilhDleuDsstVraaDntdeDdt,hineVFdTiegHv.i6,c.eV3Gc0aS(brrd)i.reNospomsteatoxthiVmaTtu,Homw, tciunurgrnritenongtb.tohAdesytVeraf1fnesrciists,etoVs,rTVoHfGfv.SaTrfhaieellssdwraaintihdn V1 if the substrate is tied to ground. Exercise Repeat the above example if the gate of M1 is tied to a voltage equal to 1.5 V and VDD = 2 V. 6.3.2 Small-Signal Model If the bias currents and voltages of a MOSFET are only slightly disturbed by signals, the nonlinear, large-signal models can be reduced to linear, small-signal representations. The development BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 307 (1) Sec. 6.3 MOS Device Models 307 of the model proceeds in a manner similar to that in Chapter 4 for bipolar devices. Of particular interest to us in this book is the small-signal model for the saturation region. Viewing the transistor as a voltage-controlled current source, we draw the basic model as in Fig. 6.31(a), where iD = gmvGS and the gate remains open. To represent channel-length modulation, i.e., variation of iD with vDS, we add a resistor as in Fig. 6.31(b): G D G D v GS gmv GS v GS gmv GS r O S S (a) (b) Figure 6.31 (a) Small-signal model of MOSFET, (b) inclusion of channel-length modulation. rO = @ID @VDS ,1 (6.60) = 1 1 2 nCox W L VGS : , VTH2   (6.61) Since channel-length modulation is relatively small, the denominator of (6.61) can be approxi- mated as ID  , yielding rO  1 ID : (6.62) Example 6.14 A  =MO0:S1FVE,T1i,scablicauseladteatitas drain current of 0.5 mA. small-signal parameters. If nCox = 100 A=V2, W=L = 10, and Solution We have gm = r 2nCox W L ID = 1 1 k : (6.63) (6.64) Also, rO = 1 ID = 20 k : (6.65) (6.66) This means that the intrinsic gain, gmrO, (Chapter 4) is equal to 20 for this choice of device dimensions and bias current. Exercise Repeat the above example if W=L is doubled. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 308 (1) 308 Chap. 6 Physics of MOS Transistors 6.4 PMOS Transistor Having seen both npn and pnp bipolar transistors, the reader may wonder if a p-type counterpart exists for MOSFETs. Indeed, as illustrated in Fig. 6.32(a), changing the doping polarities of the substrate and the S/D areas results in a “PMOS” device. The channel now consists of holes and is formed if the gate voltage is below the source potential by one threshold voltage. That is, to turn the device on, VGS VT H , where VT H itself is negative. Following the conventions used for bipolar devices, we draw the PMOS device as in Fig. 6.32(b), with the source terminal identified by the arrow and placed on top to emphasize its higher potential. The transistor operates in the , j j triode to VG region if VT H the drain = VG + voltage VTH . is near Figure the source potential, approaching saturation as 6.32(c) conceptually illustrates the gate-drain VD falls voltages required for each region of operatioGn. S D S p+ p+ n −substrate (a) G ID D (b) Triode Region Edge of Saturation Saturation Region > VTHP VTHP (c) < VTHP Figure 6.32 (a) Structure of PMOS device, (b) PMOS circuit symbol, (c) illustration of triode and saturation regions based on gate and drain voltages. Example 6.15 In the circuit of Fig. 6.33, determine the region Assume VDD = 2:5 V and jVTHj = 0:5 V. of operation of M1 as V1 goes from VDD to zero. VDD M1 V1 1V Figure 6.33 Simple PMOS circuit. Solution For V1 = VDD, VGS = 0 and M1 is off. As V1 falls and approaches VDD,jVTHj, the gate-source BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 309 (1) Sec. 6.4 PMOS Transistor 309 pVMVoGD1tSDeinsb,tieaacjtlVoitTmshHeneesjegd=magtoei+vreoe2fenVntehogweuahtgtirihviloeetodVaenfDodrre=mtghieo+antc1r.haVAanns;sinis.Veetol1.,orgMfcohue1orsrilesebnsse,taltortuuiwsrrenas0itn.e.5gdFotV[hFr,eiVtgdh1.ee6v=.ti3rca+2en(o1scin)sV].t.oAA,rtsetjhVnVit1TserfHpsaoljtlihsn=etf,u0tVrr:tGi5hoedV=re,, region further. The voltage and current polarities in PMOS devices can prove confusing. Using the current direction shown in Fig. 6.32(b), we express ID in the saturation region as ID;sat = , 1 2 pCox W L VGS , VT H 21 , VDS ; (6.67) where  is multiplied by a negative sign.15 In the triode region, ID;tri = , 1 2 pCox W L 2VGS , VTHVDS , VD2S : (6.68) Alternatively, both equations can be expressed in terms of absolute values: jID;satj = 1 2 pCox W L jVGSj , jVT H j21 + jVDS j jID;trij = 1 2 pCox W L 2jVGSj , jVTHjjVDSj , VD2S : (6.69) (6.70) The small-signal model of PMOS transistor is identical to that of NMOS devices (Fig. 6.31). The following example illustrates this point. Example 6.16 6 For the configurations RY . Assume  = 0. shown in Fig. 6.34(a), determine the small-signal resistances RX and RX M1 (a) VDD iX M2 vx v1 gm1v 1 r O1 iY v1 vY RY (b) M2 gm2v 1 r O2 (c) Figure 6.34 (a) Diode-connected NMOS and PMOS devices, (b) small-signal model of (a), (c) smallsignal model of (b). Solution For the NMOS version, the small-signal equivalent appears as depicted in Fig. 6.34(b), yielding RX = vX iX = gm1vX + vX rO1  1 iX (6.71) (6.72) and 15To make this equation more consistent with express ID as 1=2pCoxW=LVGS , VthTaHt of2N1M+OSdVeDviSce.s [Eq. But,  (6.34)], we can define itself to be negative  a negative carries little physical meaning. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 310 (1) 310 Chap. 6 Physics of MOS Transistors = 1 gm1 jjrO1 : (6.73) For the PMOS version, we draw the equivalent as shown in Fig. 6.34(c) and write RY = vY iY = gm2vY + vY rO1  1 iY = 1 gm2 jjrO2: (6.74) (6.75) (6.76) In both cases, the small-signal resistance is equal to 1=gm if  ! 0. In analogy with their bipolar counterparts [Fig. 4.44(a)], the structures shown in Fig. 6.34(a) are called “diode-connected” devices and act as two-terminal components: we will encounter many applications of diode-connected devices in Chapters 9 and 10. Owing to the lower mobility of holes (Chapter 2), PMOS devices exhibit a poorer performance than NMOS transistors. For example, Eq. (6.46) indicates that the transconductance of a PMOS device is lower for a given drain current. We therefore prefer to use NMOS transistors wherever possible. 6.5 CMOS Technology Is it possible to build both NMOS and PMOS devices on the same wafer? Figures 6.2(a) and 6.32(a) reveal that the two require different types of substrate. Fortunately, a local n-type substrate can be created in a p-type substrate, thereby accommodating PMOS transistors. As illus- trated in Fig. 6.35, an “n-well” encloses a PMOS device while the NMOS transistor resides in the p-substrate. NMOS PMOS Device G Device G B S D S D B p+ n+ n+ p+ p+ n+ p −substrate Figure 6.35 CMOS technology. n −well Called “complementary MOS” (CMOS) technology, the above structure requires more complex processing than simple NMOS or PMOS devices. In fact, the first few generations of MOS technology contained only NMOS transistors,16 and the higher cost of CMOS processes seemed prohibitive. However, many significant advantages of complementary devices eventually made CMOS technology dominant and NMOS technology obsolete. 16The first Intel microprocessor, the 4004, was realized in NMOS technology. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 311 (1) Sec. 6.6 Comparison of Bipolar and MOS Devices 311 6.6 Comparison of Bipolar and MOS Devices Having studied the physics and operation of bipolar and MOS transistors, we can now compare their properties. Table 6.2 shows some of the important aspects of each device. Note that the exponential IC-VBE dependence of bipolar devices accords them a higher transconductance for a given bias current. Bipolar Transistor Exponential Characteristic Active: VCB > 0 Saturation: VCB < 0 Finite Base Current Early Effect Diffusion Current − MOSFET Quadratic Characteristic Saturation: VDS VGS VTH Triode: VDS VGS VTH Zero Gate Current Channel−Length Modulation Drift Current Voltage−Dependent Resistor −> −< Table 6.2 Comparison of bipolar and MOS transistors. 6.7 Chapter Summary A voltage-dependent current source can form an amplifier along with a load resistor. MOSFETs are electronic devices that can operate as voltage-dependent current sources. A MOSFET consists of a conductive plate (the “gate”) atop a semiconductor substrate and two junctions (“source” and “drain”) in the substrate. The gate controls the current flow from the source to the drain. The gate draws nearly zero current because an insulating layer separates it from the substrate. As the gate voltage rises, a depletion region is formed in the substrate under the gate area. Beyond a certain gate-source voltage (the “threshold voltage”), mobile carriers are attracted to the oxide-silicon interface and a channel is formed. If the drain-source voltage is small, the device operates a voltage-dependent resistor. As the drain voltage rises, the charge density near the drain falls. If the drain voltage reaches one threshold below the gate voltage, the channel ceases to exist near the drain, leading to “pinch-off.” MOSFETs operate in the “triode” region if the drain voltage is more than one threshold below the gate voltage. In this region, the drain current is a current is also proportional to the device aspect ratio, W=L. function of VGS and VDS . The tem MOSFETs enter the “saturation region” if channel pinch-off occurs, i.e., the drain voltage is less than one threshold below the gate volatge. In this region, the drain current is proportional to VGS , VTH2. MOSFETs operating in the saturation region behave as current sources and find wide appli- cation in microelectronic circuits. , As the drain voltage exceeds VGS VT H and pinch-off occurs, the drain end of the chan- nel begins to move toward the source, reducing the effective length of the device. Called “channel-length modulation,” this effect leads to variation of drain current in the saturation region. That is, the device is not an ideal current source. A measure of the small-signal performance of voltage-dependent current sources is the “transconductance,” defined as the change in the output current divided by the change in BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 312 (1) 312 Chap. 6 Physics of MOS Transistors the input voltage. The transconductance of MOSFETs can be expressed by one of three equations in terms of the bias voltages and currents. Operation across different regions and/or with large swings exemplifies “large-signal behavior.” If the signal swings are sufficiently small, the MOSFET can be represented by a small-signal model consisting of a linear voltage-dependent current source and an output resistance. The small-signal model is derived by making a small change in the voltage difference between two terminals while the the other voltages remain constant. The small-signal models of NMOS and PMOS devices are identical. NMOS and PMOS transistors are fabricated on the same substrate to create CMOS technology. Problems In the pCox following problems, = 100 A=V2, and unless otherwise stated, assume nCox VTH = 0:4 V for NMOS devices and = ,0:4 200 A=V2, V for PMOS devices. 1. Two identical MOSFETs are placed in series as shown in Fig. 6.36. If both devices operate Figure 6.36 M1 M2 W W L L M eq as resistors, explain intuitively why this combination is equivalent to a single transistor, Meq. What are the width and length of Meq? 2. Consider a MOSFET experiencing pinch-off near the drain. Equation (6.4) indicates that the charge density and carrier velocity must change in opposite directions if the current remains constant. How can this relationship be interpreted at the pinch-off point, where the charge density approaches zero? 3. Calculate the total charge stored in the channel of an NMOS device if W = 5 m, L = 0:1 m, and VGS , VTH = 1 V. Assume VDS = 0. Cox = 10 fF=m2, 4. Referring to Fig. 6.11 and assuming that VD 0, (a) Sketch the electron density in the channel as a function of x. (b) Sketch the local resistance of the channel (per unit length) as a function of x. 5. AansdsudmVi=ndgxIaDs is constant, solve Eq. (6.7) to obtain an expression a function of x for different values of W or VT H . for V x. Plot both V x 6. The drain current of a MOSFET in the triode region is expressed as ID = nCox W L  VGS , VT H VDS , 1 2 VD2S  : (6.77) Suppose the values of nCox and tities by applying different values W=L are unknown. of VGS , VTH and Is it possible to determine VDS and measuring ID? these quan- 7. An NMOS device carries 1 mA with VGS,VTH = 0:6 V and 1.6 mA with VGS,VTH = 0:8 V. If the device operates in the triode region, calculate VDS and W=L. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 313 (1) Sec. 6.7 Chapter Summary 313 8. Compute the transconductance of a MOSFET operating in the triode @ID=@VGS for a constant VDS. Explain why gm = 0 for VDS = 0. region. Define gm = 9. An NMOS device operating with a small drain-source voltage serves as a resistor. If the supply voltage is 1.8 V, what is the minimum on-resistance that can be achieved with W=L = 20? 10. We wish to use an NMOS transistor as a variable resistor with Ron = 500 at VGS = 1 V and Ron = 400 at VGS = 1:5 V. Explain why this is not possible. 11. For a MOS transistor biased in the triode region, we can define an incremental drain-source resistance as rDS;tri = @ID @VDS ,1 : (6.78) Derive an expression for this quantity. 12. It is possible to define an “intrinsic time constant” for a MOSFET operating as a resistor: = RonCGS; (6.79) where CGS = W LCox. Obtain an expression for and explain what the circuit designer must do to minimize the time constant. 13. In the circuit of Fig. 6.37, M1 serves as an electronic switch. If Vin  0, determine W=L VG M1 Vin Vout RL Figure 6.37 such that the circuit attenuates the signal by only 5. Assume VG = 1:8 V and RL = 100 . 14. In the circuit of Fig. 6.37, the input is a small sinusoid superimposed on a dc level: Vin = V0 (a) cFoosr!Vt1+=V01,, where obtain (b) Repeat part (a) for WV0=iLs V1 = on the order of a few millivolts. 0in:5teVr.mCsoomf pRaLreatnhde other parameters results. so that Vout = 0:95Vin. 15. For an NMOS device, plot ID as a function of VGS for different values of VDS. 16. In Fig. 6.17, explain why the peaks of the parabolas lie on a parabola themselves. 17. Advanced MOS devices do not follow the square-law behavior expressed by Eq. (6.17). A somewhat better approximation is: ID = 1 2 nCox W L VGS , VTH ; (6.80) where is less than 2. Determine the transconductance of such a device. 18. For MOS devices with very short channel lengths, the square-law behavior is not valid, and we may instead write: ID = W CoxVGS , VTHvsat; (6.81) where vsat is a relatively constant velocity. Determine the transconductance of such a device. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 314 (1) 314 Chap. 6 Physics of MOS Transistors 0.5 V M1 0.5 V 2V 1.5 V (a) M1 0.5 V (b) 2V 1.5 V M1 0.5 V 0.5 V (c) 1.5 V M1 0.5 V (d) 1.5 V M1 (e) 0.5 V M1 0.5 V (f) 0.5 V M1 0.5 V M1 1V M1 0.5 V 0.5 V (g) Figure 6.38 (h) (i) 19. Determine the region of operation of M1 in each of the circuits shown in Fig. 6.38. 20. Determine the region of operation of M1 in each of the circuits shown in Fig. 6.39. M1 1V M1 1V 1V 0.2 V (a) M1 0.2 V 1V 0.2 V (b) M1 0.7 V (c) (d) Figure 6.39 21. Two current sources realized by identical MOSFETs (Fig. 6.40) match to within 1, i.e., 0:99ID2 ID1 1:01ID2. If VDS1 = 0:5 V and VDS2 = 1 V, what is the maximum tolerable value of ? 22. Assume  = 0, compute W=L of M1 in Fig. 6.41 such that the device operates at the edge of saturation. 23. Using the value of W=L found in Problem 22, explain what happens if the gate oxide thick- ness is doubled due to a manufacturing error. 24. In the Fig. 6.42, what is the minimum allowable value of VDD if M1 must not enter the BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 315 (1) Sec. 6.7 Chapter Summary 315 Figure 6.40 I D1 I D2 M1 M2 VB VDD = 1.8 V RD 1 kΩ M1 1V Figure 6.41 VDD = 1.8 V R D 500 Ω M 1 W 10 = 1V L 0.18 Figure 6.42 triode region? Assume  = 0. 25. In Fig. 6.43, derive a relationship among the circuit parameters that guarantees M1 operates VDD RD M1 W L Figure 6.43 at the edge of saturation. Assume  = 0. 26. Compute the value of W=L for M1 in Fig. 6.44 for a bias current of I1. Assume  = 0. 27. Calculate the bias current of M1 in Fig. 6.45 if  = 0. 28. StokVetDchDI=X 1a:s8aVf.uAnclstioo,no=f V0X. for the circuits shown in Determine at what value Fig. 6.46. of VX the Assume VX goes device changes its from 0 region of operation. 29. Assuming W=L = 10=0:18  = 0:1 V,1, and VDD = 1:8 V, calculate the drain current of M1 in Fig. 6.47. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 316 (1) 316 Chap. 6 Physics of MOS Transistors Figure 6.44 VDD = 1.8 V M1 RS Figure 6.45 IX M1 1V VX 1V VDD RD M1 W L IX M1 VX IX M1 VX VDD = 1.8 V M1 IX VX (a) Figure 6.46 (b) (c) (d) VDD 1 kΩ RD M1 Figure 6.47 30. In the circuit of Fig. 6.48, W=L = 20=0:18 and  = 0:1 V,1. What value of VB places the transistor at the edge of saturation? VDD = 1.8 V RD 5 kΩ M1 VB Figure 6.48 31. An NMOS device operating in saturation with  = 0 must provide a transconductance of 1=50 . (a) (b) (c) Determine Determine Determine WIWD==iLLf ViiffGIVSDG,S=V,0T:VH5TmH=A=0.:50V:5. V. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 317 (1) Sec. 6.7 Chapter Summary 317 32. Determine how the transconductance of a MOSFET (operating in saturation) changes if (a) (b) WVG=SL,isVdToHubilseddobuubt lIeDd remains constant. but ID remains constant. (c) (d) IIDD is is doubled doubled but but W=L remains constant. VGS , VTH remains constant. 33. If  = 0:1 V,1 and W=L = 20=0:18, construct the small-signal model of each of the circuits shown in Fig. 6.49. VDD = 1.8 V R D 100 Ω VDD = 1.8 V RD 5 kΩ VDD = 1.8 V 1 mA M1 1V M1 M1 (a) (b) (c) VDD = 1.8 V M1 2 kΩ VDD = 1.8 V M1 0.5 mA (d) (e) Figure 6.49 34. The “intrinsic gain” of a MOSFET operating in saturation is defined as gmrO. Derive an expression for gmrO and plot the result as a function of ID. Assume VDS is constant. 35. A((abs))saaussmaainffuugnnaccttciiooonnnsootaffnVItDGVSDif,SV,GVpSTloH,t tihVfeTIiDHntirisisnccsooicnnssgttaaainnntt,.. gmrO, of a MOSFET 36. An NMOS device with  = 0:1 V,1 must provide a Determine the required value of W=L if ID = 0:5 mA. gmrO of 20 with VDS = 1:5 V. 37. Repeat Problem 36 for  = 0:2 V,1. 38. Construct the small-signal model of the circuits depicted in Fig. 6.50. Assume all transistors operate in saturation and  6= 0. 39. Determine the region of operation of M1 in each circuit shown in Fig. 6.51. 40. Determine the region of operation of M1 in each circuit shown in Fig. 6.52. 41. If  = 0, what value of W=L places M1 at the edge of saturation in Fig. 6.53? 42. With the value of W=L obtained in Problem 41, what happens if VB changes to +0:8 V? 43. If W=L = 10=0:18 and  = 0, determine the operating point of M1 in each circuit depicted in Fig. 6.54. 44. StokVetDchDI=X 1a:s8aVf.uAnclstioo,no=f V0X. for the circuits shown in Determine at what value Fig. 6.55. of VX the Assume VX goes device changes its from 0 region of operation. 45. Construct the small-signal model of each circuit shown in Fig. 6.56 if all of the transistors operate in saturation and  6= 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 318 (1) 318 Chap. 6 Physics of MOS Transistors VDD RD Vout M2 VB Vin M1 VDD RD Vout Vin M1 Vin M2 VDD RD Vout M1 M2 (a) Vin (b) VDD M1 Vout M2 VB (c) VDD RD M1 Vin M2 Vout (d) (e) Figure 6.50 M1 2V M1 0.3 V M1 1V M1 2V 0.3 V 0.3 V 0.6 V (a) (b) (c) (d) Figure 6.51 46. Cchoannsnideel-rlethnegtchirmcuoidt duelaptiicotnedcoinefFfiicgi.e6n.t5s7,nwahnedreMp,1raenspdeMcti2voelpye.rate in saturation and exhibit (a) Construct the small-signal equivalent circuit and explain why M1 and M2 appear in “parallel.” (b) Determine the small-signal voltage gain of the circuit. SPICE Problems In the following problems, use the MOS models and source/drain dimensions given in Ap- pendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD, respectively. 47. For the the circuit shown in sharp change in VX Fig. 6.58, plot as IX exceeds VX as a function a certain value. of IX for 0 IX 3 mA. Explain 48. Plot the input/output characteristic of the stage shown in Fig. 6.59 for 0 Vin 1:8 V. At what value of Vin does the slope (gain) reach a maximum? 49. For the arrangements shown in Fig. 6.60, plot ID as a function of VX as VX varies from 0 to 1.8 V. Can we say these two arrangements are equivalent? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 319 (1) Sec. 6.7 Chapter Summary 319 1.5 V M1 0.5 V M1 0.9 V 0.9 (a) (b) M1 M1 0.9 V 0.4 V 1V 0.4 V 0.9 V Figure 6.52 (c) 1V (d) VDD = 1.8 V M1 2 kΩ Figure 6.53 VDD = 1.8 V M1 500 Ω VDD = 1.8 V M1 1 kΩ VDD = 1.8 V 1 kΩ M1 Figure 6.54 (a) (b) (c) VDD = 1.8 V M1 VX IX (a) VDD = 1.8 V M1 IX VX VDD = 1.8 V M1 1V IX VX (b) IX M1 VX (c) (d) Figure 6.55 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 320 (1) 320 Chap. 6 Physics of MOS Transistors VDD RS Vin M1 Vout RD VDD Vin M1 Vout RD M2 Vin Vb M1 Vout R1 M2 RD (a) Vin R1 VDD M1 Vout RD M2 (b) Vin VDD R2 M1 R1 (c) Vout M2 Figure 6.56 Figure 6.57 (d) Vin (e) VDD M2 Vout M1 Figure 6.58 Figure 6.59 M1 0.9 V 2 0.18 VX IX VDD = 1.8 V 500 Ω M1 Vout Vin 10 0.18 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 321 (1) Sec. 6.7 Chapter Summary 321 IX IX M1 M1 5 VX 5 VX 0.9 V 0.36 0.9 V 0.36 M2 5 0.36 (a) (b) Figure 6.60 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 322 (1) 322 Chap. 6 Physics of MOS Transistors 50. Plot IX as a function of VX for the arrangement depicted in Fig. 6.61 as VX varies from 0 to 1.8 V. Can you explain the behavior of the circuit? IX M1 M1 5 5 VX 0.9 V 0.18 0.18 Figure 6.61 51. Repeat Problem 50 for the circuit illustrated in Fig. 6.62. VDD = 1.8 V M1 5 0.18 IX M1 5 VX 0.18 Figure 6.62 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 323 (1) 7 CMOS Amplifiers Most CMOS amplifiers have identical bipolar counterparts and can therefore be analyzed in the same fashion. Our study in this chapter parallels the developments in Chapter 5, identifying both similarities and differences between CMOS and bipolar circuit topologies. It is recommended that the reader review Chapter 5, specifically, Section 5.1. We assume the reader is familiar with concepts such as I/O impedances, biasing, and dc and small-signal analysis. The outline of the chapter is shown below. General Concepts Biasing of MOS Stages Realization of Current Sources MOS Amplifiers Common−Source Stage Common−Gate Stage Source Follower 7.1 General Considerations 7.1.1 MOS Amplifier Topologies Recall from Section 5.3 that the nine possible circuit topologies using a bipolar transistor in fact reduce to three useful configurations. The similarity of bipolar and MOS small-signal models (i.e., a voltage-controlled current source) suggests that the same must hold for MOS amplifiers. In other words, we expect three basic CMOS amplifiers: the “common-source” (CS) stage, the “common-gate” (CG) stage, and the “source follower.” 7.1.2 Biasing Depending on the application, MOS circuits may incorporate biasing techniques that are quite different from those described in Chapter 5 for bipolar stages. Most of these techniques are beyond the scope of this book and some methods are studied in Chapter 5. Nonetheless, it is still instructive to apply some of the biasing concepts of Chapter 5 to MOS stages. Consider the circuit assume M1 operates in shown in Fig. 7.1, saturation. Also, in where the gate voltage is defined by R1 and R2. We most bias calculations, we can neglect channel-length modulation. Noting that the gate current is zero, we have VX = R2 R1 + R2 VDD: (7.1) 323 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 324 (1) 324 Chap. 7 CMOS Amplifiers VDD = 1.8 V 4 kΩ R1 RD Y ID X M1 10 k Ω R2 R S 1 kΩ Figure 7.1 MOS stage with biasing. Since VX = VGS + IDRS, R2 R1 + R2 VDD = VGS + IDRS: (7.2) Also, ID = 1 2 nCox W L VGS , VT H 2: (7.3) Equations (7.2) and (7.3) can be solved to obtain ID and VGS, either by iteration or by finding ID from (7.2) and replacing for it in (7.3): R1 R2 + R2 VDD , VGS 1 RS = 12 n Cox W L VGS , VTH2: (7.4) That is VGS = = ,V1 ,V1 , , VT VT H H   + + r V1 s V12 , VTH2 , VT2H + 2V1 R2VDD R1 + R2 + 2R2 R1 + R2 , VTH ; V1VDD; (7.5) (7.6) where V1 = 1 nCox W L RS : (7.7) , This value of VGS can then be substituted in (7.2) to obtain ID. Of course, VY must exceed VX VT H to ensure operation in the saturation region. Example 7.1 DWe=teLrm=in5e=t0h:e18b,iaasndcurr=ent0o. fWMha1t in is Fig. 7.1 assuming VT H the maximum allowable = 0:5 V, nCox value of RD for = M1 100 A=V2, to remain in saturation? Solution We have VX = R2 R1 + R2 VDD (7.8) = 1:286 V: (7.9) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 325 (1) Sec. 7.1 General Considerations 325 vuut Wo2f8i6VthGmaSVna, isyniietiladlinggueasds rVaGinScu=rr1enVt ,otfh2e8v6oltaAg.eSdurbosptitauctrionsgs fRorSIcDaninbEe qe.x(p7r.e3s)sgedivaess VX the , VGS = new value VGS = VTH + 2ID nCox W L (7.10) = 0:954 V: (7.11) Consequently, ID = VX , VGS RS = 332 A; (7.12) (7.13) and hence VGS = 0:989 V: (7.14) This gives ID = 297 A. As seen from the iterations, the solutions converge more slowly than those encountered in Chapter 5 for bipolar circuits. This is due to the quadratic (rather than exponential) ID-VGS dependence. We may therefore utilize the exact result in (7.6) to avoid lengthy calculations. Since V1 = 0:36 V, VGS = 0:974 V (7.15) and ID = VX , VGS RS = 312 A: (7.16) (7.17) The maximum allowable value of RD is obtained if VY = VX , VTH = 0:786 V. That is, RD = VDD , ID VY = 3:25 k : (7.18) (7.19) Exercise What is the value of R2 that places M1 at the edge of saturation? Example 7.2 In (a) the the cmiracxuiimt oufmEaxllaomwpalbele7.v1a,luaessoufmWe =ML1 ainsdin(bs)atthueramtioinnimanudmRaDllow=ab2le:5vaklueaonfdRcSom(wpuitthe W=L = 5=0:18). Assume  = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 326 (1) 326 Chap. 7 CMOS Amplifiers Solution (aan)dAVsXW==L1:b2e8c6oVm, etshelamrgaexr,imMu1mcaalnlocwararbylea larger current value of ID is for a given given by VGS. With RD = 2:5 k ID = VDD , RD VY = 406 A: (7.20) (7.21) VT.hIenvootlhtaegrewdorrodps,aMcro1sms RusSt is then carry a ecquurraelntot o4f0460m6V,AyiwelidthinVgGVSGS==0:818:2V86: V , 0:406 V = 0:88 ID = 1 2 nCox W L VGS , VT H 2 (7.22) 406 A = 50 A=V2 W L 0:38 V2; (7.23) thus, W L = 56:2: (7.24) (b) With A. Since W=L = 5=0:18, the minimum allowable value of RS gives a drain current of 406 VGS = VT H + vuut 2ID nCox W L (7.25) = 1:041 V; (7.26) the voltage drop across RS is equal to VX , VGS = 245 mV. It follows that RS = VX , VGS ID = 604 : (7.27) (7.28) Exercise Repeat the above example if VTH = 0:35 V. The self-biasing technique of Fig. 5.22 can also be applied to MOS amplifiers. Depicted in Fig. 7.2, the circuit can be analyzed drop across RG is zero. Thus, by noting that M1 is in saturation (why?) and the voltage IDRD + VGS + RSID = VDD: (7.29) Finding VGS from this equation and substituting it in (7.3), we have ID = 1 2 nCox W L VDD , RS + RDID , VTH 2; (7.30) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 327 (1) Sec. 7.1 General Considerations 327 VDD RD RG ID M1 RS Figure 7.2 Self-biased MOS stage. where channel-length modulation is neglected. It follows that 2 3 RS + RD2ID2 , 2 64VDD , VT H RS + RD + 1 nCox W L 75 ID + VDD , VT H 2 = 0: (7.31) Example 7.3 Calculate the drain current of M1 in Fig. 7.3 if nCox = 100 A=V2, VTH = 0:5 V, and  = 0. What value of RD is necessary to reduce ID by a factor of two? RD 20 k Ω VDD= 1.8 V 1 kΩ = W5 M 1 L 0.18 200 Ω Figure 7.3 Example of self-biased MOS stage. Solution Equation (7.31) gives ID = 556 A: To reduce ID to 278 A, we solve (7.31) for RD: RD = 2:867 k : (7.32) (7.33) Exercise Repeat the above example if VDD drops to 1.2 V. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 328 (1) 328 Chap. 7 CMOS Amplifiers 7.1.3 Realization of Current Sources MOS transistors operating in saturation can act as current sources. As illustrated in Fig. 7.4(a), an NMOS device serves as a current source with one terminal tied to ground, i.e., it draws current from node X to ground. On the other hand, a PMOS transistor [Fig. 7.4(b)] draws current from VDD to node Y . If  = 0, these currents remain independent of VX or VY (so long as the transistors are in saturation). X X Vb M1 VDD Vb M2 VDD Vb Y Vb M1 VDD M1 Y Y X (a) (b) (c) (d) Figure 7.4 (a) NMOS device operating as a current source, (b) PMOS device operating as a current source, (c) PMOS topology not operating as a current source, (d) NMOS topology not operating as a current source. It is important to understand that only the drain terminal of a MOSFET can draw a dc current and still present a high impedance. Specifically, NMOS or PMOS devices configured as shown in Figs. 7.4(c) and (d) do not operate as current sources because variation of VX or VY directly changes the gate-source voltage of each transistor, thus changing the drain current considerably. From another perspective, the small-signal model of these two structures is identical to that of the diode-connected devices  = 0) rather than infinity. in Fig. 6.34, revealing a small-signal impedance of only 1=gm (if 7.2 Common-Source Stage 7.2.1 CS Core Shown in Fig. 7.5(a), the basic CS stage is similar to the common-emitter topology, with the input applied voltage to the gate and the output variations to proportional sensed at the drain current cdhraainng.eFso, ransmd aRllDsitgrannaslsf,oMrm1s converts the input the drain currents to the output voltage. If channel-length modulation is neglected, the small-signal model in Fig. 7.5(b) yields vin = v1 and vout = ,gmv1RD. That is, VDD RD ID Vout Vin Output Sensed M1 at Drain Input Applied to Gate (a) v in v1 g v m 1 v out RD (b) Figure 7.5 (a) Common-source stage, (b) small-signal mode. vout vin = ,gmRD; a result similar to that obtained for the common emitter stage in Chapter 5. (7.34) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 329 (1) Sec. 7.2 Common-Source Stage 329 p The voltage gain of the CS 2nCoxW=LID, we have stage is also limited by the supply voltage. Since gm = Av = r , 2nCox W L IDRD; (7.35) concluding that if ID or RD is increased, so is the voltage drop across RD (= IDRD).1 For M1 to remain in saturation, VDD , RDID VGS , VTH; (7.36) that is, RDID VDD , VGS , VTH: (7.37) Example 7.4 Calculate the small-signal voltage gain of the CS stage shown in Fig. 7.6 if ID = 1 mA, nCox = 100 A=V2, VTH = 0:5 V, and  = 0. Verify that M1 operates in saturation. VDD = 1.8 V RD 1 kΩ v out v in M 1 W 10 = L 0.18 Figure 7.6 Example of CS stage. Solution We have Thus, gm = r 2nCox W L ID = 1 300 : Av = ,gmRD = 3:33: (7.38) (7.39) (7.40) (7.41) To check the operation region, we first determine the gate-source voltage: VGS = VTH + vuutnC2IoDx WL = 1:1 V: (7.42) (7.43) W 1It is possible to raise the gain to some extent by increasing , but “subthreshold conduction” eventually limits the transconductance. This concept is beyond the scope of this book. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 330 (1) 330 Chap. 7 CMOS Amplifiers The drain voltage is equal to VDD , RDID = 0:8 V. Since VGS , VTH = 0:6 V, the device indeed operates in saturation and has a margin of 0.2 V with respect to the triode region. For example, if RD is doubled with the intention of doubling Av, then M1 enters the triode region and its transconductance drops. Exercise What value of VT H places M1 at the edge of saturation? Since the gate terminal of MOSFETs draws a zero current (at very low frequencies), we say the CS amplifier provides a current gain of infinity. By contrast, the current gain of a commonemitter stage is equal to . Let us now compute the I/O impedances of the CS amplifier. Since the gate current is zero (at low frequencies), Rin = 1; (7.44) a point of contrast to the CE stage (whose Rin is equal to r). The high input impedance of the CS topology plays a critical role in many analog circuits. The similarity between the small-signal equivalents of CE and CS stages indicates that the output impedance of the CS amplifier is simply equal to Rout = RD: (7.45) This is also seen from Fig. 7.7. iX v1 gmv 1 RD vX Figure 7.7 Output impedance of CS stage. In practice, channel-length modulation may not be negligible, especially if RD is large. The small-signal model of CS topology is therefore modified as shown in Fig. 7.8, revealing that iX v1 gv m 1 rO RD vX Figure 7.8 Effect of channel-length modulation on CS stage. Av = ,gmRDjjrO (7.46) Rin = 1 (7.47) Rout = RDjjrO: (7.48) In other words, channel-length modulation and the Early effect impact the CS and CE stages, respectively, in a similar manner. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 331 (1) Sec. 7.2 Common-Source Stage 331 Example 7.5 Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. 7.9(a) and plot the result as a function of the transistor channel length while other parameters remain constant. VDD Av v out v in M1 L (a) (b) Figure 7.9 (a) CS stage with ideal current source as a load, (b) gain as a function of device channel length. Solution The ideal current source presents an infinite small-signal resistance, allowing the use of (7.46) with RD = 1: Av = ,gmrO: (7.49) pThis is the highest 2nCoxW=LID voltage and rO = gaiInD t,ha1t, a we single have transistor can provide. Writing gm = jAvj = r 2pnCIDox W L : (7.50) j j This result may imply that Av falls as L increases, but recall from Chapter 6 that  jAvj r 2nCoxW ID L : L,1: (7.51) Consequently, jAvj increases with L [Fig. 7.9(b)]. Exercise Repeat M1. the above example if a resistor of value R1 is tied between the gate and drain of 7.2.2 CS stage With Current-Source Load As seen in the above example, the trade-off between the voltage gain and the voltage headroom can be relaxed by replacing the load resistor with a current source. The observations made in relation to Fig. 7.4(b) therefore suggest the use of a PMOS device as the load of an NMOS CS amplifier [Fig. 7.10(a)]. Let us determine the small-signal gain and output impedance of the circuit. Having a constant gate-source voltage, M2 simply behaves as a resistor equal to its output impedance [Fig. 7.10(b)] BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 332 (1) 332 Chap. 7 CMOS Amplifiers VDD VDD Vb M2 v1 gm2v 1 r O2 v out v in M1 (a) v in M1 (b) v out r O1 Figure 7.10 (a) CS stage using a PMOS device as a current source, (b) small-signal model. because v1 = 0 and hence gm2v1 = 0. Thus, the drain node of M1 sees both rO1 and rO2 to ac ground. Equations (7.46) and (7.48) give Av = ,gm1rO1jjrO2 Rout = rO1jjrO2: (7.52) (7.53) Example 7.6 Figure 7.11 shows a PMOS CS stage using an NMOS current source load. Compute the voltage gain of the circuit. VDD v in M2 v out Vb M1 Figure 7.11 CS stage using an NMOS device as current source. Solution Transistor rO1jjrO2, pMro2dugceinngervaotuest a = small-signal current ,gm2vinrO1jjrO2. equal Thus, to gm2vin, which then flows through Av = ,gm2rO1jjrO2: (7.54) Exercise Calculate the gain if the circuit drives a loads resistance equal to RL. 7.2.3 CS stage With Diode-Connected Load In some applications, we may use a diode-connected MOSFET as the drain load. Illustrated in Fig. 7.12(a), such a topology exhibits only a moderate gain due to the relatively low impedance of the diode-connected device (Section 7.1.3). With  = 0, M2 acts as a small-signal resistance equal to 1=gm2, and (7.34) yields BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 333 (1) Sec. 7.2 Common-Source Stage 333 VDD M2 Vout Vin M1 VCC Q2 Vout Vin Q1 1 g m2 v in M1 r O2 v out r O1 (a) (b) (c) Figure 7.12 (a) MOS stage using a diode-connected load, (b) bipolar counterpart, (c) simplified circuit of (a). Av = = ,,sgppm221 nngCCm1oo2xx WW==LL12 IIDD (7.55) (7.56) =, W=L1 W=L2 : (7.57) Interestingly, the gain process parameters n is given and Cox by the dimensions of and the drain current, IMD1. and M2 and remains independent of The reader may wonder why we did not consider a common-emitter stage with a diode- connected load in Chapter 5. Shown in Fig. 7.12(b), such a circuit is not used because it provides a voltage gain of only unity: Av = ,gm1  1 gm2 = , IC1 VT  1 IC2=VT  ,1: (7.58) (7.59) (7.60) The contrast between (7.57) and (7.60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not. A more accurate expression for the gain of the stage in Fig. 7.12(a) must take channel-length modulation into account. As depicted in Fig. 7.12(c), the resistance seen at the drain is now equal to 1=gm2jjrO2jjrO1, and hence Av = ,gm1 1 gm2 jjrO2jjrO1 : (7.61) Similarly, the output resistance of the stage is given by Rout = 1 gm2 jjrO2jjrO1: (7.62) Example 7.7 6 Determine the voltage gain of the circuit shown in Fig. 7.13(a) if  = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 334 (1) 334 Chap. 7 CMOS Amplifiers VDD Vin M2 Vout M1 Figure 7.13 CS stage with diode-connected PMOS device. Solution This stage is similar to that in Fig. 7.12(a), but with NMOS devices changed to PMOS transistors: M1 serves as a common-source device and M2 as a diode-connected load. Thus, Av = ,gm2 1 gm1 jjrO1jjrO2 : (7.63) Exercise Repeat the above example if the gate of M1 is tied to a constant voltage equal to 0.5 V. 7.2.4 CS Stage With Degeneration Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain, I/O impedances, and linearity. We expect similar results for a degenerated CS amplifier. Figure 7.14 depicts the stage along with its small-signal equivalent (if  = 0). As with the bipolar counterpart, the degeneration resistor sustains a fraction of the input voltage change. From Fig. 7.14(b), we have VDD RD Vout Vin M1 RS v in v1 gmv 1 v out RD RS (a) (b) Figure 7.14 (a) CS stage with degeneration, (b) small-signal model. and hence vin = v1 + gmv1RS v1 = 1 vin + gmRS : (7.64) (7.65) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 335 (1) Sec. 7.2 Common-Source Stage Since gmv1 flows through RD, vout = ,gmv1RD and vout vin = , 1 gmRD + gmRS = , RD 1 gm + RS ; a result identical to that expressed by (5.157) for the bipolar counterpart. Example 7.8 Compute the voltage gain of the circuit shown in Fig. 7.15(a) if  = 0. VDD RD Vout Vin M1 M2 RD v out v in M1 1 g m2 335 (7.66) (7.67) (a) (b) Figure 7.15 (a) Example of CS stage with degeneration, (b) simplified circuit. Solution 7T.r1a5n(sbis)t]o. rThMe2gasienrvisesthaesreafodreiogdiev-ecnobnyne(c7t.e6d7)diefvRicSe,isprreepselanctiendgwainthi1m=pgemd2a:nce of 1=gm2 [Fig. Av = , RD 1 gm1 + 1 gm2 : (7.68) Exercise What happens if  6= 0 for M2? In parallel with the developments in Chapter 5, we may study the effect of a resistor appearing in series with the gate (Fig. 7.16). However, since the gate current is zero (at low frequencies), RG sustains no voltage drop and does not affect the voltage gain or the I/O impedances. Effect of Transistor Output Impedance As with the bipolar counterparts, the inclusion of the transistor output impedance complicates the analysis and is studied in Problem 31. Nonethe- less, the output impedance of the degenerated CS stage plays a critical role in analog design and is worth studying here. to iX iF,Xigg(umwreh,7y.?i1)X7, RwshSeohw=asvteihXev1+sm=gaml,l-isXiiXgRnRSaSl. .AeqAdudlisviona,gletthnheteocvfuotrlhrteeangcteirtdhcrurooitpu.sgShaicnrrcOoesRsisrSeOqcuaanrarldietRos SaiXcaun,rdreegnqmtuevaq1tiun=agl the result to vX , we have BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 336 (1) 336 Chap. 7 CMOS Amplifiers RG Vin VDD RD Vout M1 RS Figure 7.16 CS stage with gate resistance. v1 iX gmv 1 r O vX RS Figure 7.17 Output impedance of CS stage with degeneration. rOiX + gmiXRS + iXRS = vX; (7.69) and hence vX iX = rO1 + gmRS + RS = 1 + gmrORS + rO  gmrORS + rO: (7.70) (7.71) (7.72) Alternatively, we observe that the model in Fig. 7.17 is similar to its bipolar counterpart in Fig. 5.46(a) but with r = 1. Letting r ! 1 in Eqs. (5.196) and (5.197) yields the same results as above. As expected from our study of the bipolar degenerated stage, the MOS version also exhibits a “boosted” output impedance. Example 7.9 Compute the output resistance of the circuit in Fig. 7.18(a) if M1 and M2 are identical. R out R out Vb M1 M2 r O1 M1 1 g m2 r O2 (a) (b) Figure 7.18 (a) Example of CS stage with degeneration, (b) simplified circuit. Solution The diode-connected device M2 can be represented by a small-signal resistance of BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 337 (1) Sec. 7.2 Common-Source Stage 337 1=gm2jjrO2  1=gm2. Transistor M1 is degenerated by this resistance, and from (7.70): Rout = rO1 1 + gm1 1 gm2 + 1 gm2 (7.73) which, since gm1 = gm2 = gm, reduces to Rout = 2rO1 + 1 gm  2rO1: (7.74) (7.75) Exercise Do the results remain unchanged if M2 is replaced with a diode-connected PMOS de- vice? Example 7.10 Determine the output resistance of the circuit in Fig. 7.19(a) and compare the result with that in the above example. Assume M1 and M2 are in saturation. R out R out Vb2 M1 Vb1 M2 r O1 M1 r O2 (a) (b) Figure 7.19 (a) Example of CS stage with degeneration, (b) simplified circuit. Solution With its sistance gate-source of rO2 from vthoeltasoguerficexeodf,Mtra1ntsoisgtororuMnd2 operates as a current [Fig. 7.19(b)]. source, introducing a re- Equation (7.71) can therefore be written as Rout = 1 + gm1rO1rO2 + rO1  gm1rO1rO2 + rO1: (7.76) (7.77) Assuming gm1rO2 1 (which is valid in practice), we have Rout  gm1rO1rO2: (7.78) We observe that this value is quite higher than that in (7.75). BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 338 (1) 338 Chap. 7 CMOS Amplifiers Exercise Repeat the above example for the PMOS counterpart of the circuit. 7.2.5 CS Core With Biasing The effect of the simple biasing network shown in Fig. 7.1 is similar to that analyzed for the bipo- lar stage in Chapter 5. Depicted in Fig. 7.20(a) along with an input coupling capacitor (assumed a short circuit), such a circuit no longer exhibits an infinite input impedance: VDD VDD VDD R1 C1 Vin R2 RD Vout M1 Vin RS R1 RG C1 R2 RD Vout M1 Vin RS R1 RG C1 R2 R in RD Vout M1 RS C2 (a) (b) (c) Figure 7.20 (a) CS stage with input coupling capacitor, (b) inclusion of gate resistance, (c) use of bypass capacitor. Rin = R1jjR2: (7.79) Thus, if the circuit is driven by a finite source impedance [Fig. 7.20(b)], the voltage gain falls to Av = R1jjR2 RG + R1jjR2  ,RD 1 gm + RS ; (7.80) where  is assumed to be zero. As mentioned in Chapter 5, it is possible to utilize degeneration for bias point stability but eliminate its effect on the small-signal performance by means of a bypass capacitor [Fig. 7.20(c)]. Unlike the case of bipolar realization, this does not alter the input impedance of the CS stage: Rin = R1jjR2; (7.81) but raises the voltage gain: Av = , R1jjR2 RG + R1jjR2 gmRD : (7.82) Example 7.11 Design the CS stage of Fig. 7.20(c) for a voltage gain of 5, an input impedance of 50 k , and a power budget of 5 mW. Assume nCox = 100 A=V2, VTH = 0:5 V,  = 0, and VDD = 1:8 V. Also, assume a voltage drop of 400 mV across RS. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 339 (1) Sec. 7.2 Common-Source Stage 339 Solution The power budget along with VDD = 1:8 V implies a maximum supply current of 2.78 mA. As an initial guess, we allocate 2.7 mA to M1 and the remaining 80 A to R1 and R2. It follows that RS = 148 : (7.83) As with typical design problems, the choice of gm and RD is somewhat flexible so long as gmRD = 5. However, with ID known, we must ensure a reasonable value for VGS, e.g., VGS = 1 V. This choice yields gm = 2ID VGS , VTH = 1 92:6 ; (7.84) (7.85) and hence RD = 463 : (7.86) Writing ID = 1 2 nCox W L VGS , VT H 2 (7.87) gives W L = 216: (7.88) With VGS = 1 V and a 400-mV drop across RS, the gate voltage reaches 1.4 V, requiring that R2 R1 + R2 VDD = 1:4 V; (7.89) which, along with Rin = R1jjR2 = 50 k , yields, R1 = 64:3 k R2 = 225 k : (7.90) (7.91) We must now check given by VDD , IDRD to = verify 1:8 V ,tha1t:2M5 1Vin=de0e:d55oVpe.rSatiensceinthseatguartaetivoonl.taTgheeisdreaqiunalvotolta1g.4e is V, the gate-drain voltage difference exceeds VT H How did our design procedure lead to this ,rdesriuvlitn?gFMor1thinetogitvheentrIiDod, ewreeghiaovne! chosen an ex- cessively large reasonable. We RD, i.e., an excessively must therefore increase small gm so gm (because as to allow a glomwReDr v=alue5)f,oervRenDt.hFoourghexVamGSpleis, suppose we halve RD and double gm by increasing W=L by a factor of four: W L = 864 gm = 1 46:3 : (7.92) (7.93) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 340 (1) 340 Chap. 7 CMOS Amplifiers The corresponding gate-source voltage is obtained from (7.84): VGS = 250 mV; (7.94) yielding a gate voltage of 650 mV. thaInstMhe1gaintesvaotultraagtieomn?inTuhseVdTrHai.nTvhoulsta,gMe 1isoepqeuraatletsoinVDsaDtur,atiRonD.ID = 1:17 V, a value higher Exercise Repeat the above example for a power budget of 3 mW and VDD = 1:2 V. 7.3 Common-Gate Stage Shown in Fig. 7.21, the CG topology resembles the common-base stage studied in Chapter 5. Here, if the input rises by a small value, V , then the gate-source voltage of M1 decreases by the same amount, thereby lowering the drain current by gmV and raising Vout by gmV RD. That is, the voltage gain is positive and equal to VDD RD Vout M1 Vb Vin Input Applied to Source Figure 7.21 Common-gate stage. Output Sensed at Drain Av = gmRD: (7.95) The CG stage suffers from voltage headroom-gain trade-offs similar to those of the CB topol- ogy. In VDD , particular, to IDRD, must raecmhiaeivneaabohvigehVbga,inV, TaHhitgoheInDsuorer MRD1 is necessary, is saturated. but the drain voltage, Example 7.12 A microphone having a dc level of zero drives a CG stage nCox = 100 A=V2, VTH = 0:5 V, and VDD = 1:8 biased at ID = 0:5 mA. If W=L = 50, V, determine the maximum allowable value of RD and hence the maximum voltage gain. Neglect channel-length modulation. Solution With W=L known, the gate-source voltage can be determined from ID = 1 2 nCox W L VGS , VT H 2 (7.96) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 341 (1) Sec. 7.3 Common-Gate Stage 341 as VGS = 0:947 V: For M1 to remain in saturation, VDD , IDRD Vb , VTH (7.97) (7.98) and hence RD 2:71 k : Also, the above value of W=L and ID yield gm = 447 ,1 and Av  6:06: (7.99) (7.100) Figure 7.22 summarizes the allowable signal levels in this design. The gate voltage can be generated using a resistive divider similar to that in Fig. 7.20(a). VDD − Vb VTH = 0.447 V 0 RD Vout M1 Vin Vb = 0.947 V Figure 7.22 Signal levels in CG stage. Exercise If a gain of 10 is required, what value should be chosen for W=L? We now compute the I/O impedances of the CG stage, expecting to obtain results similar to those of the CB topology. Neglecting channel-length modulation for now, we have from Fig. 7.23(a) v1 = ,vX and iX v1 gmv 1 RD v1 gmv 1 RD vX vX iX (a) (b) Figure 7.23 (a) Input and (b) output impedances of CG stage. iX = ,gmv1 = gmvX: (7.101) (7.102) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 342 (1) 342 Chap. 7 CMOS Amplifiers That is, Rin = 1 gm ; a relatively low value. Also, from Fig. 7.23(b), v1 = 0 and hence Rout = RD; (7.103) (7.104) an expected result because the circuits of Figs. 7.23(b) and 7.7 are identical. Let us study the behavior of the CG stage in the presence of a finite source impedance (Fig. 7.24) but still with  = 0. In a manner similar to that depicted in Chapter 5 for the CB topology, we write VDD RD Vout RS M 1 Vb X v in 1 gm RS vX v in 1 gm Figure 7.24 Simplification of CG stage with signal source resistance. 1 vX = 1 gm gm + RS vin = 1 + 1 gmRS vin: (7.105) (7.106) Thus, vout vin = vout vX  vX vin = 1 gmRD + gmRS = RD 1 gm + RS : (7.107) (7.108) (7.109) The gain is therefore equal to that of the degenerated CS stage except for a negative sign. In contrast to the common-source stage, the CG amplifier exhibits a current gain of unity: the current provided by the input voltage source simply flows through the channel and emerges from the drain node. The analysis of the common-gate stage in the general case, i.e., including both channel-length modulation and a finite source impedance is beyond the scope of this book (Problem 41). However, we can make two observations. First, a resistance appearing in series with the gate terminal [Fig. 7.25(a)] does not alter the gain or I/O impedances (at low frequencies) because it sustains BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 343 (1) Sec. 7.3 Common-Gate Stage 343 VDD RD Vout M1 Vb RG v in R out RS rO M1 (a) (b) Figure 7.25 (a) CG stage with gate resistance, (b) output resistance of CG stage. a zero potential drop—as if its value were zero. Second, the output resistance of the CG stage in the general case [Fig. 7.25(b)] is identical to that of the degenerated CS topology: Rout = 1 + gmrORS + rO: (7.110) Example 7.13 For the circuit shown in Fig. 7.26(a), calculate the voltage gain if  = 0 and the output impedance if  0. VDD RD Vout RS M 1 Vb X Vin M2 1 g m1 RS vX v in 1 g m2 R out1 RS r O1 M1 1 g m2 r O2 (a) (b) (c) Figure 7.26 (a) Example of CG stage, (b) equivalent input network, (c) calculation of output resistance. Solution We first compute vX =vin with the aid of the equivalent circuit depicted in Fig. 7.26(b): vX vin = gm1 2gjm1j g2m1jj1gm1+1 RS = 1 + gm1 1 + gm2RS : (7.111) (7.112) Noting that vout=vX = gm1RD, we have vout vin = 1 + gm1RD gm1 + gm2RS : (7.113) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 344 (1) 344 Chap. 7 CMOS Amplifiers To compute the output impedance, we first consider Rout1, as shown in Fig. 7.26(c), which from (7.110) is equal to Rout1 = 1 + gm1rO1 1 gm2 jjrO2jjRS  + rO1  gm1rO1 1 gm2 jjRS  + rO1 : (7.114) (7.115) The overall output impedance is then given by Rout = Rout1jjRD  gm1rO1 1 gm2 jjRS  + rO1 jjRD: (7.116) (7.117) Exercise Calculate the output impedance if the gate of M2 is tied to a constant voltage. 7.3.1 CG Stage With Biasing Following our study of the CB biasing in Chapter 5, we surmise the CG amplifier can be biased as shown in Fig. 7.27. Providing a path for the bias current to ground, resistor R3 lowers the input impedance—and hence the voltage gain—if the signal source exhibits a finite output impedance, RS. VDD RD R1 Vout RS Vin M1 X R2 C1 R3 Figure 7.27 CG stage with biasing. Since the impedance seen to the right of node X is equal to R3jj1=gm, we have vout vin = vX vin  vout vX = R3jj1=gm R3jj1=gm + RS  gmRD; (7.118) (7.119) where channel-length modulation is neglected. As mentioned earlier, the voltage divider consist- ing of R1 and R2 does not affect the small-signal behavior of the circuit (at low frequencies). Example 7.14 Design the common-gate stage of Fig. 7.27 for the following parameters: vout=vin = 5, BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 345 (1) Sec. 7.3 Common-Gate Stage 345 RnSCo=x 0, = R3 100 = 500 A=V2, , VT H1==gm0:5=V5, 0and , power  = 0. budget = 2 mW, VDD = 1:8 V. Assume Solution From the power budget, we obtain a total supply current of 1.11 mA. Allocating 10 A to the vacorlotasgseRd3iviisdeeqr,uRal1toan5d5R0 2m,Vw.e We must now compute two leave 1.1 mA for the drain current of M1. Thus, the voltage drop interrelated parameters: W=L and RD. A larger value of W=L yields value W=L f=aorgr2Ve4Ga4tSe, ratongmdar,gramivlleo=watin2agIrDaea=lsooVwnGeaSrblv,ealguVueTeHsosffRo=rDW.A1=3sL6i.:n4FEoxra,emx1ap,mldepic7lte.a1,t1iinf, gwVGRe SDch=o=os0e6:88an2V,intihtfieoanrl vout=vin = 5. Let us determine whether M1 operates in saturation. The gate voltage is equal to VGS plus the , , dIDroRpDac=ros1s:0R53V, .aSmionucenttihnegdtroai1n.3v5olVta.gOenexthceeeodtsheVrGhanVd,TtHhe, drain M1 is voltage is indeed in given by VDD saturation. The resistive divider while drawing 10 A: consisting of R1 and R2 must establish a gate voltage equal to 1.35 V VDD R1 + R2 = 10 A R2 R1 + R2 VDD = 1:35 V: (7.120) (7.121) It follows that R1 = 45 k and R2 = 135 k . Exercise If W=L cannot exceed 100, what voltage gain can be achieved? Example 7.15 Suppose in Example 7.14, we wish to minimize W=L (and hence transistor capacitances). What is the minimum acceptable value of W=L? Solution For a given ID, as W=L decreases, VGS , VT H increases. Thus, we must first compute the maximum allowable VGS. We impose the condition for saturation as VDD , IDRD VGS + VR3 , VTH; (7.122) where VR3 denotes the voltage drop across R3, and set gmRD to the required gain: 2ID VGS , VT H RD = Av : Eliminating RD from (7.122) and (7.123) gives: VDD , Av 2 VGS , VT H  VGS , VTH + VR3 (7.123) (7.124) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 346 (1) 346 and hence In other words, It follows that Chap. 7 CMOS Amplifiers VGS , VTH VDD Av 2 , VR3 +1 : W=L nCox 2 2ID VDD Av , VR3 +2 2 : (7.125) (7.126) W=L 172:5: (7.127) Exercise Repeat the above example for Av = 10. 7.4 Source Follower The MOS counterpart of the emitter follower is called the “source follower” (or the “common- drain” stage) and shown in Fig. 7.28. The amplifier senses the input at the gate and produces the output at the source, with the drain tied to VDD. The circuit’s behavior is similar to that of the bipolar counterpart. VDD Vin M1 Input Applied to Gate Vout RL Output Sensed at Source Figure 7.28 Source follower. 7.4.1 Source Follower Core If the tends gate voltage to increase, of M1 in Fig. 7.28 is raised by a small amount, Vin, the thereby raising the source current and hence the output gate-source voltage voltage. Thus, Vout “follows” Vin. Since the dc level of Vout is lower than that of Vin by VGS, we say the follower can serve as a “level shift” circuit. From our analysis of emitter followers in Chapter 5, we expect this topology to exhibit a subunity gain, too. Figure 7.29(a) depicts the small-signal equivalent of the source follower, including channel- length modulation. Recognizing that rO appears in parallel with RL, we have gmv1rOjjRL = vout: (7.128) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 347 (1) Sec. 7.4 Source Follower 347 v in v1 g v m 1 rO v out RL 1 gm v out v in RL rO (a) (b) Figure 7.29 (a) Small-signal equivalent of source follower, (b) simplified circuit. Also, vin = v1 + vout: (7.129) It follows that vout vin = gmrOjjRL 1 + gmrOjjRL = rOjjRL 1 gm + rOjjRL : (7.130) (7.131) The voltage gain is therefore positive and less than unity. It is desirable to maximize RL (and rO ). As with emitter followers, we can view the above result as voltage division between a resis- tance equal to 1=gm and another equal to rOjjRL [Fig. 7.29(b)]. Note, however, that a resistance placed in series with the gate does not affect (7.131) (at low frequencies) because it sustains a zero drop. Example 7.16 A source follower is realized as shown in Fig. 7.30(a), where M2 serves as a current source. Calculate the voltage gain of the circuit. VDD Vin M1 Vout Vb M2 Vin M1 r O1 Vout r O2 (a) (b) Figure 7.30 (a) Follower with ideal current source, (b) simplified circuit. Solution SwiencseubMst2itusitme RplLy presents an impedance = rO2 in Eq. (7.131): of rO2 from the output node to ac ground [Fig. 7.30(b)], Av = rO1jjrO2 1 gm1 + rO1jjrO2 : (7.132) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 348 (1) 348 If rO1jjrO2 1=gm1, then Av  1. Chap. 7 CMOS Amplifiers Exercise Repeat M2. the above example if a resistance of value RS is placed in series with the source of Example 7.17 Design a source follower to drive a 50- load with a voltage gain of 0.5 and a power budget of 10 mW. Assume nCox = 100 A=V2, VTH = 0:5 V,  = 0, and VDD = 1:8 V. Solution With RL = 50 and rO = 1 in Fig. 7.28, we have Av = RL 1 gm + RL (7.133) and hence gm = 1 50 : (7.134) p The power budget and supply voltage yield a maximum supply current of 5.56 mA. Using this value for ID in gm = 2nCoxW=LID gives W=L = 360: (7.135) Exercise What voltage gain can be achieved if the power budget is raised to 15 mW? It is instructive to compute the output impedance of the source follower.2 As illustrated in Fig. 7.31, Rout consists of looking down into RL. the resistance seen looking up into the source With  6= 0, the former is equal to 1=gmjjrO in parallel , yielding with that seen Rout = 1 gm jjrOjjRL  1 gm jjRL: (7.136) (7.137) In summary, the source follower exhibits a very high input impedance and a relatively low output impedance, thereby providing buffering capability. 2The input impedance is infinite at low frequencies. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 349 (1) Sec. 7.4 Source Follower 349 rO M1 RL R out Figure 7.31 Output resistance of source follower. rO M1 1 gm rO RL 7.4.2 Source Follower With Biasing The biasing of source followers is similar to that of emitter followers (Chapter 5). Figure 7.32 advnoedpltiaRcgtSsesasanertseextehaqemudaprlla.eiAnwlbshoiea,rsethcReurGirnepenust.ttaNibmoliptseehdtehasanatcMedco1fvotophleetarcagiterecseuqiintuhsaalatstuodrarVtoiDpoDpnebdaetfctrahouemsegiatnhtfieenogiftaytMetoa1nR(dwGdh.ryai?n) C1 RG Vin VDD M1 C2 RS Vout Figure 7.32 Source follower with input and output coupling capacitors. Let us compute the bias current of the circuit. With a zero voltage drop across RG, we have VGS + IDRS = VDD: (7.138) Neglecting channel-length modulation, we write ID = 1 2 nCox W L VGS , VT H 2 = 1 2 nCox W L VDD , IDRS , VT H 2 : The resulting quadratic equation can be solved to obtain ID. (7.139) (7.140) Example 7.18 Design the source follower of Fig. 7.32 for a drain current of 1 mA and a voltage gain of 0.8. Assume nCox = 100 A=V2, VTH = 0:5 V,  = 0, VDD = 1:8 V, and RG = 50 k . Solution The unknowns in this problem are VGS, W=L, and RS. The following three equations can be formed: ID = 1 2 nCox W L VGS , VT H 2 IDRS + VGS = VDD (7.141) (7.142) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 350 (1) 350 Chap. 7 CMOS Amplifiers Av = RS 1 gm + RS : (7.143) If gm is written as 2ID=VGS , VTH, then (7.142) and (7.143) do not contain W=L and can be solved to determine VGS and RS. With the aid of (7.142), we write (7.143) as Av = VGS , RS VT H 2ID + RS = VGS , 2IDRS VTH + 2IDRS = VDD 2IDRS , VTH + IDRS : (7.144) (7.145) (7.146) Thus, RS = VDD , ID VT H 2 Av , Av = 867 : (7.147) (7.148) and VGS = VDD , IDRS = VDD , VDD , VT H  2 Av , Av = 0:933 V: (7.149) (7.150) (7.151) It follows from (7.141) that W L = 107: (7.152) Exercise What voltage gain can be achieved if W=L cannot exceed 50? Equation (7.140) reveals that the bias current of the source follower varies with the supply voltage. To avoid this effect, integrated circuits bias the follower by means of a current source (Fig. 7.33). 7.5 Summary and Additional Examples In this chapter, we have studied three basic CMOS building blocks, namely, the common-source stage, the common-gate stage, and the source follower. As observed throughout the chapter, the small-signal behavior of these circuits is quite similar to that of their bipolar counterparts, with the exception of the high impedance seen at the gate terminal. We have noted that the biasing BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 351 (1) Sec. 7.5 Summary and Additional Examples 351 C1 RG Vin VDD M1 C2 Vout C1 RG Vin Vb VDD M1 C2 M2 Vout Figure 7.33 Source follower with biasing. schemes are also similar, IC-VBE characteristic. with the quadratic ID-VGS relationship supplanting the exponential In this section, we consider a number of additional examples to solidify the concepts intro- duced in this chapter, emphasizing analysis by inspection. Example 7.19 Calculate the voltage gain and output impedance of the circuit shown in Fig. 7.34(a). VDD Vin M1 Vout Vb M2 M3 v in M1 r O2 r O1 v out 1 g m3 r O3 (a) (b) Figure 7.34 (a) Example of CS stage, (b) simplified circuit. Solution jj aWthseeaoidcueutpnrruteitfnyattMsiots1urdacrseaaiancn.odTmrtahmneoslinas-ttosteorrsuarMcse2adadenviodicdMee-b3ceotcnhaneureseceftoeitrdesdeaencvsteiacsset.thhTeehilnuopsa,udMt, aw2t iitcthsangthabeteefoarernmpdleagrceesndeerrwvaitinethgs a small-signal resistance equal to rO2, and M3 with another equal to 1=gm3 rO3. The circuit now reduces to that depicted in Fig. 7.34(b), yielding Av = ,gm1 1 gm3 jjrO1 jjrO2jjrO3 (7.153) and Rout = 1 gm3 jjrO1jjrO2jjrO3: Note that 1=gm3 is dominant in both expressions. (7.154) Exercise Repeat the above example if M2 is converted to a diode-connected device. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 352 (1) 352 Chap. 7 CMOS Amplifiers Example 7.20 Compute the voltage gain of the circuit shown in Fig. 7.35(a). Neglect channel-length modulation in M1. VDD M3 1 g m3 r O3 Vin M1 Vout Vin M1 Vout Vb M2 r O2 (a) (b) Figure 7.35 (a) Example of CS stage, (b) simplified circuit. Solution Operating as a CS stage the current-source load, and degenerated by the diode-connected M2. Simplifying the amplifier to that in device M3, transistor M1 Fig. 7.35(b), we have drives Av = , 1 gm1 rO2 + 1 gm3 jjrO3 : (7.155) Exercise Repeat the above example if the gate of M3 is tied to a constant voltage. Example 7.21 Determine the voltage gain of the amplifiers illustrated in Fig. 7.36. For simplicity, assume rO1 = 1 in Fig. 7.36(b). VDD VDD Vin M2 Vb2 M2 Vout Vout Vb M1 Vb1 M1 RS (a) Figure 7.36 Examples of (a) CS and (b) CG stages . RS Vin (b) Solution Degenerated by RS, transistor M1 in Fig. 7.36(a) presents an impedance of 1 + gm1rO1RS + rO1 to the drain of M2. Thus the total impedance seen at the drain is equal to 1+gm1rO1RS + BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 353 (1) Sec. 7.5 Summary and Additional Examples 353 rO1 jjrO2, giving a voltage gain of Av = ,gm2 f 1 + gm1rO1RS + rO1 jjrO1g : (7.156) In Fig. 7.36(b), M1 operates as a common-gate stage and M2 as the load, obtaining (7.109): Av2 = rO2 1 gm1 + RS : (7.157) Exercise Replace RS wit a diode-connected device and repeat the analysis. Example 7.22 Calculate the voltage gain of the circuit shown in Fig. 7.37(a) if  = 0. VDD RD Vout Vin M1 M2 Vb RD 1 g m1 M 2 v out I1 v in (a) (b) Figure 7.37 (a) Example of a composite stage, (b) simplified circuit. Solution In of tahniaslcyizricnugitt,hMe c1irocpueirtaitsestoasreapslaocuercveinfoalnlodwMer1awndithMa2 as a CG stage (why?). A simple method Thevenin equivalent. From Fig. 7.29(b), we derive the model depicted in Fig. 7.37(b). Thus, Av = RD 1 gm1 + 1 gm2 : (7.158) Exercise What happens if a resistance of value R1 is placed in series with the drain of M1? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 354 (1) 354 Chap. 7 CMOS Amplifiers Example 7.23 The circuit of Fig. 7.38 produces two outputs. Calculate the voltage gain from the input to Y and to X. Assume  = 0 for M1. VDD Vb M3 M4 Y Vout2 Vin M1 X Vout1 M2 Figure 7.38 Example of composite stage. Solution jj 1 FM1o=3rgaVmno2dutM1,r4Oth2de,otcrniaronctusaiistftfsoeercrtMvteh2seaascsotusaracssoeuafrolcolelaodfwofelolrorowtpheeerr.faTotilholoenw.reEearx,dhyeiirbeicltdaininnggsahforsowmmatlh(l7-ast.i1gi3fn1ra)Ol i1m=pedan,cteheonf vout1 vin = gm1 2gjjm1r2Oj2jr+O2gm1 1 : (7.159) For Vout2, M1 operates as a degenerated CS stage with a drain load consisting of the d1io=dgem-c3ojnjrnOec3tjejrdOd4,evreicsueltMing3 and in the current source M4. This load impedance is equal to vout2 vin = , gmg1m113+jjrgOm132jjjrjOrO42 : (7.160) Exercise Which one of the two gains is higher? Explain intuitively why. 7.6 Chapter Summary The impedances seen looking into the gate, drain, and source of a MOSFET are equal to infinity, rO (with source grounded), and 1=gm (with gate grounded), respectively . In order to obtain the required small-signal MOS parameters such as gm and rO, the tran- sistor must be “biased,” i.e., carry a certain drain current and sustain certain gate-source and drain-source voltages. Signals simply perturb these conditions. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 355 (1) Sec. 7.6 Chapter Summary 355 Biasing techniques establish the required gate voltage by means of a resistive path to the supply rails or the output node (self-biasing). With a single transistor, only three amplifier topologies are possible: common-source and common-gate stages and source followers. The CS stage provides a moderate voltage gain, a high input impedance, and a moderate output impedance. Source degeneration improves the linearity but lowers the voltage gain. Source degeneration raises the output impedance of CS stages considerably. The CG stage provides a moderate voltage gain, a low input impedance, and a moderate output impedance. The voltage gain expressions for CS and CG stages are similar but for a sign. The source follower provides a voltage gain less than unity, a high input impedance, and a low output impedance, serving as a good voltage buffer. Problems In the pCox following problems, unless otherwise = 100 A=V2,  = 0, and VTH = stated, 0:4 V foasrsuNmMeOSndCeovxices=and20,00:4AV=Vfo2r, PMOS devices. 1. In the circuit of Fig. 7.39, determine the maximum allowable value of W=L if M1 must VDD = 1.8 V 50 k Ω 1 kΩ M1 Figure 7.39 remain in saturation. Assume  = 0. 2. We wish to design the circuit of Fig. 7.40 for a drain current of 1 mA. If W=L = 20=0:18, compute R1 and R2 such that the input impedance is at least 20 k . VDD = 1.8 V R1 500 Ω M1 R2 Figure 7.40 3. Consider the circuit shown in Fig. 7.41. Calculate the maximum transconductance that M1 can provide (without going into the triode region.) 4. The circuit of Fig. 7.42 must be designed for a voltage drop of 200 mV across RS. (a) (b) Calculate What are the the minimum allowable value of W=L if required values of R1 and R2 if the M1 must remain in saturation. input impedance must be at least 30 k. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 356 (1) 356 Chap. 7 CMOS Amplifiers 10 k Ω VDD = 1.8 V 1 kΩ M1 100 Ω Figure 7.41 VDD = 1.8 V R1 500 Ω M1 R2 R S 100 Ω Figure 7.42 5. Consider the circuit depicted in Fig. 7.43, where W=L = 20=0:18. Assuming the current flowing through R2 is one-tenth of ID1, calculate the values of R1 and R2 so that ID1 = 0:5 VDD = 1.8 V R1 500 Ω M1 R2 R S 200 Ω Figure 7.43 mA. 6. The self-biased stage of Fig. 7.44 must be designed for a drain current of 1 mA. If M1 is to VDD = 1.8 V RG RD M1 Figure 7.44 provide a transconductance of 1=100 , calculate the required value of RD. 7. We wish to design the stage in Fig. 7.45 for a drain current of 0.5 mA. If W=L = 50=0:18, calculate of ID1. the values of R1 and R2 such that these resistors carry a current equal to one-tenth 8. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.46. We know that circuit samples free from this error exhibit VGS = VDS whereas defective BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 357 (1) Sec. 7.6 Chapter Summary 357 R1 R2 VDD = 1.8 V 2 kΩ M1 Figure 7.45 Figure 7.46 10 k Ω 20 k Ω VDD = 1.8 V 1 kΩ M1 RP R S 200 Ω samples exhibit VGS = VDS + VTH. Determine the values of W=L and RP . 9. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.47. We know that circuit samples free from this error exhibit VGS = VDS + 100 mV whereas 30 k Ω VDD = 1.8 V RP 2 kΩ M1 Figure 7.47 defective samples exhibit VGS = VDS + 50 mV. Determine the values of W=L and RP . 10. In the circuit of Fig. 7.48, M1 and M2 have lengths equal to 0.25 m and  = 0:1 V,1. IX IY M1 M2 VB Figure 7.48 Determine W1 and W2 such that IX = 2IY = 1 mA. Assume VDS1 = VDS2 = VB = 0:8 V. What is the output resistance of each current source? 11. An NMOS current source must be designed for an output resistance of 20 k and an output current of 0.5 mA. What is the maximum tolerable value of ? 12. TV,heVBtw2o=cu1r:r2enVt,sou=rce0s:1inVF,ig1., 7.49 must and L1 = be designed L2 = 0:25 fomr,IcXalc=ulIaYte = 0:5 mA. If W1 and W2. VB1 = 1 Compare the output resistances of the two current sources. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 358 (1) 358 Chap. 7 CMOS Amplifiers IX IY M1 M2 VB1 VB2 Figure 7.49 13. Athe=stsuo0du:e1rncVte m,of1is,MtVaBk1.e1n=ly uses the circuit of 0:2 V, and VX has Fig. a dc 7.50 level as of a current source. If 1.2 V, calculate the W=L = 10=0:25, impedance seen at M1 VX VB1 Figure 7.50 14. In the circuit of Fig. 7.51, M1 and M2 serve as current sources. Calculate IX and IY if W L M1 I X VB VDD 2W L M2 IY Figure 7.51 VB = 1 V and W=L = 20=0:25. How are the output resistances of M1 and M2 related? 15. Cifons=id0e:r1thVe,c1ir,ccuailtcsuhloawtenViBn Fig. 7.52, such that where VX = 0W:9=VL. 1 = 10=0:18 and W=L2 = 30=0:18. VDD = 1.8 V M2 X VB M1 Figure 7.52 16. I((ban2))t=DNheeo0twce:1irrsm5ckuiVenitt,echo1Vf.IBXFsigua.csh7a.t5fhu3an,tcItWDio1=nL=of1jVIDX=2aj5s==V0X0:1:58g,omeAWs ff=rooLrmV2X0=t=o 1V00D:=9D0V.:1.8, 1 = 0:1 V,1, and 17. In the common-source stage of Fig. 7.54, W=L = 30=0:18 and  = 0. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M1 operates in satura- tion.) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 359 (1) Sec. 7.6 Chapter Summary 359 VDD = 1.8 V M2 IX VB M1 VX Figure 7.53 Figure 7.54 VDD = 1.8 V RD 2 kΩ Vout Vin M1 (b) With such a drain bias current, calculate the voltage gain of the stage. 18. The circuit of Fig. 7.54 is designed with W=L = 20=0:18,  = 0, and ID = 0:25 mA. (a) Compute the required gate bias voltage. (b) With such tion? What is tahegamteaxvoimltaugme,vhooltwagme ugcahinctahnatWca=nLbbeeaicnhcireevaesdedaswWhil=eLMin1crreemasaeisn?s in satura- 19. We wish to design the stage of Fig. 7.55 for a voltage gain of 5 with W=L  20=0:18. VDD = 1.8 V RD Vout Vin M1 Figure 7.55 Determine the required value of RD if the power dissipation must not exceed 1 mW. 20. The CS Assume stage 1 = o0f:1FiVg.,71.,5a6ndmus2t =pro0v:1id5eVa,v1o.ltage gain of 10 with a bias current of 0.5 mA. Vb Vin VDD = 1.8 V M2 Vout M1 Figure 7.56 (a) Compute the required value of W=L1. (b) if W=L2 = 20=0:18, calculate the required value of VB. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 360 (1) 360 Chap. 7 CMOS Amplifiers 21. In the stage if 1 = 0:1 Vof,F1 ,ig.W7.=5L6, 1M=2 2h0a=s 0a:1lo8n,ganlednIgDth=so1thmaAt . 2 1. Calculate the voltage gain 22. The and circuit of M2. If the Fig. 7.56 is designed for a bias current of width and the length of both transistors are I1 with certain dimensions for M1 doubled, how does the voltage gain change? Consider two cases: (a) the bias current remains constant, or (b) the bias current is doubled. 23. Explain which one of the topologies shown in Fig. 7.57 is preferred. Vb Vin VDD M2 Vout M1 Vin Vb VDD M2 Vout M1 (a) (b) Figure 7.57 24. The CS stage depicted in Fig. 7.58 must achieve a voltage gain of 15 at a bias current of 0.5 Vin Vb VDD = 1.8 V M2 Vout M1 Figure 7.58 mA. If 1 = 0:15 V,1 and 2 = 0:05 V,1, determine the required value of W=L2. 25. We wish to design the circuit shown in Fig. 7.59 for a voltage gain of 3. If W=L1 = VDD = 1.8 V M2 Vout Vin M1 Figure 7.59 20=0:18, determine W=L2. Assume  = 0. 26. I(an)tIhfeci=rcu0i,tdoefteFrimg.in7e.59W, =WL=2Ls1uc=h t1h0a=t 0M:118oapnedraItDes1 = 0:5 mA. at the edge of saturation. (b) Now calculate the voltage gain. (c) Explain why this choice of W=L2 yields the maximum gain. 27. The CS stage of Fig. 7.59 must achieve a voltage gain of 5. (a) If W=L2 = 2=0:18, compute the required value of W=L1. (b) What is the maximum allowable bias current if M1 must operate in saturation? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 361 (1) Sec. 7.6 Chapter Summary VDD M2 Vout Vin M1 Vb M2 Vin VDD M3 Vout M1 361 Vb Vin VDD M2 M1 Vout M3 Vin Vb (a) VDD M2 M1 Vout M3 (d) Figure 7.60 Vin Vb (b) VDD M2 M1 Vout M3 (e) (c) VDD M2 RD Vout Vin M1 (f) 6 28. If  = 0, determine the voltage gain of the stages shown in Fig. 7.60. 29. In the circuit of Fig. 7.61, determine saturation. Assume  = 0. the gate voltage such that M1 operates at the edge of VDD = 1.8 V RD Vout Vin M1 RS Figure 7.61 30. The degenerated CS stage of Fig. 7.61 must provide a voltage gain of 4 with a bias current of 1 mA. Assume a drop of 200 mV across RS and  = 0. (a) If RD = 1 k , determine the required value of W=L. Does the transistor operate in saturation for this choice of W=L? (b) If W=L = 50=0:18, determine the required value of RD. Does the transistor operate in saturation for this choice of RD? 31. Consider a degenerated CS stage with  0. Assuming gmrO 1, calculate the voltage gain of the circuit. 32. Calculate the voltage gain of the circuits depicted in Fig. 7.62. Assume  = 0. 6 33. Determine the output impedance of each circuit shown in Fig. 7.63. Assume  = 0. 34. The CS stage of Fig. 7.64 carries a bias current of 1 mA. If RD = 1 k and  = 0:1 V,1, compute the required value of W=L for a gate voltage of 1 V. What is the voltage gain of the circuit? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 362 (1) 362 Chap. 7 CMOS Amplifiers VDD VDD M2 M2 Vout RD Vin M1 Vout M3 Vin M1 M3 VDD RD Vout Vin M1 M2 Vb I1 (a) (b) (c) VDD RD Vout Vin M1 M2 Vb Vb Vin VDD M2 M1 Vout M3 (d) (e) Figure 7.62 35. Repeat Problem 34 with  = 0 and compare the results. 36. An adventurous student decides to try a new circuit topology wherein the input is applied to 6 the drain and the output is sensed at the source (Fig. 7.65). Assume  = 0, determine the voltage gain of the circuit and discuss the result. 37. In the common-source stage depicted in Fig. 7.66, the drain current of ideal current RD = 500 (a) Compute st,hoeur=vcael0uI,e1aonafnddWCr1=emLisatvioneorsybintlaadirengpeae.nvdoeltnatgoefgRa1inaonfd5R. 2 (why?). SMu1ppisosdeefiI1ne=d by the 1 mA, (r(ecbg))iWConhitowhohtshieleethvRea1luv+easluRfeo2sudonrfdaRwins1(nbaon),dmwRohr2aettthohaappnlpa0ec.ne1smtihfAeWtfrr=aoLnmsiisstthotewr si2uc0ep0pthlmya.tVfoauwnadyinfro(am)?tCheontrsiioddeer both the bias conditions (e.g., whether M1 comes closer to the triode region) and the voltage gain. 38. Consider the CS stage shown in Fig. 7.67, where I1 defines the bias current of M1 and C1 is very large. (a) If  = 0 and I1 = 1 mA, what is the maximum allowable value of RD? (b) With the value found in (a), determine W=L to obtain a voltage gain of 5. 39. The common-gate stage shown in Fig. 7.68 must provide a voltage gain of 4 and an input impedance of 50 . If ID = 0:5 mA, and  = 0, determine the values of RD and W=L. 40. Suppose and RD in for Fig. 7.68, ID = 0:5 an input impedance mA,  of 50 = 0, and and Vb = maximum 1 V. Determine the voltage gain (while values of W=L M1 remains in saturation). 41. A CG stage with a source resistance of RS employs a MOSFET with  0. Assuming gmrO, calculate the voltage gain of the circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 363 (1) Sec. 7.6 Chapter Summary 363 R out R out VDD Vin M1 M2 Vb Vin M1 M2 Vb I1 Figure 7.63 Vb Vin (a) R out M2 M1 M3 (c) (b) VDD Vin M2 Vb M1 M3 R out (d) Figure 7.64 VDD = 1.8 V RD Vout Vin M1 Figure 7.65 Vin VB M1 Vout RS 42. The CG stage depicted in Fig. 7.69 must provide an input impedance of 50 impedance of 500 . Assume  = 0. (a) (b) What With is the maximum allowable value of ID? the value obtained in (a), calculate the required value of W=L. and an output (c) Compute the voltage gain. 43. The CG amplifier C1 is very large. shown in Fig. 7.70 is biased by means of I1 = 1 mA. Assume  = 0 and (a) (b) What What value is the oref qRuDirepdlaWce=sLthief transistor M1 100 mV away from the circuit must provide a voltage the triode gain of 5 region? with the value of RD obtained in (a)? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 364 (1) 364 Figure 7.66 R1 C1 Vin R2 Chap. 7 CMOS Amplifiers VDD = 1.8 V RD Vout M1 I1 C1 Figure 7.67 R1 C1 Vin VDD = 1.8 V RD Vout M1 I1 C1 Figure 7.68 Figure 7.69 VDD = 1.8 V RD Vout M1 Vb Vin RD Vout M1 Vin VDD = 1.8 V 44. Determine the voltage gain of each stage depicted in Fig. 7.71. Assume  = 0. 45. Consider the circuit of Fig. 7.72, where a common-source stage by (a) a common-gate stage Writing vout=vin = (MvX2 a=nvdinRDvo2u).t=vX  and assuming  (M1 and RD1) = 0, compute is followed the overall voltage gain. ! 1 (b) Simplify the result obtained in (a) if RD1 . Explain why this result is to be expected. 46. Repeat Problem 45 for the circuit shown in Fig. 7.73. 47. Assuming  = 0, calculate the voltage gain of the circuit shown in Fig. 7.74. Explain why this stage is not a common-gate amplifier. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 365 (1) Sec. 7.6 Chapter Summary 365 Figure 7.70 RD Vout C1 M 1 VDD = 1.8 V Vin I1 VDD M2 Vout M1 Vb Vin RS (a) VDD M2 RD Vout M1 Vb Vin (b) VDD M2 Vout M1 Vb Vin RS R1 (c) VDD Vb M3 M2 Figure 7.71 RD Vout M1 Vb Vin (d) Vin Vb M1 M2 Vout RD VDD I1 (e) 48. Calculate the voltage gain of the stage depicted in Fig. 7.75. Assume  = 0 and the capaci- tors are very large. 49. The source follower shown in W=L = 20=0:18 and  = 0:1 VFi,g1. .7.76 is biased through RG. Calculate the voltage gain if 50. We wish to design the source follower shown in Fig. 7.77 for a voltage gain of 0.8. If W=L = 30=0:18 and  = 0, determine the required gate bias voltage. 51. The source follower of Fig. 7.77 is to be designed with a maximum bias gate voltage of 1.8 V. Compute the required value of W=L for a voltage gain of 0.8 if  = 0. 52. The source follower depicted in Fig. 7.78 employs a current source. Determine the values of I1 V. and W=L if the Assume  = 0. circuit must provide an output impedance less than 100 with VGS = 0:9 53. The circuit of Fig. 7.78 must exhibit an output impedance of less than 50 with a power budget of 2 mW. Determine the required value of W=L. Assume  = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 366 (1) 366 Figure 7.72 R D1 X VDD R D2 Vout M2 Vb Vin M1 Chap. 7 CMOS Amplifiers Figure 7.73 VDD R D2 Vin M1 Vout M2 Vb R D1 X Figure 7.74 VDD I1 Vout RG M1 Vin 54. We wish to design the source follower of Fig. 7.79 for a voltage gain of 0.8 with a power budget of 3 mW. Compute the required value of W=L. Assume C1 is very large and  = 0. 6 55. Determine the voltage gain of the stages shown in Fig. 7.80. Assume  = 0. 56. Consider the circuit shown in Fig. 7.81, where a source c(ao)mWmroitnin-ggavteoustta=gvein(M=2vaXnd=vRinD).vout=vX, compute the follower (M1 and I1 overall voltage gain. ) precedes a (b) Simplify the result obtained in (a) if gm1 = gm2. Design Problems In the following problems, unless otherwise stated, assume  = 0. 57. Design the CS stage shown in Fig. 7.82 for a voltage gain of 5 and an output impedance of 1 k . Bias the transistor so that it operates 100 mV away from the triode region. Assume the capacitors are very large and RD = 10 k . 58. The CS amplifier of Fig. 7.82 must be designed for a voltage gain of 5 with a power budget of 2 mW. If RDID = 1 V, determine the required value of W=L. Make the same assumptions BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 367 (1) Sec. 7.6 Chapter Summary 367 VDD RD C1 R3 R4 Vin Vout R2 M1 R1 CB Figure 7.75 RG Vin 50 k Ω VDD = 1.8 V 1 kΩ M1 RS Vout Figure 7.76 VDD = 1.8 V Vin M1 500 Ω Vout RS Figure 7.77 Figure 7.78 VDD = 1.8 V Vin M1 Vout I1 as those in Problem 57.  59. We wish to design the CS stage of Fig. 7.82 for maximum voltage gain but with W=L 50=0:18 and a maximum output impedance of 500 . Determine the required current. Make the same assumptions as those in Problem 57. 60. The degenerated stage depicted in Fig. 7.83 must provide a voltage gain of 4 with a power budget of 2 mW while the voltage drop across RS is equal to 200 mV. If the overdrive voltage of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5 of the allocated power, design the circuit. Make the same assumptions as those in Problem 57. 61. Design the circuit of Fig. 7.83 for a voltage gain of 5 and a power budget of 6 mW. Assume BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 368 (1) 368 Chap. 7 CMOS Amplifiers VDD = 1.8 V Vin M1 C1 Vout I1 50 Ω RL Figure 7.79 VDD Vin M1 Vout RS Vb M2 (a) Vin R1 VDD M1 Vout M2 R2 (d) Figure 7.80 VDD Vin M1 Vout Vb M2 RS (b) VDD Vb M3 M1 Vout Vin M2 (e) VDD Vin M1 Vout M2 Vb2 Vb1 Vin (c) VDD M3 M2 Vout M1 (f) VDD RD Vout Vin M1 X M2 Vb I1 Figure 7.81 the voltage drop across RS is equal to the overdrive voltage of the transistor and RD = 200 . 62. The circuit shown in Fig. 7.84 must provide a voltage gain of 6, with CS serving as a low impedance at the frequencies of interest. Assuming a power budget of 2 mW and an input impedance of region. Select 20 k , design the circuit the values of C1 and CS such that M1 operates 200 mV away from the triode so that their impedance is negligible at 1 MHz. 63. In the circuit of Fig. 7.85, M2 serves as a current source. Design the stage for a voltage BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 369 (1) Sec. 7.6 Chapter Summary 369 RG C1 Vin VDD = 1.8 V RD C2 M1 Vout Figure 7.82 R1 C1 Vin R2 VDD = 1.8 V RD Vout M1 RS Figure 7.83 Figure 7.84 R1 C1 Vin VDD = 1.8 V RD Vout M1 RS CS Vb Vin VDD = 1.8 V M2 Vout M1 Figure 7.85 gain of 20 and a power budget of 2 mW. Assume  = 0:1 V,1 for both transistors and  the maximum allowable Vout 1:5 V). level at the output is 1.5 V (i.e., M2 must remain in saturation if 64. Consider the circuit shown in Fig. 7.86, where CB is very large and n = 0:5p = 0:1 V,1. (a) Calculate the voltage gain. (b) Design the circuit 10rO1jjrO2 and the for a voltage gain of 15 and a dc level of the output must be power budget of equal to VDD=2. 3 mW. Assume RG  65. The CS stage of Fig. 7.87 incorporates a degenerated PMOS current source. The degener- ation must raise the voltage gain remains output nearly impedance equal to the of the current source to about 10rO1 intrinsic gain of M1. Assume  = 0:1 Vsu,ch1 that the for both BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 370 (1) 370 Figure 7.86 Chap. 7 CMOS Amplifiers CB RG Vin VDD = 1.8 V M2 Vout M1 Figure 7.87 Vb Vin VDD = 1.8 V RS M2 Vout M1 transistors and a power budget of 2 mW. ((inab)t)oIDftheVteBedrm=raiin1neVof,WdMe=t2Lerims1eitnqoeuaatchlhetoivev1ael0uraeOsv1oo.fltaWge=gLain2 and RS of 30. so that the impedance seen looking 66. Assuming a power budget of 1 mW and an overdrive of 200 mV for M1, design the circuit shown in Fig. 7.88 for a voltage gain of 4. VDD = 1.8 V M2 Vout Vin M1 Figure 7.88 67. Design the common-gate stage depicted in Fig. 7.89 for an input impedance of 50 voltage gain of 5. Assume a power budget of 3 mW. VDD = 1.8 V RD Vout M1 Vin I1 and a Figure 7.89 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 371 (1) Sec. 7.6 Chapter Summary 371 68. Design the circuit of Fig. 7.90 such that M1 operates 100 mV away from the triode region while providing a voltage gain of 4. Assume a power budget of 2 mW. VDD = 1.8 V RD Vout M1 Vin RS Figure 7.90 69. Figure 7.91 shows a self-biased common-gate stage, where RG  10RD and CG serves as a VDD = 1.8 V RD Vout RG M1 Vin CG RS Figure 7.91  low impedance so that the voltage gain is still given by gmRD. Design the circuit for a power budget of 5 mW and a voltage gain of 5. Assume RS 10=gm so that the input impedance remains approximately equal to 1=gm. 70. Design the CG stage shown in Fig. 7.92 such that it can accommodate an output swing of 500 RD Vout M1 Vin RS VDD = 1.8 V R2 R1 Figure 7.92  mVpp, region. i.e., Vout Assume can fall below a voltage gain its of bias value by 250 mV without driving M1 4 and an input impedance of 50 . Select into RS the triode 10=gm hanavdeRR1S+IDR+2 = 20 k VGS , V.T(HHi+nt:2s5i0ncmeVM=1 is biased 250 mV VDD , IDRD.) away from the triode region, we 71. Design the source follower depicted in Fig. 7.93 for a voltage gain of 0.8 and a power budget of 2 mW. Assume the output dc level is equal to VDD=2 and the input impedance exceeds 10 k . 72. Consider the source follower shown in Fig. 7.94. The circuit must provide a voltage gain of BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 372 (1) 372 Figure 7.93 RG Vin Chap. 7 CMOS Amplifiers VDD = 1.8 V M1 RS Vout RG Vin VDD = 1.8 V M1 X RS C1 50 Ω Vout RL Figure 7.94 0.8 at 100 MHz while consuming 3 mW. Design the circuit such that the dc voltage at node X is equal to VDD=2. Assume the input impedance exceeds 20 k . 73. In the source follower of Fig. 7.95, M2 serves as a current source. The circuit must operate VDD = 1.8 V Vin M1 Vout Vb M2 Figure 7.95 with a power budget of 3 V (i.e., M2 must remain mW, a voltage in saturation if gain of 0.9, and a VDS2  0:3 V). minimum Assuming allo=wa0b:1leVo,ut1pufot rofbo0t.3h transistors, design the circuit. SPICE Problems In the following problems, use the MOS models and source/drain dimensions given in Ap- pendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD, respectively. 74. In the circuit of Fig. 7.96, I1 is an ideal current source equal to VDD = 1 mA. 1.8 V Figure 7.96 10 k Ω I1 1 kΩ Vin C1 Vout (W L1 M1 ( (a) Using hand calculations, determine W=L1 such that gm1 = 100 ,1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 373 (1) Sec. 7.6 Chapter Summary 373 (b) Select C1 for an impedance of  100 ( 1 k ) at 50 MHz. (c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz.. (d) What is the change in the gain if I1 varies by 20? 75. The source follower of Fig. 7.97 employs a bias current source, M2. M1 Vin VDD = 1.8 V 20 0.18 Vout M2 10 0.8 V 0.18 Figure 7.97  (a) (b) (c) What value of What value of Determine the VViinn places places MM21 voltage gain if at the edge of saturation? at the edge of saturation? Vin has a dc value of 1.5 V. (d) What is the change in the gain if Vb changes by 50 mV? 76. Figure 7.98 depicts a cascade of a source follower and a common-gate stage. Assume Vb = 1:2 V and W=L1 = W=L2 = 10 m=0:18 m. VDD 1 kΩ Vout Vin M1 M2 Vb 1 mA Figure 7.98 (a) Determine the voltage gain if Vin has a dc value of 1.2 V. (b) Verify that the gain drops if the dc value of Vin is higher or lower than 1.2 V. (c) What dc value at the input reduces the gain by 10 with respect to that obtained in (a)? 77. Consider the CS stage shown in Fig. 7.99, where M2 operates as a resistor. Figure 7.99 M2 Vin M1 VDD = 1.8 V W2 0.18 Vout 10 0.18 (a) Determine W2 such that an input dc level of 0.8 V yields an output dc level of 1 V. What is the voltage gain under these conditions?  (b) What is the change in the gain if the mobility of the NMOS device varies by 10? Can you explain this result using the expressions derived in Chapter 6 for the transconductance? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 374 (1) 374 Chap. 7 CMOS Amplifiers 78. Repeat Problem 77 for the circuit illustrated in Fig. 7.100 and compare the sensitivities to the mobility. Figure 7.100 M2 Vin M1 VDD = 1.8 V W2 0.18 Vout 10 0.18 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 375 (1) 8 Operational Amplifier As A Black Box The term “operational amplifier” (op amp) was coined in the 1940s, well before the invention of the transistor and the integrated circuit. Op amps realized by vacuum tubes1 served as the core of electronic “integrators,” “differentiators,” etc., thus forming systems whose behavior followed a given differential equation. Called “analog computers,” such circuits were used to study the stability of differential equations that arose in fields such as control or power systems. Since each op amp implemented a mathematical operation (e.g., integration), the term “operational amplifier” was born. Op amps find wide application in today’s discrete and integrated electronics. In the cellphone studied in Chapter 1, for example, integrated op amps serve as building blocks in (active) filters. Similarly, the analo-to-digital converter(s) used in digital cameras often employ op amps. In this chapter, we study the operational amplifier as a black box, developing op-amp-based circuits that perform interesting and useful functions. The outline is shown below. General Concepts Op Amp Properties Linear Op Amp Circuits Noninverting Amplfier Inverting Amplifier Integrator and Differentiator Voltage Adder Nonlinear Op Amp Circuits Precision Rectifier Logarithmic Amplifier Square Root Circuit Op Amp Nonidealities DC Offsets Input Bias Currents Speed Limitations Finite Input and Output Impedances 8.1 General Considerations The operational amplifier can be abstracted as a black box having two inputs and one output.2 Shown in Fig. 8.1(a), the op amp symbol distinguishes between the two inputs by the plus and minus sign; Vin1 and Vin2 are called the “noninverting” and “inverting” inputs, respectively. We view the op amp as a circuit that amplifies the difference between the two inputs, arriving at the equivalent circuit depicted in Fig. 8.1(b). The voltage gain is denoted by A0: Vout = A0Vin1 , Vin2: (8.1) 1Vacuum tubes were amplifying devices consisting of a filament that released electrons, a plate that collected them, and another that controlled the flow—somewhat similar to MOSFETs. 2In modern integrated circuits, op amps typically have two outputs that vary by equal and opposite amounts. 375 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 376 (1) 376 Vin1 Chap. 8 Operational Amplifier As A Black Box Vin1 Vin2 Vout Vin1 Vin2 Vout A 0 (Vin1 − Vin2 ) (a) (b) Figure 8.1 (a) Op amp symbol, (b) equivalent circuit. It is instructive to plot Vout as a function of one input while the other remains at zero. With , 0Vsl,ionVp2oeu=(tg=a0in, )wiAse0chVoainvnse2isV[tFeoniugtt.w8=i.t2hA(tbh0)eV],ilrnaeb1v,eeloa“blnitnaoginniainnvngeergtthaientigvb”eeghsilavovepinoertaosnhVdoinhw1enn. OcinenaFtnhige“.ion8tvh.2ee(rrathi)na.gnT”dh,beiefhpVaoivsnii1toirv=.e Vout Vout A0 Vin1 Vin2 Vout Vout −A 0 Vin2 (a) (b) Figure 8.2 Op amp characteristics from (a) noninverting and (b) inverting inputs to output. The reader may wonder why the op amp has two inputs. After all, the amplifier stages studied in Chapters 5 and 7 have only one input node (i.e., they sense the input voltage with respect to , gaVmrionpu2lni,fidfe)o.rrAmhsasvstiehneegnfVtohourunotdu=agthiAoonuVtfitnohr.ismAcmahnapyplitcfieierr,crtuhciietrctpourpiintosclohipgaavielispnrgthotapwteowrtyionuoplfudtthbseeaordepifsafitmcuudpli,teVtdooiurnteaC=lhizaAep0utesVrini1ng01.an How does the “ideal” op amp behave? Such an op amp would provide an infinite voltage gain, an infinite input impedance, a zero output impedance, and infinite speed. In fact, the first-order analysis of an op-amp-based circuit typically begins with this idealization, quickly revealing the basic function of the circuit. We can then consider the effect of the op amp “nonidealities” on the performance. The very high gain of the op amp leads to an important observation. Since realistic circuits produce finite output swings, e.g., 2 V, the difference between Vin1 and Vin2 in Fig. 8.1(a) is always small: Vin1 , Vin2 = Vout A0 : (8.2) 1 Ionthoetrh.eFrowlloorwdisn,gthteheopabaomvpe,iadleoanligzawtiiothn,thweecmircauyitsrayyaVroinu1nd=itV, ibnr2inigfsAV0in=1 and . Vin2 close to each A common mistake is to interpret Vin1 = , shorted together. It must be borne in mind that VViinn21 as Vifint2hebetwcoomteesrmoninlyalisnVfininit1esainmdalVlyins2maarlel ! 1 as A0 but cannot be assumed exactly equal to zero. Example 8.1 The circuit shown in Fig. 8.3 is called a “unity-gain” buffer. Note that the output is tied to the inverting input. Determine the output voltage if Vin1 = +1 V and A0 = 1000. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 377 (1) Sec. 8.2 Op-Amp-Based Circuits 377 +1V A 0 = 1000 Vin Vout Figure 8.3 Unity-gain buffer. Solution If the voltage gain of the op amp were infinite, the difference between the two inputs would be zero and Vout = Vin; hence the term “unity-gain buffer.” For a finite gain, we write Vout = A0Vin1 , Vin2 (8.3) = A0Vin , Vout: (8.4) That is, Vout Vin = 1 A0 + A0 : (8.5) As Vin expected, the gain = 1 V, and Vout = a0p:9p9ro9aVc.hIensdueneidt,yVains1A,0 becomes large. In this Vin2 is small compared example, to Vin and AVo0ut=. 1000, Exercise What value of A0 is necessary so that the output voltage is equal to 0.9999? Op amps are sometimes represented as shown in Fig. 8.4 to explicitly indicate the supply vsuopltpalgye,si,nVwEhEichancdasVeCVCE.EFo=r example, 0. an op amp may operate between ground and a positive VCC Vin1 Vin2 VEE Vout Figure 8.4 Op amp with supply rails. 8.2 Op-Amp-Based Circuits In this section, we study a number of circuits that utilize op amps to process analog signals. In each case, we first assume an ideal op amp to understand the underlying principles and subsequently examine the effect of the finite gain on the performance. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 378 (1) 378 Chap. 8 Operational Amplifier As A Black Box 8.2.1 Noninverting Amplifier Recall from Chapters 5 and 7 that the voltage gain of amplifiers typically depends on the load resistor and other parameters that may vary considerably with temperature or process.3 As a  result, the voltage gain itself may suffer from a variation of, say, 20. However, in some applications (e.g., A/D converters), a much more precise gain (e.g., 2.000) is required. Op-ampbased circuits can provide such precision. Illustrated in Fig. 8.5, the noninverting amplifier consists of an op amp and a voltage divider that returns a fraction of the output voltage to the inverting input: Vin1 A0 Vout Vin Vin2 R1 R2 Figure 8.5 Noninverting amplifier. Vin2 = R2 R1 + R2 Vout: (8.6) Since a high op amp gain translates to a small difference between Vin1 and Vin2, we have Vin1  Vin2 (8.7)  R2 R1 + R2 Vout; (8.8) and hence Vout Vin  1 + R1 R2 : (8.9) Due to the positive gain, the circuit is called a “noninverting amplifier.” by Interestingly, 20, R1=R2 the voltage gain depends on only the ratio of the resistors; if R1 and R2 increase remains constant. The idea of creating dependence on only the ratio of quantities that have the same dimension plays a central role in circuit design. Example 8.2 Study the noninverting amplifier for two extreme cases: R1=R2 = 1 and R1=R2 = 0. Solution If R1=R2 ! 1, e.g., if R2 approaches zero, we note that Vout=Vin ! 1. Of course, as depicted in Fig. 8.6(a), this occurs because the circuit reduces to the op amp itself, with no fraction of the output fed back to the input. Resistor R1 simply loads the output node, with no effect on the gain if the op amp is ideal. If R1=R2 ! 0, e.g., if R2 approaches infinity, we have Vout=Vin ! 1. Shown in Fig. 8.6(b), this case in fact reduces to the unity-gain buffer of Fig. 8.3 because the ideal op amp draws no current at its inputs, yielding a zero drop across R1 and hence Vin2 = Vout. 3Variation with process means the circuits fabricated in different “batches” exhibit somewhat different characteristics. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 379 (1) Sec. 8.2 Op-Amp-Based Circuits 379 Vout Vin Vin R1 R2 = 0 (a) (b) Figure 8.6 Noninverting amplifier with (a) zero and (b) infinite value for R2. Vout R1 R2 = Exercise  Suppose the mismatch of circuit is designed 5% (i.e., R1 = 1 for a nominal gain of 0:05R2). What is the 2.00 but the R1 and actual voltage gain? R2 suffer from a Let us now take into account the finite gain of the op amp. Based on the model shown in Fig. 8.1(b), we write Vin1 , Vin2A0 = Vout; (8.10) and substitute for Vin2 from (8.6): Vout Vin = 1 + A0 R2 R1 + R2 A0 : (8.11) As the expected, this result gain of the op amp, rAed0u, caensdtoth(e8g.9a)inifoAf 0thRe2=ovRer1al+l aRm2plifier1, .VToouta=vVoiind, confusion between we call the former the “open-loop” gain and the latter the “closed-loop” gain. Equation (8.11) indicates that the finite gain of the op amp creates a small error in the value of Vout=Vin. denominator If to much greater than unity, permit the approximation th1e+term,1A0R12,=Rf1or+ R2 can 1: be factored from the Vout Vin  1 + R1 R2  1 , 1 + R1 R2 1 A0 : (8.12) Called the “gain error,” the term 1 + R1=R2=A0 must be minimized according to each appli- cation’s requirements. Example 8.3 A noninverting amplifier incorporates an op amp having a gain of 1000. Determine the gain error if the circuit is to provide a nominal gain of (a) 5, or (b) 50. Solution For a nominal gain of 5, we have 1 + R1=R2 = 5, obtaining a gain error of: 1 + R1 R2 1 A0 = 0:5: (8.13) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 380 (1) 380 Chap. 8 Operational Amplifier As A Black Box On the other hand, if 1 + R1=R2 = 50, then 1 + R1 R2 1 A0 = 5: In other words, a higher closed-loop gain inevitably suffers from less accuracy. (8.14) Exercise Repeat the above example if the op amp has a gain of 500. With an ideal op amp, the noninverting amplifier exhibits an infinite input impedance and a zero output impedance. For a nonideal op amp, the I/O impedances are derived in Problem 7. 8.2.2 Inverting Amplifier , ! iDapsnoeditpneRinfictnt2ieaitdwle,ehinvitlheFeenitnght.hea8onfi.u7ong(niahti)en,ivttoehiuresttip“nnuiognttvisnsewhprtiouinnrtgtgiestdargmatrnoopsullginafirtdoeeeusrd”nt.doiRn. cVeFocionrarp1llothfrraiostVemrisneSaa2nesocotnpi,o0annm;o8idp..1eea.,tXlhonanotigdsifewctXaihtlehlebordeepsaaairsms“tovaprirszgteuaRriaon1l gSorfinoVcuienndt=h.R”e2Ul,enfwdt heteircrtmhhiimns auclsotontfdhRietni1oflrneo,mwthaetihnersnoatuitgrzeheirRnop1auintfdvthtoheletoargpiegahmatpptpeeirnamprisuntaadclrraoatwsVssoRunto2,,cpurrorednutci[nFgiga. current 8.7(b)]. R1 R2 X Vin Vout Vin R2 R1 R2 X Vin Vout Virtual Ground (a) (b) A R2 R1 B (c) Figure 8.7 (a) Inverting amplifier, (b) currents flowing in resistors, (c) analogy with a seesaw. yielding 0 , Vout R1 = Vin R2 Vout Vin = ,R1 R2 : (8.15) (8.16) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 381 (1) Sec. 8.2 Op-Amp-Based Circuits 381 Due to the negative gain, the circuit is called the “inverting amplifier.” As with its noninverting counterpart, the gain of this circuit is given by the ratio of the two resistors, thereby experiencing only small variations with temperature and process. It is important to understand the role of the virtual ground in this circuit. If the inverting input of the op represent amp were not near zero potential, the currents flowing through R2 then and Rne1i,threesrpVeicnt=ivRel2y.noTrhVisoubte=hRav1iowroiusldsiamcicluarrattoelya seesaw [Fig. 8.7(c)], where the point between the two arms is “pinned” (e.g., does not move), allowing displacement of point A to be “amplified” (and “inverted”) at point B. The above development also reveals why the virtual ground cannot be shorted to the actual ground. Such yielding Vout a short = 0. It in Fig. 8.7(b) would is interesting to note force to ground all of the current flowing through R2, that the inverting amplifier can also be drawn as shown in Fig. 8.8, displaying a similarity with the noninverting circuit but with the input applied at a different point. Vout R2 R1 Vin Figure 8.8 Inverting amplifier. In contrast to the noninverting amplifier, the topology of Fig. 8.7(a) exhibits an input impedance is, a lower Req2uraelsutoltsRin2—a agsrecaatenr be seen gain but from the input a smaller input current, Vin=R2, impedance. This in Fig. 8.7(b). That trade-off sometimes makes this amplifier less attractive than its noninverting counterpart. Let us now compute the closed-loop gain of the inverting amplifier with a finite op amp gain. We note and VX from Fig. 8.7(a) that the currents flowing , Vout=R1, respectively. Moreover, through R2 and R1 are given by Vin ,VX =R2 Vout = A0Vin1 , Vin2 = ,A0VX: (8.17) (8.18) Equating the currents through R2 and R1 and substituting ,Vout=A0 for VX , we obtain Vout Vin = , 1 A0 + 1 R2 R1  1 A0 + 1 = , R2 R1 + 1 1 A0 1 + R2 R1  : Factoring R2=R1 from the deVnVooiunmt inat,orRRa21nd1as,sumA1i0ng 11++RRR211 =R 2: =A0 (8.19) (8.20) 1, we have (8.21)  , As expected, a higher closed-loop gain ( R1=R2) is accompanied with a greater gain error. Note that the gain error expression is the same for noninverting and inverting amplifiers. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 382 (1) 382 Chap. 8 Operational Amplifier As A Black Box Example 8.4 Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 4, a gain error of 0:1, and an input impedance of at least 10 k . Solution Since both the nominal gain and the gain error are given, we must first determine the minimum op amp gain. We have 1 A0 1 + R1 RR1 2 R2 = = 4 0:1: (8.22) (8.23) Thus, A0 = 5000: (8.24) Since the input impedance is approximately equal to R2, we choose: R2 = 10 k R1 = 40 k : (8.25) (8.26) Exercise Repeat the above example for a gain error of 1% and compare the results. a,acsVscIuuonmurattp=htet5eio0iasn0b0oltehvaiesdse,axts4oasVmuaimnpnlp=eet5r,ir0owo0nre0?o,afWysasiiebutlohmduieAntdg00:ta0hn=8eiinn5—pp0uu0attn0ci,muatcrphrceeeendpvtatainorbcftuleeaVilvsiangalrup+oepur4inonVdxmiinmeo=xas5ptt0eear0lpyi0epenl=qiccRueasa1tli.aotTnovhsoR.alt2tai.sgH,eoouowrf 8.2.3 Integrator and Differentiator Our study of the inverting topology in previous sections has assumed a resistive network around the op amp. In general, it is possible to employ complex impedances instead (Fig. 8.9). In analogy with (8.16), we can write Z1 Z2 Vout Vin Figure 8.9 Circuit with general impedances around the op amp. Vout Vin  , Z1 Z2 ; (8.27) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 383 (1) Sec. 8.2 Op-Amp-Based Circuits 383 where the gain of the op amp is assumed large. If Z1 or Z2 is a capacitor, two interesting functions result. InCt1esgr,a1toanrd ZS2up=poRse1.iWn Fitihg.a8n.9id,eZal1 is op a capacitor and amp, we have Z2 a resistor (Fig. 8.10). That is, Z1 = C1 R1 X Vin Vout Figure 8.10 Integrator. 1 Vout Vin = , C1s R1 = , 1 R1C1s : (8.28) (8.29) Providing a pole at the origin,4 the circuit operates as an integrator (and a low-pass filter). Figure 8.11 plots the magnitude of Vout=Vin as a function of frequency. This can also be seen in the time domain. Equating the currents flowing through R1 and C1 gives Vout Vin f Figure 8.11 Frequency response of integrator. Vin R1 = ,C1 dVout dt (8.30) and hence Vout = , 1 R1C1 Z Vindt: (8.31) Equation (8.29) indicates that Vout=Vin approaches infinity as the input frequency goes to zero. This is to be expected: the capacitor impedance becomes very large at low frequencies, approaching an open circuit and reducing the circuit to the open-loop op amp. As mentioned at the beginning of the chapter, integrators originally appeared in analog com- puters to simulate differential equations. Today, electronic integrators find usage in analog filters, control systems, and many other applications. Example 8.5 Plot the output waveform of the circuit shown in Fig. 8.12(a). Assume a zero initial condition across C1 and an ideal op amp. 4Pole frequencies are obtained by setting the denominator of the transfer function to zero. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 384 (1) 384 Chap. 8 Operational Amplifier As A Black Box V1 0 Tb C1 Vin R1 X V1 R1 Vout V1 Vin 0 Tb V1 I C1 R 1 0 0 Vout − V1 R1C1 (a) Figure 8.12 (a) Integrator with pulse input, (b) input and output waveforms. 0 (b) − V1Tb R1C1 t Solution When the input jumps resistor and hence the fcraopmac0ittoor,Vf1o,racicnognsthtaenrticguhrtrepnlatteeqvuoallttaogeV1o=fRC11bteogifnaslltolinfleoawrlythwroiuthghtimthee while its left plate is pinned at zero [Fig. 8.12(b)]: Vout = , 1 R1C1 Z Vindt (8.32) = , V1 R1C1 t 0 t Tb: (8.33) , V(zNeoruoott,ersetomhadatointhteheqeuocauultprtrouetnwtsVa1tvhTerbfo=ourgmRh1bCRe11coam(npderosCp“o1sr.htaTiorhpnueasrl,”totahtsehRevoa1lrCtea1ageudneadccrereroastshseesth.i)nepWcuathppeanuclisVteoi)nr tahrneedtruerhanfestnectro.e Exercise Repeat the above example if V1 is negative. The above example demonstrates the role of the virtual ground in the integrator. The ideal integration expressed by (8.32) occurs because the left plate of C1 is pinned at zero. To gain more insight, let us compare the integrator with a first-order RC filter in terms of their step response. , As illustrated in Fig. 8.13, the integrator forces a constant current (equal to capacitor. On the other hand, the RC filter creates a current equal to Vin decreases as Vout rises, leading to an increasingly slower voltage variation Vac1rV=oRosus1t)C=th1R.ro1W,uegwhmhitachyhe therefore consider the RC filter as a “passive” approximation of the integrator. In fact, for a large R1C1 product, the exponential response of Fig. 8.13(b) becomes slow enough to be approximated as a ramp. We virtual now examine ground node the performance in Fig. 8.10 with of the integrator VX , we have for A0 1. Denoting the potential of the Vin , VX R1 = VX , Vout 1 (8.34) C1s BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 385 (1) Sec. 8.2 Op-Amp-Based Circuits 385 C1 V1 0 Vin R1 X V1 R1 Vout V1 0 R1 Vin V1 −Vout R1 Vout C1 Figure 8.13 Comparison of integrator with and RC circuit. and VX = Vout ,A0 : (8.35) Thus, Vout Vin = 1 A0 + 1 ,1 + 1 A0 R1C1 s ; (8.36) revealing that the gain at s = 0 is limited to A0 (rather than infinity) and the pole frequency has moved from zero to sp = A0 ,1 + 1R1C1 : (8.37) Such a circuit is sometimes called a “lossy” integrator to emphasize the nonideal gain and pole position. Example 8.6 Recall from basic circuit theory that the RC filter shown in Fig. 8.14 contains a pole at ,1=RXCX . Determine RX and CX such that this circuit exhibits the same pole as that of the above integrator. RX Vin Vout CX Figure 8.14 Simple low-pass filter. Solution From (8.37), RXCX = A0 + 1R1C1: (8.38) The choice of RX and CX is arbitrary so long as their product satisfies (8.38). An interesting choice is RX = R1 CX = A0 + 1C1: (8.39) (8.40) It is as if the op amp “boosts” the value of C1 by a factor of A0 + 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 386 (1) 386 Chap. 8 Operational Amplifier As A Black Box Exercise What value of RX is necessary if CX = C1? Differentiator 8.15), we have If in the general topology of Fig. 8.9, Z1 is a resistor and Z2 a capacitor (Fig. R1 C1 X Vin Vout Figure 8.15 Differentiator. Vout Vin = , R1 1 C1s = ,R1C1s: (8.41) (8.42) Exhibiting a zero at the origin, the circuit acts as a differentiator (and a high-pass filter). Figure 8.16 tive, wpleotcsatnheeqmuaatgentihtuedceuorrfeVntosuflt=oVwiningastharofuungchtiCon1 of frequency. and R1: From a time-domain perspec- Vout Vin Figure 8.16 Frequency response of differentiator. R1 C1 f arriving at C1 dVin dt = , Vout R1 ; Vout = ,R1C1 dVin dt : (8.43) (8.44) Example 8.7 Plot the output waveform of the circuit shown in Fig. 8.17(a) assuming an ideal op amp. AStot l=ut0i,o,nVin = 0 and Vout = 0 (why?). When Vin jumps through C1 because the op amp maintains VX constant: to V1, an impulse of current flows Iin = C1 dVin dt (8.45) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 387 (1) Sec. 8.2 Op-Amp-Based Circuits 387 V1 0 Tb R1 Vin C1 X I in Vout V1 Vin 0 Tb I C1 0 Vout 0 0 t (a) (b) Figure 8.17 (a) Differentiator with pulse input, (b) input and output waveforms. = C1V1 t: (8.46) The current flows through R1, generating an output given by Vout = ,IinR1 = ,R1C1V1 t: (8.47) (8.48) Figure 8.17(b) current in C1: depicts the result. At t = Tb, Vin returns to zero, again creating an impulse of Iin = C1 dVin dt = C1V1 t: (8.49) (8.50) It follows that Vout = ,IinR1 = R1C1V1 t: (8.51) (8.52)  We can therefore say that the circuit generates an impulse of current it by R1 to produce Vout. In reality, of course, the output exhibits C1V1 t and “amplifies” neither an infinite height (limited by the supply voltage) nor a zero width (limited by the op amp nonidealities). Exercise Plot the output if V1 is negative. It is instructive to compare the operation of the differentiator with that of its “passive” counterpart (Fig. 8.18). In the ideal differentiator, the virtual ground node permits the input to change the voltage across C1 instantaneously. In the RC filter, on the other hand, node X is not “pinned,” thereby following the input change at t = 0 and limiting the initial current in the circuit to V1=R1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 388 (1) 388 Chap. 8 Operational Amplifier As A Black Box If the decay time constant, R1C1, is sufficiently small, the passive circuit can be viewed as an approximation of the ideal differentiator. R1 V1 0 Vin C1 X I in Vout V1 0 C1 X V1 Vin Vout R1 (a) (b) Figure 8.18 Comparison of differentiator and RC circuit. Let us now study the differentiator with a finite op amp gain. Equating the capacitor and resistor currents in Fig. 8.15 gives Vin , VX 1 C1s = VX , Vout R1 : (8.53) Substituting ,Vout=A0 for VX , we have Vout Vin = 1+ A,10R+1CR1s1AC01s : (8.54) In contrast to the ideal differentiator, the circuit contains a pole at sp = , A0 + 1 R1C1 : (8.55) Example 8.8 Determine the transfer function of the high-pass filter shown in Fig. 8.19 and choose RX and CX such that the pole of this circuit coincides with (8.55). CX Vin Vout RX Figure 8.19 Simple high-pass filter. Solution The capacitor and resistor operate as a voltage divider: Vout Vin = RX RX + 1 CX s = RX CX s RXCXs + 1: (8.56) (8.57) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 389 (1) Sec. 8.2 Op-Amp-Based Circuits 389 The circuit therefore exhibits a zero at the origin (s = 0) and a pole at ,1=RXCX . For this pole to be equal to (8.55), we require One choice of RX and CX is 1 RX CX = A0 + 1 R1C1 : (8.58) RX = R1 A0 + 1 CX = C1; (8.59) (8.60) Exercise What is the necessary value of CX if RX = R1? An important drawback of differentiators stems from the amplification of high-frequency noise. As suggested by (8.42) and Fig. 8.16, the increasingly larger gain of the circuit at high frequencies tends to boost noise in the circuit. The general topology of Fig. 8.9 and its integrator and differentiator descendants operate as inverting circuits. The reader may wonder if it is possible to employ a configuration similar to the noninverting amplifier of Fig. 8.5 to avoid the sign reversal. Shown in Fig. 8.20, such a circuit provides the following transfer function Vin Z1 Z2 Vout Figure 8.20 Op amp with general network. Vout Vin = 1+ Z1 Z2 ; (8.61) if the op amp is ideal. Unfortunately, this function does not translate to ideal integration or dif- ferentiation. For example, Z1 = R1 and Z2 = 1=C2s yield a nonideal differentiator (why?). 8.2.4 Voltage Adder The need for adding voltages arises in many applications. In audio recording, for example, a number of microphones may convert the sounds of various musical instruments to voltages, and these voltages must then be added to create the overall musical piece. This operation is called “mixing” in the audio industry.5 For example, in“noise cancelling” headphones, the environmen- 5The term “mixing” bears a completely different meaning in the RF and wireless industry. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 390 (1) 390 Chap. 8 Operational Amplifier As A Black Box tal noise is applied to an inverting amplifier and subsequently added to the signal so as to cancel itself. Figure 8.21 depicts a voltage adder (“summer”) incorporating an op amp. With an ideal op amp, VX = currents add 0, at tahnedvRir1tuaanl dgrRou2ncdanrroydecuarnrdenfltsowprtohproorutgiohnRalFto: V1 and V2, respectively. The two Figure 8.21 Voltage adder. RF R1 V1 X V2 R2 Vout V1 R1 + V2 R2 = ,Vout RF : (8.62) That is, Vout = ,RF V1 R1 + V2 R2 : For example, if R1 = R2 = R, then Vout = ,RF R V1 + V2: (8.63) (8.64) This circuit can therefore add and amplify voltages. Extension to more than two voltages is straightforward. RFE=qRu2a,tiroensp(8ec.6ti3v)eilnyd. iTchatiessptrhoapteVr1tyaanldsoV2prcoavnebseuasdefdueldiwn imthadniyffaeprepnlitcwateiiognhst.inFgosr: RF =R1 and example, in audio recording it may be necessary to lower the “volume” of one musical instrument for part of the piece, a task possible by varying R1 and R2. The behavior of the circuit in the presence of a finite op amp gain is studied in Problem 31. 8.3 Nonlinear Functions It is possible to implement useful nonlinear functions through the use of op amps and nonlinear devices such as transistors. The virtual ground property plays an essential role here as well. 8.3.1 Precision Rectifier The rectifier circuits described in Chapter 3 suffer from a “dead zone” due to the finite voltage required to turn on the diodes. That is, if the input signal amplitude is less than approximately 0.7 V, the diodes remain off and the output voltage remains at zero. This drawback prohibits the use of the circuit in high-precision applications, e.g., if a small signal received by a cellphone must be rectified to determine its amplitude. It is possible to place a diode around an op amp to form a “precision rectifier,” i.e., a circuit that rectifies even very small signals. Let us begin with a unity-gain buffer tied to a resistive load [Fig. 8.22(a)]. We note that the high positive and negative cycles). Now sguapinpoosfethweeowpiasmh ptoenhsouldreXs thaattzneordoedXuritnrgacnkesgVaitniv(efocrycbloetsh, i.e., “break” the connection between the output of the op amp and its inverting input. This can be BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 391 (1) Sec. 8.3 Nonlinear Functions 391 accomplished Vout is sensed as at depicted X rather in Fig. than at 8.22(b), where D1 is inserted the output of the op amp. in the feedback loop. Note that Vin X R1 Vin Vout Vin X Y Vout VY R1 D1 t VD,on t Vout t (a) (b) (c) Figure 8.22 (a) Simple op amp circuit, (b) precision rectifier, (c) circuit waveforms. To analyze the operation of this circuit, let us first assume that Vin = 0. In its attempt to minimize the voltage difference between the noninverting and the inverting inputs, the op amp   rcaNanaoirdsWwreyRshia1fVactYyVuhiierntarolpedbpnaseeptVcnpfoorsruomoitmfxeVismXisnValittibgoenelh.ycYtTolVy,mhDwapet1hos;iiossscni,lhti,iegvitvhseuet,rnnlnyVoisYtnnmgpeargoDilasslste1ipisvbobelfsae?uir.trFeitTvlohyehreurolVesnosv,oueDbtlutst1htoaatwtuat sitrtthsnhhuesemlioicntfeutpflraeuartenncnaeduptgrtrpaflheteeoniavwtorespianvotaagttmlhhutaehpetr,opoVDuruXot1gpdhumutDc.ue0s1st. a very large negative output (near the negative supply rail) because its noninverting input falls below its inverting input. Figure 8.22(c) plots the circuit’s waveforms in response to an input sinusoid. Example 8.9 Plot the waveforms in the circuit of Fig. 8.23(a) in responsVeinto an input sinusoid. D1 R1 X Vin VX Y VY −VD,on (a) Figure 8.23 (a) Inverting precision rectifier, (b) circuit waveforms. t t t (b) Solution sFalnoigdrhVXtilnyisd=aecv0ri,erttahuseaelsogptoroaaumlnlpodw.cAreDsat1VeistnoVbcYeacrroym,tehVseDpho;iosgnihtisevore,cthutharutresDnrt1a.iiTssihnbagatrtiehsle,yVcouXnrr,eRn1t0tchaarnrorduiegVshYlRitt1le, V,cYuVrDroen;nolnty, for positive input cycles. For Vin 0, D1 turns off (why?), leading to VX = Vin and driving VY to a very positive value. Figure 8.23(b) shows the resulting waveforms. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 392 (1) 392 Chap. 8 Operational Amplifier As A Black Box Exercise , Repeat the above example for a triangular input that goes from 2 V to +2 V. The large swings at the output of the op amp in Figs. 8.22(b) and 8.23(a) lower the speed of the circuit as the op amp must “recover” from a saturated value before it can turn D1 on again. Additional techniques can resolve this issue (Problem 39). 8.3.2 Logarithmic Amplifier Consider the circuit of Fig. 8.24, where a bipolar transistor is placed around the op amp. With an ideal op amp, R1 carries a current equal to Vin=R1 and so does Q1. Thus, Vin R1 R1 X Vin Q1 Vout Figure 8.24 Logarithmic amplifier. VBE = VT ln Vin=R1 IS : (8.65) Also, Vout = ,VBE and hence Vout = ,VT ln Vin R1IS : (8.66) The output is therefore proportional to the natural logarithm of Vin. As with previous linear and nonlinear circuits, the virtual ground plays an essential role here as it guarantees the current flowing through Q1 is xactly proportional to Vin. Logarithmic amplifiers (“logamps”) prove useful in applications where the input signal level may vary by a large factor. It may be desirable in such cases to amplify weak signals and attenuate (“compress”) strong signals; hence a logarithmic dependence. The negative sign in (8.66) is to be expected: if Vin rises, so do the currents flowing through R1 fall and Q1, requiring an below zero to provide increase in VBE. Since the base a greater collector current. Note is at zero, the emitter that Q1 operates in the voltage must active region because both the base and the collector remain at zero. The effect of finite op amp gain is studied in Problem 41. tVhoeuTtohpiesarnmeoaptddeiserfibmnraoeydk.ewnIno, natdhneedraVwcothuuatatlahpcapirprcpoueainct,hsQeifs1Vthcienannbneeogctaoctmiavreersysnuaepg“panltyeivgreaa.tiilEv. eqI”tuaicstuitorhrneenr(e8t,f.6oth6ree) predicts that loop around necessary to ensure Vin remains positive. 8.3.3 Square-Root Amplifier Recognizing that the logarithmic amplifier of Fig. 8.24 in fact implements the inverse function of the exponential characteristic, we surmise that replacing the bipolar transistor with a MOSFET BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 393 (1) Sec. 8.4 Op Amp Nonidealities 393 leads to a “square-root” amplifier. current equal to Vin=R1: Illustrated in Fig. 8.25, such a circuit requires that M1 carry a R1 X Vin M1 Vout Figure 8.25 Square-root circuit. Vin R1 = 1 2 nCox W L VGS , VT H 2: (8.67) vuut (Channel-length modulation is neglected here.) Since VGS = ,Vout, Vout = , 2Vin nCox W L R1 , VT H : (8.68) , If Vin is becomes nmeoarrezperoos,ittihveen, VVoouuttfraellms atoinasllaotw VT H , M1 to placing carry a M1 at the edge greater current. of conduction. As Vin With its gate and drain at zero, M1 operates in saturation. 8.4 Op Amp Nonidealities Our study in previous sections has dealt with a relatively idealized op amp model—except for the finite gain—so as to establish insight. In practice, however, op amps suffer from other imperfections that may affect the performance significantly. In this section, we deal with such nonidealities. 8.4.1 DC Offsets The op amp characteristics shown in Fig. 8.2 imply that Vout = 0 if Vin1 = Vin2. In reality, a zero input difference may not give a zero output difference! Illustrated in Fig. 8.26(a), the characteristic is “offset” to the right or to the left; i.e., for Vout = 0, the input difference must be raised to a certain value, Vos, called the input “offset voltage.” Vout Vos Vin1 − Vin1 Vos Vout (a) (b) (c) Figure 8.26 (a) Offset in an op amp, (b) mismatch between input devices, (c) representation of offset. What causes offset? The internal circuit of the op amp experiences random asymmetries (“mismatches”) during fabrication and packaging. For example, as conceptually shown in Fig. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 394 (1) 394 Chap. 8 Operational Amplifier As A Black Box 8.26(b), the bipolar transistors sensing the two inputs may display slightly different base-emitter voltages. The same effect occurs for MOSFETs. We model the offset by a single voltage source placed in series with one of the inputs [Fig. 8.26(c)]. Since offsets are random and hence can be positive or negative, Vos can appear at either input with arbitrary polarity. Why are DC offsets important? Let us reexamine some of the circuit topologies studied in Section 8.2 in the presence of op amp offsets. Depicted in Fig. 8.27, the noninverting amplifier now sees a total input of Vin + Vos, thereby generating Vos Vin Vout R1 R2 Figure 8.27 Offset in noninverting amplifier. Vout = 1 + R1 R2 Vin + Vos: (8.69) In other words, the circuit amplifies the offset as well as the signal, thus incurring accuracy limitations.6 Example 8.10 A truck weighing station employs an electronic pressure meter whose output is amplified by the circuit of Fig. 8.27. If the pressure meter generates 20 mV for every 100 kg of load and if the op amp offset is 2 mV, what is the accuracy of the weighing station? Solution An offset of 2 mV corresponds to a load of 10 kg. We therefore say the station has an error of 10 kg in its measurements. Exercise  What offset voltage is required for an accuracy of 1 kg? DC offsets may also cause “saturation” in amplifiers. The following example illustrates this point. Example 8.11 An electrical engineering student constructs the circuit shown in Fig. 8.28 to amplify the signal produced by a microphone. The targeted gain is 104 so that very low level sounds (i.e., microvolt signals) can be detected. Explain what happens if op amp A1 exhibits an offset of 2 mV. Solution From Fig. 8.27, we recognize that the first stage amplifies the offset by a factor of 100, generating a dc level of 200 mV at node X (if the microphone produces a zero dc output). The second stage V 6The reader can show that placing os in series with the inverting input of the op amp yields the same result. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 395 (1) Sec. 8.4 Op Amp Nonidealities 395 A1 X 10 k Ω 100 Ω A2 Vout 10 k Ω 100 Ω Figure 8.28 Two-stage amplifier. now amplifies VX by another factor of 100, thereby attempting to generate Vout = 20 V. If A2 operates with a supply voltage of, say, 3 V, the output cannot exceed this value, the second op amp drives its transistors into saturation (for bipolar devices) or triode region (for MOSFETs), and its gain falls to a small value. We say the second stage is saturated. (The problem of offset amplification in cascaded stages can be resolved through ac coupling.) Exercise Repeat the above example if the second stage has a voltage gain of 10. DC offsets impact the inverting amplifier of Fig. 8.7(a) in a similar manner. This is studied in Problem 49. We now examine the effect of offset on the integrator of Fig. 8.10. Suppose the input is set to zero and Vos is referred to the noninverting input [Fig. 8.29(a)]. What happens at the output? Re- call from Fig. 8.20 and Eq. (8.61) that the response to this “input” consists of the input itself [the unity term in (8.61)] and the integral of the input [the second term in (8.61)]. We can therefore express Vout in the time domain as Vout = Vos + 1 R1C1 Zt 0 Vosdt = Vos + Vos R1C1 t; (8.70) (8.71) 1 ,1 where the initial condition across C1 is assumed op amp offset, generating an output that tends to zero. In + or other words, the circuit integrates depending on the sign of Vos. the Of course, as Vout approaches the positive or negative supply voltages, the transistors in the op amp fail to provide gain and the output saturates [Fig. 8.29(b)]. The problem of offsets proves quite serious in integrators. Even in the presence of an input sig- nal, the circuit of Fig. 8.29(a) integrates the offset and reaches saturation. Figure 8.29(c) depicts a modification, where resistor R2 is placed in parallel with C1. Now the effect of Vos at the output is given by (8.9) because the circuits of Figs. 8.5 and 8.29(c) are similar at low frequencies: Vout = Vos 1 + R2 R1 : (8.72) For example, if Vos = 2 mV and R2=R1 = 100, then Vout contains a dc error of 202 mV, but at least remains away from saturation.. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 396 (1) 396 Chap. 8 Operational Amplifier As A Black Box C1 R1 VCC Vout Vout VCC VEE Vos t (a) R2 C1 R1 Vos Vout (b) R2 C1 R1 Vin Vout (c) (d) Figure 8.29 (a) Offset in integrator, (b) output waveform, (c) addition of R2 to reduce effect of offset, (d) determination of transfer function. How does R2 affect the integration function? Disregarding Vos, viewing the circuit as shown in Fig. 8.29(d), and using (8.27), we have Vout Vin = , R2 R1 1 R2C1s + 1: (8.73) , Thus, the circuit now contains frequencies of interest lie well a pole above at this 1=R2C1 value, then rather than at the R2C1s 1 and origin. If the input signal Vout Vin = , 1 R1C1 s : (8.74) That is, the integration function holds for input frequencies much higher than 1=R2C1. Thus, RR22=CR1 1mmusutsbt ebesusuffifficiceinetnltylylasrmgealslosoasatsotonemgilnigimibilzyeimthpeaacmt tphleifiseigdnoaflfsferetqguiveenncibeys (8.72) whereas of interest. 8.4.2 Input Bias Current Op amps implemented in bipolar technology draw a base current from each input. While rela-  tively small ( 0:1-1 A), the input bias currents may create inaccuracies in some circuits. As shown in Fig. 8.30, each bias current is modeled by a current source tied between the correspond- ing input and ground. Nominally, IB1 = IB2. Let us study the effect of the input currents on the noninverting amplifier. As depicted in Fig. 8.31(a), IB2, on IB1 has no effect on the other hand, flows the circuit because it flows through a voltage source. The current through R1 and R2, introducing an error. Using superposition and setting Vin to zero, we arrive at the circuit in Fig. 8.31(b), which can be transformed to that in Fig. 8.31(c) if IB2 and R2 are replaced with their Thevenin equivalent. Interestingly, the circuit now resembles the inverting amplifier of Fig. 8.7(a), thereby yielding BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 397 (1) Sec. 8.4 Op Amp Nonidealities 397 Figure 8.30 Input bias currents. Vin1 Vin2 I B1 Vout I B2 Vin I B1 Vout R1 I B2 R2 I B1 X I B2 Vout R1 R2 (a) R2 (b) Vout R1 − I B2 R2 (c) Figure 8.31 (a) Effect of input bias currents on noninverting amplifier, (b) simplified circuit, (c) Thevenin equivalent. Vout = ,R2IB2 , R1 R2 = R1IB2 (8.75) (8.76) if the op amp gain is pected result because infinite. This expression suggests that the virtual ground at X in Fig. 8.31(b) fIoBr2ceflsoawzseroonvlyoltthargoeuagchroRs1s,Ra2n exand hence a zero current through it. The error due to the input bias current appears similar to the DC offset effects illustrated in Fig. 8.27, corrupting the output. However, unlike DC offsets, this phenomenon is not random; for a given bias current in the bipolar transistors used in the op amp, the base currents drawn from the inverting and noninverting inputs remain approximately equal. We may therefore seek a method of canceling this error. For example, we can insert a corrective voltage in series with the noninverting input so as to drive Vout to zero (Fig. 8.32). Since Vcorr “sees” a noninverting amplifier, we have Vout = Vcorr 1 + R1 R2 + IB2R1: (8.77) For Vout = 0, Vcorr = ,IB2R1jjR2: (8.78) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 398 (1) 398 Chap. 8 Operational Amplifier As A Black Box Vcorr Vout = 0 R1 X I B2 R2 Figure 8.32 Addition of voltage source to correct for input bias currents. Example 8.12 A bipolar op amp employs a collector current of 1 mA in each of the input devices. If = 100 and and the circuit of Fig. 8.32 incorporates the required value of Vcorr. R2 = 1 k , R1 = 10 k , determine the output error Solution We have IB = 10 A and hence Vout = 0:1 mV: (8.79) Thus, Vcorr is chosen as Vcorr = ,9:1 V: (8.80) Exercise Determine the correction voltage if = 200. jj Equation (8.78) implies that Vcorr depends Since varies with process and temperature, “track” . Fortunately, (8.78) also reveals that oVVnccooIrrBrr2ccaaannndnboehteonrbectmeaitanhienedcabutyrarepfinaxtssegidanigvnaaolufbeatrsaaenncdsiusmrtroeurnsstt. tiIhnBrto2o,uatgchhceonauVrneotsuaitsntd=orp0reoqfvuoearltVhtaoint RV=o1u0tR.is2T,hslteeilarl ednaiendagerrtzoiesrteohn.ectoouproalgoegdytsohtoawken in Fig. 8.33. Here, if IB1 = the finite gain of the op amp R1 I B1 Vin R 2 I B2 Vout R1 R2 Figure 8.33 Correction for variation of beta. From the drawing in Fig. 8.31(b), we observe that the input bias currents have an identical effect on the inverting amplifier. Thus, the correction technique shown in Fig. 8.33 applies to this circuit as well. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 399 (1) Sec. 8.4 Op Amp Nonidealities 399 In reality, asymmetries in the op amp’s internal circuitry introduce a slight (random) mismatch between IB1 and IB2. Problem 53 studies the effect of this mismatch on the output in Fig. 8.33. We now consider the effect of the input bias currents on the performance of integrators. Il- lustrated in Fig. 8.34(a) with Vin = 0 and IB1 omitted (why?), the circuit forces IB2 to flow through C1 because R1 sustains a zero voltage drop. In fact, the Thevenin equivalent of R1 and IB2 [Fig. 8.34(b)] yields C1 C1 R1 I B2 Vout R1 − I B2 R1 Vout (a) (b) Figure 8.34 (a) Effect of input bias currents on integrator, (b) Thevenin equivalent. Vout = , 1 R1C1 Z Vindt = + 1 R1C1 IB2 R1dt = IB2 C1 dt: (8.81) (8.82) (8.83) (Of course, the flow of integrates the input bias IB2 through C1 current, thereby leads to the forcing Vout same result.) In other words, to eventually saturate near the the circuit positive or negative supply rails. Can we apply the correction technique of Fig. 8.33 to the integrator? The model in Fig. 8.34(b) suggests that a resistor equal to R1 placed in series with the noninverting input can cancel the effect. The result is depicted in Fig. 8.35. C1 R1 Vin Vout R1 Figure 8.35 Correction for input currents in an integrator. Example 8.13 An electrical engineering student attempts the topology of Fig. 8.35 in the laboratory but observes that the output still saturates. Give three possible reasons for this effect. Solution First, the DC offset voltage of the op amp itself is still integrated (Section 8.4.1). Second, the two input bias currents always suffer from a slight mismatch, thus causing incomplete cancellation. Third, the two resistors in Fig. 8.35 also exhibit mismatches, creating an additional error. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 400 (1) 400 Chap. 8 Operational Amplifier As A Black Box Exercise Is resistor R1 necessary if the internal circuitry of the op amp uses MOS devices? The problem of input bias current mismatch requires a modification similar to that in Fig. 8.29(c). The mismatch current then flows through R2 rather than through C1 (why?). 8.4.3 Speed Limitations Finite Bandwidth Our study of op amps has thus far assumed no speed limitations. In reality, the internal capacitances of the op amp degrade the performance at high frequencies. For example, as illustrated in Fig. 8.36, the gain begins to fall as the frequency of operation exceeds f1. In this chapter, we provide a simple analysis of such effects, deferring a more detailed study to Chapter 11. Av A0 1 f1 Figure 8.36 Frequency response of an op amp. fu f To represent the gain roll-off shown in Fig. 8.36, we must modify the op amp model offered in Fig. 8.1. As a simple approximation, the internal circuitry of the op amp can be modeled by a first-order (one-pole) system having the following transfer function: Vout Vin1 , Vin2 s = 1 +A0!s1 ; (8.84) where A0. At !1 = 2f1. Note that very high frequencies, at frequencies well below s=!1 1, and the gain of !1, the s=!1 op amp 1 and the gain is equal to falls to unity at !u = A0!1. This frequency is called the “unity-gain bandwidth” of the op amp. Using this model, we can reexamine the performance of the circuits studied in the previous sections. Consider the noninverting amplifier of Fig. 8.5. We utilize Eq. (8.11) but replace A0 with the above transfer function: Vout Vin s = 1 + R1R+12+RA20!s+1 1 +A0!s1 : (8.85) Multiplying the numerator and the denominator by 1 + s=!1 gives Vout Vin s = s !1 + A0 R2 R1 + R2 A0 : +1 (8.86) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 401 (1) Sec. 8.4 Op Amp Nonidealities 401 The system is still of first order and the pole of the closed-loop transfer function is given by j!p;closedj = 1 + R2 R1 + R2 A0 !1: (8.87) As depicted in Fig. 8.37, the bandwidth of the closed-loop circuit is substantially higher than that of the op amp itself. This improvement, of course, accrues at the cost of a proportional reduction in gain—from A0 to 1 + R2A0=R1 + R2. Av A0 Op Amp Frequency Response A0 (1+ R2 R 1+ R 2 A0 ) 1 Noninverting Amplifier Frequency Response f1 fu f (1+ R R2 1+ R 2 A 0 ) f 1 Figure 8.37 Frequency response of (a) open-loop op amp and (b) closed-loop circuit. Example 8.14 A noninverting amplifier incorporates an op amp having an open-loop gain of 100 and bandwidth of 1 MHz. If the circuit is designed for a closed-loop gain of 16, determine the resulting bandwidth and time constant. Solution For a closed-loop gain of 16, we require that 1 + R1=R2 = 16 and hence j!p;closedj = 1 0 + R2 R1 + R2 A0 1 !1 = BB@1 + 1 R1 R2 + 1A0CCA !1 = 2  635 MHz: (8.88) (8.89) (8.90) Given by j!p;closedj,1, the time constant of the circuit is equal to 2.51 ns. Exercise Repeat the above example if the op amp gain is 500. The above analysis can be repeated for the inverting amplifier as well. The reader can prove that the result is similar to (8.87). The finite bandwidth of the op amp may considerably degrade the performance of integrators. The analysis is beyond the scope of this book, but it is outlined in Problem 57 for the interested reader. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 402 (1) 402 Chap. 8 Operational Amplifier As A Black Box Another critical issue in the use of op amps is stability; if placed in the topologies seen above, some op amps may oscillate. Arising from the internal circuitry of the op amp, this phenomenon often requires internal or external stabilization, also called “frequency compensation.” These concepts are studied in Chapter 12. Slew Rate In addition to bandwidth and stability problems, another interesting effect is ob- served in op amps that relates to their response to large signals. Consider the noninverting con- figuration shown in Fig. 8.38(a), where the closed-loop transfer function is given by (8.86). A j j small equal stotep!opf;closVeda,t t1he[Finigp.u8t.t3h8u(sbr)e].suIflttshieniannpuamt sptelipfieisdroauistepduttowa2veVfo,rmeahchavpinoginat time constant on the output waveform also rises by a factor of two.7 In other words, doubling the input amplitude doubles both the output amplitude and the output slope. Vin Vin Vout ∆V Vin R1 R2 Vout 2 ∆V t Vout Ramp t Linear Settling t t (a) (b) (c) Figure 8.38 (a) Noninverting amplifier, (b) input and output waveforms in linear regime, (c) input and output waveforms in slewing regime. In reality, op amps do not exhibit the above behavior if the signal amplitudes are large. As illustrated in Fig. 8.38(c), the output first rises with a constant slope (i.e., as a ramp) and eventu- ally settles as in the linear case of Fig. 8.38(b). The ramp section of the waveform arises because, with a large input step, the internal circuitry of the op amp reduces to a constant current source charging a capacitor. We say the op amp “slews” during this time. The slope of the ramp is called the “slew rate” (SR). Slewing further limits the speed of op amps. While for small-signal steps, the output response is determined by the closed-loop time constant, large-signal steps must face slewing prior to linear settling. Figure 8.39 compares the response of a non-slewing circuit with that of a slewing op amp, revealing the longer settling time in the latter case. It is important to understand that slewing is a nonlinear phenomenon. As suggested by the ! waveforms in Fig. 8.38(c), the points on the ramp section do not follow linear scaling (if x y, 6! then 2x 2y). The nonlinearity can also be observed by applying a large-signal sine wave to the circuit of Fig. 8.38(a) and gradually increasing the frequency (Fig. 8.40). At low frequencies, the op amp output “tracks” the sine wave because the maximum slope of the sine wave remains less than the op amp slew rate [Fig. R1=R2 sin !t, we observe that 8.40(a)]. Writing Vint = V0 sin !t and Voutt = V01 + 7Recall that in a linear system, if xt ! yt, then 2xt ! 2yt. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 403 (1) Sec. 8.4 Op Amp Nonidealities 403 Vin Without Slewing Vout t With Slewing t Figure 8.39 Output settling speed with and without slewing. Vout Vout Vin Vin t R1 R2 (a) (b) Vout Vin t1 t2 t (c) Figure 8.40 (a) Simple noninverting amplifier, (b) input and output waveforms without slewing, (c) input and output waveforms with slewing. dVout dt = V0 1 + R1 R2 ! cos !t: (8.91) The output therefore exhibits a maximum slope of V0!1 + R1=R2 (at its zero crossing points), and the op amp slew rate must exceed this value to avoid slewing. What happens if the op amp slew rate is insufficient? The output then fails to follow the sinusoidal shape while passing through zero, exhibiting the distorted behavior shown in Fig. 8.40(b). Note that the output tracks the input so long as the slope of the waveform does not exceed the op amp slew rate, e.g., between t1 and t2. Example 8.15 The internal circuitry of an op amp can be simplified to a 1-mA current source charging a 5-pF capacitor during large-signal operation. If an amplifier using this op amp produces a sinusoid with a peak amplitude of 0.5 V, determine the maximum frequency of operation that avoids slewing. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 404 (1) 404 Chap. 8 Operational Amplifier As A Black Box Solution The slew rate is given by I=C = 0:2 V/ns. Vp = 0:5 V, the maximum slope is equal to For an output given by Vout = Vp sin !t, where dVout dt jmax = Vp!: (8.92) Equating this to the slew rate, we have ! = 263:7 MHz: (8.93) That is, for frequencies above 63.7 MHz, the zero crossings of the output experience slewing. Exercise Plot the output waveform if the input frequency is 200 MHz. Equation (8.91) indicates that the onset of slewing depends on the closed-loop gain, 1 + R1=R2. To define the maximum sinusoidal frequency that remains free from slewing, it is com- mon to assume the worst case, namely, when the op amp produces its maximum allowable voltage swing without saturation. As exemplified by Fig. 8.41, the largest sinusoid permitted at the output is given by Vin1 Vin2 VDD VDD Vout 0 Vmax Vmin Figure 8.41 Maximum op amp output swings. Vout = Vmax , 2 Vmin sin !t + Vmax + 2 Vmin ; (8.94) where Vmax and Vmin denote the bounds on the output level without saturation. If the op amp provides a slew rate of SR, then the maximum frequency of the above sinusoid can be obtained by writing dVout dt jmax = SR (8.95) and hence !F P = SR Vmax , Vmin : (8.96) 2 Called the “full-power bandwidth,” !F P serves as a measure of the useful large-signal speed of the op amp. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 405 (1) Sec. 8.4 Op Amp Nonidealities 405 8.4.4 Finite Input and Output Impedances Actual op amps do not provide an infinite input impedance8 or a zero output impedance—the latter often creating limitations in the design. We analyze the effect of this nonideality on one circuit here. Consider the inverting amplifier shown in Fig. 8.42(a), assuming the op amp suffers from an output resistance, Rout. How should the circuit be analyzed? We return to the model in Fig. 8.1 and place Rout in series with the output voltage source [Fig. 8.42(b)]. We must solve the circuit in ,A0vX ,thevopurtes=eRncoueto, fwRe owurti.teRaecKoVgnLizfirnogmthvaint the current flowing through to vout through R2 and R1: Rout is equal to R1 R1 R2 X Vin Vout R2 X v in R out −A 0v X v out (a) (b) Figure 8.42 (a) Inverting amplifier, (b) effect of finite output resistance of op amp. vin + R1 + R2  ,A0vX , Rout vout = vout: (8.97) To construct another equation for vX , we view R1 and R2 as a voltage divider: vX = R2 R1 + R2 vout , vin + vin: (8.98) Substituting for vX in (8.97) thus yields vout vin = , R1 R2 1 + RARo02ut,+RRAo1u0t+ R1 R2 : (8.99) The additional terms ,Rout=R1 in the numerator and Rout=R2 in the denominator increase the gain error of the circuit. Example 8.16 An electrical engineering student purchases an op amp with A0 = 10; 000 and Rout = 1 and constructs the circuit fails to amplifier of Fig. 8.42(a) using R1 = 50 provide large voltage swings at the output and even Rth2ou=gh1R0 ou.t=URn1foarntudnRatoeulyt,=tRh2e remain much less than A0 in (8.99). Explain why. Solution For an output swing of, say, 2 V, the op amp may need to deliver a current as high as 40 mA to R1 (why?). Many op amps can provide only a small output current even though their small-signal output impedance is very low. 8Op amps employing MOS transistors at their input exhibit a very high input impedance at low frequencies. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 406 (1) 406 Chap. 8 Operational Amplifier As A Black Box Exercise If the op amp can deliver a current of 5 mA, what value of R1 is acceptable for output voltages as high as 1 V? 8.5 Design Examples Following our study of op amp applications in the previous sections, we now consider several examples of the design procedure for op amp circuits. We begin with simple examples and gradually proceed to more challenging problems. Example 8.17 Design an inverting amplifier with a nominal gain of 4, a gain error of 0:1, and an input impedance of at least 10 k . Determine the minimum op amp gain required here. Solution For R1 an input = 40 k impedance of 10 k for a nominal gain of , we choose the same value of R2 in Fig. 8.7(a), arriving 4. Under these conditions, Eq. (8.21) demands that at 1 A0 1 + R1 R2 0:1 (8.100) and hence A0 5000: (8.101) Exercise Repeat the above example for a nominal gain of 8 and compare the results. Example 8.18 Design a noninverting amplifier for the following specifications: closed-loop gain = 5, gain error = 1, closed-loop bandwidth = 50 MHz. Determine the required open-loop gain and bandwidth of the op amp. Assume the op amp has an input bias current of 0.2 A. Solution From Fig. 8.5 and Eq. (8.9), we have R1 R2 = 4: (8.102) The choice of R1 and R2 the op amp. For example, themselves depends on we may select R1 = 4 the k “driving and R2 capability” (output = 1 k and check resistance) of the gain error from (8.99) at the end. For a gain error of 1%, 1 A0 1 + R1 R2 1 (8.103) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 407 (1) Sec. 8.5 Design Examples and hence A0 500: Also, from (8.87), the open-loop bandwidth is given by !1 !1 !p;closed 1 + R!1pR;+c2loRse2dA0 1 + 1 + R1 R2 ,1A0 250 MHz 100 : Thus, the op amp must provide an open-loop bandwidth of at least 500 kHz. Exercise Repeat the above example for a gain error of 2 and compare the results. 407 (8.104) (8.105) (8.106) (8.107) Example 8.19 Design an integrator for a unity-gain frequency of 10 MHz and an input impedance of 20 k . If the op amp provides a slew rate of 0.1 V/ns, what is the largest peak-to-peak sinusoidal swing at the input at 1 MHz that produces an output free from slewing? Solution From (8.29), we have and, with R1 = 20 k , R1C12 1  10 MHz = 1 (8.108) C1 = 0:796 pF: (8.109) (In discrete design, such a small capacitor value may prove impractical.) For an input given by Vin = Vp cos !t, Vout = ,1 R1C1 Vp ! sin !t; with a maximum slope of dVout dt jmax = 1 R1C1 Vp: Equating this result to 0.1 V/ns gives Vp = 1:59 V: (8.110) (8.111) (8.112) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 408 (1) 408 Chap. 8 Operational Amplifier As A Black Box In other words, the input peak-to-peak swing at 1 MHz must remain below 3.18 V for the output to be free from slewing. Exercise How do the above results change if the op amp provides a slew rate of 0.5 V/ns? 8.6 Chapter Summary An op amp is a circuit that provides a high voltage gain and an output proportional to the difference between two inputs. Due to its high voltage gain, an op amp producing a moderate output swing requires only a very small input difference. The noninverting amplifier topology exhibits a nominal gain equal to one plus the ratio of two resistors. The circuit also suffers from a gain error that is inversely proportional to the gain of the op amp. The inverting amplifier configuration provides a nominal gain equal to the ratio of two resistors. Its gain error is the same as that of the noninverting configuration. With the noninverting input of the op amp tied to ground, the inverting input also remains close to the ground potential ans is thus called a “virtual ground.” If the feedback resistor in an inverting configuration is replaced with a capacitor, the circuit operates as an integrator. Integrator find wide application in analog filters and analog-todigital converters. If the input resistor in an inverting configuration is replaced with a capacitor, the circuit acts as a differentiator. Due to their higher noise, differentiators are less common than integrators. An inverting configuration using multiple input resistors tied to the virtual ground node can serve as a voltage adder. Placing a diode around an op amp leads to a precision rectifier, i.e., a circuit that can rectify very small input swings. Placing a bipolar device around an op amp provides a logarithmic function. Op amps suffer from various imperfections, including dc offsets and input bias currents. These effects impact the performance of various circuits, most notably, integrators. The speed of op amp circuits is limited by the bandwidth of the op amps. Also, for large signals, the op amp suffers from a finite slew rate, distorting the output waveform. Problems 1. Actual op amps exhibit “nonlinear” characteristics. For example, the voltage gain may be equal to 1000 for ,1 V jVoutj 2 V. Vout +1 V, 500 for 1 V jVoutj 2 V, and close to zero for (a) Plot the input/output characteristic of this op amp. (b) What is the largest input swing that the op amp can sense without producing “distortion” (i.e., nonlinearity)? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 409 (1) Sec. 8.6 Chapter Summary 409 2. An op amp exhibits the following nonlinear characteristic: Vout = tanh Vin1 , Vin2 : (8.113) Sketch this characteristic and determine the small-signal gain of the op amp in the vicinity of Vin1 , Vin2  0. 3. A noninverting amplifier employs an op amp having a nominal gain of 2000 to achieve a nominal closed-loop gain of 8. Determine the gain error. 4. A noninverting amplifier must provide a nominal gain of 4 with a gain error of 0:1. Com- pute the minimum required op amp gain. 5. Looking at Equation (8.11), an adventurous student decides that it is possible to achieve a zero gain error with a finite A0 if R2=R1 + (a) Suppose a nominal closed-loop gain of R2 is slightly 1 is required. adjusted from its nominal value. How should R2=R1 + R2 be chosen? (b) With the value obtained in (a), determine the gain error if A0 drops to 0:6A0. 6. A noninverting amplifier incorporates an op amp having an input impedance of Rin. Model- ing the op amp as shown in Fig. 8.43, determine the closed-loop gain and input impedance. Vin1 Vout R in A 0 (Vin1 − Vin2 ) Vin2 Figure 8.43 What happens if A0 ! 1? 7. A noninverting amplifier employs an op amp with a finite output impedance, Rout. Rep- resenting the op amp as depicted in Fig. 8.44, compute the closed-loop gain and output Vin1 Vin2 R out Vout A 0 (Vin1 − Vin2 ) Figure 8.44 impedance. What happens if A0 ! 1? 8. In the noninverting amplifier shown in Fig. 8.45, resistor R2 deviates from its nominal value Vin1 A0 Vout Vin Vin2 R1 R2 Figure 8.45 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 410 (1) 410 Chap. 8 Operational Amplifier As A Black Box by R. Calculate the gain error of the circuit if R=R2 1. 9. The input/output characteristic of an op amp can be approximated by the piecewise-linear behavior illustrated in Fig. 8.46, where the gain drops from A0 to 0:8A0 and eventually to Vout 0.8A 0 −4 mV −2 mV A0 +2 mV +4 mV Vin1 − Vin2 Figure 8.46 zero as jVin1 , Vin2j increases. Suppose this op amp is used in a noninverting amplifier with a nominal gain of 5. Plot the closed-loop input/output characteristic of the circuit. (Note that the closed-loop gain experiences much less variation; i.e., the closed-loop circuit is much more linear.) 10. A truck weighing station incorporates a sensor whose resistance varies linearly with the weight: RS = R0 + weight of each truck. 8.47). Also, Vin = 1 WSVu..pDHpeoetsreeermRRi0SneipstlahayecsogntahsitenanrootflvetaholeufesR,y2steainmptr,hodepeonfirontineoidnnavalesirtyttihnfeagccathomarn,paglinefideinrW(VFotihuget. Vin =1 V A0 Vout R1 RS Figure 8.47 divided by the change in W . ! ! 1 11. Calculate the closed-loop gain of the noninverting Verify that the result reduces to expected values if amplifier shown R1 0 or R3 in Fig. 0. 8.48 if A0 = . A0 Vout Vin R1 R3 R2 R4 Figure 8.48 12. An inverting amplifier must provide a nominal gain of 8 with a gain error of 0:2. Determine the minimum required op amp gain. 13. The op amp used in an inverting amplifier exhibits a finite input impedance, Rin. Modeling the op amp as shown in Fig. 8.43, determine the closed-loop gain and input impedance. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 411 (1) Sec. 8.6 Chapter Summary 411 14. An inverting amplifier employs an op amp having an output impedance of Rout. Modeling the op amp as depicted in Fig. 8.44, compute the closed-loop gain and output impedance. 15. An inverting amplifier must provide an input impedance of approximately 10 k and a nom- inal gain of 4. If the op amp exhibits an open-loop gain of 1000 and an output impedance of 1 k , determine the gain error. 16. An inverting amplifier is designed for a nominal gain of 8 and a gain error of 0:1 using an op amp that exhibits an output impedance of 2 k . If the input impedance of the circuit must be equal to approximately 1 k , calculate the required open-loop gain of the op amp. 1 ! ! 17. Assuming A0 = 8.49. Verify that , compute the closed-loop the result reduces to expected gain of the inverting amplifier values if R1 0 or R3 0. shown in Fig. R3 R1 R2 Vin R4 Vout Figure 8.49 1 18. Determine the closed-loop gain of the circuit depicted in Fig. 8.50 if A0 = . R1 R2 X A0 Vin Vout R4 R3 Figure 8.50 19. The integrator of Fig. 8.51 senses an input signal given by Vin = V0 sin !t. Determine the C1 R1 A0 Vin Vout Figure 8.51 output signal amplitude if A0 = 1. 1 20. The and integrator of Fig. 8.51 is R1C1 = 10 ns, compute used to amplify a sinusoidal input the frequency of the sinusoid. by a factor of 10. If A0 = 21. The integrator of Fig. and C1 are limited to 8.51 must provide a pole at no higher than 1 Hz. If the values of R1 10 k and 1 nF, respectively, determine the required gain of the op amp. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 412 (1) 412 Chap. 8 Operational Amplifier As A Black Box 22. Consider the integrator shown in Fig. 8.51 and suppose the op amp is modeled as shown in Fig. 8.43. Determine the transfer function Vout=Vin and compare the location of the pole with that given by Eq. (8.37). 23. The op amp used in the integrator of Fig. 8.51 exhibits a finite output impedance and is modeled as depicted in Fig. 8.44. Compute the transfer function Vout=Vin and compare the location of the pole with that given by Eq. (8.57). 24. The differentiator of Fig. 8.52 is used to amplify a sinusoidal input at a frequency of 1 MHz C1 Vin R1 A0 Vout Figure 8.52 by a factor of 5. If A0 = 1, determine the value of R1C1. 25. We wish to design the differentiator of Fig. 8.52 for a pole frequency of 100 MHz. If the values of R1 and C1 cannot be lower than 1 k and 1 nF, respectively, compute the required gain of the op amp. 26. Suppose the op amp in Fig. 8.52 exhibits a finite input impedance and is modeled as shown in Fig. 8.43. Determine the transfer function Vout=Vin and compare the result with Eq. (8.42). 27. The op amp used in the differentiator of Fig. 8.52 suffers from a finite output impedance and is modeled as depicted in Fig. 8.44. Compute the transfer function and compare the result with Eq. (8.42). j j 1 28. Calculate the transfer function of the component values reduces Vout=Vin circuit shown to unity at all in Fig. 8.53 if frequencies? A0 = . What choice of R2 C1 C2 Vin R1 A0 Vout Figure 8.53 29. RjVeopueta=tVPinroj btoleampp2r8oxifimAa0tely 1. Can unity? the resistors and capacitors be chosen so as to reduce 30. Consider the voltage adder shown in Fig. 8.54. Plot Vout as a function of time if V1 = RF R2 V1 X V2 A0 R1 Vout Figure 8.54 V0 sin !t and V2 = V0 sin3!t. Assume R1 = R2 and A0 = 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 413 (1) Sec. 8.6 Chapter Summary 413 31. The op amp in Fig. 8.54 suffers from a finite gain. Calculate Vout in terms of V1 and V2. 1 1 32. Due to a manufacturing error, a parasitic resistance RP has appeared in the adder of Fig. 8.55. Calculate Vout in terms of V1 and V2 for A0 = and A0 . (Note that RP can RF R2 V1 X V2 A0 R1 RP Vout Figure 8.55 also represent the input impedance of the op amp.) 33. The voltage adder of Fig. 8.54 employs an op amp having a finite output impedance, Rout. Using the op amp model depicted in Fig. 8.44, compute Vout in terms of V1 and V2. 34. Consider the voltage adder illustrated in Fig. 8.5R6,Fwhere RP is a parasitic resistance and the R2 V1 X V2 A0 R1 Vout RP Figure 8.56 op amp exhibits a finite input impedance. With the aid of the op amp model shown in Fig. 8.43, determine Vout in terms of V1 and V2. 35. Plot the current flowing through D1 in the precision rectifier of Fig. 8.22(b) as a function of time for a sinusoidal input. 36. Plot the current flowing through D1 in the precision rectifier of Fig. 8.23(a) as a function of time for a sinusoidal input. 37. Figure 8.57 shows a precision rectifier producing negative cycles. Plot VY , Vout, and the Vin Y X Vout R1 D1 Figure 8.57 current flowing through D1 as a function of time for a sinusoidal input. 38. Consider the precision rectifier depicted in Fig. 8.58, where a parasitic resistor RP has ap- peared in parallel with D1. Plot VX and VY as a function of time in response to a sinusoidal input. Use a constant-voltage model for the diode. 39. We wish to improve the speed of the rectifier shown in Fig. 8.22(b) by connecting a diode from node Y to ground. Explain how this can be accomplished. 40. Suppose Vin in Fig. 8.24 varies from ,1 V to +1 V. Sketch Vout and VX as a function of Vin if the op amp is ideal. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 414 (1) 414 Chap. 8 Operational Amplifier As A Black Box Figure 8.58 Vin Y X Vout D1 RP R1 41. Suppose the gain of the op amp in Fig. 8.24 is finite. Determine the input/output characteristic of the circuit. 42. A student attempts to construct a noninverting logarithmic amplifier as illustrated in Fig. 8.59. Describe the operation of this circuit. R1 X Vin Q1 Vout Figure 8.59 43. Determine the small-signal voltage gain of the logarithmic amplifier depicted in Fig. 8.24 by differentiating both sides of (8.66) with respect to Vin. Plot the magnitude of the gain as a function of Vin and explain why the circuit is said to provide a “compressive” characteristic. 44. The logarithmic amplifier of Fig. 8.24 must “map” an input range of 1 V to 10 V to an output range of ,1 V to ,1:5 V. (a) Determine the required values of IS and R1. (b) Calculate the small-signal voltage gain at the two ends of the range. 45. The circuit illustrated in Fig. 8.60 can be considered a “true” square-root amplifier. Deter- R1 X Vin VTH M1 Vout Figure 8.60 mwiitnherVesopuetcitntoteVrmins. of Vin and compute the small-signal gain by differentiating the result 46. Calculate Vout in terms of Vin for the circuit shown in Fig. 8.61. 47. In the noninverting amplifier of Fig. 8.62, the op amp offset is represented by a voltage source in series with the inverting input. Calculate Vout. 48. Suppose each op amp in Fig. 8.28 suffers from an input offset of 3 mV. Determine the maximum offset error in Vout if each amplifier is designed for a gain of 10. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 415 (1) Sec. 8.6 Chapter Summary 415 Figure 8.61 R1 X Vin M1 Vout A0 Vout Vin R1 VOS R2 Figure 8.62 49. For the inverting amplifier illustrated in Fig. 8.63, calculate Vout if the op amp exhibits an R1 R2 A0 Vin Vout Figure 8.63 input offset of Vos. Assume A0 = 1. 50. The integrator of Fig. 8.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV. Determine the required values of R1 and R2 if C1  100 pF. 51. Explain why dc offsets are not considered a serious issue in differentiators. 52. Explain the effect of op amp offset on the output of a logarithmic amplifier. 53. Suppose the input Calculate Vout. bias currents in Fig. 8.31 incur a small offset, i.e., IB1 = IB2 + I. 54. Repeat Problem 53 for the circuit shown in Fig. 8.33. What is the maximum allowable value jj of R1 R2 if the output error due to this mismatch must remain below a certain value, V ? 55. A noninverting amplifier must provide a bandwidth of 100 MHz with a nominal gain of 4. Determine which one of the following op amp specifications are adequate: (a) (a) AA00 = = 1500000, f, f11==15M0HHzz.. 56. An inverting amplifier incorporates an op amp whose frequency response is given by Eq. (8.84). Determine the transfer function of the closed-loop circuit and compute the bandwidth. 57. Figure 8.64 shows an integrator employing an op amp whose frequency response is given by As = 1 +A0!s0 : (8.114) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 416 (1) 416 Chap. 8 Operational Amplifier As A Black Box Determine 1=R1C1. the transfer function of the overall integrator. Simplify the result if !0 C1 R1 Vin A (s Vout ( Figure 8.64 58. A noninverting amplifier with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0.5 V. If the op amp provides a slew rate of 1 V/ns, what is the highest input frequency for which no slewing occurs? 59. The unity-gain buffer of Fig. 8.3 must be designed to drive a 100 load with a gain error of 0:5. Determine the required op amp gain if the op amp has an output resistance of 1 k . Design Problems 60. Design a noninverting amplifier with a nominal gain of 4, a gain error of 0:2, and a total resistance of 20 k . Assume the op amp has a finite gain but is otherwise ideal. 61. Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 8 and a gain error of 0:1. Assume Rout = 100 . 62. Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz. Assume the largest available capacitor is 50 pF. 63. With a finite op amp gain, the step response of an integrator is a slow exponential rather than an ideal ramp. Design an integrator whose step response approximates V t = t with an error less than 0:1 for the range 0 V t V0 (Fig. 8.65). Assume = 10 V=s, V0 = 1 Ideal Ramp V0 ∆V ∆V = 0.1% V0 Vout t Figure 8.65 V, and the capacitor must remain below 20 pF. 64. A voltage adder must realize the following and 0:5 2 = ,1:5. Design the circuit and the input impedance seen if the by V1 function: Vout = 1V1+ worst-case or V2 must error in 1 or exceed 10 k . 2V2, where 1 = ,0:5 2 must remain below 65. Design a logarithmic amplifier that “compresses” an input range of 0:1 V 2 V to an output range of ,0:5 V , 1 V . 66. Can a logarithmic amplifier be designed to have a small-signal gain (dVout=dVin) of 2 at Vin = 1 V and 0.2 at Vin = 2 V? Assume the gain of the op amp is sufficiently high. SPICE Problems BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 417 (1) Sec. 8.6 Chapter Summary 417 67. Assuming an op amp gain of 1000 and IS = 10,17 A for D1, plot the input/output charac- teristic of the precision rectifier shown in Fig. 8.66. Vin Y Vout 1 kΩ D1 Figure 8.66 68. Repeat Problem 67 but assuming that the op amp suffers from an output resistance of 1 k . 69. In the circuit of Fig. 8.67, each op amp provides a gain of 500. Apply a 10-MHz sinusoid at the input and plot the output as a function of time. What is the error in the output amplitude with respect to the input amplitude? 1 kΩ 10 pF 1 kΩ 10 pF V in Vout Figure 8.67 70. Using ac analysis in SPICE, plot the frequency response of the circuit depicted in Fig. 8.68. 10 kΩ 1 kΩ 10 pF 1 kΩ 10 pF V in Vout Figure 8.68 71. Tsthageea.rrAasnsguemmeenISt s;Qh1ow=n5inFi1g0.,81.669Ain, caonrdpora=te1s0a0n.op amp to “linearize” a common-emitter VCC = 2.5 V 500Ω Vout Q1 Vin X 100Ω Figure 8.69  (a) Explain why the small-signal gain of the circuit approaches RC=RE if the gain of the op amp is very high. (Hint: VX Vin.) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 418 (1) 418 Chap. 8 Operational Amplifier As A Black Box (b) Plot the input/output characteristic of the circuit for 0:1 V Vin 0:2 V and an op amp gain of 100. (c) Subtract Vout = 5Vin (e.g., using a voltage-dependent voltage source) from the above characteristic and determine the maximum error. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 419 (1) 9 Cascode Stages and Current Mirrors Following our study of basic bipolar and MOS amplifiers in previous chapters, we deal with two other important building blocks in this chapter. The “cascode”1 stage is a modified version of common-emitter or common-source topologies and proves useful in high-performance circuit design, and the “current mirror” is an interesting and versatile technique employed extensively in integrated circuits. Our study includes both bipolar and MOS implementations of each building block. Shown below is the outline of the chapter. Cascode Stages Cacode as Current Source Cacode as Amplifier Current Mirrors Bipolar Mirrors MOS Mirrors 9.1 Cascode Stage 9.1.1 Cascode as a Current Source Recall from Chapters 5 and 7 that the use of current-source loads can markedly increase the voltage gain of amplifiers. We also know that a single transistor can operate as a current source but its output impedance is limited due to the Early effect (in bipolar devices) or channel-length modulation (in MOSFETs). How can we increase the output impedance of a transistor that acts as a current source? An important observation made in Chapters 5 and 7 forms the foundation for our study here: emitter or source degeneration “boosts” the impedance seen looking into the collector or drain, respectively. For the circuits shown in Fig. 9.1, we have R out1 R out2 Vb Q1 RE Vb M1 RS Figure 9.1 Output impedance of degenerated bipolar and MOS devices. 1Coined in the vacuum-tube era, the term “cascode” is believed to be an abbreviation of “cascaded triodes.” 419 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 420 (1) 420 Chap. 9 Cascode Stages and Current Mirrors Rout1 = 1 + gmREjjr rO + REjjr (9.1) = 1 + gmrOREjjr + rO (9.2) Rout2 = 1 + gmRSrO + RS (9.3) = 1 + gmrORS + rO; (9.4) observing that RE or RS can be increased to raise the output resistance. Unfortunately, how- ever, the voltage drop across the degeneration resistor also increases proportionally, consuming voltage headroom and ultimately limiting the voltage swings provided by the circuit using such a current source. For example, if RE sustains 300 mV and Q1 requires a minimum collector- emitter voltage of 500 mV, then the degenerated current source “‘consumes” a headroom of 800 mV. Bipolar Cascode In order to relax the trade-off between the output impedance and the volt- age headroom, we can replace the degeneration resistor with a transistor. Depicted in Fig. 9.2(a) for the bipolar version, the idea is to introduce a high small-signal resistance (= rO2) in the R out R out Vb1 Q1 Vb2 Q2 Vb Q1 r O2 (a) (b) Figure 9.2 (a) Cascode bipolar current source, (b) equivalent circuit. emitter of Q1 while consuming a headroom independent of the current. In this case, Q2 requires a headroom of approximately 0.4 V to remain soft saturation. This configuration is called the  “cascode” stage.2 To the cascode transistor eamndphQa2siztheethdaetgeQn1eraantidonQt2rapnlsaiystdoirs. tNinocttelythdaitfIfCer1ent roles here, IC2 if 1 we call 1. Q1 Let us compute the output impedance of the bipolar cascode of Fig. 9.2(a). Since the base- teomriOtte2r[vFoiglt.a9g.e2o(bf)Q].2Inisacnoanlsotgayntw, tihthistthreanrseissitsotrivseimlyp-dlyegoepneerraatteesdacsoausnmtearlpl-asritginnaFl irge.si9s.t1a,nwceeehqauvael Rout = 1 + gm1rO2jjr1 rO1 + rO2jjr1: (9.5) Since typically gm1rO2jjr1 1, Rout  1 + gm1rO1rO2jjr1 (9.6)  gm1rO1rO2jjr1: (9.7) Note, however, that rO cannot generally be assumed much greater than r. Example 9.1 If Q1 and resistance. AQs2suinmeFig.=9.120(a0)aanrdeVbAia=sed5 at V a collector current for both transistors. of 1 mA, determine the output 2Or simply the “cascode.” BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 421 (1) Sec. 9.1 Cascode Stage 421 Solution Since Q1 by noting and that Qgm2 are identical and = IC=VT , rO = biased VA=IC at the same , and r = current level, VT =IC: Eq. (9.7) can be simplified Rout  IC1 VT  VA1 IC1  VA2 VIAC22 IC2  + VT ICV1T IC1 (9.8)  1 IC1  VA VT  VAVT VA + VT ; (9.9) where IC = IC1 = IC2 and VA = VA1 = VA2. At room temperature, VT  26 mV and hence Rout  328:9 k : (9.10) By comparison, the output resistance of i.e., “cascoding” has boosted Rout by a Qfa1ctworitohfn6o6dheegreen. eNraottieonthwatoruOld2 be equal and r1 to rO1 = 5 k ; are comparable in this example. Exercise What Early voltage is required for an output resistance of 500 k ? It is interesting to note that if rO2 becomes much greater than r1, then Rout1 approaches Rout;max  gm1rO1r1  1rO1: (9.11) (9.12) This is the maximum output impedance provided by a bipolar cascode. After all, even with trhOe2re=by1lim(Fitiign.g9R.3o)u[totroRE1r=O11. in (9.1)], r1 still appears from the emitter of Q1 to ac ground, R out Q1 r π1 Ideal Figure 9.3 Cascode topology using an ideal current source. Example 9.2 Suppose in Example 9.1, the Early voltage of Q2 is equal to 50 V.3 Compare the resulting output impedance of the cascode with the upper bound given by Eq. (9.12). 3In integrated circuits, all bipolar transistors fabricated on the same wafer exhibit the same Early voltage. This example applies to discrete implementations. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 422 (1) 422 Chap. 9 Cascode Stages and Current Mirrors Solution Since gm1 = 26 ,1, r1 = 2:6 k , rO1 = 5 k , and rO2 = 50 k , we have Rout  gm1rO1rO1jjr1  475 k : The upper bound is equal to 500 k , about 5 higher. (9.13) (9.14) Exercise Repeat the above example if the Early voltage of Q1 is 10 V. Example 9.3 We wish to increase the output resistance of the bipolar cascode of Fig. 9.2(a) by a factor of two through the use of resistive degeneration in the emitter the degeneration resistor if Q1 and Q2 are identical. of Q2. Determine the required value of Solution As illustrated in Fig. 9.4, we replace Q2 and RE with their equivalent resistance from (9.1): R out R out Vb1 Q1 R outA Vb Q1 Vb2 Q2 RE R outA Figure 9.4 . RoutA = 1 + gm2REjjr2 rO2 + REjjr2: (9.15) It follows from (9.7) that Rout  gm1rO1RoutAjjr1: (9.16) We wish this value to be twice that given by (9.7): RoutAjjr1 = 2rO2jjr1: (9.17) That is, RoutA = 2rO2r1 r1 , rO2 : (9.18) In practice, r1 is typically less than rO2, and no positive value of RoutA exists! In other words, it is impossible to double the output impedance of the cascode by emitter degeneration. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 423 (1) Sec. 9.1 Cascode Stage 423 Exercise Is there a solution if the output impedance must increase by a factor of 1.5? What does the above result mean? Comparing the output resistances obtained in Examples 9.1 and 9.2, we recognize that even identical transistors yield an Rout (= 328:9 k ) that is not far from the upper bound (= 500 k ). More specifically, the ratio of (9.7) and (9.12) is equal to rO2=rO2 + r1, a value greater than 0.5 if rO2 r1. Q2Faosrtchoemdepgleetneenreastsio, nFidge.v9i.c5e.shTohwe souatppnutpimcapsecdoadnec, ewihsegreivQen1bsyer(v9e.5s)a.s the cascode device and VCC Vb2 Q2 Vb1 Q1 Figure 9.5 PNP cascode current source. R out While we have arrived at the cascode as an extreme case of emitter degeneration, it is also possible to impedance view the evolution as illustrated in of rO2, we “stack” Q1 on top of it Fig. 9.6. That to raise Rout. is, since Q2 provides only an output R out g m1 r O1 ( r O2 r π1 ) R out = r O2 Vb1 Q1 Vb2 Q2 Vb2 Q2 Figure 9.6 Evolution of cascode topology viewed as stacking Q1 atop Q2. Example 9.4 Explain why the topologies depicted in Fig. 9.7 are not cascodes. R out Vb1 Q1 Vb1 X Vb2 Q2 (a) R out Q1 1 g m2 r O2 VCC Vb1 Q2 X Vb2 Q1 Vb2 R out (b) Figure 9.7 VCC 1 g m2 r O2 Q1 R out BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 424 (1) 424 Chap. 9 Cascode Stages and Current Mirrors Solution   jj Unlike of Q2. the cascode of Transistor Q2 Fig. now 9.2(a), the circuits of Fig. 9.7 connect the emitter of Q1 to the emitter operates as a diode-connected device (rather than a current source), tthheeroeubtypuptreimsepnetidnagncane,iRmopuetd, aisnctheeoreffo1r=egcmo2nsidreOr2ab(lryatlhoewretrh:an rO2) at node X. Given by (9.1), Rout = 1 + gm1 1 gm2 jjrO2jjr1 rO1 + 1 gm2 jjrO2jjr1 : (9.19) In fact, since 1=gm2 rO2 , r1 and Rout sin ce1g+m1ggmm21 g mr2O(1w+hyg?m)1,2  2rO1: (9.20) (9.21) The same observations apply to the topology of Fig. 9.7(b). Exercise Estimate the output impedance for a collector bias current of 1 mA and VA = 8 V. MOS Cascodes The similarity of Eqs. (9.1) and (9.3) for degenerated stages suggests that cascoding can also be realized with MOSFETs so as to increase the output impedance of a current source. Illustrated in Fig. 9.8, the idea is to replace the degeneration resistor with a MOS current R out Vb1 M1 X Vb2 M2 R out Vb M1 r O2 Figure 9.8 MOS cascode current source and its equivalent. source, thus presenting a small-signal resistance of rO2 from X to ground. Equation (9.3) can now be written as Rout = 1 + gm1rO2rO1 + rO2  gm1rO1rO2; (9.22) (9.23) where it is assumed gm1rO1rO2 rO1, rO2. Equation (9.23) is an extremely important result, implying that the output impedance is pro- portional to the intrinsic gain of the cascode device. Example 9.5 Design an NMOS cascode for an output impedance of 500 k and a current of 0.5 mA. For simplicity, assume 100 A=V2 and  =M01:1anVd,M1.2 in Fig. 9.8 are identical (they need not be). Assume nCox = BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 425 (1) Sec. 9.1 Cascode Stage 425 Solution We must determine W=L for both transistors such that gm1rO1rO2 = 500 k : Since rO1 = rO2 = ID,1 = 20 k , we require that gm1 = 800 ,1 and hence r 2nCox W L ID = 1 800 : It follows that We should also note that gm1rO1 = 25 W L = 15:6: 1. (9.24) (9.25) (9.26) Exercise What is the output resistance if W=L = 32? Invoking the alternative view depicted in Fig. 9.6 for the MOS counterpart (Fig. 9.9), we R out g m1 r O1 r O2 R out = r O2 Vb2 M2 Vb1 M1 X Vb2 M2 Figure 9.9 MOS cascode viewed as stack of M1 atop of M2. recognize that stacking a MOSFET on top of a current source “boosts” the impedance by a factor topToofhiRignsmtoiuos2trfb;Obceio2pcna(=uttrhsaeestirinnbOteM1rti,wnOwseSiehcnedgrebeaviaipinscoeiolnsaf,rtthahneeadnlcadMatstreOcro,SdaRecreaotusricatn;onfiMdsniOeiststSe:oir(=n)a.ttThglomehwif1sorforOrmeb1qsereurOr,ev2nraacitiniiseocisnnr)eg.raersvOees2awelsviteahnntnuionatlbelyroeulsentaidnd.g4s Figure 9.10 illustrates a PMOS cascode. The output resistance is given by (9.22). Example 9.6 During manufacturing, a large parasitic resistor, Rp, has appeared in a cascode as shown in Fig. 9.11. Determine the output resistance. Solution We observe that Rp is in parallel with rO1. It is therefore possible to rewrite (9.23) as Rout = gm1rO1jjRprO2: (9.27) 4In reality, other second-order effects limit the output impedance of MOS cascodes. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 426 (1) 426 Chap. 9 Cascode Stages and Current Mirrors Vb2 Vb1 Figure 9.10 PMOS cascode current source. VDD M2 X M1 R out M1 Vb1 R out RP Vb2 M2 Figure 9.11 sIftitgumti1ngrOrO1j1jjRjRpp is not much for rO1: greater than unity, we return to the original equation, (9.22), sub- Rout = 1 + gm1rO2rO1jjRp + rO2: (9.28) Exercise What value of Rp degrades the output impedance by a factor of two? 9.1.2 Cascode as an Amplifier In addition to providing a high output impedance as a current source, the cascode topology can also serve as a high-gain amplifier. In fact, the output impedance and the gain of amplifiers are closely related. For our study below, we need to understand the concept of the transconductance for circuits. In Chapters 4 and 6, we defined the transconductance of a transistor as the change in the collector or drain current divided by the change in the base-emitter or gate-source voltage. This concept can be generalized to circuits as well. As illustrated in Fig. 9.12, the output voltage is set to zero i out Circuit v in ac GND Figure 9.12 Computation of transconductance for a circuit. be shorting the output node to ground, and the “short-circuit transconductance” of the circuit is BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 427 (1) Sec. 9.1 Cascode Stage 427 defined as Gm = iout vin jvout=0: (9.29) The transconductance signifies the “strength” of a circuit in converting the input voltage to a current.5 Note the direction of iout in Fig. 9.12. Example 9.7 Calculate the transconductance of the CS stage shown in Fig. 9.13(a). VDD VDD RD v out v in M1 RD i out v in M1 ac GND (a) (b) Figure 9.13 Solution As depicted in Fig. 9.13(b), we short the output node to ac ground and, noting that RD carries no current (why?), write Gm = iout vin = iD1 vGS1 = gm1: (9.30) (9.31) (9.32) Thus, in this case, the transconductance of the circuit is equal to that of the transistor. Exercise How does Gm change if the width and bias current of the transistor are doubles? Lemma The voltage gain of a linear circuit can be expressed as Av = ,GmRout; (9.33) where Rout denotes the output resistance of the circuit (with the input voltage set to zero). Proof We know that a linear circuit can be replaced with its Norton equivalent [Fig. 9.14(a)]. Norton’s theorem states that iout is obtained by shorting the output to ground vout = 0 and v = 0 5While omitted for simplicity in Chapters 4 and 6, the condition out is also required for the transconductance of transistors. That is, the collector or drain must by shorted to ac ground. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 428 (1) 428 Chap. 9 Cascode Stages and Current Mirrors Vout Vout v in i out R out (a) i out v in (b) Figure 9.14 (a) Norton equivalent of a circuit, (b) computation of short-circuit output current . computing the short-circuit current [Fig. 9.14(b)]. We also relate iout to vin by the transconductance of the circuit, Gm = iout=vin. Thus, in Fig. 9.14(a), vout = ,ioutRout = ,GmvinRout (9.34) (9.35) and hence vout vin = ,GmRout: (9.36) Example 9.8 Determine the voltage gain of the common-emitter stage shown in Fig. 9.15(a). VCC I1 v out v in Q1 i out v in Q1 ac GND iX Q1 vX (a) (b) (c) Figure 9.15 Solution To calculate the short-circuit transconductance of the circuit, we place an ac short from the output to ground and find the current through collector current of Q1, gm1vin, i.e., it [Fig. 9.15(b)]. In this case, iout is simply equal to the Gm = iout vin = gm1: (9.37) (9.38) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 429 (1) Sec. 9.1 Cascode Stage 429 Note that rO does not carry a current in this test (why?). Next, we obtain the output resistance as depicted in Fig. 9.15(c): Rout = vX iX = rO1: (9.39) (9.40) It follows that Av = ,GmRout = ,gm1rO1: (9.41) (9.42) Exercise Suppose the transistor is degenerated by an emitter resistor equal to RE. The transconductance falls but the ouput resistance rises. Does the voltage gain increase or decrease? The above lemma serves as an alternative method of gain calculation. It also indicates that the voltage gain of a circuit can be increased by raising the output impedance, as in cascodes. Bipolar Cascode Amplifier Recall from Chapter 4 that to maximize the voltage gain of a common-emitter stage, the collector load impedance must be maximized. In the limit, an ideal current source serving as the load [Fig. 9.16(a)] yields a voltage gain of I1 v in VCC g m1v in Q1 v out r O1 VCC I1 v out Vb1 Q2 v in Q1 (a) (b) Figure 9.16 (a) Flow of output current generated by a CE stage through rO1, (b) use of cascode to increase the output impedance. Av = ,gm1rO1 = , VA VT : (9.43) (9.44) In an tohuistpcuatsev,otlhtaegsemeaqlul-asligtona,l cgumr1revnint,rgOm1.1vin, produced by Q1 flows through rO1, thus generating Now, suppose we stack a transistor on top of Q1 as shown in Fig. 9.16(b). We know from Section 9.1.1 that the circuit achieves a high output impedance and, from the above lemma, a voltage gain higher than that of a CE stage. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 430 (1) 430 Chap. 9 Cascode Stages and Current Mirrors Let us determine the voltage gain of the bipolar cascode with the aid of the above lemma. As shown in Fig. 9.17(a), the short-circuit transconductance is equal to iout=vin. As a common- i out i out Q2 ac GND Q1 v in g m1v in Q2 X Q1 v in ac r O2 GND g m1v in r O1 (a) (b) Figure 9.17 (a) Short-circuit output current of a cascode, (b) detailed view of (a). emitter Q2 and stage, hence Q1 still produces a through the output collector short: current of gm1vin , which subsequently flows through iout = gm1vin: (9.45) That is, Gm = gm1: (9.46) The reader may view (9.46) dubiously. After all, as shown in Fig. 9.17(b), the collector current jj otchhoafevlQlrieen1cfgotmorareunvsvitoemlsrtippaflygeidtetsabhneaocttfweoQeonef2lnyar1arO=eng1eemaqg2nulidaglitr,bhOtlehe2ii.sfmrDatpriceavtdniiodasniinnsctgooefrgsgmecmea1nn1vvilbnoienobkvieisitnew“gwleoieensdntto”athstihnisaeridemOmi1op.idetetSde-aircnnooccnefenQtaehnc2etd.ebWdraOesde1em,vawuincsdeet have iout = gm1vin rO1jjr2 rO1jjr2 + 1 gm2 jjrO2 : (9.47) For typical transistors, 1=gm2 rO2, rO1, and hence iout  gm1vin: (9.48) That is, the approximation Gm = gm1 is reasonable. To obtain the overall voltage gain, we write from (9.33) and (9.5), Av = ,GmRout (9.49) = ,gm1 f 1 + gm2rO1jjr2 rO2 + rO1jjr2g (9.50)  ,gm1 gm2rO1jjr2rO2 + rO1jjr2 : (9.51) Also, since Q1 and Q2 carry approximately equal bias currents, gm1  gm2 and rO1  rO2: Av = ,gm1rO1 gm1rO1jjr2 + 1 (9.52)  ,gm1rO1gm1rO1jjr2: (9.53) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 431 (1) Sec. 9.1 Cascode Stage 431 Compared to the simple CE stage of Fig. 9.16(a), the cascode amplifier exhibits a gain that is higher by a greater than factor of 1=gm1. gm1rO1jjr2—a relatively large value because rO1 and r2 are much Example 9.9 The bipolar cascode of Fig. 9.16(b) is biased at a current of 1 mA. If VA = 5 V and = 100 for both transistors, determine the voltage gain. Assume the load is an ideal current source. Solution We have gm1 = 26 ,1, r1  r2  2600 , rO1  rO2 = 5 k . Thus, gm1rO1jjr2 = 65:8 (9.54) and from (9.53), jAvj = 12; 654: (9.55) Cascoding thus raises the voltage gain by a factor of 65.8. Exercise What Early voltage gives a gain of 5,000? It is possible to view the cascode amplifier as a common-emitter stage followed by a common- base base stage. Illustrated in Fig. 9.18, the idea transistor that senses the small-signal ciusrtroenctonpsroiddeurctehdebcyasQco1d. eTdheisvipceer,sQpe2c,tiavseamcaoympmroovne- useful in some cases. VCC I1 v out Q2 Vb CB Stage v in Q 1 CE Stage Figure 9.18 Cascode amplifier as a cascade of a CE stage and a CB stage. The high voltage gain of the cascode topology makes it attractive for many applications. But, in the circuit of Fig. 9.16(b), the load is assumed to be an ideal current source. An actual current source lowers the impedance seen at the output node and hence the voltage gain. For example, the circuit illustrated in Fig. 9.19(a) suffers from a low gain because the pnp current source introduces an impedance of only rO3 from the output node to ac ground, dropping the output impedance to Rout = rO3jj f 1 + gm2rO1jjr2 rO2 + rO1jjr2g (9.56)  rO3jj gm2rO2rO1jjr2 + rO1jjr2 : (9.57) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 432 (1) 432 Chap. 9 Cascode Stages and Current Mirrors Vb2 Vb1 v in VCC Q3 v out Q2 Q1 Vb1 v in VCC r O3 Q2 R out Q1 Vb3 Vb2 v out Vb1 v in VCC Q4 Q3 R op R on Q2 Q1 (a) (b) Figure 9.19 (a) Cascode with a simple current-source load, (b) use of cascode in the load to raise the voltage gain. How should we realize the load current source to maintain a high gain? We know from Section 9.1.1 that cascoding also raises the output impedance of current sources, postulating that the circuit of Fig. 9.5 is a good candidate and arriving at the stage depicted in Fig. 9.19(b). The output impedance is now given by the parallel combination of those of the npn and pnp cascodes, Ron and Rop, respectively. Using (9.7), we have Ron  gm2rO2rO1jjr2 Rop  gm3rO3rO4jjr3: (9.58) (9.59) Note that, since npn and be equal to rO3 (= rO4) Recognizing that the equal to gm1 (why?), we pnp devices may display different Early voltages, . short-circuit transconductance, Gm, of the stage express the voltage gain as rO1 (= rO2) may not is still approximately Av = ,gm1RonjjRop (9.60)  ,gm1 f gm2rO2rO1jjr2 jj gm3rO3rO4jjr3 g : (9.61) This result represents the highest voltage gain that can be obtained in a cascode stage. For com- parable values of Ron and Rop, this gain is about half of that expressed by (9.53). Example 9.10 Suppose the circuit of Example 9.9 incorporates a cascode load using pnp transistors with VA = 4 V and = 50. What is the voltage gain? Solution The load transistors carry a collector current of approximately 1 mA. Thus, Rop = gm3rO3rO4jjr3 = 151 k (9.62) (9.63) and Ron = 329 k : (9.64) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 433 (1) Sec. 9.1 Cascode Stage 433 It follows that jAvj = gm1RonjjRop = 3; 981: (9.65) (9.66) Compared to the ideal current source case, the gain has fallen by approximately a factor of 3 because the pnp devices suffer from a lower Early voltage and . Exercise Repeat the above example for a collector bias current of 0.5 mA. It is important to take a step back and appreciate our analysis techniques. The cascode of Fig. 9.19(b) proves quite formidable if we attempt to replace each transistor with its small-signal model and solve the resulting circuit. Our gradual approach to constructing this stage reveals the role of each device, allowing straightforward calculation of the output impedance. Moreover, the lemma illustrated in Fig. 9.14 utilizes our knowledge of the output impedance to quickly provide the voltage gain of the stage. CMOS Cascode Amplifier The foregoing analysis of the bipolar cascode amplifier can readily be extended to the CMOS counterpart. Depicted in Fig. 9.20(a) with an ideal current-source VDD Vb2 M4 VDD I1 v out Vb1 v in M2 X M1 Vb2 R op R on M3 v out Vb1 v in M2 X M1 (a) (b) Figure 9.20 (a) MOS cascode amplifier, (b) realization of load by a PMOS cascode. load, this stage also provides a short-circuit transconductance Gm  gm1 if 1=gm2 output resistance is given by (9.22), yielding a voltage gain of Av = ,GmRout  ,gm1 1 + gm2rO2rO1 + rO2  ,gm1rO1gm2rO2: rO1. The (9.67) (9.68) (9.69) In other words, compared to a simple common-source stage, the voltage gain has risen by a factor of gm2rO2 (the intrinsic gain of the cascode device). Since and r are infinite for MOS devices (at low frequencies), we can also utilize (9.53) to arrive at (9.69). Note, however, that M1 and BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 434 (1) 434 Chap. 9 Cascode Stages and Current Mirrors M2 need not exhibit equal transconductances or output resistances (their widths and lengths need not be the same) even though they carry equal currents (why?). As with the bipolar counterpart, the MOS cascode amplifier must incorporate a cascode PMOS current source so as to maintain a high voltage gain. Illustrated in Fig. 9.20(b), the circuit exhibits the following output impedance components: Ron  gm2rO2rO1 Rop  gm3rO3rO4: (9.70) (9.71) The voltage gain is therefore equal to Av  ,gm1 gm2rO2rO1jjgm3rO3rO4 : (9.72) Example 9.11 The cascode amplifier of Fig. 9.20(b) incorporates the following device parameters: WpC=oLx1=;25=0 3A0=, VW2,=Ln=3;40=:1 V40,,1IaDn1d = p = 0:=15IVD,41=, de0t:e5rmminAe. If nCox = 100 the voltage gain. A=V2, Solution s With the particular choice rO3 = rO4. We have of device parameters here, gm1 = gm2, rO1 = rO2, gm3 = gm4, and gm1;2 = 2nCox W L ID1;2 1;2 (9.73) = 577 ,1 (9.74) and gm3;4 = 707 ,1: (9.75) Also, rO1;2 = 1 nID1;2 = 20 k (9.76) (9.77) and rO3;4 = 13:3 k : Equations (9.70) and (9.71) thus respectively give Ron  693 k Rop  250 k and Av = ,gm1RonjjRop  ,318: (9.78) (9.79) (9.80) (9.81) (9.82) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 435 (1) Sec. 9.2 Current Mirrors 435 Exercise Explain why a lower bias current results in a higher output impedance in the above example. Calculate the output impedance for a drain current of 0.25 mA. 9.2 Current Mirrors 9.2.1 Initial Thoughts The biasing techniques studied for bipolar and MOS amplifiers in Chapters 4 and 6 prove inadequate for high-performance microelectronic circuits. For example, the bias current of CE and CS stages is a function of the supply voltage—a serious issue because in practice, this voltage experiences some variation. The rechargeable battery in a cellphone or laptop computer, for example, gradually loses voltage as it is discharged, thereby mandating that the circuits operate properly across a range of supply voltages. Another critical issue in biasing relates to ambient temperature variations. A cellphone must , maintain its performance at 20 C in Finland and +50 C in Saudi Arabia. To understand how temperature affects the biasing, consider the bipolar current source shown in Fig. 9.21(a), where VCC R1 I1 Q1 R2 VBE VDD R1 I1 M1 R2 VGS (a) (b) Figure 9.21 Impractical biasing of (a) bipolar and (b) MOS current sources. R1 and R2 divide VCC down to the required VBE. That is, for a desired current I1, we have R2 R1 + R2 VCC = VT ln I1 IS ; (9.83) where the base current is neglected. But, what happens if the temperature varies? The left-hand side remains constant if the resistors are made of the same material and hence vary by the same percentage. The right-hand side, however, contains two temperature-dependent parameters: VT = kT =q and IS. Thus, even if the base-emitter voltage remains constant with temperature, I1 does not. A similar situation arises in CMOS circuits. Illustrated in Fig. 9.21(b), a MOS current source biased by means of a resistive divider suffers from dependence on VDD and temperature. Here, we can write I1 = = 1 2 1 2 nCox nCox W L W L VGS , VTH2 R2 R1 + R2 VDD , VT H 2 : (9.84) (9.85) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 436 (1) 436 Chap. 9 Cascode Stages and Current Mirrors Since both if VGS is. the mobility and the threshold voltage vary with temperature, I1 is not constant even In summary, the typical biasing schemes introduced in Chapters 4 and 6 fail to establish a constant collector or drain current if the supply voltage or the ambient temperature are subject to change. Fortunately, an elegant method of creating supply- and temperature-independent volt- ages and currents exists and appears in almost all microelectronic systems. Called the “bandgap reference circuit” and employing several tens of devices, this scheme is studied in more advanced books [1]. The bandgap circuit by itself does not solve all of our problems! An integrated circuit may incorporate hundreds of current sources, e.g., as the load impedance of CE or CS stages to achieve a high gain. Unfortunately, the complexity of the bandgap prohibits its use for each current source in a large integrated circuit. Let us summarize our thoughts thus far. In order to avoid supply and temperature dependence, a bandgap reference can provide a “golden current” while requiring a few tens of devices. We must therefore seek a method of “copying” the golden current without duplicating the entire bandgap circuitry. Current mirrors serve this purpose. Figure 9.22 conceptually illustrates our goal here. The golden current generated by a bandgap reference is “read” by the current mirror and a copy having the same characteristics as those of IREF is produced. For example, Icopy = IREF or 2IREF . VCC I REF I copy Current Mirror Figure 9.22 Concept of current mirror. 9.2.2 Bipolar Current Mirror Since the current source generating Icopy in Fig. 9.22 must be implemented as a bipolar or MOS transistor, we surmise that the current mirror resembles the topology shown in Fig. 9.23(a), where Q1 operates in the forward active region and the black box guarantees Icopy = IREF regardless of temperature or transistor characteristics. (The MOS counterpart is similar.) I REF VCC I copy I REF VCC I REF VCC I copy ?X Q1 VBE Q REF V1 Q REF X Q 1 Current Mirror (a) (b) (c) Figure 9.23 (a) Conceptual illustration of current copying, (b) voltage proportional to natural logarithm of current, (c) bipolar current mirror. How should the black box of Fig. 9.23(a) be realized? The black box generates an output voltage, VX = VBE, such that Q1 carries a current equal to IREF : IS1 exp VX VT = IREF ; (9.86) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 437 (1) Sec. 9.2 Current Mirrors 437 where Early effect is neglected. Thus, the black box satisfies the following relationship: VX = VT ln IREF IS1 : (9.87) We must therefore seek a circuit whose output voltage is proportional to the natural logarithm of its input, i.e., the inverse function of bipolar transistor characteristics. Fortunately, a single diode-connected device satisfies (9.87). Neglecting the base-current in Fig. 9.23(b), we have V1 = VT ln IREF IS;REF ; (9.88) IwSh;RerEeFIS=;RIESF1, denotes the reverse saturation current i.e., if QREF is identical to Q1. of QREF . In other Figure 9.23(c) consolidates our thoughts, displaying the current mirror words, V1 = VX if circuitry. We say Q1 “mirrors” From one poerrcsoppeicetsivteh,eQcRuErrFenttaflkeoswtihnegntahtruoruaglhloQgaRrEithFm. FoofrInRoEwF, we neglect the base currents. and Q1 takes the exponential of VX , thereby yielding Icopy = IREF . From another perspective, since QREF and Q1 have equal base-emitter voltages, we can write IREF = IS;REF exp VX VT Icopy = IS1 exp VX VT (9.89) (9.90) and hence Icopy = IS1 IS;REF IREF ; (9.91) which reduces to Icopy = IS vary with temperature. NIRoEteFthifatQVRXEdFoeasndvaQry1 are identical. This holds even with temperature but such that though VT Icopy does and not. Example 9.12 An electrical engineering student who is excited by the concept of the current mirror constructs the circuit but forgets to tie the base of QREF to its collector (Fig. 9.24). Explain what happens. I REF VCC I copy ? Figure 9.24 Q REF Q1 Solution The circuit provides no path for the base currents of the transistors. More fundamentally, the base-emitter voltage of the devices is not defined. The lack of the base currents translates to Icopy = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 438 (1) 438 Chap. 9 Cascode Stages and Current Mirrors Exercise What is the region of operation of QREF ? Example 9.13 Realizing the mistake in the above circuit, the student makes the modification shown in Fig. 9o.f2Q5,RhEoFpianngdthQa1t .thEexbpalatitnerwy hVaXt provides happens. the base currents and defines the base-emitter voltage I REF VCC I copy ? I REF VCC I copy ? Q REF Q1 VX Q REF Q1 VX VX Figure 9.25 Solution While Q1 now carries a finite current, the biasing of Q1 is no different from that in Fig. 9.21; i.e., Icopy = IS1 exp VX VT ; (9.92) which is a function of temperature if VX is constant. The student has forgotten that a diodeconnected device is necessary here to ensure that VX remains proportional to lnIREF =IS;REF . Exercise dSouepspoQsReEVFX is slightly operate? greater than the necessary value, VT lnIREF =IS;REF . In what region We must now address two important questions. First, how do we make additional copies roveafcluIoRegsnEifFzoerttothhaefetseeVdcXodpcifiafenesr,seeen.rtgv.pe, a2arIstsRthEoeFf an integrated circuit? Second, how do we obtain different , 5IREF , etc.? Considering the topology in Fig. 9.22(c), we base-emitter voltage of multiple transistors, thus arriving at the circuit shown in Fig. 9.26(a). The circuit is often drawn as in Fig. 9.26(b) for simplicity. Here, transistor Qj carries a current Icopy;j, given by Icopy;j = IS;j exp VX VT ; (9.93) which, along with (9.87), yields Icopy;j = IS;j IS;REF IREF : (9.94) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 439 (1) Sec. 9.2 Current Mirrors 439 I REF VCC I copy1 I copy2 I copy3 Q REF Q1 Q2 Q3 I REF Q REF VCC I copy1 I copy2 I copy3 Q1 Q2 Q3 (a) VCC I REF Q1 Q REF I copy = 3 I REF Q2 Q3 (b) (c) Figure 9.26 (a) Multiple copies of a reference current, (b) simplified drawing of (a), (c) combining output currents to generate larger copies. The key point here is that multiple copies of IREF can be generated with minimal additional complexity because IREF Equation (9.94) readily and QREF themselves need answers the second question not be duplicated. as well: If IS;j ( the emitter area of Qj ) is chosen to be n times IS;REF ( copies are “scaled” with respect to tIhReEeFm.iRtteercaalrlefaroomf QCRhEaFpt)e,rth4etnhaItcothpyis;jis=eqnuIiRvaElFen.tWtoepslaaycitnhge n unit transistors QREF , providing in parallel. Figure Icopy = 3IREF . 9.26(c) depicts an example where Q1-Q3 are identical to Example 9.14 A multistage amplifier incorporates two current sources of values 0.75 mA and 0.5 mA. Using a bandgap reference current of 0.25 mA, design the required current sources. Neglect the effect of the base current for now. Solution Figure 9.27 illustrates the circuit. Here, all transistors are identical to ensure proper scaling of IREF . VCC I REF 0.25 mA 0.75 mA Q1 Q2 Q3 Q REF 0.5 mA Q4 Q5 Figure 9.27 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 440 (1) 440 Chap. 9 Cascode Stages and Current Mirrors Exercise Repeat the above example if the bandgap reference current is 0.1 mA. The use of multiple transistors in parallel provides an accurate means of scaling the reference iQnRcEurFreintstemlfirarsorms.uBltuipt,lehopwaradlolewl teracnrseiastteorfsr.acEtxioenmspoliffiIeRdEbFy?thTehicsiricsuaict cionmFpigli.s9h.e2d8b, ythreeaidliezainigs VCC I REF 0.25 mA I copy X Q1 Q REF1 Q REF2 Q REF3 Figure 9.28 Copying a fraction of a reference current . to begin with a larger IS;REF (= 3IS here) so that a unit transistor, Q1, can generate a smaller current. Repeating the expressions in (9.89) and (9.90), we have IREF = 3IS exp VX VT (9.95) Icopy = IS exp VX VT (9.96) and hence Icopy = 1 3 IREF : (9.97) Example 9.15 It is desired to generate two currents equal to 50 A and 500 A from a reference of 200 A. Design the current mirror circuit. Solution To produce the smaller current, we carries 50 A. A unit transistor thus mgeunsetreamtespl5o0yfoAu(rFuingi.t9t.r2a9n)s.iTsthoerscfuorrreQntRoEfF50s0uchAthreaqt ueiarcehs 10 unit transistors, denoted by 10AE for simplicity. VCC I REF 0.2 mA I copy1 X Q1 AE Figure 9.29 4A E I copy2 Q2 10A E BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 441 (1) Sec. 9.2 Current Mirrors 441 Exercise Repeat the above example for a reference current of 150 A. Effect of Base Current We have thus far neglected the base current drawn from node X in Fig. 9.26(a) by all transistors, an effect leading to a significant error as the number of copies (i.e., the total copied current) increases. The error arises because a fraction of IREF flows through the bases rather than through the collector of QREF . We analyze the error with the aid of the diagram shown in Fig. 9.30, where AE and nAE denote one unit transistor and n unit transistors, VCC I REF Q REF AE I copy nβ Q1 I copy β I copy nA E Figure 9.30 Error due to base currents. respectively. Our objective is to calculate Icopy, recognizing that base-emitter voltages and hence carry currents with a ratio of n. and QREF can be expressed as QREF Thus, and Q1 the base still have equal currents of Q1 IB1 = Icopy (9.98) IB;REF = Icopy  1 n : (9.99) Writing a KCL at X therefore yields IREF = IC;REF + Icopy  1 n + Icopy ; (9.100) which, since IC;REF = Icopy=n, leads to Icopy = 1 nIREF + 1 n + : 1 (9.101) For a large and moderate n, the second term in the denominator is much less than unity and Icopy  nIREF . However, as the copied current ( n) increases, so does the error in Icopy. To suppress the above error, the bipolar current mirror can be modified as illustrated in Fig. 9.31. Here, emitter follower QF is interposed between the collector of QREF and node X, thereby reducing the effect of the base currents by a factor of . More specifically, assuming IC;F  IE;F , we can repeat the above analysis by writing a KCL at X: IC;F = Icopy + Icopy  1 n ; (9.102) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 442 (1) 442 Chap. 9 Cascode Stages and Current Mirrors I REF P AE I B,F Q REF VCC I C,F QF X Q1 I copy nβ I copy β I copy nA E Figure 9.31 Addition of emitter follower to reduce error due to base currents. obtaining the base current of QF as IB;F = Icopy 2 1+ 1 n : Another KCL at node P gives IREF = = IIBco;2Fpy+ I1C+;REn1F + Icopy n (9.103) (9.104) (9.105) and hence Icopy = 1 + nIREF 1 2 n + : 1 (9.106) That is, the error is lowered by a factor of . Example 9.16 Compute the error in Icopy1 and Icopy2 in Fig. 9.29 before and after adding a follower. Solution Noting that Icopy1, Icopy2, and IC;REF (the total still retain their nominal ratios (why?), we write a current KCL at flowing X: through four unit transistors) IREF = IC;REF + Icopy1 + Icopy2 + IC;REF = 4Icopy1 + Icopy1 + 10Icopy1 + IC;REF : (9.107) (9.108) Thus, Icopy1 = IREF 4 + 15 Icopy2 = 10IREF 4 + 15 : With the addition of emitter follower (Fig. 9.32), we have at X: (9.109) (9.110) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 443 (1) Sec. 9.2 Current Mirrors I REF P 0.2 mA VCC Q F Q 1 I copy1 AE X Figure 9.32 4A E I copy2 Q 2 10A E IC;F = IC;REF + Icopy1 + Icopy2 = 4Icopy1 + Icopy1 + 10Icopy1 = 15Icopy1 : A KCL at P therefore yields IREF = 15Icopy1 2 + IC;REF = 15Icopy1 2 + 4Icopy1; and hence Icopy1 = IREF 4 + 15 2 Icopy2 = 10IREF 4 + 15 2 : 443 (9.111) (9.112) (9.113) (9.114) (9.115) (9.116) (9.117) Exercise Caraelacuolfa3teAIEco.py1 if one of the four unit transistors is omitted, i.e., the reference transistor has an PNP Mirrors Consider the common-emitter stage shown in Fig. 9.33(a), where a current source serves as a load to achieve a high voltage gain. The current source can be realized as a pnp transistor operating in the active region [Fig. 9.33(b)]. We must therefore define the bias current current of Q2 mirror properly. In analogy with the npn counterpart depicted in Fig. 9.33(c). For example, if QREF of Fig. 9.23(c), we form and Q2 are identical and the the pnp base currents negligible, then Q2 Q1 carries a current equal to IREF . BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 444 (1) 444 Chap. 9 Cascode Stages and Current Mirrors VCC I1 v out v in Q1 VCC VCC Vb Q2 Q REF X Q2 v out v out v in Q1 I REF v in Q1 (a) (b) (c) Figure 9.33 (a) CE stage with current-source load, (b) realization of current source by a pnp device, (c) proper biasing of Q2. Example 9.17 Design the circuit of Fig. 9.33(c) for a voltage gain of 100 and a power budget of 2 mW. Assume VA;npn = 5 V, VA;pnp = 4 V, IREF = 100 A, and VCC = 2:5 V. Solution w7Fin0rhco0iomcrhpAto1hr,0ear0teepqsouwoAinreienirsgubdnutehidtdagditecettavhtieaecnde(deatmonVidCIttRCQeEr1)F=aseraev2nae:dn5ofQuVnQR,it2EwdFbeee.voiT7cbhettiausmi.s)n,esQa t1htoaattanoldfsQuQp2RpEalyrFec.bu(iFraroserendet xoaatfma8p0cl0eu,rrQeAnR,tEooFff The voltage gain can be written as Av = ,gm1rO1jjrO2 = , 1 VT  VA;npnVA;pnp VA;npn + VA;pnp = ,85:5: (9.118) (9.119) (9.120) What happened here?! We sought a gain of 100 but inevitably obtained a value of 85.5! This is because the gain of the stage is simply given by the Early voltages and VT , a fundamental constant of the technology and independent of the bias current. Thus, with the above choice of Early voltages, the circuit’s gain cannot reach 100. Exercise What Early voltage is necessary for a voltage gain of 100? We must now address an interesting problem. In the mirror of Fig. 9.23(c), it is assumed that the golden current flows from VCC to node X, whereas in Fig. 9.33(c) it flows from X to ground. How do we generate the latter from the former? It is possible to combine the npn and pnp mirrors fbIavoRnaarrdsEietoFhQcuiuss2frrpsaroceurmaenrlptiisQondisgeRnentsE,rtcaioFcesd2anui,lalclrtauheinoseadstrrecabnbuteeeymtgdwlfueioelnceartcntiFiinvniQggeg.Rteth9Erhe.re3Fob4r1sa.aaasAmsensIdecsRuuQcErmurMFreirnneiagstnsntc,fdootwhrpbreiseoeitoudmwbgopeshneelinrtQcoviQ2etIyCRtaht;nEhMadaFtt,Q2QQaan1MRn.ddEWIdFCQrea1;M2w,c.aQsNnoaMnoattcl,oesuQoIrthrCRcea2Ernte.tFtahot2eef, Example 9.18 We wish to bias Q1 and Q2 in Fig. 9.34 at a collector current of 1 mA while IREF = 25 A. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 445 (1) Sec. 9.2 Current Mirrors 445 I REF Q REF1 Q REF2 I C,M X1 QM X2 v in VCC Q2 v out Q1 Figure 9.34 Generation of current for pnp devices. Choose the scaling factors in the circuit so as to minimize the number of unit transistors. Solution For an overall scaling factor of 1 mA=25 A = 40, we can choose either IC;M = 8IREF jIC2j = 5IC;M (9.121) (9.122) or IC;M = 10IREF jIC2j = 4IC;M: (9.123) (9.124) (In each case, the npn and pnp scaling factors can be swapped.) In the former case, the four transistors in the current mirror circuitry require 15 units, and in the latter case, 16 units. Note that we have implicitly dismissed the case IC;M = 40IC;REF 1 and IC2 = IC;REF 2 as it would necessitate 43 units. Exercise Calculate the exact value of IC2 if = 50 for all transistors. Example 9.19 An electrical engineering student purchases two nominally identical discrete bipolar transistors and constructs the current IREF . Explain why. mirror shown in Fig. 9.23(c). Unfortunately, Icopy is 30 higher than Solution It is possible that the two transistors were fabricated in different batches and hence underwent slightly different processing. Random variations during manufacturing may lead to changes in the device parameters and even the emitter area. As a result, the two transistors suffer from significant IS mismatch. This is why current mirrors are rarely used in discrete design. Exercise How much IS mismatch results in a 30% collector current mismatch? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 446 (1) 446 Chap. 9 Cascode Stages and Current Mirrors 9.2.3 MOS Current Mirror The developments in Section 9.2.2 can be applied to MOS current mirrors as well. In particular, drawing the MOS counterpart of Fig. 9.23(a) as in Fig. 9.35(a), we recognize that the black box must generate VX such that VDD VDD VDD I REF I copy1 I REF I REF I copy X ? M1 VGS M REF VX M REF X M 1 Current Mirror (a) (b) (c) Figure 9.35 (a) Conceptual illustration of copying a current by an NMOS device, (b) generation of a voltage proportional to square root of current, (c) MOS current mirror. 1 2 nCox W L 1 VX , VT H1 2 = IREF ; (9.125) where channel-length modulation is neglected. Thus, the black box must satisfy the following input (current)/output (voltage) characteristic: VX = vuuut nC2oIxR EWFL 1 + VT H1 : (9.126) That is, it must operate as a “square-root” circuit. From Chapter 6, we recall that a diode- connected MOSFET provides such a characteristic [Fig. 9.35(b)], thus arriving at the NMOS current mirror depicted in Fig. 9.35(c). As with the bipolar version, we can view the circuit’s operation from two perspectives: (1) MREF takes the square root of IREF and M1 squares the result; or (2) the drain currents of the two transistors can be expressed as ID;REF Icopy = = 1 2 1 2 nCox nCox W L W L VX , VTH2 REF VX , VTH2; 1 (9.127) (9.128) where the threshold voltages are assumed equal. It follows that W Icopy = WL 1 IREF ; L REF which reduces to Icopy = IREF if the two transistors are identical. (9.129) Example 9.20 The student working on the circuits in Examples 9.12 and 9.13 decides to try the MOS counterpart, thinking that the gate current is zero and hence leaving the gates floating (Fig. 9.36). Explain what happens. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 447 (1) Sec. 9.2 Current Mirrors 447 I REF M REF VDD X I copy ? M1 Figure 9.36 Floating Node Solution This circuit is not a current mirror because only a diode-connected device can establish (9.129) and hence a copy current independent of device parameters and temperature. Since the gates of MREF and M1 are floating, they can assume any voltage, e.g., an initial condition created at node X when the power supply is turned on. In other words, Icopy is very poorly defined. Exercise Is MREF always off in this circuit? Generation of additional copies of IREF with different scaling factors also follows the prin- ciples shown in Fig. 9.26. The following example illustrates these concepts. Example 9.21 An integrated circuit employs the source follower and the common-source stage shown in Fig. 9.37(a). Design a current mirror that produces I1 and I2 from a 0.3-mA reference. Vin1 0.2 mA VDD M1 Vout1 I1 Vin2 0.5 mA VDD M2 Vout2 I2 Figure 9.37 (a) I REF 3 (W L ( VDD Vin1 0.3 mA VDD M1 Vin2 Vout1 I1 M I1 VDD M2 Vout2 I2 M I2 ( M REF ( 2 (W L (b) 5 (W L BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 448 (1) 448 Chap. 9 Cascode Stages and Current Mirrors Solution Following the methods depicted in Figs. 9.28 and 9.29, we select an aspect ratio of 3W=L for the diode-connected device, 2W=L for MI1, and 5W=L for MI2. Figure 9.37(b) shows the overall circuit. Exercise Repeat the above example if IREF = 0:8 mA. Since MOS devices draw a negligible gate current,6 MOS mirrors need not resort to the technique shown in Fig. 9.31. On the other hand, channel-length modulation in the current-source transistors does lead to additional errors. Investigated in Problem 53, this effect mandates circuit modifications that are described in more advanced texts [1]. The idea of combining NMOS and PMOS current mirrors follows the bipolar counterpart depicted in Fig. 9.34. The circuit of Fig. 9.38 exemplifies these ideas. CS Stage Follower VDD I REF VDD M REF Vin1 Vout1 Vin2 Vout2 Follower Vin3 Vin4 Vout3 CS Stage VDD Vout4 Figure 9.38 NMOS and PMOS current mirrors in a typical circuit. 9.3 Chapter Summary Stacking a transistor atop another forms a cascode structure, resulting in a high output impedance. The cascode topology can also be considered an extreme case of source or emitter degeneration. A 6In deep-submicron CMOS technologies, the gate oxide thickness is reduced to less than 30 , leading to “tunneling” and hence noticeable gate current. This effect is beyond the scope of this book. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 449 (1) Sec. 9.3 Chapter Summary 449 The voltage gain of an amplifier can be expressed as ,GmRout, where Gm denotes the short-circuit transconductance of the amplifier. This relationship indicates that the gain of amplifiers can be maximized by maximing their output impedance. With its high output impedance, a cascode stage can operate as a high-gain amplifier. The load of a cascode stage is also realized as a cascode circuit so as to approach an ideal current source. Setting the bias currents of analog circuits to well-defined values is difficult. For example, resistive dividers tied to the base or gate of transistors result in supply- and temperaturedependent currents. If VBE or VGS are well-defined, then IC or ID are not. Current mirrors can “copy” a well-defined reference current numerous times for various blocks in an analog system. Current mirrors can scale a reference current by integer or non-integer factors. Current mirrors are rarely used in disrcete design as their accuracy depends on matching between transistors. Problems 1. In the bipolar cascode stage of Fig. 9.2(a), IS = 6  10,17 A and = 100 for both transistors. Neglect the Early effect. (a) (b) CNoomtinpguttehaVtbV2CfoEr2a=biVasb1c,urVreBnEt 1o,fd1emterAm.ine the value of Vb1 such that Q2 experiences a base-collector forward bias of only 300 mV. 2. Consider the cascode stage depicted in Fig. 9.39, where VCC = 2:5 V. VCC RC V1 Vb1 Q1 Vb2 Q2 Figure 9.39 (a) Repeat Problem 1 for this circuit, assuming a bias current of 0.5 mA. RC(bs)ucWhitthhatthQe m1 einxipmeruimenaclelsowa abbalsee-vcaolulleecotforVfbo1r,wcoamrdpbuitaestohfe maximum allowable value no more than 300 mV. of 3. In the circuit of Fig. 9.39, we have chosen RC = 1 k and VCC = 2:5 V. Estimate the maximum allowable bias current if each transistor sustains a base-collector forward bias of 200 mV. 4. Due to a manufacturing error, a parasitic resistor RP has appeared in the cascode circuits of Fig. 9.40. Determine the output resistance in each case. 5. Repeat Example 9.1 for mA, i.e., IC1 = 0:5 mA the circuit while IC2 shown in = 1 mA. Fig. 9.41, assuming I1 is ideal and equal to 0.5 6. Suppose the circuit of Fig. 9.41 is realized as shown in Fig. 9.42, where Q3 plays the role of BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 450 (1) 450 Chap. 9 Cascode Stages and Current Mirrors R out R out R out R out Vb1 Q1 RP Vb2 Q2 Q1 Vb1 RP Vb2 Q2 Vb1 Q1 Q2 Vb2 RP Vb1 Q1 RP Vb2 Q2 (a) (b) (c) (d) Figure 9.40 Figure 9.41 R out VCC Vb1 Q1 I1 Vb2 Q2 R out VCC Vb1 Q1 Q3 Vb3 Vb2 Q2 Figure 9.42 I1. Assuming VA1 = VA2 = VA;n and VA3 = VA;p, determine the output impedance of the circuit. 7. Excited by the output impedance “boosting” capability of cascodes, a student decides to extend the idea as illustrated in Fig. 9.43. What is the maximum output impedance that the R out Vb1 Q1 Vb2 Q2 Vbn Qn Figure 9.43 student can achieve? Assume the transistors are identical. 8. While constructing a cascode stage, a student adventurously swaps the collector and base terminals of the degeneration transistor, arriving at the circuit shown in Fig. 9.44. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 451 (1) Sec. 9.3 Chapter Summary 451 R out Vb1 Q1 Vb2 Q2 Figure 9.44 (a) Assuming both transistors operate in the active region, determine the output impedance of the circuit. (b) Compare the result with that of a cascode stage for a given bias current (IC1) and explain why this is generally not a good idea. 9. For discrete bipolar transistors, the Early voltage reaches tens of volts, allowing the approx- imation VA VT if 100. Using this approximation, simplify Eq. (9.9) and explain why the result resembles that in Eq. (9.12). 10. The pnp cascode depicted in Fig. 9.45 must provide a bias current of 0.5 mA to a circuit. If VCC = 2.5 V Vb2 Q2 X Vb1 Q1 Circuit 0.5 mA Figure 9.45 IS = 10,16 and = 100, j j tha((tbaQ)) 2CNaeolxtcipnueglraittehenatctheVesXraeqb=uasiVreeb-d1co+vlalelVucBetoEorf1foV,rbdw2e.aterrdmbiinaes the maximum allowable of only 200 mV. value of Vb1 such 11. Determine the output impedance of each circuit shown in Fig. 9.46. Assume 1. Explain which ones are considered cascode stages. 12. The MOS cascode of Fig. 9.47 must provide a bias current of 0.5 mA with an output p impedance of tors, compute athtelemasatx5im0 ukm.tIoflernabCloexv=alu1e0o0fA. /V2 and W=L = 20=0:18 for both transis- 13. (a) Writing gm = 2nCoxW=LID, express Eq. (9.23) in terms of ID and plot the result as a function of ID. (b) Compare this expression with that in Eq. (9.9) for the bipolar counterpart. Which one is a stronger function of the bias current? 14. The cascode current source shown in Fig. 9.48 must be designed for a bias current of 0.5 mA. Assume nCox = 100 A/V2 and VTH = 0:4 V. (a) Neglecting channel-length modulation, compute the required value of m(bi)nAimssuummtionlgerab=le0v:a1luVe,o1f, Vb1 if M2 must remain in saturation? calculate the output impedance of the circuit. Vb2. What is the 15. Consider the circuit shown in Fig. 9.49, where VDD = 1:8 V, W=L1 = 20=0:18; and W=L2 = 40=0:18. Assume nCox = 100 A/V2 and VTH = 0:4 V. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 452 (1) 452 Chap. 9 Cascode Stages and Current Mirrors R out Vb1 Q1 Vb2 Q2 RB (a) VCC RE Vb2 Q2 Vb1 Q1 R out (e) Figure 9.46 Vb1 Vb2 RB R out Q1 Q2 R out Vb1 Q1 RB Q2 Q1 Vb1 R out RP Q2 (b) (c) (d) VCC R out Vb2 Q2 Q1 Vb I1 VCC I1 Vb2 Q 1 Vb2 Q2 R out (f) (g) Figure 9.47 R out Vb1 M1 Vb2 M2 Figure 9.48 = = Vb1 M 1 W 30 L 0.18 Vb2 M 2 W 20 L 0.18 val(u(bae))oIWff Vwitbhe1s?ruecqhuiarevaalbuieacshcousrerennftoorfV1b1m, wAhaantdisRthDe = 500 value of , what VX ? is the highest allowable 16. Compute the output resistance of the circuits depicted in Fig. 9.50. Assume all of the tran- sistors operate in saturation and gmrO 1. 17. The PMOS cascode impedance of 40 k . of Fig. 9.51 must provide If pCox = 50 A/V2 and a  =bia0s:2cVur,re1n, tdeotfer0m.5inme Athewreitqhuiarnedovuatpluuet of W=L1 = W=L2. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 453 (1) Sec. 9.3 Chapter Summary 453 VDD RD V1 Vb1 M1 X Vb2 M2 Figure 9.49 R out Vb1 M1 Vb1 RG M2 R out M1 Vb1 M2 Vb2 R out R out M1 M3 M2 Vb3 Vb1 M1 M2 (a) (b) (c) (d) Figure 9.50 VDD Vb2 M2 Figure 9.51 Vb1 M1 R out 18. The PMOS cascode of Fig. 9.51 is designed for a given output impedance, (9.23), explain what happens if the widths of both transistors are increased while the transistor lengths and bias currents remain unchanged. Assume  bRyouLat,f.aU1c.tsoinr gofENq. 19. Determine the output impedance of the stages shown in Fig. 9.52. Assume all of the transis- tors operate in saturation and gmrO 1. 20. Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. 9.53. Assume  0 and VA 1. 21. Prove that Eq. (9.53) reduces to Av  VT VA2 VA + VT ; (9.130) a quantity independent of the bias current. 22. The cascode stage of Fig. 9.16(b) must be designed for a voltage gain of 500. If 100, determine the minimum required value of VA1 = VA2. Assume I1 = 1 mA. 1= 2= 23. Having learned about the high voltage gain of the cascode stage, a student adventurously constructs the circuit depicted in Fig. 9.54, where the input is applied to the base of Q2 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 454 (1) 454 Chap. 9 Cascode Stages and Current Mirrors R out Vb1 M1 R out VDD Vb1 M1 M3 Vb3 M2 RG Vb2 M2 Vb3 Figure 9.52 (a) VDD Vb2 M2 M 3 Vb1 M1 R out (c) (b) Vb1 Vb2 Vb3 R out M1 M2 M3 (d) VDD Vb M2 Vout Vin M1 VCC VCC VDD Vb Q2 Vin Q2 Vin M2 Vout Vout Vout Vin Q1 Vb Q1 Vb M1 RE RE (a) VDD RE Vb2 M2 Vout M1 Vb1 Vin RS (e) Figure 9.53 (b) (c) (d) VDD RE Vin M2 Vout M1 Vb1 RS (f) VCC RE Vin Q2 Vout RC (g) rather than to (a) Replacing the Q1 bwaistehorfOQ1,1e. xplain intuitively why the voltage gain of this stage cannot be as high as that of the cascode. (b) Assuming gmrO 1, compute the short-circuit transconductance and the voltage gain. 24. Determine the short-circuit transconductance and the voltage gain of the circuit shown in Fig. 9.55. 25. Calculate the voltage gain of each stage illustrated in Fig. 9.56. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 455 (1) Sec. 9.3 Chapter Summary 455 VCC I1 Vout Vin Q2 Vb1 Q1 Figure 9.54 Figure 9.55 VCC I1 Vout Vb2 Q2 Vb1 Q1 Vin VCC VCC I1 Vout I1 Vout Vb1 Q1 RP Vin Q2 Q1 Vb1 RP Vin Q2 VCC I1 Vout Vb1 Q1 Vin Q2 RE VCC I1 Vout VCC Vb1 Q1 Q3 Vb3 Vin Q2 (a) (b) (c) (d) Figure 9.56 26. Consider the VA;N , 3 = cascode amplifier of 4 = P , V31 = VA4 =FigV.A9;.P1.9EaxnpdreassssuEmq.e(9.161=) in 2= terms N , VA1 of these = VA2 = quantities. Does the result depend on the bias current? 27. Due to a manufacturing error, a bipolar cascode amplifier has been configured as shown in p Fig. 9.57. Determine the voltage gain of the circuit. 28. Writing gm = 2nCoxW=LID device parameters and plot the result aansdarfOun=ctio1n=ofIIDD., express Eq. (9.72) in terms of the 29. The 100 MOS cascode A=V2 and  of = Fig. 0:1 9V.2,01(a)fomr ubsotthprtorvanidseistaorvs,oldtaegteermgianine of 200. If nCox the required value = of W=L1 = W=L2. 30. The MOS cascode of Fig. 9.20(a) is designed for a given voltage gain, Av. Using Eq. (9.79) and the result obtained in Problem 28, explain what happens if the widths of the transis- tors are increased by a factor of N while the transistor lengths and bias currents remain BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 456 (1) 456 Figure 9.57 Chap. 9 Cascode Stages and Current Mirrors VCC Q4 Vb2 Q3 v out Vb1 Q2 v in Q1 unchanged. 31. Repeat Problem 30 if the lengths of both transistors are increased by a factor of N while the transistor widths and bias currents remain unchanged. 32. Due to a manufacturing error, a CMOS cascode amplifier has been configured as shown in Fig. 9.58. Calculate the voltage gain of the circuit. VDD Vb4 M4 Vb3 Vb2 V in Vb1 M3 Vout M2 M1 Figure 9.58 33. I1n00theAc=asVc2o,daensdtagpeCoofxF=ig.590.20A(b=)V, 2W, =nL=1 = 0:1 V ,=1, aWnd=Lp4==0:2105=V0:,118,. If nCox = calculate the bias current such that the circuit achieves a voltage gain of 500. 34. Determine the voltage gain of each circuit in Fig. 9.59. Assume gmrO 1. VDD VDD VDD Vb4 M4 Vb4 M4 Vin Vb4 M4 Vb4 M5 Vb3 M3 Vb3 M3 Vb3 M3 Vb3 M2 Vout Vout Vout Vb2 RP Vb2 M2 Vb2 M2 Vb2 Vin M1 Vin M1 RP Vb1 M1 Vin M5 Vb1 VDD M4 M3 Vout M2 M1 (a) (b) (c) (d) Figure 9.59 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 457 (1) Sec. 9.3 Chapter Summary 457 35. From Eq. intuitively (9.83), determine the why this sensitivity is pseronpsiotrivtiiotynaol ftoI1thetotrVanCsCc,onddeuficnteadncaeso@f IQ1=1.@ VCC . Explain 36. Repeat Problem 35 for Eq. (9.85) (in terms of VDD). 37. The parameters nCox and VT H in Eq. (9.85) also vary with the fabrication process. (In- tegrated circuits fabricated in different batches exhibit slightly different parameters.) Deter- mine the sensitivity of I1 to VT H and explain why this issue becomes more serious at low supply voltages. 38. Having learned about the logarithmic function of the circuit in Fig. 9.23(b), a student remembers the logarithmic amplifier studied in Chapter 8 and constructs the circuit depicted in Fig. 9.60. Explain what happens. Figure 9.60 R1 VREF Q1 IX V1 Q2 39. Repeat Problem 38 for the topology shown in Fig. 9.61. IX R1 VREF Q1 Q2 V1 Figure 9.61 40. Due Fig. to a manufacturing 9.62. If I1 is half of error, resistor RP its nominal value, hexaspraepspsetahreevdailnueseorfieRsPwiinthtethrme semofitotethr eorfcQir1cuiint VCC I REF I1 Q REF Q1 RP Figure 9.62 parameters. Assume QREF and Q1 are identical and 1. 41. Repeat Problem 40 for the circuit shown in Fig. 9.63, but assuming that I1 is twice its nominal value. 42. We wish to generate two currents equal to 50 A and 230 A from a reference of 130 A. Design an npn current mirror for this purpose. Neglect the base curents. 43. Repeat Example 9.15 if the reference current is equal to 180 A. 44. Due to a manufacturing error, resistor RP has appeared in series with the base of QREF in Fig. 9.64. If I1 is 10% greater than its nominal value, express the value of RP in terms of other circuit parameters. Assume QREF and Q1 are identical. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 458 (1) 458 Chap. 9 Cascode Stages and Current Mirrors VCC I REF I1 Q REF Q1 RP Figure 9.63 Figure 9.64 VCC I REF I1 Q REF Q1 RP Figure 9.65 VCC I REF I1 Q REF Q1 RP 45. Repeat Problem 44 for the circuit shown in Fig. 9.65, but assuming I1 is 10% less than its nominal value. 46. Taking base currents Fig. 9.66. Normalize tihnetoerarcocrotuontth, ednetoemrminianlevtahleuevaolfuIecoopfyI. copy in each circuit depicted in VCC VCC VCC I REF AE I copy Q1 5A E Q REF I REF 5A E Q1 Q REF I copy AE I REF Q 1 I copy 2A E Q REF 3A E Q2 I 2 5A E (a) (b) (c) Figure 9.66 47. Calculate the error in Icopy for the circuits shown in Fig. 9.67. 48. Taking base currents into account, compute the error in Icopy for each of the circuits illus- trated in Fig. 9.68. 49. Determine the choice of RP , value of RP in the circuit of does I1 change if the threshold Fig. 9.69 such that I1 = voltage of both transistors IREF =2. increases With this by V ? 50. Determine the value of RP in the circuit of Fig. 9.70 such that I1 = 2IREF . With this choice of RP , does I1 change if the threshold voltage of both transistors increases by V ? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 459 (1) Sec. 9.3 Chapter Summary 459 VCC I REF nAE Q REF Q 1 I copy1 mA E Q2 I 2 kAE Figure 9.67 I REF AE AE AE VCC AE I copy I REF 3A E 5A E 2A E VCC 9A E I copy Figure 9.68 Figure 9.69 Figure 9.70 (a) (b) I REF VDD W L M REF M1 I1 W L RP I REF VDD W L M REF RP M1 I1 W L 51. Repeat Example 9.21 if the reference current is 0.35 mA. 52. Calculate Icopy in each of the circuits shown in Fig. 9.71. Assume all of the transistors operate in saturation. 6 53. Consider the but  = 0. MOS current mirror shown in Fig. 9.35(c) and assume M1 and M2 are identical (a) How should VDS1 be chosen so that Icopy1 is exactly equal to IREF ? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 460 (1) 460 Chap. 9 Cascode Stages and Current Mirrors VDD I REF 3 (W Ln ( 5 (W Lp M REF ( 2 (W Ln ( 3 (W Lp I copy ( (a) Figure 9.71 VDD I REF (W Lp ( ( (W Ln M REF 5 (W Ln (b) ( ( ( 2 (W Lp I copy 3 (W Ln (b) Determine the error in Icopy1 with respect to IREF if VDS1 is equal to VGS , VT H (so that M1 resides at the edge of saturation). Design Problems IVVNnATMHt;nhO;enS=f)=oalVln0oAd:w4;ppiVn-t=g,yappn5erdo(VbpV,lnTepmHno;spr,=Pu=Mn1l,eO0s00Ss:;)5odtpVhe,ev=wriwche5iess0r,ee;rsettshnapetCeescoduxt,ibvas=esclsryui1.pm0tse0nISaA;nn/dV=p2,rIeSfpe;pCr ot=ox 6  10,16 A, = 50 A/V2, n-type (npn or 54. Assuming a bias current of 1 mA, design the degenerated current source of Fig. 9.72(a) such that RE sustains a voltage approximately equal to the minimum required collector-emitter R out R out Vb Q1 RE Vb1 Q1 Vb2 Q2 (a) (b) Figure 9.72  voltage of Q2 in Fig. 9.72(b) ( 0:5 V). Compare the output impedances of the two circuits. 55. Design the cascode current source of Fig. 9.72(b) for an output impedance of 50 k . Select Vb1 such that Q2 experiences a base-collector forward bias of only 100 mV. Assume a bias current of 1 mA. 56. We wish to design the MOS cascode of Fig. 9.73 for an output impedance of 200 k and a R out Vb1 M1 Vb2 M2 Figure 9.73 bias current of 0.5 mA. (a) Determine W=L1 = W=L2 if  = 0:1 V,1. (b) Calculate the required value of Vb2. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 461 (1) Sec. 9.3 Chapter Summary 461 57. The bipolar cascode amplifier of Fig. 9.74 must be designed for a voltage gain of 500. Use VCC I1 Vout Vb1 Q2 Vin Q1 Figure 9.74 Eq. (9.53) and assume = 100. (a) What is the minimum required value of VA? (b) For a bias current of 0.5 mA, calculate the required bias component in Vin. (c) Compute the value of Vb1 such that Q1 sustains a collector-emitter voltage of 500 mV. 58. Design the cascode amplifier shown in Fig. 9.75 for a power budget of 2 mW. Select Vb1 and VCC = 2.5 V Vb3 Q4 Vb2 Q3 Vout Vb1 Q2 Vin Q1 Figure 9.75 Vb2 such that Q1 and Q4 sustain a base-collector forward bias of 200 mV. What voltage gain is achieved? 59. Design the CMOS cascode amplifier of Fig. 9.76 for a voltage gain of 200 and a power VDD Vb3 M4 Vb2 M3 Vout Vb1 M2 Vin M1 Figure 9.76 budget of 2 aspsu=me2Vbn1 =mW0:2wiVth,V1.DDDet=erm1:i8neVt.hAe srseuqmuieredWd=cLle1ve=ls = Vb2 = 0:9 V.  of = Vin aWnd=LVb43.=Fo2r0s=i0m:1p8licaintyd, 1 60. The current mirror shown in Fig. 9.77 power budget of 2 mW. Assuming VA must = deliver and I1 = 1, 0:5 mA to a circuit with a total determine the required value of IREF and the relative sizes of QREF and Q1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 462 (1) 462 Chap. 9 Cascode Stages and Current Mirrors VCC = 2.5 V I REF Q REF Circuit I1 Q1 Figure 9.77 61. In the circuit of Fig. 9.78, Q2 operates as an emitter follower. Design the circuit for a power VCC = 2.5 V Vin I REF Q2 Vout Q REF Q1 Figure 9.78 1 budget of 3 mW and an output impedance of 50 . Assume VA = and 1. 62. In the circuit of Fig. 9.79, Q2 operates as a common-base stage. Design the circuit for an I REF RC Q2 VCC = 2.5 V Vout Vb Vin Q REF Q1 Figure 9.79 output impedance of 500 , a voltage gain of 20, and a power budget of 3 mW. Assume VA = 1 and 1. 63. Design the circuit of Fig. 9.30 for Icopy = 0:5 mA and an error of less than 1 with respect to the nominal value. Explain the trade-off between accuracy and power dissipation in this circuit. Assume VCC = 2:5 V. 64. Design the circuit of Fig. 9.34 such that the bias current of Q2 is 1 mA and the error in IC1 with respect to its nominal value is less than 2. Is the solution unique? 65. Figure 9.80 shows an arrangement where M1 and M2 serve as current sources for circuits 1 and 2. Design the circuit for a power budget of 3 mW. 66. The common-source stage depicted a power budget of 2 mW. Assuming in Fig. 9.81 W=L1 = m20u=s0t b:1e8d,esnig=ne0d:f1oVr a,v1o,latnagdegpa=in o0f:220Va,n1d, design the circuit. 67. The source follower of Fig. 9.82 must achieve a of 100 . Assuming W=L2 = 10=0:18, n v=olt0a:g1eVga,i1n,oafn0d.85pan=d a0n:2ouVt,pu1t, impedance design the circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 463 (1) Sec. 9.3 Chapter Summary 463 I REF M REF VDD = 1.8 V Circuit 1 0.5 mA M1 Circuit 2 1 mA M2 Figure 9.80 Figure 9.81 M REF I REF Vin VDD = 1.8 V M2 M1 Figure 9.82 I REF Vin M REF VDD = 1.8 V M1 Vout M2 68. The common-gate stage of Fig. 9.83 employs the current source M3 as the load to achieve VDD = 1.8 V I REF M4 M3 Vout M1 Vb Vin M REF M5 M2 Figure 9.83 a high voltage gain. W=L3 = 40=0:18, Fnor=si0m:1plVic,it1y,, annedglepct=ch0a:n2nVel,-l1e,ndgetshigmnothdeulcaitricounitinfoMr a1v.oAltsasguemgianign of 20, an input impedance of 50 , and a power budget of 13 mW. (You may not need all of the power budget.) SPICE Problems BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 464 (1) 464 Chap. 9 Cascode Stages and Current Mirrors ItArna,nthspeinstpfoor=lslo, 5wa0sis,nuVgmApe;rpoInbSp;lne=pmn3s:,=5uVs5e.th1e0M,1O6 SA,devnipcne =mo1d0e0l,sVgAiv;nepnnin=A5pVp,eInSd;ipxnpA=. F8orb1ip0o,l1a6r 69. In the circuit of Fig. 9.84, we wish to suppress the error due to the base currents by means of resistor RP . VCC = 2.5 V I REF 1 mA I1 Q REF Q1 RP Figure 9.84  (a) Tying the collector between I1 and IREF . of Q2 to VC C , select the value of RP so as to minimize the error (b) What is the change in the error if the of both transistors varies by 3? (c) What is the change in the error if RP changes by 10? 70. Repeat Problem 69 for the circuit shown in Fig. 9.85. Which circuit exhibits less sensitivity to variations in and RP ? VCC = 2.5 V I REF 1 mA I1 Q REF Q1 RP Figure 9.85 71. Figure 9.86 depicts a cascode current source whose value is defined by the mirror arrange- ment, M1-M2. Assume W=L = 5 m=0:18 m for M1-M3. VDD = 1.8 V 0.5 mA I out Vb M3 Figure 9.86 M2 M1  (a) (b) Select the value of Vb so Determine the change in that Iout IiofuVtbisvaprrieecsibseyly equal to 0.5 mA. 100 mV. Explain the cause of this change. (c) Using both hand analysis and SPICE simulations, determine the output impedance of the cascode and compare the results. 72. We wish to study the problem of biasing in a high-gain cascode stage, Fig. 9.87. Assume W=L1;2 = 10 m=0:18 mum, Vb = 0:9 V, and I1 = (a) Plot the input/output characteristic and determine 1 mA is an ideal the value of Vin current source. at which the slope (small-signal gain) reaches a maximum. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 465 (1) References 465 Vb Vin VDD = 1.8 V I1 Vout M2 M1 Figure 9.87  (b) Now, suppose the biasing circuitry that must produce the above dc value for Vin incurs an error of 20 mV. From (a), explain what happens to the small-signal gain. 73. Repeat Problem 72 for the cascode shown in Fig. 9.88, assuming W=L = 10 m=0:18 m for all of the transistors. Figure 9.88 M5 1 mA Vb Vin VDD = 1.8 V M4 M3 Vout M2 M1 References 1. B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 466 (1) Differential Amplifiers 10 The elegant concept of “differential” signals and amplifiers was invented in the 1940s and first utilized in vacuum-tube circuits. Since then, differential circuits have found increasingly wider usage in microelectronics and serve as a robust, high-performance design paradigm in many of today’s systems. This chapter describes bipolar and MOS differential amplifiers and formulates their large-signal and small-signal properties. The concepts are outlined below. General Considerations Differential Signals Differential Pair Bipolar Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis MOS Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis Other Concepts Cascode Pair Common−Mode Rejection Pair with Active Load 10.1 General Considerations 10.1.1 Initial Thoughts In order to understand the need for differential circuits, let us first consider an example. Example 10.1 Having learned the design of rectifiers and basic amplifier stages, an electrical engineering student constructs the circuit shown in Fig. 10.1(a) to amplify the signal produced by a microphone. Unfortunately, upon applying the result to a speaker, the student observes that the amplifier output contains a strong “humming” noise, i.e., a steady low-frequency component. Explain what happens. Solution Recall from Chapter 3 that the current drawn from the rectified output creates a ripple waveform at twice the ac line frequency (50 or 60 Hz) [Fig. 10.1(b)]. Examining the output of the commonemitter stage, we can identify two components: (1) the amplified version of the microphone signal and (2) the ripple waveform present on VCC. For the latter, we can write Vout = VCC , RCIC; (10.1) noting that Vout simply “tracks” VCC and hence contains the ripple in its entirety. The “hum” originates from the ripple. Figure 10.1(c) depicts the overall output in the presence of both the signal and the ripple. Illustrated in Fig. 10.1(d), this phenomenon is summarized as the “supply 466 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 467 (1) Sec. 10.1 General Considerations 467 110 V 60 Hz VCC To Bias RC Vout C1 Q1 (a) Voice Signal VCC Vout t (b) t (c) VCC Ripple Signal (d) Figure 10.1 (a) CE stage powered by a rectifier, (b) ripple on supply voltage, (c) effect at output, (d) ripple and signal paths to output. noise goes to the output with a gain of unity.” (A MOS implementation would suffer from the same problem.) Exercise What is the hum frequency for a full-wave rectifier or a half-wave rectifier? How should we suppress the hum in the above example? We can increase C1, thus lowering the ripple amplitude, but the required capacitor value may become prohibitively large if many circuits draw current from the rectifier. Alternatively, we can modify the amplifier topology such that the output is insensitive to VCC. How is that possible? Equation (10.1) implies that a change in VCC directly appears in Vout, fundamentally because both Vout and VCC are measured with respect to ground and differ by RCIC . But what if Vout is not “referenced” to ground?! More specifically, what if Vout is measured with respect to another point that itself experiences the supply ripple to the same extent? It is thus possible to eliminate the ripple from the “net” output. While rather abstract, the above conjecture can be readily implemented. Figure 10.2(a) illus- trates the core concept. The CE stage is duplicated on the right, and the output is now measured between Both VX nodes X and Y and VY rise and rather than from fall by the same aXmotoungtraonudndh.eWncheatthheadpipffeenresnicfeVbCeCtwceoenntaViXns ripple? and VY remains free from the ripple. In fact, denoting the ripple by vr, we express the small-signal voltages at these nodes as vX = Avvin + vr vY = vr: (10.2) (10.3) That is, vX , vY = Avvin: Note that Q2 carries no signal, simply serving as a constant current source. (10.4) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 468 (1) 468 Chap. 10 Differential Amplifiers VCC R C1 Ripple R C2 To Bias Vout To Bias X Y Q1 Q2 v in VCC R C1 Ripple R C2 A1 X Y Q1 Q2 (a) (b) Figure 10.2 Use of two CE stages to remove effect of ripple. The above development serves as the foundation for differential amplifiers: the symmetric CE stages provide two output nodes whose voltage difference remains free from the supply ripple. 10.1.2 Differential Signals , apLasintregtodetnvmauRidlspCectr,o2eswmtirugeeprnmnodanalitreioanenmcstthts“lpeyailditcfialXiepcr,cpa”uatliytniohtdnteohrYfeeinbFiaynairgpde“.udwi1tnita0sipso.it2ghni(nnaatsgao)el”,atecconsuadttrnahrbrceeeelniclbstia.hnaliWlsgnetgeehoaamacfthQartheyo2feteth[hrdeFeeurnirpgaecl.sfeioc1tprha0eote.e3yiwn(saaottp)anf]gpod.eereUarVcrnioofifunnottsrhv.itisuXsItnnisnatogtaeugvloryeYf,fi:cQtrahsn2et vX = Avvin + vr vY = Avvin + vr  vX , vY = 0: (10.5) (10.6) (10.7) Vr VCC R C1 R C2 To Bias X To Bias Y Q1 Q2 Vin R C1 X +v in Q1 VCC R C2 Y Q2 −v in (a) (b) (c) Figure 10.3 (a) Application of one input signal to two CE stages, (b) use of differential input signals, (c) generation of differential phases from one signal. For the signal components to enhance each other at the output, we can invert one of the input BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 469 (1) Sec. 10.1 General Considerations 469 phases as shown in Fig. 10.3(b), obtaining vX = Avvin + vr vY = ,Avvin + vr (10.8) (10.9) and hence vX , vY = 2Avvin: (10.10) Compared to the circuit of Fig. 10.2(a), this topology provides twice the output swing by exploiting the amplification capability of the duplicate stage. , The reader may wonder how vin can be generated. Illustrated in Fig. 10.3(c), a simple approach is to utilize a transformer to convert the microphone signal to two components bearing a phase difference of 180 . Our thought process has led us to the specific waveforms in Fig. 10.3(b): the circuit senses two inputs that vary by equal and opposite amounts and generates two outputs that behave in a similar fashion. These waveforms are examples of “differential” signals and stand in contrast to “single-ended” signals—the type to which we are accustomed from basic circuits and previous chapters of this book. More specifically, a single-ended signal is one measured with respect to the common ground [Fig. 10.4(a)] and “carried by one line,” whereas a differential signal is measured between two nodes that have equal and opposite swings [Fig. 10.4(b)] and is thus “carried by two lines.” VCC Vin Vout Q1 (a) VCC Q1 Q2 V1 Output VCM Differential Signal 2V0 Input Differential Signal V2 t (b) (c) Figure 10.4 (a) Single-ended signals, (b) differential signals, (c) illustration of common-mode level. Figure 10.4(c) opposite amounts summarizes and have the the foregoing same average (ddecv)elleovpeml,eVnCt.MH,ewrei,thV1reaspnedcVt t2ovgarroyunbdy:equal and V1 = V0 sin !t + VCM V2 = ,V0 sin !t + VCM (10.11) (10.12) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 470 (1) 470 Chap. 10 Differential Amplifiers S4Vin0c.eWeeacmhaoyfaVls1o opposite amounts and say VV12 around has a peak-to-peak swing of and V2 a fixed are differential level, VCM . signals 2V0, we say to emphasize the that “differential they vary by swing” is equal and The dc voltage that is common to both V1 and V2 [VCM in Fig. 10.4(c)] is called the “common- mode (CM) level.” That is, in the absence of differential signals, the two nodes remain at a , potential equal to VCM with respect to the global ground. For example, in the transformer of Fig. 10.3(c), +vin and vin display a CM level of zero because the center tap of the transformer is grounded. Example 10.2 How can the transformer of Fig. 10.3(c) produce an output CM level equal to +2 V. Solution The center tap can simply be tied to a voltage equal to +2 V (Fig. 10.5). v in1 v in1 +2 V Figure 10.5 2 V v in2 v in2 t Exercise Does the CM level change if the inputs of the amplifier draw a bias current? Example 10.3 Determine the common-mode level at the output of the circuit shown in Fig. 10.3(b). Solution In the absence of signals, VX RC1 = RC2 and IC denotes Interestingly, the ripple affects = VY = VCC , RCIC (with respect the bias VCM but current not the of Q1 and differential Q2. Thus, output. to ground), where VCM = VCC , RC = RC IC . Exercise If a resistor of value R1 is inserted between VCC and the top terminals of RC1 and RC2, what is the output CM level? Our observations regarding supply ripple and the use of the “duplicate stage” provide suf- ficient justification for studying differential signals. But, how about the common-mode level? , What is the significance that the ripple appears in oVfCVMCMbut=noVt CinCthe RCIC in the above example? Why differential output? We will answer is it interesting these important questions in the following sections. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 471 (1) Sec. 10.2 Bipolar Differential Pair 471 10.1.3 Differential Pair Before formally introducing the differential pair, we must recognize that the circuit of Fig. 10.4(b) senses two inputs and can therefore serve as A1 in Fig. 10.2(b). This observation leads to the differential pair. While sensing and producing differential signals, the circuit of Fig. 10.4(b) suffers from some drawbacks. Fortunately, a simple modification yields an elegant, versatile topology. Illustrated in Fig. 10.6(a), the (bipolar) “differential pair”1 is similar to the circuit of Fig. 10.4(b), except that the emitters of Q1 and Q2 are tied to a constant current source rather than to ground. We call IEE the “tail current source.” The MOS counterpart is shown in Fig. 10.6(b). In both cases, the sum of the transistor currents is equal to the tail current. Our objective is to analyze the large-signal and small-signal behavior of these circuits and demonstrate their advantages over the “single-ended” stages studied in previous chapters. RC Vin1 X Q1 VCC RC Y Q2 Vin2 RD Vin1 X M1 VDD RD Y M2 Vin2 I EE I SS (a) (b) Figure 10.6 (a) Bipolar and (b) MOS differential pairs. For each differential pair, we begin with a qualitative, intuitive analysis and subsequently formulate the large-signal and small-signal behavior. We also assume each circuit is perfectly symmetric, i.e., the transistors are identical and so are the resistors. 10.2 Bipolar Differential Pair 10.2.1 Qualitative Analysis It is instructive to first examine the bias conditions of the circuit. Recall from Section 10.1.2 that in the absence of signals, differential nodes reside at the common-mode level. We therefore draw the pair as shown in Fig. 10.7, with the two inputs tied to VCM to indicate no signal exists at the input. By virtue of symmetry, VBE1 = VBE2 IC1 = IC2 = IEE 2 ; (10.13) (10.14) where the collector and emitter currents are assumed equal. We say the circuit is in “equilibrium.” Thus, the voltage drop across each load resistor is equal to RCIEE=2 and hence VX = VY = VCC , RC IEE 2 : (10.15) 1Also called the “emitter-coupled pair” or the “long-tailed pair.” BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 472 (1) 472 Chap. 10 Differential Amplifiers VCC R C1 R C2 VCM X Q1 Y Q2 I EE R C1 = R C2 = R C Figure 10.7 Response of differential pair to input CM change. In other words, if the two input voltages are equal, so are the two outputs. We say a zero dif- ferential input produces a zero differential output. The circuit also “rejects” the effect of supply , ripple: if VCC experiences a change, the differential output, VX VY , does not. Are Q1 and Q2 in the active region? To avoid saturation, the collector voltages must not fall below the base voltages: VCC , RC IEE 2  VCM ; (10.16) revealing that VCM cannot be arbitrarily high. Example 10.4 A bipolar differential pair employs a load resistance of 1 k and a tail current of 1 mA. How close to VCC can VCM be chosen? Solution Equation 10.16 gives VCC , VCM  RC IEE 2  0:5 V: (10.17) (10.18) That is, VCM must remain below VCC by at least 0.5 V. Exercise What value of RC allows the input CM level to approach VCC is the transistors can tolerate a base-collector forward bias of 400 mV? Now, let us vary VCM in Fig. 10.7 by a small amount and determine the circuit’s response. In- terestingly, Eqs. (10.13)-(10.15) remain unchanged, thereby suggesting that neither the collector current nor the collector voltage of the transistors is affected. We say the circuit does not respond to changes in the input common-mode level; or the circuit “rejects” input CM variations. Figure 10.8 summarizes these results. The “common-mode rejection” capability of the differential pair distinctly sets it apart from our original circuit in Fig. 10.4(b). In the latter, if the base voltage of Q1 and Q2 changes, so do their collector currents and voltages (why?). The reader may recognize that it is the tail current source in the differential pair that guarantees constant collector currents and hence rejection of the input CM level. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 473 (1) Sec. 10.2 Bipolar Differential Pair Upper Limit of VCM to Avoid Saturation VCM1 VCM2 Figure 10.8 Effect of VCM1 and VCM2 at output. 473 R C I EE 2 VCC VX , VY With our treatment of the common-mode response, we now turn to the more interesting case of differential response. We hold one input constant, vary the other, and examine the currents flowing in the two transistors. While not exactly differential, such input signals provide a simple, intuitive starting point. Recall that IC1 + IC2 = IEE. Consider the circuit shown in Fig. 10.9(a), where the two transistors are drawn with a vertical tothhfeefsrbeetbasytoetuveromnltipanhggaesQsiz2oefotQfhfa.1tTaQhna1dt senses a Q2 is so is, more positive base large, we postulate voltage. that Q1 Since the difference between “hogs” all of the tail current, VCC = 2.5 V VCC = 2.5 V RC RC RC RC Vin1 = +2 V X Vout Q1 Y Q2 Vin2 = +1 V Vin1 = +1 V Vout Y X Q2 Q1 Vin2 = +2 V P I EE P I EE (a) (b) Figure 10.9 Response of bipolar differential pair to (a) large positive input difference and (b) large negative input difference. IC1 = IEE IC2 = 0; (10.19) (10.20) and hence VX = VCC , RCIEE VY = VCC: (10.21) (10.22) 6 But, how can we i.e., IC1 IEE and IpCro2v=e t0h.atIfQQ12incadrereiedsaabnsoarpbpsreaclliaobfleIEcuEr?reLnte,tthuesnaistssubmaeset-heamt iittteirs not so; voltage must reach a typical value of, say, 0.8 V. With its base held at +1 V, the device therefore requires an of emitter Vin1 , voltage VP = of VP +2 V  , 0:2 0:2 V. V H=ow1e:v8erV, !th! iSs imnceeanwsitthhatVQBE1 sustains = 1:8 a base-emitter voltage V, a typical transistor cVaBrEri1es=an1e:8noVrmanodusVcPurren0t:,2anVdcsainnnceotIoCc1ccuar.nInnoftaecxtc, eweidthIEa Ety,pwicealcobnacselu-edme tihttaetr the conditions voltage of 0.8 V, Q1 holds node P at approximately +1:2 V, ensuring that Q2 remains off. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 474 (1) 474 Chap. 10 Differential Amplifiers Symmetry of the circuit implies that swapping the base voltages of Q1 and Q2 reverses the situation [Fig. 10.9(b)], giving IC2 = IEE IC1 = 0; (10.23) (10.24) and hence VY = VCC , RCIEE VX = VCC: (10.25) (10.26) The above experiments reveal that, as the difference between the two inputs departs from zero, the differential pair “steers” the tail current from one transistor to the other. In fact, based on Eqs. (10.14), (10.19), and (10.23), we can sketch the collector currents of Q1 and Q2 as a function of the input difference [Fig. 10.10(a)]. We have not yet formulated these characteristics but we do observe that the collector current of each transistor goes from 0 to IEE if jVin1 , Vin2j becomes sufficiently large. Q1 Q2 Q1 Q2 Q1 Q2 I EE I C2 I EE I C1 2 0 Vin1− Vin2 (a) VX VY VCC VCC − R C I EE 2 VCC− R C I EE 0 Vin1− Vin2 (b) Figure 10.10 Variation of (a) collector currents and (b) output voltages as a function of input. It is also important to note that VX and VY vary differentially in response to Vin1 ,Vin2. From Eqs. (10.15), (10.21), and (10.25), we can sketch the input/output characteristics of the circuit as shown in Fig. 10.10(b). That is, a nonzero differential input yields a nonzero differential output— , a a behavior in sharp contrast to the CM response. common-mode level for them. Given by VCC Since RC IVEXEa=n2d, VY this are differential, we can define quantity is called the “output CM level.” Example 10.5 A bipolar differential pair employs a tail current of 0.5 mA and a collector resistance of 1 k . What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume VCC = 2:5 V. Solution , IVfCICEE is completely steered, the transistor carrying the current lowers its collector voltage to RCIEE = 2 V. Thus, the base voltage must remain below this value so as to avoid saturation. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 475 (1) Sec. 10.2 Bipolar Differential Pair 475 Exercise Repeat the above example if the tail current is raised to 1 mA. + ∆V VCM , In the last step of our qualitative analysis, we “zoom in” around Vin1 Vin2 = 0 (the equilib- rium condition) and study the circuit’s behavior for a small input difference. As illustrated in Fig. 10.11(a), the base voltage VCM by the same amount. IC2 decreases by the same oWf eQs1urims riaseistehdatfrIoCm1 amount: VinCcMreabseysslVighwtlhyilaendth,astinocfeQIC2 1is+loIwCe2re=d from IEE, VCC RC RC X Y Q1 Q2 P I EE VCM − ∆V + ∆V VCM X Y Q1 Q2 VCM P ∆VP I EE − ∆V (a) (b) Figure 10.11 (a) Differential pair sensing small, differential input changes, (b) hypothetical change at P . IC1 = IEE 2 + I IC2 = IEE 2 , I: (10.27) (10.28) WwHooewumldiusssitmtIhpelryreelbfaoetereedqctuooamlptoVutg?emIthfetVhceh. aeInnmgtihetteeinrdsVifoPffe.rQen1tiaanldpaQir2, were directly tied to ground, then I however, node P is free to rise or fall. is Suppose, as equal to V shown in Fig. 10.11(b), , VP and hence VP rises by VP . As a result, the net increase in VBE1 IC1 = gmV , VP : (10.29) Similarly, the net decrease in VBE2 is equal to V + VP , yielding IC2 = ,gmV + VP : (10.30) , But recall from (10.27) and (10.28) that IC1 must be equal to IC2, dictating that gmV , VP  = gmV + VP  (10.31) and hence VP = 0: (10.32) Interestingly, the tail voltage remains constant if the two inputs vary differentially and by a small amount—an observation critical to the small-signal analysis of the circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 476 (1) 476 Chap. 10 Differential Amplifiers The reader may wonder why (10.32) does not hold if V is large. Which one of the above equations is violated? For a large differential input, Q1 and Q2 carry rents, thus exhibiting unequal transconductances and prohibiting the significantly different cur- omission of gm’s from the two sides of (10.31). With VP = 0 in Fig. 10.11(a), we can rewrite (10.29) and (10.30) respectively as IC1 = gmV IC2 = ,gmV (10.33) (10.34) and VX = ,gmV RC VY = gmV RC: (10.35) (10.36) The differential output therefore goes from 0 to VX , VY = ,2gmV RC: (10.37) We define the small-signal differential gain of the circuit as Av = Change in Di Change in Di erential Output erential Input = ,2gmV 2V RC = ,gmRC: (10.38) (10.39) (10.40) (Note that the change in the differential input is equal to 2V .) This expression is similar to that of the common-emitter stage. Example 10.6 Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V. Solution With VCC = 2 V, the power budget translates to a tail current of 0.5 mA. Each transistor thus car- ries a 104 cu,rr1e.nIttoffo0ll.o2w5smthAatnear equilibrium, providing a transconductance of 0:25 mA=26 mV = RC = jAV gm j = 1040 : (10.41) (10.42) Exercise Redesign the circuit for a power budget of 0.5 mW and compare the results. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 477 (1) Sec. 10.2 Bipolar Differential Pair 477 Example 10.7 Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains, collector resistances, and supply voltages. Solution The gain of the differential pair is written from (10.40) as jAV;di j = gm1;2RC; (10.43) where gm1;2 denotes the transconductance of each of the two transistors. For a CE stage jAV;CEj = gmRC: (10.44) Thus, gm1;2RC = gmRC (10.45) and hence IEE 2VT = IC VT ; (10.46) where IEE=2 is the bias current of each transistor in the differential pair, and IC represents the bias current of the CE stage. In other words, IEE = 2IC; (10.47) indicating that the differential pair consumes twice as much power. This is one of the drawbacks of differential circuits. Exercise If both circuits are designed for the same power budget, equal collector resistances, and equal supply voltages, compare their voltage gains. 10.2.2 Large-Signal Analysis Having obtained insight into the operation of the bipolar differential pair, we now quantify its large-signal behavior, aiming to formulate the input/output characteristic of the circuit (the sketches in Fig. 10.10). Not having seen any large-signal analysis in the previous chapters, the reader may naturally wonder why we are suddenly interested in this aspect of the differential pair. Our interest arises from (a) the need to understand the circuit’s limitations in serving as a linear amplifier, and (b) the application of the differential pair as a (nonlinear) current-steering circuit. In order to derive the relationship between the differential input and output of the circuit, we first note from Fig. 10.12 that Vout1 = VCC , RCIC1 Vout2 = VCC , RCIC2 (10.48) (10.49) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 478 (1) 478 Chap. 10 Differential Amplifiers VCC RC RC Vout1 Vout Vout2 Vin1 Q1 Q2 Vin2 P I EE Figure 10.12 Bipolar differential pair for large-signal analysis. and hence Vout = Vout1 , Vout2 = ,RCIC1 , IC2: (10.50) (10.51) We VA 1 must therefore compute IC1 and IC2 in = , and recalling from Chapter 4 that terms VBE of the input difference. Assuming = VT lnIC=IS, we write a KVL = 1 and around the input network, Vin1 , VBE1 = VP = Vin2 , VBE2; (10.52) obtaining Vin1 , Vin2 = VBE1 , VBE2 = VT ln IC1 IS1 , VT ln IC2 IS2 = VT ln IC1 IC2 : Also, a KCL at node P gives (10.53) (10.54) (10.55) IC1 + IC2 = IEE: (10.56) Equations (10.55) and (10.56) contain two unknowns. Substituting for IC1 from (10.55) in (10.56) yields IC2 exp Vin1 , VT Vin2 + IC2 = IEE (10.57) and, therefore, IC2 = 1 + exp IEE Vin1 , VT Vin2 : (10.58) The symmetry of the circuit with respect to Vin1 and Vin2 and with respect to IC1 and IC2 suggests that IC1 exhibits the same behavior as (10.58) but with the roles of Vin1 and Vin2 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 479 (1) Sec. 10.2 Bipolar Differential Pair 479 exchanged: IC1 = 1 + IEE exp Vin2 , VT Vin1 = IEE 1+ exp exp Vin1 , Vin2 Vin1 V,TVin2 VT : (10.59) (10.60) Alternatively, the reader can substitute for IC2 from (10.58) in (10.56) to obtain IC1. Equations (10.58) and (10.60) play a crucial role in our quantitative understanding of the differential pair’s operation. Vin2=VT ! 0 and In particular, if Vin1 , Vin2 is very negative, then expVin1 , IC1 ! 0 IC2 ! IEE; (10.61) (10.62) as predicted expVin1 , by our qualitative analysis Vin2=VT ! 1 and [Fig. 10.9(b)]. Similarly, if Vin1 , Vin2 is very positive, IC1 ! IEE IC2 ! 0: (10.63) (10.64) What is meant by “very” negative IEE if Vin1 , Vin2 = ,10VT ? Since oerxppo,si1ti0ve?F4o:r5e4xam1p0l,e,5c, an we say IC1  0 and IC2  IC1  IEE  4:54  10,5 1 + 4:54  10,5  4:54  10,5IEE (10.65) (10.66) and IC2  1 + IEE 4:54  10,5  IEE1 , 4:54  10,5: (10.67) (10.68) IcnomotphleertewlyortodsQ, Q2.1 carries only 0:0045 of the tail current; and IEE can be considered steered Example 10.8 Determine the differential input voltage that steers 98 of the tail current to one transistor. Solution We require that IC1 = 0:02IEE  IEE exp Vin1 , VT Vin2 (10.69) (10.70) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 480 (1) 480 Chap. 10 Differential Amplifiers and hence Vin1 , Vin2  ,3:91VT : (10.71) We off. often Note say that tahdisifvfaelrueentrieaml ianipnustinodfe4pVeTndiesnstuofffiIcEieEntatnodtuISrn. one side of the bipolar pair nearly Exercise What differential input is necessary to steer 90% of the tail current? For the output voltages in Fig. 10.12, we have Vout1 = VCC , RCIC1 = VCC , RC IEE 1+ exp exp Vin1 , Vin1 V,T VT Vin2 Vin2 (10.72) (10.73) and Vout2 = VCC , RCIC2 = VCC , RC 1 + exp IEE Vin1 , VT Vin2 : (10.74) (10.75) Of particular importance is the output differential voltage: Vout1 , Vout2 = ,RCIC1 , IC2 = RC IEE 1 1 , + exp exp Vin1 Vin1 , V,T VT Vin2 Vin2 = ,RC IEE tanh Vin1 , Vin2 2VT : (10.76) (10.77) (10.78) Figure 10.13 summarizes the results, indicating that the differential output voltage begins from a a“jfoVusfdani,nitcfu1tfRrie,oaCrtneeIVndoEit”fniEaV2vljiaainmlsn1upVue,usionttVf1roie+f,nm24RVaVfCiioTnnrI2wErebEelela1lcft0iobov4merelalmoeywsvVsevmtreh“yraisyslwnlpveivgaotaclasluhitutieeviesvsfe”eood.rtfhFilfjierfVnoedeirmnaeif1rnfEte,oixrapealVenmriitnanipatp2illjuoe,ptn1a,a.n0gird.r8,ar,tdehwuaeacerlhelrbyeesycboaecgcosnoanitmczulereuastdtheiaandtglilenetvehveaaenrtl Example 10.9 Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q1 and Q2 remain in the forward active region. Solution For the sinusoids depicted in Fig. 10.14(b), the circuit operates linearly because the maximum BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 481 (1) Sec. 10.2 Bipolar Differential Pair 481 I C2 I EE I C1 2 0 I EE Vin1− Vin2 Vout1 Vout2 VCC VCC − R C I EE 2 VCC− R C I EE 0 Vin1− Vin2 Vout1 − Vout2 0 Figure 10.13 Variation of currents and voltages as a function of input. + R C I EE Vin1− Vin2 − R C I EE VCC Vin1 RC Vout1 RC Vout2 VCM Vin2 Vin1 Q1 Q2 Vin2 P I EE (a) (b) Vout2 VCM Vout1 (d) Figure 10.14 1 mV Vin1 VCM 100 mV t 1 mV x g mR C Vin2 t1 (c) Vout2 Vout1 t t1 (e) t VCC VCC − R C I EE 2 VCC− R C I EE t  differential input is equal to 2 mV. The outputs are therefore sinusoids having a peak amplitude omfa1ximmuVmingpmutRdCiffe[Freingc. e1o0f.14(2d0)0].mOVn, 50 mV above VCM and Vin2 reaches 50 the other hand, the sinusoids in Fig. 10.14(c) force a mtuVrnibnegloQw1VoCrMQ2(aotftf.=Fotr1)e,xQam1 palbes,oarsbsVmin1osatpopfrtohaechtaeisl current, thus producing Vout1  VCC , RCIEE Vout2  VCC: (10.79) (10.80) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 482 (1) 482 Chap. 10 Differential Amplifiers j , j Thereafter, the outputs remain saturated until Vin1 Vin2 falls to less than 100 mV. The result is sketched in Fig. 10.14(e). We say the circuit operates as a “limiter” in this case, playing a role similar to the diode limiters studied in Chapter 3. Exercise What happens to the above results if the tail current is halved? 10.2.3 Small-Signal Analysis Our brief investigation of the differential pair in Fig. 10.11 revealed that, for small differential inputs, the tail node maintains a constant voltage (and hence is called a “virtual ground”). We also obtained a voltage gain equal to gmRC. We now study the small-signal behavior of the circuit in greater detail. As explained in previous chapters, the definition of “small signals” is somewhat arbitrary, but the requirement is that the input signals not influence the bias currents of Q1 and Q2 appreciably. In transconductances—the same other words, the two transistors must exhibit approximately condition required for node P to appear as virtual ground. In equal prac- tice, an input difference of less than 10 mV is considered “small” for most applications. , 1 scmhaaAnllsg-sesusigminnianelgamcphoedirnfeeplcuottfsatyhnmed mcmieructsrutyi,staaatnsissfihydoevwailnn1tai=nil Fciugvr.irn1e2n0t.f1os5ro(udari)fc.feHe,reearnnetd,iavVlinoA1pea=rnadtiovni,n.2wNreoetpceroetnhssaettnrutthcsetmttaahilell current source is replaced with an open circuit. As with the foregoing large-signal analysis, let us write a KVL around the input network and a KCL at node P : v1 r1 vin1 , v1 + gm1v1 + vr=22vP+=gmv2inv22,=v02: With r1 = r2 and gm1 = gm2, (10.82) yields (10.81) (10.82) v1 = ,v2 (10.83) and since vin1 = ,vin2, (10.81) translates to 2vin1 = 2v1: (10.84) That is, vP = vin1 , v1 = 0: (10.85) (10.86) Thus, the small-signal model confirms the prediction made by (10.32). In Problem 28, we prove that this property holds in the presence of Early effect as well. The virtual-ground nature of node P for differential small-signal inputs simplifies the analysis considerably. Since vP = 0, this node can be shorted to ac ground, reducing the differential pair of Fig. 10.15(a) to two “half circuits” [Fig. 10.15(b)]. With each half resembling a common- emitter stage, we can write vout1 = ,gmRCvin1 (10.87) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 483 (1) Sec. 10.2 Bipolar Differential Pair 483 v in1 v in1 RC RC r π1 vπ1 gm1vπ1 gm2vπ2 P (a) vπ2 r π2 RC RC r π1 vπ1 gm1vπ1 gm2vπ2 vπ2 r π2 v in2 v in2 (b) VCC RC RC Vin1 Q1 Q2 Vin2 (c) Figure 10.15 (a) Small-signal model of bipolar pair, (b) simplified small-signal model, (c) simplied diagram. vout2 = ,gmRCvin2: (10.88) It follows that the differential voltage gain of the differential pair is equal to vout1 vin1 , , vout2 vin2 = ,gmRC; (10.89) the same as that expressed by (10.40). For simplicity, we may draw the two half circuits as in Fig. 10.15(c), with the understanding that the incremental inputs are small and differential. Also, since the two halves are identical, we may draw only one half. Example 10.10 Compute the differential gain of the circuit shown in Fig. 10.16(a), where ideal current sources are used as loads to maximize the gain. Solution With ideal current sources, the Early effect in Q1 and Q2 cannot be neglected, and the half circuits must be visualized as depicted in Fig. 10.16(b). Thus, vout1 = ,gmrOvin1 vout2 = ,gmrOvin2 (10.90) (10.91) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 484 (1) 484 Chap. 10 Differential Amplifiers VCC Vin1 Vout Q1 Q2 P I EE Vin2 v in1 Q1 v out r O1 r O2 v in2 Q2 (a) (b) Figure 10.16 and hence vout1 vin1 , vout2 , vin2 = ,gmrO: (10.92) Exercise Calculate the gain for VA = 5 V. Example 10.11 Figure 10.17(a) illustrates an implementation of the topology shown in Fig. 10.16(a). Calculate the differential voltage gain. Vb Q3 Vin1 Q4 Vout Q1 Q2 VCC Vin2 P I EE (a) Figure 10.17 Q3 v in1 Q1 v out (b) Solution Noting that each pnp device introduces a resistance of rOP at the output nodes and drawing the half circuit as in Fig. 10.17(b), we have vout1 vin1 , vout2 , vin2 = ,gmrONjjrOP ; (10.93) where rON denotes the output impedance of the npn transistors. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 485 (1) Sec. 10.2 Bipolar Differential Pair 485 Exercise Calculate the gain if Q3 and Q4 are configured as diode-connected devices. We must emphasize that the differential voltage gain is defined as the difference between the outputs divided by the difference between the inputs. As such, this gain is equal to the single- ended gain of each half circuit. We now make an observation that proves useful in the analysis of differential circuits. As noted above, the symmetry of the circuit (gm1 = gm2) establishes a virtual ground at node P in Fig. 10.12 if the incremental inputs are small and differential. This property holds for any other node that appears on the axis of symmetry. For example, the two resistors shown in Fig. 10.18 acrmeaotuenatsv.2irAtudadligtiroonuanldexaat mXplief s(1m)aRke1 = R2 and (2) nodes A and B vary by equal and opposite this concept clearer. We assume perfect symmetry in each case. ∆V A R1 R2 B ∆V X Figure 10.18 Example 10.12 1 Determine the differential gain of the circuit in Fig. 10.19(a) if VA . Vb Q3 VCC Q4 Vout R1 R2 Q3 Vin1 Q1 Q2 P I EE Vin2 Vin1 Q1 Vout R1 (a) (b) Figure 10.19 Solution Drawing one of the half circuits as shown in Fig. 10.19(b), we express the total resistance seen at the collector of Q1 as Rout = rO1jjrO3jjR1: (10.94) Thus, the voltage gain is equal to Av = ,gm1rO1jjrO3jjR1: (10.95) 2Since the resistors are linear, the signals need not be small in this case. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 486 (1) 486 Chap. 10 Differential Amplifiers Exercise Repeat the above example if R1 6= R2. Example 10.13 1 Calculate the differential gain of the circuit illustrated in Fig. 10.20(a) if VA . VCC X Q3 Q4 X Q3 Vin1 R1 R2 Vout Q1 Q2 P I EE Vin2 v in1 Q1 R1 v out1 (a) (b) Figure 10.20 Solution For small differential inputs and outputs, VX remains constant, leading to the conceptual half circuit shown in Q4 experience a Fig. 10.20(b)—the same as that constant base-emitter voltage in in the above example. This both cases, thereby serving is because as current Q3 and sources and exhibiting only an output resistance. It follows that Av = ,gm1rO1jjrO3jjR1: (10.96) Exercise Calculate the gain if VA = 4 V for all transistors, R1 = R2 = 10 k , and IEE = 1 mA. Example 10.14 Determine the gain of the degenerated differential pairs shown in Figs. 10.21(a) and (b). Assume VA = 1. Solution In the topology of Fig. 10.21(a), node P is a virtual ground, yielding the half circuit depicted in BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 487 (1) Sec. 10.2 Bipolar Differential Pair 487 RC Vin1 X Q1 Vout VCC RC Y Q2 Vin2 RE P I R EE E VCC RC Vin1 X Q1 Vout RC Y Q2 Vin2 I EE RE I EE (a) (b) RC v in1 Q1 Figure 10.21 v out RE (c) RC v in1 Q1 v out RE 2 (d) Fig. 10.21(c). From Chapter 5, we have Av = , RC RE + 1 gm : (10.97) In the circuit of Fig. other words, if RE is 10.21(b), the line of symmetry passes through the regarded as two RE=2 units in series, then the node “midpoint” of RE. In between the units acts as a virtual ground [Fig. 10.21(d)]. It follows that Av = , RC RE 2 + 1 gm : (10.98) The two circuits provide equal gains if the pair in Fig. 10.21(b) incorporates a total degeneration resistance of 2RE. Exercise Design each circuit for a gain VA = 1, and RE = 2=gm. of 5 and power consumption of 2 mW. Assume VCC = 2:5 V, I/O Impedances For a differential pair, we can define the input impedance as illustrated in Fig. 10.22(a). From the equivalent circuit in Fig. 10.22(b), we have v1 rpi1 = iX = , v2 r2 : (10.99) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 488 (1) 488 Chap. 10 Differential Amplifiers RC iX Q1 VCC RC Q2 vX I EE iX RC RC iX r π1 vπ1 gm1vπ1 gm2vπ2 P vπ2 r π2 vX (a) (b) Figure 10.22 (a) Method for calculation of differential input impedance, (b) equivalent circuit of (a). Also, vX = v1 , v2 = 2r1iX: (10.100) (10.101) It follows that vX iX = 2rpi1; (10.102) as if the two base-emitter junctions appear in series. The above quantity is called the “differential input impedance” of the circuit. It is also possible to define a “single-ended input impedance” with the aid of a half circuit (Fig. 10.23), obtaining VCC RC iX Q1 vX Figure 10.23 Calculation of single-ended input impedance. vX iX = r1: (10.103) This result provides no new information with respect to that in (10.102) but proves useful in some calculations. In a manner similar to the foregoing development, the reader can show that the differential and single-ended output impedances are equal to 2RC and RC, respectively. 10.3 MOS Differential Pair Most of the principles studied in the previous section for the bipolar differential pair apply directly to the MOS counterpart as well. For this reason, our treatment of the MOS circuit in this section is more concise. We continue to assume perfect symmetry. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 489 (1) Sec. 10.3 MOS Differential Pair 489 10.3.1 Qualitative Analysis Figure 10.24(a) depicts the MOS pair with the two inputs tied to VCM , yielding VDD RD RD VCM X M1 Y M2 I SS Figure 10.24 Response of MOS differential pair to input CM variation. ID1 = ID2 = ISS 2 (10.104) and VX = VY = VDD , RD ISS 2 : (10.105) That is, a zero differential input gives a zero differential output. Note that the output CM level is equal to VDD , RDISS=2. For our subsequent derivations, it is useful to compute the “equilibrium overdrive voltage” of MVT1Han2d. CMa2rr,yiVnGgSa,cuVrTreHnteoqfuIilS:.SW=2e, assume  = each device 0 and hence ID = 1=2nCoxW=LVGS exhibits an overdrive of , VGS , VT H equil: = vuut ISS nCox W L : (10.106) As expected, a greater tail current or a smaller W=L translates to a larger equilibrium overdrive. , To guarantee fall below VCM thaVtTMH :1 and M2 operate in saturation, we require that their drain voltages not VDD , RD ISS 2 VCM , VTH: (10.107) It can also be observed that a change in VY undisturbed. The circuit thus rejects VCM input cannot alter ID1 CM variations. = ID2 = ISS =2, leaving VX and Example 10.15 A MOS differential pair is driven with an input CM level of 1.6 V. If ISS = 0:5 mA, VT H = 0:5 V, and VDD = 1:8 V, what is the maximum allowable load resistance? Solution From (10.107), we have RD 2 VDD , VCM ISS + VT H 2:8 k : (10.108) (10.109) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 490 (1) 490 Chap. 10 Differential Amplifiers We may suspect that this limitation in turn constrains the voltage gain of the circuit, as explained later. Exercise What is the maximum tail current if the load resistance is 5 k . Figure 10.25 well above Vin2 illustrates the response of the MOS pair to large differential inputs. [Fig. 10.25(a)], then M1 carries the entire tail current, generating If Vin1 is VDD VDD RD RD RD RD Vin1 Vout X M1 Y M2 Vin2 Vin1 Vout Y X M2 M1 Vin2 I SS I SS (a) (b) I SS I D2 I SS I D1 2 VX VY 0 Vin1− Vin2 (c) VDD VDD − R D I SS 2 VDD− R D I SS 0 Vin1− Vin2 Figure 10.25 (a) Response of MOS differential pair to very positive input, (b) response of MOS differential pair to very negative input, (c) qualitative plots of currents and voltages. VX = VDD , RDISS VY = VDD: Similarly, if Vin2 is well above Vin1 [Fig. 10.25(b)], then VX = VDD VY = VDD , RDISS: (10.110) (10.111) (10.112) (10.113) The circuit therefore steers the tail current from one side to the other, producing a differential output in response to a differential input. Figure 10.25(c) sketches the characteristics of the circuit. Let us now examine the circuit’s behavior for a small input difference. Depicted in Fig. 10.26(a), such a scenario maintains VP constant because Eqs. (10.27)-(10.32) apply to this case equally well. It follows that BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 491 (1) Sec. 10.3 MOS Differential Pair 491 + ∆V VCM RD X M1 P VDD RD Y M2 VCM I SS − ∆V Figure 10.26 Response of MOS pair to small differential inputs. ID1 = gmV ID2 = ,gmV (10.114) (10.115) and VX , VY = ,2gmRDV: (10.116) As expected, the differential voltage gain is given by Av = ,gmRD; (10.117) similar to that of a common-source stage. Example 10.16 Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1.6 V. Assume nCox = 100 A=V2,  = 0, and VDD = 1:8 V. Solution From the power budget and the supply voltage, we have ISS = 1:11 mA: (10.118) The output CM level (in the absence of signals) is equal to VCM;out = VDD , RD ISS 2 : (10.119) For VCM;out = 1:6 V, each resistor must sustain a voltage drop of no more than 200 mV, thereby assuming a maximum value of RD = 360 : (10.120) r Setting gmRD each transistor = 5, we carries a must choose the drain current of transistor ISS=2, dimensions such that gm = 5=360 . Since gm = 2nCox W L ISS 2 ; (10.121) and hence W L = 1738: (10.122) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 492 (1) 492 Chap. 10 Differential Amplifiers The large aspect ratio arises from the small drop allowed across the load resistors. Exercise If the aspect ratio must remain below 200, what voltage gain can be achieved? Example 10.17 What is the maximum allowable input CM level in the above example if VT H = 0:4 V? Solution We rewrite (10.107) as VCM;in VDD , RD ISS 2 + VT H VCM;out + VTH: (10.123) (10.124) This is conceptually illustrated in Fig. 10.27. Thus, VDD RD RD VCM,in X M1 Y M2 I SS VCM,in VTH VCM,out Figure 10.27 VCM;in 2 V: (10.125) Interestingly, the input CM level can comfortably remain at VDD. In contrast to Example 10.5, the constraint on the load resistor in this case arises from the output CM level requirement. Exercise Does the above result hold if VT H = 0:2 V. Example 10.18 The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load resistors. If the two circuits are designed for the same voltage gain and the same supply voltage, discuss the choice of (a) transistor dimensions for a given power budget, (b) power dissipation for given transistor dimensions. Solution (a) For the two circuits to consume the same amount of power ID1 = ISS = 2ID2 = 2ID3; i.e., BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 493 (1) Sec. 10.3 MOS Differential Pair 493 VDD R v in M1 R Vin1 M1 VDD R M2 Vin2 I SS Figure 10.28 each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. Equation (10.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. (b) If the transistors in both circuits have the same dimensions, then the tail current of the differential pair must be twice the bias current of the CS stage for M1-M3 to have the same transconductance, doubling the power consumption. Exercise Discuss the above results if the CS stage and the differential pair incorporate equal source degeneration resistors. 10.3.2 Large-Signal Analysis As with the large-signal analysis of the bipolar pair, our objective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values. From Fig. 10.29. VDD RD RD Vout1 Vout Vout2 Vin1 M1 M2 Vin2 I SS Figure 10.29 MOS differential pair for large-signal analysis. Vout = Vout1 , Vout2 = ,RDID1 , ID2: (10.126) (10.127) , To obtain ID1 ID2, we neglect channel-length modulation and write a KVL around the input network and a KCL at the tail node: Vin1 , VGS1 = Vin2 , VGS2 ID1 + ID2 = ISS: (10.128) (10.129) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 494 (1) 494 Chap. 10 Differential Amplifiers Since ID = 1=2nCoxW=LVGS , VTH2, VGS = VT H + vuut 2ID nCox W L : Substituting for VGS1 and VGS2 in (10.128), we have Vin1 , Vin2 = = VvuutGS1n C,2oVx GWLS2pID1 , pID2: Squaring both sides yields Vin1 , Vin22 = = 2 nCox W L 2 nCox W L ID1 ISS + , ID2 , 2pID1ID2 2pID1ID2: We now find pID1ID2, 4pID1ID2 = 2ISS , nCox W L Vin1 , Vin2 2; square the result again, 16ID1ID2 =  2ISS , nCox W L Vin1 , Vin2 2 2 ; and substitute ISS , ID1 for ID2, 16ID1ISS , ID1 =  2ISS , nCox W L Vin1 , Vin2 2 2 : It follows that 16ID2 1 , 16ISSID1 +  2ISS , nCox W L Vin1 , 2 Vin22 = 0 and hence ID1 = ISS 2  s 1 4 4IS2S ,  nCox W L Vin1 , Vin22 , 2 2ISS : (10.130) (10.131) (10.132) (10.133) (10.134) (10.135) (10.136) (10.137) (10.138) (10.139) In Problem 44, we show that only the solution with the sum of the two terms is acceptable: ID1 = ISS 2 + Vin1 , 4 Vin2 s nCox W L  4ISS , nCox W L Vin1 ,  Vin22 : (10.140) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 495 (1) Sec. 10.3 MOS Differential Pair 495 The symmetry of the circuit also implies that ID2 = ISS 2 + Vin2 , 4 Vin1 s nCox W L  4ISS , nCox W L Vin2 ,  Vin12 : (10.141) That is, ID1 , ID2 = 1 2 nCox W L Vin1 , Vin2vuut 4ISS nCox W L , Vin1 , Vin22: (10.142) Equations (10.140)-(10.142) form the foundation of our understanding of the MOS differential pair. Let us now examine (10.142) closely. As expected from the characteristics in Fig. 10.25(c), the , right-hand side is an odd (symmetric) function of Vin1 Vin2, dropping to zero for a zero input difference. But, can the difference under the square root vanish, too? That would suggest that ID1 , ID2 falls to zero as Vin1 , Vin22 reaches 4ISS=nCoxW=L , an effect not predicted by our qualitative sketches in Fig. 10.25(c). Furthermore, it appears that the argument of the , square root becomes negative as Vin1 Vin22 exceeds this value! How should these results be interpreted? Implicit in our foregoing derivations is the assumption that both transistors are on. However, as jVin1 , Vin2j rises, at some point that M1 or M2 turns off, violating the above equations. We must therefore determine the input difference that places one of the transistors at the edge of conduction. This can be accomplished by equating (10.140), (10.141), but leading to lengthy algebra. Instead, we recognize from Fig. 10.30 that or if, f(o1r0.e1x4a2m) ptloe,IMSS1, Edge of Conduction ~0 + M1 VTH − I SS M2 + − VGS2 I SS Figure 10.30 MOS differential pair with one device off. approaches the edge of conduction, then its gate-source voltage falls to a value equal to VT H . Also, the gate-source voltage of M2 must be sufficiently large to accommodate a drain current of ISS : VGS1 VGS2 = = VT H VT H + vuut 2ISS nCox W L : (10.143) (10.144) It follows from (10.128) that jVin1 , Vin2jmax = vuut 2ISS nCox W L ; (10.145) where jVin1 , Vin2jmax denotes the input difference that places one transistor at the edge of conduction. Equation (10.145) is invalid for input differences greater than this value. Indeed, BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 496 (1) 496 Chap. 10 Differential Amplifiers substituting from (10.145) Vin2jmax can be related to in (10.142) also the equilibrium yields jID1 , ID2j = ISS. overdrive [Eq. (10.106)] as We also follows: note that jVin1 , jVin1 , Vin2jmax = p2VGS , VTHequil:: (10.146) The above findings are very important and stand in contrast to the behavior of the bipolar differential pair and Eq. (10.78): the MOS pair steers all of the tail current3 for jVin1 , Vin2jmax whereas the bipolar counterpart only approaches this condition for a finite input difference. Equa- tion (10.146) provides a great deal of intuition into the operation of the MOS pair. Specifically, we plot ID1 and ID2 as in Fig. 10.31(a), where Vin = Vin1 , Vin2, arriving at the differen- tial characteristics in Figs. 10.31(b) and (c). The circuit thus behaves linearly for small values of Vin and becomes completely nonlinear for Vin Vin;max. In other words, Vin;max serves as an absolute bound on the input signal levels that have any effect on the output. I SS I D2 I SS I D1 2 − ∆Vin,max 0 + ∆Vin,max (a) Vin1− Vin2 I D1 − I D2 − ∆Vin,max 0 + I SS + ∆Vin,max Vin1− Vin2 − I SS (b) Vout1 − Vout2 − ∆Vin,max 0 + R D I SS + ∆Vin,max Vin1− Vin2 − R D I SS (c) Figure 10.31 Variation of (a) drain currents, (b) the difference between drain currents, and (c) differential output voltage as a function of input. Example 10.19 Examine the input/output characteristic of a MOS differential pair if (a) the tail current is doubled, or (b) the transistor aspect ratio is doubled. p Solution (a) the Echqauraatciotenri(s1ti0c.1o4f5F)igsu. g1g0e.3st1s(cth)aetxdpoaunbdlsinhgorIiSzoSnitnacllrye.aFsuesrtheVrmino;mrea,xsibnyceaIfSaSctRorDodfoub2l.eTs,htuhse, characteristic expands vertically as well. Figure 10.32(a) illustrates the result, displaying a greater slope. V = V 3In reality, MOS devices carry a small current for GS T H , making these observations only an approximate illustration. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 497 (1) Sec. 10.3 MOS Differential Pair 497 Vout1 − Vout2 +2R D I SS − 2 ∆Vin,max − ∆Vin,max − R D I SS + R D I SS + ∆Vin,max + 2 ∆Vin,max Vin1− Vin2 −2R D I SS (a) Vout1 − Vout2 − ∆Vin,max − ∆Vin,max 2 + R D I SS + ∆Vin,max 2 Vin1− Vin2 + ∆Vin,max − R D I SS (b) Figure 10.32 (b) Doubling W=L lowers Vin;max by a factor of p2 while maintaining ISSRD constant. The characteristic therefore contracts horizontally [Fig. 10.32(b)], exhibiting a larger slope in the vicinity of Vin = 0. Exercise Repeat the above example if (a) the tail current is halved, or (b) the transistor aspect ratio is halved. Example 10.20 Design an NMOS differential pair for a power budget Assume nCox = 100 A=V2 and VDD = 1:8 V. of 3 mW and Vin;max = 500 mV. Solution The tail current must not exceed 3 mW=1:8 V = 1:67 mA. From Eq. (10.145), we write W L = 2ISS nCoxVi2n;max = 133:6: (10.147) (10.148) The value of the load resistors is determined by the required voltage gain. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 498 (1) 498 Chap. 10 Differential Amplifiers Exercise How does the above design change if the power budget is raised to 5 mW? 10.3.3 Small-Signal Analysis The small-signal analysis of the MOS differential pair proceeds in a manner similar to that in Section 10.2.3 for the bipolar counterpart. The definition of “small” signals in this case can be seen from Eq. (10.142); if jVin1 , Vin2j 4ISS nCox W L ; (10.149) then ID1 , ID2  = r21 nnCCooxxWLWL IVSiSn1V,inV1 i,n2 Vvuutin2n: 4CIoSxSWL (10.150) (10.151) Now, the differential inputs and outputs are linearly proportional, and the circuit operates linearly. We now use the small-signal model to prove that the tail node remains constant in the presence of small differential inputs. If  = 0, the circuit reduces to that shown in Fig. 10.33(a), yielding v in1 v in1 RD RD v1 gm1v1 gm2v2 v2 P (a) RC v1 gm1v1 RC gm2v2 v2 v in2 v in2 (b) Figure 10.33 (a) Small-signal model of MOS differential pair, (b) simplified circuit. vin1 , v1 = vin2 , v2 gm1v1 + gm2v2 = 0: Assuming perfect symmetry, we have from (10.153) v1 = ,v2 (10.152) (10.153) (10.154) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 499 (1) Sec. 10.3 MOS Differential Pair 499 , and for differential inputs, we require vin1 = vin2. Thus, (10.152) translates to vin1 = v1 (10.155) and hence vP = vin1 , v1 =0 (10.156) (10.157) Alternatively, we can simply utilize Eqs. (10.81)-(10.86) with the observation that v=r = 0 for a MOSFET, arriving at the same result. With node P acting as a virtual ground, the concept of half circuit applies, leading to the simplified topology in Fig. 10.33(b). Here, vout1 = ,gmRDvin1 vout2 = ,gmRDvin2; (10.158) (10.159) and, therefore, vout1 vin1 , , vout2 vin2 = ,gmRD: (10.160) Example 10.21 Prove that (10.151) can also yield the differential voltage gain. Solution Since Vout1 , Vout2 = ,RD ID1 , ID2 and since gm = pnCoxW=LISS (why?), we have from (10.151) Vout1 , Vout2 = r ,RD nCox W L ISS Vin1 , Vin2 (10.161) = ,gmRDVin1 , Vin2: (10.162) This is, of course, to be expected. After all, small-signal operation simply means approximating the input/output characteristic [Eq. (10.142)] with a straight line [Eq. (10.151)] around an operating point (equilibrium). Exercise Using the equation gm = 2ID=VGS ,VT H , express the above result in terms of the equilibrium overdive voltage. As with the bipolar circuits studied in Examples 10.10 and 10.14, the analysis of MOS differential topologies is greatly simplified if virtual grounds can be identified. The following examples reinforce this concept. Example 10.22 6 Determine the voltage gain of the circuit shown in Fig. 10.34(a). Assume  = 0. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 500 (1) 500 Chap. 10 Differential Amplifiers Vin1 VDD M3 M4 Vout M1 M2 Vin2 I SS v in1 M3 v out1 M1 (a) (b) Figure 10.34 Solution Drawing the half circuit as in Fig. 10.34(b), we note that the total resistance seen at the drain of M1 is equal to 1=gm3jjrO3jjrO1. The voltage gain is therefore equal to Av = ,gm1 1 gm3 jjrO3jjrO1 : (10.163) Exercise Repeat the and M4. above example if a resistance of value R1 is inserted in series with the sources of M3 Example 10.23 Assuming  = 0, compute the voltage gain of the circuit illustrated in Fig. 10.35(a). VDD Vout Vin1 M3 M4 Q P I SS1 I SS2 Vin2 v in1 M1 M3 v out1 (a) (b) Figure 10.35 Solution Identifying both nodes P and Q as virtual grounds, we construct the half circuit shown in Fig. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 501 (1) Sec. 10.4 Cascode Differential Amplifiers 10.35(b), and write Av = , gm1 gm3 : 501 (10.164) Exercise Repeat the above example if  6= 0. Example 10.24 Assuming  = 0, calculate the voltage gain of the topology shown in Fig. 10.36(a). VDD Vin1 Vout R DD M1 M2 R SS Vin2 v in1 R DD 2 M1 R SS 2 v out1 (a) (b) Figure 10.36 . Solution Grounding the midpoint of RSS and RDD, we obtain the half circuit in Fig. 10.36(b), where RDD Av = , RSS 2 2 + 1 gm : (10.165) Exercise Repeat the above example if the load current sources are replaced with diode-connected PMOS devices. 10.4 Cascode Differential Amplifiers Recall from Chapter 9 that cascode stages provide a substantially higher voltage gain than simple CE and CS stages do. Noting that the differential gain of differential pairs is equal to the single- BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 502 (1) 502 Chap. 10 Differential Amplifiers ended gain of their corresponding half circuits, we surmise that cascoding boosts the gain of differential pairs as well. We begin our cascode devices study with and I1 and the I2 structure are ideal. dReepcicotgendizininFgigth. a1t0t.h3e7(baa),sewshoefreQQ3 3aannddQQ44asreervaet as ac ground, we construct the half circuit shown in Fig. 10.37(b). Equation (9.51) readily gives the gain as I1 Q3 Vb Vout Q4 VCC I2 Vin1 Q1 Q2 Vin2 v out1 Q3 v in1 Q1 I EE (a) (b) Figure 10.37 (a) Bipolar cascode differential pair, (b) half circuit of (a). Av = ,gm1 gm3rO1jjr3rO3 + rO1jjr3 ; (10.166) confirming that a differential cascode achieves a much higher gain. The and I2 developments in in Fig. 10.37(a). Chapter 9 Illustrated also suggest the in Fig. 10.38(a), use the of pnp cascodes for current sources I1 resulting configuration can be analyzed with the aid of its half circuit, Fig. 10.38(b)V.CUCtilizing Eq. (9.61), we express the voltage gain as Vb3 Q7 Vb2 Q5 Q3 Vb1 Q8 Q6 Vout Q4 Q7 Q5 v out1 Q3 Vin1 Q1 Q2 Vin2 v in1 Q1 I EE (a) (b) Figure 10.38 (a) Bipolar cascode differential pair with cascode loads, (b) half circuit of (a). Av  ,gm1 gm3rO3rO1jjr3 jj gm5rO5rO7jjr5 : (10.167) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 503 (1) Sec. 10.4 Cascode Differential Amplifiers 503 Called a “telescopic cascode,” the topology of Fig. 10.38(b) exemplifies the internal circuit of some operational amplifiers. Example 10.25 Due to a manufacturing defect, a parasitic resistance has appeared between nodes A and B in the circuit of Fig. 10.39(a). Determine the voltage gain of the circuit. VCC Vb3 Q7 A Vb2 Q5 Q3 Vb1 Q8 B R1 Q6 Vout Q4 Q7 R1 2 Q5 v out1 Q3 Vin1 Q1 Q2 Vin2 v in1 Q1 I EE (a) (b) Figure 10.39 Solution The symmetry of the circuit implies that half circuit shown in Fig. 10.39(b). Thus, impedance of the pnp cascode. Since the Rtvha1el=um2e iaodpfppRoeia1nrtsisoinfnoRpta1graiivlsleeanl,vwwiirttehucaralOng7nr,oolutonmwdea,rklieenagadptihpnergooxtuoitmpthuae-t tions and must return to the original expression for the cascode output impedance, Eq. (9.1): Rop =  1 + gm5 rO7jjr5 jj R1 2  rO5 + rO7jjr5 jj R1 2 : (10.168) The resistance seen looking down into the npn cascode remains unchanged and approximately equal to gm3rO3rO1jjr2. The voltage gain is therefore equal to Av = ,gm1 gm3rO3rO1jjr2 jjRop: (10.169) Exercise If = 50 and VA = 4 V for all transistors and IEE = 1 mA, what value of R1 degrades the gain by a factor of two? We now turn our attention to differential MOS cascodes. Following the above developments for bipolar counterparts, we consider the simplified topology of Fig. 10.40(a) and draw the half BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 504 (1) 504 Chap. 10 Differential Amplifiers circuit as depicted in Fig. 10.40(b). From Eq. (9.69), VDD M3 Vout Vb1 M4 Vin1 M1 M2 Vin2 I SS M3 v out1 v in1 M1 (a) (b) Figure 10.40 (a) MOS cascode differential pair, (b) half circuit of (a). Av  ,gm3rO3gm1rO1: (10.170) Illustrated in Fig. 10.41(a), the complete CMOS telescopic cascode amplifier incorporates PMOS cascades as load current sources, yielding the half circuit shown in Fig. 10.41(b). It follows from Eq. (9.72) that the voltage gain is given by M7 M8 VDD Vb3 M7 Vb2 M5 M3 Vb1 M6 Vout M4 M5 M3 v out1 Vin1 M1 M2 I SS Vin2 v in1 M1 (a) (b) Figure 10.41 (a) MOS telescopic cascode amplifier, (b) half circuit of (a). Av  ,gm1 gm3rO3rO1jjgm5rO5rO7 : (10.171) Example 10.26 Due to a manufacturing defect, two equal parasitic resistances, R1 and R2, have appeared as shown in Fig. 10.42(a). Compute the voltage gain of the circuit. Solution Noting that R1 and circuit as depicted in R2 appear in Fig. 10.42(b). parallel Without with rO5 the value oafnRd1rgOi6v,enre, swpeecmtiuvsetlyre, sworet draw to the the half original expression for the output impedance, Eq. (9.3): Rp = 1 + gm5rO5jjR1 rO7 + rO5jjR1: (10.172) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 505 (1) Sec. 10.5 Common-Mode Rejection 505 M7 M8 VDD Vb3 M7 Vb2 Vb1 Vin1 R1 R2 M5 M6 M3 Vout M4 M1 M2 Vb2 Vin2 I SS R1 M5 M3 v out1 v in1 M1 (a) (b) Figure 10.42 The resistance seen looking into the drain of the NMOS cascode can still be approximated as Rn  gm3rO3rO1: (10.173) The voltage gain is then simply equal to Av = ,gm1RpjjRn: (10.174) Exercise Repeat the the sources above example if of M3 and M4. in addition to R1 and R2, a resistor of value R3 appears between 10.5 Common-Mode Rejection In our study of bipolar and MOS differential pairs, we have observed that these circuits produce no change in the output if the input CM level changes. The common-mode rejection property of differential circuits plays a critical role in today’s electronic systems. As the reader may have guessed, in practice the CM rejection is not infinitely high. In this section, we examine the CM rejection in the presence of nonidealities. The first nonideality relates to the output impedance of the tail current source. Consider the pstsnooteoiplnddloseoclsoiea,fgrsrrtyehVydesPeuhqi.conuIiwpnnaunlgftcaitCunchrtMer,Fenitngoloet.ptsvio1neal0lgno.dc4gth3hyVa(aotantou)gV,tet1owhsu=ahtbt1eyVsr=ehaoouRswtVm2Eon.auEBltil2nud,ateF,mwnsigooein.tucecn1aset0n?tt.hh4pTee3lha(obecbuae)sts.pyeaTumvsthohmailomtteraipttgsrecy,edisarrasceonuqffciuabetriorboeatefhsstIwQtnEheo1aEedtan.eQnWtPdh1ehQaaions2tudchrtioapQsnpue2--t, RceErnEeda,nQd 1heanncdeQth2eocpoelrlaetcetoars an emitter follower. As currents of Q1 and Q2. VP increases, so does the Consequently, the output current through common-mode level falls. The change in the output CM level can be computed by noting that the stage in Fig. 10.43(b) resembles a degenerated CE stage. That is, from Chapter 5, BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 506 (1) 506 Chap. 10 Differential Amplifiers VCM RC Vout1 VCC RC Vout2 Q1 Q2 P I EE R EE VCM RC VCC 2 Vout Q2 Q1 P I EE R EE (a) (b) Figure 10.43 (a) CM response of differential pair in the presence of finite tail impedance, (b) simplified circuit of (a). Vout;CM Vin;CM = RC , REE 2 + 1 2gm = , RC 2REE + gm,1 ; (10.175) (10.176) where the term 2gm represents the transconductance of the parallel combination of Q1 and Q2. This quantity is called the “common-mode gain.” These observations apply to the MOS counter- part equally well. An alternative approach to arriving at (10.175) is outlined in Problem 65. In summary, if the tail current exhibits a finite output impedance, the differential pair pro- duces an output CM change in response to an input CM change. The reader may naturally wonder whether this is a serious issue. After all, so long as the quantity of interest is the dif- ference between the outputs, a change in the output CM level introduces no corruption. Figure 10.44(a) illustrates such a situation. Here, two common-mode noise, Vin;CM . As a result, the dbiafsfeerveonlttiaagl einspouftQs, 1Viann1daQnd2 Vin2, experience some with respect to ground appear as shown in Fig. 10.44(b). With an ideal tail current source, the input CM variation would have no effect at the output, leading to the output waveforms shown in Fig. 10.44(b). On the 1 other hand, with REE , the single-ended outputs are corrupted, but not the differential output [Fig. 10.44(c)]. In summary, the above study indicates that, in the presence of input CM noise, a finite CM gain does not corrupt the differential output and hence proves benign.4 However, if the circuit suffers from asymmetries and a finite tail current source impedance, then the differential output is corrupted. During manufacturing, random “mismatches” appear between the two sides of the differential pair; for example, the transistors or the load resistors may display slightly different dimensions. Consequently, the change in the tail current due to an input CM variation may affect the differential output. As an example of the effect of asymmetries, we consider the simple case of load resistor mismatch. Depicted in Fig. 10.45(a) for a MOS pair,5 this imperfection leads to a difference bbeytwReDenanVdouRt1Da+ndVRouDt2.. We must compute the change in ID1 and ID2 and multiply the result 4Interestingly, older literature has considered this effect troublesome. 5We have chosen a MOS pair here to show that the treatment is the same for both technologies. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 507 (1) Sec. 10.5 Common-Mode Rejection 507 VCC RC Vout1 RC Vout2 A Vin1 Q1 Q2 P B Vin2 VA VB Vout1 VA VB Vout1 VCM I EE R EE Vout2 Vout2 Vout1 Vout2 Vout1 Vout2 − − t t (a) (b) (c) 1 6 1 Figure 10.44 (a) Differential pair sensing input CM noise, (b) effect of CM noise at output with REE = , (c) effect of CM noise at the output with REE = . ∆V VCM VDD RD Vout1 RD + ∆RD Vout2 M1 M2 P I SS R SS Figure 10.45 MOS pair with asymmetric loads. How do we determine the change in ID1 and ID2? Neglecting channel-length modulation, we first observe that ID1 = 1 2 nCox W L VGS1 , VT H 2 ID2 = 1 2 nCox W L VGS2 , VT H 2 ; (10.177) (10.178) ccaoVrnrGcielSud2d.binyIngMotht1haatenrdwIMoDr1d2.s6m, WtuhsertitlbioneagdeqrueIasDils1ttoo=rmIiDsImD2 2abtce=hcaduosIeeDsVanGnoSdt1im=VpGaVcStG1tSh=2e and hence symmetry VGS2 = VGS1 = of currents VGS, we recognize that both ID1 and ID2 flow through RSS, creating a voltage change of 2IDRSS 6But with  6= 0, it would. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 508 (1) 508 Chap. 10 Differential Amplifiers across it. Thus, VCM = VGS + 2IDRSS and, since VGS = ID=gm, VCM = ID 1 gm + 2RSS : (10.179) (10.180) That is, ID = VCM 1 gm + 2RSS : (10.181) Produced by each transistor, this current change flows through both RD and RD +RD, thereby generating a differential output change of Vout = Vout1 , Vout2 = IDRD , IDRD + RD = ,ID  RD = , VCM 1 gm + 2RSS RD: (10.182) (10.183) (10.184) (10.185) It follows that Vout VCM = RD 1 gm + 2RSS : (10.186) (This result can also be obtained through small-signal analysis.) We say the circuit exhibits “com- mon mode to differential mode (DM) conversion” and denote the above gain by ACM,DM . In practice, we strive to minimize this corruption by maximizing the output impedance of the tail current source. For example, a bipolar current source may employ emitter degeneration and a MOS current source may incorporate a relatively long transistor. It is therefore reasonable to assume RSS 1=gm and ACM,DM  RD 2RSS : (10.187) Example 10.27 Determine ACM,DM for the circuit shown in Fig. 10.46. Assume VA = 1 for Q1 and Q2. Solution Recall from Chapter 5 that emitter degeneration raises the output impedance to Rout3 = 1 + gm3R1jjr3 rO3 + R1jjr3: (10.188) Replacing this value for RSS in (10.186) yields ACM,DM = 1 gm1 + 2f RC 1 + gm3R1jjr3 rO3 : + R1jjr3g (10.189) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 509 (1) Sec. 10.5 Common-Mode Rejection 509 VCM VCC RC Vout1 RC + ∆RC Vout2 Q1 Q2 P R out3 Vb Q3 R1 Figure 10.46 Exercise Calculate the above result if R1 ! 1. The mismatches between the transistors in a differential pair also lead to CM-DM conversion. This effect is beyond the scope of this book [1]. While undesirable, CM-DM conversion cannot be simply quantified by ACM,DM . If the circuit provides a large differential gain, ADM , then the relative corruption at the output is small. We therefore define the “common-mode rejection ratio” (CMRR) as CMRR = ADM ACM,DM : (10.190) Representing the ratio of “good” to “bad,” CMRR serves as a measure of how much wanted signal and how much unwanted corruption appear at the output if the input consists of a differential component and common-mode noise. Example 10.28 Calculate the CMRR of the circuit in Fig. 10.46. Solution For small mismatches (e.g., 1), RC Thus, RC, and the differential gain is equal to gm1RC. CMRR = gm1RC RC 1 gm1 + 2 1 + gm3R1jjr3 rO3 + 2R1jjr3 : (10.191) Exercise Determine the CMRR if R1 ! 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 510 (1) 510 Chap. 10 Differential Amplifiers 10.6 Differential Pair with Active Load In this section, we study an interesting combination of differential pairs and current mirrors that proves useful in many applications. To arrive at the circuit, let us first address a problem encountered in some cases. Recall that the op amps used in Chapter 8 have a differential input but a single-ended output [Fig. 10.47(a)]. Thus, the internal circuits of such op amps must incorporate a stage that “converts” a differential input to a single-ended output. We may naturally consider the topology shown in Fig. 10.47(b) as a candidate for this task. Here, the output is sensed at node Y with respect to ground rather than with respect to node X.7 Unfortunately, the voltage gain is now halved because the signal swing at node X is not used. Vin1 Vin2 Vout Vin1 Vin2 RC X VCC RC Y Vout (a) (b) Figure 10.47 (a) Circuit with differential input and single-ended output, (b) possible implementation of (a). We now introduce a topology that serves the task of “differential to single-ended” conversion while resolving the above issues. Shown in Fig. 10.48, the circuit employs a symmetric differ- ential pair, Q1-Q2, along with a current-mirror load, Q3-Q4. (Transistors Q3 and Q4 are also identical.) The output is sensed with respect to ground. VCC Q3 Q4 N Vin1 Q1 Q2 Vin2 Vout I EE Figure 10.48 Differential pair with active load. 7In practice, additional stages precede this stage so as to provide a high gain. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 511 (1) Sec. 10.6 Differential Pair with Active Load 511 10.6.1 Qualitative Analysis It is instructive to first decompose the circuit of Fig. 10.48 into two sections: the input differential pair and and the current-mirror load. As Q2 produce equal and opposite depicted in Fig. changes in their 10.49(a) (along with collector currents in a fictitious load RL), Q1 response to a differential ∆I RL VCC I EE + ∆I 2 + ∆V I EE − ∆I RL 2 Vb Q3 Q4 N VCM Q1 Q2 VCM − ∆V I EE + ∆I ∆I RL 2 P I EE RL (a) (b) Figure 10.49 (a) Response of input pair to input change, (b) response of active load to current change. FcWhigha.natg1e0h.aa4pt9pt(hebne)sia?nnpFduirtss,utcp,rpseioanstcienegththaeevcsoumlrtraaeglnle-tscidghrnaawanlgniemforpofemdaIQnRc3eLinsaeccerrenoasassteRsnofLrd.oeNmNoIwEisEcoa=np2spirtdooexrIiEmthEaet=ec2liyr+ceuqituiIanl. to 1=gm3, VN changes the collector current of IRL. by Q4 alIso=gimnc3re(afosressmbyall I.IA).sSaerceosnudlt,,bthyevvirotluteagoef current mirror action, across RL changes by In order to understand the detailed operation of the circuit, we apply small, differential changes at the input and follow the signals to the output (Fig. 10.50). The load resistor, RL, is added to augment our intuition but it is not necessary for the actual operation. With the input IvbthCoyel2rtthaetgferoaesrnacesmhlbaaeetneaagsmnetsoaosmuahnportliw.isfiIengenihdnoevrrVieenor,ugswitotehbneenocorfaotuelesteVhoaQf.tQ2IC3d1raaniwndcsQrlee4asssfeoscrubtrhyreesnmotmofrmeoamemntRo, uwLn.etTohbIeseoarnuvdtepItuhCta2cthtdhaenecgrfeeaalclsaeinns VCC Q3 Q4 N I C4 I EE + ∆I 2 I EE − ∆I 2 RL Vout + ∆V VCM Q1 Q2 VCM − ∆V P I EE Figure 10.50 Detailed operation of pair with active load. j j j j accdhuigfarfrLrneeeerganetettneusirtssioacncfluootripwhnreiependsudetetiittsnnewhrttomooowItithnCrnaee4niohnbsuoiyFswtptivoguitr.rhtst1e,nu0oewc.dh5oeea0f,rn,teVhgIceoeCouc1igtnu,nrrIiiIrzsCeCeen1s3tt.htm,raaativnrterdholesrItacChchr4taoinouigngne.hcIrinQenao3IstCehan3ebrdyiwsQoa4lrIs.d.oNsS,eeiiqgnnulceraeeclstQiptnoo4gn“tsiheIne.jteobTcaththssi”ees BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 512 (1) 512 Chap. 10 Differential Amplifiers In summary, the and another through circuit of Fig. 10.50 Q1, Q3 and Q4 [Fig. contains two signal paths, one through Q1 and Q2 10.51(a)]. For a differential input change, each path experiences a current change, which translates to a voltage change at the output node. The key point here is that the two paths enhance each other at the output; in the above example, each path forces Vout to increase. VCC Q3 Q4 N Path 1 Vin1 Q 1 Path 2 Q 2 Vin2 Vout I EE Figure 10.51 Signal paths in pair with active load. Our respect initial examination of Q3 to current mirrors studied and Q4 in in Chapter Fig. 10.50 9: here Q3 indicates an interesting and Q4 carry signals in difference addition to with bias currents. This also stands in contrast to the current-source loads in Fig. 10.52, where the base- emitter voltage of the load transistors remains constant and independent of signals. Called an “active load” to distinguish it Q4 plays a critical role in the from the load transistors operation of the circuit. in Fig. 10.52, the combination of Q3 and VCC Vb Q3 Q4 Vout Vin1 Q1 Q2 Vin2 P I EE (a) Figure 10.52 Differential pair with current-source loads. The foregoing analysis directly applies to the CMOS counterpart, shown in Fig. 10.53. Specif- ically, in ISS=2 , into ID4, irneIcsr.peToanhssienecghtojaInDag4esjmiannadlIlD,ra2diistfeifnnegdresVntotouiatrl.a(iiIsnneputVhto,iusItcD.iAr1clusriiots,,ettsohoeto,cthhIaSenScg=ue2rrien+nItDm1IiraranondrdtIrDaInD3s2iisstfocaorllspsaietrode identical.) 10.6.2 Quantitative Analysis The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground [e.g., Fig. 10.47(b)]. To confirm this , conjecture, we wish to determine the small-signal single-ended output, vout, divided by the smallsignal differential input, vin1 vin2. We deal with a CMOS implementation here (Fig. 10.54) to demonstrate that both CMOS and bipolar versions are treated identically. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 513 (1) Sec. 10.6 Differential Pair with Active Load 513 VDD M3 M4 + ∆V M1 M2 − ∆V RL Vout I SS Figure 10.53 MOS differential pair with active load. Vin1 M3 A M1 P VDD M4 Vout M2 Vin2 I SS Figure 10.54 MOS pair for small-signal analysis. The circuit of Fig. 10.54 presents a quandary. While the transistors themselves are symmet- ric and the input signals are small and differential, the circuit is asymmetric. With the diode- csMwon4innpger—cotveoiddnedteahvehicioger,hdMeimr3po, efcdrtehaanetciinengpanaudtloshwweniincmgep—aedlaaatrngthceeisvaontlontadogede.esOAwn,inwthgeeaetoxttphheeecrothuaatprneudlta, nttirovadenelsy.is(sAtmofratsellrMvaol2ll,taatnghdee circuit serves as an amplifier.) The asymmetry resulting from the very different voltage swings at the drains of M1 and M2 disallows grounding node P for small-signal analysis. We present two approaches to solving this circuit. Approach I Without a half circuit available, the analysis can be performed through the use of a complete small-signal model of the amplifier. Referring to the equivalent circuit shown in Fig. 10.55, where the dashed boxes indicate each transistor, we perform the analysis in two steps. In M3 M4 r OP 1 g mP A iX vA gmPvA iY r OP v out v in1 v1 gmNv1 r ON r ON M1 P gmNv2 v2 M2 v in2 Figure 10.55 (a) Small-signal equivalent circuit of differential pair with active load. the first step, we note that iX and iY must add up to zero at node P and hence iX = ,iY . Also, BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 514 (1) 514 Chap. 10 Differential Amplifiers vA = ,iXgm,1P jjrOP  and ,iY = vout rOP + gmP vA = vout rOP , gmP iX  1 gmP jjrOP  = iX: (10.192) (10.193) (10.194) Thus, iX = rOP 1 + vout gmP  1 gmP jjrOP  : (10.195) In the second step, we write a KVL around the loop consisting of all four transistors. The current through iY , gmNv2. It rON of M1 follows that is equal to iX , gmN v1 and that through rON of M2 equal to ,vA + iX , gmNv1rON , iY , gmNv2rON + vout = 0: (10.196) Since v1 , v2 = vin1 , vin2 and iX = ,iY , ,vA + 2iXrON , gmNrON vin1 , vin2 + vout = 0: (10.197) Substituting for vA and iX from above, we have rOP 1+ vout gmP  1 gmP jjrOP   1 gmP jjrOP  + 2rON rOP 1 + vout gmP  1 gmP jjrOP  + vout = gmNrONvin1 , vin2: (10.198) Solving for vout yields vout vin1 , vin2 = gmN rON rOP 1 + gmP  1 gmP jjrOP  2rON + 2rOP : (10.199) This is the exact expression for the gain. If gmP rOP 1, then vout vin1 , vin2 = gmN rON jjrOP : (10.200) The gain is indepedent of gmP and equal to that of the fully-differential circuit. In other words, the use of the active load has restored the gain. Approach II In this approach, we decompose the circuit into sections that more easily lend themselves to analysis by inspection. As illustrated in Fig. 10.56(a), we first seek a Thevenin equivalent for the differential. Recall section that vT hceovnsisisttihnegvoofltavgine1b, evtiwn2e,enMA1 and and BM2in, assuming vin1 and vin2 are the “open-circuit condition” This section can be skipped in a first reading. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 515 (1) Sec. 10.6 Differential Pair with Active Load 515 [Fig. 10.56(b)]. Under this condition, the circuit is symmetric, resembling the topology of Fig. 10.16(a). Equation (10.92) thus yields vThev = ,gmNrONvin1 , vin2; (10.201) where the subscript N refers to NMOS devices. M3 A VDD M4 v out B v in1 M1 M2 P I SS v in2 v Thev RThev v in1 v Thev A B M1 M2 P I SS v in2 (a) vX M1 v1 iX iX M2 r O1 r O2 P v2 I SS (b) (c) Figure 10.56 (a) Thevenin equivalent, (b) Thevenin voltage, and (c) Thevenin resistance of input pair. To determine the Thevenin resistance, we set the inputs to zero and apply a voltage between the (v1 output terminals [Fig. 10.56(c)]. = v2) and writing a KVL around Noting that the “output” M1 and M2 have loop, we have equal gate-source voltages iX , gm1v1rO1 + iX + gm2v2rO2 = vX (10.202) and hence RThev = 2rON : (10.203) The reader is encouraged to obtain this result using half circuits as well. Having reduced the input sources and transistors to a Thevenin equivalent, we now compute the gain of the overall amplifier. Figure 10.57 depicts the simplified circuit, where the diode- connected explicitly. transistor M3 The objective is is rteopclaaclceudlwatiethvou1t=ginmt3erjmjrsOo3favnTdhtehve. output impedance Since the voltage of at nMod4 eisEdrwawithn respect to ground is equal to vout + vT hev, we can view vA as a divided version of vE: vA = 1 gm3 1 gm3 jjrO3 jjrO3 + RT hev vout + vThev: (10.204) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 516 (1) 516 Chap. 10 Differential Amplifiers r O3 1 g m3 A RThev v Thev E VDD M4 v out B r O4 Figure 10.57 Simplified circuit for calculation of voltage gain. Given by gm4vA, the small-signal drain current of M4 must satisfy KCL at the output node: gm4vA + vout rO4 + vout + vThev 1 gm3 jjrO3 + RT hev = 0; (10.205) where the last term on the left hand side represents the current flowing through RT hev. It follows from (10.204) and (10.205) that 0 BB@gm4 1 gm3 1 gm3 jjrO3 jjrO3 + RT hev + 1 1 gm3 jjrO3 + 1 RThev CCA vout + vT hev  + vout rO4 = 0: (10.206) RrOe3co=gnriOzi4ng=thraOtP1,=wgme 3reducreO(31,0.a2n0d61) =togm3 RThev and assuming gm3 = gm4 = gmp and 2 RT hev vout + vThev + vout rOP = 0: (10.207) Equations (10.201) and (10.207) therefore give vout 1 rON + 1 rOP = gmNrON vin1 rON , vin2 (10.208) and hence vout vin1 , vin2 = gmN rON jjrOP : (10.209) The gain is independent of gmp. Interestingly, the gain of this circuit is the same as the differential gain of the topology in Fig. 10.51(b). In other words, the path through the active load restores the gain even though the output is single-ended. Example 10.29 In our earlier observations, we surmised that the voltage swing at node A in Fig. 10.56 is much less than that at the output. Prove this point. Solution , , As depicted in must be equal Fig. to 10.58, KCL at the output vout=rO4 gm4vA. This cnuordreenitnfldiocwatsesthtrhoautgthheMto1taalncduhrreennctedtrharwonugbhyMM32, generating vA = ,voutrO4 + gm4 vA 1 gm3 jjrO3 : (10.210) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 517 (1) Sec. 10.7 Chapter Summary That is, vA  ,2gmvoPurtOP ; revealing that vA is indeed much less that vout. r O3 1 g m3 A VDD M 4 r O4 v out −v in M1 M2 P I SS +v in Figure 10.58 Exercise Calculate the voltage gain from the differential input to node A. 517 (10.211) 10.7 Chapter Summary Single-ended signals are voltages measured with respect to ground. A differential signal consists of two single-ended signals carried over two wires, with the two components beginning from the same dc (common-mode) level and changing by equal and opposite amounts. Compared with single-ended signals, differential signals are more immune to common-mode noise. A differential pair consists of two identical transistors, a tail current, and two identical loads. The transistor currents in a differential pair remain constant as the input CM level changes, i.e., the circuit “rejects” input CM changes. The transistor currents change in opposite directions if a differential input is applied, i.e., the circuit responds to differential inputs. For small, differential changes at the input, the tail node voltage of a differential pair remains constant and is thus considered a virtual ground node. Bipolar differential pairs exhibit a hyperbolic tangent input/output characteristic. The tail current can be mostly steered to one side with a differential input of about 4VT . For small-signal operation, the input differential swing of a bipolar differential pair must remain below roughly VT . The pair can then be decomposed into two half circuits, each of which is simply a common-emitter stage. pMOS differential pairs can 2ISS=nCoxW=L, which sisteper2 the tail current with a differential input larger than the equilibrium overdrive of each equal to transistor. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 518 (1) 518 Chap. 10 Differential Amplifiers Unlike their bipolar counterparts, MOS differential pairs can provide more or less linear characteristics depending on the choice of the device dimensions. The input transistors of a differential pair can be cascoded so as to achieve a higher voltage gain. Similarly, the loads can be cascoded to maximize the voltage gain. The differential output of a perfectly symmetric differential pair remains free from input CM changes. In the presence of asymmetries and a finite tail current source impedance, a fraction of the input CM change appears as a differential component at the output, corrupting the desired signal. The gain seen by the CM change normalized to the gain seen by the desired signal is called the common-mode rejection ration. It is possible to replace the loads of a differential pair with a current mirror so as to provide a single-ended output while maintaining the original gain. The circuit is called a differential pair with active load. Problems 1 1. To calculate the effect of is a small-signal “input” this gain, assuming VA ripple at the output of the circuit and determine the (small-signal) . ginaiFnigfr.o1m0.V1,CwCetocaVnoausts. uCmoemVpCutCe 2. Repeat Problem 1 for the circuit of Fig. 10.2(a), assuming RC1 = RC2. 1 3. Repeat Problem 1 for the stages shown in Fig. 10.59. Assume VA and  0. VCC RC Vout Q1 Vb Vin I EE VDD RD Vout Vin Vin M1 RS VCC Q1 Vin Vout I EE VDD M1 Vout RS (a) (b) (c) (d) Figure 10.59 4. In the circuit of Fig. 10.60, I1 = I0 cos !t+I0 and I2 = ,I0 cos !t+I0. Plot the waveforms VCC I1 I2 X Y RC RC Figure 10.60 at X and Y and determine their peak-to-peak swings and common-mode level. 5. Repeat Problem 4 for the circuit depicted in Fig. 10.61. Also, plot the voltage at node P as a function of time. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 519 (1) Sec. 10.7 Chapter Summary 519 VCC R1 RC P RC X Y I1 I2 Figure 10.61 VCC RC RC X Y I1 I2 Figure 10.62 6. Repeat Problem 4 for the topology shown in Fig. 10.62. 7. Repeat Problem 4 for the topology shown in Fig. 10.63. VCC I1 I2 X Y RC RC Vb Figure 10.63 8. Repeat Problem 4, but assume I2 = ,I0 cos !t + 0:8I0. Can X and Y be considered true differential signals? 9. Assuming I1 = I0 cos !t + I0 time for the circuits illustrated iannFdigI.21=0.6,4I. 0Acsossum!te+I1Ii0s, plot VX and constant. VY as a function of VCC VCC VCC VCC RC RC X Y RC RC IT X Y RC RC RP X Y RC RC X Y I1 I2 IT I1 I2 I1 I2 I1 I 2 RP (a) (b) (c) (d) Figure 10.64 10. Assuming V1 = V0 cos !t + V0 and V2 = the circuits shown in Fig. 10.65. Assume I,TVi0s cos !t + V0, constant. plot VP as a function of time for BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 520 (1) 520 RC Chap. 10 Differential Amplifiers RC RC V1 RC P V1 RC P V1 RC P V2 V2 R1 V2 I1 (a) Figure 10.65 (b) (c) , 11. Suppose in Fig. 10.7, VCC rises by V . Neglecting the Early effect, determine the change in VX , VY , and VX VY . Explain why we say the circuit “rejects” supply noise. 12. In Fig. 10.7, IEE experiences a change of I. How do VX , VY , and VX , VY change? 13. Repeat Problem 12, but assuming that RC1 = RC2 + R. Neglect the Early effect. 14. Consider the circuit of Fig. 10.9(a) and assume IEE = 1 mA. What is the maximum allowable value of RC if Q1 must remain in the active region? 15. In the circuit of Fig. 10.9(b), RC = 500 . What is the maximum allowable value of IEE if Q2 must remain in the active region? 16. Suppose IEE = 1 mA and RC = 800 in Fig. 10.9(a). Determine the region of operation of Q1. 17. What happens to the characteristics depicted in Fig. 10.10 if (a) IEE is halved, (b) VCC rises by V , or (c) RC is halved? 18. In the ential differential pair of Fig. 10.12, IC1 voltage? With this voltage applied, =IC2 how = 5. What is does IC1=IC2 the corresponding input differchange if the temperature rises from 27 C to 100 C? 19. Suppose the input differential signal applied to a bipolar differential pair must not change the transconductance (and hence the bias current) of each transistor by more than 10. From Eq. (10.58), determine the maximum allowable input. , 20. ItrrinsaentshsceboecncidracuuucsiettaInoCcfe2Fodigfe.cQr1e20a.ds1re2os,p. tsUhbesyinsamg fEaalqcl-t.so(ir1go0nf.a5l28.t)r,adnestceornmdiuncetathneceinopfuQt d2ifffaelrlesnacse Vin1 Vin2 at which the 21. It is possible to define a differential transconductance for the bipolar differential pair of Fig. 10.12: Gm = @IC1 @Vin1 , , IC2 Vin2 : (10.212) , From , What Eqs. (10.58) and is the maximum (10.60), value of compute Gm Gm? At what and plot value of the result as Vin1 Vin2 adofuens cGtimondorfopVibny1 a Vin2. factor of two with respect to its maximum value? 22. With the aid of Eq. (10.78), we can compute the small-signal voltage gain of the bipolar differential pair: Av = @Vout1 @Vin1 , , Vout2 Vin2 : (10.213) , Determine the gain and compute its value if Vin1 Vin2 contains a dc component of 30 mV. 23. Explain what happens to the characteristics shown in Fig. 10.13 if the ambient temperature goes from 27 C to 100 C. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 521 (1) Sec. 10.7 Chapter Summary 521 24. In Example 10.9, RC = 500 , IEE = 1 mA, and VCC = 2:5 V. Assume Vin1 = V0 sin !t + VCM Vin2 = ,V0 sin !t + VCM; (10.214) (10.215) where VCM = 1 V denotes the input common-mode level. (a) (b) If If VV00 =2 = mV, plot the output waveforms (as a function of time). 50 mV, determine the time t1 at which one transistor carries 95 of the tail current. Plot the output waveforms. 25. The study in Example 10.9 suggests that a differential pair can convert a sinusoid to a square wave. Using the circuit parameters given in Problem 24, plot the output waveforms if V0 = 80 mV or 160 mV. Explain why the output square wave becomes “sharper” as the input amplitude increases. 26. In ! Problem 25, estimate = 2  100 MHz. the slope of the output square waves for V0 = 80 mV or 160 mV if 27. Repeat the small-signal analysis of Fig. 10.15 for the circuit shown in Fig. 10.66. (First, prove that P is still a virtual ground.) VCC RC RC Vin1 Vout Q1 Q2 Vin2 P I EE R EE Figure 10.66 28. Using a small-signal model and including the output resistance of the transistors, prove that Eq. (10.86 holds in the presence of the Early effect. 29. In Fig. 10.67, IEE = 1 mA and VA = 5 V. Calculate the voltage gain of the circuit. Note that the gain is independent of the tail current. VCC Vin1 Vout Q1 Q2 P I EE Vin2 Figure 10.67 30. Consider the circuit shown in Fig. 10.68, where IEE = 2 mA, VA;n = 5 V VA;p = 4 V. What value of R1 = R2 allows a voltage gain of 50? 31. The circuit of Fig. 10.68 must provide a gain of 50 and VA;p = 4 V, calculate the required tail current. with R1 = R2 = 5 k . If VA;n = 5 V BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 522 (1) 522 Figure 10.68 Chap. 10 Differential Amplifiers VCC X Q3 Q4 Vin1 R1 R2 Vout Q1 Q2 P I EE Vin2 32. Assuming perfect symmetry and VA stage depicted in Fig. 10.69. VCC R1 R2 Q3 Q4 Vout Vin1 Q1 Q2 Vin2 P I EE 1, compute the differential voltage gain of each RC Vout Vin1 R1 R2 Q1 P I EE VCC RC Vin2 Q2 (a) Vin1 VCC R1 R2 Q3 Vout Q4 Q1 Q2 Vin2 P I EE (b) Vin1 Q3 Q1 R1 R2 Vout VCC Q4 Q2 Vin2 P I EE (c) (d) Figure 10.69 1 33. Assuming perfect symmetry and VA , compute the differential voltage gain of each , stage depicted in Fig. 10.70. You may need to compute the gain as Av = GmRout in some cases. 1 34. Consider the differential pair illustrated in Fig. 10.71. Assuming perfect symmetry and VA = , (a) Determine the voltage gain. (b) Under what condition does the gain become independent of the tail currents? This is an example of a very linear circuit because the gain does not vary with the input or output signal levels. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 523 (1) Sec. 10.7 Chapter Summary 523 RC Vin1 Q1 Vout VCC RC Q2 Vin2 RE P RE R SS RC Vin1 Q1 Vout R1 R2 RE P RE R SS VCC RC Vin2 Q2 (a) (b) Figure 10.70 VCC Q3 Q4 RC Vin1 Q1 Vout RC Q2 Vin2 I EE RE I EE Figure 10.71 35. Consider the MOS differential pair of Fig. 10.24. What happens to the tail node voltage if (a) the width of M1 and M2 is doubled, (b) ISS is doubled, (c) the gate oxide thickness is doubled. 36. In the MOS differential pair of Fig. 10.24, VCM = 1 V, ISS = 1 mA, and RD = 1 k . What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VTH;n = 0:5 V. 37. The MOS differential pair of Fig. 10.24 must be designed for an equilibrium overdrive of 200 mV. If nCox = 100 A=V2 and W=L = 20=0:18, what is the required value of ISS? 38. For a MOSFET, the “current density” can be defined as the drain current divided by the device width for a given channel length. Explain how the equilibrium overdrive voltage of a MOS differential pair varies as a function of the current density. 39. A MOS differential pair contains a parasitic resistance tied between its tail node and ground (Fig. 10.72). Without using the small-signal model, prove that P is still a virtual ground for small, differential inputs. 40. In Fig. among 1th0e.2c5i(rac)u,iVt pina1ra=me1t:e5rsVthaantdgVuianr2an=te0es:3oVp.eArastisounmoinf gMM1 2inissaotfuf,radteiotenr.mine a condition 41. Repeat Example 10.16 for a supply voltage of 2 V. and W=L for a given output common-mode level. Formulate the trade-off between VDD 42. An adventurous student constructs the circuit shown in Fig. 10.73 and calls it a “differential amplifier” because ID Vin1 , Vin2. Explain which aspects of our differential signals and amplifiers this circuit violates. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 524 (1) 524 Chap. 10 Differential Amplifiers RD Vin1 X M1 I SS VDD RD Y M2 P R SS Vin2 Figure 10.72 Figure 10.73 Vin1 VDD RD Vout M1 Vin2 43. Examine Eq. (10.134) for the following cases: (a) ID1 = ISS. Explain the significance of these cases. ID1 = 0, (b) ID1 = ISS=2, and (c) 44. Prove that the right hand side of Eq. (10.139) is always negative if the solution with the negative sign is considered. 45. p , From Eq. (10.142), determine the value of Vin1 Vin2 such that ID1 that is result is equal to 2 times the equilibrium overdrive voltage. , ID2 = ISS. Verify 46. From Eq. (10.142), compute the small-signal transconductance of a MOS differential pair, defined as Gm = @ID1 @Vin1 , , ID2 Vin2 : (10.216) , Plot the result as a function of Vin1 Vin2 and determine its maximum value. , 47. Using the result obtained in Problem 46, calculate the value of Vin1 Vin2 at which the transconductance drops by a factor of 2. 48. Suppose a new type of MOS transistor has been invented that exhibits the following I-V characteristic: ID = VGS , VTH3; (10.217) where is a proportionality factor. Figure 10.74 shows a differential pair employing such transistors. (a) What similarities exist between this circuit and the standard MOS differential pair? , (b) (c) ACat lwcuhlaattevathlueeeoqfuViliinb1riumVoinv2erddoreivseovnoelttaragnesoisftoTr1taunrnd T2. off? 49. Explain what happens to the characteristics shown in Fig. 10.31 if (a) the gate oxide thickness of the transistor is doubled, (b) the threshold voltage is halved, (c) ISS and W=L are halved. 50. Assuming that the mobility of carriers falls at high temperatures, explain what happens to the characteristics of Fig. 10.31 as the temperature rises. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 525 (1) Sec. 10.7 Chapter Summary 525 RD Vin1 Vout T1 T2 VDD RD Vin2 I SS Figure 10.74 51. A student who has a single-ended voltage source constructs the circuit shown in Fig. 10.75, hoping to obtain differential outputs. Assume perfect symmetry but  = 0 for simplicity. VDD RD RD X Vout Y M1 M2 Vin P Vb I SS Figure 10.75 o(o(abff))MvVVini2iee.,wwciainnlcgguMMlat11eaavssXaa common-source stage degenerated by the impedance seen at the source in terms of vin. source follower and M2 as a common-gate stage, calculate vY in terms (c) Add the results obtained in (a) and (b) with proper polarities. If the voltage gain is defined as vX , vY =vin, how does it compare with the gain of differentially-driven pairs? 52. Calculate the differential voltage gain of the circuits depicted in Fig. 10.76. Assume perfect symmetry and  0. Vin1 M3 M4 Vout M1 M2 I SS VDD Vin2 Vb M5 Vin1 M3 M4 Vout M1 M2 I SS VDD Vb M6 Vin2 Vin1 VDD M3 M4 R1 R2 Vout M1 M2 Vin2 I SS (a) Figure 10.76 (b) (c) 53. Calculate the differential voltage gain of the circuits depicted in Fig. 10.77. Assume perfect symmetry and  0. You may need to compute the gain as Av = ,GmRout in some cases. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 526 (1) 526 Chap. 10 Differential Amplifiers Vin1 M3 M4 Vout R1 R2 M1 R SS M2 VDD Vin2 M Vb 3 Vin1 VDD M4 Vout M1 M2 R SS Vin2 RS VbM 3 VDD RS M4 Vout Vin1 M1 M2 Vin2 R SS (a) Figure 10.77 (b) (c) 54. The cascode differential pair of Fig. 10.37(a) must achieve a voltage gain of 4000. If Q1-Q4 are identical and = 100, what is the minimum required Early voltage? 55. Due to a manufacturing error, a parasitic resistance, RP , has appeared in the circuit of Fig. 10.78. Calculate the voltage gain. VCC Q3 Vb Vout Q4 RP Vin1 Q1 Q2 I EE Vin2 Figure 10.78 56. Repeat Problem 55 for the circuit shown in Fig. 10.79. VCC Figure 10.79 Q3 Vb Vout RP RP Q4 Vb Vin1 Q1 Q2 Vin2 I EE BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 527 (1) Sec. 10.7 Chapter Summary 527 , 57. Calculate the GmRout.) voltage gain of the degenerated pair depicted in Fig. 10.80. (Hint: Av = VCC Q3 Vb Vout Q4 Vin1 Q1 Q2 RS Vin2 Figure 10.80 58. A student has mistakenly used pnp cascode transistors in a differential pair as illustrated in Fig. 10.81. Calculate the voltage gain of the circuit. (Hint: Av = ,GmRout.) VCC Q3 Vb Vout Q4 Vin1 Q1 Q2 Vin2 I EE Figure 10.81 59. Realizing that the circuit of Fig. 10.81 suffers from a low gain, the student makes the modification shown in Fig. 10.82. Calculate the voltage gain of this topology. 60. The telescopic cascode of Fig. 10.38 is to operate as an op amp having an open-loop gain of 800. If Q1-Q4 voltage. Assume anre=id2enptic=al1a0n0dasnodaVrAe ;Qn 5=-Q28V,Ad;ept.ermine the minimum allowable Early 61. Determine the voltage gain of the circuit depicted in Fig. 10.83. Is this topology considered a telescopic cascode? 62. The MOS cascode of Fig. 10.40(a) must provide a voltage gain of 300. If W=L = 20=0:18 for 0:1 MV,11-M. 4 and nCox = 100 A=V2, determine the required tail current. Assume  = 63. The MOS telescopic cascode of Fig. 10.41(a) is designed for a voltage gain tapil=cu0rr:2enVt ,of1,1dmetAer.mIifnenCWo=xL=1 100 = A==VW2,=LpC8.ox = 50 A=V2, n = o0f:12V00,w1,itahnda 64. A student adventurously modifies a CMOS telescopic cascode as shown in Fig. 10.84, where the PMOS cascode transistors are replaced with NMOS devices. Assuming  0, compute BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 528 (1) 528 Chap. 10 Differential Amplifiers VCC Q3 Q4 Vb Vout Vin1 Q1 Q2 Vin2 I EE Figure 10.82 Vb3 Q7 Vb2 Q5 Q3 Vb1 VCC Q8 Q6 Vout Q4 Vin1 Q1 Q2 Vin2 I EE Figure 10.83 jj the M6 voltage gain of the circuit. is not equal to 1=gm rO.) (Hint: the impedance seen looking into the source of M5 or 65. Consider the 2REE places circuit on the of Fig. 10.43(a) and replace REE with two two sides of the current source. Now draw parallel resistors a vertical line of equal to symme- try through the circuit and decompose it to two common-mode half circuits, each having a degeneration resistor equal to 2REE. Prove that Eq. (10.175) still holds. 66. The bipolar differential pair depicted in Fig. 10.85 must exhibit a common-mode gain of less than 0.01. Assuming VA = 1 for Q1 and Q2 but VA 1 for Q3, prove that RCIC 0:02VA + VT : (10.218) 67. Compute the common-mode gain of the MOS differential pair shown in Fig. 10.86. Assume  = 0 for M1 and M2 but  6= 0 for M3. Prove ACM = 2  RDISS ; + VGS , VTHeq: (10.219) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 529 (1) Sec. 10.7 Chapter Summary 529 M7 Vb3 VDD M8 Vb2 M5 M3 Vb1 M6 Vout M4 Vin1 M1 M2 Vin2 I SS Figure 10.84 Figure 10.85 v CM RC v out1 Q1 Vb Q3 VCC RC v out2 Q2 I EE RD Vin1 X M1 VDD RD Y M2 Vin2 Vb M3 Figure 10.86 where VGS , VT H eq: denotes the equilibrium overdrive of M1 and M2. 68. Calculate the common-mode gain of the circuit depicted in Fig. 10.87. Assume  0, gmrO 1, and use the relationship Av = ,GmRout. 69. Repeat Problem 68 for the circuits shown in Fig. 10.88. 70. Compute the common-mode rejection ratio of the stages illustrated in Fig. 10.89 and com- pare the results. For simplicity, neglect channel-length modulation in M1 and M2 but not in other transistors. 71. Determine the small-signal gain vout=i1 in the circuit of Fig. 10.90 if W=L3 = NW=L4. Neglect channel-length modulation. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 530 (1) 530 Figure 10.87 Chap. 10 Differential Amplifiers Vb1 M3 Vout VDD M4 Vin1 M1 M2 Vin2 Vb2 M5 Vb1 M3 Vout VDD M4 Vin1 M1 M2 Vin2 Vb2 M5 Vb3 M6 (a) Figure 10.88 Vb3 M5 VDD M6 Vb1 M3 M4 Vout Vin1 M1 M2 Vin2 Vb2 M7 (b) VDD RD RD + ∆RD v out1 v out2 Vin1 M1 M2 P Vin2 Vb1 M3 (a) Figure 10.89 VDD RD RD + ∆RD v out1 v out2 Vin1 M1 M2 P Vin2 Vb2 M3 Vb3 M4 (b) , 72. In the circuit shown in Fig. Neglecting channel-length m10o.d9u1l,aIt1iocnh,acnaglceuslfartoemVoIu0t to I0 + before I and I2 from I0 to I0 and after the change if I. (a) (b) WW==LL33 = = 2WW=L=L4.4 73. Consider the circuit of Fig. 10.92, where the inputs are tied to a common-mode level. Assume M1 and M2 are identical and so are M3 and M4. (a) Neglecting channel-length modulation, calculate the voltage at node N . (b) Invoking symmetry, determine the voltage at node Y . BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 531 (1) Sec. 10.7 Chapter Summary 531 Figure 10.90 VDD M3 M4 Vout I1 RL VDD M3 M4 Vout I1 I2 RL Figure 10.91 v CM VDD M3 M4 N Y M1 M2 P I SS Figure 10.92 (c) What happens to the results obtained in (a) and (b) if VDD changes by a small amount V ? 74. Neglecting channel-length modulation, compute the small-signal gains vout=i1 and vout=i2 in Fig. 10.93. VDD M3 M4 Vout I1 I2 RL Figure 10.93 75. We wish to design the stage shown in Fig. 10.94 for a voltage gain of what is the required Early voltage for the pnp transistors? 100. If VA;n = 5 V, 76. Repeat the analysis in Fig. 10.56 but by constructing a Norton equivalent for the input differential pair. 77. Determine the output impedance of the circuit shown in Fig. 10.54. Assume gmrO 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 532 (1) 532 Chap. 10 Differential Amplifiers VCC Q3 Vin1 Q1 Q4 Q2 Vout Vin2 I EE Figure 10.94 78. Using the result obtained in Problem 77 and the relationship Av = ,GmRout, compute the voltage gain of the stage. Design Problems 79. Design the bipolar differential pair of Fig. 10.6(a) for a voltage gain of 10 and a power budget of 2 mW. Assume VCC = 2:5 V and VA = 1. 80. The bipolar differential pair of Fig. 10.6(a) must operate with an input common-mode level of 1.2 V without driving the transistors into saturation. Design the circuit for maximum voltage gain and a power budget of 3 mW. Assume VCC = 2:5 V. 81. The differential pair depicted in Fig. 10.95 must provide a gain of 5 and a power budget of 4 VCC RC RC Vout Vin1 Q1 Q2 Vin2 I EE RE I EE Figure 10.95 mW. Moreover, the gain of the circuit must change by less than 2 if the collector current of either transistor changes by 10. Assuming VCC = 2:5 V and VA = 1, design the circuit. (Hint: a 10 change in IC leads to a 10 change in gm.) 82. Design the circuit of Fig. 10.96 for a gain of 50 and a power budget of 1 mW. Assume VCC Vb Q3 Q4 Vout Vin1 Q1 Q2 Vin2 I EE Figure 10.96 VA;n = 6 V and VCC = 2:5 V. 83. Design the circuit of Fig. 10.97 for a gain of 100 and a power budget of 1 mW. Assume BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 533 (1) Sec. 10.7 Chapter Summary 533 VCC Q3 Q4 Vin1 R1 R2 Vout Q1 Q2 P I EE Vin2 Figure 10.97 VA;n = 10 V, VA;p = 5 V, and VCC = 2:5 V. Also, R1 = R2. 84. Design the MOS differential pair of Fig. 10.29 for Vin;max = 0:3 V and a power budget of 3 mW. Assume RD = 500 ,  = 0, nCox = 100 A=V2, and VDD = 1:8 V. 85. Design the MOS differential pair of Fig. 10.29 for an equilibrium overdrive voltage of 100 mV and a power budget of 2 mW. Select the value of RD to place the transistor at the edge of triode region for an input common-mode level of 1 V. Assume  = 0, nCox = 100 A=V2, VTH;n = 0:5 V, and VDD = 1:8 V. What is the voltage gain of the resulting design? 86. Design the MOS differential pair of Fig. 10.29 for a voltage gain of 5 and a power dissipation of 1 mW if the equilibrium overdrive must be at least 150 mV. Assume  = 0, nCox = 100 A=V2, and VDD = 1:8 V. 87. The differential pair depicted in Fig. 10.98 must provide a gain of 40. Assuming the same Vb1 M3 Vout VDD M4 Vin1 M1 M2 Vin2 Vb2 M5 Figure 10.98 (equilibrium) overdrive the circuit. Assume n for = a0l:l1oVf t,h1e, transistors p = 0:2 aVnd,1a, power dissipation of 2 mW, design nCox = 100 A=V2, pCox = 100 A=V2, and VDD = 1:8 V. 88. Design the circuit and determine the of Fig. 10.37(a) required Early vfoolrtaagveo. lAtalgseo,gain=of140000,0V. CACssu=me2:Q5 1V-Q, a4nadrethiedepnotwicearl budget is 1 mW. 89. Design the telescopic cascode of Fig. are identical and so are Q5-Q8. Also, 10.38(a) for n = 100, a p =vol5t0ag, eVAg;anin=of52V0,0V0.CACss=um2:e5QV1, -aQnd4 the power budget is 2 mW. 90. Design the telescopic cascode of Fig. 10.41(a) for a voltage gain of 600 and a power budget of 4 mW. Assume an (equilibrium) overdrive of 100 mV for the NMOS devices and 150 mV for the PMOS devices. If VDD = 1.8 V, nCox = 100 A=V2, pCox = 50 A=V2, and BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 534 (1) 534 Chap. 10 Differential Amplifiers n = 0:1 M5-M8. V,1 , determine the required value of p . Assume M1-M4 are identical and so are 91. The differential pair of Fig. 10.99 must achieve a CMRR of 60 dB (= 100). Assume a power VDD RD v out1 RD + ∆RD v out2 Vin1 M1 M2 P Vin2 Vb1 M3 Figure 10.99 budget of 2 mW, a nominal differential voltage gain of 5, and neglecting channel-length modulation in M1 and M2, compute the minimum required  for M3. Assume W=L1;2 = 10=0:18, nCox = 100 A=V2, VDD = 1:8 V, and R=R = 2. 92. Design the differential pair of Fig. 10.48 for a voltage gain of 200 and a power budget of 3 mW with a 2.5-V supply. Assume VA;n = 2VA;p. 93. Design the circuit of Fig. 10.54 for a voltage gain of 20 and a power budget of 1 mW with VDD = 1:8 level is 1 V. n = 0:5p =AV.l0sAo:1,ssVun,mC1e.oxM=1 operates 2pCox at the edge of saturation if = 100 A=V2, VTH;n = the 0:5 input V, VT common-mode H;p = ,0:4 V, SPICE Problems In the following problems, use transistors, assume IS;npn = 5 the10M,O16SAd,evincpenm=od1e0l0s ,gVivAe;nnpinn the Appendix = 5 V, IS;pnp I=. F8or b1ip0o,l1a6r A, pnp = 50, VA;pnp = 3:5 V. 94. Consider the differential amplifier shown in Fig. 10.100, where the input CM level is equal to 1.2 V. VCC= 2.5 V Vb Q4 Vout Vin1 Q1 Q2 Vin2 1 mA I EE Figure 10.100 (a) Adjust the value of Vb so as to set the output CM level to 1.5 V. (b) Determine the small-signal differential gain of the circuit. (Hint: to provide differential inputs, use an independent voltage source for one side and a voltage-dependent voltage source for the other.)  (c) What happens to the output CM level and the gain if Vb varies by 10 mV? 95. The differential amplifier depicted in Fig. 10.101 employs two current mirrors to establish the bias for the input and load devices. Assume W=L = 10 m=0:18 m for M1-M6. The input CM level is equal to 1.2 V. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 535 (1) Sec. 10.7 Chapter Summary 535 M7 1 kΩ VDD= 1.8 V M4 M3 Vout Vin1 M1 M2 Vin2 M6 M5 Figure 10.101 (a) Select W=L7 so as to set the output CM level to 1.5 V. (Assume L7 = 0:18 m.) (b) Determine the small-signal differential gain of the circuit. (c) Plot the differential input/output characteristic. 96. Consider the circuit illustrated in Fig. 10.102. Assume a small dc drop across R1 and R2. VCC= 2.5 V Q3 Q4 Vin1 R1 R2 Vout Q1 Q2 Vin2 1 mA I EE Figure 10.102 (a) (b) Select Select the the input value CM level of R1 (= tRo 2p)lascuechQt1haatntdheQse2 at the edge of saturation. resistors reduce the differential gain by no more than 20. 97. In the differential amplifier of Fig. 10.103, W=L = 10 m=0:18 m for all of the transistors. Assume an input CM level of 1 V and Vb = 1:5 V. M7 M9 VDD= 1.8 V M8 I1 M3 Vout Vb M4 Vin1 M1 M2 Vin2 1 mA I SS Figure 10.103 (a) Select the value of I1 so that the output CM level places M3 and M4 at the edge of saturation. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 536 (1) 536 Chap. 10 Differential Amplifiers (b) Determine the small-signal differential gain. 98. In the circuit of Fig. 10.104, W=L = 10 m=0:18 m for M1-M4. Assume an input CM level of 1.2 V. VDD= 1.8 V Vin1 M3 X M1 M4 M2 Vout Vin2 0.5 mA I SS Figure 10.104 (a) (b) (c) Determine Determine Determine the the the ocsmhuatapnlugl-tesdiigcnnltaehlvegeolauiantnpsduvetoxdupct=laleivvnienwl1ihf,yWivt4iinsc2heqaanungadlesvtoXbVy=X5v/in.1 , vin2. References 1. B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 537 (1) 11 Frequency Response The need for operating circuits at increasingly higher speeds has always challenged designers. From radar and television systems in the 1940s to gigahertz microprocessors today, the demand for pushing circuits to higher frequencies has required a solid understanding of their speed limitations. In this chapter, we study the effects that limit the speed of transistors and circuits, identifying topologies that better lend themselves to high-frequency operation. We also develop skills for deriving transfer functions of circuits, a critical task in the study of stability and frequency compensation (12). We assume bipolar transistors remain in the active mode and MOSFETs in the saturation region. The outline is shown below. Fundamental Concepts Bode’s Rules Association of Poles with Nodes Miller’s Theorem High−Frequency Models of Transistors Bipolar Model MOS Model Transit Frequency Frequency Response of Circuits CE/CS Stages CB/CG Stages Followers Cascode Stage Differential Pair 11.1 Fundamental Concepts 11.1.1 General Considerations What do we mean by “frequency response?” Illustrated in Fig. 11.1(a), the idea is to apply a sinusoid at the input of the circuit and observe the output while the input frequency is varied. As exemplified by Fig. 11.1(a), the circuit may exhibit a high gain at low frequencies but a “roll-off” as the frequency increases. We plot the magnitude of the gain as in Fig. 11.1(b) to represent the circuit’s behavior at all frequencies of interest. We may loosely call f1 the useful bandwidth of the circuit. Before investigating the cause of this roll-off, we must ask: why is frequency response important? The following examples illustrate the issue. Example 11.1 Explain why people’s voice over the phone sounds different from their voice in face-to-face conversation. 537 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 538 (1) 538 Chap. 11 Frequency Response Av Roll−Off f1 f (a) (b) Figure 11.1 (a) Conceptual test of frequency response, (b) gain roll-off with frequency. Solution Human voice contains frequency components from 20 Hz to 20 kHz [Fig. 11.2(a)]. Thus, circuits 20 Hz Figure 11.2 20 kHz f 400 Hz 3.5 kHz f (a) (b) processing the voice must accommodate this frequency range. Unfortunately, the phone system suffers from a limited bandwidth, exhibiting the frequency response shown in Fig. 11.2(b). Since the phone suppresses frequencies above 3.5 kHz, each person’s voice is altered. In high-quality audio systems, on the other hand, the circuits are designed to cover the entire frequency range. Exercise Whose voice does the phone system alter more, men’s or women’s? Example 11.2 When you record your voice and listen to it, it sounds somewhat different from the way you hear it directly when you speak. Explain why? Solution During recording, your voice propagates through the air and reaches the audio recorder. On the other hand, when you speak and listen to your own voice simultaneously, your voice propagates not only through the air but also from your mouth through your skull to your ear. Since the frequency response of the path through your skull is different from that through the air (i.e., your skull passes some frequencies more easily than others), the way you hear your own voice is different from the way other people hear your voice. Exercise Explain what happens to your voice when you have a cold? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 539 (1) Sec. 11.1 Fundamental Concepts 539 Example 11.3 Video signals typically occupy a bandwidth of about 5 MHz. For example, the graphics card delivering the video signal to the display of a computer must provide at least 5 MHz of bandwidth. Explain what happens if the bandwidth of a video system is insufficient. Solution With insufficient bandwidth, the “sharp” edges on a display become “soft,” yielding a fuzzy picture. This is because the circuit driving the display is not fast enough to abruptly change the contrast from, e.g., complete white to complete black from one pixel to the next. Figures 11.3(a) and (b) illustrate this effect for a high-bandwidth and low-bandwidth driver, respectively. (The display is scanned from left to right.) Figure 11.3 (a) (b) Exercise What happens if the display is scanned from top to bottom? What causes the gain roll-off in Fig. 11.1? As a simple example, let us consider the low-pass filter depicted in Fig. 11.4(a). At low frequencies, C1 is nearly open and the current through R1 Vout R1 Vin 1.0 Vin C1 Vout f Figure 11.4 (a) Simple low-pass filter, and (b) its frequency response. nearly zero; thus, Vout = voltage divider consisting Vin. As the frequency increases, the impedance of of R1 and C1 attenuates Vin to a greater extent. The C1 falls and the circuit therefore exhibits the behavior shown in Fig. 11.4(b). As a more interesting example, consider the common-source stage illustrated in Fig. 11.5(a), where a load capacitance, CL, appears at the output. At low frequencies, the signal current pro- duced by M1 prefers At high frequencies, to flow on the oththreorughhanRdD, CbLec“asutseealtsh”esiommpeedoafntcheeosfigCnLa,l 1=CLs, remains high. current and shunts it to ground, leading to a lower voltage swing at the output. In fact, from the small-signal equivalent BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 540 (1) 540 Chap. 11 Frequency Response VDD RD Vin Vout Vin M1 CL gmVin RD Vout CL (a) (b) Figure 11.5 (a) CS stage with load capacitance, (b) small-signal model of the circuit. circuit of Fig. 11.5(b),1 we note that RD and CL are in parallel and hence: Vout = ,gmVinRD jj 1 CLs : (11.1) That is, as the frequency increases, the parallel impedance falls and so does the amplitude of Vout.2 The voltage gain therefore drops at high frequencies. The reader may wonder why we use sinusoidal inputs in our study of frequency response. After all, an amplifier may sense a voice or video signal that bears no resemblance to sinusoids. Fortunately, such signals can be viewed as a summation of many sinusoids with different frequencies (and phases). Thus, responses such as that in Fig. 11.5(b) prove useful so long as the circuit remains linear and hence superposition can be applied. 11.1.2 Relationship Between Transfer Function and Frequency Response We know from basic circuit theory that the transfer function of a circuit can be written as H s = A0 1 1 + + s !z1 s !p1 1 1 + + s !z2 s !p2       ; (11.2) ! ! !wzhjeraendA!0 pdjerneoptreessethnet low frequency gain the zeros and poles because Hs of the transfer A0 as s 0. The function, respectively. If frequencies the input to the circuit is a sinusoid of the form xt = A cos2ft = A cos !t, then the output can be expressed as yt = AjHj!j cos !t + 6 Hj! ; (11.3) where Hj! is obtained by making the substitution s = j!. Called the “magnitude” and the “phase,” jHj!j and 6 Hj! respectively reveal the frequency response of the circuit. In this chapter, we are primarily concerned with the former. Note that f (in Hz) and ! (in radians per second) are related by a factor of 2. For example, we may write ! = 5  1010 rad/s = 27:96 GHz: Example 11.4 Determine the transfer function and frequency response of the CS stage shown in Fig. 11.5(a). 1Channel-length modulation is neglected here. 2We use upper case letters for frequency-domain quantities (Laplace transforms) even though they denote smallsignal values. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 541 (1) Sec. 11.1 Fundamental Concepts 541 Solution From Eq. (11.1), we have H s = Vout Vin s = ,gmRDjj 1 CLs  (11.4) = ,gmRD RDCLs + 1: (11.5) For a sinusoidal input, we replace s = j! and compute the magnitude of the transfer function:3 Vout Vin = pRD2gmCRL2 !D2 + 1: (11.6) As expected, the gain begins at gmRD at low comparable with unity. At ! = 1=RDCL, frequencies, rolling off as RD2 CL2 !2 becomes Vout Vin = gmpR2D : (11.7) Since 20 log p2  3 dB, we say the ,3-dB bandwidth of the circuit is equal to 1=RDCL (Fig. 11.6). Vout V in −3−dB Bandwidth −3−dB Rolloff Figure 11.6 1 ω RD CL Exercise Derive the above results if  6= 0. Example 11.5 Consider the common-emitter stage shown in Fig. 11.7. Derive a relationship between the gain, , 1 the 3-dB bandwidth, and the power consumption of the circuit. Assume VA = . Solution In a manner similar to the low-frequency gain the by CS topology gmRC = IC =oVf TFigR.C1,1a.5n(da)th, ethpeobwaenrdcwoindstuhmisptgiiovnenbybIyC1= VRCCCC. FLor, the highest performance, we wish to maximize both the gain and the bandwidth (and hence the p a jb + 3The magnitude of the complex number is equal to a2 + b2. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 542 (1) 542 Chap. 11 Frequency Response VCC RC Vin Q1 Vout CL Figure 11.7 product of the two) and minimize the power dissipation. We therefore define a “figure of merit” as Gain  Bandwidth Power Consumption = IC VT RC IC VCRCC1CL (11.8) = VT 1  VCC 1 CL : (11.9) Thus, the overall performance can be improved by lowering (a) the temperature;4 (b) VCC but at the cost of limiting the voltage swings; or (c) the load capacitance. In practice, the load ca- pacitance receives the greatest attention. Equation (11.9) becomes more complex for CS stages (Problem 15). Exercise Derive the above results if VA 1. Example 11.6 Explain the relationship between the frequency response and step response of the simple lowpass filter shown in Fig. 11.4(a). Solution To obtain the transfer function, we view the circuit as a voltage divider and write 1 Hs = Vout Vin s = C11sC1+s R1 = 1 R1C1s + 1: (11.10) (11.11) The frequency response is determined by replacing s with j! and computing the magnitude: jHs = j!j = p1 R12C12!2 + 1: (11.12) T = 77 4For example, by immersing the circuit in liquid nitrogen ( K), but requiring that the user carry a tank around! BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 543 (1) Sec. 11.1 Fundamental Concepts 543 The ,3-dB bandwidth is The circuit’s response equal to to a step 1=R1C1. of the form V0 ut is given by Vout t = V01 , exp ,t R1C1 ut: (11.13) The relationship between (11.12) and (11.13) is that, as R1C1 increases, the bandwidth drops and the step response becomes slower. Figure 11.8 plots this behavior, revealing that a narrow bandwidth results in a sluggish time response. This observation explains the effect seen in Fig. H R 1C1 1.0 R 1C1 Vout Figure 11.8 f (a) t (b) 11.3(b): since the signal cannot rapidly jump from low (white) to high (black), it spends some time at intermediate levels (shades of gray), creating “fuzzy” edges. Exercise j j At what frequency does H fall by a factor of two? 11.1.3 Bode’s Rules The task of obtaining jHj!j from Hs and plotting the result is somewhat tedious. For this j j reason, we often utilize Bode’s rules (approximations) to construct Hj! rapidly. Bode’s rules for jHj!j are as follows: As ! passes each pole frequency, the slope of jHj!j decreases by 20 dB/dec; (A slope of 20 dB/dec simply means a tenfold change in H for a tenfold increase in frequency.) As ! passes each zero frequency, the slope of jHj!j increases by 20 dB/dec.5 Example 11.7 Construct the Bode plot of jHj!j for the CS stage depicted in Fig. 11.5(a). Solution Equation (11.5) indicates a pole frequency of j!p1j = 1 RDCL : (11.14) j j The magnitude thus begins at gmRD at low frequencies and remains flat up to ! = !p1 . At this , point, the slope changes from zero to 20 dB/dec. Figure 11.9 illustrates the result. In contrast 5Complex poles may result in sharp peaks in the frequency response, an effect neglected in Bode’s approximation. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 544 (1) 544 Chap. 11 Frequency Response to Fig. 11.5(b), the Bode approximation ignores the 3-dB roll-off at the pole frequency—but it greatly simplifies the algebra. As evident from Eq. (11.6), for RD2 CL2 !2 1, Bode’s rule provides a good approximation. 20log Vout V in gmRD −20 dB/dec Figure 11.9 ω p1 log ω Exercise Construct the Bode plot for gm = 150 ,1; RD = 2 k , and CL = 100 fF. 11.1.4 Association of Poles with Nodes The poles of a circuit’s transfer function play a central role in the frequency response. The de- signer must therefore be able to identify the poles intuitively so as to determine which parts of the circuit appear as the “speed bottleneck.” The CS topology studied in Example 11.4 serves as a good example for identifying poles by inspection. Equation (11.5) reveals that the pole frequency is given by the inverse of the product of the total resistance seen between the output node and ground and the total capacitance seen between the output node and ground. Applicable to many circuits, this observation can be generalized ground and as follows: if a capacitance node of Cj j in the signal path exhibits a small-signal resistance to ground, then it contributes a pole of magnitude Rj of Cj R,j1 to to the transfer function. Example 11.8 Determine the poles of the circuit shown in Fig. 11.10. Assume  = 0 VDD RS Vin RD M1 C in Vout CL Figure 11.10 . Solution SofetCtiinngtVoignrotounzder.oT,hwues,recognize that the gate of M1 sees a resistance of RS and a capacitance j!p1j = 1 RSCin : (11.15) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 545 (1) Sec. 11.1 Fundamental Concepts 545 We may call !p1 the “input pole” to indicate that it arises in the input network. Similarly, the “output pole” is given by j!p2j = 1 RDCL : (11.16) , Since the low-frequency gain of the circuit is equal to gmRD, we can readily write the magni- tude of the transfer function as: Vout Vin =q gmRD : 1 + !2=!p211 + !2!p22 (11.17) Exercise If !p1 = !p2, at what frequency does the gain drop by 3 dB? Example 11.9 Compute the poles of the circuit shown in Fig. 11.11. Assume  = 0. VDD RD R M S 1 Vb Vin Vout CL C in Figure 11.11 . Solution With Vin = 0, the small-signal resistance seen at the source of M1 is given by RSjj1=gm, yielding a pole at !p1 = RSjj 1 1 gm Cin : (11.18) The output pole is given by !p2 = RDCL,1. Exercise How do we choose the value of RD such that the output pole frequency is ten times the input pole frequency? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 546 (1) 546 Chap. 11 Frequency Response The reader may wonder how the foregoing technique can be applied if a node is loaded with a “floating” capacitor, i.e., a capacitor whose other terminal is also connected to a node in the signal path (Fig. 11.12). In general, we cannot utilize this technique and must write the circuit’s equations and obtain the transfer function. However, an approximation given by “Miller’s Theorem” can simplify the task in some cases. VDD RD RS Vin CF Vout M1 Figure 11.12 Circuit with floating capacitor. 11.1.5 Miller’s Theorem Our above study and the example in Fig. 11.12 make it desirable to obtain a method that “transforms” a floating capacitor to two grounded capacitors, thereby allowing association of one pole with each node. Miller’s theorem is such a method. Miller’s theorem, however, was originally conceived for another reason. In the late 1910s, John Miller had observed that parasitic capacitances appearing between the input and output of an amplifier may drastically lower the input impedance. He then proposed an analysis that led to the theorem. Consider the general circuit shown in Fig. 11.13(a), where the floating impedance, ZF , ap- 1 ZF 2 1 2 V1 V2 Z 1 V1 V2 Z 2 (a) (b) Figure 11.13 (a) General circuit including a floating impedance, (b) equivalent of (a) as obtained from Miller’s theorem. pears between nodes 1 and 2. We wish to transform ZF to two grounded impedances as depicted in Fig. 11.13(b), while ensuring all of the currents and voltages in the circuit remain unchanged. To determine Z1 and Z2, we Fig. 11.13(a) must be equal node 2 in Fig. 11.13(a) must make two observations: (1) the current drawn by ZF from node 1 in tboe tehqaut adlrtaowtnhabtyinZje1ctiendFbigy.Z121.i1n3F(big).; and (2) the current injected to 11.13(b). (These requirements guarantee that the circuit does not “feel” the transformation.) Thus, V1 , V2 ZF = V1 Z1 V1 , V2 ZF = , V2 Z2 : (11.19) (11.20) Denoting the voltage gain from node 1 to node 2 by Av, we obtain Z1 = ZF V1 V1 , V2 (11.21) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 547 (1) Sec. 11.1 Fundamental Concepts 547 = 1 ZF , Av (11.22) and Z2 = ZF ,V2 V1 , V2 = 1 ZF , 1 Av : (11.23) (11.24) Called Miller’s theorem, the results expressed by (11.22) and (11.24) prove extremely useful in analysis and design. In particular, (11.22) suggests that the floating impedance is reduced by a factor of 1 , Av when “seen” at node 1. As an important example of Miller’s theorem, let us assume ZF is a single capacitor, CF , tied between the input and output of an inverting amplifier [Fig. 11.14(a)]. Applying (11.22), we have Z1 = 1 ZF , Av = 1 + 1 A0CF s; (11.25) (11.26) , wwsuohgregdreess,ttahseacascupaabpcsaitctitoiutrotiCrooFnfAtviaevldu=beet1wA+e0eAnis0tmhCeaFdine,p.auWstiahfnaCdt Ftoyupistep“ouaftmoimpflpaifineedidan”nvceberytiiasngZfaa1cm?toTprlhoifiefe11r=+ws iAdthe0p.aeIngndaoientnhcoeefr A0 raises the input capacitance by an amount equal to 1 + A0CF . We say such a circuit suffers from “Miller multiplication” of the capacitor. CF Vin ∆V −A 0 Vout Vin −A 0 −A 0 ∆V CF (1 + A0 ( Vout CF (1 + 1 A0 ( (a) (b) Figure 11.14 (a) Inverting circuit with floating capacitor, (b) equivalent circuit as obtained from Miller’s theorem. The effect of CF at the output can be obtained from (11.24): Z2 = 1 ZF , 1 Av = 1 + 1 1 A0 CF s ; (11.27) (11.28) which is close to CF s,1 if A0 1. Figure 11.14(b) summarizes these results. The Miller multiplication of capacitors can also be explained intuitively. Suppose the input voltage That is, in Fig. 11.14(a) goes up the voltage across CF by a small amount increases by 1 + V . The A0V , output then goes down by A0V . requiring that the input provide a BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 548 (1) 548 Chap. 11 Frequency Response proportional charge. By did not change, it would contrast, if experience oCnFlywaevreolntaogteacflhoanatgiengofcapVaciatnodr and its right plate voltage require less charge. The above study points to the utility of Miller’s theorem for conversion of floating capacitors to grounded capacitors. The following example demonstrates this principle. Example 11.10 Estimate the poles of the circuit shown in Fig. 11.15(a). Assume  = 0. RS Vin VDD RD CF Vout M1 RS Vin VDD RD Vout M 1 Cout C in (a) (b) Figure 11.15 Solution , Noting that M1 and RD constitute an inverting amplifier having a gain of gmRD, we utilize the results in Fig. 11.14(b) to write: Cin = 1 + A0CF = 1 + gmRDCF (11.29) (11.30) and Cout = 1 + 1 gmRD CF ; (11.31) thereby arriving at the topology depicted in Fig. 11.15(b). From our study in Example 11.8, we have: !in = 1 RSCin = RS1 + 1 gmRDCF (11.32) (11.33) and !out = 1 RDCout = RD 1 + 1 1 gmRD CF : (11.34) (11.35) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 549 (1) Sec. 11.1 Fundamental Concepts 549 Exercise Calculate Cin if gm = 150 ,1; RD = 2 k , and CF = 80 fF. The reader may find the above example somewhat inconsistent. Miller’s theorem requires that the floating impedance and the voltage gain be computed at the same frequency whereas Example 11.10 uses the low-frequency gain, gmRD, even for the purpose of finding high-frequency poles. After all, we know that the existence of CF lowers the voltage gain from the gate of M1 to the output at high frequencies. Owing to this inconsistency, we call the procedure in Example 11.10 the “Miller approximation.” Without this approximation, i.e., if A0 is expressed in terms of circuit parameters at the frequency of interest, application of Miller’s theorem would be no simpler than direct solution of the circuit’s equations. Another artifact of Miller’s approximation is that it may eliminate a zero of the transfer func- tion. We return to this issue in Section 11.4.3. The general expression in Eq. (11.22) can be interpreted as follows: an impedance tied be- tween of 1 + the Av input and if seen at output of an inverting the input (with respect amplifier with a to ground). This gain of Av is lowered by a factor reduction of impedance (hence in- crease in capacitance) is called “Miller effect.” For example, we say Miller effect raises the input capacitance of the circuit in Fig. 11.15(a) to 1 + gmRDCF . 11.1.6 General Frequency Response Our foregoing study indicates that capacitances in a circuit tend to lower the voltage gain at high frequencies. It is possible that capacitors reduce the gain at low frequencies as well. As a simple example, consider the high-pass filter shown in Fig. 11.16(a), where the voltage division between C1 and R1 yields Vout C1 Vin 1.0 v in R1 Vout 1 ω R 1C1 (a) (b) Figure 11.16 (a) Simple high-pass filter, and (b) its frequency response. and hence Vout Vin s = R1 R1 + 1 C1s = R1C1s R1C1s + 1; Vout Vin = p R1C1! R12C12!12 + 1: (11.36) (11.37) (11.38) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 550 (1) 550 Chap. 11 Frequency Response Plotted in Fig. 11.16(b), the response exhibits a roll-off as the frequency of operation falls below 1=R1C1. As seen from Eq. (11.37), this roll-off arises because the zero of the transfer function occurs at the origin. The low-frequency roll-off may prove undesirable. The following example illustrates this point. Example 11.11 Figure 11.17 depicts a source follower used in a high-quality audio amplifier. Here, Ri estab- Ri Vin Ci VDD M1 Vout I1 CL Figure 11.17 lishes a gate bias voltage equal to VDD  = 0; gm = 1=200 the maximum tolerable , and value oRf 1C=L. 100 for k M1, and I1 . Determine defines the drain bias current. Assume the minimum required value of C1 and Solution Similar to the high-pass filter of Fig. 11.16, the input network consisting of Ri and Ci attenuates the signal at low frequencies. To ensure that audio components as low as 20 Hz experience a small attenuation, we set the corner frequency 1=RiCi to 2  20 Hz, thus obtaining Ci = 79:6 nF: (11.39) This value is, of course, much to large to be integrated on a chip. Since Eq. (11.38) reveals a 3-dB attenuation at ! = 1=RiCi, in practice we must choose even a larger capacitor if a lower attenuation is desired. The load capacitance creates a pole at the output node, lowering the gain at high frequencies. Setting the pole frequency to the upper end of the audio range, 20 kHz, and recognizing that the resistance seen from the output node to ground is equal to 1=gm, we have !p;out = gm CL = 2  20 kHz; (11.40) (11.41) and hence CL = 39:8 nF: (11.42) An efficient driver, the source follower can tolerate a very large load capacitance (for the audio band). Exercise Repeat the above example if I1 and the width of M1 are halved. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 551 (1) Sec. 11.1 Fundamental Concepts 551 Why did we use capacitor Ci in the above example? Without Ci, the circuit’s gain would not fall at low frequencies, and we would not need perform the above calculations. Called a “coupling” capacitor, while blocking the dc cConi taelnltoowfsVtihne. signal frequencies of interest to pass through In other words, Ci isolates the bias conditions of the the circuit source follower from those of the preceding stage. Figure 11.18(a) illustrates an example, where a CS stage precedes the source follower. The coupling capacitor permits independent bias voltages VDD RD Ri Y M1 Ci X Vin M2 I1 Vout RD P Vin M2 VDD M1 I1 Vout (a) (b) Figure 11.18 Cascade of CS stage and source follower with (a) capacitor coupling and (b) direct coupling. at nodes X and region) to allow Y a . For large example, VY drop across can RD, be chosen relatively thereby maximizing low (placing M2 near the triode the voltage gain of the CS stage (why?). To convince the reader that capacitive coupling proves essential in Fig. 11.18(a), we consider the case of “direct coupling” [Fig. 11.18(b)] as well. Here, to maximize the voltage gain, we , rIwe1is.sihSdietnoacteseaVtvGVoSPl1taj+guestVoaIf1baomtvlaeeyaVsrGteSaVc2GhS610V+0T-HV702I1,0,emw.gVh.,,e2rthe0e0VtImw1Vod.seOtnaongteetshseathroeethqmeuriintheiaminnudcm,otmhvepoalgttaaigbteleeoriefnqMtuei2rrmemdsubosyft their bias points, necessitating capacitive coupling. Capacitive coupling (also called “ac coupling”) is more common in discrete circuit design due to the large capacitor values required in many applications (e.g., Ci in the above audio example). Nonetheless, many integrated circuits also employ capacitive coupling, especially at low supply voltages, if the necessary capacitor values are no more than a few picofarads. Figure 11.19 shows a typical frequency response and the terminology used to refer to its H Midband Gain Midband ωL Figure 11.19 Typical frequency response. ωH ω various attributes. We call !L the lower corner or lower “cut-off” frequency and !H the upper corner or upper cut-off frequency. Chosen to accommodate the signal frequencies of interest, the band between !L and !H is called the “midband range” and the corresponding gain the “midband gain.” BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 552 (1) 552 Chap. 11 Frequency Response 11.2 High-Frequency Models of Transistors The speed of many circuits is limited by the capacitances within each transistor. It is therefore necessary to study these capacitances carefully. 11.2.1 High-Frequency Model of Bipolar Transistor Recall from Chapter 4 that the bipolar transistor consists of two pn junctions. The depletion re- gion associated with the junctions6 gives rise to a capacitance between base and emitter, denoted by Cje, and another between base and collector, denoted by C [Fig. 11.20(a)]. We may then add these capacitances to the small-signal model to arrive at the representation shown in Fig. 11.20(b). C n Cµ p B C je n+ B C je Cµ rπ vπ g m v π C rO E (a) B Cπ Cµ rπ vπ E (b) g m vπ C rO E (c) Figure 11.20 (a) Structure of bipolar transistor showing junction capacitances, (b) small-signal model with junction capacitances, (c) complete model accounting for base charge. Unfortunately, this model is incomplete because the base-emitter junction exhibits another effect that must be taken into account. As explained in Chapter 4, the operation of the transistor requires a (nonuniform) charge profile in the base region to allow the diffusion of carriers toward the collector. In other words, if the transistor is suddenly turned on, proper operation does not begin until enough charge carriers enter the base region and accumulate so as to create the nec- essary profile. Similarly, if the transistor is suddenly turned off, the charge carriers stored in the base must be removed for the collector current to drop to zero. The above phenomenon is quite similar to charging and discharging a capacitor: to change the collector current, we must change the base charge profile by injecting or removing some electrons or holes. Modeled by a is typically more significant than parallel, they are lumped into one second capacitor between the base and emitter, the depletion region capacitance. Since and denoted by C [Fig. 11.20(c)]. Cb and CCbj,e this effect appear in 6As mentioned in Chapter 4, both forward-biased and reversed-biased junctions contain a depletion region and hence a capacitance associated with it. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 553 (1) Sec. 11.2 High-Frequency Models of Transistors 553 In integrated circuits, the bipolar transistor is fabricated atop a grounded substrate [Fig. 11.21(a)]. The collector-substrate junction remains reverse-biased (why?), exhibiting a junction capacitance employ this denoted model in by CCS. The complete our analysis. In modern model is depicted in Fig. 11.21(b). integrated-circuit bipolar transistors, We Cje hereafter , C, and CCS are on the order of a few femtofarads for the smallest allowable devices. CBE Cµ Cµ C p n Substrate n+ C CS (a) B C π rπ vπ CB g m v π rO C CS Cπ E (b) C CS E (c) Figure 11.21 (a) Structure of an integrated bipolar transistor, (b) small-signal model including collectorsubstrate capacitance, (c) device symbol with capacitances shown explicitly. In the analysis of frequency response, it is often helpful to first draw the transistor capacitances on the circuit diagram, simplify the result, and then construct the small-signal equivalent circuit. We may therefore represent the transistor as shown in Fig. 11.21(c). Example 11.12 Identify all of the capacitances in the circuit shown in Fig. 11.22(a). Vb1 Vin VCC RC Vout Q2 Q1 VCC C µ2 RC Vout Vb C π2 Q2 C µ1 C CS2 Vin C π1 Q1 C CS1 (a) (b) Figure 11.22 Solution From Fig. 11.21(b), we add the three capacitances of each transistor as depicted in Fig. 11.22(b). Interestingly, CCS1 and C2 appear in parallel, and so do C2 and CCS2. Exercise Construct the small-signal equivalent circuit of the above cascode. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 554 (1) 554 Chap. 11 Frequency Response 11.2.2 High-Frequency Model of MOSFET Our study of the MOSFET structure in Chapter 6 revealed several capacitive components. We now study these capacitances in the device in greater detail. Illustrated in Fig. 11.23(a), the MOSFET displays three prominent capacitances: one between the gate and the channel (called the “gate oxide capacitance” and given by W LCox), and two associated with the reverse-biased source-bulk and drain-bulk junctions. The first component presents a modeling difficulty because the transistor model does not contain a “channel.” We must therefore decompose this capacitance into one between the gate and the source and another between the gate and the drain [Fig. 11.23(b)]. The exact partitioning of this capacitance is be-  yond the scope of this book, capacitance whereas C2 0. but, in the saturation region, C1 is about 2=3 of the gate-channel C2 C1 n+ n+ p −substrate (a) (b) Figure 11.23 (a) Structure of MOS device showing various capacitances, (b) partitioning of gate-channel capacitance between source and drain. Two other capacitances in the MOSFET become critical in some circuits. Shown in Fig. 11.24, these components arise from both the physical overlap of the gate with source/drain areas7 and the fringe field lines between the edge of the gate and the top of the S/D regions. Called the gate- drain or gate-source “overlap” capacitance, this (symmetric) effect persists even if the MOSFET is off. n+ Figure 11.24 Overlap capacitance between gate and drain (or source). We now construct the high-frequency model of the MOSFET. Depicted in Fig. 11.25(a), this representation consists of: (1) the capacitance between the gate and source, CGS (including the overlap component); (2) the capacitance between the gate and drain (including the overlap com- ponent); (3) the junction capacitances between the source and bulk and the drain and bulk, CSB and CDB, respectively. (We assume the bulk remains at ac ground.) As mentioned in Section 11.2.1, we often draw the capacitances on the transistor symbol [Fig. 11.25(b)] before constructing the small-signal model. Example 11.13 Identify all of the capacitances in the circuit of Fig. 11.26(a). Solution Adding the four capacitances of each device from Fig. 11.25, we arrive at the circuit in Fig. 11.26(b). Note that CSB1 and CSB2 are shorted to ac ground on both ends, CGD2 is shorted 7As mentioned in Chapter 6, the S/D areas protrude under the gate during fabrication. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 555 (1) Sec. 11.2 High-Frequency Models of Transistors 555 C GD G CGS v GS g mv GS rO D C DB S C SB C GD G CGS S D C DB C SB (a) (b) Figure 11.25 (a) High-frequency model of MOSFET, (b) device symbol with capacitances shown explic- itly. VDD M2 Vout Vin M1 CGS2 CSB2 M2 C GD2 C GD1 VDD C DB2 Vout Vin CGS1 M1 C DB1 C SB1 CSB2 VDD M2 C GD1 Vout Vin CGS1 M1 CDB1 + CDB2 + CGS2 C SB1 (a) (b) (c) Figure 11.26 “out,” and CDB1, CDB2, and CGS2 appear in parallel at the output node. The circuit therefore reduces to that in Fig. 11.26(c). Exercise Noting that M2 is a diode-connected device, construct the small-signal equivalent circuit of the amplifier. 11.2.3 Transit Frequency With various capacitances surrounding bipolar and MOS devices, is it possible to define a quantity that represents the ultimate speed of the transistor? Such a quantity would prove useful in comparing different types or generations of transistors as well as in predicting the performance of circuits incorporating the devices. A measure of the intrinsic speed of transistors8 is the “transit” or “cut-off” frequency, fT , 8By “intrinsic” speed, we mean the performance of the device by itself, without any other limitations imposed or enhancements provided by the circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 556 (1) 556 Chap. 11 Frequency Response defined as the frequency at which the small-signal current gain of the device falls to unity. Illustrated in Fig. 11.27 (without the biasing circuitry), the idea is to inject a sinusoidal current into I out ac GND I out ac GND Q1 I in Vin C in M1 I in Vin C in Figure 11.27 Conceptual setup for measurement of fT of transistors. the base or gate and measure the resulting collector or drain current while the input frequency, fin, is increased. We note that, as fin increases, the input capacitance of the device lowers the innepguletcitmCpedaanndceC,GZDinh, earned(bhuetntcaekethteheimnpiunttovoalctacgoeunVtiinn = IinZin and the output current. We Problem 26). For the bipolar device in Fig. 11.27(a), Since Iout = gmIinZin, Zin = 1 Cs jjr: (11.43) Iout Iin = gmr rCs + 1 (11.44) = rCs + 1: (11.45) At the transit frequency, !T = 2fT , the magnitude of the current gain falls to unity: r2 C2!T2 = 2 , 1  2: (11.46) (11.47) That is, !T  gm C (11.48) The transit frequency of MOSFETs is obtained in a similar fashion. We therefore write: 2fT  gm C or gm CGS : (11.49) Note that the collector-substrate or drain-bulk capacitance does not affect fT owing to the ac ground established at the output. Modern bipolar and MOS transistors boast fT ’s above 100 GHz. Of course, the speed of complex circuits using such devices is quite lower. Example 11.14 The minimum channel length of MOSFETs has been scaled from 1 m in the late 1980s to 65 nm today. Also, the inevitable reduction of the supply voltage has reduced the gate-source overdive voltage from about 400 mV to 100 mV. By what factor has the fT of MOSFETs increased? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 557 (1) Sec. 11.3 Analysis Procedure 557 Solution It can proved (Problem 28) that 2fT = 3 2 n L2 VGS , VT H : (11.50)  Thus, the transit frequency has increased by approximately a factor of 59. For example, if n = 400 cm2=(V s), then 65-nm devices having an overdrive of 100 mV exhibit an fT of 226 GHz. Exercise  Determine the fT if the channel length is scaled down to 45 nm but the mobility degrades to 300 cm2=(V s). 11.3 Analysis Procedure We have thus far seen a number of concepts and tools that help us study the frequency response of circuits. Specifically, we have observed that: The frequency response refers to the magnitude of the transfer function of a system.9 Bode’s approximation simplifies the task of plotting the frequency response if the poles and zeros are known. In many cases, it is possible to associate a pole with each node in the signal path. Miller’s theorem proves helpful in decomposing floating capacitors into grounded elements. Bipolar and MOS devices exhibit various capacitances that limit the speed of circuits. In order to methodically analyze the frequency response of various circuits, we prescribe the following steps: 1. Determine which capacitors impact the low-frequency region of the response and compute the low-frequency cut-off. In this calculation, the transistor capacitances can be neglected as they typically impact only the high-frequency region. 2. Calculate the midband gain by replacing the above capacitors with short circuits while still neglecting the transistor capacitances. 3. Identify and add to the circuit the capacitances contributed by each transistor. 4. Noting ac grounds (e.g., the supply voltage or constant bias voltages), merge the capacitors that are in parallel and omit those that play no role in the circuit. 5. Determine the high-frequency poles and zeros by inspection or by computing the transfer function. Miller’s theorem may prove useful here. 6. Plot the frequency response using Bode’s rules or exact calculations. We now apply this procedure to various amplifier topologies. 9In a more general case, the frequency response also includes the phase of the transfer function, as studied in Chapter 12. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 558 (1) 558 Chap. 11 Frequency Response 11.4 Frequency Response of CE and CS Stages 11.4.1 Low-Frequency Response As mentioned in Section 11.1.6, the gain of amplifiers may fall at low frequencies due to certain capacitors in the signal path. Let us consider a general CS stage with its input bias network and an input coupling capacitor [Fig. 11.28(a)]. At low frequencies, the transistor capacitances VDD R1 RD VDD Vout VX R1 RD gmRD X Vout X Vout Vin Ci R2 M1 RS Vin Ci R2 M1 RS Cb gmRD 1 + gmRS 1 1 + gmRS ω RSCb RSCb (a) (b) (c) Figure 11.28 (a) CS stage with input coupling capacitor, (b) effect of bypassed degeneration, (c) frequency response with bypassed degeneration. negligibly affect the frequency response, leaving only Ci as the frequency-dependent component. We write Vout=Vin both R1 and R2 are = Vout=VX tied between XVaXn=dVaicng,ronuengdle.cTthcuhsa,nVnoeult-=leVnXgth=m,oRduDla=tiRonS, and note + 1=gm that and VX Vin s = R1jjR2 R1jjR2 + 1 Cis = R1jjR2Cis R1jjR2Cis + 1: (11.51) (11.52) Similar to the high-pass filter of Fig. 11.16, this network attenuates the low frequencies, dictating that the lower cut-off be chosen below the lowest signal frequency, fsig;min (e.g., 20 Hz in audio applications): 1 2 R1jjR2Ci fsig;min: (11.53) In applications demanding a greater midband gain, we place a “bypass” capacitor in parallel with RS [Fig. 11.28(b)] so as to remove the effect of degeneration at midband frequencies. To quantify the role of Cb, we place its impedance, 1=Cbs, in parallel with RS in the midband gain expression: Vout VX s = ,RD RSjj 1 Cbs + 1 gm = ,gmRD RS Cb s RSCbs + gmRS + 1 +1 : (11.54) (11.55) Figure 11.28(c) shows the Bode plot of the frequency response in this case. At frequencies well below the zero, the stage operates as a degenerated CS amplifier, and at frequencies well above BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 559 (1) Sec. 11.4 Frequency Response of CE and CS Stages 559 the pole, the circuit experiences no degeneration. Thus, the pole frequency must be chosen quite smaller than the lowest signal frequency of interest. The above analysis can also be applied to a CE stage. Both types exhibit low-frequency rolloff due to the input coupling capacitor and the degeneration bypass capacitor. 11.4.2 High-Frequency Response Consider the CE and CS amplifiers shown in Fig. 11.29(a), where RS may represent the output impedance of the preceding stage, i.e., it is not added deliberately. Identifying the capacitances  cboayfpQoanc1liaytanrndcMe[Fo1if,gMw. 1e11ai.rs2r9giv(rceo)ua]n,t1dt0heeadncodonmcbaponltebhteeercneidrdscu.ucTiethsdedtosempoiancltele-idsfiigVnniFnali,geR.q1Su1iav.2na9dle(rnbt)s,aworfehterhereepslteahcceeisrdocuwuiritctshed-tbihfufeelikrr Thevenin equivalent [Fig. 11.29(d)]. In practice, RS r and hence RT hev RS. Note that the output resistance of each transistor would simply appear in parallel with RL. VCC RL VDD RL VCC RL Cµ Vout RL C GD VDD Vout RS Vin Vout RS Q1 Vin Vout M1 Vin RS Cπ Q1 C CS Vin CGS M1 C DB C SB (a) (b) Cµ C GD RS Vin RS Vout Vin Vout Cπ rπ vπ g m Vπ CCS RL CGS v GS g mVGS CDB RL RThev X (c) C XY Y VThev Cin VX g mVX C out Vout RL (d) Figure 11.29 (a) CE and CS stages, (b) inclusion of transistor capacitances, (c) small-signal equivalents, (d) unified model of both circuits. With this unified model, we now study the high-frequency response, first applying Miller’s approximation to develop insight and then performing an accurate analysis to arrive at more general results. 10The Early effect and channel-length modulation are neglected here. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 560 (1) 560 Chap. 11 Frequency Response 11.4.3 Use of Miller’s Theorem With CXY tied between two floating nodes, we However, following Miller’s approximation as cannot simply associate one pole with each node. in Example 11.10, we can decompose CXY into two grounded components (Fig. 11.30): CX CY = =  11++ggmmR1RLLC XCYXY : (11.56) (11.57) Now, each node sees a resistance and capacitances only to ground. In accordance with our notations in Section 11.1, we write j!p;inj = RT hev Cin + 1 1 + gmRLCXY j!p;outj = RL  Cout + 1 1 + 1 gmRL CXY : (11.58) (11.59) If gmRL 1, the capacitance at the output node is simply equal to Cout + CXY . R Thev X VThev CX Cin v X Y g mv X Vout C out CY RL CE Stage VThev = Vin rπ r π +RS R Thev = RS r π CX = C µ (1 + gmRL CY = C µ (1 + 1 gmRL ( ( CS Stage VThev = Vin R Thev = RS CX = C GD ( 1 + g m RL CY = C GD (1 + 1 gmRL ( ( Figure 11.30 Parameters in unified model of CE and CS stages with Miller’s approximation. The intuition gained from the application of Miller’s theorem proves invaluable. The input pole is approximately given by the source resistance, the base-emitter or gate-source capacitance, and the Miller multiplication of the base-collector or gate-drain capacitance. The Miller multiplication makes it undesirable to have a high gain in the circuit. The output pole is roughly determined by the load resistance, the collector-substrate or drain-bulk capacitance, and the basecollector or gate-drain capacitance. Example 11.15 In the CE stage of Fig. 11.29(a), RS = 200 ; IC = 1 mA, = 100; C = 100 fF, C = 20 fF, and CCS = 30 fF. (a) Calculate the input and output poles if RL = 2 k . Which node appears as the speed bottle- neck (limits the bandwidth)? (b) Is it possible to choose RL such that the output pole limits the bandwidth? Solution (a) Since r = 2:6 k , we have RT hev = 186 . Fig. 11.30 and Eqs. (11.58) and (11.59) thus BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 561 (1) Sec. 11.4 Frequency Response of CE and CS Stages 561 give j!p;inj = 2  516 MHz j!p;outj = 2  1:59 GHz: (11.60) (11.61) We observe that the Miller effect multiplies C by a factor of 78, making its contribution much greater (b) We than must tsheaetkosfuCch.aAvsalaureeosuf lRt,Lthtehaintpyuiet lpdoslej!lpim;initjs the bandwidth. !p;outj: 1 RSjjr C + 1 + gmRLC RL CCS + 1 1 + 1 gmRL C : (11.62) If gmRL 1, then we have CCS + C , gmRSjjrC RL RSjjrC: (11.63) With the values assumed in this example, the left-hand side is negative, implying that no solution exists. The reader can prove that this holds even if gmRL is not much greater than unity. Thus, the input pole remains the speed bottleneck here. Exercise Repeat the above example if IC = 2 mA and C = 180 fF. Example 11.16 An electrical engineering student designs the CS stage of Fig. 11.29(a) for a certain lowfrequency gain and high-frequency response. Unfortunately, in the layout phase, the student uses a MOSFET half as wide as that in the original design. Assuming that the bias current is also halved, determine the gain and the poles of the circuit. Solution Both the width and the bias current of the transistor are halved, and so is its transconductance (why?). The small-signal gain, gmRL, is therefore halved. Reducing the transistor width by a factor of two also lowers all of the capacitances by the same factor. From Fig. 11.30 and Eqs. (11.58) and (11.59), we can express the poles as j!p;inj = RS  Cin 2 + 1 1 + gmRL 2 CXY 2  j!p;outj = RL  Cout 2 + 1 1 + 2 gmRL CXY 2 ; (11.64) (11.65) iWwmheaetoreeblysCeairnvfe,agcthmtoa,rtC!oXfp;tYiwnaohna(disfCrgisomeunRt diLnenmoateg2nt)h.iteIunpdaoertbahmyermewtoeorrserdctsho,artrnheeaspfgoaancitdnoirinsgohftaotwltvhoee,daoanrnidgd!intpha;eloudbteavbniydcweapwidpitrdhotxhis-. roughly doubled, suggesting that the gain-bandwidth product is approximately constant. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 562 (1) 562 Chap. 11 Frequency Response Exercise What happens if both the width and the bias current are twice their nominal values? 11.4.4 Direct Analysis The use of Miller’s theorem in the previous section provides a quick and intuitive perspective of the performance. However, we must carry out a more accurate analysis so as to understand the limitations of Miller’s approximation in this case. The circuit of Fig. 11.29(d) contains two nodes and can therefore be solved by writing two KCLs. That is,11 At At Node Node X: Y: Vout , VXCXY VX , VoutCXY s s = = VgmXVCXin+s +VoVutX R,RT1hVLeTv+hevCouts : (11.66) (11.67) We compute VX from (11.67): VX = Vout CXYCsX+YRs1L,+gmCouts (11.68) and substitute the result in (11.66) to arrive at VoutCXY s , CXY s + Cins + 1 RT hev CXY Cs X+YRs1L,+gmCouts Vout = ,VT hev RT hev : (11.69) It follows that Vout VT hev s = CXY as2 s , gmRL + bs + 1 ; (11.70) where a = RThevRLCinCXY + CoutCXY + CinCout b = 1 + gmRLCXY RThev + RThevCin + RLCXY + Cout: (11.71) (11.72) Note from Fig. 11.30 that for Vout=Vin—without affecting a CE stage, the location (11.70) must be of the poles and multiplied the zero. by r=RS + r to obtain Let us examine the above results carefully. The transfer function exhibits a zero at !z = gm CXY : (11.73) 11Recall that we denote frequency-domain quantities with upper-case letters. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 563 (1) Sec. 11.4 Frequency Response of CE and CS Stages 563 (The Miller approximation fails to predict this zero.) Since CXY (i.e., the base-collector or the gate-drain overlap capacitance) is relatively small, the zero typically appears at very high frequencies and hence is unimportant.12 As expected, the system contains two poles given by the values of s that force the denominator to zero. We can solve the quadratic as2 + bs + 1 = 0 to determine the poles but the results provide little insight. Instead, we first make an interesting observation in regards to the quadratic denominator: if the poles are given by !p1 and !p2, we can write as2 + bs + 1 = = !p!s1sp!21p2++1 !1p!1sp2++!11p2 s + 1: (11.74) (11.75)  tNThhoeew“nd,sou!mpp,p1i1on+saen!topnp,2oe1lpeo”l!eapp,isp11rm,oixu.eicm.h, aftairotnhetrofreommphthaesiozreigthinatth!apn1thdeomotihneart:e!s pth2e !p1. (This is called frequency response). b = 1 !p1 ; (11.76) and from (11.72), j!p1j = 1 + gmRLCXY RT hev + 1 RT hev Cin + RLCXY + Cout: (11.77) How does this result compare with that obtained using the Miller approximation? Equa- tion (11.77) does reveal the Miller effect of CXY but it also contains the additional term RLCXY + Cout [which is close to the output time constant predicted by (11.59)]. To determine the “nondominant” pole, !p2, we recognize from (11.75) and (11.76) that j!p2j = b a = 1 + gmRLCXY RThev + RT hev RLCin CX Y RThevCin + RLCXY + + CoutCXY + CinCout Cout  : (11.78) (11.79) Example 11.17 Using the dominant-pole approximation, compute the poles of the circuit shown in Fig. 11.31(a). 6 Assume both transistors operate in saturation and  = 0. Solution Noting that CSB1, CGS2, and CSB2 do not affect the circuit (why?), we add the remaining capacitances as depicted in Fig. 11.31(b), simplifying the result as illustrated in Fig. 11.31(c), where Cin = CGS1 CXY = CGD1 Cout = CDB1 + CGD2 + CDB2: (11.80) (11.81) (11.82) 12As explained in more advanced courses, this zero does become problematic in the internal circuitry of op amps. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 564 (1) 564 Vb RS Vin Chap. 11 Frequency Response C SB2 M 2 CDB2 VDD M2 C GD2 C GD1 Vout C XY Vout M1 RS Vin CGS1 RS M1 CDB1 Vin Cin Vout M1 C out r O1 r O2 (a) (b) (c) Figure 11.31 It follows from (11.77) and (11.79) that !p1  1 1 + gm1rO1jjrO2 CXY RS + RSCin + rO1jjrO2CXY + Cout (11.83) !p2  1 + gm1rO1jjrO2 CXY RS + RSCin + rO1jjrO2CXY RSrO1jjrO2CinCXY + CoutCXY + CinCout + Cout : (11.84) Exercise Repeat the above example if  6= 0. Example 11.18 In the CS stage of CDB = 100 fF; gm F=ig.11510.29(a,)1, ;we=ha0v;eanRdS = RL 200 =2 k ; CGS . Plot = the 250 fF, CGD = 80 fF, frequency response with the aid of (a) Miller’s approximation, (b) the exact transfer function, (c) the dominant-pole approximation. Solution (a) With gmRL = 13:3, Eqs. (11.58) and (11.59) yield j!p;inj = 2  571 MHz j!p;outj = 2  428 MHz: (11.85) (11.86) (ab=) T2h:e12tran1sf0e,r2f0usn,c2tioanndinb E=q6. :(3191.701)0g,iv10ess.aTzheurso, at gm=CGD = 2  13:3 GHz). Also, j!p1j = 2  264 MHz j!p2j = 2  4:53 GHz: (11.87) (11.88) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 565 (1) Sec. 11.4 Frequency Response of CE and CS Stages 565 Note the large error in the values predicted by Miller’s approximation. This error arises be- cause we have multiplied CGD by the midband gain 1 + gmRL rather than the gain at high frequencies.13 (c) The results obtained in part (b) predict that the dominant-pole approximation produces relatively accurate results as the two poles are quite far apart. From Eqs. (11.77) and (11.79), we have j!p1j = 2  249 MHz j!p2j = 2  4:79 GHz: (11.89) (11.90)  , Figure 11.32 plots the results. The low-frequency gain is equal to 22 dB 13 and the 3-dB bandwidth predicted by the exact equation is around 250 MHz. Magnitude of Transfer Function (dB) 30 20 10 0 −10 −20 −30 107 Figure 11.32 Dominant−Pole Appr. Miller’s Approx. Exact Eq. 108 109 1010 Frequency (Hz) Exercise Repeat the above example if the device width (and hence its capacitances) and the bias current are halved. 11.4.5 Input Impedance The high-frequency input impedances of the CE and CS amplifiers determine the ease with which these circuits can be driven by other stages. Our foregoing analysis of the frequency response and particularly the Miller approximation readily yield this impedance. j! j j! j 13The large discrepancy between p;out and p2 results from an effect called “pole splitting” and studied in more advanced courses. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 566 (1) 566 Chap. 11 Frequency Response As illustrated in Fig. 11.33(a), the input impedance of a CE stage consists of two parallel components: C + 1 + gmRDC and r.14 That is, VCC RC Cµ C GD VDD RD Cπ Z in Q1 C CS CGS Z in M1 C DB (a) (b) Figure 11.33 Input impedance of (a) CE and (b) CS stages. Zin  C + 1 + 1 gmRDC s jjr : (11.91) Similarly, the MOS counterpart exhibits an input impedance given by Zin  CGS + 1 + 1 gmRDCGD s : (11.92) With a high voltage gain, the Miller effect may substantially lower the input impedance at high frequencies. 11.5 Frequency Response of CB and CG Stages 11.5.1 Low-Frequency Response As with CE and CS stages, the use of capacitive coupling leads to low-frequency roll-off in CB and CG amplifiers. Consider the CB circuit depicted in Fig. 11.34(a), where I1 defines the bias VCC RC Vout Q1 Vb RS Ci Vin I1 (a) Vout Vin RD RS+ 1 gm gm ω (1 + gmRS Ci ( (b) Figure 11.34 (a) CB stage with input capacitor coupling, (b) resulting frequency response. current of Q1 and the collector bias Vb is chosen to ensure operation in voltage). How large should Ci be? the forward active Since Ci appears region (Vb is less in series with RS than , we R 14In calculation of the input impedance, the output impedance of the preceding stage (denoted by S ) is excluded. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 567 (1) Sec. 11.5 Frequency Response of CB and CG Stages 567 replace RS with RS + Cis,1 in the midband gain expression, RC=RS + 1=gm, and write the resulting transfer function as Vout Vin s = RS + RC Cis,1 + 1=gm = 1 + gm RC Ci s gmRSCis + gm : (11.93) (11.94) Equation (11.93) implies that the signal does not “feel” the effect of Ci if jCis,1j RS + 1=gm. From another perspective, Eq. (11.94) yields the response shown in Fig. 11.34(b), revealing a pole at j!pj = 1 + gm gmRS Ci (11.95) and suggesting that this pole must remain quite lower than the minimum signal frequency of interest. These two conditions are equivalent. 11.5.2 High-Frequency Response We know from Chapters 5 and 7 that CB and CG stages exhibit a relatively low input impedance ( 1=gm). The high-frequency response of these circuits does not suffer from Miller effect, an important advantage in some cases. 1 Consider the stages shown in Fig. 11.35, where rO = and the transistor capacitances are VCC RC CCS Y C µ Vout Q1 RS Vin X Vb Cπ VDD RD CDB Y CGD Vout M1 Vin RS X Vb C GS C SB (a) (b) Figure 11.35 (a) CB and (b) CG stages including transistor capacitances. included. Since Vb is at ac ground, we note that (1) C and CGS + CSB go to ground; (2) CCS and C of Q1 appear in parallel to ground, and so do CGD and CDB of M1; (3) no capacitance appears between the input and output networks, avoiding Miller effect. In fact, with all of the capacitances seeing ground at one of their terminals, we can readily associate one pole with each node. At node X, the total resistance seen to ground is given by RSjj1=gm, yielding j!p;X j = RSjj 1 1 gm CX ; (11.96) where CX = C or CGS + CSB. Similarly, at Y , j!p;Y j = 1 RLCY ; (11.97) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 568 (1) 568 Chap. 11 Frequency Response where CY = C + CCS or CGD + CDB. It is interesting to note that the “input” pole magnitude is on the order of the fT of the transis- tor: CX is equal to C or roughly equal to CGS while the resistance seen to ground is less than 1=gm. For this reason, the input pole of the CB/CG stage rarely creates a speed bottleneck.15 Example 11.19 Compute the poles of the circuit shown in Fig. 11.36(a). Assume  = 0. C SB2 VDD VDD M2 Vout RSM 1 Vb Vin M2 Y Vout RSM 1 Vb CDB1 + CGD1 + CGS2 + CDB2 Vin X CSB1 + CGS1 (a) (b) Figure 11.36 Solution Noting that CGD2 and CSB2 play no role in the circuit, we add the device capacitances as de- picted in Fig. 11.36(b). The input pole is thus given by j!p;X j = RS jj 1 gm1 1 CSB1 + : CGD1 (11.98) Since the small-signal resistance at the output node is equal to 1=gm2, we have j!p;Y j = 1 gm2 CDB1 1 + CGD1 + CGS2 : + CDB2 (11.99) Exercise Repeat the above example if M2 operates as a current source, i.e., its gate is connected to a constant voltage. Example 11.20 The CS stage of Example 11.18 is reconfigured to a common-gate amplifier (with RS tied to the source of the transistor). Plot the frequency response of the circuit. 15One exception is encountered in radio-frequency circuits (e.g., cellphones), where the input capacitance becomes undesirable. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 569 (1) Sec. 11.6 Frequency Response of Followers 569 Solution With the values given in Example 11.18 and noting that CSB = CDB,16 we obtain from Eqs. (11.96) and (11.97), j!p;Xj = 2  5:31 GHz j!p;Y j = 2  442 MHz: (11.100) (11.101) With no Miller effect, the input pole has dramatically risen in magnitude. The output pole, how- ever, limits the bandwidth. Also, the low-frequency gain is now equal to RD=RS+1=gm = 5:7, more than a factor of two lower than that of the CS stage. Figure 11.37 plots the result. The low- frequency gain is equal to 15 dB  5:7 and the ,3-dB bandwidth is around 450 MHz. 20 Magnitude of Frequency Response (dB) 15 10 5 0 −5 −10 −15 −20 106 107 108 109 1010 Frequency (Hz) Figure 11.37 Exercise Repeat the above example if the CG amplifier drives a load capacitance of 150 fF. 11.6 Frequency Response of Followers The low-frequency response of followers is similar to that studied in Example 11.11 and that of CE/CS stages. We thus study the high-frequency behavior here. In Chapters 5 and 7, we noted that emitter and source followers provide a high input impedance and a relatively low output impedance while suffering from a sub-unity (positive) C C 16In reality, the junction capacitances SB and DB sustain different reverse bias voltages and are therefore not quite equal. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 570 (1) 570 Chap. 11 Frequency Response voltage gain. Emitter followers, and occasionally source followers, are utilized as buffers and their frequency characteristics are of interest. Figure 11.38 illustrates the stages with relevant capacitances. The emitter follower is loaded with CL to create both a more general case and greater similarity between the bipolar and MOS counterparts. We observe that each circuit contains two grounded capacitors and one floating ca- pacitor. While the latter may be decomposed using Miller’s approximation, the resulting analysis is beyond the scope of this book. We therefore perform a direct analysis by writing the circuit’s equations. Since the bipolar and MOS versions in Fig. 11.38 differ by only r, we first analyze the emitter follower and subsequently let r (or ) approach infinity to obtain the transfer function of the source follower. Cµ VCC C GD VDD C DB Vin RS X Q1 Cπ Y Vout Vin RS X M1 C GS Y Vout CL CSB + CL (a) (b) Figure 11.38 (a) Emitter follower and (b) source follower including transistor capacitances. Consider the small-signal equivalent shown in Fig. 11.39. Recognizing that VX = Vout + V and the current through the parallel combination of r and C is given by V=r + VCs, we write a KCL at node X: RS X Vin C µ C π r π Vπ g m Vπ Vout CL Figure 11.39 Small-signal equivalent of emitter follower. Vout + V RS , Vin + Vout + VCs + V r + VCs = 0; and another at the output node: V r + VCs + gmV = VoutCLs: The latter gives V = 1 r VoutCLs ; + gm + Cs (11.102) (11.103) (11.104) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 571 (1) Sec. 11.6 Frequency Response of Followers 571 which, upon substitution in (11.102) and with the assumption r Vout Vin = 1 + C gm s as2 + bs + 1; gm,1 leads to (11.105) where a b = = RRgmSSCC +CCgm++C C1L++RrCS CLCgmL : (11.106) (11.107) The circuit thus exhibits a zero at j!zj = gm C ; (11.108) which, from (11.49), is near the fT of the transistor. The poles of the circuit can be computed using the dominant-pole approximation described in Section 11.4.4. In practice, however, the two poles do not fall far from each other, necessitating direct solution of the quadratic denominator. ! 1 The above results also apply to the source follower substitutions are made (CSB and CL are in parallel): if r and corresponding capacitance Vout Vin = 1 + CGS gm s as2 + bs + 1 ; (11.109) where a = RS gm CGDCGS + CGDCSB + CL + CGSCSB + CL b = RSCGD + CGD + CSB gm + CL : (11.110) (11.111) Example 11.21 A source follower is driven by a resistance of 200 and drives a load capacitance of 100 fF. Using the transistor parameters given in Example 11.18, plot the frequency response of the circuit. Solution The zero occurs at gm=CGS = 2  4:24 GHz). To compute the poles, we obtain a and b from Eqs. (11.110) and (11.111), respectively: a = 2:58  10,21 s,2 b = 5:8  10,11 s (11.112) (11.113) The two poles are then equal to !p1 = 2 ,1:79 GHz + j2:57 GHz !p2 = 2 ,1:79 GHz , j2:57 GHz : (11.114) (11.115) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 572 (1) 572 Chap. 11 Frequency Response With the values chosen here, the poles are complex. Figure 11.40 plots the frequency response. , The 3-dB bandwidth is approximately equal to 3.5 GHz. Magnitude of Frequency Response (dB) 0 −2 −4 −6 −8 −10 −12 −14 106 Figure 11.40 107 108 109 Frequency (Hz) 1010 Exercise For what value of gm do the two poles become real and equal? Example 11.22 Determine the transfer function of the source follower shown in Fig. 11.41(a), where M2 acts as a current source. RS Vin VDD M1 Vb M2 Vout (a) Figure 11.41 CGD1 VDD Vin RS X M1 C GS1 Y C DB1 Vout C GD2 CDB2 + CSB1 Vb CGS2 M 2 C SB2 (b) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 573 (1) Sec. 11.6 Frequency Response of Followers 573 Solution NailplouptseitnargaritntehgdaitinnCpFGaiSrga2.ll1aen1ld.w4C1it(hSbB)C.2STpBhl1ae.yrTenhsouurlsto,lr(ee1si1en.m1t0hb9ele)csciratchnuabitte,inwreeFwiigrni.cttl1eu1nd.3eas8th, ebutrtawnsiitshtoCrGcDap2acaintdanCceDsBa2s Vout Vin s = 1 + CGS1 gm1 s as2 + bs + 1 ; (11.116) where a = RS gm1 CGD1CGS1 + CGD1 + CGS1CSB1 + CGD2 + CDB2 b = RSCGD1 + CGD1 + CSB1 + CGD2 gm1 + CDB2 : (11.117) (11.118) Exercise Assuming M1 and M2 are identical and using the transistor parameters given in Example 11.18, calculate the pole frequencies. 11.6.1 Input and Output Impedances In Chapter 5, we observed that the input resistance of the emitter follower is given by r +  + 1RL, where RL denotes the load resistance. Also, in Chapter 7, we noted that the source follower input resistance approaches infinity at low frequencies. We now employ an approximate but intuitive analysis to obtain the input capacitance of followers. Consider the circuits shown in Fig. 11.42, where C and CGS appear between the input and output and can therefore be decomposed using Miller’s theorem. Since the low-frequency gain is equal to Cµ VCC C GD VDD X Q1 CXY = C π Y X M1 CXY = CGS Y C DB RL CL RL CL+ CSB (a) (b) Figure 11.42 Input impedance of (a) emitter follower and (b) source follower. Av = RL RL + 1 gm ; (11.119) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 574 (1) 574 Chap. 11 Frequency Response we note that the “input” component of C or CGS is expressed as CX = 1 , AvCXY = 1 + 1 gmRL CXY : (11.120) (11.121) Interestingly, the input capacitance of the follower contains only a fraction of C or CGS, depending on how large gmRL is. Of course, C or CGD directly adds to this value to yield the total input capacitance. Example 11.23 6 Estimate the input capacitance of the follower shown in Fig. 11.43. Assume  = 0. VDD Vin M1 Figure 11.43 Vb M2 Solution From Chapter 7, the low-frequency gain of the circuit can be written as Av = rO1jjrO2 rO1jjrO2 + 1 gm1 : (11.122) Also, from Fig. 11.42(b), the capacitance appearing between the input and output is equal to CGS1, thereby providing Cin = CGD1 + 1 , AvCGS1 = CGD1 + 1 + 1 gm1rO1jjrO2 CGS1: For example, if gm1rO1jjrO2  10, then only 9 of CGS1 appears at the input. (11.123) (11.124) Exercise Repeat the above example if  = 0. Let us now turn our attention to the output impedance of followers. Our study of the emitter follower Chapter in Chapter 5 revealed that the output resistance is equal to 7 indicated an output resistance of 1=gm for the source RS= +1+1=gm. Similarly, follower. At high frequencies, these circuits display an interesting behavior. Consider the followers depicted in Fig. 11.44(a), where other capacitances and resistances are neglected for the sake of simplicity. As usual, RS represents the output resistance of a preceding stage or device. We first compute the output impedance of the emitter follower and subsequently BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 575 (1) Sec. 11.6 Frequency Response of Followers 575 RS Vin Cπ VCC RS Q1 Vin C GS Z out VDD M1 Z out RS Cπ r π Vπ g m Vπ IX VX (a) (b) Figure 11.44 (a) Output impedance of emitter and source followers, (b) small-signal model. ! 1 let r to determine that of the source follower. From the equivalent circuit in Fig. 11.44(b), we have IX + gmV  rjj 1 Cs = ,V (11.125) and also IX + gmVRS , V = VX: (11.126) Finding V from (11.125) V = ,IX r rCs + +1 (11.127) and substituting in (11.126), we obtain VX IX = RSrCs rCs + + r + RS +1 : (11.128) As the eoxthpeerchteadn,da,taltovwerfyrehqiguhenfcreieqsueVnXc=ieIsX, V=X =IrX + = RRSS,a=me+an1ingful 1=gm result + RS= + 1. considering that On C becomes a short circuit. The two extreme values calculated above for the output impedance of the emitter follower can be used to develop greater insight. Plotted in Fig. 11.45, the magnitude of this impedance falls with with ! if the RS 1=gm + RS= + 1 or rises with ! impedance of capacitors and inductors, we siafyRZSout 1=gm + exhibits RS= + 1. In analogy a capacitive behavior in the former case and an inductive behavior in the latter. Zout RS β+ 1 + 1 gm RS Zout RS ω RS β+ 1 + 1 gm (a) ω (b) Figure 11.45 Output impedance of emitter follower as a function of frequency for (a) small RS and (b) large RS. Which case is more likely to occur in practice? Since a follower serves to reduce the driving impedance, it is reasonable to assume that the follower low-frequency output impedance is lower BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 576 (1) 576 Chap. 11 Frequency Response than RS.17 Thus, the inductive behavior is more commonly encountered. ( It is even possible that the inductive output impedance leads to oscillation if the follower sees a certain amount of load capacitance.) The above development can be extended to source ator and denominator of (11.128) and letting r and followers by factoring approach infinity: r from the numer- VX IX = RSCGSs CGSs + +1 gm ; (11.129) where  + 1=r is replaced with gm, and C with CGD. The plots of Fig. 11.45 are redrawn for the source follower in Fig. 11.46, displaying a similar behavior. Zout Zout 1 gm RS ω (a) RS 1 gm ω (b) Figure 11.46 Output impedance of source follower as a function of frequency for (a) small RS and (b) large RS. The inductive impedance seen at the output of followers proves useful in the realization of “active inductors.” Example 11.24 Figure 11.47 depicts a two-stage amplifier consisting of a CS circuit and a source follower. 6 Assuming  = CGS3, compute 0 for M1 the output and M2 but  = 0 for M3, impedance of the amplifier. and neglecting all capacitances except Vb M2 Vin M1 VDD M3 Vout r O1 r O2 VDD M3 (a) Figure 11.47 Z out (b) Solution The source impedance seen by the follower is equal to the output resistance of the CS stage, which is equal to rO1jjrO2. Assuming RS = rO1jjrO2 in (11.129), we have VX IX = rO1jjrO2CGS3s CGS3s + gm3 + 1 : (11.130) R 17If the follower output resistance is greater than S, then it is better to omit the follower! BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 577 (1) Sec. 11.7 Frequency Response of Cascode Stage 577 Exercise Determine Zout in the above example if  6= 0 for M1-M3. 11.7 Frequency Response of Cascode Stage Our analysis of the CE/CS stage in Section 11.4 and the CB/CG stage in Section 11.5 reveals that the former provides a relatively high input resistance but it suffers from Miller effect whereas the latter exhibits a relatively low input resistance but it is free from Miller effect. We wish to combine the desirable properties of the two topologies, obtaining a circuit with a relatively high input resistance and no or little Miller effect. Indeed, this thought process led to the invention of the cascode topology in the 1940s. Consider the cascodes shown in Fig. 11.48. As mentioned in Chapter 9, this structure can be VCC RL Vout Vb1 Q2 C µ1 RS Y Vin Q1 X VDD RL Vout Vb M2 C GD1 RS Y Vin X M1 (a) (b) Figure 11.48 (a) Bipolar and (b) MOS cascode stages. 1 vcaWiirevecwoumleittadusgsatetislfilgaerasxCitnhEcieb/oCqimtuSsapatlurratteoenlastgihtmsievto1evRrl,oyLQlht.ai11gg8oehBr(gfMuaotir,n1Qh, fofr1owo)lmlooarwbnioneoufiddtnebtiyhtXeea(fMtCooBrilnMl/oeCrd1Ge)midYnuepl.vtuiiAptclresiesc,suaQimtsi2toainnongrcoeMfrwOC2h.=iA1lesopsrruoCcvfhGoid,rDitanh1lg?el transistors, we recognize that the impedance seen at Y is equal to 1=gm2, yielding a small-signal gain of Av;XY = = vY ,vXggmm21 : (11.131) (11.132) , , IwMne1tahkaendbdeippMeonl2adrneenceacdsecunopodoten,begWmid=1eLn=.tiWcgamel,2thb(euwrtehgfyom?r1)e, resulting in and gm2 are say the gain a gain of 1. In the MOS counterpart, comparable because of their relatively from X to Y remains near 1 in most R r 18The voltage division between S and 1 lowers the gain slightly in the bipolar circuit. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 578 (1) 578 Chap. 11 Frequency Response practical cases, concluding that the Miller effect of CXY = C1 or CGD1 is given by CX = 1 , Av;XY CXY  2CXY : (11.133) (11.134) This result stands in contrast to that expressed by (11.56), suggesting that the cascode transistor breaks the trade-off between the gain and the input capacitance due to Miller effect. Let us continue our analysis and estimate the poles of the cascode topology with the aid of Miller’s approximation. Illustrated in Fig. 11.49 is the bipolar cascode along with the transis- Vb1 RS X Vin C π 1+ 2C µ1 VCC RL Q2 Y Q1 Vout CCS2 + C µ2 CCS1 + C π 2+ 2C µ1 Figure 11.49 Bipolar cascode including transistor capacitances. tor capacitances. Note that the effect of C1 at Y is also equal to 1 , A,v;1XY C1 = 2C1. Associating one pole with each node gives j!p;X j = 1 RS jjr1 C1 + 2C1 j!p;Y j = 1 gm2 CCS1 1 + C2 + 2C1 j!p;outj = 1 RLCCS2 + C2  : (11.135) (11.136) (11.137) It is interesting to note that the pole at node Y falls near Even for comparable values fT =2, a frequency typically of C2 and CCS1 + much higher than the 2C1, signal the fT of Q2 if we can say this bandwidth. For C2 CCS1 + 2C1. pole is on the order of this reason, the pole at node Y often has negligible effect on the frequency response of the cascode stage. The MOS cascode is shown in Fig. 11.50 along with its capacitances after the use of Miller’s , approximation. Since the gain from X to Y in this case may not be equal to 1, we use the actual , value, gm1=gm2, to arrive at a more general solution. Associating one pole with each node, we have j!p;X j = RS CGS1 + 1 1+ gm1 gm2 CGD1 j!p;Y j = 1 gm2 1 CDB1 + CGS2 + 1 + gm2 gm1 CGD1 + CSB2 j!p;outj = 1 RLCDB2 + CGD2 : (11.138) (11.139) (11.140) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 579 (1) Sec. 11.7 Frequency Response of Cascode Stage 579 VDD RL Vb RS X Vin CGS1 + CGD1 (1+ g m1 g m2 ) M2 Y M1 Vout CGD2 + CDB2 CGS2 + CGD1 (1+ g m2 g m1 ) + CDB1 + CSB2 Figure 11.50 MOS cascode including transistor capacitances. We note that !p;Y is still in the range of fT =2 if CGS2 and CDB1 + 1 + gm2=gm1CGD1 are comparable. Example 11.25 The CS stage studied in Example 11.18 is converted to a cascode topology. Assuming the two transistors are identical, estimate the poles, plot the frequency response, and compare the results with those of Example 11.18. Assume CDB = CSB. Solution Using the values given in Example 11.18, we write from Eqs. (11.138) (11.139), and (11.140): j!p;Xj = 2  1:95 GHz j!p;Y j = 2  1:73 GHz j!p;outj = 2  442 MHz: (11.141) (11.142) (11.143) Note that the pole at node Y is quite lower than fT =2 in this particular example. Compared with the Miller approximation results obtained in Example 11.18, the input pole has risen consider- ably. Compared with the exact values derived in that example, the cascode bandwidth (442 MHz) is nearly twice as large. Figure 11.51 plots the frequency response of the cascode stage. Exercise RAesspuematethgem2ab=ove10e0xamp,l1e. if the width of M2 and hence all of its capacitances are doubled. Example 11.26 In the M1 to ccaasrcryodaelasrhgoewr ncuirnreFnitgt.h1a1n.5M2,2t.rEanstsiimstaotreMth3e serves as a constant current source, allowing poles of the circuit, assuming  = 0. Solution Transistor M3 contributes CGD3 and CDB3 to node Y , thus lowering the corresponding pole magnitude. The circuit contains the following poles: j!p;X j = RS CGS1 + 1 1+ gm1 gm2 CGD1 (11.144) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 580 (1) 580 Chap. 11 Frequency Response 30 Magnitude of Frequency Response (dB) 20 10 0 −10 −20 −30 106 Figure 11.51 107 108 109 Frequency (Hz) 1010 Vb2 M3 Vb1 RS Vin X VDD RL Vout M2 Y M1 Figure 11.52 . j!p;Y j = 1 gm2 CDB1 + CGS2 + 1 + 1 gm2 gm1 CGD1 + CGD3 + CDB3 j!p;outj = 1 RLCDB2 + CGD2 : (11.145) (11.146) Note gm2. that !p;X also reduces in magnitude because the addition of M3 lowers ID2 and hence Exercise Calculate the pole frequencies in the above example using the transistor parameters given in Example 11.18 for M1-M3. From our studies of the cascode topology in Chapter 9 and in this chapter, we identify two important, distinct attributes of this circuit: (1) the ability to provide a high output impedance and BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 581 (1) Sec. 11.8 Frequency Response of Differential Pairs 581 hence serve as a good current source and/or high-gain amplifier; (2) the reduction of Miller effect and hence better high-frequency performance. Both of these properties are exploited extensively. 11.7.1 Input and Output Impedances The foregoing analysis of the cascode stage readily provides estimates for the I/O impedances. From Fig. 11.49, the input impedance of the bipolar cascode is given by Zin = r1 jj C1 1 + 2C1 s ; (11.147) where Zin does not include RS. The output impedance is equal to Zout = RLjj C2 1 + CC S2s ; (11.148) where the Early effect is neglected. Similarly, for the MOS stage shown in Fig. 11.50, we have Zin = CGS1 + 1 1 + gm1 gm2 CGD1 s Zout = 1 RLCGD2 + CDB2  ; (11.149) (11.150) where it is assumed  = 0 If RL is large, the output resistance of the transistors must be taken into account. This calcu- lation is beyond the scope of this book. 11.8 Frequency Response of Differential Pairs The half-circuit concept introduced in Chapter 10 can also be applied to the high-frequency model of differential pairs, thus reducing the circuit to those studied above. Figure 11.53(a) depicts two bipolar and MOS differential pairs along with their capacitances. For small differential inputs, the half circuits can be constructed as shown in Fig. 11.53(b). The transfer function is therefore given by (11.70): Vout VT hev s = CXY as2 s , gmRL + bs + 1 ; (11.151) where the same notation is used for various parameters. Similarly, the input and output impedances (from each node to ground) are equal to those in (11.91) and (11.92), respectively. Example 11.27 A differential pair employs cascode devices to lower the Miller effect [Fig. 11.54(a)]. Estimate the poles of the circuit. Solution Employing the half circuit shown in Fig. 11.54(b), we utilize the results obtained in Section 11.7: j!p;X j = RS CGS1 + 1 1+ gm1 gm3 CGD1 (11.152) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 582 (1) 582 Vin1 RC CCS1 C µ1 RS Cπ2 Q1 VCC RC CCS2 C µ2 RS Q2 Cπ1 Vin2 I EE Vin1 Chap. 11 RD C DB1 C GD1 RS CGS1 M1 Frequency Response VDD RD C DB2 C GD2 RS M 2 CGS2 Vin2 C SB1 I SS C SB2 Vin1 RC C µ1 RS Cπ2 Q1 VCC Vout1 C CS1 (a) Vin1 RS CGS1 RD C GD1 M1 VDD C DB1 C SB1 (b) Figure 11.53 (a) Bipolar and MOS differential pairs including transistor capacitances, (b) half circuits. Vin1 RD M3 Vb Vout VDD RD M4 RS RS M1 M2 I SS (a) Figure 11.54 VDD RD Vin2 Vb M3 RS X Y Vin M1 Vout CGD3 + CDB3 CGS1 + CGD1 (1+ g m1 g m3 ) CGS3 + CGD1 (1+ g m3 g m1 ) + CDB1 + CSB3 (b) j!p;Y j = 1 gm3 1 CDB1 + CGS3 + 1 + gm3 gm1 CGD1 j!p;outj = 1 RLCDB3 + CGD3 : (11.153) (11.154) Exercise BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 583 (1) Sec. 11.8 Frequency Response of Differential Pairs 583 p Calculate the pole frequencies using the transistor parameters given in Example 11.18 Assume the width and hence the capacitances of M3 are twice those of M1. Also, gm3 = 2gm1. 11.8.1 Common-Mode Frequency Response The CM response studied in Chapter 10 included no transistor capacitances. At high frequencies, capacitances may raise the CM gain (and lower the differential gain), thus degrading the common-mode rejection ratio. Let us consider the MOS differential pair shown in Fig. 11.55(a), where a finite capacitance VCM VDD RD Vout1 RD + ∆RD Vout2 M1 M2 P I EE R SS C SS CM Gain gm ∆RD ∆RD 2 R SS + 1 gm 1 2 gm ω R SSCSS CSS (a) (b) Figure 11.55 (a) Differential pair with parasitic capacitance at the tail node, (b) CM frequency response. appears between node P between P and ground to and fall ground. Since CSS at high frequencies, shunts RSS leading toa , we expect the total impedance higher CM gain. In fact, we can simply replace RSS with RSSjj 1=CSSs in Eq. (10.186): Vout VCM = 1 gm RD + 2RSSjj 1 CSS s  = gmRDRSSCSS + RSSCSSs + 2gmRSS 1 +1 : (11.155) (11.156) Since RSS is typically quite large, 2gmRSS 1, yielding the following zero and pole frequen- cies: j!zj = 1 RSSCSS j!pj = 2gm CSS ; (11.157) (11.158) and the Bode approximation plotted in Fig. 11.55(b). The CM gain indeed rises dramatically at high frequencies—by a factor of 2gmRSS (why?). Figure 11.56 depicts the transistor capacitances that constitute CSS. For cally a wide device so that it can operate with a small VDS, thereby adding example, M3 is typi- large capacitances to node P . This section can be skipped in a first reading. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 584 (1) 584 Chap. 11 Frequency Response M1 M2 P C SB1 C GD3 Vb M3 C SB3 C SB2 Figure 11.56 Transistor capacitance contributions to the tail node. 11.9 Additional Examples Example 11.28 The amplifier shown in Fig. 11.57(a) incorporates capacitive coupling both at the input 100 k Ω RB1 R C 1 kΩ 200 nF R B2 C1 Vin X Q1 C2 200 nF R in2 VCC = 2.5 V 50 kΩ Y Q2 Vout 1 kΩ RE Q1 I1 C2 RC (a) VY R in2 VThev RC C2 VY R in2 (b) (c) Figure 11.57 . aISnd=b5etwe1e0n,1th6eA,two=st1a0g0e,sa. nDdeVteArm=in1e .the low-frequency cut-off of the circuit. Assume Solution We must first compute the operating point and small-signal parameters of the circuit. From Chap- ter 5, we begin with an estimate of as VCC , VBE1=RB1 and hence for VBE1, e.g., 800 mV, and express the base current of Q1 IC1 = VCC , VBE1 RB1 = 1:7 mA: (11.159) (11.160) It14fo:9llow,s 1thaantdVrB1E=1 = VT 1:49 k ln. FIoCr1Q=I2S, 1we = 748 have mV and IC1 = 1:75 mA. Thus, gm1 = VCC = IB2RB2 + VBE2 + REIC2; (11.161) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 585 (1) Sec. 11.9 Additional Examples 585 and, therefore, IC2 = VCC , RB2= VBE2 + RE = 1:13 mA; (11.162) (11.163) wawrnhi2dtLehjrjreRetth2iBeut 1=siis,nnta2phos:ues2wtu2lormcekwosei-ndsf.strViaedBnqecuEree2tnohcfeyt8fich0ures0tt-comisrftcfVauo.gifIett,tehbRriaysitnisio1ttsna,egtylhefi.ueisslCdeaasqtpItueaCanc2liuttoa=otrin1Cg:11l7ofwmorAmfr.seTqahuuehsni,gcghiem-sp2.aSs=sinfic2el2teR:r2ianl1o,n=g1 !L1 = 1 r1jjRB1C1 = 2  542 Hz: (11.164) (11.165) The second coupling capacitor also creates a high-pass response along with the input resistance ocsiofmnthpstelreurscettoctohrneepdsliasmtcaepgIlei1,fiaeRndidnin2RteC=rfwaRcietBhs2ahjjoTrwhne2vi+ennFinige.+q1u1i1v.5aR7le(Enbt).,aFTniodg.cd1oe1mte.5prm7u(ticen)e,thwVehYce=urIet-1Vo. fTIfnhfetrvheiq=suce,anscIey1,,RitwCies. We now have VY VT hev s = RC + Rin2 1 C2 s + Rin2 ; (11.166) obtaining a pole at !L2 = RC + 1 Rin2C2 =   22:9 Hz: (11.167) (11.168) Since drops !L2 by 3 dB!aLt 1!,Lw1.e conclude that !L1 “dominates” the low-frequency response, i.e., the gain Exercise Repeat the above example if RE = 500 . Example 11.29 The circuit of Fig. 11.58(a) is an example of amplifiers realized in integrated circuits. It consists of a M1 adnedgeMne2raatreedisdteangteicaanldanadsehlafv-beiathseedsasmtageep,awraimthemteorsdearsattehovsaelugeisvefnorinC1Exaanmd pCle2.1A1.s1s8u,mpilnogt the frequency response of the amplifier. Solution BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 586 (1) 586 Chap. 11 Frequency Response VDD R D1 1 kΩ C2 X R D2 RF 1 kΩ RS Vin 200 Ω M 1 10 pF 10 k Ω Vout M2 R S1 C1 50 pF 200 Ω (a) ac GND R D1 1 kΩ R D2 X RF 1 kΩ RS v in 200 Ω M1 R in2 10 k Ω v out M2 ac GND (b) R D1 C GD1 RS Vin CGS1 M1 R D2 RF X C GD2 Vout CDB1 CGS2 M 2 CDB2 C GD1 RS Vin CGS1 M1 RD1 Rin2 VX CDB1 + CGS2 + (1− A v2 )CGD2 (c) (d) Figure 11.58 . Low-Frequency Behavior We begin with the low-frequency region and first consider the role of C1. From Eq. (11.55) and Fig. 11.28(c), we note that C1 contributes a low-frequency cut-off at !L1 = gm1RS1 + RS1C1 1 = 2  42:4 MHz: (11.169) (11.170) ARisne2c.oTnhdislorwes-ifsrteaqnuceenccayncbuet-ocafflcisulcaotendtriwbuitthedthbeyaCid2oafnMd tihlleeri’nsptuhteroerseimsta: nce of the second stage, Rin2 = 1 RF , Av2 ; (11.171) w,hgemr2eRADv22 denotes the voltage gain from = ,6:67,19, obtaining Rin2 X = to the output. Since 1:30 k . Using an RF RD2, we have Av2  analysis similar to that in the previous example, the reader can show that !L2 = RD1 1 + Rin2C2 = 2  6:92 MHz: (11.172) (11.173) 19With this estimate of the gain, place this resistance in parallel with wReLc2a,naenxdpwrersistethAe vM2 il=lergemff2ectRoLf 2RjjF8:7atth=e o,u5tp:9ut8a. sBRutFw=e1co,ntAin,vu2e1with8o:u7t k, this iteration for simplicity. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 587 (1) Sec. 11.9 Additional Examples 587 Since !L1 remains well above !L2, the cut-off is dominated by the former. Midband Behavior In the next step, we compute the midband gain. At midband frequencies, C1 the and C2 circuit act as a short to be reduced circuit to that and the transistor capacitances play a negligible role, allowing in Fig. 11.58(b). We note that vout=vin = vX =vinvout=vX and recognize that the drain of M1 sees two resistances to ac ground: RD1 and Rin2. That is, vX vin = ,gm1RD1jjRin2 = ,3:77: (11.174) (11.175) , The voltage gain from node X to the output is approximately equal to RD2.20 The overall midband gain is therefore roughly equal to 25.1. gm2RD2 because RF High-Frequency Behavior To study the response of the amplifier at high frequencies, we itFneirsgme.r1itn1tah.l5es8ot(rcfa)nM, swi1shteaornredctahMpea2ocviateraernacalletstar,acnnogstrfioenrugnfudthn.acWttiCoenSthBisu1sgaiavnredrnivCbeSyaBVt 2othupetl=asVyiminnpo=lirfioelVedXbto=epVcoainulosgeVytohsuehto=swVouXnrci.ne How do we compute VX =Vin in the presence of the loading of the second stage? The two capacitances CDB1 and CGS2 are in parallel, but how about the effect of RF and CGD2? We apply Miller’s approximation to both components so as to convert them to grounded elements. TmhueltiMpliilcleartioenffeocftCoGf DR2Fiswgaivsecnalbcyula1te,d above to be equivalent to Av2CGD2 = 614 fF. The Rin2 = 1:3 k . The first stage can now be Miller drawn as illustrated in Fig. 11.58(d), lending itself to the CS analysis performed in Section 11.4. The zero is given by gm1=CGD1 = 2  13:3 GHz. The two poles can be calculated from Eqs. (11.70), (11.71), and (11.72): j!p1j = 2  308 MHz j!p2j = 2  2:15 GHz: (11.176) (11.177) is eTxhperessesceodnadssta1g,e cAon,v2t1ribCuGteDs2a pole at its output  1:15CGD2 = n9o2dfeF..TAhdedMiniglleCr DefBfe2cttoofthCisGvDa2luaet the output yields the output pole as j!p3j = 1 RL21:15CGD2 + CDB2 = 2  1:21 GHz: (11.178) (11.179)  We observe that !p1 dominates the high-frequency response. Figure 11.59 plots the overall re- sponse. The midband gain is about 26 dB 20, around 20% lower than the calculated result. ,  ,  This is primarily due to the use of Miller approximation for RF . Also, the “useful” bandwidth can be defined from the lower 3-dB cut-off ( 40 MHz) to the upper 3-dB cut-off ( 300 MHz) and is almost one decade wide. The gain falls to unity at about 2.3 GHz. 20If not, then the circuit must be solved using a complete small-signal equivalent. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 588 (1) 588 30 20 10 0 −10 −20 −30 106 Figure 11.59 Magnitude of Frequency Response (dB) Chap. 11 Frequency Response 107 108 109 Frequency (Hz) 1010 11.10 Chapter Summary The speed of circuits is limited by various capacitances that the transistors and other components contribute to each node. The speed can be studied in the time domain (e.g., by applying a step) or in the frequency domain (e.g., by applying a sinusoid). The frequency response of a circuit corresponds to the latter test. As the frequency of operation increases, capacitances exhibit a lower impedance, reducing the gain. The gain thus rolls off at high signal frequencies. To obtain the frequency response, we must derive the transfer function of the circuit. The magnitude of the transfer function indicates how the gain varies with frequency. Bode’s rules approximate the frequency response if the poles and zeros are known. A capacitance tied between the input and output of an inverting amplifier appears at the input with a factor equal to one minus the gain of the amplifier. This is called Miller effect. In many circuits, it is possible to associate a pole with each node, i.e., calculate the pole frequency as the inverse of the product of the capacitance and resistance seen between the node and ac ground. Miller’s theorem allows a floating impedance to be decomposed into to grounded impedances. Owing to coupling or degeneration capacitors, the frequeny response may also exhibit rolloff as the frequency falls to very low values. Bipolar and MOS transistors contain capacitances between their terminals and from some terminals to ac ground. When solving a circuit, these capacitances must be identified and the resulting circuit simplified. The CE and CS stages exhibit a second-order transfer function and hence two poles. Miller’s approximation indicates an input pole that embodies Miller multiplication of the basecollector or gate-drain capacitance. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 589 (1) Sec. 11.10 Chapter Summary 589 If the two poles of a circuit are far from each other, the “dominant-pole approximation” can be made to find a simple expression for each pole frequency. The CB and CG stages do not suffer from Miller effect and achieve a higher speed than CE/CS stages, but their lower input impedance limits their applicability. Emitter and source followers provide a wide bandwidth. Their output impedance, however, can be inductive, causing instability in some cases. To benefit from the higher input impedance of CE/CS stages but reduce the Miller effect, a cascode stage can be used. The differential frequency response of differential pairs is similar to that of CE/CS stages. Problems 1. In the amplifier of Fig. 11.60, RD = 1 k and CL = 1 pF. Neglecting channel-length VDD RD Vin M1 Vout CL Figure 11.60 modulation and other capacitances, determine the frequency at which the gain falls by 10 ( 1 dB). , 2. In the circuit of Fig. 11.61, we wish to achieve a 3-dB bandwidth of 1 GHz with a load VCC R1 Vin Q1 Vout CL Figure 11.61 capacitance of 2 pF. What is the maximum (low-frequency) gain that can be achieved with a power dissipation of 2 mW? Assume VCC = 2:5 V and neglect the Early effect and other capacitances. , 1 3. Determine the 3-dB bandwidth of the circuits shown in Fig. 11.62. Assume VA = but  0. Neglect other capacitances. 4. Construct the Bode plot of jVout=Vinj for the stages depicted in Fig. 11.62. 5. A circuit contains jVout=Vinj. two coincident (i.e., equal) poles at !p1. Construct the Bode plot of 6. An amplifier exhibits two poles at 100 MHz and 10 GHz and a zero at 1 GHz. Construct the Bode plot of jVout=Vinj. j j 7. An ideal integrator contains a pole at the origin, i.e., !p = 0. Construct the Bode plot of Vout=Vin . What is the gain of the circuit at arbitrarily low frequencies? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 590 (1) 590 Chap. 11 Frequency Response VCC Q2 Vout VCC Q2 RB Vb Vout VDD M2 Vin Vout VDD M1 Vout Vin Q1 CL Vin Q1 CL Vin M1 CL M2 CL (a) (b) Figure 11.62 (c) (d) j j 8. AVnouitd=eVailndi.fWferheanttiiasttohrepgraoivnidoefsthaezceirrocuaitttahteaorbriigtrianr,iliy.e.h,i!ghz = 0. Construct frequencies? the Bode plot of 9. Figure 11.63 illustrates a cascade of two identical CS stages. Neglecting channel-length mod- VDD RD RD X Vin M1 CL M2 Vout CL Figure 11.63 ulation and other capacitances, construct the Bode plot of jVout=Vinj. Note that Vout=Vin = VX =VinVout =VX . 10. In Problem 9, derive the transfer function of the circuit, substitute s = j!, and obtain an expression for jVout=Vinj. Determine the ,3-dB bandwidth of the circuit. 11. Consider the circuit shown in Fig. 11.64. Derive the transfer function assuming  0 but VDD Vout Vin M1 CL Figure 11.64 ! neglecting other capacitances. Explain why the circuit operates as an ideal integrator if  0. 12. Due to a of M1 in manufacturing error, a Fig. 11.65. Assuming pa=ras0itaicndrensiesgtalenccteinRg pothhaesr appeared in series with the source capacitances, determine the input and output poles of the circuit. 13. Repeat Problem 12 for the circuit shown in Fig. 11.66. 14. Repeat Problem 12 for the CS stage depicted in Fig. 11.67. 15. Derive a relationship for the figure of merit defined by Eq. (11.8) for a CS stage. Consider only the load capacitance. 16. Apply Miller’s theorem to resistor RF in Fig. 11.68 and estimate the voltage gain of the BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 591 (1) Sec. 11.10 Chapter Summary 591 RS Vin VDD RD Vb RP C in Vout CL Figure 11.65 Figure 11.66 RS Vin VDD RD RP Vb C in Vout CL RS Vin VDD RD Vout M1 CL Cin RP Figure 11.67 circuit. Assume ,gmRC . VA = 1 and RF is large enough to allow the approximation vout=vX = 17. Repeat Problem 16 for the source follower enough to allow the approximation vout=vX in = Fig. 11.69. RL=RL + gAm,s1su.me  = 0 and RF is large 18. Consider the common-base stage illustrated in is drawn explicitly. Utilize Miller’s theorem to to allow the approximation vout=vX = gmRC. Fig. 11.70, where estimate the gain. AthsesuomutepurtOreissilsatragneceenoofuQgh1 19. Using Miller’s theorem, estimate the input capacitance of the circuit depicted in Fig. 11.71. Assume  ! 0 but neglect other capacitances. What happens if  0? 20. Repeat Problem 19 for the source follower shown in Fig. 11.72. 21. Using Miller’s theorem, explain how the common-base stage illustrated in Fig. 11.73 provides 1 a negative input capacitance. Assume VA = and neglect other capacitances. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 592 (1) 592 Figure 11.68 Chap. 11 VCC RC RF RB Vout Vin Q1 X Frequency Response Figure 11.69 RS X Vin VDD M1 Vout RF RL Figure 11.70 Figure 11.71 VCC RC rO Vin RB Vout Vb Q1 X VDD CF M1 C in 22. Use Miller’s theorem to estimate the input and output poles of the circuit shown in Fig. 11.74. Assume VA = 1 and neglect other capacitances. 23. Repeat Problem 22 for the circuit in Fig. 11.75. 24. For the bipolar circuits depicted in Fig. 11.76, identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends. 25. For the MOS circuits shown in Fig. 11.77, identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends. 26. In arriving at Eq. (11.49) for the fT of transistors, we neglected C and CGD. Repeat the derivation without this approximation. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 593 (1) Sec. 11.10 Chapter Summary 593 CF C in VDD M1 Figure 11.72 VCC RC Figure 11.73 C1 Vb Q1 C in Figure 11.74 RB Vin CF RC VCC Vout Q1 RB Vin RC Q1 CF VCC Q2 Vout Figure 11.75 27. IEs(taeq)cc.oWa(nn1dr1ibst.4ietn9ogs)hc,Crodowesrnsi=vttehhCeaanbtb,a+eisxfepCtrrhjeeeegs,simaoiosninsn,uotfmhoriertinynthgCcetabhfrTar=iteoCrgfsmjbeiinpiFjsoe.clianterddterpabenynsditsheteonrtesomifnitthtteeerrmbiinsatsoofctuthhreerecbnoatl,sleaencttdaokuresbiinaFgs current. (b) Sketch fT as a function of IC. 28. It can be shown that CGS  2=3W LCox for a MOSFET operating in saturation. Using Eq. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 594 (1) 594 Chap. 11 Frequency Response VCC Q2 Vout VCC Q2 RB Vout VCC I1 Vout VCC Vb1 Q1 Q3 Vb3 Vin Q1 CL Vin Q1 CL Vin Q2 (a) (b) Figure 11.76 VDD Vb M2 Vout Vin M1 (a) Figure 11.77 VDD Vin M2 Vout Vb M1 (b) (c) VDD RE Vin M2 Vout M1 Vb1 RS (c) (11.49), prove that 2fT = 3 2 n L2 VGS , VT H : (11.180) Note that fT increases with the overdrive voltage. 29. Having solved Problem 28 successfully, 2ID=VGS , VTH, arriving at a student attempts a different substitution for gm: 2fT = 3 2 2ID W LCox VGS 1 , VT H : (11.181) This result suggests that fT decreases as the overdrive voltage increases! Explain this apparent discrepancy between Eqs. (11.180) and (11.181). 30. Using Eq. (11.49) and the results of Problems 28 and 29, plot the fT of a MOSFET (a) as a function of W for a constant ID, (b) as a function of ID for a constant W . Assume L remains constant in both cases. , , 31. Using Eq. (11.49) and the results of Problems 28 and 29, plot the fT of a MOSFET (a) as a function Assume LofrVemGSainsVcToHnstfaonrtaincobnosthtancat sIeDs., (b) as a function of ID for a constant VGS VT H . , , 32. UAfussnsicnutgmioEenqLo.f(r1We1m.4afoi9nr)saacncodonntshstateannrtetisnVuGlbtSostohfcVPaTrsoeHbs.,le(mb)sa2s8aafnudnc2t9io,npoloftVthGeSfT of a MOSFET (a) as a VT H for a constant W . 33. In order to lower channel-length modulation in a MOSFET, we double the device length. (a) How should the device width be adjusted to maintain the same overdrive voltage and the same drain current? (b) How do these changes affect the fT of the transistor? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 595 (1) Sec. 11.10 Chapter Summary 595 34. We wish to halve the overdrive voltage of a transistor so as to provide a greater voltage head- room in a circuit. (b) W is constant DanedteIrmDiinsedtehcerecahsaendg.eAinsstuhme efTL if (a) ID is constant is constant. and W is increased, or 35. Using Miller’s theorem, determine the input and output poles of the CE and CS stages depicted in Fig. 11.29(a) while including the output impedance of the transistors. 36. The common-emitter stage of Fig. 11.78 employs a current-source load to achieve a high gain VCC RS Vin Vout Q1 Figure 11.78 1 (at low frequencies). Assuming VA and using Miller’s theorem, determine the input and output poles and hence the transfer function of the circuit. 37. Repeat Problem 36 for the stage shown in Fig. 11.79. Vb RS Vin VCC Q2 Vout Q1 Figure 11.79 38. Assuming  0 and using Miller’s theorem, determine the input and output poles of the stages depicted in Fig. 11.80. VDD M2 VDD M2 RS Vin VDD M2 RS Vin Vout M1 RS Vin Vout M1 Vout Vb M1 (a) (b) (c) Figure 11.80 39. In the CS stage of Fig. CGD = 10 fF, CDB = 1151.f2F9, (aan)d, RVGSS=,2V0T0H , RD = 1 k , ID1 = 1 mA, CGS = 50 fF, = 200 mV. Determine the poles of the circuit using (a) Miller’s approximation, and (b) the transfer function given by Eq. (11.70). Compare the results. 1 40. Consider the amplifier shown in Fig. 11.81, where VA = . Determine the poles of the cir- cuit using (a) Miller’s approximation, and (b) the transfer function expressed by Eq. (11.70). Compare the results. 41. Repeat Problem 40 but use the dominant-pole approximation. How do the results compare? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 596 (1) 596 Chap. 11 Frequency Response VCC Figure 11.81 RS Vin Vout Q1 42. The circuit depicted in Fig. 11.82 is called an “active inductor.” Neglecting other capacitances Z in R 1 M1 C1 Figure 11.82 and assuming  = 0, compute Zin. Use Bode’s rule to plot jZinj as a function of frequency and explain why it exhibits inductive behavior. 43. Determine the input and output impedances of the stage depicted in Fig. 11.83 without using Miller’s theorem. Assume VA = 1. VCC Figure 11.83 Q1 Z out Z in 44. Compute the transfer function of the circuit shown in Fig. 11.84 without using Miller’s theo- RS Vin VDD M2 Vout M1 Figure 11.84 rem. Assume  0. 45. Calculate the input impedance of the stage illustrated in Fig. 11.85 without using Miller’s theorem. Assume  = 0. 46. Determine the transfer function of the circuits shown in Fig. 11.86. Assume  = 0 for M1. 47. Consider the source follower shown in Fig. 11.87, where the current source is mistakenly BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 597 (1) Sec. 11.10 Chapter Summary 597 Figure 11.85 VDD M2 Vout Z in M1 VDD M2 Vout RSM 1 Vb Vin (a) Figure 11.86 VDD Vb M2 Vout RSM 1 Vb Vin (b) VDD RSM 1 Vb Vin (c) Vout M2 Figure 11.87 VDD M1 C in M2 6 replaced with a diode-connected device. Taking capacitance of the circuit. Assume  = 0. into account only CGS1, compute the input j j 1 48. Determine the output impedance of the emitter follower Sketch Zout as a function of frequency. Assume VA = depicted . in Fig. 11.88, including C. RB Vin VCC Q1 Figure 11.88 Z out 1 49. In the cascode bias current of oQf1F. iAg.ss1u1m.8i9n,gQV3A serves = as a constant current source, providing 75 of the and using Miller’s theorem, determine the poles of the circuit. Is Miller’s effect more or less significant here than in the standard cascode topology of Fig. 11.48(a)? BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 598 (1) 598 Figure 11.89 Vb2 Q3 Vb1 Vin RB Chap. 11 VCC RC Vout Q2 Frequency Response Q1 50. Due to manufacturing error, a parasitic resistor Rp has appeared in the cascode stage of Fig. 11.90. Assuming  = 0 and using Miller’s theorem, determine the poles of the circuit. VDD RD Vout Vb M2 RS Vin M1 RP Figure 11.90 51. In analogy with the circuit of Fig. 11.89, a student constructs the stage depicted in Fig. 11.91 but mistakenly uses an NMOS device for M3. Assuming V=DD0 and using Miller’s theorem, Vb2 M3 RD Vout Vb1 M2 Figure 11.91 Vin M1 RG compute the poles of the circuit. Design Problems 52. Using the results obtained in Problems 9 and 10, design the two-stage amplifier of Fig. 11.63 , for a total voltage gain of 20 and a 3-db bandwidth of 1 GHz. Assume each stage carries a bias current of 1 mA, CL = 50 fF, and nCox = 100 A=V2. 53. We wish to design the CE stage of Fig. 11.92 for an input pole at 500 MHz and an output pole VCC RC RB Vin Vout Q1 Figure 11.92 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 599 (1) Sec. 11.10 Chapter Summary 599 at 2 GHz. Assuming IC using Miller’s theorem, d=et1ermmAin,eCthe=va2lu0efsF,oCf R B= a5ndfFR, CCCsSuc=h 10 fF, and VA = 1, and that the (low-frequency) voltage gain is maximized. You may need to use iteration. 54. Repeat Problem 53 with the additional assumption that the circuit must drive a load capaci- tance of 20 fF. , 55. We wish to design the common-base stage of Fig. 11.93 for a 3-dB bandwidth of 10 GHz. VCC RC RS Vin Vout Vb Q1 Figure 11.93 Assume IC = 1 mA, VA = 1, RS = 50 , C = 20 fF, C = 5 fF, and CCS = 20 fF. Determine the maximum allowable value of RC and hence the maximum achievable gain. (Note that the input and output poles may affect the bandwidth.) 56. The emitter follower of Fig. 11.94 must be designed for an input capacitance of less than 50 VCC Vin Q1 Vout RL Figure 11.94 fF. If C = 10 fF, C = 100 fF, VA = 1, and IC = 1 mA, what is the minimum tolerable value of RL? 57. An NMOS source follower must drive a load resistance of 100 with a voltage gain of 0.8. If ID = 1 mA, minimum input nCox = 100 A=V2, Cox = 12 fF/m2, capacitance that can be achieved? Assume  and L = 0:18 m, what = 0, CGD  0, CSB  is 0, the and CGS = 2=3W LCox. 58. We wish to design the MOS cascode of Fig. 11.95 for an input pole of 5 GHz and an output VDD RD Vout Vb M2 RG Vin M1 Figure 11.95 pole Cox of = 10 12 fGFH/zm. 2A,ssunmCoexM=1 and 100 MA2=Var2e, identical, ID  = 0, L = C0 = 0:2 fF=m denotes the gate-drain capacitance per = 0:5 mA, CGS = 2=3W LCox, 0:18 m, and CGD = C0W , where unit width. Determine the maximum BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 600 (1) 600 Chap. 11 Frequency Response allowable values of RG, RD, and the voltage gain. Use Miller’s approximation for CGD1. Assume an overdrive voltage of 200 mV for each transistor. 59. Repeat Problem 58 if W2 = 4W1 so as to reduce the Miller multiplication of CGD1. SPICE Problems ItArna,nthspeinsftpoorl=lso,w5as0ins,ugVmpAer;opInbSpl;en=mpns3,=:u5se5Vt.hAe1lMs0o,O,1SS6PAdIeC,vEincmepnmod=oedl1se0ltsh0ge, iVevAfefn;encipntnoth=f ec5hAaVprgp, eeInSs;dtpoinxrpaAg=e. Fi8northbe1ip0bo,al1sa6er by a parameter called F = Cb=gm. Assume F tf = 20 ps. 60. In the two-stage amplifier shown in Fig. 11.96, W=L = 10 m=0:18 m for M1-M4. VDD= 1.8 V M2 M3 Vin M1 Vout M4 Figure 11.96 (a) Select the input dc level to obtain an output dc level of 0.9 V. , (b) Plot the frequency response and compute the low-frequency gain and the 3-dB band- width. (c) Repeat (a) and (b) for W = 20 m and compare the results. 61. The circuit of Fig. 11.97 must drive a load capacitance of 100 fF. 1 kΩ VCC = 2.5 V 1 kΩ 5 kΩ Vin Q1 Vout Q2 Figure 11.97 (a) Select the input dc level to obtain an output dc level of 1.2 V. , (b) Plot the frequency response and compute the low-frequency gain and the 3-dB band- width. 62. The self-biased stage depicted in Fig. 11.98 must drive a load capacitance of 50 fF with  a maximum gain-bandwidth product (= midband gain unity-gain bandwidth). Assuming R1 = 500 and L1 = 0:18 m, determine W1, RF , and RD. VDD= 1.8 V RD 100 pF R1 Vin RF Vout M1 CL Figure 11.98 63. Repeat Problem 62 for the circuit shown in Fig. 11.99. (Determine RF and RC.) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 601 (1) Sec. 11.10 Chapter Summary 601 Figure 11.99 100 pF R1 Vin VCC= 2.5 V RC Q1 Q 1 1 mA Vout CL RF 64. The two-stage amplifier shown in Fig. 11.100 must achieve maximum gain-bandwidth prod- udcettewrmhiilneedRrivFinagndCWL =. 50 fF. Assuming M1-M4 have a width of W and a length of 0.18 m, VDD= 1.8 V 1 kΩ RF M2 Vin 1 pF M1 M4 Vout M3 Figure 11.100 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 602 (1) 12 Feedback Feedback is an integral part of our lives. Try touching your fingertips with your eyes closed; you may not succeed the first time because you have broken a feedback loop that ordinarily “regulates” your motions. The regulatory role of feedback manifests itself in biological, mechanical, and electronic systems, allowing precise realization of “functions.” For example, an amplifier targeting a precise gain of 2.00 is designed much more easily with feedback than without. This chapter deals with the fundamentals of (negative) feedback and its application to electronic circuits. The outline is shown below. General Considerations Elements of Feedback Systems Loop Gain Properties of Negative Feedback Amplifiers and Sense/Return Methods Types of Amplifiers Amplifier Models Sense/Return Methods Polarity of Feedback Analysis of Feedback Circuits Four Types of Feedback Effect of Finite I/O Impedances Stability and Compensation Loop Instability Phase Margin Frequency Compensation 12.1 General Considerations As soon as he reaches the age of 18, John eagerly obtains his driver’s license, buys a used car, and begins to drive. Upon his parents’ stern advice, John continues to observe the speed limit while noting that every other car on the highway drives faster. He then reasons that the speed limit is more of a “recommendation” and exceeding it by a small amount would not be harmful. Over the ensuing months, John gradually raises his speed so as to catch up with the rest of the drivers on the road, only to see flashing lights in his rear view mirror one day. He pulls over to the shoulder of the road, listens to the sermon given by the police officer, receives a speeding ticket, and, dreading his parents’ reaction, drives home—now strictly adhering to the speed limit. John’s story exemplifies the “regulatory” or “corrective” role of negative feedback. Without the police officer’s involvement, John would probably continue to drive increasingly faster, eventually becoming a menace on the road. Shown in Fig. 12.1, a negative feedback system consists of four essential components. (1) The “feedforward” system:1 the main system, probably “wild” and poorly-controlled. John, the gas 1Also called the “forward” system. 602 BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 603 (1) Sec. 12.1 General Considerations 603 Feedforward System X Comparison Mechanism A1 XF K Y Sense Mechanism Output Port of Feedback Network Feedback Network Input Port of Feedback Network Figure 12.1 General feedback system. pedal, and the car form the feedforward system, where the input is the amount of pressure that John applies to the gas pedal and the output is the speed of the car. (2) Output sense mechanism: a means of measuring the output. The police officer’s radar serves this purpose here. (3) Feedback network: a network that generates a “feedback signal,” XF , from the sensed output. The police officer acts as the feedback network by reading the radar display, walking to John’s car, and giving him a speeding ticket. The quantity K = XF =Y is called the “feedback factor.” (4) Comparison or return mechanism: a means of subtracting the feedback signal from the input to , obtain the “error,” E = X XF . John makes this comparison himself, applying less pressure to the gas pedal—at least for a while. The feedback in Fig. 12.1 is called “negative” because XF is subtracted from X. Positive feedback, too, finds application in circuits such as oscillators and digital latches. If K = 0, i.e., 6 no signal is fed back, then we obtain the “open-loop” system. If K = 0, we say the system operates in the “closed-loop” mode. As seen throughout this chapter, analysis of a feedback system requires expressing the closed-loop parameters in terms of the open-loop parameters. Note that the input port of the feedback network refers to that sensing the output of the forward system. As our first step towards understanding the feedback system of Fig. 12.1, let us determine the closed-loop transfer function Y =X equal to X , KY , which serves as . Since XF the input of = KY , the the forward error produced system: by the subtractor is X , KY A1 = Y: (12.1) That is, Y X = 1 A1 +K A1 : (12.2) This equation plays a central role in our treatment of feedback, revealing that negative feedback rKedAu1cesisthcealgleadintfhreom“cAlo1se(df-olrotohpe open-loop system) gain.” Why do we to A1=1 + deliberately KA1. The quantity A1=1 + lower the gain of the circuit? As explained in Section 12.2, the benefits accruing from negative feedback very well justify this reduction of the gain. Example 12.1 Analyze the noninverting amplifier of Fig. 12.2 from a feedback point of view. Solution The op amp A1 performs two functions: subtraction of X and XF and amplification. The network BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 604 (1) 604 Chap. 12 Feedback X A1 XF Y R1 R2 Figure 12.2 Rfa1ctoanr dofRK2 also performs two = R2=R1 + R2. functions: sensing Thus, (12.2) gives the output voltage and providing a feedback Y X = 1 + A1 R2 R1 + R2 A1 ; (12.3) which is identical to the result obtained in Chapter 8. Exercise 1 Perform the above analysis if R2 = . It is instructive to compute the error, E, produced by the subtractor. Since E = X , XF and XF = KA1E, E = 1 X + KA1 ; (12.4) suggesting that the difference between the feedback signal and the input diminishes as KA1 increases. In other words, the feedback signal becomes a close “replica” of the input (Fig. 12.3). This observation leads to a great deal of insight into the operation of feedback systems. X A1 Good XF R1 Replica R2 Figure 12.3 Feedback signal as a good replica of the input. Example 12.2 Explain why in the circuit of Fig. 12.2, Y=X approaches 1 + R1=R2 as R2=R1 + R2 A1 becomes much greater than unity. Solution If KA1 = R2=R1 + R2 A1 is large, XF becomes almost identical to X, i.e., XF  X. The BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 605 (1) Sec. 12.1 General Considerations voltage divider therefore requires that Y R2 R1 + R2  X and hence Y X  1 + R1 R2 : Of course, (12.3) yields the same result if R2=R1 + R2 A1 1. Exercise Repeat the above example if R2 = 1. 605 (12.5) (12.6) 12.1.1 Loop Gain In Fig. 12.1, the quantity KA1, which is equal to product of the gain of the forward system and the feedback factor, determines many properties of the overall system. Called the “loop gain,” KA1 has an interesting interpretation. Let us set the input X to zero and “break” the loop at an arbitrary point, e.g., as depicted in Fig. 12.4(a). The resulting topology can be viewed as a system A1 N K M A1 VN K Vtest (a) (b) Figure 12.4 Computation of the loop gain by (a) breaking the loop and (b) applying a test signal. with an input M and an output N . Now, as shown in Fig. 12.4(b), let us apply a test signal at M and follow it through the feedback network, the subtractor, and the forward system to obtain the signal at N .2 The input of A1 is equal to ,KVtest, yielding VN = ,KVtestA1 (12.7) and hence K A1 = , VN Vtest : (12.8) , In other the term the loop words, if a signal “loop gain.” It is gain, KA1. “goes around important not the loop,” it experiences a gain equal to to confuse the closed-loop gain, A1=1 + KKAA11;h, ewnicthe 2We use voltage quantities in this example, but other quantities work as well. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 606 (1) 606 Chap. 12 Feedback Example 12.3 Compute the loop gain of the feedback system of Fig. 12.1 by breaking the loop at the input of A1. Solution Illustrated in the feedback Fig. 12.5 is the system with the test signal network is equal to KA1Vtest, yielding applied to the input of A1 . The output of VN = ,KA1Vtest (12.9) and hence the same result as in (12.8). N M A1 Y VN Vtest K Figure 12.5 Exercise Compute the loop gain by breaking the loop at the input of the subtractor. The reader may wonder if an ambiguity exists with respect to the direction of the signal flow in the loop gain test. For example, can we modify the topology of Fig. 12.4(b) as shown in Fig. 12.6? This would mean applying Vtest to the output of A1 and expecting to observe a signal at its X A1 Vtest K VN Figure 12.6 Incorrect method of applying test signal. input and eventually at N . While possibly yielding a finite value, such a test does not represent the actual behavior of the circuit. In the feedback system, the signal flows from the input of A1 to its output and from the input of the feedback network to its output. 12.2 Properties of Negative Feedback 12.2.1 Gain Desensitization Suppose provides Aa v1oinltaFgieg.g1a2in.1oifsgamn RamDpwlifiheilrewbhoothsegmgaianndisRpoDorvlayrycownittrholplerodc. eFsosraenxdamtepmlep,earaCtuSres;tatghee BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 607 (1) Sec. 12.2 Properties of Negative Feedback 607  gain thus may vary by as much as 20. Also, suppose we require a voltage gain of 4.00.3 How can we achieve such precision? Equation (12.2) points to a potential solution: if KA1 1, we have Y X  1 K ; (12.10) taKaotqtaauciaasnnnmetdbiat.leylTdiehneredrfioecnrpie,redfcnoupdricreteinonctfgiosFeXfilAgyF.,1t1.thoF2e.rbn2oemAenx1eaeanmirmolpytphliaeeficqretupssaeYtlrhst=iposXeXccotnineavcgneel,dipEghtqiebv.nle(yc1rey2a.nYw4d)enialnel.hadIriifglcyhaAteep1qsrRuetah2cl=iasttioRoKnX1Ai+=n1KtRh.e2T1ghalueisna,d1iissf, then Y X  1 K  1 + R1 R2 : (12.11) (12.12) Why is R1=R2 more precisely defined than gmRD is? If R1 and R2 are made of the same ma- terial and constructed identically, then the variation of their value with process and temperature Feadanoigcde.hsi1mun2nop.7itlt,eaitmfnhfeeeRcni1tdt teRahane1diisrahtsroeatntehicnoees.sutAehrreesietathsonatcateolxRmva1amblaiupnneladeot,iRfofoRn2r“1oat,frsactthclioklrles”eeyedi“ae-uclldohnioinotp”gthgraeaergis;niasiifotnoRfro4s2f.e0i1nq0+cu,rawe1lae:ts2oecRshR1bo2=yo.s21Iel0:l2RuRs1,t2rs=aot=ed3doR4ein.2s R1 R2 Figure 12.7 Construction of resistors for good matching. Example 12.4 The circuit of Fig. 12.2 is designed for a nominal gain of 4. (a) Determine the actual gain if A1 = 1000. (b) Determine the percentage change in the gain if A1 drops to 500. Solution For a nominal gain of 4, Eq. (12.12) implies that R1=R2 = 3. (a) The actual gain is given by Y X = A1 1 + KA1 = 3:984: (12.13) (12.14) Note that the loop gain KA1 = 1000=4 = 250. (b)If A1 falls to 500, then Y X = 3:968: (12.15) 3Some analog-to-digital converters (ADCs) require very precise voltage gains. For example, a 10-bit ADC may call for a gain of 2.000. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 608 (1) 608 Chap. 12 Feedback Thus, the closed-loop gain changes by only 3:984=3:968=3:984 = 0:4 if A1 drops by factor of 2. Exercise Determine the percentage change in the gain if A1 falls to 200. The above example reveals that the closed-loop gain of a feedback circuit becomes relatively independent of the open-loop gain so long as the loop gain, KA1, remains sufficiently higher than unity. This property of negative feedback is called “gain desensitization.” We now see why we are willing to accept a reduction in the gain by a factor of 1 + KA1. We begin with an amplifier having a high, but poorly-controlled gain and apply negative feedback around it so as to obtain a better-defined, but inevitably lower gain. This concept was also extensively employed in the op amp circuits described in Chapter 8. The gain desensitization property of negative feedback means that any factor that influences the open-loop gain has less effect on the closed-loop gain. Thus far, we have blamed only process and temperature variations, but many other phenomena change the gain as well. As the signal frequency rises, A1 may fall, but A1=1 + KA1 remains relatively constant. We therefore expect that negative feedback increases the bandwidth (at the cost of gain). If the load resistance changes, A1 may change; e.g., the gain of a CS stage depends on the load resistance. Negative feedback, on the other hand, makes the gain less sensitive to load variations. The signal amplitude affects A1 because the forward amplifier suffers from nonlinearity. For example, the large-signal analysis of differential pairs in Chapter 10 reveals that the smallsignal gain falls at large input amplitudes. With negative feedback, however, the variation of the open-loop gain due to nonlinearity manifests itself to a lesser extent in the closedloop characteristics. That is, negative feedback improves the linearity. We now study these properties in greater detail. 12.2.2 Bandwidth Extension Let us consider a one-pole open-loop amplifier with a transfer function A1s = 1 +A0!s0 : (12.16) , Here, A0 denotes the low-frequency gain and !0 negative feedback lowers the low-frequency gain the by a 3-dB factor bandwidth. Noting from of 1 + KA1, we wish to (12.2) that determine the resulting bandwidth improvement. The closed-loop transfer function is obtained by substitut- ing (12.16) for A1 in (12.2): Y X = 1 +1K+A10!+sA00!s0 : (12.17) BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 609 (1) Sec. 12.2 Properties of Negative Feedback 609 Multiplying the numerator and the denominator by 1 + s=!0 gives Y X s = 1 + A0 KA0 + s !0 A0 = 1 + 1 + KsA0 1 + KA0!0 : In analogy with (12.16), we conclude that the closed-loop system now exhibits: Closed , Loop Gain = 1 A0 + KA0 Closed , Loop Bandwidth = 1 + KA0!0: (12.18) (12.19) (12.20) (12.21) In other words, the gain and bandwidth are scaled by the same factor but in opposite directions, displaying a constant product. Example 12.5 Plot the closed-loop frequency response given by (12.19) for K = 0, 0.1, and 0.5. Assume A0 = 200. Solution wFfaoecrthoKar.v=Se i1m0+,iltahKrelyAf,e0feod=rbKa2c1k,=nvoa0tni:in5sg,h1eths+aatnKtdheAYg=0aX=inrd1eed0cu1rc,eeyassieetolsdaAinn1gdsathpearbsoapgnoivdrewtinoidnbtayhl (ir1ne2cd.ru1ec6ats)i.oeFsnobirnyKtghae=insa0am:n1de, increase in bandwidth. The results are plotted in Fig. 12.8. Figure 12.8 A0 K= 0 K = 0.1 K = 0.5 ω Exercise Repeat the above example for K = 1. Example 12.6 Prove that the unity-gain bandwidth of the above system remains independent of K if 1 + KA0 1 and K2 1. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 610 (1) 610 Chap. 12 Feedback Solution The magnitude of (12.19) is equal to A0 Y X j! = s 1 + KA0 : 1 + 1 + !2 KA02!02 (12.22) Equating this result to unity and squaring both sides, we write 1 A0 +K A0 2 = 1 + 1 + !u2 KA02 !02 ; where !u denotes the unity-gain bandwidth. It follows that q !u = !0qA20 , 1 + KA02  !0 A20 , K A2 2 0  !0A0; (12.23) (12.24) (12.25) (12.26) which is equal to the gain-bandwidth product of the open-loop system. Figure 12.9 depicts the results. A0 Figure 12.9 0 dB ω0 A0ω0 ω Exercise If A0 = 1000; !0 = 2  10 MHz, and K = 0:5, calculate the unity-gain bandwidth from Eqs. (12.24)and (12.26) and compare the results. 12.2.3 Modification of I/O Impedances As mentioned above, negative feedback makes the closed-loop gain less sensitive to the load resistance. This effect fundamentally arises from the modification of the output impedance as a result of feedback. Feedback modifies the input impedance as well. We will formulate these effects carefully in the following sections, but it is instructive to study an example at this point. Example 12.7 Figure 12.10 depicts a transistor-level realization of the feedback circuit shown in Fig. 12.2. BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 611 (1) Sec. 12.2 Properties of Negative Feedback 611 Assume  = 0 and R1 + R2 RD for simplicity. (a) Identify the four components of the feedback system. (b) Determine the open-loop and closed-loop voltage gain. (c) Determine the open-loop and closed-loop I/O impedances. VDD RD Vout R1 M1 Vin R2 Figure 12.10 Solution (a) In analogy with Fig. 12.10, we surmise that the forward system (the main amplifier) con- smtriasetccsthooar.fnTiMsrma1nasaninsddtothrReMDfe,1eiid.etbs.e,alcafkocnopemetrwmatoeorsnk-,agrseattthueersntsiaungbget.araRscietgosnrisabtloeercqsauuRasl1etotahnVedosuRmtR2al2sl=-esriRvgen1aa+lsdRbroa2itnhtocthutehrreseesnunt sbies- proportional to the difference between the gate and s