首页资源分类嵌入式系统 > smart210 核心板原理图

smart210 核心板原理图

已有 445499个资源

下载专区

上传者其他资源

    文档信息举报收藏

    标    签:smart210核心板原理图

    分    享:

    文档简介

    smart210 核心板原理图

    文档预览

    5 4 Revision History D Revision 1.0 Date 2011-12-9 初初初初 Comments C B 3 2 1 Index D 01:Revision History and Index 1 02:Function Block Diagram 2 03:S5PV210 (SYS)/Boot Option 3 04:S5PV210(Memory) 4 05:S5PV210 (Media) 5 06:S5PV210 (Power) 6 07:NAND/NOR Flash 08:Memory(DDR2) 7 C 8 09:Reset/JTAG/SD/Clock 9 10: LCD IF 10 11:system power 11 12:board connector 12 13:ID Mark/Fixed Hold 13 B A A Title Size A3 Date: Tiny210 Document Number Friday, May 24, 2013 Sheet Rev 0.1 1 of 11 5 D 4 3 2 NAND Flash: 128M/256M/512M/1GB SLC or 2GB/4GB/8GB MLC Memory 4片DDR2,32bit,512MB 1 D C 连连连: C Reset JTAG 测测测 S5PV210 - 30x2 2.0mm双双双x2 - 15x2 2.0mm双双双x1 B B Power A A Title Size A3 Date: Tiny210 Document Number Wednesday, September 25, 2013 Sheet Rev 2 of 11 5 [11] XuRXD0 [11] XuTXD0 XuCTSn0 XuRTSn0 D [11] XuRXD1 [11] XuTXD1 [11] XuCTSn1 [11] XuRTSn1 [11] XuRXD2/UART_AUDIO_RXD [11] XuTXD2/UART_AUDIO_TXD [11] XuRXD3/CTSn2/UART_AUDIO_CTSn [11] XuTXD3/RTSn2/UART_AUDIO_RTSn XspiCLK0 XspiCS0 XspiMISO0 XspiMOSI0 [11] XspiCLK1 [11] XspiCS1 [11] XspiMISO1 [11] XspiMOSI1 DGND R89 44.2K,1% [11] XuhDP [11] XuhDM XuhPWREN XuhOVERCUR C DGND [11] XuoDP [11] XuoDM R88 44.2K,1% [11] XuoID [11] XuoVBUS [11] XuoDRVVBUS [11] Audio_Xi2sSCLK0 [11] Audio_Xi2sCDCLK0 [11] Audio_Xi2sLRCK0 [11] Audio_Xi2sSDI0 [11] Audio_Xi2sSDO0_0 Xi2sCLK1/PCM_SCLK1/AC97_BITCLK Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC Xi2sSDI1/PCM_SIN1/AC97_SDI Xi2sSDO1/PCM_SOUT1/AC97_SDO XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 XpcmFSYNC0/LCD_FRM/Xi2sLRCK2 XpcmSIN0/Xi2sSDI2 XpcmSOUT0/Xi2sSDO2 [11] XmmcCLK0 [11] XmmcCMD0 [11] Xmmc0CDn [11] Xmmc0DATA0 [11] Xmmc0DATA1 B [11] Xmmc0DATA2 [11] Xmmc0DATA3 XmmcCLK1 XmmcCMD1 XmmcCDn1 Xmmc1DATA0 Xmmc1DATA1 Xmmc1DATA2 Xmmc1DATA3 [11] Xmmc2CLK/SPI_CLK2 [11] Xmmc2CMD/SPI_CSn2 [11] Xmmc2CDn/SPI_MISO2 [11] Xmmc2DATA0/SPI_MOSI2 [11] Xmmc2DATA1 [11] Xmmc2DATA2 [11] Xmmc2DATA3 Xmmc3CLK Xmmc3CMD Xmmc3CDn Xmmc3DATA0/Xmmc2DATA4 Xmmc3DATA1/Xmmc2DATA5 Xmmc3DATA2/Xmmc2DATA6 Xmmc3DATA3/Xmmc2DATA7 A 4 U1A C8 D8 D9 A7 G10 F10 B8 E10 AC20 AC14 AC13 AB13 B7 E9 J9 J11 G12 B11 G13 A11 AE19 AD19 AC17 AD23 AC22 AD21 AE21 AE18 AD18 AC18 AC19 AD2 AC4 AE3 AE2 AD3 AC3 AA3 AD1 AB3 AC2 AA5 AB4 AA2 AA1 AB1 AB2 AC1 B5 E6 F7 C5 A5 D6 C6 B6 F8 C7 D7 E7 A6 F9 Y6 W6 AA4 Y4 Y5 Y3 W4 A9 D10 E11 B10 C10 D11 A10 XuRXD0/GPA0_0 XuTXD0/GPA0_1 XuCTSn0/GPA0_2 XuRTSn0/GPA0_3 UART/IrDA XuRXD1/GPA0_4 XuTXD1/GPA0_5 XuCTSn1/GPA0_6 XuRTSn1/GPA0_7 XuRXD2/UART_AUDIO_RXD/GPA1_0 XuTXD2/UART_AUDIO_TXD/GPA1_1 XuRXD3/CTSn2/UART_AUDIO_CTSn/GPA1_2 XuTXD3/RTSn2/UART_AUDIO_RTSn/GPA1_3 XspiCLK0/GPB0 XspiCSn0/GPB1 XspiMISO0/GPB2 XspiMOSI0/GPB3 XspiCLK1/GPB4 XspiCSn1/GPB5 XspiMISO1/GPB6 XspiMOSI1/GPB7 HS-SPI XuhDP XuhDM XuhREXT XuhPWREN XuhOVERCUR USB HOST2.0 XuoDP XuoDM XuoREXT XuoID XuoVBUS XuoDRVVBUS USB OTG 2.0 Xi2sSCLK0/PCM_SCLK2 Xi2sCDCLK0/PCM_EXTCLK2 Xi2sLRCK0/PCM_FSYNC2 Xi2sSDI0/PCM_SIN2 Xi2sSDO0_0/PCM_SOUT2 Xi2sSDO0_1 I2S/PCM/AC97 Xi2sSDO0_2 Xi2sSCLK1/PCM_SCLK1/AC97BITCLK/GPC0_0 Xi2sCDCLK1/PCM_EXTCLK1/AC97RESETn/GPC0_1 Xi2sLRCK1/PCM_FSYNC1/AC97SYNC/GPC0_2 Xi2sSDI1/PCM_SIN1/AC97SDI/GPC0_3 Xi2sSDO1/PCM_SOUT1/AC97SDO/GPC0_4 XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2/GPC1_0 XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2/GPC1_1 XpcmFSYNC0/LCD_FRM/Xi2sLRCK2/GPC1_2 XpcmSIN0/Xi2sSDI2/GPC1_3 XpcmSOUT0/Xi2sSDO2/GPC1_4 XmmcCLK0/GPG0_0 XmmcCMD0/GPG0_1 Xmmc0CDn/GPG0_2 Xmmc0DATA0/GPG0_3 Xmmc0DATA1/GPG0_4 Xmmc0DATA2/GPG0_5 Xmmc0DATA3/GPG0_6 HS-MMC Xmmc1CLK/GPG1_0 Xmmc1CMD/GPG1_1 Xmmc1CDn/GPG1_2 Xmmc1DATA0/Xmmc0DATA4/GPG1_3 Xmmc1DATA1/Xmmc0DATA5/GPG1_4 Xmmc1DATA2/Xmmc0DATA6/GPG1_5 Xmmc1DATA3/Xmmc0DATA7/GPG1_6 Xmmc2CLK/SPI_CLK2/GPG2_0 Xmmc2CMD/SPI_CSn2/GPG2_1 Xmmc2CDn/SPI_MISO2/GPG2_2 Xmmc2DATA0/SPI_MOSI2/GPG2_3 Xmmc2DATA1/GPG2_4 Xmmc2DATA2/GPG2_5 Xmmc2DATA3/GPG2_6 Xmmc3CLK/GPG3_0 Xmmc3CMD/GPG3_1 Xmmc3CDn Xmmc3DATA0/Xmmc2DATA4/GPG3_3 Xmmc3DATA1/Xmmc2DATA5/GPG3_4 Xmmc3DATA2/Xmmc2DATA6/GPG3_5 Xmmc3DATA3/Xmmc2DATA7/GPG3_6 S5PV210 3 2 1 BootingMode Option VDD_SYS_3.3V SYSTEM [JTAG] XjTRSTn XjTMS XjTCK XjTDI XjTDO XjDBGSEL [SYSTEM OPTION] XOM0 XOM1 XOM2 XOM3 XOM4 XOM5 [CLOCK] XXTI XXTO XusbXTI XusbXTO XCLKOUT XhdmiXTI XhdmiXTO [RESET] XnWRESET XnRESET XnRSTOUT XPWRRGTON XrtcXTI XrtcXTO XRTCCLKO XefFSOURCE XpwmTOUT0/GPD0_0 XpwmTOUT1/GPD0_1 XpwmTOUT2/GPD0_2 XpwmTOUT3/PWM_MIE/GPD20_3 P5 R5 U4 T5 W3 P3 T23 T22 V23 U21 V25 V24 U24 U25 AD20 AE20 AE24 Y2 Y1 T21 U23 T20 U22 T24 T25 R22 AD4 E8 B9 A8 F12 PWM Timer EINT KEYPAD I2C XEINT0/GPH0_0 XEINT1/GPH0_1 XEINT2/GPH0_2 XEINT3/GPH0_3 XEINT4/GPH0_4 XEINT5/GPH0_5 XEINT6/GPH0_6 XEINT7/GPH0_7 XEINT8/GPH1_0 XEINT9/GPH1_1 XEINT10/GPH1_2 XEINT11/GPH1_3 XEINT12/HDMI_CEC/GPH1_4 XEINT13/HDMI_HPD/GPH1_5 XEINT14/GPH1_6 XEINT15/GPH1_7 XEINT16/KP_COL0/GPH2_0 XEINT17/KP_COL1/GPH2_1 XEINT18/KP_COL2/GPH2_2 XEINT19/KP_COL3/GPH2_3 XEINT20/KP_COL4/GPH2_4 XEINT21/KP_COL5/GPH2_5 XEINT22/KP_COL6/GPH2_6 XEINT23/KP_COL7/GPH2_7 XEINT24/KP_ROW0/GPH3_0 XEINT25/KP_ROW1/GPH3_1 XEINT26/KP_ROW2/GPH3_2 XEINT27/KP_ROW3/GPH3_3 XEINT28/KP_ROW4/GPH3_4 XEINT29/KP_ROW5/GPH3_5 XEINT30/KP_ROW6/GPH3_6 XEINT31/KP_ROW7/GPH3_7 Xi2cSDA0/GPD1_0 Xi2cSCL0/GPD1_1 Xi2cSDA1/GPD1_2 Xi2cSCL1/GPD1_3 Xi2cSDA2/IEM_SCLK/GPD1_4 Xi2cSCL2/IEM_SPWI/GPD1_5 Y21 W25 W23 Y25 AA22 W24 W21 AA25 V20 V22 Y24 W22 AA24 AC23 AB25 W20 U20 Y23 V21 AB24 AA21 AA23 AC25 Y20 AC24 AB22 AD25 Y22 AD24 AA20 Y19 AB23 F11 C9 AE23 AD22 AC16 AE22 EPLL Filter NC/EPLL(evt1) R21 XjTRSTn XjTMS XjTCK XjTDI R1 XjTDO 100K XOM0 XOM1 XOM2 XOM3 XOM4 XOM5 XXTI [9] XXTO [9] XusbXTI [9] XusbXTO [9] XhdmiXTI [9] XhdmiXTO [9] XnRESET [9] DGND XOM1 XOM2 XOM3 XM1 , XM2, XM3 SD 启启启启 VDD_SYS_3.3V R2 R3 R4 R5 R6 R7 10K/NC 10K 10K/NC 10K 10K/NC 10K/NC XOM0 R8 XOM1 R9 XOM2 R10 XOM3 R11 XOM4 R12 XOM5 R13 XOM[5:0] 10K 10K/NC 10K/NC 10K 10K 10K DGND XOM5 XOM4 XOM3 XOM2 XOM1 XOM0 XCLKOUT TP1 CLKOUT XnRSTOUT [11] R24 10K VDD_5V XnWRESET R55 10K XOM2 R53 XOM3 R61 R68 0R/NC XPWRRGTON [10] U51 VDD_SYS_3.3V 1 nc 5 0R 2 VCC 0R A 4 R33 3 Y GND DGND 74LVC1G04 XrtcXTI [9] XrtcXTO [9] TP4 RTCCLKOUT XRTCCLKO R124 10K/NC XOM2 R86 0R OM2 [11] R87 0R DGND XpwmTOUT0 [11] XpwmTOUT1 [11] XpwmTOUT2 XpwmTOUT3/PWM_MIE DGND XOM0 XOM1 XOM2 XOM3 XOM4 XOM5 OM0 OM1 OM2 OM3 OM4 OM5 D 0R XOM1 C XEINT0 XEINT1 XEINT2 XEINT3 XEINT4 XEINT5 XEINT6_SD0_nWP [11] XEINT7 [11] XEINT8 [11] XEINT9 [11] XEINT10 [11] XEINT11 [11] XEINT12/HDMI_CEC XEINT13/HDMI_HPD [11] XEINT14 [11] XEINT15 [11] XEINT16/KP_COL0 [11] XEINT17/KP_COL1 [11] XEINT18/KP_COL2 [11] XEINT19/KP_COL3 [11] XEINT20/KP_COL4 XEINT21/KP_COL5 XEINT22/KP_COL6 XEINT23/KP_COL7 XEINT24/KP_ROW0 [11] XEINT25/KP_ROW1 [11] XEINT26/KP_ROW2 [11] XEINT27/KP_ROW3 [11] XEINT28/KP_ROW4 XEINT29/KP_ROW5 XEINT30/KP_ROW6 XEINT31/KP_ROW7 Xi2cSDA0 [11] Xi2cSCL0 [11] Xi2cSDA1 Xi2cSCL1 Xi2cSDA2/IEM_SCLK [11] Xi2cSCL2/IEM_SPWI [11] C1 1.8nF R90 4.7K R91 4.7K R14 4.7K R15 4.7K R16 4.7K R17 4.7K VDD_SYS_3.3V 启启启启 SDBOOT OM5 OM4 OM3 OM2 OM1 OM0 001100 Nand 2KB, 5cycle 000010 (Nand 8bit ECC) Nand 4KB, 5cycle 000100 (Nand 8bit ECC) Nand 4KB, 5cycle (default) 0 0 0 1 1 0 (Nand 16bit ECC) B DGND A Title Size A3 Date: Tiny210 Document Number S5PC100 (SYS)/Boot Option Friday, May 24, 2013 Sheet Rev 0.1 3 of 11 5 4 U1B 3 2 D C [8] Xm1CSn0 [8] Xm1DQSn0 [8] Xm1DQSn1 [8] Xm1DQSn2 [8] Xm1DQSn3 B [8] Xm1SCLK [8] Xm1SCLKn A [11] Xm0ADDR[15:0] [7,11] Xm0DATA[15:0] [8] Xm1ADDR[13:0] [8] Xm1BA0 [8] Xm1BA1 [8] Xm1CASn [8] Xm1RASn [8] Xm1WEn [8] Xm1CKE0 [8] Xm1ADDR14 [8] Xm1CSn1/BA2 [8] Xm1DQS0 [8] Xm1DQS1 [8] Xm1DQS2 [8] Xm1DQS3 [8] Xm1DM0 [8] Xm1DM1 [8] Xm1DM2 [8] Xm1DM3 [8] Xm1DATA[7:0] [8] Xm1DATA[15:8] [8] Xm1DATA[23:16] [8] Xm1DATA[31:24] Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 Xm0ADDR3 Xm0ADDR4 Xm0ADDR5 Xm0ADDR6 Xm0ADDR7 Xm0ADDR8 Xm0ADDR9 Xm0ADDR10 Xm0ADDR11 Xm0ADDR12 Xm0ADDR13 Xm0ADDR14 Xm0ADDR15 Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15 Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR13 Xm1ADDR14 Xm1DATA0 Xm1DATA1 Xm1DATA2 Xm1DATA3 Xm1DATA4 Xm1DATA5 Xm1DATA6 Xm1DATA7 Xm1DATA8 Xm1DATA9 Xm1DATA10 Xm1DATA11 Xm1DATA12 Xm1DATA13 Xm1DATA14 Xm1DATA15 Xm1DATA16 Xm1DATA17 Xm1DATA18 Xm1DATA19 Xm1DATA20 Xm1DATA21 Xm1DATA22 Xm1DATA23 Xm1DATA24 Xm1DATA25 Xm1DATA26 Xm1DATA27 Xm1DATA28 Xm1DATA29 Xm1DATA30 Xm1DATA31 K5 L7 Xm0ADDR0/MP04_0 J4 Xm0ADDR1/MP04_1 H5 Xm0ADDR2/MP04_2 J6 Xm0ADDR3/MP04_3 K4 Xm0ADDR4/MP04_4 K6 J5 H4 Xm0ADDR5/MP04_5 Xm0ADDR6/MP04_6 Xm0ADDR7/MP04_7 G4 Xm0ADDR8/MP05_0 J3 Xm0ADDR9/MP05_1 K7 Xm0ADDR10/MP05_2 H6 Xm0ADDR11/MP05_3 G5 Xm0ADDR12/MP05_4 F4 Xm0ADDR13/MP05_5 H3 Xm0ADDR14/MP05_6 Xm0ADDR15/MP05_7 K3 L3 Xm0DATA0/MP06_0 L5 Xm0DATA1/MP06_1 M4 Xm0DATA2/MP06_2 N1 Xm0DATA3/MP06_3 N2 Xm0DATA4/MP06_4 P1 Xm0DATA5/MP06_5 N4 Xm0DATA6/MP06_6 L1 L2 L4 Xm0DATA7/MP06_7 Xm0DATA8/MP07_0 Xm0DATA9/MP07_1 M1 Xm0DATA10/MP07_2 M3 Xm0DATA11/MP07_3 M5 Xm0DATA12/MP07_4 N5 Xm0DATA13/MP07_5 P2 Xm0DATA14/MP07_6 Xm0DATA15/MP07_7 U3 Xm0CSn0/MP01_0 T4 Xm0CSn1/MP01_1 J1 Xm0CSn2/NFCSn0/MP01_2 N9 Xm0CSn3/NFCSn1/MP01_3 N3 Xm0CSn4/NFCSn2/ONANDXL_CSn0/MP01_4 Xm0CSn5/NFCSn3/ONANDXL_CSn1/MP01_5 Xm0OEn/MP01_6 N7 R4 P4 Xm0WEn/MP01_7 T3 Xm0BE0/MP02_0 N6 Memory Xm0BE1/MP02_1 W2 Xm0WAITn/MP02_2 M7 Port0 Xm0DATA_RDn/MP02_3 K1 Xm0FCLE/ONDXL_AVD/MP03_0 K2 Xm0FALE/ONDXL_SMCLK/MP03_1 Xm0FWEn/ONDXL_RPn/MP03_2 Xm0FREn/MP03_3 Xm0FRnB0/ONDXL_INT0/MP03_4 J2 M2 R3 M6 Xm0FRnB1/ONDXL_INT1/MP03_5 V3 Xm0FRnB2/MP03_6 L6 Xm0FRnB3/MP03_7 AB18 XDDR2SEL E21 E20 E17 E15 Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 D18 Xm1ADDR3 F15 Xm1ADDR4 D19 Xm1ADDR5 D20 Xm1ADDR6 E18 Xm1ADDR7 F16 Xm1ADDR8 F19 F14 E19 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 F18 Xm1ADDR12 E16 Xm1ADDR13 D21 Xm1BA0 F17 Xm1BA1 E12 Xm1CASn G17 Xm1RASn G15 G16 G18 G14 Xm1WEn Xm1CKE0 Xm1CKE1/ADDR14 Xm1CSn0 B22 Xm1CSn1 A22 Xm1DQS0 B18 Xm1DQSn0 A18 Xm1DQS1 A15 Xm1DQSn1 B15 Xm1DQS2 D12 C12 C21 Xm1DQSn2 Xm1DQS3 Xm1DQSn3 D17 Xm1DM0 D14 Xm1DM1 C11 Xm1DM2 A16 Xm1DM3 B16 Xm1SCLK Xm1SCLKn A24 C22 Xm1DATA0 B23 Xm1DATA1 A23 Xm1DATA2 B21 Xm1DATA3 A21 Xm1DATA4 C20 Xm1DATA5 C19 Xm1DATA6 B19 Xm1DATA7 B20 Xm1DATA8 A20 Xm1DATA9 A19 Xm1DATA10 C18 Xm1DATA11 A17 Xm1DATA12 B17 Xm1DATA13 C17 Xm1DATA14 D16 Xm1DATA15 C16 Xm1DATA16 D15 Xm1DATA17 C15 Xm1DATA18 E13 Xm1DATA19 E14 F13 XXSmm511PDDVAA2TT1AA02201 C14 Xm1DATA22 D13 Xm1DATA23 B14 Xm1DATA24 A14 Xm1DATA25 C13 Xm1DATA26 B13 Xm1DATA27 A13 Xm1DATA28 B12 Xm1DATA29 A12 Xm1DATA30 Xm1DATA31 Memory Port1 Memory Port2 Xm2ADDR0 Xm2ADDR1 L20 L19 L21 Xm2ADDR2 R23 Xm2ADDR3 F21 Xm2ADDR4 F20 Xm2ADDR5 H22 Xm2ADDR6 J19 Xm2ADDR7 G20 Xm2ADDR8 Xm2ADDR9 Xm2ADDR10 H19 K22 H23 Xm2ADDR11 J22 Xm2ADDR12 H20 Xm2ADDR13 J20 Xm2BA0 K20 Xm2BA1 J23 Xm2BA2 J21 Xm2RASn Xm2WEn Xm2CKE0 Xm2CKE1/ADDR14 P22 J24 G21 N21 Xm2CSn0 K21 Xm2CSn1 N24 Xm2DQS0 N25 Xm2DQSn0 L24 Xm2DQS1 L25 Xm2DQSn1 F24 Xm2DQS2 Xm2DQSn2 Xm2DQS3 F25 C24 C25 Xm2DQSn3 P25 Xm2DM0 L22 Xm2DM1 H21 Xm2DM2 E22 Xm2DM3 G24 Xm2SCLK G25 Xm2SCLKn Xm2DATA0 Xm2DATA1 P23 R24 R25 Xm2DATA2 P24 Xm2DATA3 N23 Xm2DATA4 M22 Xm2DATA5 N22 Xm2DATA6 M23 Xm2DATA7 M21 Xm2DATA8 Xm2DATA9 Xm2DATA10 M24 L23 M25 Xm2DATA11 K25 Xm2DATA12 K23 Xm2DATA13 J25 Xm2DATA14 K24 Xm2DATA15 H25 Xm2DATA16 H24 Xm2DATA17 Xm2DATA18 Xm2DATA19 Xm2DATA20 G23 G22 F23 E25 Xm2DATA21 E24 Xm2DATA22 E23 Xm2DATA23 D25 Xm2DATA24 D24 Xm2DATA25 D23 Xm2DATA26 F22 Xm2DATA27 Xm2DATA28 Xm2DATA29 D22 B25 C23 Xm2DATA30 B24 Xm2DATA31 Xm0CSn0 Xm0CSn1 [11] Xm0CSn2/NFCSn0 [7] Xm0CSn3/NFCSn1 [7] Xm0OEn [11] Xm0WEn [11] Xm0BE0 Xm0FCLE/ONDAVD [7] Xm0FALE/ONDSMCLK [7] Xm0FWEn/ONDRPn [7] Xm0FREn [7] XDDR2SEL [8] Xm2ADDR0 Xm2ADDR1 Xm2ADDR2 Xm2ADDR3 Xm2ADDR4 Xm2ADDR5 Xm2ADDR6 Xm2ADDR7 Xm2ADDR8 Xm2ADDR9 Xm2ADDR10 Xm2ADDR11 Xm2ADDR12 Xm2ADDR13 Xm2ADDR[13:0] Xm2DATA0 Xm2DATA1 Xm2DATA2 Xm2DATA3 Xm2DATA4 Xm2DATA5 Xm2DATA6 Xm2DATA7 Xm2DATA8 Xm2DATA9 Xm2DATA10 Xm2DATA11 Xm2DATA12 Xm2DATA13 Xm2DATA14 Xm2DATA15 Xm2DATA16 Xm2DATA17 Xm2DATA18 Xm2DATA19 Xm2DATA20 Xm2DATA21 Xm2DATA22 Xm2DATA23 Xm2DATA24 Xm2DATA25 Xm2DATA26 Xm2DATA27 Xm2DATA28 Xm2DATA29 Xm2DATA30 Xm2DATA31 Xm2DATA[7:0] Xm2DATA[15:8] Xm2DATA[23:16] Xm2DATA[31:24] 4.7K R56 4.7K R48 VDD_SYS_3.3V 1 4.7K 4.7K 4.7K R45 R46 R47 Xm0WAITn [11] Xm0DATA_RDn D Xm0FRnB0/ONDXL_INT0 [7] Xm0FRnB1/ONDXL_INT1 Xm0FRnB2 Xm0FRnB3 C Xm2BA0 Xm2BA1 Xm2CASn Xm2RASn Xm2WEn Xm2CKE0 Xm2CKE1/ADDR14 Xm2CSn0 Xm2CSn1 Xm2DQS0 Xm2DQSn0 Xm2DQS1 Xm2DQSn1 Xm2DQS2 Xm2DQSn2 Xm2DQS3 Xm2DQSn3 Xm2DM0 Xm2DM1 Xm2DM2 Xm2DM3 Xm2SCLK B Xm2SCLKn Title Size A3 Date: Tiny210 Document Number Friday, May 24, 2013 A Sheet Rev 0.1 4 of 11 5 4 3 2 1 U1C [11] XvVD[23:0] [11] XvHSYNC [11] XvVSYNC [11] XvVDEN [11] XvVCLK R62 R64 22R 22R AA13 Y10 XvHSYNC/SYSCS0/VENHSYNC/GPF0_0 R66 22R AB10 XvVSYNC/SYSCS1/VENVSYNC/GPF0_1 R67 22R AA10 XvVDEN/SYSRS/VENHREF/GPF0_2 XvVCLK/SYSWE/V601CLK/GPF0_3 RN-8P4R-19P7X50A XvVD0 200R 5 4 RN3D AA9 D RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD1 200R 5 XvVD2 200R 6 4 RN5D 3 RN3C AB9 XvVD0/SYSD0/VEND0/GPF0_4 AB8 XvVD1/SYSD1/VEND1/GPF0_5 RN-8P4R-19P7X50A XvVD3 200R 7 2 RN3B AB7 XvVD2/SYSD2/VEND2/GPF0_6 RN-8P4R-19P7X50A RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD4 200R 6 XvVD5 200R 8 XvVD6 200R 8 3 RN5C 1 RN4A 1 RN7A Y9 AB6 AE7 XvVD3/SYSD3/VEND3/GPF0_7 XvVD4/SYSD4/VEND4/GPF1_0 XvVD5/SYSD5/VEND5/GPF1_1 RN-8P4R-19P7X50A XvVD7 200R 8 1 RN6A AC9 XvVD6/SYSD6/VEND6/GPF1_2 RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD8 200R 8 XvVD9 200R 5 1 RN5A 4 RN4D AA8 XvVD7/SYSD7/VEND7/GPF1_3 W9 XvVD8/SYSD8/V656D0/GPF1_4 RN-8P4R-19P7X50A XvVD10 200R 6 3 RN7C AE6 XvVD9/SYSD9/V656D1/GPF1_5 RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD11 200R 7 XvVD12 200R 7 2 RN6B 2 RN5B AC8 XvVD10/SYSD10/V656D2/GPF1_6 Y8 XvVD11/SYSD11/V656D3/GPF1_7 RN-8P4R-19P7X50A XvVD13200R 6 3 RN6C AC7 XvVD12/SYSD12/V656D4/GPF2_0 RN-8P4R-19P7X50A RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD14 200R 8 XvVD15 200R 7 XvVD16 200R 5 1 RN8A 2 RN8B 4 RN6D AD6 AE5 AD7 XvVD13/SYSD13/V656D5/GPF2_1 XvVD14/SYSD14/V656D6/GPF2_2 XvVD15/SYSD15/V656D7/GPF2_3 [DSI] MIPI-DSI/CSI [CSI] XmipiMDPCLK XmipiMDNCLK XmipiMDP0 XmipiMDN0 XmipiMDP1 XmipiMDN1 XmipiMDP2 XmipiMDN2 XmipiMDP3 XmipiMDN3 XmipiSDPCLK XmipiSDNCLK XmipiSDP0 XmipiSDN0 XmipiSDP1 XmipiSDN1 XmipiSDP2 XmipiSDN2 XmipiSDP3 XmipiSDN3 AE15 AD15 AE17 AD17 AE16 AD16 AE14 AD14 AE13 AD13 AD10 AE10 AD12 AE12 AD11 AE11 AD9 AE9 AD8 AE8 XmipiMDPCLK XmipiMDNCLK XmipiMDP0 XmipiMDN0 XmipiMDP1 XmipiMDN1 XmipiMDP2 XmipiMDN2 XmipiMDP3 XmipiMDN3 XmipiSDPCLK XmipiSDNCLK XmipiSDP0 XmipiSDN0 XmipiSDP1 XmipiSDN1 XmipiSDP2 XmipiSDN2 XmipiSDP3 XmipiSDN3 D RN-8P4R-19P7X50A RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD17200R 8 XvVD18 200R 6 XvVD19 200R 5 1 RN3A 3 RN8C 4 RN7D AA7 XvVD16/SYSD16/GPF2_4 AD5 XvVD17/SYSD17/GPF2_5 AA6 XvVD18/SYSD18/GPF2_6 LCDC AC15 XmipiVREG_0P4V C4 2nF DGND RN-8P4R-19P7X50A RN-8P4R-19P7X50A RN-8P4R-19P7X50A RN-8P4R-19P7X50A XvVD20 200R 7 XvVD21200R 5 XvVD22 200R 7 XvVD23 200R 6 2 RN7B 4 RN8D 2 RN4B 3 RN4C AB5 XvVD19/SYSD19/GPF2_7 AC5 XvVD20/SYSD20/GPF3_0 AC6 XvVD21/SYSD21/GPF3_1 Y7 W8 AE4 XvVD22/SYSD22/GPF3_2 XvVD23/SYSD23/V656_CLK/GPF3_3 VSYNC_LDI/GPF3_4 SYS_OE/VEN_FIELD/GPF3_5 HDMI T2 XhdmiTX0P T1 XhdmiTX0N U2 XhdmiTX1P XhdmiTX1N XhdmiTX2P XhdmiTX2N U1 V2 V1 R2 XhdmiTXCP R1 XhdmiTXCN W1 XhdmiREXT XhdmiTX0P XhdmiTX0N XhdmiTX1P XhdmiTX1N XhdmiTX2P XhdmiTX2N XhdmiTXCP XhdmiTXCN R57 4.7K DGND C VDD_DAC_AP TP13 XADCOUT R25 0R C5 104 [11] XdacOUT DACVREF TP5 [11] XadcAIN0 [11] XadcAIN1 XadcAIN2 XadcAIN3 XadcAIN4 XadcAIN5 [11] XadcAIN6_YM [11] XadcAIN7_YP [11] XadcAIN8_XM [11] XadcAIN9_XP R26 1.2K,1% C6 R27 104 75,1% [11] XciPCLK [11] XciVSYNC [11] XciHREF DGND DGND DGND [11] XciYDATA0 [11] XciYDATA1 [11] XciYDATA2 [11] XciYDATA3 B [11] XciYDATA4 [11] XciYDATA5 [11] XciYDATA6 AC11 AC12 AB11 AC10 Y11 W12 Y12 AA12 AA11 AB12 U5 W5 V5 V4 XadcAIN0 XadcAIN1 XadcAIN2 XadcAIN3 XadcAIN4 XadcAIN5 XadcAIN6 XadcAIN7 XadcAIN8 XadcAIN9 XdacOUT XdacIREF XdacVREF XdacCOMP AC21 AA14 AB14 AB15 AB16 AB20 AA19 AB21 Y18 AB17 AA17 XciPCLK/GPE0_0 XciVSYNC/GPE0_1 XciHREF/GPE0_2 XciYDATA0/GPE0_3 XciYDATA1/GPE0_4 XciYDATA2/GPE0_5 XciYDATA3/GPE0_6 XciYDATA4/GPE0_7 XciYDATA5/GPE1_0 XciYDATA6/GPE1_1 TouchScreen ADC TVOUT DAC CAM (VDD_CAM) H1 XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK/GPJ0_0 G6 XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK/GPJ0_1 E4 XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK/GPJ0_2 XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC/GPJ0_3 XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL/GPJ0_4 H7 G1 H2 XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA/GPJ0_5 F5 XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR/GPJ0_6 D5 XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0/GPJ0_7 F6 XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1/GPJ1_0 G2 XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2/GPJ1_1 F1 XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3/GPJ1_2 G3 XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4/GPJ1_3 Modem XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5/GPJ1_4 Camera B XmsmADDR13/KP_COL_0/SROM_ADDR21/MHL_D6/GPJ1_5 E5 F2 CF F3 XmsmDATA0/KP_COL_1/CF_DATA0/MHL_D7/GPJ2_0 E2 MHL XmsmDATA1/KP_COL_2/CF_DATA1/MHL_D8/GPJ2_1 E1 XmsmDATA2/KP_COL_3/CF_DATA2/MHL_D9/GPJ2_2 D3 Key SROM XmsmDATA3/KP_COL_4/CF_DATA3/MHL_D10/GPJ2_3 D1 XmsmDATA4/KP_COL_5/CF_DATA4/MHL_D11/GPJ2_4 E3 XmsmDATA5/KP_COL_6/CF_DATA5/MHL_D12/GPJ2_5 D2 XmsmDATA6/KP_COL_7/CF_DATA6/MHL_D13/GPJ2_6 addr[16:22] XmsmDATA7/KP_ROW_0/CF_DATA7/MHL_D14/GPJ2_7 (VDD_MODEM) XmsmDATA8/KP_ROW_1/CF_DATA8/MHL_D15/GPJ3_0 C1 C2 D4 XmsmDATA9/KP_ROW_2/CF_DATA9/MHL_D16/GPJ3_1 B1 XmsmDATA10/KP_ROW_3/CF_DATA10/MHL_D17/GPJ3_2 C3 XmsmDATA11/KP_ROW_4/CF_DATA11/MHL_D18/GPJ3_3 C4 XmsmDATA12/KP_ROW_5/CF_DATA12/MHL_D19/GPJ3_4 B2 XmsmDATA13/KP_ROW_6/CF_DATA13/MHL_D20/GPJ3_5 B3 XmsmDATA14/KP_ROW_7/CF_DATA14/MHL_D21/GPJ3_6 A2 XmsmDATA15/KP_ROW_8/CF_DATA15/MHL_D22/GPJ3_7 GPJ3_2 CAM_B_D0 CAM_B_D1 CAM_B_D2 CAM_B_D3 CAM_B_D4 CAM_B_D5 CAM_B_D6 CAM_B_D7 CAM_B_PCLK CAM_B_VSYNC CAM_B_HREF CAM_B_FIELD CAM_B_CLKOUT camera B GPJ3_3 GPJ3_4 LED1 [11] LED2 [11] LED LED3 [11] LED4 [11] CAMERA_A_GPIO0 CAMERA_A_GPIO1 [11] CAMERA_A_GPIO2 [11] camera 控控 CAMERA_B_GPIO1 CAMERA_B_GPIO2 CAM_A_RESET [11] CAM_B_RESET GPJ3_3 GPJ3_4 GPIO WIFI0_PWR_ONOFF WIFI0_RESET_GPIO [11] WIFI0_PD_GPIO [11] WIFI C B [11] XciYDATA7 [11] XciCLKenb [11] XciFIELD AA18 AB19 XciYDATA7/GPE1_2 XciCLKenb/GPE1_3 XciFIELD/GPE1_4 XmsmCSn/KP_ROW_9/CF_CSn0/MHL_D23/GPJ4_0 XmsmWEn/KP_ROW_10/CF_CSn1/MHL_HSYNC/GPJ4_1 G8 B4 G9 XmsmRn/KP_ROW_11/CF_IORN/MHL_IDCK/GPJ4_2 A3 XmsmIRQn/KP_ROW_12/CF_IOWN/MHL_VSYNC/GPJ4_3 A4 WIFI1_nWP WIFI1_IO WIFI1_PWR_ONOFF WIFI1_PD_GPIO XmsmADVN/KP_ROW_13/SROM_ADDR22/MHL_DE/GPJ4_4 WIFI1_RESET_GPIO S5PV210 VDD_SYS_3.3V R22 R21 R23 10K 10K 10K GPJ3_2 GPJ3_3 GPJ3_4 R19 10K R20 10K R18 10K A DGND A 硬硬 版版版版 Title Size A3 Date: Micro210 Document Number Friday, May 24, 2013 Sheet Rev 0.1 5 of 11 5 VDD_ARM_AP D VDD_INT_AP VDD_ALIVE_AP VDD_M0_AP C VDD_MEM_1.8V VDD_ADC_AP VDD_AUD_AP VDD_CAM_AP VDD_DAC_AP VDD_MODEM_AP VDD_KEY_AP VDD_LCD_AP VDD_MIPI_1.1V_AP B VDD_MIPI_PLL_AP VDD_MIPI_1.8V_AP VDD_HDMI_OSC_AP VDD_HDMI_PLL_AP VDD_HDMI_AP VDD_UH_3.3V_AP VDD_UO_3.3V_AP VDD_UH_1.1V_AP VDD_UO_1.1V_AP VDD_CKO__AP VDD_RTC_AP VDD_EXT_AP VDD_SYS_AP VDD_APLL_AP VDD_MPLL_AP VDD_EPLL_AP VDD_VPLL_AP A U1D L13 L14 VDD_ARM0 L15 VDD_ARM1 M13 VDD_ARM2 M14 M15 N14 N15 VDD_ARM3 VDD_ARM4 VDD_ARM5 VDD_ARM6 N16 VDD_ARM7 P14 VDD_ARM8 P15 VDD_ARM9 VDD_ARM10 K13 K14 K15 L10 L11 M11 N10 N11 P11 R11 R12 R13 T11 R17 W15 K9 M9 J13 J14 J15 J16 J17 K17 L17 M17 W10 U9 U19 V19 V7 U7 J7 T17 U10 U12 U13 W14 Y13 T7 R6 P6 Y16 W16 W13 U15 P17 P21 J10 T9 W18 G11 P9 U16 U17 T19 M20 N20 R20 P20 VDD_INT0 VDD_INT1 VDD_INT2 VDD_INT3 VDD_INT4 VDD_INT5 VDD_INT6 VDD_INT7 VDD_INT8 VDD_INT9 VDD_INT10 VDD_INT11 VDD_INT12 VDD_ALIVE_0 VDD_ALIVE_1 VDD_M0_0 VDD_M0_1 VDD_M1_0 VDD_M1_1 VDD_M1_2 VDD_M1_3 VDD_M2_0 VDD_M2_1 VDD_M2_2 VDD_M2_3 VDD_ADC VDD_AUD_0 VDD_AUD_1 VDD_CAM VDD_DAC VDD_DAC_A VDD_MODEM VDD_KEY VDD_LCD VDD_MIPI_D_0 VDD_MIPI_D_1 VDD_MIPI_PLL VDD_MIPI_A VDD_HDMI_OSC VDD_HDMI_PLL VDD_HDMI VDD_UHOST_A VDD_UOTG_A VDD_UHOST_D VDD_UOTG_D VDD_CKO VDD_RTC VDD_EXT0 VDD_EXT1_0 VDD_EXT1_1 VDD_EXT2 VDD_SYS0_0 VDD_SYS0_1 VDD_SYS0_2 VDD_SYS1 VDD_APLL VDD_MPLL VDD_EPLL VDD_VPLL S5PV210 4 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 A1 A25 AE1 AE25 G7 G19 J12 K10 K11 K12 K16 K19 L9 L12 L16 M10 M12 M16 N12 N17 P10 P12 P13 P16 R9 R10 R14 R15 R16 T10 T12 T13 T14 T15 T16 W7 W19 DGND VSS_ADC VSS_DAC VSS_HDMI VSS_MIPI_0 VSS_MIPI_1 VSS_DAC_A VSS_UHOST_A VSS_UOTG_A VSS_UHOST_AC VSS_UOTG_AC VSS_UHOST_D VSS_UOTG_D VSS_HDMI_OSC VSS_HDMI_PLL W11 V6 R7 U11 U14 U6 AA15 Y17 AA16 Y15 Y14 W17 T6 P7 DGND M19 VSS_APLL N19 VSS_MPLL VSS_EPLL VSS_VPLL R19 P19 DGND 3 2 1 VDD_ALIVE_AP VDD_M0_AP VDD_MEM_1.8V VDD_SYS_AP TC1 C7 10u 104 TC2 C8 C9 10u 104 104 TC3 C10 C11 C12 C13 10u 104 104 104 104 C14 C15 104 104 VDD_LCD_AP VDD_CAM_AP D C16 C17 104 104 DGND DGND VDD_AUD_AP DGND VDD_EXT_AP VDD_RTC_AP DGND DGND DGND VDD_ADC_AP VDD_DAC_AP VDD_HDMI_AP C18 C19 C20 C21 C22 C23 C24 C25 C26 104 104 104 104 104 104 104 104 104 DGND DGND DGND DGND DGND DGND VDD_MIPI_1.1V_AP VDD_MIPI_1.8V_APVDD_MIPI_PLL_AP VDD_APLL_AP VDD_MPLL_AP VDD_EPLL_APVDD_VPLL_AP VDD_UH_1.1V_AVPDD_UO_1.1V_AP VDD_UO_3.3V_AP C C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 104 104 104 104 104 104 104 104 104 104 104 DGND DGND VDD_ARM_AP DGND DGND DGND DGND DGND DGND DGND VDD_CKO__AP VDD_MODEM_AP DGND VDD_UH_3.3V_AP TC4 TC5 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C49 10u 10u 104 104 104 104 104 104 104 104 104 104 104 C48 C51 C50 104 104 104 DGND DGND DGND DGND B VDD_HDMI_OSC_AP VDD_KEY_AP VDD_INT_AP C52 C53 VDD_HDMI_PLL_AP 104 104 C54 TC6 TC7 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 10u 10u 104 104 104 104 104 104 104 104 104 104 104 104 104 DGND VDD_HDMI_AP C68 DGND VDD_VPLL_AP 104 DGND DGND 104 C69 104 DGND DGND A Title Size A3 Date: Tiny210 Document Number Friday, May 24, 2013 Sheet Rev 0.1 6 of 11 5 4 3 2 1 D VDD_SYS_3.3V NAND Flash memory D VDD_SYS_3.3V R54 0R/NC U2 VDD_SYS_3.3V R95 1 48 R28 4.7K DGND 0R/NC 2 NC0 3 4 NC1 NC2 5 NC3 NC29/ VSS2 47 NC28/ IO15 NC27/ IO7 46 45 NC26/ IO14 44 Xm0DATA7 Xm0DATA[15:0] [4,11] [4] Xm0FRnB0/ONDXL_INT0 [4] Xm0FREn [4] Xm0CSn2/NFCSn0 [4] Xm0CSn3/NFCSn1 C R29 0R R30 0R 6 NC4 7 8 NC5 R/nB 9 nRE 10 nCE 11 NC6 12 13 NC7 VCC0 IO7/ IO6 43 IO6/ IO13 IO5 42 41 IO4/ IO12 40 NC25/ IO4 39 NC24 38 NC23 VCC1 37 36 Xm0DATA6 Xm0DATA5 Xm0DATA4 R59 0R/NC VDD_SYS_3.3V C 14 VSS0 VSS/ NC22 35 [4] Xm0FCLE/ONDAVD [4] Xm0FALE/ONDSMCLK [4] Xm0FWEn/ONDRPn VDD_SYS_3.3V R32 10K DGND R110 15 NC8 16 17 NC9 CLE 18 ALE 19 nWE 20 nWP 21 22 NC10 NC11 23 NC12 24 NC13 NC21 34 NC20 NC19/ IO11 33 32 IO3 31 IO2/ IO10 30 IO1/ IO2 29 IO0/ IO9 NC18/ IO1 28 27 NC17/ IO8 26 NC16/ IO0 25 R60 0R/NC Xm0DATA3 Xm0DATA2 Xm0DATA1 Xm0DATA0 NAND 0R/NC NC14 NC15/ VSS1 DGND R58 0R/NC K9K8G08U0B/或或或或或 R35 R36 0R NC B B VDD_SYS_3.3V VDD_SYS_3.3V DGND TC8 C70 C71 10u 104 104 DGND A A Title Size A4 Date: Tiny210 Document Number Wednesday, September 25, 2013 Sheet Rev 0.1 7 of 11 D C 5 4 [4,8] Xm1ADDR[13:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR13 [4,8] Xm1BA0 [4,8] Xm1BA1 [4,8] Xm1CSn1/BA2 [4] Xm1DQSn0 [4] Xm1DQS0 [4] Xm1DM0 [4,8] Xm1SCLKn [4,8] Xm1SCLK [4,8] Xm1RASn [4,8] Xm1CASn [4,8] Xm1CSn0 [4,8] Xm1CKE0 [4,8] Xm1WEn U3 H8 H3 A0 H7 A1 J2 A2 J8 A3 J3 A4 J7 A5 K2 A6 K8 A7 K3 A8 H2 A9 K7 A10/AP L2 A11 L8 A12 A13 G2 G3 BA0 G1 BA1 BA2 A8 B7 nDQS DQS B3 A2 DM/RDQS NU/nRDQS F8 E8 nCK CK F7 G7 nRAS nCAS G8 F2 nCS F3 CKE nWE B8 B2 VSSQ0 A7 VSSQ1 D2 VSSQ2 D8 VSSQ3 VSSQ4 K9 J1 VSS0 A3 VSS1 E3 VSS2 VSS3 A9 VDDQ0 C1 VDDQ1 C9 VDDQ2 C7 VDDQ3 C3 VDDQ4 A1 VDD0 E9 VDD1 H9 VDD2 L1 VDD3 E1 VDDL E7 VSSDL E2 VREF F9 ODT VDD_MEM_1.8V C98 104 DGND ODT1 VDD_MEM_1.8V R39 10K/1% C105 100n R42 10K/1% C8 Xm1DATA0 DQ0 C2 Xm1DATA1 DQ1 D7 Xm1DATA2 DQ2 D3 Xm1DATA3 DQ3 D1 Xm1DATA4 DQ4 D9 Xm1DATA5 DQ5 B1 Xm1DATA6 DQ6 B9 Xm1DATA7 DQ7 DGND Xm1DATA[7:0] [4] L3 NC0 L7 NC1 Xm1ADDR14 Xm1ADDR14 [4,8] 兼兼2Gbit的的的 DGND K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb) [4,8] Xm1ADDR[13:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR13 B [4,8] Xm1BA0 [4,8] Xm1BA1 [4,8] Xm1CSn1/BA2 [4] Xm1DQSn2 [4] Xm1DQS2 [4] Xm1DM2 [4,8] Xm1SCLKn [4,8] Xm1SCLK [4,8] Xm1RASn [4,8] Xm1CASn [4,8] Xm1CSn0 [4,8] Xm1CKE0 [4,8] Xm1WEn U5 H8 H3 A0 H7 A1 J2 A2 J8 A3 J3 A4 J7 A5 K2 A6 K8 A7 K3 A8 H2 A9 K7 A10/AP L2 A11 L8 A12 A13 G2 G3 BA0 G1 BA1 BA2 A8 B7 nDQS DQS B3 A2 DM/RDQS NU/nRDQS F8 E8 nCK CK F7 G7 nRAS nCAS G8 F2 nCS F3 CKE nWE B8 B2 VSSQ0 A7 VSSQ1 D2 VSSQ2 D8 VSSQ3 VSSQ4 K9 J1 VSS0 A3 VSS1 E3 VSS2 VSS3 A9 VDDQ0 C1 VDDQ1 C9 VDDQ2 C7 VDDQ3 C3 VDDQ4 A1 VDD0 E9 VDD1 H9 VDD2 L1 VDD3 E1 VDDL E7 VSSDL E2 VREF F9 ODT VDD_MEM_1.8V C151 104 DGND ODT1 VDD_MEM_1.8V R51 10K/1% C152 100n R52 10K/1% C8 Xm1DATA16 DQ0 C2 Xm1DATA17 DQ1 D7 Xm1DATA18 DQ2 D3 Xm1DATA19 DQ3 D1 Xm1DATA20 DQ4 D9 Xm1DATA21 DQ5 B1 Xm1DATA22 DQ6 B9 Xm1DATA23 DQ7 DGND Xm1DATA[23:16] [4] L3 NC0 L7 NC1 Xm1ADDR14 Xm1ADDR14 [4,8] 兼兼2Gbit的的的 K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb) DGND A 5 4 3 2 [4,8] Xm1ADDR[13:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR13 [4,8] Xm1BA0 [4,8] Xm1BA1 [4,8] Xm1CSn1/BA2 [4] Xm1DQSn1 [4] Xm1DQS1 [4] Xm1DM1 [4,8] Xm1SCLKn [4,8] Xm1SCLK [4,8] Xm1RASn [4,8] Xm1CASn [4,8] Xm1CSn0 [4,8] Xm1CKE0 [4,8] Xm1WEn U4 H8 H3 A0 H7 A1 J2 A2 J8 A3 J3 A4 J7 A5 K2 A6 K8 A7 K3 A8 H2 A9 K7 A10/AP L2 A11 L8 A12 A13 G2 G3 BA0 G1 BA1 BA2 A8 B7 nDQS DQS B3 A2 DM/RDQS NU/nRDQS F8 E8 nCK CK F7 G7 nRAS nCAS G8 F2 nCS F3 CKE nWE B8 B2 VSSQ0 A7 VSSQ1 D2 VSSQ2 D8 VSSQ3 VSSQ4 K9 J1 VSS0 A3 VSS1 E3 VSS2 VSS3 A9 VDDQ0 C1 VDDQ1 C9 VDDQ2 C7 VDDQ3 C3 VDDQ4 A1 VDD0 E9 VDD1 H9 VDD2 L1 VDD3 E1 VDDL E7 VSSDL E2 VREF F9 ODT VDD_MEM_1.8V C99 104 DGND ODT1 VDD_MEM_1.8V R40 10K/1% C100 100n R44 10K/1% C8 Xm1DATA8 DQ0 C2 Xm1DATA9 DQ1 D7 Xm1DATA10 DQ2 D3 Xm1DATA11 DQ3 D1 Xm1DATA12 DQ4 D9 Xm1DATA13 DQ5 B1 Xm1DATA14 DQ6 B9 Xm1DATA15 DQ7 DGND Xm1DATA[15:8] [4] L3 NC0 L7 NC1 Xm1ADDR14 Xm1ADDR14 [4,8] 兼兼2Gbit的的的 DGND K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb) [4,8] Xm1ADDR[13:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR13 [4,8] Xm1BA0 [4,8] Xm1BA1 [4,8] Xm1CSn1/BA2 [4] Xm1DQSn3 [4] Xm1DQS3 [4] Xm1DM3 [4,8] Xm1SCLKn [4,8] Xm1SCLK [4,8] Xm1RASn [4,8] Xm1CASn [4,8] Xm1CSn0 [4,8] Xm1CKE0 [4,8] Xm1WEn U6 H8 H3 A0 H7 A1 J2 A2 J8 A3 J3 A4 J7 A5 K2 A6 K8 A7 K3 A8 H2 A9 K7 A10/AP L2 A11 L8 A12 A13 G2 G3 BA0 G1 BA1 BA2 A8 B7 nDQS DQS B3 A2 DM/RDQS NU/nRDQS F8 E8 nCK CK F7 G7 nRAS nCAS G8 F2 nCS F3 CKE nWE B8 B2 VSSQ0 A7 VSSQ1 D2 VSSQ2 D8 VSSQ3 VSSQ4 K9 J1 VSS0 A3 VSS1 E3 VSS2 VSS3 A9 VDDQ0 C1 VDDQ1 C9 VDDQ2 C7 VDDQ3 C3 VDDQ4 A1 VDD0 E9 VDD1 H9 VDD2 L1 VDD3 E1 VDDL E7 VSSDL E2 VREF F9 ODT VDD_MEM_1.8V C96 104 DGND ODT1 VDD_MEM_1.8V R49 10K/1% C97 100n R50 10K/1% C8 Xm1DATA24 DQ0 C2 Xm1DATA25 DQ1 D7 Xm1DATA26 DQ2 D3 Xm1DATA27 DQ3 D1 Xm1DATA28 DQ4 D9 Xm1DATA29 DQ5 B1 Xm1DATA30 DQ6 B9 Xm1DATA31 DQ7 DGND Xm1DATA[31:24] [4] L3 NC0 L7 NC1 Xm1ADDR14 Xm1ADDR14 [4,8] 兼兼2Gbit的的的 K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb) DGND 3 2 1 VDD_MEM_1.8V R37 10K R38 NC DGND VDD_MEM_1.8V R41 R43 10K 10K/NC DGND XDDR2SEL [4] ODT1 D VDD_MEM_1.8V TC9 TC10 + + C74 C75 C76 C77 C78 C79 C80 C72 C73 C81 10u 10u 104 104 104 104 104 104 104 104 104 104 DGND VDD_MEM_1.8V TC11 10u TC12 10u C87 C88 C89 C91 C90 C92 C93 C85 C86 C95 104 104 104 104 104 104 104 104 104 104 DGND VDD_MEM_1.8V TC14 10u TC15 10u C111 C112 C113 C115 C114 C116 C117 C109 C110 C119 104 104 104 104 104 104 104 104 104 104 DGND VDD_MEM_1.8V TC13 10u TC16 10u C124 C125 C126 C128 C127 C129 C130 C122 C123 C132 104 104 104 104 104 104 104 104 104 104 DGND C B A Title Size A2 Date: Tiny210 Document Number Memory(mDDR) Friday, May 24, 2013 1 Sheet Rev 0.1 8 of 11 5 4 3 2 1 D D 24Mhz-M For PLL XXTI [3] For 24Mhz-H USB HOST XusbXTI [3] 1 1 X1 X2 3 4 R77 C137 3 4 R79 C139 C 5.1M 15p 5.1M 15p C 2 2 24MHz 24MHz 复复复复 DGND C138 15p XXTO [3] DGND C143 15p XusbXTO [3] [11] M_nRESET VDD_SYS_3.3V R69 4.7K C136 104 C135 104 U8 4 VCC 1 GND 3 MR# RESET# 2 MAX811 DGND TP14 V_RST R70 10K XnRESET [3] 27Mhz DGND 1 X3 3 4 R78 5.1M C140 15p 2 27MHz DGND C142 For VEDIO 15p XhdmiXTI [3] X4 32.768K xtal-32K-MC146 RTC_CLK C144 DGND 13p 4 4 1 1 3 3 2 2 R82 10M XhdmiXTO [3] 13p C141 For RTC XrtcXTI [3] XrtcXTO [3] B DGND DGND DGND B A A Title Size A3 Date: Tiny210 Document Number Friday, May 24, 2013 Sheet Rev 0.1 9 of 11 5 4 3 TP21 V_PLL [3,10] XPWRRGTON VDD_5V C189 10u U13 4 3 VIN LX L2 2.2UH R138 0R 1 EN 2 5 GND FB R140 120K C190 C191 VDD_INT_AP D rt8024 10u R141 104 100K 2 1 VDD_SYS_3.3V 3.3V电电电电电 R139 1K LED3v3 LED DGND D DGND [3,10] XPWRRGTON VDD_5V C192 10u DGND TP22 V_ARM U15 4 3 L3 VIN LX 2.2UH R143 0R 1 EN 2 5 GND FB R144 120K C195 C196 rt8024 10u R146 104 100K VDD_ARM_AP VDD_SYS_1.2V VDD_5V C193 100n DGND C194 100p R145 10K DGND U14 1 VIN VOUT 5 2 GND 3 EN 4 NC XC6209-1.2V TP23 R142 1.2V 0R VDD_ALIVE_AP C197 10u C198 104 DGND C DGND DGND C [3,10] XPWRRGTON VDD_5V C199 10u TP24 U16 4 VIN LX 3 1 EN 2 5 GND FB L4 2.2UH R148 100K C200 R147 C201 V_HDMI 0R [3,10] XPWRRGTON VDD_HDMI_AP VDD_5V VDD_MIPI_1.1V_AP VDD_UO_1.1V_AP VDD_UH_1.1V_AP VDD_APLL_AP C202 10u VDD_EPLL_AP rt8024 10u R149 104 VDD_MPLL_AP VDD_VPLL_AP 120K VDD_MIPI_PLL_AP VDD_HDMI_PLL_AP U17 4 3 L5 VIN LX 1 EN 2 5 GND FB rt8059 2.2UH R152 200K C203 10u R153 100K R151 C204 104 TP25 V_MEM 0R 1.8V VDD_MEM_1.8V VDD_MIPI_1.8V_AP VDD_SYS_1.8V DGND DGND DGND DGND B B V_SYS_3V3 VDD_HDMI_OSC_AP VDD_CKO__AP VDD_KEY_AP U18 MP2143DJ TP26 VDD_MODEM_AP VDD_5V C251 22u C447 104 R324 100K/NC SOT23-8-25P6 2 VIN 3 SW 8 EN 5 OUT L1 L4D18 MNR-4018-1R0M COMMON C246 104 TC20 + 33u C245 104 R154 0R VDD_CAM_AP VDD_DAC_AP VDD_SYS_AP VDD_SYS_GPS_AP VDD_EXT_AP VDD_MSM_AP VDD_MMC_AP VDD_AUD_AP DGND [3,10] XPWRRGTON R326 0R 1 PG 4 6 GND FB 7 R331 200K,1% R1 R325 R2 100K,1% GND1 0R R157 VDD_CAN_AP VDD_ADC_AP VDD_UH_3.3V_AP VDD_UO_3.3V_AP VDD_LCD_AP VDD_M0_AP VDD_SYS_3.3V VDD_RTC_AP R158 A DGND 0R/NC A DGND Title Size A3 Date: Tiny210 Document Number Wednesday, September 25, 2013 Sheet 10 of Rev 0.1 11 5 4 3 2 1 VDD_5V P1 P2 [4,11] Xm0ADDR[15:0] Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 Xm0ADDR3 [4,11] Xm0ADDR[15:0] Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 C159 100n D9 6.3V 1 XvVD23 3 1 XvVD21 5 3 XvVD19 7 5 XvVD15 9 7 XvVD13 11 9 2 24 46 68 8 10 10 12 XvVD22 XvVD20 XvVD18 XvVD14 XvVD12 DGND [3] OM2 [9] M_nRESET [3] XuRTSn1 [3] XuTXD0 [3] XuTXD1 1 31 53 75 97 11 9 2 24 46 68 8 10 10 12 R181 0R XuCTSn1 [3] XuRXD0 [3] XuRXD1 [3] DGND VDD_RTC_AP D Xm0ADDR4 Xm0ADDR3 Xm0ADDR5 Xm0ADDR4 Xm0ADDR6 Xm0ADDR5 Xm0ADDR7 Xm0ADDR6 DGND XvVD11 13 11 XvVD7 15 13 XvVD5 17 15 XvVD3 19 17 12 14 14 16 16 18 18 20 XvVD10 XvVD6 XvVD4 XvVD2 [3] XuTXD2/UART_AUDIO_TXD [3] XuTXD3/RTSn2/UART_AUDIO_RTSn [3] XspiMOSI1 [3] XspiCLK1 13 11 15 13 17 15 19 17 12 14 14 16 16 18 18 20 XuRXD2/UART_AUDIO_RXD [3] XuRXD3/CTSn2/UART_AUDIO_CTSn [3] XspiMISO1 [3] XspiCS1 [3] D Xm0ADDR8 Xm0ADDR9 Xm0ADDR7 Xm0ADDR8 XvVDEN 21 19 XvVSYNC23 21 20 22 22 24 XvHSYNC XEINT10 [3] [3,11] Xi2cSCL0 [3] XmmcCLK0 21 19 23 21 20 22 22 24 Xi2cSDA0 [3,11] XmmcCMD0 [3] Xm0ADDR10 Xm0ADDR11 Xm0ADDR12 Xm0ADDR13 Xm0ADDR14 Xm0ADDR15 Xm0ADDR9 Xm0ADDR10 Xm0ADDR11 Xm0ADDR12 Xm0ADDR13 Xm0ADDR14 [3] XuoVBUS [3] XuoID [3] XuoDM [3] XuoDP XvVCLK 25 23 27 25 29 27 31 29 33 31 35 33 24 26 26 28 28 30 30 32 32 34 34 36 XpwmTOUT1 [3] XuoDRVVBUS [3] XEINT8 [3] XuhDM [3] XuhDP [3] [3] Xmmc0CDn [3] Xmmc0DATA0 [3] Xmmc0DATA2 25 23 27 25 29 27 [3] Audio_Xi2sSCLK0 31 29 [3] Audio_Xi2sLRCK0 [3] Audio_Xi2sSDI0 33 31 Xm0ADDR0 35 33 24 26 26 28 28 30 30 32 32 34 34 36 XEINT6_SD0_nWP [3] Xmmc0DATA1 [3] Xmmc0DATA3 [3] Audio_Xi2sCDCLK0 [3] Audio_Xi2sSDO0_0 [3] Xm0ADDR1 XEINT9 [3] Xm0ADDR15 [5] XadcAIN9_XP 37 35 36 38 XadcAIN8_XM [5] Xm0ADDR2 37 35 36 38 Xm0ADDR15 [5] XadcAIN7_YP 39 37 38 40 XadcAIN6_YM [5] 39 37 38 40 [4,7] Xm0DATA[15:0] Xm0DATA0 [5] XadcAIN0 [5] WIFI0_PD_GPIO 41 39 43 41 40 42 42 44 XadcAIN1 [5] WIFI0_RESET_GPIO [5] [4] Xm0CSn1 [4] Xm0WAITn 41 39 43 41 40 42 42 44 XEINT7 [3] XnRSTOUT [3] Xm0DATA1 Xm0DATA2 [3] Xmmc2CLK/SPI_CLK2 [3] Xmmc2CDn/SPI_MISO2 45 43 47 45 44 46 46 48 Xmmc2CMD/SPI_CSn2 [3] XEINT11 [3] [4] Xm0WEn Xm0DATA0 45 43 Xm0DATA2 47 45 44 46 Xm0DATA1 Xm0OEn [4] 46 48 Xm0DATA3 Xm0DATA3 [3] Xmmc2DATA0/SPI_MOSI2 49 47 48 50 Xmmc2DATA1 [3] Xm0DATA4 49 47 48 50 Xm0DATA5 Xm0DATA4 [3] Xmmc2DATA2 51 49 50 52 Xmmc2DATA3 [3] Xm0DATA6 51 49 50 52 Xm0DATA7 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 [5] XdacOUT [3] XEINT16/KP_COL0 [3] XEINT18/KP_COL2 [3] XEINT24/KP_ROW0 [3] XEINT26/KP_ROW2 53 51 55 53 57 55 59 57 59 52 54 54 56 56 58 58 60 60 XpwmTOUT0 [3] XEINT17/KP_COL1 [3] XEINT19/KP_COL3 [3] XEINT25/KP_ROW1 [3] XEINT27/KP_ROW3 [3] Xm0DATA8 53 51 Xm0DATA1055 53 Xm0DATA1257 55 Xm0DATA1459 57 59 52 54 54 56 56 58 58 60 60 Xm0DATA9 Xm0DATA11 Xm0DATA13 Xm0DATA15 Xm0DATA10 Xm0DATA11 J2x25 2.0mm J2x25 2.0mm Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15 [5] XvVD[23:0] XvVD0 XvVD1 XvVD2 XvVD3 XvVD4 XvVD5 C XvVD6 XvVD7 LCD总总 XvVD8 XvVD9 XvVD10 XvVD11 XvVD12 XvVD13 XvVD14 XvVD15 XvVD16 XvVD17 XvVD18 XvVD19 XvVD20 XvVD21 XvVD22 XvVD23 [5] XvVCLK [5] XvVSYNC [5] XvHSYNC [5] XvVDEN XvVCLK XvVSYNC XvHSYNC XvVDEN C [3] XEINT13/HDMI_HPD R179 2K DGND [3,11] Xi2cSDA0 [5] XciFIELD [5] CAMERA_A_GPIO2 R175 0R/NC R176 0R [5] XciCLKenb [5] XciVSYNC [5] XciYDATA7 [5] XciYDATA5 [5] XciYDATA3 [5] XciYDATA1 VDD_SYS_3.3V VDD_CAM_1.8V [3] Xi2cSDA2/IEM_SCLK [3] Xi2cSCL2/IEM_SPWI XvVD0 XvVD8 XvVD16 CON2 1 2 31 24 53 46 75 68 97 8 10 11 9 10 12 13 11 12 14 15 13 14 16 17 15 16 18 19 17 18 20 21 19 20 22 23 25 21 22 2J32X10 24 24 26 27 25 26 28 29 27 28 30 29 30 Xi2cSCL0 [3,11] CAM_A_RESET [5] XciHREF [5] XciPCLK [5] XciYDATA6 [5] XciYDATA4 [5] XciYDATA2 [5] XciYDATA0 [5] VDD_CAM_2.8V DGND XEINT15 [3] XvVD1 XEINT14 [3] XvVD9 XvVD17 改改改改改,也也2.0mm间间间IDC连连连 B LED x 4 [5] LED1 [5] LED2 [5] LED3 [5] LED4 LED1 LED LED2 LED LED3 LED LED4 LED R180 1K VDD_SYS_3.3V R185 1K VDD_SYS_3.3V R190 1K VDD_SYS_3.3V R191 1K VDD_SYS_3.3V A 5 4 VDD_SYS_3.3V XjTRSTn XjTMS XjTCK XjTDI XjTDO DGND JTAG 1 21 32 43 54 65 76 7 HEADER 7 3 B VDD_SYS_3.3V C188 104 R134 C218 10K 10uF/6.3V DGND R133 10K/nc 5 VIN 4 3 EN1 EN2 U12 6 VOUT1 1 VOUT2 2 GND RT9011-MGPJ6 VDD_CAM_2.8V VDD_CAM_1.8V C187 104 C217 DGND 4.7uF/6.3V C186 104 C216 4.7uF/6.3V [5] CAMERA_A_GPIO1 DGND DGND DGND DGND DGND A Title Tiny210 Size A2 Document Number Rev Date: Wednesday, September 25, 2013 Sheet 11 of 11 2 1

    Top_arrow
    回到顶部
    EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。