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    Intel® Pentium® Dual-Core Desktop Processor E2000Δ Series Datasheet December 2007 Document Number: 316981-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. The Intel® Pentium® Dual-Core Desktop processor E2000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information.” Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel SpeedStep, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007 Intel Corporation. 2 Datasheet Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology ............................................................................ 10 1.2 References ....................................................................................................... 11 2 Electrical Specifications ........................................................................................... 13 2.1 Power and Ground Lands.................................................................................... 13 2.2 Decoupling Guidelines ........................................................................................ 13 2.2.1 VCC Decoupling ..................................................................................... 13 2.2.2 Vtt Decoupling ....................................................................................... 13 2.2.3 FSB Decoupling...................................................................................... 14 2.3 Voltage Identification ......................................................................................... 14 2.4 Market Segment Identification (MSID) ................................................................. 16 2.5 Reserved, Unused, and TESTHI Signals ................................................................ 16 2.6 Voltage and Current Specification ........................................................................ 17 2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17 2.6.2 DC Voltage and Current Specification ........................................................ 19 2.6.3 Vcc Overshoot ....................................................................................... 21 2.6.4 Die Voltage Validation ............................................................................. 22 2.7 Signaling Specifications...................................................................................... 22 2.7.1 FSB Signal Groups.................................................................................. 23 2.7.2 CMOS and Open Drain Signals ................................................................. 24 2.7.3 Processor DC Specifications ..................................................................... 25 2.7.3.1 GTL+ Front Side Bus Specifications ............................................. 26 2.8 Clock Specifications ........................................................................................... 28 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 28 2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 28 2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 29 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 29 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 31 2.9 PECI DC Specifications ....................................................................................... 32 3 Package Mechanical Specifications .......................................................................... 33 3.1 Package Mechanical Drawing............................................................................... 33 3.2 Processor Component Keep-Out Zones ................................................................. 37 3.3 Package Loading Specifications ........................................................................... 37 3.4 Package Handling Guidelines............................................................................... 37 3.5 Package Insertion Specifications.......................................................................... 38 3.6 Processor Mass Specification ............................................................................... 38 3.7 Processor Materials............................................................................................ 38 3.8 Processor Markings............................................................................................ 38 3.9 Processor Land Coordinates ................................................................................ 39 4 Land Listing and Signal Descriptions ....................................................................... 41 4.1 Processor Land Assignments ............................................................................... 41 4.2 Alphabetical Signals Reference ............................................................................ 64 5 Thermal Specifications and Design Considerations .................................................. 73 5.1 Processor Thermal Specifications ......................................................................... 73 5.1.1 Thermal Specifications ............................................................................ 73 5.1.2 Thermal Metrology ................................................................................. 77 5.2 Processor Thermal Features ................................................................................ 77 5.2.1 Thermal Monitor..................................................................................... 77 Datasheet 3 5.2.2 Thermal Monitor 2 ..................................................................................78 5.2.3 On-Demand Mode ...................................................................................79 5.2.4 PROCHOT# Signal ..................................................................................80 5.2.5 THERMTRIP# Signal ................................................................................80 5.3 Thermal Diode...................................................................................................81 5.4 Platform Environment Control Interface (PECI) ......................................................83 5.4.1 Introduction ...........................................................................................83 5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management .......83 5.4.2 PECI Specifications .................................................................................85 5.4.2.1 PECI Device Address..................................................................85 5.4.2.2 PECI Command Support .............................................................85 5.4.2.3 PECI Fault Handling Requirements ...............................................85 5.4.2.4 PECI GetTemp0() Error Code Support ..........................................85 6 Features ..................................................................................................................87 6.1 Power-On Configuration Options ..........................................................................87 6.2 Clock Control and Low Power States .....................................................................88 6.2.1 Normal State .........................................................................................88 6.2.2 HALT and Extended HALT Powerdown States ..............................................88 6.2.2.1 HALT Powerdown State ..............................................................89 6.2.2.2 Extended HALT Powerdown State ................................................89 6.2.3 Stop Grant and Extended Stop Grant States ...............................................89 6.2.3.1 Stop-Grant State.......................................................................90 6.2.3.2 Extended Stop Grant State .........................................................90 6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State..................................................90 6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................90 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State.......91 6.3 Enhanced Intel SpeedStep® Technology ...............................................................91 7 Boxed Processor Specifications................................................................................93 7.1 Mechanical Specifications ....................................................................................94 7.1.1 Boxed Processor Cooling Solution Dimensions.............................................94 7.1.2 Boxed Processor Fan Heatsink Weight .......................................................96 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....96 7.2 Electrical Requirements ......................................................................................96 7.2.1 Fan Heatsink Power Supply ......................................................................96 7.3 Thermal Specifications........................................................................................98 7.3.1 Boxed Processor Cooling Requirements......................................................98 7.3.2 Fan Speed Control Operation (Intel® Pentium® Dual-Core Desktop Processor E2000 Series) ........................................................................ 100 8 Debug Tools Specifications .................................................................................... 103 8.1 Logic Analyzer Interface (LAI) ........................................................................... 103 8.1.1 Mechanical Considerations ..................................................................... 103 8.1.2 Electrical Considerations ........................................................................ 103 4 Datasheet Figures 1 VCC Static and Transient Tolerance for Processors......................................................... 21 2 VCC Overshoot Example Waveform ............................................................................. 22 3 Differential Clock Waveform ...................................................................................... 30 4 Differential Clock Crosspoint Specification ................................................................... 30 5 Differential Measurements......................................................................................... 30 6 Differential Clock Crosspoint Specification ................................................................... 31 7 Processor Package Assembly Sketch ........................................................................... 33 8 Processor Package Drawing Sheet 1 of 3 ..................................................................... 34 9 Processor Package Drawing Sheet 2 of 3 ..................................................................... 35 10 Processor Package Drawing Sheet 3 of 3 ..................................................................... 36 11 Processor Top-Side Markings Example ........................................................................ 38 12 Processor Land Coordinates and Quadrants, Top View ................................................... 39 13 land-out Diagram (Top View – Left Side) ..................................................................... 42 14 land-out Diagram (Top View – Right Side) ................................................................... 43 15 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h).................. 75 16 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) ................. 76 17 Case Temperature (TC) Measurement Location ............................................................ 77 18 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 79 19 Processor PECI Topology ........................................................................................... 83 20 Conceptual Fan Control on PECI-Based Platforms ......................................................... 84 21 Conceptual Fan Control on Thermal Diode-Based Platforms............................................ 84 22 Processor Low Power State Machine ........................................................................... 88 23 Mechanical Representation of the Boxed Processor ....................................................... 93 24 Space Requirements for the Boxed Processor (Side View).............................................. 94 25 Space Requirements for the Boxed Processor (Top View)............................................... 95 26 Space Requirements for the Boxed Processor (Overall View) .......................................... 95 27 Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 97 28 Baseboard Power Header Placement Relative to Processor Socket ................................... 98 29 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................... 99 30 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 99 31 Boxed Processor Fan Heatsink Set Points................................................................... 100 Datasheet 5 Tables 1 References ..............................................................................................................11 2 Voltage Identification Definition ..................................................................................15 3 Market Segment Selection Truth Table for MSID[1:0], , , ..............................................16 4 Absolute Maximum and Minimum Ratings ....................................................................18 5 Voltage and Current Specifications..............................................................................19 6 VCC Static and Transient Tolerance for Processors .........................................................20 7 VCC Overshoot Specifications......................................................................................21 8 FSB Signal Groups ....................................................................................................23 9 Signal Characteristics................................................................................................24 10 Signal Reference Voltages .........................................................................................24 11 GTL+ Signal Group DC Specifications ..........................................................................25 12 Open Drain and TAP Output Signal Group DC Specifications ...........................................25 13 CMOS Signal Group DC Specifications..........................................................................26 14 GTL+ Bus Voltage Definitions .....................................................................................27 15 Core Frequency to FSB Multiplier Configuration.............................................................28 16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................29 17 Front Side Bus Differential BCLK Specifications .............................................................29 18 Front Side Bus Differential BCLK Specifications .............................................................31 19 PECI DC Electrical Limits ...........................................................................................32 20 Processor Loading Specifications.................................................................................37 21 Package Handling Guidelines......................................................................................37 22 Processor Materials ...................................................................................................38 23 Alphabetical Land Assignments...................................................................................44 24 Numerical Land Assignment .......................................................................................54 25 Signal Description.....................................................................................................64 26 Processor Thermal Specifications ................................................................................74 27 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h) ..................75 28 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) ..................76 29 Thermal “Diode” Parameters using Diode Model ............................................................81 30 Thermal “Diode” Parameters using Transistor Model ......................................................82 31 Thermal Diode Interface ............................................................................................82 32 GetTemp0() Error Codes ...........................................................................................85 33 Power-On Configuration Option Signals .......................................................................87 34 Fan Heatsink Power and Signal Specifications ...............................................................97 35 Fan Heatsink Power and Signal Specifications ............................................................. 101 6 Datasheet Intel® Pentium® Dual-Core Desktop Processor E2000Δ Series • Available at 2.2 GHz, 2.0 GHz, 1.80 GHz, and 1.60 GHz • Enhanced Intel SpeedStep® Technology • Supports Intel® 64 architecture • Supports Execute Disable Bit capability • Binary compatible with applications running on previous members of the Intel microprocessor line • FSB frequency at 800 MHz • Advance Dynamic Execution • Very deep out-of-order execution • Enhanced branch prediction • Optimized for 32-bit applications running on advanced 32-bit operating systems • Two 32-KB Level 1 data caches • 1 MB Advanced Smart Cache • Advanced Digital Media Boost • Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance • Power Management capabilities • System Management mode • Multiple low-power states • 8-way cache associativity provides improved cache hit rate on load/store operations • 775-land Package The Intel Pentium® Dual-Core desktop processor E2000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep® technology allows tradeoffs to be made between performance and power consumption. The Intel Pentium® Dual-Core desktop processor E2000 series also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. §§ Datasheet 7 Revision History Revision Number -001 -002 -003 -004 Description • Initial release • Added specifications for Intel® Pentium® Dual-Core Desktop processor E2180 • Added specifications for Intel® Pentium® Dual-Core Desktop processor E2160 and E2140 for a second thermal profile (See Table 26) • Added specifications for Intel® Pentium® Dual-Core Desktop processor E2200 Date June 2007 August 2007 September 2007 December 2007 §§ 8 Datasheet Introduction 1 Note: Note: 1.1 Introduction The Intel® Pentium® Dual-Core Desktop processor E2000 series combines the performance of the current generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These dual-core processors are based on 65 nm process technology. They are 64-bit processors that maintain compatibility with IA-32 software. The Intel® Pentium® Dual-Core Desktop processor E2000 series uses Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. In this document, unless otherwise specified, the Intel® Pentium® Dual-Core Desktop processor E2000 series refers to Intel® Pentium® Dual-Core Desktop processor E2200, E2180, E2160, and E2140. In this document, unless otherwise specified, the Intel® Pentium® Dual-Core Desktop processor E2000 series is referred to as “processor.” The processor supports advanced technologies including Execute Disable Bit, Intel® 64 architecture, and Enhanced Intel SpeedStep® technology. The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s. Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor. Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. Datasheet 9 Introduction 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: • Intel® Pentium® Dual-Core Desktop processor E2000 series — Dual core processor in the FC-LGA6 package with a 1 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel® Pentium® Dual-Core Desktop processor E2000 series. The processor is a single package that contains one or more execution units. • Keep-out zone — The area on or near the processor that system design can not use. • Processor core — Processor core die with integrated L2 cache. • LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket. • Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. • Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. • FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. • Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. • Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied. • Execute Disable Bit — The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. • Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/ 64bitextensions/. • Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). 10 Datasheet Introduction 1.2 Table 1. References Material and concepts available in the following documents may be beneficial when reading this document. References Document Location Intel® Pentium® Dual-Core Desktop Processor E2000 Series Specification Update Intel® Core™2 Duo Processor and Intel® Pentium® Dual Core Thermal and Mechanical Design Guidelines Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, Intel® Pentium® 4 Processor, and Intel® Core™2 Duo Extreme Processor Thermal and Mechanical Design Guidelines. Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket LGA775 Socket Mechanical Design Guide Intel® 64 and IA-32 Architecture Software Developer’s Manuals Intel® 64 and IA-32 Architecture Software Developer’s Manual Volume 1: Basic Architecture Intel® 64 and IA-32 Architecture Software Developer’s Manual Volume 2A: Instruction Set Reference Manual A–M Intel® 64 and IA-32 Architecture Software Developer’s Manual Volume 2B: Instruction Set Reference Manual, N–Z Intel® 64 and IA-32 Architecture Software Developer’s Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 Architecture Software Developer’s Manual Volume 3B: System Programming Guide http://www.intel.com// design/processor/ specupdt/316982.htm http://www.intel.com/ design/processor/ designex/317804.htm http://www.intel.com/ design/pentiumXE/ designex/306830.htm http://www.intel.com/ design/processor/ applnots/313214.htm http://intel.com/ design/Pentium4/ guides/302666.htm http://www.intel.com/ products/processor/ manuals/ §§ Datasheet 11 Introduction 12 Datasheet Electrical Specifications 2 Electrical Specifications 2.1 2.2 2.2.1 2.2.2 This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component. VCC Decoupling VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information. VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. Datasheet 13 Electrical Specifications 2.2.3 2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. Voltage Identification The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Section 2.6.3 for VCC overshoot specifications). Refer to Table 13 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 5. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 5. Refer to the Intel® Pentium® Dual-Core Desktop Processor E2000 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Enhanced HALT State). The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to VSS on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 5 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 5 and Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details. 14 Datasheet Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 0 1 0.8500 1 1 1 1 0 0 0.8625 1 1 1 0 1 1 0.8750 1 1 1 0 1 0 0.8875 1 1 1 0 0 1 0.9000 1 1 1 0 0 0 0.9125 1 1 0 1 1 1 0.9250 1 1 0 1 1 0 0.9375 1 1 0 1 0 1 0.9500 1 1 0 1 0 0 0.9625 1 1 0 0 1 1 0.9750 1 1 0 0 1 0 0.9875 1 1 0 0 0 1 1.0000 1 1 0 0 0 0 1.0125 1 0 1 1 1 1 1.0250 1 0 1 1 1 0 1.0375 1 0 1 1 0 1 1.0500 1 0 1 1 0 0 1.0625 1 0 1 0 1 1 1.0750 1 0 1 0 1 0 1.0875 1 0 1 0 0 1 1.1000 1 0 1 0 0 0 1.1125 1 0 0 1 1 1 1.1250 1 0 0 1 1 0 1.1375 1 0 0 1 0 1 1.1500 1 0 0 1 0 0 1.1625 1 0 0 0 1 1 1.1750 1 0 0 0 1 0 1.1875 1 0 0 0 0 1 1.2000 1 0 0 0 0 0 1.2125 0 1 1 1 1 1 1.2250 VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 0 1 1 1 1 0 1.2375 0 1 1 1 0 1 1.2500 0 1 1 1 0 0 1.2625 0 1 1 0 1 1 1.2750 0 1 1 0 1 0 1.2875 0 1 1 0 0 1 1.3000 0 1 1 0 0 0 1.3125 0 1 0 1 1 1 1.3250 0 1 0 1 1 0 1.3375 0 1 0 1 0 1 1.3500 0 1 0 1 0 0 1.3625 0 1 0 0 1 1 1.3750 0 1 0 0 1 0 1.3875 0 1 0 0 0 1 1.4000 0 1 0 0 0 0 1.4125 0 0 1 1 1 1 1.4250 0 0 1 1 1 0 1.4375 0 0 1 1 0 1 1.4500 0 0 1 1 0 0 1.4625 0 0 1 0 1 1 1.4750 0 0 1 0 1 0 1.4875 0 0 1 0 0 1 1.5000 0 0 1 0 0 0 1.5125 0 0 0 1 1 1 1.5250 0 0 0 1 1 0 1.5375 0 0 0 1 0 1 1.5500 0 0 0 1 0 0 1.5625 0 0 0 0 1 1 1.5750 0 0 0 0 1 0 1.5875 0 0 0 0 0 1 1.6000 0 0 0 0 0 0 OFF Datasheet 15 Electrical Specifications 2.4 Table 3. 2.5 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Market Segment Selection Truth Table for MSID[1:0]1, 2, 3, 4 MSID1 MSID0 Description 0 0 Intel® Pentium® Dual-Core Desktop processor E2000 series 0 1 Reserved 1 0 Reserved 1 1 Reserved NOTES: 1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed. 2. These signals are not connected to the processor die. 3. A logic 0 is achieved by pulling the signal to ground on the package. 4. A logic 1 is achieved by leaving the signal as a no connect on the package. Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details, see Table 14. TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor that matches the nominal trace impedance. 16 Datasheet Electrical Specifications 2.6 2.6.1 The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI8/FC42 – cannot be grouped with other TESTHI signals • TESTHI9/FC43 – cannot be grouped with other TESTHI signals • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI12/FC44 – cannot be grouped with other TESTHI signals • TESTHI13 – cannot be grouped with other TESTHI signals However, use of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used. Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Datasheet 17 Electrical Specifications Table 4. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC VTT TC TSTORAGE Core voltage with respect to VSS FSB termination voltage with respect to VSS Processor case temperature Processor storage temperature –0.3 1.55 V –0.3 1.55 V See See Chapter 5 Chapter 5 °C –40 85 °C 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long term reliability of the processor. 18 Datasheet Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 5. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes1, 2 VID Range VCC VID Processor Number E2200 E2180 E2160 E2140 VCC for 775_VR_CONFIG_06 2.2 GHz 2.0 GHz 1.8 GHz 1.6 GHz 0.8500 — 1.5 Refer to Table 6 and Table 1 V 3 V 4, 5, 6 VCC_BOOT VCCPLL ICC Default VCC voltage for initial power up — 1.10 — V PLL VCC - 5% 1.50 + 5% Processor Number VCC for 775_VR_CONFIG_06 E2200 E2180 2.2 GHz 2.0 GHz 75 — — 75 A 7 E2160 1.8 GHz 75 E2140 1.6 GHz 75 FSB termination voltage VTT (DC + AC specifications) 1.14 1.20 1.26 V 8 VTT_OUT_LEFT and DC Current that may be drawn from VTT_OUT_RIGHT VTT_OUT_LEFT and VTT_OUT_RIGHT per — — 580 mA 9 ICC pin ITT ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable 4.5 — — A 10 4.6 ICC_VCCPLL ICC for PLL land — — 130 mA ICC_GTLREF ICC for GTLREF — — 200 μA NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® technology, or Extended HALT State). 4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. 7. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details. 8. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. 9. Baseboard bandwidth is limited to 20 MHz. 10.This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. Datasheet 19 Electrical Specifications Table 6. VCC Static and Transient Tolerance for Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.425 mΩ Minimum Voltage 1.55 mΩ 0 0.000 5 -0.007 10 -0.013 -0.019 -0.026 -0.033 -0.038 -0.046 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 40 -0.052 45 -0.059 50 -0.065 55 -0.072 -0.069 -0.076 -0.083 -0.090 -0.097 -0.092 -0.100 -0.108 -0.116 -0.123 60 -0.078 -0.105 -0.131 65 -0.085 -0.112 -0.139 70 -0.091 -0.119 -0.147 75 -0.098 -0.126 -0.154 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This table is intended to aid in reading discrete points on Figure 1. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation. 20 Datasheet Electrical Specifications Figure 1. VCC Static and Transient Tolerance for Processors ICC (A) 0 10 20 30 40 50 60 70 VID – 0.000 VID – 0.013 VCC (V) VID – 0.025 VID – 0.038 VID – 0.050 VID – 0.063 VID – 0.075 VID – 0.088 VID – 0.100 VID – 0.113 VID – 0.125 VID – 0.138 VID – 0.150 VID – 0.163 VCC Typical VCC Minimum VCC Maximum 2.6.3 Table 7. NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. VCC Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes VOS_MAX Magnitude of VCC overshoot above VID — 50 mV 2 1 TOS_MAX Time duration of VCC overshoot above VID — 25 μs 2 1 NOTES: 1. Adherence to these specifications is required to ensure reliable processor operation. Datasheet 21 Electrical Specifications Figure 2. VCC Overshoot Example Waveform VID + 0.050 Example Overshoot Waveform VOS Voltage [V] VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID 2.6.4 2.7 NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. 22 Datasheet Electrical Specifications 2.7.1 Table 8. FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 8 identifies which signals are common clock, source synchronous, and asynchronous. FSB Signal Groups Signal Group Type Signals1 GTL+ Common Clock Input GTL+ Common Clock I/O Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK# GTL+ Source Synchronous to Synchronous I/O assoc. strobe Signals REQ[4:0]#, A[16:3]#3 A[35:17]#3 D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# GTL+ Strobes CMOS Open Drain Output Open Drain Input/Output FSB Clock Power/Other Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:0], VID[6:1] FERR#/PBE#, IERR#, THERMTRIP#, TDO Clock PROCHOT#4 BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0] NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. Datasheet 23 Electrical Specifications . Table 9. . Table 10. 2.7.2 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. 4. PROCHOT# signal type is open drain output and CMOS input. Signal Characteristics Signals with RTT A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY# Open Drain Signals1 Signals with No RTT A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SMI#, STPCLK#, TESTHI[13:0], VID[6:1], GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL, MSID[1:0] THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, FCx NOTES: 1. Signals that do not have RTT, nor are actively driven to their high-voltage level. Signal Reference Voltages GTLREF VTT/2 BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY# A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1 NOTES: 1. These signals also have hysteresis added to the reference voltage. See Table 12 for more information. CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 24 Datasheet Electrical Specifications 2.7.3 Table 11. . Table 12. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage VIH Input High Voltage VOH Output High Voltage -0.10 GTLREF + 0.10 VTT – 0.10 GTLREF – 0.10 VTT + 0.10 VTT V 2, 3 V 4, 5, 3 V 5, 3 IOL Output Low Current ILI Input Leakage Current ILO Output Leakage Current N/A N/A N/A VTT_MAX/ [(RTT_MIN)+(2*RON_MIN)] A - ± 100 µA 6 ± 100 µA 7 RON Buffer On Resistance 10 13 Ω NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VTT referred to in these specifications is the instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 6. Leakage to VSS with land held at VTT. 7. Leakage to VTT with land held at 300 mV Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VOL Output Low Voltage 0 0.20 V - VOH Output High Voltage VTT – 0.05 VTT + 0.05 V 2 IOL Output Low Current 16 50 mA 3 ILO Output Leakage Current N/A ± 200 µA 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VOH is determined by the value of the external pull-up resister to VTT. 3. Measured at VTT * 0.2. 4. For Vin between 0 and VOH Datasheet 25 Electrical Specifications . Table 13. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 3 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 6, 5, 3 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.70 mA 3, 7 ILI Input Leakage Current N/A ± 100 µA 8 ILO Output Leakage Current N/A ± 100 µA 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VTT referred to in these specifications refers to instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 6. All outputs are open drain. 7. IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT. 8. Leakage to VSS with land held at VTT. 9. Leakage to VTT with land held at 300 mV. 2.7.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 9 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. 26 Datasheet Electrical Specifications Table 14. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF pull up resistor on GTLREF_PU Intel 975X and 96x Express 124 * 0.99 124 124 * 1.01 Ω 2 Chipset family boards GTLREF pull down resistor GTLREF_PD on Intel 975X and 96x Express Chipset family 210 * 0.99 210 210 * 1.01 Ω 2 boards GTLREF pull up resistor on GTLREF_PU Intel Series 3 Express 100 * 0.99 100 100 * 1.01 Ω 2 Chipset family boards GTLREF pull down resistor GTLREF_PD on Intel Series 3 Express 200 * 0.99 200 200 * 1.01 Ω 2 Chipset family boards RTT Termination Resistance COMP[3:0] COMP Resistance 45 50 55 Ω 3 49.40 49.90 50.40 Ω 4 COMP8 COMP Resistance 24.65 24.90 25.15 Ω 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land). 3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver. 4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and COMP8 resistors are to VSS. Datasheet 27 Electrical Specifications 2.8 Clock Specifications 2.8.1 Table 15. 2.8.2 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Platforms using a CK505 Clock Synthesizer/Driver should comply with the specifications in Section 2.8.4. Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications in Section 2.8.5. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (200 MHz BCLK/800 MHz FSB) Notes1, 2 1/6 1.20 GHz - 1/7 1.40 GHz - 1/8 1.60 GHz - 1/9 1.80 GHz - 1/10 2 GHz - 1/11 2.2 GHz - 1/12 2.4 GHz - NOTES: 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel Pentium Dual-Core Desktop processor E2000 series operates at a 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). 28 Datasheet Electrical Specifications Table 16. 2.8.3 2.8.4 BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency RESERVED RESERVED RESERVED 200 MHz RESERVED RESERVED RESERVED RESERVED Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. BCLK[1:0] Specifications (CK505 based Platforms) Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter VL VH VCROSS(abs) ΔVCROSS VOS VUS VSWING ILI Cpad Input Low Voltage Input High Voltage Absolute Crossing Point Range of Crossing Points Overshoot Undershoot Differential Output Swing Input Leakage Current Pad Capacitance Min -0.30 N/A 0.300 N/A N/A -0.300 0.300 -5 .95 Typ N/A N/A N/A N/A N/A N/A N/A N/A 1.2 Max N/A 1.15 0.550 0.140 1.4 N/A N/A 5 1.45 Unit V V V V V V V μA pF Figure 3 3 3, 4 3, 4 3 3 5 Notes1 2 2 3,4 5 4 6 6 7 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. "Steady state" voltage, not including overshoot or undershoot. 3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 4. VHavg is the statistical average of the VH measured by the oscilloscope. 5. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. 7. Measurement taken from differential waveform. 8. Cpad includes die capacitance only. No package parasitics are included. Datasheet 29 Electrical Specifications Figure 3. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS V median CROSS Median - 75 mV CLK 1 VCROSS Max 550 mV VCROSS Min 300 mV High Time Low Time Period VCROSS median Figure 4. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 300 + 0.5 (VHavg - 700) 350 300 300 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5. Differential Measurements +150 mV 0.0 V -150 mV Diff Sl ew_ris e V_swing Slew _fall +150 mV 0.0V - 150 mV 30 Datasheet Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.00 0 N/A V 3 - VH Input High Voltage 0.660 0.70 0 0.850 V 3 - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 3, 4 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg – 0.700) N/A 0.550 + 0.5(VHavg – 0.700) V 3, 4 4, 3, 5 ΔVCROSS Range of Crossing Points N/A N/A 0.140 V 3, 4 - VOS Overshoot N/A N/A VH + 0.3 V 3 6 VUS Undershoot -0.300 N/A N/A V 3 7 VRBM Ringback Margin 0.200 N/A N/A V 3 8 VTM Threshold Region VCROSS – 0.100 N/A VCROSS + 0.100 V 3 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 4. VHavg is the statistical average of the VH measured by the oscilloscope. 5. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes. 6. vershoot is defined as the absolute value of the maximum voltage. 7. Undershoot is defined as the absolute value of the minimum voltage. 8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. Figure 6. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Datasheet 31 Electrical Specifications 2.9 Table 19. PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment Control Interface (PECI) Specification. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range Vhysteresis Hysteresis -0.15 VTT 0.1 * VTT — V V 2 Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.762 * VTT V Isource High level output source (VOH = 0.75 * VTT) -6.0 N/A mA Low level output sink Isink (VOL = 0.25 * VTT) 0.5 Ileak+ High impedance state leakage to VTT N/A Ileak- High impedance leakage to GND N/A Cbus Bus capacitance per node N/A 1.0 mA 50 µA 3 10 µA 3 10 pF 4 Vnoise Signal noise immunity above 300 MHz 0.1 * VTT — Vp-p NOTES: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 4 for VTT specifications. 2. The input buffers use a Schmitt-triggered input design for improved noise immunity. 3. The leakage specification applies to powered devices on the PECI bus. 4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. §§ 32 Datasheet Package Mechanical Specifications 3 Package Mechanical Specifications Figure 7. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 7 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket. The package components shown in Figure 7 include the following: • Integrated Heat Spreader (IHS) • Thermal Interface Material (TIM) • Processor core (die) • Package substrate • Capacitors Processor Package Assembly Sketch Core (die) TIM IHS Substrate 3.1 System Board Capacitors LGA775 Socket Processor_Pkg_Assembly_775 NOTE: 1. Socket and system board are included for reference and are not part of processor package. Package Mechanical Drawing The package mechanical drawings are shown in Figure 8 and Figure 9. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • Package reference with tolerances (total height, length, width, etc.) • IHS parallelism and tilt • Land dimensions • Top-side and back-side component keep-out dimensions • Reference datums • All drawing dimensions are in mm [in]. • Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines (see Section 1.2). Datasheet 33 Figure 8. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 34 Datasheet Package Mechanical Specifications Figure 9. Processor Package Drawing Sheet 2 of 3 Datasheet 35 Figure 10. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 36 Datasheet Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. 3.3 . Table 20. 3.4 Table 21. Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions. Processor Loading Specifications Parameter Minimum Maximum Notes Static Dynamic 80 N [17 lbf] — 311 N [70 lbf] 756 N [170 lbf] 1, 2, 3 1, 3, 4 NOTES: 1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS. 2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N [70 lbf] 1, 2 Tensile 111 N [25 lbf] 2, 3 Torque 3.95 N-m [35 lbf-in] 2, 4 NOTES: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface. 2. These guidelines are based on limited testing for design characterization. 3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface. 4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. Datasheet 37 Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Table 22. Processor Materials Table 22 lists some of the package components and associated materials. Processor Materials Component Integrated Heat Spreader (IHS) Substrate Substrate Lands Material Nickel Plated Copper Fiber Reinforced Resin Gold Plated Copper 3.8 Processor Markings Figure 11. Figure 11 shows the topside markings on the processors. This diagram aids in the identification of the processor. Processor Top-Side Markings Example INTEL M ©'05 E2160 PENTIUM® DUAL-CORE SLxxx [COO] 1.80GHZ/1M/800/06 [FPO] e4 ATPO S/N 38 Datasheet Package Mechanical Specifications 3.9 Processor Land Coordinates . Figure 12. Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V /V CC SS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y Preliminary W V Socket 775 U T Quadrants R P Top View N M L K J H G F E D C B A 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V / Clocks TT Data AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W Address/ V U Common Clock/ T Async R P N M L K J H G F E D C B A §§ Datasheet 39 Package Mechanical Specifications 40 Datasheet Land Listing and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 provides a list of processor lands ordered alphabetically by land (signal) name. Table 24 provides a list of processor lands ordered by land number. Datasheet 41 Land Listing and Signal Descriptions Figure 13. land-out Diagram (Top View – Left Side) 30 29 28 27 26 25 24 23 22 21 20 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS AM VCC AL VCC AK VSS AJ VSS AH VCC AG VCC AF VSS AE VSS AD VCC AC VCC AB VSS AA VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS 19 VCC VCC VCC VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC VCC VCC VCC 17 VSS VSS VSS VSS VSS VSS VSS VSS VSS 16 VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 VCC VCC VCC VCC VCC VCC VCC VCC VCC Y VCC W VCC V VSS U VCC T VCC R VSS P VSS N VCC M VCC L VSS K VCC J VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VCC VCC VCC VCC FC34 FC31 VCC H BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32 G BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# F RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30# E FC26 VSS VSS VSS VSS FC10 RSVD D45# D42# VSS D40# D39# VSS D34# D33# D VTT VTT VTT VTT VTT VTT VSS VCCPLL D46# VSS D48# DBI2# VSS D49# RSVD VSS C VTT VTT VTT VTT VTT VTT VSS VCCIO PLL VSS D58# DBI3# VSS D54# DSTBP3# VSS D51# B VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53# A VTT VTT VTT VTT VTT VTT FC23 VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 42 Datasheet Land Listing and Signal Descriptions Figure 14. 14 13 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS land-out Diagram (Top View – Right Side) 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 8 7 6 5 VCC VID_SELE VSS_MB_ VCC_MB_ CT REGULATION REGULATION VCC VID7 FC40 VID6 VCC VSS VID3 VID1 VCC VSS FC8 VSS VCC VSS A35# A34# VCC VSS VSS A33# VCC VSS A29# A31# VCC VSS VSS A27# SKTOCC# VSS RSVD VSS VCC VSS A22# ADSTB1# VCC VSS VSS A25# VCC VSS A17# A24# VCC VSS VSS A23# VCC VSS A19# VSS VCC VSS A18# A16# VCC VCC VCC VSS VSS VSS VSS A10# VSS A14# A12# A9# VCC VSS ADSTB0# VSS VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS A4# VSS REQ2# VSS REQ3# RSVD RSVD A5# A3# VSS VCC VSS REQ4# REQ1# VSS VSS VSS TESTHI10 4 VSS_ SENSE VSS VID5 VID4 VSS A32# A30# A28# RSVD VSS RSVD A26# A21# A20# VSS A15# A13# A11# A8# VSS RSVD A7# A6# REQ0# VSS FC35 3 2 1 VCC_ SENSE VSS VSS VID2 VID0 VSS VRDSEL PROCHOT# THERMDA ITP_CLK0 VSS THERMDC ITP_CLK1 BPM0# BPM1# VSS RSVD VSS BPM5# BPM3# TRST# VSS BPM4# TDO FC18 VSS TCK FC36 BPM2# TDI VSS DBR# TMS FC37 IERR# VSS VSS FC39 VTT_OUT_ RIGHT FC17 VSS FC0 TESTHI1 TESTHI12/ FC44 MSID0 VSS RSVD MSID1 FC30 FC29 FC28 VSS FC4 COMP1 FERR#/ PBE# VSS COMP3 INIT# SMI# TESTHI11 VSS IGNNE# PWRGOOD STPCLK# THERMTRIP# VSS VSS TESTHI13 LINT1 A20M# VSS LINT0 FC22 FC3 VTT_OUT_ LEFT VSS GTLREF1 GTLREF0 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H D29# D28# VSS RSVD D27# DSTBN1# DBI1# FC38 VSS D26# D25# D24# D23# VSS DSTBP1# VSS D21# VSS D15# D22# D16# D18# D19# VSS BPRI# DEFER# D17# VSS D12# VSS RSVD D20# D52# VSS D14# D11# VSS FC38 DSTBN0# VSS RSVD FC21 RSVD VSS D3# PECI TESTHI9/ TESTHI8/ FC43 FC42 COMP2 FC27 G RS1# VSS BR0# FC5 F FC20 HITM# TRDY# VSS E VSS HIT# VSS ADS# RSVD D D1# C VSS LOCK# BNR# DRDY# VSS D50# 14 COMP8 COMP0 13 D13# VSS 12 VSS D9# 11 D10# DSTBP0# D8# VSS 10 9 VSS DBI0# 8 D6# D7# 7 D5# VSS 6 VSS D4# 5 D0# RS0# DBSY# VSS B D2# RS2# VSS A 4 3 2 1 Datasheet 43 Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction A3# A4# A5# A6# A7# L5 Source Synch Input/Output P6 Source Synch Input/Output M5 Source Synch Input/Output L4 Source Synch Input/Output M4 Source Synch Input/Output A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# ADSTB0# ADSTB1# BCLK0 BCLK1 R4 Source Synch Input/Output T5 Source Synch Input/Output U6 Source Synch Input/Output T4 Source Synch Input/Output U5 Source Synch Input/Output U4 Source Synch Input/Output V5 Source Synch Input/Output V4 Source Synch Input/Output W5 Source Synch Input/Output AB6 Source Synch Input/Output W6 Source Synch Input/Output Y6 Source Synch Input/Output Y4 Source Synch Input/Output K3 Asynch CMOS Input AA4 Source Synch Input/Output AD6 Source Synch Input/Output AA5 Source Synch Input/Output AB5 Source Synch Input/Output AC5 Source Synch Input/Output AB4 Source Synch Input/Output AF5 Source Synch Input/Output AF4 Source Synch Input/Output AG6 Source Synch Input/Output AG4 Source Synch Input/Output AG5 Source Synch Input/Output AH4 Source Synch Input/Output AH5 Source Synch Input/Output AJ5 Source Synch Input/Output AJ6 Source Synch Input/Output D2 Common Clock Input/Output R6 Source Synch Input/Output AD5 Source Synch Input/Output F28 Clock Input G28 Clock Input Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction BNR# BPM0# BPM1# BPM2# BPM3# C2 Common Clock Input/Output AJ2 Common Clock Input/Output AJ1 Common Clock Input/Output AD2 Common Clock Input/Output AG2 Common Clock Input/Output BPM4# BPM5# BPRI# BR0# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 COMP8 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# AF2 Common Clock Input/Output AG3 Common Clock Input/Output G8 Common Clock Input F3 Common Clock Input/Output G29 Power/Other Output H30 Power/Other Output G30 Power/Other Output A13 Power/Other Input T1 Power/Other Input G2 Power/Other Input R1 Power/Other Input B13 Power/Other Input B4 Source Synch Input/Output C5 Source Synch Input/Output A4 Source Synch Input/Output C6 Source Synch Input/Output A5 Source Synch Input/Output B6 Source Synch Input/Output B7 Source Synch Input/Output A7 Source Synch Input/Output A10 Source Synch Input/Output A11 Source Synch Input/Output B10 Source Synch Input/Output C11 Source Synch Input/Output D8 Source Synch Input/Output B12 Source Synch Input/Output C12 Source Synch Input/Output D11 Source Synch Input/Output G9 Source Synch Input/Output F8 Source Synch Input/Output F9 Source Synch Input/Output E9 Source Synch Input/Output D7 Source Synch Input/Output E10 Source Synch Input/Output 44 Datasheet Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D10 F11 F12 D13 E13 G13 F14 G14 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC0 FC3 FC4 FC5 FC8 FC10 FC15 FC17 FC18 FC20 FC21 FC22 FC23 FC26 FC27 FC28 FC29 FC30 FC31 FC32 A19 Source Synch Input/Output A22 Source Synch Input/Output B22 Source Synch Input/Output A8 Source Synch Input/Output G11 Source Synch Input/Output D19 Source Synch Input/Output C20 Source Synch Input/Output AC2 Power/Other Output B2 Common Clock Input/Output G7 Common Clock Input C1 Common Clock Input/Output C8 Source Synch Input/Output G12 Source Synch Input/Output G20 Source Synch Input/Output A16 Source Synch Input/Output B9 Source Synch Input/Output E12 Source Synch Input/Output G19 Source Synch Input/Output C17 Source Synch Input/Output Y1 Power/Other J2 Power/Other T2 Power/Other F2 Power/Other AK6 Power/Other E24 Power/Other H29 Power/Other Y3 Power/Other AE3 Power/Other E5 Power/Other F6 Power/Other J3 Power/Other A24 Power/Other E29 Power/Other G1 Power/Other U1 Power/Other U2 Power/Other U3 Power/Other J16 Power/Other H15 Power/Other Datasheet 45 Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC33 FC34 FC35 FC36 FC37 H16 J17 H4 AD3 AB3 Power/Other Power/Other Power/Other Power/Other Power/Other FC38 FC38 FC39 FC40 FERR#/PBE# GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK# MSID0 MSID1 PECI PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED G10 Power/Other C9 Power/Other AA2 Power/Other AM6 Power/Other R3 Asynch CMOS Output H1 Power/Other Input H2 Power/Other Input D4 Common Clock Input/Output E4 Common Clock Input/Output AB2 Asynch CMOS Output N2 Asynch CMOS Input P3 Asynch CMOS Input AK3 TAP Input AJ3 TAP Input K1 Asynch CMOS Input L1 Asynch CMOS Input C3 Common Clock Input/Output W1 Power/Other Output V1 Power/Other Output G5 Power/Other Input/Output AL2 Asynch CMOS Input/Output N1 Power/Other Input K4 Source Synch Input/Output J5 Source Synch Input/Output M6 Source Synch Input/Output K6 Source Synch Input/Output J6 Source Synch Input/Output A20 AC4 AE4 AE6 AH2 D1 D14 Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction RESERVED RESERVED RESERVED RESERVED RESERVED D16 E23 E6 E7 F23 RESERVED F29 RESERVED G6 RESERVED N4 RESERVED N5 RESERVED P5 RESERVED V2 RESET# G23 Common Clock RS0# B3 Common Clock RS1# F5 Common Clock RS2# A3 Common Clock SKTOCC# AE8 Power/Other SMI# P2 Asynch CMOS STPCLK# M3 Asynch CMOS TCK AE1 TAP TDI AD1 TAP TDO AF1 TAP TESTHI0 F26 Power/Other TESTHI1 W3 Power/Other TESTHI10 H5 Power/Other TESTHI11 P1 Power/Other TESTHI12/ FC44 W2 Power/Other TESTHI13 L2 Power/Other TESTHI2 F25 Power/Other TESTHI3 G25 Power/Other TESTHI4 G27 Power/Other TESTHI5 G26 Power/Other TESTHI6 G24 Power/Other TESTHI7 F24 Power/Other TESTHI8/FC42 G3 Power/Other TESTHI9/FC43 G4 Power/Other THERMDA AL1 Power/Other THERMDC AK1 Power/Other THERMTRIP# M2 Asynch CMOS TMS AC1 TAP Input Input Input Input Output Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input 46 Datasheet Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC E3 Common Clock AG1 TAP AA8 Power/Other AB8 Power/Other AC23 Power/Other AC24 Power/Other AC25 Power/Other AC26 Power/Other AC27 Power/Other AC28 Power/Other AC29 Power/Other AC30 Power/Other AC8 Power/Other AD23 Power/Other AD24 Power/Other AD25 Power/Other AD26 Power/Other AD27 Power/Other AD28 Power/Other AD29 Power/Other AD30 Power/Other AD8 Power/Other AE11 Power/Other AE12 Power/Other AE14 Power/Other AE15 Power/Other AE18 Power/Other AE19 Power/Other AE21 Power/Other AE22 Power/Other AE23 Power/Other AE9 Power/Other AF11 Power/Other AF12 Power/Other AF14 Power/Other AF15 Power/Other AF18 Power/Other AF19 Power/Other AF21 Power/Other Input Input Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AF22 Power/Other AF8 Power/Other AF9 Power/Other AG11 Power/Other AG12 Power/Other AG14 Power/Other AG15 Power/Other AG18 Power/Other AG19 Power/Other AG21 Power/Other AG22 Power/Other AG25 Power/Other AG26 Power/Other AG27 Power/Other AG28 Power/Other AG29 Power/Other AG30 Power/Other AG8 Power/Other AG9 Power/Other AH11 Power/Other AH12 Power/Other AH14 Power/Other AH15 Power/Other AH18 Power/Other AH19 Power/Other AH21 Power/Other AH22 Power/Other AH25 Power/Other AH26 Power/Other AH27 Power/Other AH28 Power/Other AH29 Power/Other AH30 Power/Other AH8 Power/Other AH9 Power/Other AJ11 Power/Other AJ12 Power/Other AJ14 Power/Other AJ15 Power/Other Datasheet 47 Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC AJ18 AJ19 AJ21 AJ22 AJ25 Power/Other Power/Other Power/Other Power/Other Power/Other VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AJ26 Power/Other AJ8 Power/Other AJ9 Power/Other AK11 Power/Other AK12 Power/Other AK14 Power/Other AK15 Power/Other AK18 Power/Other AK19 Power/Other AK21 Power/Other AK22 Power/Other AK25 Power/Other AK26 Power/Other AK8 Power/Other AK9 Power/Other AL11 Power/Other AL12 Power/Other AL14 Power/Other AL15 Power/Other AL18 Power/Other AL19 Power/Other AL21 Power/Other AL22 Power/Other AL25 Power/Other AL26 Power/Other AL29 Power/Other AL30 Power/Other AL8 Power/Other AL9 Power/Other AM11 Power/Other AM12 Power/Other AM14 Power/Other AM15 Power/Other AM18 Power/Other Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC AM19 AM21 AM22 AM25 AM26 Power/Other Power/Other Power/Other Power/Other Power/Other VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 48 Datasheet Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC J28 J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_MB_ REGULATION VCC_SENSE VCCA VCCIOPLL VCCPLL VID_SELECT T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 AN5 AN3 A23 C23 D23 AN7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Datasheet 49 Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VID0 VID1 VID2 VID3 VID4 AM2 AL5 AM3 AL6 AK4 Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output VID5 VID6 VID7 VRDSEL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AL4 AM5 AM7 AL3 A12 A15 A18 A2 A21 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 AC6 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS AC7 AD4 AD7 AE10 AE13 Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 50 Datasheet Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AG23 Power/Other AG24 Power/Other AG7 Power/Other AH1 Power/Other AH10 Power/Other AH13 Power/Other AH16 Power/Other AH17 Power/Other AH20 Power/Other AH23 Power/Other AH24 Power/Other AH3 Power/Other AH6 Power/Other AH7 Power/Other AJ10 Power/Other AJ13 Power/Other AJ16 Power/Other AJ17 Power/Other AJ20 Power/Other AJ23 Power/Other AJ24 Power/Other AJ27 Power/Other AJ28 Power/Other AJ29 Power/Other AJ30 Power/Other AJ4 Power/Other AJ7 Power/Other AK10 Power/Other AK13 Power/Other AK16 Power/Other AK17 Power/Other AK2 Power/Other AK20 Power/Other AK23 Power/Other AK24 Power/Other AK27 Power/Other AK28 Power/Other AK29 Power/Other AK30 Power/Other Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AK5 Power/Other AK7 Power/Other AL10 Power/Other AL13 Power/Other AL16 Power/Other AL17 Power/Other AL20 Power/Other AL23 Power/Other AL24 Power/Other AL27 Power/Other AL28 Power/Other AL7 Power/Other AM1 Power/Other AM10 Power/Other AM13 Power/Other AM16 Power/Other AM17 Power/Other AM20 Power/Other AM23 Power/Other AM24 Power/Other AM27 Power/Other AM28 Power/Other AM4 Power/Other AN1 Power/Other AN10 Power/Other AN13 Power/Other AN16 Power/Other AN17 Power/Other AN2 Power/Other AN20 Power/Other AN23 Power/Other AN24 Power/Other AN27 Power/Other AN28 Power/Other B1 Power/Other B11 Power/Other B14 Power/Other B17 Power/Other B20 Power/Other Datasheet 51 Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS B24 B5 B8 C10 C13 Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C16 C19 C22 C24 C4 C7 D12 D15 D18 D21 D24 D3 D5 D6 D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E8 F10 F13 F16 F19 F22 F4 F7 H10 H11 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS H12 H13 H14 H17 H18 Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 52 Datasheet Land Listing and Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 T7 U7 V23 V24 V25 V26 V27 V28 V29 V3 V30 V6 V7 W4 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS W7 VSS Y2 VSS Y5 VSS Y7 VSS_MB_ REGULATION AN6 VSS_SENSE AN4 VSSA B23 VTT A25 VTT A26 VTT A27 VTT A28 VTT A29 VTT A30 VTT B25 VTT B26 VTT B27 VTT B28 VTT B29 VTT B30 VTT C25 VTT C26 VTT C27 VTT C28 VTT C29 VTT C30 VTT D25 VTT D26 VTT D27 VTT D28 VTT D29 VTT D30 VTT_OUT_LEFT J1 VTT_OUT_RIG HT AA1 VTT_SEL F27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Datasheet 53 Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Land Name VSS RS2# D02# D04# VSS D07# DBI0# VSS D08# D09# VSS COMP0 D50# VSS DSTBN3# D56# VSS D61# RESERVED VSS D62# VCCA FC23 VTT VTT VTT VTT VTT VTT VSS DBSY# RS0# D00# VSS D05# D06# VSS DSTBP0# D10# Signal Buffer Type Direction Power/Other Common Clock Input Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Input Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Land # B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Land Name VSS D13# COMP8 VSS D53# D55# VSS D57# D60# VSS D59# D63# VSSA VSS VTT VTT VTT VTT VTT VTT DRDY# BNR# LOCK# VSS D01# D03# VSS DSTBN0# FC38 VSS D11# D14# VSS D52# D51# VSS DSTBP3# D54# VSS Signal Buffer Type Direction Power/Other Source Synch Input/Output Power/Other Input Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other 54 Datasheet Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Land Name DBI3# D58# VSS VCCIOPLL VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# VSS HIT# VSS VSS D20# D12# VSS D22# D15# VSS D25# RESERVED VSS RESERVED D49# VSS DBI2# D48# VSS D46# VCCPLL VSS VTT VTT VTT VTT Signal Buffer Type Direction Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Land # D29 D30 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 F2 F3 F4 F5 F6 F7 F8 F9 F10 Land Name VTT VTT VSS TRDY# HITM# FC20 RESERVED RESERVED VSS D19# D21# VSS DSTBP1# D26# VSS D33# D34# VSS D39# D40# VSS D42# D45# RESERVED FC10 VSS VSS VSS VSS FC26 FC5 BR0# VSS RS1# FC21 VSS D17# D18# VSS Signal Buffer Type Direction Power/Other Power/Other Power/Other Common Clock Input Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Common Clock Input Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Datasheet 55 Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 VSS Power/Other D37# Source Synch Input/Output D38# Source Synch Input/Output VSS Power/Other D41# Source Synch Input/Output D43# Source Synch Input/Output VSS Power/Other RESERVED TESTHI7 Power/Other Input TESTHI2 Power/Other Input TESTHI0 Power/Other Input VTT_SEL Power/Other Output BCLK0 Clock Input RESERVED FC27 Power/Other COMP2 Power/Other Input TESTHI8/FC42 Power/Other Input TESTHI9/FC43 Power/Other Input PECI Power/Other Input/Output RESERVED DEFER# Common Clock Input BPRI# Common Clock Input D16# Source Synch Input/Output FC38 Power/Other DBI1# Source Synch Input/Output DSTBN1# Source Synch Input/Output D27# Source Synch Input/Output D29# Source Synch Input/Output D31# Source Synch Input/Output D32# Source Synch Input/Output D36# Source Synch Input/Output D35# Source Synch Input/Output DSTBP2# Source Synch Input/Output DSTBN2# Source Synch Input/Output Land # G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 Land Name D44# D47# RESET# TESTHI6 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 BSEL2 GTLREF0 GTLREF1 VSS FC35 TESTHI10 VSS VSS VSS VSS VSS VSS VSS VSS VSS FC32 FC33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC15 Signal Buffer Type Direction Source Synch Input/Output Source Synch Input/Output Common Clock Input Power/Other Input Power/Other Input Power/Other Power/Other Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Output Output Input Input Input 56 Datasheet Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction H30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 BSEL1 Power/Other Output VTT_OUT_LEFT Power/Other Output FC3 Power/Other FC22 Power/Other VSS Power/Other REQ1# Source Synch Input/Output REQ4# Source Synch Input/Output VSS Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other FC31 Power/Other FC34 Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other LINT0 Asynch CMOS Input VSS Power/Other A20M# Asynch CMOS Input REQ0# Source Synch Input/Output VSS Power/Other REQ3# Source Synch Input/Output VSS Power/Other VCC Power/Other Land # Land Name Signal Buffer Type Direction K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M23 M24 M25 M26 M27 M28 M29 VCC VCC VCC VCC VCC VCC VCC VCC LINT1 TESTHI13 VSS A06# A03# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS THERMTRIP# STPCLK# A07# A05# REQ2# VSS VCC VCC VCC VCC VCC VCC VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input Power/Other Input Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Output Asynch CMOS Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 57 Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # M30 N1 N2 N3 N4 N5 N6 N7 N8 N23 N24 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6 Land Name VCC PWRGOOD IGNNE# VSS RESERVED RESERVED VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TESTHI11 SMI# INIT# VSS RESERVED A04# VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP3 VSS FERR#/PBE# A08# VSS ADSTB0# Signal Buffer Type Direction Power/Other Power/Other Asynch CMOS Power/Other Input Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Asynch CMOS Power/Other Input Input Input Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Power/Other Asynch CMOS Output Source Synch Input/Output Power/Other Source Synch Input/Output Land # R7 R8 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U23 U24 U25 U26 U27 Land Name VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP1 FC4 VSS A11# A09# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC FC28 FC29 FC30 A13# A12# A10# VSS VCC VCC VCC VCC VCC VCC Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 58 Datasheet Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 Power/Other Output V2 RESERVED V3 VSS Power/Other V4 A15# Source Synch Input/Output V5 A14# Source Synch Input/Output V6 VSS Power/Other V7 VSS Power/Other V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other W1 MSID0 Power/Other Output W2 TESTHI12/FC44 Power/Other Input W3 TESTHI1 Power/Other Input W4 VSS Power/Other W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W7 VSS Power/Other W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other Y1 FC0 Power/Other Y2 VSS Power/Other Y3 FC17 Power/Other Y4 A20# Source Synch Input/Output Land # Land Name Signal Buffer Type Direction Y5 VSS Power/Other Y6 A19# Source Synch Input/Output Y7 VSS Power/Other Y8 VCC Power/Other Y23 VCC Power/Other Y24 VCC Power/Other Y25 VCC Power/Other Y26 VCC Power/Other Y27 VCC Power/Other Y28 VCC Power/Other Y29 VCC Power/Other Y30 VCC Power/Other AA1 VTT_OUT_RIGHT Power/Other Output AA2 FC39 Power/Other AA3 VSS Power/Other AA4 A21# Source Synch Input/Output AA5 A23# Source Synch Input/Output AA6 VSS Power/Other AA7 VSS Power/Other AA8 VCC Power/Other AA23 VSS Power/Other AA24 VSS Power/Other AA25 VSS Power/Other AA26 VSS Power/Other AA27 VSS Power/Other AA28 VSS Power/Other AA29 VSS Power/Other AA30 VSS Power/Other AB1 VSS Power/Other AB2 IERR# Asynch CMOS Output AB3 FC37 Power/Other AB4 A26# Source Synch Input/Output AB5 A24# Source Synch Input/Output AB6 A17# Source Synch Input/Output AB7 VSS Power/Other AB8 VCC Power/Other AB23 VSS Power/Other AB24 VSS Power/Other AB25 VSS Power/Other Datasheet 59 Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2 Land Name VSS VSS VSS VSS VSS TMS DBR# VSS RESERVED A25# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TDI BPM2# FC36 VSS ADSTB1# A22# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TCK VSS Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Input Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Power/Other Land # AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 Land Name FC18 RESERVED VSS RESERVED VSS SKTOCC# VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS TDO BPM4# VSS A28# A27# VSS VSS VCC VCC VSS VCC Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Output Common Clock Input/Output Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 60 Datasheet Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 Land Name VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS TRST# BPM3# BPM5# A30# A31# A29# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Common Clock Input/Output Common Clock Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 24. Numerical Land Assignment Land # AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 Land Name VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC VSS RESERVED VSS A32# A33# VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 61 Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Table 24. Numerical Land Assignment Land # AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 Land Name VCC BPM1# BPM0# ITP_CLK1 VSS A34# A35# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS THERMDC VSS ITP_CLK0 VID4 VSS FC8 VSS VCC Signal Buffer Type Direction Power/Other Common Clock Input/Output Common Clock Input/Output TAP Input Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Power/Other Output Power/Other Power/Other Power/Other Power/Other Land # AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 Land Name VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS THERMDA PROCHOT# VRDSEL VID5 VID1 VID3 VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input/Output Power/Other Power/Other Output Power/Other Output Power/Other Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 62 Datasheet Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 Land Name VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VID0 VID2 VSS VID6 FC40 VID7 VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC Signal Buffer Type Direction Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AM27 AM28 AM29 AM30 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 VSS VSS VCC VCC VSS VSS VCC_SENSE VSS_SENSE VCC_MB_ REGULATION VSS_MB_ REGULATION VID_SELECT VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Datasheet 63 Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# A20M# ADS# Type Description Input/ Output A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details. Input If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1# BCLK[1:0] BNR# Input Input/ Output The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. 64 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 2 of 9) Name Type Description BPM[5:0]# BPRI# BR0# BSEL[2:0] COMP8 COMP[3:0] Input/ Output BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. These signals do not have on-die termination. Refer to Section 2.6.2 for termination requirements. Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. Input/ Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to Section 2.8.2. Analog COMP[3:0] and COMP8 must be terminated to VSS on the system board using precision resistors. Datasheet 65 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. D[63:0]# Input/ Output Quad-Pumped Signal Groups Data Group DSTBN#/ DSTBP# DBI# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 DBI[3:0]# Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0] Assignment To Data Bus Input/ Output Bus Signal Data Bus Signals DBI3# DBI2# DBI1# DBI0# D[63:48]# D[47:32]# D[31:16]# D[15:0]# DBR# DBSY# Output DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. Input/ Output DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents. 66 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 4 of 9) Name DEFER# DRDY# Type Description Input Input/ Output DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. Signals Associated Strobe DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP[3:0]# DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. Input/ Output Signals D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe DSTBP0# DSTBP1# DSTBP2# DSTBP3# FCx FERR#/PBE# GTLREF[1:0] Other FC signals are signals that are available for compatibility with other processors. Output FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/ disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1. Datasheet 67 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 5 of 9) Name Type Description HIT# HITM# IERR# IGNNE# INIT# ITP_CLK[1:0] LINT[1:0] Input/ Output Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination. Refer to Section 2.6.2 for termination requirements. Input IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/ Output Write bus transaction. Input INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents. Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/ lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these signals as LINT[1:0] is the default configuration. 68 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 6 of 9) Name Type Description LOCK# MSID[1:0] PECI PROCHOT# PWRGOOD REQ[4:0]# RESET# RESERVED Input/ Output Output Input/ Output Input/ Output Input Input/ Output Input LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. These signals indicate the Market Segment for the processor. Refer to Table 3 for additional information. PECI is a proprietary one-wire bus interface. See Section 5.4 for details. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system de-asserts PROCHOT#. See Section 5.2.4 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins/ lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated on the system board. All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. Datasheet 69 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI[13:0] THERMDA THERMDC Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# (Socket Occupied) will be pulled to ground by the Output processor. System board designers may use this signal to determine if the processor is present. Input SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs. Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. Input TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. Output TDO provides the serial output needed for JTAG specification support. Input TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See Section 2.5 for more details. Other Thermal Diode Anode. See Section 5.3. Other Thermal Diode Cathode. See Section 5.3. 70 Datasheet Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 8 of 9) Name Type Description THERMTRIP# TMS TRDY# TRST# VCC VCCPLL VCC_SENSE VCC_MB_ REGULATION VID[7:0] VID_SELECT Output Input Input Input Input Input Output Output Output Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid) and is disabled on de-assertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, VTT, or VCC is de-asserted. While the de-assertion of the PWRGOOD, VTT, or VCC will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins. VCCPLL provides isolated power for internal processor FSB PLLs. VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure voltage near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VCC. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself. This land is tied high on the processor package and is used by the VR to choose the proper VID table. Refer to the Voltage RegulatorDown (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. Datasheet 71 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 9 of 9) Name Type Description VRDSEL VSS VSSA VSS_SENSE VSS_MB_ REGULATION VTT VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL Input Input Input Output Output Input Output Output This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA is the isolated ground for internal PLLs. VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. This land is provided as a voltage regulator feedback sense point for VSS. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Miscellaneous voltage supply. The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. The VTT_SEL signal is used to select the correct VTT voltage level for the processor. This land is connected internally in the package to VTT. §§ 72 Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Note: 5.1.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor. Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.4.1.1. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) and the Processor Power Characterization Methodology for the details of this methodology. Datasheet 73 Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2. To ensure maximum flexibility for future requirements, systems should be designed to the 775_VR_CONFIG_06 guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases the Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within specification. Table 26. Processor Thermal Specifications Processor Number Core Frequency (GHz) Thermal Design Power (W)1,2 Extended HALT Power (w)3 775_VR_ CONFIG_06 Guidance4 Minimum TC (°C) Maximum TC (°C) Notes E2200 2.2 E2180 2.0 E2160 1.8 E2140 1.6 E2160 1.8 E2140 1.6 65.0 65.0 65.0 65.0 65.0 65.0 8 5 5 8 8 775_VR_ CONFIG_06 Guidance 5 5 5 Table 28, Figure 16 5 8 5 5 8 8 775_VR_ CONFIG_06 Guidance 5 5 6 Table 27, Figure 15 6 NOTES: 1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate. 2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and TC. 3. Specification is at 35 °C TC and typical voltage loadline. Specification is ensured by design characterization and not 100% tested. 4. 775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal requirements. 5. These processors have CPUID = 06FDh. 6. These processors have CPUID = 06F2h. 74 Datasheet Thermal Specifications and Design Considerations Table 27. Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 2 43.8 4 44.3 6 44.9 8 45.4 10 46.0 12 46.6 14 47.1 16 47.7 18 48.2 20 48.8 22 49.4 24 49.9 26 50.5 28 51.0 30 51.6 32 52.2 34 52.7 36 53.3 38 53.8 40 54.4 42 55.0 44 55.5 46 56.1 48 56.6 50 57.2 52 57.8 54 58.3 56 58.9 58 59.4 60 60.0 62 60.6 64 61.1 65 61.4 Figure 15. Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h) 65.0 60.0 y = 0.28x + 43.2 55.0 Tcase (C) 50.0 45.0 40.0 0 10 20 30 40 50 60 Power (W) Datasheet 75 Thermal Specifications and Design Considerations Table 28. Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 45.3 2 46.2 4 47.0 6 47.9 8 48.7 10 49.6 12 50.5 14 51.3 16 52.2 18 53.0 20 53.9 22 54.8 24 55.6 26 56.5 28 57.3 30 58.2 32 59.1 34 59.9 36 60.8 38 61.6 40 62.5 42 63.4 44 64.2 46 65.1 48 65.9 50 66.8 52 67.7 54 68.5 56 69.4 58 70.2 60 71.1 62 72.0 64 72.8 65 73.3 Figure 16. Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) 76 Datasheet Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology Figure 17. The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 17 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Case Temperature (TC) Measurement Location Measure TC at this point (geometric center of the package) 37.5 mm 5.2 5.2.1 37.5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An Datasheet 77 Thermal Specifications and Design Considerations 5.2.2 under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID is that specified in Table 5. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 5). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, to ensure proper operation once the processor reaches its normal operating frequency. Refer to Figure 18 for an illustration of this ordering. 78 Datasheet Thermal Specifications and Design Considerations Figure 18. Thermal Monitor 2 Frequency and Voltage Ordering T TM2 f MAX f TM2 VID VID TM2 Temperature Frequency VID 5.2.3 PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode. On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature. The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/ 12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. Datasheet 79 Thermal Specifications and Design Considerations 5.2.4 5.2.5 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature. THERMTRIP# Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the timeframe defined in Table 11. 80 Datasheet Thermal Specifications and Design Considerations 5.3 Table 29. Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 29,Table 30, and Table 31 provide the "diode" parameter and interface specifications. Two different sets of "diode" parameters are listed in Table 29 and Table 30. The Diode Model parameters (Table 29) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 30) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. TCONTROL is a temperature specification based on a temperature reading from the thermal diode. The value for TCONTROL will be calibrated in manufacturing and configured for each processor. The TCONTROL temperature for a given processor can be obtained by reading a MSR in the processor. The TCONTROL value that is read from the MSR needs to be converted from Hexadecimal to Decimal and added to a base value of 50 °C. The value of TCONTROL may vary from 00 h to 1E h (0 to 30 °C). When TDIODE is above TCONTROL, then TC must be at or below TC_MAX as defined by the thermal profile in Table 27; otherwise, the processor temperature can be maintained at TCONTROL (or lower) as measured by the thermal diode. Thermal “Diode” Parameters using Diode Model Symbol Parameter Min Typ Max Unit Notes IFW Forward Bias Current 5 — 200 µA 1 n Diode Ideality Factor 1.000 1.009 1.050 - 2, 3, 4 RT Series Resistance 2.79 4.52 6.24 Ω 2, 3, 5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Preliminary data. Will be characterized across a temperature range of 50 – 80 °C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT –1) where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N–1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge. Datasheet 81 Thermal Specifications and Design Considerations Table 30. Table 31. Thermal “Diode” Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes IFW IE nQ Beta RT Forward Bias Current Emitter Current Transistor Ideality Series Resistance 5 5 0.997 0.391 2.79 — — 1.001 — 4.52 200 200 1.005 0.760 6.24 µA 1, 2 - 3, 4, 5 3, 4 Ω 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 29. 3. Preliminary data. Will be characterized across a temperature range of 50–80 °C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, RT, provided in the Diode Model Table (Table 29) can be used for more accurate readings as needed. The Intel® Pentium® Dual-Core Desktop processor E2000 series does not support the diode correction offset that exists on other Intel processors. Thermal Diode Interface Signal Name Land Number THERMDA THERMDC AL1 AK1 Signal Description diode anode diode cathode 82 Datasheet Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction Figure 19. PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 19 shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS. Processor PECI Topology PECI Host Controller Land G5 30h Domain 0 5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management Fan speed control solutions based on PECI uses a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative. Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or optimize fan speeds. Figure 20 shows a conceptual fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero. Datasheet 83 Thermal Specifications and Design Considerations . Figure 20. Conceptual Fan Control on PECI-Based Platforms Fan Speed (RPM) TCONTROL Setting TCC Activation Temperature Max PECI = -10 PECI = 0 Min PECI = -20 Temperature Note: Not intended to depict actual implementation . Figure 21. Conceptual Fan Control on Thermal Diode-Based Platforms Fan Speed (RPM) TCONTROL Setting TCC Activation Temperature Max TDIODE = 80 °C TDIODE = 90 °C Min TDIODE = 70 °C Temperature 84 Datasheet Thermal Specifications and Design Considerations 5.4.2 5.4.2.1 5.4.2.2 5.4.2.3 5.4.2.4 Table 32. PECI Specifications PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification. PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI. To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition. PECI GetTemp0() Error Code Support The error codes supported for the processor GetTemp() command are listed in Table 32. GetTemp0() Error Codes Error Code 8000h 8002h Description General sensor error Sensor is operational, but has detected a temperature below its operational range (underflow). §§ Datasheet 85 Thermal Specifications and Design Considerations 86 Datasheet Features 6 Features 6.1 Table 33. Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 33. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset. Power-On Configuration Option Signals Configuration Option Signal1,2,3 Output tristate SMI# Execute BIST A3# Disable dynamic bus parking A25# Symmetric agent arbitration ID BR0# RESERVED A[8:5]#, A[24:11]#, A[35:26]# NOTES: 1. Asserting this signal during RESET# will select the corresponding option. 2. Address signals not identified in this table as configuration options should not be asserted during RESET#. 3. Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core. Datasheet 87 Features 6.2 Clock Control and Low Power States Figure 22. The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 22 for a visual representation of the processor low power states. Processor Low Power State Machine Normal State - Normal Execution HALT or MWAIT Instruction and HALT Bus Cycle Generated INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Extended HALT or HALT State - BCLK running - Snoops and interrupts allowed 6.2.1 6.2.2 STPCLK# STPCLK# Asserted De-asserted Stop Grant State - BCLK running - Snoops and interrupts allowed STPCLK# Asserted STPCLK# De-asserted Snoop Event Occurs Snoop Event Serviced Snoop Event Occurs Snoop Event Serviced Extended HALT Snoop or HALT Snoop State - BCLK running - Service Snoops to cahces Stop Grant Snoop State - BCLK running - Service Snoops to cahces Normal State This is the normal operating state for the processor. HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default powerdown state entered will be HALT. Refer to the sections below for details about the HALT and Extended HALT states. 88 Datasheet Features 6.2.2.1 6.2.2.2 6.2.3 HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT powerdown state, the processor will process bus snoops. Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT powerdown state must be enabled via the BIOS for the processor to remain within its specification. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Extended HALT state, the processor will process bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value. Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extended Stop Grant states. The Extended Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer to the following sections for details about the Stop Grant and Extended Stop Grant states. Datasheet 89 Features 6.2.3.1 6.2.3.2 6.2.4 6.2.4.1 Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop. Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled via the BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. The processor exits the Extended Stop Grant state when a break event occurs. When the processor exits the Extended Stop Grant state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value. Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on HALT Snoop State, Stop Grant Snoop State, Extended HALT Snoop State, and Extended Stop Grant Snoop State. HALT Snoop State, Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT powerdown state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT powerdown state, as appropriate. 90 Datasheet Features 6.2.4.2 6.3 Note: Extended HALT Snoop State, Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state. While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the processor will return to the Extended HALT state or Extended Stop Grant state. Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/frequency states is software controlled. Not all processors are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Intel® Pentium® Dual-Core Desktop Processor E2000 Series Specification Update when available. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 22. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers), thus eliminating chipset dependency. — If the target frequency is higher than the current frequency, VCC is incriminated in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. — If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. Datasheet §§ 91 Features 92 Datasheet Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 23 shows a mechanical representation of a boxed processor. Note: Figure 23. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales Representative for this document. Mechanical Representation of the Boxed Processor NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Datasheet 93 Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 23 shows a mechanical representation of the boxed processor. Figure 24. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 24 (Side View), and Figure 25 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 29 and Figure 30. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning. Space Requirements for the Boxed Processor (Side View) 95.0 [3.74] 81.3 [3.2] 10.0 [0.39] 25.0 [0.98] Boxed_Proc_SideView 94 Datasheet Boxed Processor Specifications Figure 25. Space Requirements for the Boxed Processor (Top View) Figure 26. NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Space Requirements for the Boxed Processor (Overall View) Datasheet Boxed Proc OverallView 95 Boxed Processor Specifications 7.1.2 7.1.3 7.2 7.2.1 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly. Electrical Requirements Fan Heatsink Power Supply The processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 27. Baseboards must provide a matched power header to support the boxed processor. Table 34 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 28 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket. 96 Datasheet Boxed Processor Specifications Figure 27. Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND 2 +12 V 3 SENSE 4 CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. Table 34. 1 2 34 Fan Heatsink Power and Signal Specifications Description Min Typ +12 V: 12 volt fan power supply 11.4 12 IC: - Maximum fan steady-state current draw — 1.2 - Average fan steady-state current draw — 0.5 - Maximum fan start-up current draw — 2.2 - Fan start-up current draw maximum duration — 1.0 SENSE: SENSE frequency — 2 CONTROL 21 25 NOTES: 1. Baseboard should pull this pin up to 5 V with a resistor. 2. Open drain type, pulse width modulated. 3. Fan will have pull-up resistor for this signal to maximum of 5.25 V. Max 12.6 — — — — — 28 B d P P C bl Unit V Notes - A A - A Second pulses per fan 1 revolution kHz 2, 3 Datasheet 97 Boxed Processor Specifications Figure 28. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C 7.3 7.3.1 Boxed Proc PwrHeaderPlacement Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is listed in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 26) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 29 and Figure 30 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator. 98 Datasheet Boxed Processor Specifications Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 30. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) Datasheet 99 Boxed Processor Specifications 7.3.2 Fan Speed Control Operation (Intel® Pentium® Dual-Core Desktop Processor E2000 Series) If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler than a lower set point. These set points, represented in Figure 31 and Table 35, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. Figure 31. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 35 for the specific requirements. Boxed Processor Fan Heatsink Set Points Increasing Fan Speed & Noise Higher Set Point Highest Noise Level Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) 100 Datasheet Boxed Processor Specifications Table 35. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. 1 Recommended maximum internal chassis temperature for nominal operating environment. Y = 35 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for - worst-case operating environment. Z ≥ 38 When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. - NOTES: 1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink. If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 34) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's temperature diode (T-diode). Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures. If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). § §§ Datasheet 101 Boxed Processor Specifications 102 Datasheet Debug Tools Specifications 8 Debug Tools Specifications 8.1 8.1.1 8.1.2 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical. Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI. Electrical Considerations The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides. §§ Datasheet 103 Debug Tools Specifications 104 Datasheet

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