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DM9051NP datasheet

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  • 日期: 2018-09-25
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标签: DM9051NP

DM9051NP

datasheet

datasheet

RJ45

RJ45是布线系统中信息插座(即通信引出端)连接器的一种,连接器由插头(接头、水晶头)和插座(模块)组成,插头有8个凹槽和8个触点。

DM9051NP datasheet 

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DM9051DM9051I SPI to Ethernet Controller DAVICOM Semiconductor Inc DM9051DM9051I SPI to Ethernet Controller DATA SHEET Version DM9051DM9051Ieng May 23 2014 1 Doc No DM9051DM9051Ieng May 23 2014 1 2 3 4 5 6 Content DM9051DM9051I SPI to Ethernet Controller General Description 5 Features 6 Block Diagram 7 Pin Configuration 8 41 32Pin QFN 8 Pin Description 9 51 SPI Processor Interface 9 52 EEPROM Interf......

DM9051/DM9051I SPI to Ethernet Controller DAVICOM Semiconductor, Inc. DM9051/DM9051I SPI to Ethernet Controller DATA SHEET Version: DM9051/DM9051I-eng May 23, 2014 1 Doc No: DM9051/DM9051I-eng May 23, 2014 1 2 3 4 5 6 Content DM9051/DM9051I SPI to Ethernet Controller General Description ................................................................................................................................ 5 Features ................................................................................................................................................... 6 Block Diagram ......................................................................................................................................... 7 Pin Configuration .................................................................................................................................... 8 4.1 32-Pin QFN ......................................................................................................................................... 8 Pin Description ........................................................................................................................................ 9 5.1 SPI Processor Interface ...................................................................................................................... 9 5.2 EEPROM Interface ............................................................................................................................. 9 5.3 Clock Interface .................................................................................................................................... 9 5.4 LED Interface .................................................................................................................................... 10 5.5 10/100 PHY/Fiber ............................................................................................................................. 10 5.6 Miscellaneous ................................................................................................................................... 10 5.8 Strap Pins ........................................................................................................................................... 11 Vender Control and Status Register Set ............................................................................................. 12 6.1 Network Control Register (00H) ........................................................................................................ 14 6.2 Network Status Register (01H) ......................................................................................................... 14 6.3 TX Control Register (02H) ................................................................................................................ 15 6.4 TX Status Register I (03H) for Packet Index I ................................................................................... 16 6.5 TX Status Register II (04H) for packet index I I ................................................................................ 17 6.6 RX Control Register (05H) ................................................................................................................ 18 6.7 RX Status Register (06H) ................................................................................................................. 19 6.8 Receive Overflow Counter Register (07H) ....................................................................................... 20 6.9 Back Pressure Threshold Register (08H) ......................................................................................... 20 6.10 Flow Control Threshold Register (09H) .......................................................................................... 21 6.11 RX/TX Flow Control Register (0AH) ............................................................................................... 21 6.12 EEPROM & PHY Control Register (0BH) ....................................................................................... 22 6.13 EEPROM & PHY Address Register (0CH) ..................................................................................... 22 6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH EE_PHY_H:0EH) ....................................... 22 6.15 Wake Up Control Register (0FH) .................................................................................................... 23 6.16 Physical Address Register (10H~15H) ........................................................................................... 23 6.17 Multicast Hash_Table Address Register (16H~1DH) ...................................................................... 23 6.18 General purpose control Register (1EH) ........................................................................................ 24 6.19 General purpose Register (1FH) .................................................................................................... 24 6.20 TX SRAM Read Pointer Address Register (22H~23H) ................................................................... 24 6.21 RX SRAM Write Pointer Address Register (24H~25H) .................................................................. 24 6.22 Vendor ID Register (28H~29H) ....................................................................................................... 24 6.23 Product ID Register (2AH~2BH) ..................................................................................................... 24 6.24 CHIP Revision (2CH) ...................................................................................................................... 24 6.25 Transmit Control Register 2 (2DH) ................................................................................................. 25 6.26 Transmit Check Sum Control Register (31H) ................................................................................. 25 6.27 Receive Check Sum Status Register (32H) .................................................................................... 26 6.28 INT Pin Control Register (39H) ....................................................................................................... 26 6.29 Pause Packet Control/Status Register (3DH) ................................................................................. 26 6.30 IEEE 802.3az Enter Counter Register (3EH).................................................................................. 27 6.31 IEEE 802.3az Leave Counter Register (3FH) ................................................................................. 27 6.32 SPI Byte Align Error Counter Register (4AH) ................................................................................. 27 6.33 RX Packet Length Control Register (52H) ...................................................................................... 27 6.34 RX Broadcast Control Register (53H) ............................................................................................. 27 6.35 INT Pin Clock Output Control Register (54H) ................................................................................. 27 6.36 Memory Pointer Control Register (55H) ......................................................................................... 28 6.37 More LED Control Register (57H) ................................................................................................... 28 6.38 Memory Control Register (59H) ...................................................................................................... 28 6.39 Transmit Memory Size Register (5AH) ........................................................................................... 28 6.40 Full Memory Size Register (5BH) ................................................................................................... 28 6.41 Memory Data Pre-Fetch Read Command without Address Increment Register (70H) .................. 28 6.42 Memory Data Read Command with Address Increment Register (72H) ........................................ 29 6.43 Data Read Delay Counter Register (73H) (for SPI mode only) ...................................................... 29 Doc No: DM9051/DM9051I-eng May 23, 2014 2 DM9051/DM9051I SPI to Ethernet Controller 7 9 8 6.44 Memory Data Read address Register (74H~75H) .......................................................................... 29 6.45 Memory Data Write Command without Address Increment Register (76H) ................................... 29 6.46 Memory data write command with address increment Register (78H) ........................................... 29 6.47 Memory data write address Register (7AH~7BH) .......................................................................... 29 6.48 TX Packet Length Register (7CH~7DH) ......................................................................................... 29 6.49 Interrupt Status Register (7EH) ...................................................................................................... 30 6.50 Interrupt Mask Register (7FH) ........................................................................................................ 30 EEPROM and SPI Command Format .................................................................................................. 31 7.1 EEPROM Format .............................................................................................................................. 31 7.2 SPI Command Format ...................................................................................................................... 32 PHY Register Description .................................................................................................................... 33 8.1 Basic Mode Control Register (BMCR) – 00H ................................................................................... 34 8.2 Basic Mode Status Register (BMSR) – 01H ..................................................................................... 35 8.3 PHY ID Identifier Register #1 (PHYID1) – 02H ................................................................................. 36 8.4 PHY ID Identifier Register #2 (PHYID2) – 03H ................................................................................. 36 8.5 Auto-negotiation Advertisement Register (ANAR) – 04H ................................................................. 37 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H ...................................................... 38 8.7 Auto-negotiation Expansion Register (ANER) – 06H ....................................................................... 39 8.8 DAVICOM Specified Configuration Register (DSCR) – 10H ............................................................ 39 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H ........................................ 40 8.10 10BASE-T Configuration/Status (10BTCSR) – 12H ....................................................................... 41 8.11 Power down Control Register (PWDOR) – 13H ................................................................................... 42 8.12 (Specified Config) Register – 14H .................................................................................................. 42 8.13 Power Saving Control Register (PSCR) – 1DH .............................................................................. 43 Functional Description ......................................................................................................................... 44 9.1 SPI Processor Interface .................................................................................................................... 44 9.2 Direct Memory Access Control.......................................................................................................... 44 9.3 Packet Transmission ......................................................................................................................... 44 9.4 Packet Reception .............................................................................................................................. 44 9.5 100Base –TX Operation ................................................................................................................... 45 9.5.1 4B5B Encoder ....................................................................................................................... 45 9.5.2 Scrambler .............................................................................................................................. 45 9.5.3 Parallel to Serial Converter ................................................................................................... 45 9.5.4 NRZ to NRZI Encoder ........................................................................................................... 45 9.5.5 MLT-3 Converter .................................................................................................................... 45 9.5.6 MLT-3 Driver .......................................................................................................................... 45 9.5.7 4B5B Code Group ................................................................................................................. 46 9.6 100Base-TX Receiver ....................................................................................................................... 47 9.6.1 Signal Detect ......................................................................................................................... 47 9.6.2 Adaptive Equalization ............................................................................................................ 47 9.6.3 MLT-3 to NRZI Decoder ........................................................................................................ 47 9.6.4 Clock Recovery Module ........................................................................................................ 47 9.6.5 NRZI to NRZ .......................................................................................................................... 47 9.6.6 Serial to Parallel .................................................................................................................... 48 9.6.7 Descrambler .......................................................................................................................... 48 9.6.8 Code Group Alignment .......................................................................................................... 48 9.6.9 4B5B Decoder ....................................................................................................................... 48 9.7 10Base-T Operation .......................................................................................................................... 48 9.8 Collision Detection ............................................................................................................................ 48 9.9 Carrier Sense .................................................................................................................................... 48 9.10 Auto-Negotiation ............................................................................................................................. 49 9.11 Power Reduced Mode .................................................................................................................... 49 9.11.1 Power down Mode ............................................................................................................... 49 10 DC Characteristics ................................................................................................................................. 50 10.1 Absolute Maximum Ratings (25C) ................................................................................................. 50 10.1.1 Operating Conditions .......................................................................................................... 50 10.2 DC Electrical Characteristics (VDD = 3.3V) .................................................................................... 50 Doc No: DM9051/DM9051I-eng May 23, 2014 3 DM9051/DM9051I SPI to Ethernet Controller 11 AC Electrical Characteristics & Timing Waveforms ........................................................................... 51 11.1 SPI timing ........................................................................................................................................ 51 11.2 TP Interface ..................................................................................................................................... 51 11.3 Oscillator/Crystal Timing ................................................................................................................. 51 11.4 Power On Reset Timing .................................................................................................................. 52 11.5 EEPROM Interface Timing .............................................................................................................. 53 11.6 LED (traffic ON/OFF timing) any LED as traffic .............................................................................. 53 12 Package Information ............................................................................................................................. 54 13 Ordering Information ............................................................................................................................ 55 Doc No: DM9051/DM9051I-eng May 23, 2014 4 1 General Description DM9051/DM9051I SPI to Ethernet Controller The DM9051/DM9051I is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a Serial Peripheral Interface (SPI), a 10/100M PHY and SRAM. It is designed with low power and high performance process interface that support 3.3V with 5V IO tolerance. The PHY of the DM9051/DM9051I can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX. It is fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9051/DM9051I to take the maximum advantage of its abilities. The DM9051/DM9051I also supports IEEE 802.3az and IEEE 802.3x full- duplex flow control. Doc No: DM9051/DM9051I-eng May 23, 2014 5
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hwmxrhx
嗯·看看,是我需要的
2019-10-11 09:54:48回复
二营长的跑马灯
有没有中文版啊
2019-06-12 14:28:18回复
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