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Design Considerations for UFS & eMMC Controllers

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  • 日期: 2015-06-22
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标签: UFSeMMCcontroller

Design Considerations for 

UFS & eMMC Controllers

Design Considerations for UFS & eMMC Controllers Andrew Haines VP Marketing Arasan Chip Systems, Inc.. San Jose, CA May, 2013 Agenda  Mobile Storage in SoC  Challenges in Mobile Storage Controller Designs  Enabling Mobile Storage Design Ecosystem  Summary Multiple Mobile Storage Interfaces in Application Processor Touch Screen Audio Spkr, Mic Hdset LCD Display Camera 4G/3G Modem Wi-Fi I2C / SPI Slimbus MIPI DSI MIPI CSI-3 HSI, LLI HSIC SDIO LPDDR2 Keyboard GPIO IrDA UART Video Audio & Display GPMC UFS 1.1 / 2.x Power Monitor PC Aps Bus Processors Controllers System Clock CLK 3DTV Typical Mobile controller HDMI 1.4a Application Processor eMMC 4.51 / 5.x SD 3.0/4.0 SATA-2 USB2.0/3.0 USB3.0 OTG LPDDR2 DRAM Flash UFS Device eMMC Device SD Device SSD USB Device Backward Compatibility Mobile Storage Evolution Faster Than Ever UFS eMMC MMC 4.1 High Speed MMC 4.2 High Capacity SD Obsolete SD 1.0 SD 1.1 High speed SD 2.0 High capacity 2003 2006 UFS 1.0 UFS 1.1 UFS 2.x eMMC eMMC 4.3 4.41 eMMC 4.51 eMMC 5.x Peaked Ramping Up Early Adopter SD 3.0 2009 SD 4.0 2011 2012 SD 4.1 2013 Challenges of Backward Compatibility eMMC Max Throughput eMMC 4.41 High Speed 832 Mbps eMMC 4.51 HS200 1.6 Gbps eMMC 5.0 HS400 3.2 Gbps Data Lines 4 or 8-bit 8-bit Signal Count IO Voltages Interface 10 Pins 1.2 V / 1.8 V 3V DDR-52 HS200 11 Pins (Data Strobe) 1.2 V / 1.8 V HS400 Data Strobe No Yes Tuning (Read) No Yes Clock (MHz) 0 – 52 MHz 0 – 200 MHz eMMC Compliance  eMMC Device spec published by JEDEC  Compliance can be done through 3rd party Compliance Testers • No formal compliance guidelines Challenges of Backward Compatibility UFS UFS 1.0 UFS 1.1 UFS 2.0 Transaction Layer Link Layer Host Interface UniPro™ HCI 1.0 v1.40 HCI 1.1 v1.41 # of Lanes Single Lane Single Lane HCI 2.0 v1.60 2-Lane Physical Layer Source: JEDEC M-PHY Data Rate # of Lanes Interface Diff Vpeak-peak v1.0 v2.0 v3.0 1.5 Gbps 2.9 Gbps 5.8 Gbps 1 2 Tx +/-, Rx +/- 500 mV Max (non-terminated) 250 mV Max (terminated) UFS 1.1 Compliance Protocol Rev. Test Spec Certification Transaction Layer UFS 1.1 UFS Test Spec v1.0 Link Layer UniPro 1.41 UniPro CTS_v1.0_r01 PHY Layer M-PHY 2.0 M-PHY CTS_v0.99 UFSA MIPI / UNH-iOL Design Challenges Can I have all these validated before starting my SoC design? 2. Backward Compatibility 3. Inter-Operability eMMC 4.3  4.4  4.5  4.51  5.x UFS 1.0  1.1  2.x UniPro 1.40  1.41  1.6x M-PHY 1.0  2.0  3.x SD 2.0  3.0  4.0  4.x UHS-II  UHS-? Data/File Transfer Read/Write Commands Link Initialization JEDEC eMMC SDA UFS UFSA Physical Layer Link Layer Application Layer MIPI® Alliance UniProSM M-PHY ® SD SDIO 1. Compliance to Industry Standard(s) M-PHY ® Verification Before Silicon Sequencer M-PHY RMMI M-PHY Agent Agent Coverage Scoreboard Sequencer M-PHY DPDN Agent M-PHY Coverage Agent VIP UVC RMMI Master CTRL DATA VIP UVC RMMI Monitor DUT M-PHY DPDN VIP UVD DPDN Monitor VIP UVC DPDN M-PHY Verification Before Silicon Reset & Initialization Sequencer Scoreboarding Scoreboard M-PHY Agent VIP UVC RMMI Master Constrained random stimulus Functional Check Coverage Coverage Collection CTRL DATA VIP UVC RMMI Monitor DUT M-PHY Coverage DPDN VIP UVD DPDN Monitor Sequencer M-PHY Agent VIP UVC DPDN M-PHY Verification Cases Sequencer Scoreboard M-PHY Agent Coverage Coverage HS/LP Random Burst Tx/Rx VIP UVC RMMI Master CTRL DATA HS/LS Modes and Power State Re-configuration Test VIP Error Injection Test UVC RMMI Monitor Timing – Gate Level Simulation DPDN DUT M-PHY VIP UVD DPDN Monitor HW Reset test Attribute read/write test Sequencer M-PHY Agent VIP UVC DPDN UFS Host UVM Agent UFS Controller Verification Before Silicon (UFS-HCI + UniPro) AXI UVC DUT UFS Host HCI IP UniPro IP UniPro UVC UFS Device UVM Agent Assertions Checkers Ref /Received UFS write/Read UPIU Packets UFS Host Functional Coverage UFS Host Scoreboard Received /Ref UFS Write/Read UPIU Packets Migrate to FPGA based System • A black-box approach enables quick access to a validation platform • FPGA with Verified UFS IP CPU PCIe UFS Controller Board FPGA M-PHY RAM Emulated NAND Flash UFS drv PCIe drv Motherboard UFS & Memory Managers Applications NAND Flash Memory Emulator Low Level UFS Device Driver PCIe Interface Layer UFS Controller Bitmap Host Controller Interface - PCIe L4 – Protocol Layer L3 – Network Layer L2 – Link Layer L1.5 – Physical Adapter Layer PCIe drv UFS drv Emulated Flash Storage CP U CP U Block drv UFS drv PCIe drv PCI e UFS HCI L4 L3 L2 L1.5 M-PHY Digita l FPGA System for Device Validation & Software Development Host Device RAM RAM HDD UFS Controller FPGA Board FPGA M-PHY UFS Controller FPGA Board M-PHY FPGA HDD M-PHY Digita l L1.5 L2 L3 L4 CP U Interface PCI e Linux System with PCIe DME DME Tested M-PHY Signals Linux System with PCIe Certified UniPro Verified and Tested UFS-HCI or System Bus Interface Verified and Tested Driver and Stacks Enabling UFS/eMMC Design Ecosystem  FPGA based Development Platform productized into Validation Platform • IP, software stacks and PHY come together  Used by IP vendor (e.g.. Arasan) for Interoperability testing with other pioneers  Used by Test & Measurement vendors as target platforms • For validation of protocol generators and analyzers  Ultimately used by SoC/Device vendors as target or reference platforms for silicon validation • Assured of IP interoperability, compliance, and backward compatibility Summary  New JEDEC storage standards continue to evolve for new markets • Early IP/SoC validation enables compliance and compatibility for fast time-to-market  Different SoC vendors at different stages of spec adoption • Different spec revisions from different OEM’s • Backward compatibility and Interoperability a must among vendors  IP vendors continue to • Lead the pack in transforming specs to RTL and GDSII • Keeping backward compatibility with older standards in new designs • Enabling ecosystem-wide Inter-Op and compliance through – Software stacks – Hardware Validation Platforms All items available before starting your SoC/Device designs !! THANK YOU




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