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Features • AUDIO CODEC – 100dB Dynamic Range Stereo Audio DAC - 8 to 96 kHz sampling frequency – 96dB Dynamic Range Stereo Audio ADC - 8 to 96 kHz sampling frequency – 16 / 32 Ohms headset amplifier with capless operation • SNR: 97 dB A-Weighted • THD: -60 dB (16Ohms / 20mW / 3.3V supply) • Maximum output power: 55mW (16Ohms / 3.3V supply) – Stereo line inputs, stereo auxiliary inputs – Stereo microphone inputs with bias generator for electret device – Low power Analog Bypass mode (Line / Aux in to Headset Out) – Low power Analog sidetone mode (Microphone in to Headset Out) – Automatic Audio path control with smooth fade in / fade out operation – I2S port • Master / Slave Operation • I2S / Left / Right justified modes • 16 / 18 / 20 / 24 bit operation • 6x SUPPLY CHANNEL VOLTAGE REGULATORS – DCDC0: • 1.85V - 600mA. 0.8 to 3.6V / 50mV step. • 2 MHz switching buck regulator • Fast load transient response - PWM / PFM modes. • Efficiency up to 92% – DCDC1: • 1.2V - 600mA. 0.8 to 3.6V / 50mV step. • 2 MHz switching buck regulator • Fast load transient response - PWM / PFM modes. • Efficiency up to 90% – LDO2: 1V - 300mA. 0.8 to 1.35V / 50mV step - Fast transient response – LDO3: 3.3V - 200mA. 2.7 to 3.6V / 50mV step - Fast transient response – LDO4: 3.3V - 200mA. 2.7 to 3.6V / 50mV step - Audio codec supply – LDO5: 2.5V - 10mA - Backup battery charger and RTC supply • LOW CONSUMPTION POWER MANAGER – 2.5V - 5.5V VIN Operation – 20uA typical consumption OFF mode – VIN monitor, CPU supplies monitor – Die temperatue and over-current protections – Reset and Interrupt generation – Automatic Voltage Ramping on supply channels for DVS applications – Standby mode with selectable supplies OFF • RTC – Ultra Low power crystal oscillator (<1uA typ.) – Wake up function with programmable alarm or selectable inputs • 10-b / 300kS/s ADC with 4 external / 6 int\ernal selectable inputs • Two-Wire Interface for PMU and Audio controls • Available in 7.5 x 7.5 x 0.9 mm 64-pin QFN Package • Applications: Multimedia, Audio + Supply solution for MPU+DDR2 designs. Power Management and Analog Companions (PMAAC) AT73C246 6 Supply Channel PMU With Audio Codec 11050A–PMAAC–07-Apr-10 1. Description The AT73C246 is an integrated high performance Power Management and Audio IC. It is specifically designed for advanced technology application processors with complex and low voltage supplies targeting audio applications from low to high end. This System-on-Chip allows significant savings in both cost and board area over previous discrete solutions. Directly operated from a 2.9V to 5.5V input voltage, the PMU generates a set of 4 regulated power supplies and an associated delayed reset signal. These 4 voltages are built up with 2 high efficiency DCDC buck converters and 2 low noise LDOs. Featuring ultra fast transient responses and integrating automatic voltage scaling function, these supplies perfectly fit with modern low voltage MCU cores and memory supplies (DDR, Flash, ...). An additional 200mA LDO under software control is provided for auxiliary application functions. The high performances of this LDO (high PSRR, low noise, fast transient response) makes it ideal for analog front-ends (Audio, RF...) as well digital peripherals. Aside from the PMU, the AT73C246 integrates a complete state-of-the art low power audio codec with headphone amplifier. On the input side, a stereo microphone preamplifier with differential or single ended connection (MICDIFF / MIC) and 2 selectable stereo inputs (LINE / AUX) are directed to a 96dB Dynamic Range stereo audio ADC through an input mixer. On the output side a 100dB dynamic range stereo audio DAC drives, through an output mixer, a 60 mW stereo headphone amplifier which comes along with a VCM buffer. This VCM buffer allows to save two large on-board coupling capacitors for area constrained applications. Additionally two fully analog paths called bypass and sidetone from line / aux and microphone inputs to headphone outputs allow to reduce the audio power consumption to minimum when needed. The PMU is complemented with a low power RTC system including a recharging LDO, a crystal oscillator and a programmable alarm that is fully integrated in the PMU digital core. Thus, the RTC function is able to wake up the PMU, i.e the regulated power supplies, at a programmed instant. Also, a 10-bit ADC equipped with a 10:1 analog multiplexer is provided to the application to perform voltage measurements. Finally, to reduce power consumption to minimum, the PMU features a flexible STANDBY mode where the MCU is placed in reset state with selectable supplies ON, OFF or in low-power mode. Power consumption in OFF mode is typically 20uA. 2 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 2. Block Diagram Figure 2-1. AT73C246 functional block diagram 37 VIN4 36 VDD4 LDO4 3.3V Max: 200mA (CODEC) 28 LINL 27 LINR 30 AUXL 29 AUXR 34 MICL 31 MICLN 33 MICR 32 MICRN 18 AVDD 35 MICBIAS 12 VMID 17 AGND 13 HPDET 14 HPR 16 HPL 15 HPVCM AUDIO IN + ADC AUDIO BIAS AUDIO CODEC AUDIO OUT + DAC 44 MCLK 43 LRFS 42 BCLK 41 DAI 40 DAO 63 XIN 64 XOUT 49 CLK32K 62 WAKEUP0 60 HRST 61 PWREN AUDIO PORT RTC + OSC VBACKUP 3 ANA0 4 ANA1 5 ANA2 6 ANA3 Internal voltages ANALOG MUX 10b SAR ADC DIGITAL CORE BUCK0 1.8V Max: 600mA (CORE + MEM) BUCK1 1.2V Max: 600mA (CORE) VIN0 57 SW0 58 VFB0 56 GND0 59 VIN1 53 SW1 54 VFB1 52 GND1 55 LDO2 1V Max: 300mA (CORE) VIN2 51 VDD2 50 LDO3 3.3V Max: 200mA (I/O) VIN3 38 VDD3 39 LDO5 VBACKUP 1 2.5V Max: 10mA (BACKUP) VINSYS 7 LDO6 1.8V / 10mA (Internal functions) VDDC 8 PMU BIAS REXT 10 VBG 9 GNDSYS 11 RSTB 20 ITB 19 WAKEUP1 23 WAKEUP2 24 PMU STATE WAKEUP3 MACHINES 25 VPAD 45 DGND 65 LED 2 TWI TWCK TWD 22 21 DIE TEMP SENSOR DCDC 4MHz RC OSCILLATOR SYSTEM 32KHz RC OSCILLATOR NC NC NC 26 47 48 NC 46 3 11050A–PMAAC–07-Apr-10 3. Package and Pinout Figure 3-1. AT73C246 QFN64 package pinout - Top view MCLK32 VDD2 VIN2 VFB1 VIN1 SW1 GND1 VFB0 VIN0 SW0 GND0 HRST PWREN WAKEUP0 XIN XOUT VBACKUP LED ANA0 ANA1 ANA2 ANA3 VINSYS VDDC VBG REXT GNDSYS VMID HPDET HPR HPVCM HPL 64 1 16 17 49 48 33 32 NC NC NC VPAD MCLK LRFS BCLK DAI DAO VDD3 VIN3 VIN4 VDD4 MICBIAS MICL MICR MICRN MICLN AUXL AUXR LINL LINR NC WAKEUP3 WAKEUP2 WAKEUP1 TWCK TWD RSTB ITB AVDD AGND 4 AT73C246 11050A–PMAAC–07-Apr-10 4. Pin Description Table 4-1. Pin Name VBACKUP Pin Description I/O Pin Number Output 1 LED Output 2 ANA0 Input 3 ANA1 Input 4 ANA2 Input 5 ANA3 Input 6 VINSYS Input 7 VDDC Output 8 VBG Output 9 REXT Output 10 GNDSYS GND 11 VMID Output 12 HPDET Input 13 HPR Output 14 HPVCM Output 15 HPL Output 16 AGND GND 17 AVDD Input 18 ITB Output 19 RSTB TWD TWCK Output 20 Input/Output 21 Input 22 WAKEUP1 Input 23 WAKEUP2 Input 24 WAKEUP3 Input 25 NC LINR LINL AUXR AUXL - 26 Input 27 Input 28 Input 29 Input 30 Type Analog Digital Analog Analog Analog Analog Power Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Power Digital Digital Digital Digital Digital Digital Digital Analog Analog Analog Analog Function RTC supply Output for blinking led. Leave not connected if a LED is not wired. Measurement input 0 Measurement Input 1 Measurement Input 2 Measurement Input 3 PMU core supply PMU / Audio digital supply. Internal use only. No resistive load. PMU Voltage reference Resistor connection for PMU bias current PMU ground Audio Codec Mid-Supply reference Headset detector Headset output right Headset virtual ground output Headset output left Audio Codec ground Audio Codec supply input Interrupt request - Active low - Opendrain CPU reset - Active low - Open drain Two Wire Interface - Data Two Wire Interface - Clock Wake up 1 Input - VPAD level - 100k Pull down Wake up 2 Input - VPAD level - 100k Pull down Wake up 3 input - VPAD level - 100k Pull down Connect to DGND Audio Line input right Audio Line input left Audio auxiliary input right Audio auxiliary input left 11050A–PMAAC–07-Apr-10 AT73C246 5 Table 4-1. Pin Name MICLN MICRN MICR MICL MICBIAS VDD4 VIN4 VIN3 VDD3 DAO DAI BCLK LRFS MCLK VPAD NC NC NC MCLK32 VDD2 VIN2 VFB1 VIN1 SW1 GND1 VFB0 VIN0 SW0 GND0 HRST Pin Description I/O Pin Number Input 31 Input 32 Input 33 Input 34 Output 35 Output 36 Input 37 Input 38 Output 39 Output 40 Input 41 Input/Output 42 Input/Output 43 Input 44 Input 45 - 46 - 47 - 48 Output 49 Output 50 Input 51 Input 52 Input 53 Output 54 Ground 55 Input 56 Input 57 Output 58 Ground 59 Input 60 PWREN Input 61 WAKEUP0 Input 62 Type Analog Analog Analog Analog Analog Power Analog Power Analog Digital Digital Digital Digital Digital Power Digital Analog Power Analog Power Analog Analog Analog Analog Analog Analog Digital Digital Digital Function Audio negative microphone input left Audio negative microphone input right Audio positive microphone input right Audio positive microphone input left Voltage bias for electret microphone LDO4 output - 3.3V typ LDO4 input LDO3 input LDO3 output - 3.3V typ Digital audio port data output Digital audio port data input Digital audio port bit clock Digital audio port left/right clock Audio codec master clock input PMU I/O ring supply Leave open Connect to DGND Connect to DGND RTC clock output - VPAD level LDO2 output LDO2 input DCDC1 Voltage feedback input DCDC1 power stage supply DCDC1 power stage output DCDC1 power stage ground DCDC0 Voltage feedback input DCDC0 power stage supply DCDC0 power stage output DCDC0 power stage ground Hard reset - VBACKUP level - 100k Pull down Power on/off - VBACKUP level - 100k Pull down Wake up 0 input - VBACKUP level 100k Pull down 6 AT73C246 11050A–PMAAC–07-Apr-10 Table 4-1. Pin Name XIN XOUT DGND Pin Description I/O Pin Number Input 63 Output 64 Ground 65 Type Analog Analog Analog Function RTC crystal oscillator input RTC crystal oscillator output PMU digital ground + Thermal pad. AT73C246 7 11050A–PMAAC–07-Apr-10 5. Application Block Diagram Figure 5-1. AT73C246 Application Block Diagram VIN C42 10µF VDD4 VIN4 37 36 C41 10µF LINEJACK 100 R30 C40 1nF 3.3µF LINL 28 R29 C39 100K J1 AUXJACK C38 1nF R31 100 100 R26 C36 1nF R28 100K 3.3µF LINR 27 C37 3.3µF AUXL 30 R25 C35 100K J2 C34 1nF R24 100K 3.3µF AUXR 29 R27 100 C33 MIC_L 1µF C31 MICL 34 J3 R22 2K R23 2K MIC_R C32 1nF 1µF C29 MICLN 31 C30 1nF 1µF C27 MICR 33 J4 R19 2K R18 C28 2K 1nF 1µF C25 MICRN 32 C26 1nF VDD4 AVDD 18 MICBIAS 35 VMID 12 C23 1µF AGND 17 HEADSET 32ohms J5 HPDET 13 HPR 14 HPL 16 HPVCM 15 LINEOUT J6 R14 100 100 R15 C22 3.3µF R13 100K C21 3.3µF R12 100K C19 12p X1 C20 12p VBACKUP S3 PUSHBUTTON S2 VBACKUP PUSHBUTTON S1 VBACKUP PUSHBUTTON I²S to MCU MCLK LRFS BCLK DAI DAO XIN XOUT CLK32K WAKEUP0 HRST PWREN 44 43 42 41 40 63 64 49 62 100K 60 100K 61 100K LDO4 3.3V Max: 200mA (CODEC) AUDIO IN + ADC AUDIO BIAS AUDIO CODEC AUDIO OUT +DAC AUDIO PORT RTC + OSC VBACKUP R8 100 ANA_0 R9 100 ANA_1 R10 100 ANA_2 R11 100 ANA_3 C15 22nF C16 22nF C17 22nF C18 22nF ANA0 3 ANA1 4 ANA2 5 ANA3 6 ANALOG INPUTS 10b SAR ADC DIGITAL CORE 57 BUCK0 58 1.8V Max: 600mA 56 (CORE + MEM) 59 VIN0 SW0 VFB0 L1 2.2µH GND0 VDD0 C2 22µF VIN C1 10µF 53 BUCK1 54 1.2V Max: 600mA 52 (CORE) 55 VIN1 SW1 VFB1 L2 2.2µH GND1 VDD1 C4 22µF VIN C3 10µF 51 LDO2 1V Max: 300mA (CORE) 50 38 LDO3 3.3V Max: 200mA (I/O) 39 1 LDO5 2.5V Max: 10mA (BACKUP) 7 LDO6 1.8V / 10mA (Internal 8 functions) 10 PMU 9 BIAS 11 VIN2 C6 10µF C5 2.2µF VDD0 VDD2 VIN3 C8 10µF VIN C7 10µF VDD3 C9 2.2µF VBACKUP R1 2K Backup Battery VINSYS VINSYS C10 2.2µF C11 2.2µF REXT VBG GNDSYS VDDC C12 22nF R2 560k 1% + BAT1 PMU STATE MACHINES 20 19 23 100K 24 100K 25 100K 45 2 65 RSTB VDD0/VDD3 R3 4.7K C13 10nF ITB WAKEUP1 VDD0/VDD3 R4 4.7K C14 10nF WAKEUP2 From MCU WAKEUP3 VDD0/VDD3 VPAD LED DGND VIN R5 470 D1 TWI 22 21 TWCK TWD DIE TEMP SENSOR DCDC 4MHz RC OSCILLATOR SYSTEM 32KHz RC OSCILLATOR 46 NC 26 47 48 VDD0/VDD3 R6 4.7K VDD0/VDD3 R7 4.7K TWD TWCK To MCU TWI 8 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Table 5-1. Typical Application Components Design Schematic Reference Value Description R1, R18, R19, R22, R23 2kΩ 5% / 0.063W R2 560kΩ 1% / 0.063W R3, R4, R6,R7 4.7kΩ 5% / 0.063W R5 470Ω 5% / 0.063W R8, R9, R10, R11, R14, R15, R26, R27, R30, R31 100Ω 5% / 0.063W R12, R13, R24, R25, R28, R29 100kΩ 5% / 0.063W C1, C3, C6, C7, C8, C10, C41, C42 10µF X5R / 6.3V TDK: C1608X5R0J106MT MURATA: GRM188R60J106ME47 C2, C4 22µF X5R / 6.3V TDK: C2012X5R0J226M MURATA: GRM21BR60J226ME39 C5, C9, C11 2.2µF X5R / 6.3V C23, C25, C27, C29, C31 1µF X5R / 6.3V C13, C14 10nF X5R / 6.3V C15, C16, C17, C18, C12 22nF X5R / 6.3V C19, C20 12pF C0G / 25V C21, C22, C33, C35, C37, C39 3.3µF X5R / 6.3V C26, C28, C30, C32, C34, C36, C38, C40 1nF X5R L1, L2 2.2µH COILCRAFT: LPS3314-222 9 11050A–PMAAC–07-Apr-10 10 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 6. Absolute Maximum Ratings Table 6-1. Absolute Maximum Ratings Operating Temperature (Industrial).................-40 C to + 85⋅C(1) *NOTICE: Storage Temperature......................................-55°C to + 150°C Power Supply Input on VINSYS, VIN{0,1,3,4}, VPAD .. -0.3V to + 5.5V Power Supply Input on VIN2, AVDD ...................... -0.3V to + 3.6V Digital I/O Input Voltage...................................... -0.3V to + 5.5V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Other Pins.......................................................-0.3V to + 5.5V ESD (all pins).........................................2 KV HBM / 100V MM(2) Notes: 1. Refer to Power Dissipation Rating section 2. According to specifications MIL-883-Method 3015.7 (HBM - Human Body Model) / JESD22 A115 (MM - Machine Model) 7. Recommended Operating Conditions Table 7-1. Recommended Operating Conditions Parameter Operating Ambiant Temperature(1) Condition Power Supply Input Power Supply Input Power Supply Input Power Supply Input Power Supply Input VINSYS VIN{0,1,3,4} VIN2 AVDD VPAD Note: 1. Refer to Power Dissipation Rating section Min Max Units -40 85 °C 2.5 5.5 V 2.9 5.5 V 1.65 3.6 V 2.7 3.6 V 1.75 5.5 V 8. Power Dissipation Ratings Table 8-1. Recommended Operating Conditions Parameter Condition Min Typ Max Units Junction Temperature (Tj) -40 125 °C RTHjA(1) Package thermal junction to ambient resistance 30 35 °C / W Maximum On-chip Power Dissipation Ambient temperature = 70°C Ambient temperature = 85°C 1.8 1.6 W 1.3 1.1 W Note: 1. According to specification JESD51-5 11 11050A–PMAAC–07-Apr-10 9. PMU Electrical Characteristics 9.1 Current Consumption Versus Modes Table 9-1. Current Consumption Versus Modes Symbol Parameter Comments Min Typ Max Units VIN Operating Supply Voltage VINSYS, VIN{0,1,3,4} present. 2.9 3.6 5.5 V POWERDOWN Mode. All LDOs and DCDC converters OFF. Audio OFF. RTC running. - 20 40 µA IDD_VIN RUN Mode. All LDOs and DCDC converters running in PWM. Audio OFF. RTC - running. 7 15 mA STANDBY Mode. Default setup: DCDC0 ON in low- power mode. LDO3 ON. All other - functions OFF. 310 500 µA IDD_RTC All Modes. RTC running. Total current entering pin VBACKUP 1 5 µA 9.2 Supply Monitor Thresholds The following table applies to functional state diagrams of Figure 11-1 “AT73C246 Power Manager Functional State Diagram” on page 25 and Figure 11-2 “AT73C246 Start-up and Shutdown State Diagram” on page 26. Table 9-2. Supply Monitor Thresholds Symbol Parameter VIN > 3.1V VIN < 2.9V VIN > 2.7V VIN < 2.7V VBKP > 1.8V VBKP < 1.8V PMU Input 3.1V Rising Threshold PMU Input 2.9V Falling Threshold PMU Input 2.7V Rising Threshold PMU Input 2.7V Falling Threshold VBACKUP Input Rising Threshold VBACKUP Input Falling Threshold Comments Min 3.070 2.870 2.70 2.60 1.80 1.70 Typ 3.1 2.9 2.75 2.65 1.85 1.75 Max 3.130 2.930 2.85 2.70 1.90 1.80 Units V V V V V V 12 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 9.3 Digital I/Os DC Characteristics Table 9-3. Symbol VPAD Referred Digital I/Os Parameter Comments Min Typ Max Units VPAD VIL VIH VOH VOL IO RP Notes: Operating Supply Voltage 1.75 3.6 5.5 V Input Low-Level Voltage Input High-Level Voltage Output High-Level Voltage Output Low-Level Voltage Output Current IO max. IO max -0.3 - 0.3 x VPAD V 0.7 x VPAD - VPAD + 0.3 V 0.75 x VPAD - - V - - 0.25 x VPAD V - - 8 mA Pull-Up or Pull-Down Resistance When applicable. 70 100 145 kΩ 1. VPAD referred pins ITB, RSTB: open drain outputs. Only VOL and IO parameters are applicable. 2. VPAD referred pins WAKEUP1, WAKEUP2, WAKEUP3, MCLK, DAI, TWCK: CMOS inputs. Only VIH and VIL parameters are applicable. 3. VPAD referred pins MCLK32K, DAO: CMOS outputs. Only VOL, VOH and IO parameters are applicable. 4. VPAD referred pin TWD: CMOS input and open drain output. Only VIL, VIH, VOL, IO parameters are applicable. 5. VPAD referred pins LRFS, BCLK: CMOS BiDir. All parameters applicable Table 9-4. Symbol VBACKUP Referred Digital I/Os Parameter Comments Min Typ Max VBACKUP Operating Supply Voltage 1.75 2.5 2.65 VIL Input Low-Level Voltage -0.3 - 0.3 x VBACKUP VIH Input High-Level Voltage 0.7 x VBACKUP - VBACKUP + 0.3 VOH Output High-Level Voltage IO max. 0.75 x VBACKUP - - VOL Output Low-Level Voltage IO max - - 0.25 x VBACKUP IO Output Current - - 8 RP Pull-Up or Pull-Down resistance When applicable. 70 100 145 Note: VBACKUP referred pins PWREN, HRST, WAKEUP0: CMOS inputs. Only VIL and VIH parameters are applicable. Units V V V V V mA kΩ 13 11050A–PMAAC–07-Apr-10 9.4 DCDC0 and DCDC1 Unless otherwise specified: External components L=2.2μH, COUT=22μF and CIN=10μF. VIN{0,1} > VDD{0,1} + 500mV. TJ = [-40°C ; +125°C]. Table 9-5. DCDC0 and DCDC1 Electrical Characteristics Symbol Parameter Comments Min Typ Max Units VIN Operating Supply Voltage VIN0, VIN1 and VINSYS OFF 2.9 3.6 5.5 V - - 1 µA IDD Supply Current(1) IO Output Current PFM operation. VDD0 = 1.85V, VDD1 = 1.2V PWM operation. VDD0 = 1.85V, VDD1 = 1.2V PFM operation. PWM operation. - 40 80 µA - 3 6.5 mA - - 50 mA - - 600 mA fSW Switching Frequency PWM operation. 1.8 VDD0 Default Output Voltage(2) VDD0 - VDD1 VDD1 - VDD_RANGE Programmable Output Voltage Range PFM or PWM operation. 0.8 VDD_STEP NSTEP Output Voltage Steps Number of Output Steps PFM or PWM operation. In case of direct output voltage programming. Automatic ramping not active. 2 1.85 1.2 50 2.2 MHz - V - V 3.6 V mV 4 step / 100µs TSTEP Step time VDD_ACC DC Output Voltage Accuracy VDD_RIPPLE ΔVDD_IL Ripple Voltage Static Load Regulation Dynamic Load Regulation ΔVDD_VIN Static Line Regulation Eff Efficiency IINRUSH Inrush Current(1) With automatic ramping. 260 280 300 µs PFM; TJ = 25°C ; IO = 0 mA -1.5 2.5 PFM; TJ = [-40;125°C] ; IO = 0 mA -2 PWM; TJ = 25°C ; IO = 0 mA -1.5 3 % 1.5 PWM; TJ = [-40;125°C] ; IO = 0 mA -2 2 PWM operation. 2 mV PWM operation. IO ranging from 0 to IOMAX PWM. IO: 0 to IOMAX ; 1μs rise time PWM. IO: IOMAX to 0 ; 1μs fall time VIN0 and VINSYS from 2.9 to 5.5V VDD0 = 1.85V, VDD1 = 1.2V PWM. IOMAX load. VDD0= 1.85V. Relative to VIN0 input supply. PWM. IOMAX load. VDD1= 1.2V. Relative to VIN1 input supply. Current from VIN(0,1) and VINSYS from 0 to 100% VDD{0,1} VDD0 = 1.85V, VDD1 = 1.2V 2 5 mV -40 mV 40 5 mV 85 % 78 % 30 200 mA 14 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Table 9-5. DCDC0 and DCDC1 Electrical Characteristics Symbol Parameter Comments Min Typ Max OCP Over-Current Protection Output current. 1 1.4 1.8 TSTART Start-up Time From OFF to PWM operation. VDD(0,1) rising to 95% of final value. 5 TPWM PFM to PWM Settling Time No output load. 10 PWRFDET Power Fail Detector Threshold Accuracy Overload of the programmed threshold by 10mV / 5us min(3). -1 - +1 COUT Total Capacitive Load At VFB{0,1} pins. 8 36 Notes: 1. Current consumption without load. One DCDC converter ON, the other one OFF. 2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings. 3. Threshold levels are programmed in register PMU_RST_LVL (0x04) Units A ms µs %.VDD µF 15 11050A–PMAAC–07-Apr-10 9.5 LDO2 Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C]. Table 9-6. LDO2 Electrical Characteristics Symbol Parameter Comments Min Typ VIN Operating Supply Voltage VIN2 IDD Supply Current(1) OFF ON 1.65 1.8 - - - - IO VDD2 VDD_RANGE Output Current Default Output Voltage(2) Programmable Output Voltage Range VIN2 > VDD2 + 500mV. - - - 1 0.8 VDD_STEP TSTEP Output Voltage Steps Step time VDD_ACC DC Output Voltage Accuracy ΔVDD_IL Static Load Regulation Dynamic Load Regulation ΔVDD_VIN Static Line Regulation VDROPOUT Drop Out Voltage(4) IINRUSH Inrush Current With automatic ramping. 570 VIN2 > VDD2 + 500mV -1 TJ = 25°C ; IO = 0 mA VIN2 > VDD2 + 500mV -1.5 TJ = [-40°C ; 125°C] ; IO = 0 mA VIN2 > VDD2 + 500mV IO ranging from 0 to IOMAX VIN2 > VDD2 + 500mV IO: 0 to IOMAX ; 1μs rise time VIN2 > VDD2 + 500mV IO: IOMAX to 0 ; 1μs fall time IO = 0 mA VIN2 from 1.65 to 3.6V IO = 200mA IO = 300mA Current from VIN2 from 0 to 95% of final value. 50 600 0.05 -50 50 200 TSTART Start-up Time VDD2 OFF and rising to 95% of final value. IO = 0 mA PWRFDET Power Fail Detector Threshold Accuracy Overload of the programmed threshold by 10mV / 5us min(3). -1 - Notes: 1. Current consumption in VIN2 without load. 2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings. 3. Threshold level is programmed in register PMU_RST_LVL (0x04) 4. VDROPOUT= VIN2 - VDD2 when VDD2 = 98% of VDD2 obtained with VIN2 > VDD2 + 500mV Max 3.6 1 250 300 1.35 630 1 1.5 1 5 300 450 500 1 +1 Units V µA µA mA V V mV µs % %.VDD2 mV mV mV mV mA ms %.VDD2 16 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 9.6 LDO3 Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C]. Table 9-7. LDO3 Electrical Characteristics Symbol Parameter Comments Min Typ VIN Operating Supply Voltage VIN3 IDD Supply Current(1) OFF ON 2.9 3.6 - - - - IO VDD3 VDD_RANGE Output Current Default Output Voltage(2) Programmable Output Voltage Range VIN3 > VDD3 + 300mV. - - - 3.3 2.7 VDD_STEP Output Voltage Steps 50 TSTEP Step time With automatic ramping. 570 600 VDD_ACC DC Output Voltage Accuracy VIN3 > VDD3 + 300mV -1 TJ = 25°C ; IO = 0 mA VIN3 > VDD3 + 300mV -1.5 TJ = [-40°C ; 125°C] ; IO = 0 mA Static Load Regulation VIN3 > VDD3 + 300mV IO ranging from 0 to IOMAX 0.05 ΔVDD_IL Dynamic Load Regulation VIN3 > VDD3 + 300mV IO: 0 to IOMAX ; 1μs rise time -40 VIN3 > VDD3 + 300mV 40 IO: IOMAX to 0 ; 1μs fall time ΔVDD_VIN Static Line Regulation VIN3 > VDD3 + 300mV. IO = 0 mA VIN3 from 2.9 to 5.5V VDROPOUT Drop Out Voltage(4) IO = 10mA IO = 200mA VIN3 > VDD3 + 300mV 60 IO = 1mA. DC to 3kHz. PSRR Power Supply Rejection Ratio VIN3 > VDD3 + 300mV 50 IO = 10mA. DC to 3kHz. IINRUSH Inrush Current Current from VIN3 from 0 to 95% of final value. 200 TSTART Start-up Time VDD3 OFF and rising to 95% of final value. IO = 0 mA PWRFDET Power Fail Detector Threshold Accuracy Overload of the programmed threshold by 10mV / 5us min(3). -1 - Notes: 1. Current consumption in VIN3 without load. 2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings. 3. Threshold level is programmed in register PMU_RST_LVL (0x04) 4. VDROPOUT= VIN3 - VDD3 when VDD3 = 98% of VDD3 obtained with VIN3 > VDD3 + 300mV Max 5.5 1 350 200 3.6 630 1 1.5 0.5 5 50 250 500 1 +1 Units V µA µA mA V V mV µs % %.VDD3 mV mV mV mV dB mA ms %.VDD3 17 11050A–PMAAC–07-Apr-10 9.7 LDO4 Unless otherwise specified: External components COUT=10µF, CIN=10μF, TJ = [-40°C ; +125°C]. Table 9-8. LDO4 Electrical Characteristics Symbol Parameter Comments Min Typ VIN Operating Supply Voltage VIN4 IDD Supply Current(1) OFF ON 2.9 3.6 - - - - IO VDD4 VDD_RANGE Output Current Default Output Voltage(2) Programmable Output Voltage Range VIN4 > VDD4 + 300mV. - - - 3.3 2.7 VDD_STEP Output Voltage Steps 50 TSTEP Step time With automatic ramping. 570 600 VDD_ACC DC Output Voltage Accuracy VIN4 > VDD4 + 300mV -1 TJ = 25°C ; IO = 0 mA VIN4 > VDD4 + 300mV -1.5 TJ = [-40°C ; 125°C] ; IO = 0 mA Static Load Regulation VIN4 > VDD4 + 300mV IO ranging from 0 to IOMAX 0.05 ΔVDD_IL Dynamic Load Regulation VIN4 > VDD4 + 300mV IO: 0 to IOMAX ; 1μs rise time -40 VIN4 > VDD4 + 300mV 40 IO: IOMAX to 0 ; 1μs fall time ΔVDD_VIN Static Line Regulation VIN4 > VDD4 + 300mV. IO = 0 mA VIN4 from 2.9 to 5.5V VDROPOUT Drop Out Voltage(3) IO = 10mA IO = 200mA VIN4 > VDD4 + 300mV 60 IO = 1mA. DC to 3kHz. PSRR Power Supply Rejection Ratio VIN4 > VDD4 + 300mV 50 IO = 10mA. DC to 3kHz. IINRUSH Inrush Current Current from VIN4 from 0 to 95% of final value. 200 TSTART Start-up Time VDD4 OFF and rising to 95% of final value. IO = 0 mA Notes: 1. Current consumption in VIN4 without load. 2. Default output voltage are set during manufacturing. Please contact Atmel for other default settings. 3. VDROPOUT= VIN4 - VDD4 when VDD4 = 98% of VDD4 obtained with VIN4 > VDD4 + 300mV Max 5.5 1 350 200 3.6 630 1 1.5 0.5 5 50 250 500 1 Units V µA µA mA V V mV µs % %.VDD4 mV mV mV mV dB mA ms 18 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 9.8 LDO5 Unless otherwise specified: External components COUT=2.2µF, CIN=10μF, TJ = [-40°C ; +125°C]. Table 9-9. LDO5 Electrical Characteristics Symbol Parameter Comments Min Typ VIN Operating Supply Voltage VINSYS IDD Supply Current(1) OFF ON 2.7 3.6 - - - - IO VBACKUP ΔVDD_VIN ΔVDD_VIN IINRUSH TSTART Output Current Output Voltage Accuracy Static Line Regulation Static Line Regulation Inrush Current Start-up Time - - 2.42 2.5 VINSYS from 2.7 to 5.5V 3 VINSYS =3.6V, IO from 0 to IOMAX 10 Current from VINSYS from 0 to TSTART(MAX). VBACKUP = 2.5V 180 VBACKUP OFF and rising to 95% of final value. Note: 1. Current consumption in VINSYS without plugged backup battery Max Units 5.5 V 1 µA 7 µA 10 mA 2.58 V 10 mV 15 mV 350 mA 1 ms 19 11050A–PMAAC–07-Apr-10 9.9 Measurement Bridge and 10-bit ADC Table 9-10. Measurement Bridge and 10-bit ADC Electrical Characteristics Symbol VIN IDD Parameter Operating Supply Voltage(1) Supply Current Comments VINSYS OFF ON Min Typ 2.9 3.6 - - - - VREF Reference Voltage Internally connected to VDDC pin. 1.75 1.8 INL Integral Non Linearity End Point Method -2 - DNL Differential Non Linearity End Point Method -1 - Offset Offset Error -2 GAIN Gain Error -2 FS TACQ Sampling Rate 300 Track and Hold Acquisition Time 500 External inputs ANA{0,1,2,3} 0.4 VMEAS Measured Input Voltage Range VDD{0,1,2,3,4} inputs 0.4 VINSYS input 0.4 External inputs ANA{0,1,2,3} -1% 0.25 ATTMEAS Measured Input Scaling Factor VDD{0,1,2,3,4,5} inputs -1% 0.4 VINSYS input -1% 0.25 RIN_NOM ANA{0,1,2,3} Input resistance Tj = 25C 96 120 TJ [-40 ; +25]. Relative to RIN_TEMP RIN deviation with temperature RIN_NOM TJ [25 ; 125]. Relative to RIN_NOM -16 CIN ANA{0,1,2,3} Input capacitance Notes: 1. The 10-bit ADC is supplied from the regulated VDDC voltage (1.8V) which is generated from VINSYS. 2. Please refer to Atmel Data Converter Terminology literature Max 5.5 1 2 1.85 +2 +1 +2 +2 VINSYS 4 5.5 +1% +1% +1% 144 + 20 15 Units V µA mA V LSB LSB LSB LSB kS/s ns V V V V/V V/V V/V kΩ % pF 20 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 9.10 RTC Crystal Oscillator Table 9-11. RTC Crystal Oscillator Electrical Characteristics Symbol Parameter Comments Min Typ Max Units VIN Freq Operating Supply Voltage Frequency VBACKUP with crystal 1.75 2.5 2.65 V - 32.768 - kHz Duty Duty Cycle 40 50 60 % IDD Supply Current(1) OFF ON - - 5 nA - - 1.5 µA TON VXIN VXOUT RF Drift Startup Time Level Sinus Wave on XIN Vpp On XOUT Internal Resistor Accuracy CL= 12pF between xin and xout @25°C, +/- 20ppm - 1000 1500 ms 250 300 mVpp 300 mVpp 10 MΩ 1.5 mn/month Esr Equivalent Series Resistance Rs Crystal @ 32.768kHz 50 100 kΩ CM Motional Capacitance Crystal @ 32.768kHz 0.6 3 fF CSHUNT Shunt Capacitance Crystal @ 32.768kHz 0.6 2 pF CLOAD Load Capacitance Crystal @ 32.768kHz 6 12.5 pF Note: 1. Current consumption in VBACKUP with crystal. In case of crystal not present on-board, back-up batteries or supercapacitors, must be avoided. 9.11 Die Temperature Sensor Table 9-12. Symbol TSHUTDOWN TRESTART Die Temperature Sensor Electrical Characteristics Parameter Comments 130°C Shutdown Threshold 110°C Restart Threshold Min Typ Max 135 145 155 105 115 125 Units °C °C 21 11050A–PMAAC–07-Apr-10 10. Audio Codec Electrical Characteristics Unless otherwise specified: AVDD = 3.3V, TA = 25C, MCLK = 12.288MHz, FS = 48kHz. Master mode and 24-bit operation on I2S port. All gains set to 0dB, audio effects are off. Noise measurements are made in the [20Hz-20kHz] band using the A-Weighting filter. Distortion measurements are made from the 2nd to the 5th harmonic products of a 997Hz input sinewave. Input sources have an internal impedance of 50 Ohms. Audio Path without mixing capability. Table 10-1. Symbol AVDD Audio Codec Bias Parameter Operating Supply Voltage IDD Supply Current VMID TMID_ON TMID_OFF VMICBIAS RMICBIAS Mid-Supply Reference Voltage Time to charge VMID capacitor Time to discharge VMID capacitor Microphone Bias Reference Voltage Microphone Bias Reference Voltage Internal Resistance Comments OFF STANDBY From 0 to 95% of final value From 0 to 95% of final value No load. Min Typ Max Units 2.7 3.3 3.6 V 20 µA 1 mA -1% AVDD / 2 +1% V 350 ms/μF 700 ms/μF AVDD V 1.5 1.9 2.3 kΩ Table 10-2. Symbol VFS SNR DR THD XTALK GLINE RIN CIN Line Record Path: Line or Auxiliary Input to ADC Output Parameter Comments Full Scale Input Voltage(1) Corresponds to 0dBFs digital output signal. Signal-to-Noise Ratio(2) AVDD = 3.3V AVDD = 2.7V Dynamic Range(3) AVDD = 3.3V AVDD = 2.7V Total Harmonic Distortion Left / Right Channel separation(5) -1dBFS digital output Programmable Gain Range Gain Step Size Mute Attenuation(6) Input Resistance Input Capacitance Table 10-3. Symbol VFS SNR Microphone Record Path: Microphone Input to ADC Output Parameter Comments Full Scale Input Voltage(1) Corresponds to 0dBFs digital output signal. Signal-to-Noise Ratio(2) AVDD = 3.3V AVDD = 2.7V Min Typ Max AVDD / 3.3 85 96 - 82 93 - 85 96 - 82 93 - - -80 -74 80 90 - -34 0 12 - 1 - 80 - - 5.9 7 8.1 - - 10 Units VRMS dB dB dB dB dB dB dB dB dB kΩ pF Min Typ Max AVDD / 3.3 85 96 - 82 93 - Units VRMS dB dB 22 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Table 10-3. Symbol DR THD XTALK GLINE RIN CIN Microphone Record Path: Microphone Input to ADC Output Parameter Comments Dynamic Range(3) AVDD = 3.3V AVDD = 2.7V Total Harmonic Distortion Left / Right Channel separation(5) -1dBFS digital output Programmable Gain Range Gain Step Size Mute Attenuation(6) Input Resistance 0dB gain Input Capacitance Table 10-4. Playback Path: DAC Input to Headphone Output Symbol Parameter Comments VFS Full Scale Output Voltage(1) 0dBFs digital input signal. SNR DR THD PO XTALK GHS Signal-to-Noise Ratio(2) Dynamic Range(3) Total Harmonic Distortion Output Power Left / Right Channel Separation(5) Programmable Gain Range Gain Step Size Mute Attenuation(6) AVDD = 3.3V AVDD = 2.7V AVDD = 3.3V AVDD = 2.7V 0dBFs input - 10kΩ load 20mW output - 32Ω load 20mW output - 16Ω load 32Ω load - THD < -40dB or 1% 16Ω load - THD < -40dB or 1% 10kΩ AC coupled load 16Ω DC coupled load Min Typ Max 85 96 - 82 93 - - -84 -74 80 90 - 0 - 46 - 1 - 80 - - 8.4 12 15.6 - - 10 Min Typ Max AVDD / 3.3 92 97 - 89 94 - 92 97 - 89 94 - - -88 -80 - -65 -60 - -60 -55 30 50 90 60 -77 - +6 - 1 - 80 - - Table 10-5. Analog Bypass Path: Line / Auxiliary Input to Headphone Output Symbol Parameter Comments Min Typ Max VFS Full Scale Output Voltage(1) AVDD / 3.3 SNR Signal-to-Noise Ratio(2) AVDD = 3.3V AVDD = 2.7V 92 97 - 89 94 - DR Dynamic Range(3) AVDD = 3.3V AVDD = 2.7V 92 97 - 89 94 - Units dB dB dB dB dB dB dB kΩ pF Units VRMS dB dB dB dB dB dB dB mW mW dB dB dB dB dB Units VRMS dB dB dB dB 23 11050A–PMAAC–07-Apr-10 Table 10-5. Analog Bypass Path: Line / Auxiliary Input to Headphone Output Symbol Parameter Comments Min Typ Max Units 0dBFs input - 10kΩ load - -88 -80 dB THD Total Harmonic Distortion 20mW output - 32Ω load - -65 -60 dB 20mW output - 16Ω load - -60 -55 dB PO Output Power 32Ω load - THD < -40dB or 1% 16Ω load - THD < -40dB or 1% 30 mW 50 mW XTALK Left / Right Channel Separation(5) 10kΩ AC coupled load 16Ω DC coupled load 90 dB 60 dB GBYP Bypass Gain Mute Attenuation(6) -1 0 +1 dB 80 - - dB Table 10-6. Analog Sidetone Path: Microphone Input to Headphone Output Symbol Parameter Comments Min Typ Max Units VFS Full Scale Output Voltage(1) AVDD / 3.3 VRMS SNR Signal-to-Noise Ratio(2) AVDD = 3.3V AVDD = 2.7V 92 97 - dB 89 94 - dB DR Dynamic Range(3) AVDD = 3.3V AVDD = 2.7V 92 97 - dB 89 94 - dB 0dBFs input - 10kΩ load - -88 -80 dB THD Total Harmonic Distortion 20mW output - 32Ω load - -65 -60 dB 20mW output - 16Ω load - -60 -55 dB PO Output Power 32Ω load - THD < -40dB or 1% 16Ω load - THD < -40dB or 1% 30 mW 50 mW XTALK Left / Right Channel Separation(5) 10kΩ AC coupled load 16Ω DC coupled load 90 dB 60 dB Programmable Gain Range -30 - 0 dB GSIDETONE Gain Steps 2.5 3 3.5 dB Mute Attenuation(6) 80 - - dB Notes: 1. Full Scale: A linear extrapolation to 0dBFS of the measured level at -10dBFS. 2. Signal-to-Noise Ratio: The ratio of the RMS value of a 997Hz full scale sine wave to the RMS value of output noise with no signal applied. Device is not muted. 3. Dynamic Range: According to AES17-1991 (Audio Engineering Society) and EIAJ CP-307 (Electronic Industries Association of Japan), an extrapolation to 0dBFS input signal of the THD+N ratio measurement at -60dBFS. As an example, if THD+N @ -60dBFS = -36dB, then DR = 96dB. 4. Total Harmonic Distortion + Noise Ratio: The ratio of the RMS sum of the noise and the distortion components to the RMS value of the signal. 5. XTALK: Attenuation measurement from one channel to the other one. Measurement is performed by stimulated one channel with a 997Hz / -10dBFS sinewave and leaving the other channel unstimulated. 6. Mute Attenuation: Attenuation measurement of a -10dBFS / 997Hz input signal when concerned gain is set to mute. 24 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11. PMU Functional Description 11.1 Power Manager State Diagram Figure 11-1. AT73C246 Power Manager Functional State Diagram POWER-OFF or POWER-FAIL EVENT POWERDOWN (all supplies OFF) RSTB = 0 STANDBY-OUT or POWER-FAIL EVENT RUN (all supplies ON) RSTB = 1 POWER-ON EVENT & Vin > 3.1V HRST_POWERDOWN EVENT STANDBY EVENT HRST EVENT HRST EVENT WAKEUP EVENT STANDBY (selected supplies ON) RSTB = 0 HRST_RUN EVENT HRST (all supplies OFF) RSTB = 0 TWI Reset HRST EVENT AT73C246 is placed in POWERDOWN state at VINSYS rising following the PMU startup state diagram described in Figure 11-2 on page 26. From this POWERDOWN state, normal CPU supplies startup is achieved through validation of one of the POWER-ON events. From this state, the PMU may be placed in STANDBY state (e.g.: during CPU sleep periods) upon software request (STANDBY event). PMU wake-up is achieved if one of the WAKEUP events is detected. The PMU returns to the POWERDOWN state as soon as a POWER-OFF event is detected. A special HRST (Hard-Reset) state is provided to ensure complete stop and restart of the CPU supplies in case of a software crash. Moreover, die temperature and VDD{0,1,2,3} supplies are supervised and may generate a POWER-FAIL event in case of out-of-specification detection. 25 11050A–PMAAC–07-Apr-10 11.2 PMU Startup and Shutdown State Diagram Figure 11-2. AT73C246 Start-up and Shutdown State Diagram Vin > 2V Start : VINSYS Monitor & VDDC = 1.8V. PMU_RSTN = 0 AUDIO_RSTN = 0 VINSYS < 2.7V or VDDC_KO VINSYS > 2.7V & VDDC_OK PMU_RSTN = 1 AUDIO_RSTN = 1 1 1 READ CONFIG VBACKUP > 1.8V START LDO5 (BACKUP) VBACKUP > 1.8V VBACKUP < 1.8V RTC_RSTN = 0 1 START LDO5 (BACKUP) VBACKUP > 1.8V OFF LDO5 (BACKUP) RTC_RSTN = 1 POWER DOWN VINSYS < 2.7V The start-up of the AT73C246 follows the flow diagram of Figure 11-2 and aims at placing the power manager in the POWERDOWN state. When VINSYS rises above 2V: • An internal VINSYS monitor starts and holds the internal PMU_RSTN and AUDIO_RSTN signals to 0, thus forcing a complete reset of AT73C246. The PMU digital core supply voltage 26 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 (VDDC = 1.8V) is started. During this PMU reset, the ‘LED’ pin is driven to VINSYS (LED is OFF). • When VDDC is ready and VINSYS > 2.7V, the internal reset signals previously mentioned are released, thus enabling the PMU digital core functions. • Before starting the LDO5 (RTC supply), VBACKUP voltage is monitored and if it is lower than 1.8V, the RTC function is resetted. In case of VBACKUP > 1.8V, no reset is issued on the RTC function. • At this step, the power manager is placed in POWERDOWN state. 11.3 Power Manager Conditional Transitions 11.3.1 11.3.2 POWER-ON EVENTS POWER-ON EVENTS are validated if all these listed conditions are true: • VINSYS > 3.1V • AT73C246 internal junction temperature Tj < 110°C • PWREN pin is high for more than 100ms (see Table 11-1 on page 28). Note: PWREN pin, with internal 100k pull-down resistor, is active high (VBACKUP level). It is possible to hard wire the PWREN pin to VBACKUP to always activate RUN state when VINSYS > 3.1V. Consequently, using the software POWER-OFF EVENT (described in Section 11.3.2) will lead to going back to the RUN state just after the POWERDOWN STATE. POWER-OFF EVENTS POWER-OFF EVENTS are validated if one of these listed conditions is true: • VINSYS < 2.9V. • PWREN pin goes from low to high state and high state is held for more than 5s (see Table 11-1 on page 28). • Software request: bit 0 (OFF) of register 0x00 (PMU_MODES) is written to 1. 11.3.3 11.3.4 POWER-FAIL EVENTS POWER-FAIL EVENTS are validated if one of these listed conditions is true: • AT73C246 internal junction temperature Tj > 130°C • Any internal power fail detection signal coming from any CPU power supply (VDD0, VDD1, VDD2, VDD3) goes from low to high level. Note: In case of PWREN pin hard wired high (VBACKUP level), the POWER-FAIL EVENTS will lead to the POWERDOWN state without possibility to go to the RUN state. The power manager will be able to reach the RUN state only after an HRST event. This prevents the power manager from oscillating between RUN and POWERDOWN states in case of permanent failure on CPU supplies. STANDBY EVENT STANDBY EVENT is validated if the following condition is true: • Software request: bit 1 (STANDBY) of register 0x00 (PMU_MODES) is written to 1. 11.3.5 STANDBY-OUT EVENT STANDBY-OUT EVENT is validated if the following condition is true: • VINSYS < 2.9V. 27 11050A–PMAAC–07-Apr-10 11.3.6 WAKEUP EVENTS WAKEUP EVENTS are validated if one of the listed condition is true: • WAKEUP0 pin goes from low to high state and WAKEUP0 bit is set to ‘1’ (see Table 11-1) in register 0x01 (PMU_WAKEUP_EVENTS). • WAKEUP1 pin goes from low to high state and WAKEUP1 bit is set to ‘1’ (see Table 11-1) in register 0x01 (PMU_WAKEUP_EVENTS). • WAKEUP2 pin goes from low to high state and WAKEUP2 bit is set to ‘1’ (see Table 11-1) in register 0x01 (PMU_WAKEUP_EVENTS). • WAKEUP3 pin goes from low to high state and WAKEUP3 bit is set to ‘1’ (see Table 11-1) in register 0x01 (PMU_WAKEUP_EVENTS). • PWREN pin goes from low to high state and high state is held for more than 10ms (see Table 11-1) and PWREN bit is set to ‘1’ in register 0x01 (PMU_WAKEUP_EVENTS). • An RTC alarm occurs and RTC bit is set to ‘1’ in register 0x01 (PMU_WAKEUP_EVENTS). Notes: 1. WAKEUP0 and PWREN pins must be driven with VBACKUP level, WAKEUP{1,2,3} pins must be driven with VPAD level. 2. If any WAKEUP EVENT is triggered while AT73C246 is going from RUN to STANDBY state, STANDBY state is then first reached before WAKEUP EVENT is taken into account. 11.3.7 HRST EVENT HRST EVENT is validated if the following condition is true: • HRST pin goes from low to high state and high state is held for more than 1s (see Table 111). 11.3.8 HRST RUN EVENTS HRST RUN EVENTS are validated if all these listed conditions are true: • HRST pin is at low level for more than 10ms (see Table 11-1). • VINSYS > 3.1V • AT73C246 internal junction temperature Tj < 110°C Note: In case of 110°C < Tj < 130°C, HRST state is maintained. The self cooling down of the die will lead to Tj < 110°C, thus exit of HRST state. 11.3.9 HRST POWERDOWN EVENTS HRST POWERDOWN EVENTS are validated if all of these listed conditions are true: • HRST pin is at low level for more than 10ms. • VINSYS < 3.1V or AT73C246 internal junction temperature Tj >130°C Table 11-1. EVENTS Timing Table Pin Parameter Comments Min Typ Max PWREN PWREN PWREN HRST HRST Pin at VBACKUP Level. Debouncing Time. Pin used as POWER-ON event 95 100 105 Pin at VBACKUP Level. Debouncing Time. Pin used as POWER-OFF event 4.75 5 5.25 Pin at VBACKUP Level. Debouncing Time. Pin used as WAKEUP event 9.5 10 10.5 Pin at VBACKUP Level. Debouncing Time. Pin used as HRST event 0.95 1 1.05 Pin at GND Level. Debouncing Time. Pin used as HRST RUN event 9.5 Pin used as HRST POWERDOWN event 10 10.5 Units ms sec ms sec ms 28 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Table 11-1. Pin WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 EVENTS Timing Table Parameter Pin pulsed to VBACKUP Level. Pulse Width. Pin pulsed to VPAD Level. Pulse Width. Pin pulsed to VPAD Level. Pulse Width. Pin pulsed to VPAD Level. Pulse Width. Comments Pin used as WAKEUP event Pin used as WAKEUP event Pin used as WAKEUP event Pin used as WAKEUP event Min Typ Max Units 5 - - ns 5 - - ns 5 - - ns 5 - - ns 11.4 Power Manager State Description AT73C246 ICs are available with 2 factory programmed power sequences. The following timing diagrams refer to “SEQUENCE A” and “SEQUENCE B” programmed ICs as defined in section 17. “Ordering Information” on page 154. See also the structure of register “VERSION (0x7F)”. 11.4.1 POWERDOWN STATE When AT73C246 is in POWERDOWN state: • Only VBACKUP supply is active. VDD{0,1,2,3,4} power supplies are OFF. • Audio function is OFF. • ADC function is OFF. • RSTB pin is held low. • Led pin is set as input with internal 120k pull-up resistor to VINSYS. • TWI registers are reset to default value. When the POWERDOWN state is reached from the RUN state, the CPU power supplies are switched off sequentially as described in Figure 11-3 on page 30. 29 11050A–PMAAC–07-Apr-10 Figure 11-3. AT73C246 - RUN to POWERDOWN state Supplies Shutdown timing diagram. SEQUENCE A SEQUENCE B RUN STATE POWEROFF EVENT TPWRDOWN SUPPLIES SHUTDOWN POWERDOWN STATE RUN STATE POWEROFF EVENT TPWRDOWN SUPPLIES SHUTDOWN POWERDOWN STATE RSTB VDD3 (3.3V) VDD1 (1.2V) VDD0 (1.85V) VDD2 (1V) VDD4 (CODEC) TOFF_AUDIO 3.3V TOFF_VDD3 1.2V TOFF_VDD1 1.85V TOFF_VDD0 1V TOFF_VDD2 TOFF_VDD4 RSTB VDD2 (1V) VDD1 (1.2V) VDD0 (1.85V) VDD3 (3.3V) VDD4 (CODEC) TOFF_AUDIO 1V TOFF_VDD2 1.2V TOFF_VDD1 1.85V TOFF_VDD0 3.3V TOFF_VDD3 TOFF_VDD4 Table 11-2. Symbol TPWRDOWN TOFF_AUDIO TOFF_VDDx RUN to POWERDOWN state timing table Parameter Comments POWERDOWN Event detection time Audio CODEC Shutdown Time VDDx SHUTDOWN Time Audio CODEC is OFF or Power Fail Occurs Audio CODEC is ON VDDx is OFF in RUN state(1) VDDx is ON in RUN state(1) Note: 1. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL. Min Typ Max Units 58 62 66 µs 58 62 66 µs 486 512 538 ms 58 62 66 µs 4.8 5.2 5.4 ms 30 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 When the POWERDOWN state is reached from the STANDBY state, the CPU power supplies are switched off sequentially as described in Figure 11-4. Figure 11-4. AT73C246 - STANDBY to POWERDOWN state Supplies Shutdown timing diagram. SEQUENCE A SEQUENCE B STANDBY STATE STANDBY_OUT EVENT TSTBY_OUT SUPPLIES SHUTDOWN POWERDOWN STATE STANDBY STATE STANDBY_OUT EVENT TSTBY_OUT SUPPLIES SHUTDOWN POWERDOWN STATE RSTB VDD3 (3.3V) VDD1 (1.2V) VDD0 (1.85V) VDD2 (1V) VDD4 (CODEC) 3.3V TOFF_VDD3 1.2V TOFF_VDD1 1.85V TOFF_VDD0 1V TOFF_VDD2 TOFF_VDD4 RSTB VDD2 (1V) VDD1 (1.2V) VDD0 (1.85V) VDD3 (3.3V) VDD4 (CODEC) 1V TOFF_VDD2 1.2V TOFF_VDD1 1.85V TOFF_VDD0 3.3V TOFF_VDD3 TOFF_VDD4 Table 11-3. STANDBY to POWERDOWN state timing table Symbol Parameter Comments TSTBY_OUT TOFF_VDDx TOFF_VDD4 STANDBY OUT Event detection time VDDx SHUTDOWN Time VDD4 SHUTDOWN Time VDDx is OFF during STANDBY state(1) VDDx is ON during STANDBY state(1) VDD4 is OFF in RUN state(2) VDD4 is ON in RUN state(2) Min Typ Max Units 95 100 105 µs 58 62 66 µs 4.8 5.2 5.4 ms 58 62 66 µs 4.8 5.2 5.4 ms Notes: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES. 2. VDD4 activity during RUN state is set by Bit7 of register VDD4_CTRL. 11.4.2 RUN STATE When AT73C246 is in RUN state: • VDD{0,1,2,3,5} power supplies are ON. • RSTB pin is released. • PMU functions are under software control (LDO4, AUDIO CODEC, ADC Controller) • Led pin is driven according to register PMU_LED (0x0B). 31 11050A–PMAAC–07-Apr-10 When RUN state is reached from the POWERDOWN state, the power supplies are sequentially started-up according to the Figure 11-5 Figure 11-5. AT73C246 - POWERDOWN to RUN state Supplies Start-Up timing diagram.. SEQUENCE A SEQUENCE B POWERDOWN STATE PWREN EVENT VDD2 (1V) VDD0 (1.85V) VDD1 (1.2V) VDD3 (3.3V) RSTB SUPPLIES START UP RUN STATE TON_SYS 1V TON_VDD2 1.85V TON_VDD0 1.2V TON_VDD1 3.3V TON_VDD3 VPAD LEVEL TRESET POWERDOWN STATE PWREN EVENT VDD3 (3.3V) VDD0 (1.85V) VDD1 (1.2V) VDD2 (1V) RSTB SUPPLIES START UP RUN STATE TON_SYS 3.3V TON_VDD3 1.85V TON_VDD0 1.2V TON_VDD1 1V TON_VDD2 VPAD LEVEL TRESET Table 11-4. Symbol TON_SYS TON_VDD0 TON_VDD1 TON_VDD2 TON_VDD3 TRESET POWERDOWN to RUN state timing table Parameter Comments POWER-ON Event Detection Time VDD0 Start-up Time VDD1 Start-up Time VDD2 Start-up Time VDD3 Start-up Time All Regulators ON To RSTB High Min Typ Max Units 1.7 1.8 1.9 ms 5 5.3 5.6 ms 5 5.3 5.6 ms 5.2 5.5 5.8 ms 5.2 5.5 5.8 ms 30.4 32 33.6 ms 32 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 When RUN state is reached from the STANDBY state, the power supplies are sequentially started-up according to the Figure 11-6. Figure 11-6. AT73C246 - STANDBY to RUN state Supplies Start-Up timing diagram. SEQUENCE A SEQUENCE B STANDBY STATE SUPPLIES START UP RUN STATE WAKEUP EVENT VDD2 (1V) VDD0 (1.85V) PFM VDD1 (1.2V) PFM VDD3 (3.3V) RSTB TON_SYS 1V TPFM VDD3 ON or OFF TON_VDD2 1.85V VDD0 PWM TON_VDD0 1.2V VDD1 PWM TON_VDD1 3.3V TON_VDD3 TRESET VPAD LEVEL STANDBY STATE SUPPLIES START UP RUN STATE WAKEUP EVENT VDD3 (3.3V) VDD0 (1.85V) PFM VDD1 (1.2V) PFM VDD2 (1V) RSTB TON_SYS 3.3V VDD3 ON or OFF TPFM TON_VDD3 1.85V VDD0 PWM TON_VDD0 1.2V VDD1 PWM TON_VDD1 1V TON_VDD2 TRESET VPAD LEVEL Table 11-5. STANDBY to RUN state timing table Symbol Parameter Comments TON_SYS Start-up Time Time from validated WAKEUP event (end of debounce time when applicable) to VDD2 or VDD3 power on. TPFM PFM/PWM Switching time TON_VDDx VDDx Start-up Time Time from validated WAKEUP event (end of debounce time when applicable) to PFM/PWM switching if applicable. VDDx is OFF during STANDBY state(1) VDDx is ON during STANDBY state(1) TRESET All Regulators ON To RSTB High Min Typ Max Units 810 900 990 µs 420 470 520 µs 5.2 5.4 5.7 ms 58 62 66 µs 30.4 32 33.6 ms Note: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES. 11.4.3 STANDBY STATE When AT73C246 is in STANDBY state: • VBACKUP is ON. • VDD{0,1,2,3} are ON or OFF according to the status in register 0x03 (PMU_STANDBY_SUPPLIES) • VDD4 is ON or OFF according to the status in register 0x0A (VDD4_CTRL) • Audio function is OFF • ADC function is ON or OFF according to the status in register 0x30 (ADC_CTRL) • RSTB pin is forced to ground. • TWI pins are ignored to prevent TWI registers from corruption • Led pin is driven according to register PMU_LED (0x0B) To reach the STANDBY state, the appropriate power supplies are shut down as described in the Figure 11-7 on page 34. 33 11050A–PMAAC–07-Apr-10 Figure 11-7. AT73C246 - RUN to STANDBY state Supplies Shutdown timing diagram. SEQUENCE A SEQUENCE B RUN STATE STANDBY EVENT TSTANDBY SUPPLIES SHUTDOWN STANDBY STATE RUN STATE STANDBY EVENT TSTANDBY SUPPLIES SHUTDOWN STANDBY STATE RSTB VDD3 (3.3V) VDD1 (1.2V) PWM VDD0 (1.85V) PWM VDD2 (1V) TWAIT + TOFF_AUDIO TOFF_VDD3 3.3V TPWM 1.2V VDD1 PFM VDD0 PFM TOFF_VDD1 1.85V TOFF_VDD0 1V (VDD3 ON or OFF) 1.85V TOFF_VDD2 RSTB VDD2 (1V) VDD1 (1.2V) PWM VDD0 (1.85V) PWM VDD3 (3.3V) TWAIT + TOFF_AUDIO TOFF_VDD2 1V TPWM VDD1 PFM 1.2V VDD0 PFM TOFF_VDD1 1.85V TOFF_VDD0 3.3V (VDD3 ON or OFF) 1.85V TOFF_VDD3 Table 11-6. RUN to STANDBY state timing table Symbol Parameter Comments Min Typ Max Units TSTANDBY STANDBY Event Detection Time 150 160 170 µs TPWM PFM/PWM Switching time Time from validated WAKEUP event (end of debounce time when applicable) to PFM/PWM switching if 460 500 540 µs applicable. TWAIT WAKEUP Event Detection Window If a WAKEUP event occurs in this window the PMU automatically restart at the end of the STANDBY process. 150 160 170 µs TOFF_AUDIO Audio CODEC Shutdown Time Audio CODEC is ON Audio CODEC is OFF 486 512 538 ms 58 62 66 µs TOFF_VDDx VDDx SHUTDOWN Time VDDx is OFF during both STANBY(1) and RUN(2) states. 58 62 66 µs VDDx is OFF during STANBY state(1). VDDx is ON during RUN state(2). 4.8 5.2 5.4 ms TON_VDDx VDDx STARTUP Time VDDx is ON during STANBY state(1). VDDx is OFF during RUN state(2). 4.8 5.2 5.4 ms VDDx is ON during both STANBY(1) and RUN(2) states. 58 62 66 µs Note: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES. 2. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL. 11.4.4 HRST STATE HRST state is a transition state used to restart the CPU: • VDD{0,1,2,3,4} are switched off according to figure Figure 11-8 on page 35 depending on the previous state • VDD5 is ON • RSTB pin is forced to ground 34 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Figure 11-8. AT73C246 - HRST state Supplies Shutdown timing diagram. SEQUENCE A RUN / STANDBY / POWERDOWN STATE HRST_EVENT EVENT THRST SUPPLIES SHUTDOWN RSTB VDD3 (3.3V) VDD1 (1.2V) VDD0 (1.85V) VDD2 (1V) PMU FUNCTIONS (LDO4, ADC, LED,...) TOFF_AUDIO 3.3V TOFF_VDD3 1.2V TOFF_VDD1 1.85V TOFF_VDD0 1V TOFF_VDD2 TOFF_PMU HRST STATE SEQUENCE B RUN / STANDBY / POWERDOWN STATE HRST_EVENT EVENT THRST SUPPLIES SHUTDOWN RSTB VDD2 (1V) VDD1 (1.2V) VDD0 (1.85V) VDD3 (3.3V) PMU FUNCTIONS (LDO4, ADC, LED,...) TOFF_AUDIO 1V TOFF_VDD2 1.2V TOFF_VDD1 1.85V TOFF_VDD0 3.3V TOFF_VDD3 TOFF_PMU HRST STATE Table 11-7. Symbol THRST TOFF_AUDIO TOFF_VDDx TOFF_PMU HRST state timing table from RUN STATE Parameter Comments HRST Event Detection Time Audio CODEC Shutdown Time VDDx SHUTDOWN Time Audio CODEC is ON Audio CODEC is OFF VDDx is OFF in RUN state(1) VDDx is ON in RUN state(1) PMU Functions Shutdown Time Min Typ Max Units 58 62 66 µs 486 512 538 ms 58 62 66 µs 58 62 66 µs 4.8 5.2 5.4 ms 1.4 1.5 1.6 ms Note: 1. VDDx activity during RUN state is set by Bit7 of register VDDx_CTRL Table 11-8. HRST state timing table from STANDBY STATE Symbol Parameter Comments THRST HRST Event Detection Time TOFF_AUDIO TOFF_VDDx TOFF_VDD4 Audio CODEC Shutdown Time VDDx SHUTDOWN Time VDD4 SHUTDOWN Time Audio CODEC is ON Audio CODEC is OFF VDDx is OFF during STANDBY state(1) VDDx is ON during STANDBY state(1) VDD4 is OFF in RUN state(2) VDD4 is ON in RUN state(2) TOFF_PMU PMU Functions Shutdown Time Notes: 1. VDDx activity during STANDBY state is set by register PMU_STANDBY_SUPPLIES. 2. VDD4 activity during RUN state is set by Bit7 of register VDD4_CTRL. Min Typ Max Units 58 62 66 µs 486 512 538 ms 58 62 66 µs 58 62 66 µs 4.8 5.2 5.4 ms 58 62 66 µs 4.8 5.2 5.4 ms 1.4 1.5 1.6 ms 35 11050A–PMAAC–07-Apr-10 11.5 DCDC0 and DCDC1 Functional Description DCDC0 and DCDC1 are 2 identical high performance synchronous step-down (buck) converters. They feature: • 2 control modes: PFM and PWM, • A soft start circuit, • A software programmable output voltage between 0.8 and 3.6V with automatic ramping for DVS application, • An Over-Current-Protection circuit, • A 180 degree out of phase operating mode. 11.5.1 PFM and PWM Control Modes Pulse Frequency Modulation control is an hysteretic control of the output voltage. It is specially intended for light loads (< 50mA typ). In this mode, the DCDC converter exhibits a very low quiescent current (< 50µA) thus achieving very high efficiency at light loads. The frequency of operation in this mode is not fixed but proportional to the load current. Pulse Width Modulation control is a fixed frequency, variable duty cycle control of the DCDC converter. It has a fast and precise feedback loop specially intended to handle hard loads and low output ripple voltage. At start-up, DCDC0 and DCDC1 operate in PWM mode. This way, high load at CPU boot are properly handled. Through software control in registers VDD0_CTRL (0x06) and VDD1_CTRL (0x07), the user may enter the low-power mode (PFM) when the application consumption is reduced. 11.5.2 Soft-start Circuit DCDC0 and DCDC1 feature a soft start circuit to prevent high input current while charging the output capacitor from 0V to the default output voltage. Typically, the in-rush current at start-up (with no load) is limited to 30 mA. 11.5.3 Output Voltage Programming DCDC0 and DCDC1 output voltages can be managed through software control in registers VDD0_CTRL (0x06) and VDD1_CTRL (0x07). 50mV steps are provided from 0.8V to 3.6V. It is recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to achieve smooth operation. When the DVS_VDD{0,1} bit is active (default mode), output voltages are ramped from the current value to the final value in 50mV / 280us steps. For users who intend to disable the DVS_VDD{0,1} bit, a maximum of 4 steps (= 200mV) per 100us is allowed. At power up, DCDC0 and DCDC1 default output voltages are respectively 1.85V and 1.20V. For different default output voltages, please contact Atmel. 11.5.4 180° Out-of-phase Operation DCDC0 and DCDC1 can be operated in-phase or at 180° out-of-phase according to the selection bit in register PMU_SUPPLY_CTRL (0x04). When operated in phase both converters will start charging their inductor at the same time. When operated at 180° out-of-phase, the inductor charge start time will be shifted by half a 2MHz clock delay (= 250ns) from one converter to the other. This latter scheme tends to average the input current of both DCDC converters. 36 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11.6 LDO2 Functional Description LDO2 is a linear voltage regulator intended to supply CPU core voltages in the range 0.8V to 1.35V. Its maximum input voltage is 3.6V. Thus, it must not be wired to the VIN plane with VINSYS, VIN0, VIN1, VIN3 and VIN4 if VIN is above 3.6V. Considering its low-output voltage and for the sake of efficiency and power dissipation, the user may connect it at the output of DCDC0. This LDO features: • A soft start circuit, • A software programmable output voltage between 0.8 and 1.35V with automatic ramping for DVS application. 11.6.1 Soft-start Circuit LDO2 features a soft start circuit to prevent high input current while charging the output capacitor from 0V to the default output voltage. This soft start circuit limits the input current during 5ms (+/-5%) at startup to 200mA in typical conditions. After this delay, LDO2 recovers full current capability. 11.6.2 Output Voltage Programming LDO2 output voltage can be managed through software control in register VDD2_CTRL (0x08). 50mV steps are provided from 0.8V to 1.35V. It is recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to achieve smooth operation. When the DVS_VDD2 bit is active (default mode), output voltages are ramped from the current value to the final value in 50mV / 600us steps. At power up, LDO2 default output voltage is 1V. For different default output voltage, please contact Atmel. 11.7 LDO3 and LDO4 Functional Description LDO3 and LDO4 are low dropout linear voltage regulators intended to supply CPU peripherals (I/Os, analog functions) in the range 2.7V to 3.6V. They can be operated directly from a 5.5V maximum input voltage. They feature: • A soft start circuit, • A software programmable output between 2.7V and 3.6V voltage with automatic ramping for DVS application, 11.7.1 Soft-start Circuit LDO3 and LDO4 feature a soft start circuit to prevent high input current while charging the output capacitor from 0V to the default output voltage. This soft start circuit limits the input current during 5ms (+/-5%) at startup to 200mA in typical conditions. After this delay, LDO3(4) recovers full current capability. 11.7.2 Output Voltage Programming LDO3 and LDO4 output voltages can be managed through software control in registers VDD3_CTRL (0x09) and VDD4_CTRL (0x0A). 50mV steps are provided from 2.7V to 3.6V. It is recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to achieve smooth operation. When the DVS_VDD{3,4} bit is active (default mode), output voltages are ramped from the current value to the final value in 50mV / 600us steps. 37 11050A–PMAAC–07-Apr-10 At power up, LDO3 an LDO4 default output voltages are both 3.3V. For different default output voltages, please contact Atmel. 11.8 Power Fail Detectors AT73C246 features a Power Fail detector on each CPU supplies (VDD0, VDD1, VDD2, VDD3). This function is made of a comparator that toggles each time one the listed power supplies goes below a defined threshold. The comparator toggling is considered by the PMU digital state machine as a POWER-FAIL event. The threshold value of the power fail detector is proportional to the output voltage of the regulator. It is not a fixed voltage, it is adapted to the programmed output voltage. The default threshold value is set according to register PMU_RST_LVL (0x05) and can be programmed to another value through TWI access. For other default threshold values at startup, please contact Atmel. 11.9 Measurement Bridge and 10-bit ADC AT73C246 features a 10-channel measurement chain including: • A multiplexer + attenuator followed by a unity gain buffer • A 300kS/s 10-bit SAR ADC. ADC function is enabled through the register ADC_CTRL (0x30). ADC_MUX_1 (0x31) and ADC_MUX_2 (0x32) allow the selection of inputs to be measured. 1 to 10 inputs can be selected. The ADC will then perform serial conversion on these inputs and write the corresponding result in registers 0x33 to 0x49. 2 sampling modes are provided to perform periodic conversions: • Max speed • Low speed. To enter these modes, refer to the sampling period bits (TS) in the register ADC_CTRL (0x30). When MAX_SPEED mode is selected, the ADC runs at 300kS/s and loop without any dead time over the selected inputs. When a LOW_SPEED sampling period is selected, the ADC performs a set of input conversions (1 to 10) at 300kS/s and then wait for one sampling period (defined by TS bits) to start another set of conversions. 38 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Figure 11-9. Measurement Bridge and 10-bit ADC Block Diagram. ADC_MUX_1 0x31 ADC_MUX_2 0x32 VINSYS VDD0 VDD1 VDD2 VDD3 VDD4 ANA0 ANA1 ANA2 ANA3 10-channel resistive attenuator MUX 10 1 BUFFER VDDC VREFP ADC VREFN GNDSYS TWI Registers ADC_ANA0_MSB 0 ADC_ANA0_LSB 0 ADCOUT <9:0> ADC_ANA_LSB 0 ADC_CTRL 0x30 39 11050A–PMAAC–07-Apr-10 11.10 Real Time Clock (RTC) User Interface Figure 11-10. RTC Block Diagram RTC_SEL RTC CTRL RTC_EN RTC_WRITE RTC DATA 3 RTC DATA 2 RTC DATA 1 RTC DATA 0 RTC CONTROL REGISTER MODE REGISTER TIME REGISTER CALENDAR REGISTER TIME ALARM REGISTER CALENDAR ALARM REGISTER STATUS REGISTER STATUS CLEAR COMMAND REGISTER INTERRUPT ENABLE REGISTER INTERRUPT DISABLE REGISTER INTERRUPT MASK REGISTER VALID ENTRY REGISTER VERSION REGISTER RESERVED REGISTER RTC ADDR Table 11-9. Register Mapping Offset Register Name 0x00 Control Register RTC_CR 0x04 Mode Register RTC_MR 0x08 Time Register RTC_TIMR 0x0C Calendar Register RTC_CALR 0x10 Time Alarm Register RTC_TIMALR 0x14 Calendar Alarm Register RTC_CALALR 0x18 Status Register RTC_SR 0x1C Status Clear Command Register RTC_SCCR 0x20 Interrupt Enable Register RTC_IER 0x24 Interrupt Disable Register RTC_IDR 0x28 Interrupt Mask Register RTC_IMR 0x2C 0xFC Valid Entry Register Version Register(1) RTC_VER RTC_VERSION 0xFC Reserved Register --- Note: 1. Values in the Version Register vary with the version of the IP block implementation. Access Read-write Read-write Read-write Read-write Read-write Read-write Read-only Write-only Write-only Write-only Read-only Read-only Read-only --- Reset 0x0 0x0 0x0 0x01819819 0x0 0x01010000 0x0 ------0x0 0x0 ----- 40 AT73C246 11050A–PMAAC–07-Apr-10 11.10.1 RTC Register Read/Write Operation Figure 11-11. RTC Read Operation AT73C246 TWI ACCESS RTC_ADDR WRITE RTC_ADDR WRITE 02 @RTC_CTRL RTC_EN = 0 RTC_SEL = 1 RTC_WRITE = 0 WRITE 03 @RTC_CTRL RTC_EN = 1 RTC_SEL = 1 RTC_WRITE = 0 WRITE 02 @RTC_CTRL RTC_EN = 0 RTC_SEL = 1 RTC_WRITE = 0 READ RTC_DATA3 READ RTC_DATA2 READ RTC_DATA1 READ RTC_DATA0 WRITE 00 @RTC_CTRL RTC_EN = 0 RTC_SEL = 0 RTC_WRITE = 0 RTC_DATA RTC_EN RTC_SEL RTC_WRITE Figure 11-12. RTC Write Operation TWI ACCESS WRITE RTC_ADDR RTC_ADDR WRITE RTC_DATA3 WRITE RTC_DATA2 WRITE RTC_DATA1 WRITE RTC_DATA0 WRITE 06 @RTC_CTRL RTC_EN = 0 RTC_SEL = 1 RTC_WRITE = 1 WRITE 07 @RTC_CTRL RTC_EN = 1 RTC_SEL = 1 RTC_WRITE = 1 WRITE 06 @RTC_CTRL RTC_EN = 0 RTC_SEL = 1 RTC_WRITE = 1 WRITE 00 @RTC_CTRL RTC_EN = 0 RTC_SEL = 0 RTC_WRITE = 0 RTC_DATA RTC_EN RTC_SEL RTC_WRITE 41 11050A–PMAAC–07-Apr-10 11.10.2 RTC Control Register Name: RTC_CR Access: Read-write Address: 0x00 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – CALEVSEL 15 14 13 12 11 10 – – – – – – 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. • UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. 0 = Minute change. 1 = Hour change. 2 = Every day at midnight. 3 = Every day at noon. • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL. 0 = Week change (every Monday at time 00:00:00). 1 = Month change (every 01 of each month at time 00:00:00). 2, 3 = Year change (every January 1 at time 00:00:00) 42 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11.10.3 RTC Mode Register Name: RTC_MR Access: Read-write Address: 0x04 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero. 43 11050A–PMAAC–07-Apr-10 11.10.4 RTC Time Register Name: RTC_TIMR Access: Read-write Address: 0x08 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM HOUR 15 14 13 12 11 10 9 8 – MIN 7 6 5 4 3 2 1 0 – SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. 44 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11.10.5 RTC Calendar Register Name: RTC_CALR Access: Read-write Address: 0x0C 31 30 29 28 27 26 25 24 – – DATE 23 22 21 20 19 18 17 16 DAY MONTH 15 14 13 12 11 10 9 8 YEAR 7 6 5 4 3 2 1 0 – CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Date The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 45 11050A–PMAAC–07-Apr-10 11.10.6 RTC Time Alarm Register Name: RTC_TIMALR Access: Read-write Address: 0x10 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR 15 14 13 12 11 10 9 8 MINEN MIN 7 6 5 4 3 2 1 0 SECEN SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. 46 AT73C246 11050A–PMAAC–07-Apr-10 11.10.7 RTC Calendar Alarm Register Name: RTC_CALALR Access: Read-write Address: 0x14 31 30 29 28 DATEEN – 23 22 21 20 MTHEN – – 15 14 13 12 – – – – 7 6 5 4 – – – – 27 26 DATE 19 18 MONTH 11 10 – – 3 2 – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. AT73C246 25 24 17 16 9 8 – – 1 0 – – 47 11050A–PMAAC–07-Apr-10 11.10.8 RTC Status Register Name: RTC_SR Access: Read-only Address: 0x18 31 30 29 – – – 23 22 21 – – – 15 14 13 – – – 7 6 5 – – – 28 – 20 – 12 – 4 CALEV 27 – 19 – 11 – 3 TIMEV 26 – 18 – 10 – 2 SEC 25 – 17 – 9 – 1 ALARM 24 – 16 – 8 – 0 ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred. 1 = An alarm matching condition has occurred. • SEC: Second Event 0 = No second event has occurred since the last clear. 1 = At least one second event has occurred since the last clear. • TIMEV: Time Event 0 = No time event has occurred since the last clear. 1 = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event 0 = No calendar event has occurred since the last clear. 1 = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 48 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11.10.9 RTC Status Clear Command Register Name: RTC_SCCR Access: Write-only Address: 0x1C 31 30 29 28 – – – – 23 22 21 20 – – – – 15 14 13 12 – – – – 7 6 5 4 – – – CALCLR 27 – 19 – 11 – 3 TIMCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). 26 – 18 – 10 – 2 SECCLR 25 – 17 – 9 – 1 ALRCLR 24 – 16 – 8 – 0 ACKCLR 49 11050A–PMAAC–07-Apr-10 11.10.10 RTC Interrupt Enable Register Name: RTC_IER Access: Write-only Address: 0x20 31 30 29 – – – 23 22 21 – – – 15 14 13 – – – 7 6 5 – – – 28 – 20 – 12 – 4 CALEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0 = No effect. • 1 = The selected calendar event interrupt is enabled. 27 – 19 – 11 – 3 TIMEN 26 – 18 – 10 – 2 SECEN 25 – 17 – 9 – 1 ALREN 24 – 16 – 8 – 0 ACKEN 50 AT73C246 11050A–PMAAC–07-Apr-10 11.10.11 RTC Interrupt Disable Register Name: RTC_IDR Access: Write-only Address: 0x24 31 30 29 – – – 23 22 21 – – – 15 14 13 – – – 7 6 5 – – – 28 – 20 – 12 – 4 CALDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. 27 – 19 – 11 – 3 TIMDIS 26 – 18 – 10 – 2 SECDIS AT73C246 25 – 17 – 9 – 1 ALRDIS 24 – 16 – 8 – 0 ACKDIS 51 11050A–PMAAC–07-Apr-10 11.10.12 RTC Interrupt Mask Register Name: RTC_IMR Access: Read-only Address: 0x28 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. 52 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11.10.13 RTC Valid Entry Register Name: RTC_VER Access: Read-only Address: 0x2C 31 30 29 – – – 23 22 21 – – – 15 14 13 – – – 7 6 5 – – – 28 27 26 – – – 20 19 18 – – – 12 11 10 – – – 4 3 2 – NVCALALR NVTIMALR • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. 25 – 17 – 9 – 1 NVCAL 24 – 16 – 8 – 0 NVTIM 53 11050A–PMAAC–07-Apr-10 11.10.14 RTC Version register Name: RTC_VERSION Access: Read-only Address: 0xFC 31 30 29 – – – 23 22 21 – – – 15 14 13 – – – 7 6 5 28 27 – – 20 19 – – 12 11 – 4 3 VERSION 26 25 24 – – – 18 17 16 MFN 10 9 8 VERSION 2 1 0 • VERSION Reserved. Value subject to change. No funcionality associated. This is the Atmel internal version of the macrocell. • MFN Reserved. Value subject to change. No funcionality associated. 11.11 Die Temperature Sensor The AT73C246 features a die temperature sensor for protection reasons. If the junction temperature rises above the shutdown threshold for a minimum time of 1ms (+/- 5%), the power manager event TJ > 130°C is asserted. In a similar fashion, if the temperature falls through the restart threshold for more than 1ms, the power manager event TJ <110°C is asserted. The two internal thresholds shutdown and restart are defined in Section 9.11 “Die Temperature Sensor” on page 21. 54 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 12. Audio Codec Functional Description 12.1 Description AT73C246 features a high quality, low power stereo audio codec with integrated headphone amplifier. The playback channel accommodates 16 to 24-bit stereo programmable format entering the digital audio interface (I2S) and delivers an internal analog audio output through a 100dB SNR Sigma Delta Stereo DAC. An output mixer allows to mix this DAC output with a line / aux or microphone input. A 16-32 Ohms Stereo headphone amplifier with virtual ground output provides a 97dB SNR output for line / headphone loads. The virtual ground output allows to remove 2 space demanding coupling capacitors on board. On the record side, a multiplexer can select between a main stereo line input and a stereo auxiliary input such as an FM radio. A stereo microphone input with up to 46dB gain is provided. A stereo input mixer allows mixing between line (or aux) and microphone channels before entering a 96dB SNR Stereo Sigma Delta ADC. The digital audio signal is then digitally filtered and transferred to the I2S audio interface. 12.2 Audio Codec Block Diagram Figure 12-1. Audio Codec Block Diagram LINL AUXL MICL MICLN MICR MICRN LINR AUXR MUX -34 -> +12dB 1dB Step 0 -> +46dB 1dB Step 0 -> +46dB 1dB Step -34 -> +12dB MUX 1dB Step BYPASS 0 -> -30dB 1dB Step ADC DAC DSP + Audio Controller ADC DAC 0 -> -30dB 1dB Step -77/+6dB 1dB Step VMID -77/+6dB 1dB Step HPL HPVCM HPR HPDET BYPASS Codec Bias 2K 200K 200K I²S MICBIAS AVDD VMID AGND PAO DAI LRFS BCLK MCLK 55 11050A–PMAAC–07-Apr-10 12.3 Audio Codec Controls Figure 12-2. Audio Codec Controls RHSBOTH LHSBOTH ENASR ASRTIME STDBY ENAC LINBOTH RINBOTH PATHSEL BCLKINV MASTER MCLKSEL SSCMODE WL DAIMODE SELFS 56 AT73C246 TWI I2S INTERFACE AUDIO CONTROLLER LINEINL AUXINL MICL MICLN MICR MICRN LINEINR AUXINR Gain Control -35 to 12dB 1dB step INLVOL MUTEINL ONLINL LINESEL MICLDIFF MICLVOL MUTEMICL ONMICL 0 to +46dB 1dB step MIXLINEL MIXMICL 0 to +46dB 1dB step MICRVOL MUTEMICR ONMICR MIXMICR MICRDIFF LINESEL INRVOL MUTEINR ONLINR Gain Control -35 to +12dB 1dB step MIXLINER ONMICBIAS MICDETLEV 2K ONMICBIAS 200K 200K + ONMIXL ADCL ONADCL ONBYPASS GSDT ONSIDETONE Sidetone -30 to +0dB 3dB step FX3D EQUALIZER MUTEDAC L DEEMP DACL ONPLAYBACK + ONDACL -77 to 6dB 1dB step HPLVOL ONHPL MUTEHPL DCBLOCK SWAPDAC MONODAC Digital Processor SWAPADC MONOADC VMID DCBLOCK + ONMIXR ADCR ONADCR FX3D EQUALIZER MUTEDACR DEEMP ONDACR DACR ONPLAYBACK + -77 to 6dB 1dB step HPRVOL ONHPR MUTEHPR DCBLOCK ONBYPASS GSDT ONSIDETONE Sidetone -30 to +0dB 3dB step ONHPL/R MICBIAS AVDD VMID AGND HPL HPVCM HPR HPDET 11050A–PMAAC–07-Apr-10 AT73C246 12.4 Audio Controller The audio controller sequences the power-up and power-down of the audio codec sub-functions (Mic.amp / ADC / DAC / …). During these transitioning phases, the controller also manages the gain steps to fade them in and out, thus providing smooth operation. Depending on the application, two modes are provided: 1. Automatic path control Dedicated to the major audio path scenarios (those described in Table 13-25 on page 95), this mode enables the whole audio path setup only via "PATHSEL" bits in register AUTOSTART (0x10). 2. Custom path control Dedicated to audio path scenarios not described in the previously mentioned table, this mode brings the flexibility to start manually the audio sub-functions. The following figure shows the global context of the audio codec control. Figure 12-3. Audio Codec Typical Control Sequence 1 Apply Supply & MCLK Configure Registers to set : - AUDIO_CONTROL (0x11) 2 Analog & Digital (Set DCBlock bit here) Interfaces - MIC_CONTROL (0x12) - DAI_CONTROL (0x13) - FRAME_CONTROL (0x14) Automatic path 6 control Custom path control Registers to set - See dedicated sections. Register to set : 3 Unmute Codec - MUTE (0x15) 7 Shutdown Audio Codec Register to set : - AUTOSTART (0x10) Start Audio 4 Codec in Standby Register to set : - AUTOSTART (0x10) 5 Software Wait Typically 350ms. - See VMID section. 8 Software Wait At least 1s. - See “Power-off Time” section. 9 Unset DCBLOCK bit Register to set : - AUDIO_CONTROL (0x11) - See “AC/DC coupled load management” section. 10 Remove & supply MCLK 57 11050A–PMAAC–07-Apr-10 12.4.1 Audio Codec General Recommendations 12.4.1.1 VMID • VMID is the common mode voltage of the audio codec analog core. It is recommended to decouple this voltage with a 1uF capacitor to ensure low noise operation as well as slow (thus silent) transients at codec power up and power down. • The VMID capacitor is charged and discharged whenever the ENAC bit is set or cleared. Particularly, placing the audio codec in STANDBY mode does not discharge the VMID capacitor. The software WAIT operations in the previous diagram (step #5 and step #8 in “Audio Codec Typical Control Sequence” on page 57) should accommodate VMID's settling time constant. See “Audio Codec Bias” on page 22.. 12.4.1.2 AC / DC Coupled Load Management • By default the audio codec is in DC-coupled load configuration: DCBLOCK = 0 in register AUDIO_CONTROL(0x11). In this case, a virtual ground voltage is provided on pin HPVCM (a buffered version of VMID). It allows to directly connect headphones or line loads between HPVCM and HPL(or R) without any coupling capacitors. To prevent any audio pop at start-up or shutdown in this DC coupling mode, the audio codec fastly starts HPL, HPR and HPVCM outputs shorted all together. No software management is required to achieve pop-less operation. • If output loads are AC coupled to the headphone amplifier, the audio codec DCBLOCK bit must be set and unset as described in “Audio Codec Typical Control Sequence” on page 57. This bit partially controls the two switches S1 and S2 described in the following figure. When DCBLOCK = 1 and the headphone amplifier is OFF, the output coupling capacitors are charged and discharged by the amplifier “VMID_BUFFER”. In order to achieve silent startup and shutdown, the following rules must be respected: – DCBLOCK = 0 at supply power-on and power-off. This ensures that the LDO4 power-on and power-off transients are not transmitted to the audio loads. – DCBLOCK = 1 when ENAC = 1. Particularly, DCBLOCK must be set before ENAC=1 and unset after ENAC=0. This ensures that the full VMID waveform is properly buffered to the output loads. – DCBLOCK = 1 after ENAC = 0 and until VMID capacitor is fully discharged. At codec shutdown (ENAC=0), VMID will discharge slowly. The VMID_BUFFER ensures slow and silent discharge of the output coupling capacitors, and needs S1 and S2 to be closed. 58 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Figure 12-4. AC / DC Coupled Load Management Schematic View 10uF 1uF VIN4 LDO4 VDD4 AVDD VMID ENAC 200k AT73C246 VMID BUFFER AGND 200k LEFT HPL S1 DCBLOCK.ONHP S2 RIGHT HPR CL RL CR RR Figure 12-5. Audio Codec Typical Startup and Shutdown Waveforms With AC Coupled Loads. VDD4 VMID HP(L/R) DCBLOCK ENAC STANDBY S1 & S2 S1 AND S2 OPENED BY AUDIO CODEC 12.4.1.3 12.4.1.4 12.4.1.5 MUTE Register By default, the audio codec starts muted. To enable the audio processing, the MUTE register (0x15) must be cleared. Unmute operation can be performed before or after releasing the STANDBY mode. During operation, this register provides a convenient way of muting the audio signal without changing the various gain registers. Master Clock Input (MCLK) The Audio Controller is clocked by MCLK pin. Therefore a clock must be present at this pin before each codec control change. Particularly, the master clock must be present at power-on, power-off, gain change, path change. The master clock must also be available when fully analog path are used. Power-off Conditions Three audio codec power-off conditions can occur: • Sofware request (ENAC = 0 in AUTOSTART register). In this case, the codec is smoothly powered off by the audio controller. • PMU Power-off event or Standby event (as defined in Section 11.3 “Power Manager Conditional Transitions” on page 27). In this case, the codec is smoothly powered off with a 59 11050A–PMAAC–07-Apr-10 12.4.1.6 500ms timeout. Contrary to the first point, which has no timeout, the audio power-off time limit is here fixed to 500ms. Beyond this limit, the codec is hardly reseted as in the following point. • PMU Power-fail event. In this case, the PMU finite state machine makes an immediate hard reset of the audio codec to ensure fast shutdown. This case may generate an audible click / pop noise. Power-off Time At power-off, the audio controller needs to perform several controls on audio codec sub-functions and to discharge the output coupling capacitors. Therefore, the codec’s power-off time is divided into: • a digital power-off time and, • an analogue one. During this power-off phase, the codec‘s master clock and supply must be present. See “Audio Codec Power-off Waveforms” on page 60. Figure 12-6. Audio Codec Power-off Waveforms VDD4 MCLK ENAC VMID AUDIO SIGNAL digital power-off time analog power-off time The digital power-off time depends on the number of controls (power-off, gain steps ramping, ...) to perform and for this reason strongly varies according to: • the master clock frequency, • the current path, • the current gains and • the current Automatic Soft Ramping time (ASR_TIME in AUDIO_CONTROL(0x11)). In worst case conditions (slowest clock, maximum ASR_TIME, maximum complexity audio path, maximum gains everywhere), the power-off time reaches 3 seconds. During this period, the 60 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 master clock must be running to properly shutdown the codec. This time linearly varies with ASR_TIME value. See Table 12-1 Table 12-1. ASR_TIME 00 01 10 11 Audio Codec Maximum Power-off Time Power-off time (ms) 375 750 1500 3000 The analog power-off time corresponds to the VMID’s discharge time specified in “Audio Codec Bias” on page 22: TMID_OFF. Finally, the wait step #8 in “Audio Codec Typical Control Sequence” on page 57 needs to accomodate the digital power-off time + the analog power-off time. 12.4.2 Automatic Path Configuration In this automatic path mode, the audio path control is fully managed by the AUTOSTART(0x10) register and more precisely by the following bits: • ENAC (Enable Audio codec), • STANDBY(1) (Audio standby) and • PATHSEL (Audio path selection). When the audio controller detects a change in these bits, it generates sequential controls to the audio codec sub-functions (power-up, gain ramping, unmute,…) with the right timing and order. Notes: 1. Audio STANDBY does not refer to the PMU STANDBY state as defined in “AT73C246 Power Manager Functional State Diagram” on page 25. The audio STANDBY mode activated by register AUTOSTART (0x10) only refers to the audio codec controller. 12.4.2.1 STANDBY Release Once the CODEC is started and in standby mode (ENAC=1 and STANDBY=1, step #5 in “Audio Codec Typical Control Sequence” on page 57), the audio path is simply selected by PATHSEL bits. At STANDBY release (STANDBY=0), the audio controller will: • Power-up the requested audio sub-functions. To do so, the audio controller makes WRITE accesses to the registers – INPUT_CONTROL (0x1E), – OUTPUT_CONTROL (0x1F) and – INPUT_MIXER (0x20). • Ramp-up the concerned path gains from mute to their current register value. Notes: 1. Changing PATHSEL value with STANDBY=1 does not changes the codec state. It remains in STANDBY mode. 2. The audio controller always ensures minimum power consumption by powering only needed sub-functions. 3. Audio parameters (volume, mute, effects…) can be modified before or after releasing the standby mode. 61 11050A–PMAAC–07-Apr-10 12.4.2.2 Pause Management With STANDBY Bit To pause the audio codec activity and reduce power consumption to few hundreds of microamps, the STANDBY bit can be activated in register AUTOSTART (0x10). The Audio codec will then: • Softly ramp down all the path concerned gains down-to mute and • Power off all the audio sub-functions. The registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20) are modified by the audio controller. Notes: 1. Placing the codec in standby mode maintains the common mode voltage at VMID pin and thus allows to re-start fastly, 2. Standby release is simply achieved by clearing the STANDBY bit (STANDBY = 0). The procedure described in “STANDBY Release” on page 61 applies. 12.4.2.3 On-the-fly Path Change The audio controller is able to softly switch from one audio path configuration to another without shutting down the codec nor entering the STANDBY mode. As soon as it detects a change in the PATHSEL value, the following mechanism occurs: • Power up and/or power down of the audio sub-functions according to the final state to reach. This operation generates automatic changes in the registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20). • Ramp up and/or ramp down of the concerned path gain. Notes: 1. A channel may be temporarily and smoothly switched off and on to reach the new path. 2. Any software write operation in the registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20) will generate a series of control on the audio codec subfunctions. In automatic path control, the order of the write operations in those registers is of prime importance. Please note that changing those registers updates the used audio path without updating the PATHSEL value. Therefore, these write operations are not recommended and must be limited to simple ones (for example changing LINESEL bit in register INPUT_CONTROL (0x1E) ). 12.4.2.4 Audio Codec Shutdown The Audio controller will start to shutdown the codec if ENAC = 0. The shutdown sequence is made of the following steps: • Softly ramp down all the path concerned gains down-to mute, • Power off all the audio sub-functions and, • Power off the common voltage VMID. Notes: 1. In this mode, the power consumption is reduced to few hundreds of nA. 2. The common mode voltage power-off follows VMID time constant and thus may take a few hundreds of milliseconds depending on VMID capacitor. See “Audio Codec Bias” on page 22. A software example of audio codec control using automatic path control is provided in the section “Basic Audio Codec Setting Using Automatic Path Control” on page 134. 12.4.3 Custom Path Configuration In this custom path mode, the audio path control is managed by the following registers: • AUTOSTART (0x10) (ENAC and STANDBY bits only) • AUDIO_CONTROL (0x11) (ENCONF and CUSTCONF bits only) 62 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 • INPUT_CONTROL (0x1E) • OUTPUT_CONTROL (0x1F) • INPUT_MIXER (0x20) Like in the automatic path configuration, the audio controller will sequence audio codec subfunctions ON/OFF as well as gain stepping. However, the audio path is no more selected via the "PATHSEL" value in register AUTOSTART. To specify a custom audio path: • The bit CUSTCONF in register AUDIO_CONTROL (0x11) must be set to '1' to specify the 'custom' path configuration mode. • The registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F), and INPUT_MIXER (0x20) are set to define the audio path, • The bit ENCONF in register AUDIO_CONTROL (0x11) is pulsed to '1' to enable the audio controller sequencing. Notes: 1. “Pulsed to ‘1’ ”means written to ‘1’ and then written to ’0’. 2. In this mode, the STANDBY bit behaves like in the automatic mode. It is possible to place the CODEC in standby mode to reduce power consumption during audio pause by simply setting the STANDBY bit to 1. STANDBY release is achieved by clearing this bit. 3. On-the-fly path change is achieved by modifying the registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F) , and INPUT_MIXER (0x20) to define the new audio path configuration and then pulsing to '1' the ENCONF bit. In this case, a channel may be temporarily (and smoothly) switched off and on to reach the new configuration. 4. Changing the three registers INPUT_CONTROL (0x1E), OUTPUT_CONTROL (0x1F) , and INPUT_MIXER (0x20) with the ENCONF bit set to ‘1’ makes the changes to take effect immediately. Therefore, the order of write operations is of prime importance. It is then recommended to write these registers with ENCONF set to 0 and then pulse ENCONF to ‘1’ once the new audio path is fully specified. Knowing the final state to reach, the audio controller is able to sequence the controls with the right order and timings to ensure noise-free operation. 5. In this custom mode, the Audio Controller may forbid any configuration that does not make sense. For example, it will prevent the headphone amplifier from being switched on if it has no input source (DAC, Microphone, or Line). 6. It is possible and sometimes convenient to switch from an automatically set path to a custom one. In this case, the audio controller softly performs the required path change. However, activating an automatic path configuration from a current custom path configuration is not allowed. The audio codec must be switched off first (ENAC=0). A software example of audio codec control using custom path control is provided in the section “Basic Audio Codec Setting Using Custom Path Control” on page 135. 12.5 Audio Codec Power Consumption Versus Programmed Audio Path Unless otherwise specified: • AVDD = 3.3V • MCLK = 12.288MHz , FS = 48KHz • All Gains set to 0dB • No audio signal • TA = 25°C. • Headphone amplifier set in AC coupling mode. 63 11050A–PMAAC–07-Apr-10 • Current consumptions don’t account for load consumption and are measured in AVDD pin and VINSYS pin. Table 12-2. Audio PATH Power Consumption PATH_SEL AUDIO PATH 00000 No Path Description Consumption VINSYS 0.10 AVDD 0.61 Units mA 00001 DAC Playback Digital IN - Headphone OUT 1.80 5.2 mA 00010 Mic Sidetone Microphone IN - Headphone OUT 0.10 2.65 mA 00011 Aux Bypass Aux IN - Headphone OUT 0.10 2.65 mA 00100 Line Bypass Line IN - Headphone OUT 0.10 2.65 mA 00101 Mic Record Mic IN - Digital OUT 2.00 3.40 mA 00110 Aux Record Aux IN - Digital OUT 2.00 3.40 mA 00111 Line Record Line IN - DIGITAL OUT 2.00 3.40 mA 01000 Mic Sidetone + Record Mic IN - Headphone and Digital OUT 2.00 5.05 mA 01001 01010 Aux Bypass + Record Line Bypass + Record Aux IN - Headphone and Digital OUT Line IN - Headphone and Digital OUT 2.00 5.05 mA 2.00 5.05 mA 01011 Mic + Aux Record Mic + Aux IN - Digital OUT 2.00 3.70 mA 01100 Mic + Line Record Mic + Line IN - Digital OUT 2.00 3.70 mA 01101 DAC Playback + Mic Sidetone Digital + Mic IN - Headphone OUT 1.80 5.60 mA 01110 DAC Playback + Aux Bypass Digital + Aux IN - Headphone OUT 1.80 5.60 mA 01111 DAC Playback + Line Bypass Digital + Line IN - Headphone OUT 1.80 5.60 mA 10000 DAC Playback + Mic Sidetone + Aux Bypass Digital + Mic + Aux IN - Headphone OUT 1.80 5.85 mA 10001 DAC Playback + Mic Sidetone + Line Bypass Digital + Mic + Line IN - Headphone OUT 1.80 5.85 mA 10010 DAC Playback and MIC Record Digital IN - Headphone OUT Mic IN - Digital OUT 3.80 8.00 mA 10011 DAC Playback and Aux Record Digital IN - Headphone OUT Aux IN - Digital OUT 3.80 8.00 mA 10100 DAC Playback and Line Record Digital IN - Headphone OUT Line IN - Digital OUT 3.80 8.00 mA 10101 10110 DAC Playback + Mic Sidetone and Mic Record DAC Playback + Aux Bypass and Aux Record Digital + Mic IN - Headphone OUT Mic IN - Digital OUT Digital + Aux IN - Headphone OUT Aux IN - Digital OUT 3.80 8.00 mA 3.80 8.00 mA 64 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Table 12-2. Audio PATH Power Consumption PATH_SEL AUDIO PATH Description 10111 11000 11001 DAC Playback + Line Bypass and Line Record DAC Playback + Mic Sidetone + Aux Bypass and Mic + Aux Record DAC Playback + Mic Sidetone + Line Bypass and Mic + Line Record Digital + Line IN - Headphone OUT Line IN - Digital OUT Digital + Mic + Aux IN - Headphone OUT Mic + Aux IN - Digital OUT Digital + Mic + Line IN - Headphone OUT Mic + Line IN - Digital OUT Consumption VINSYS AVDD 3.80 8.00 3.80 8.25 3.80 8.25 Units mA mA mA 65 11050A–PMAAC–07-Apr-10 12.6 Digital Audio Interface 12.6.1 General Description AT73C246 features a 16 to 24-bit multi-mode master / slave I2S port. The following modes are provided: • I2S, • Left Justified, • Right Justified, and • SSC The I2S port is configured through register I2S_CONTROL (0x13) and FRAME_CONTROL (0x14). For each of the listed modes, the data transfer is described in the following sections. The following table provides authorized MCLK / FS ratios and associated filter types: Table 12-3. 8 KHz 16 KHz 32 KHz 48 KHz 96 KHz 22.05 KHz 44.1 KHz 88.2 KHz Authorized MCLK / FS Ratios & Filter Types 12 MHz(1) 12.288 MHz 18.432 MHz 0 2 2 0 2 2 0 2 2 3 1 1 4 3 3 1 NA NA 1 NA NA 3 NA NA 11.2896 MHz NA NA NA NA NA 1 1 3 16.9344 MHz NA NA NA NA NA 1 1 3 12.6.2 Note: 1. 12.0000 MHz case is not provided if DAI is configured in Right-Justified and Master mode in DAI_CONTROL (0x13) and FRAME_CONTROL registers (0x14). Data Transfer: I²S MODE Figure 12-7. N-bit I²S Mode (FS = 44.1KHz - MCLK = 256 x FS) MCLK LRFS BCLK SDOUT SDIN Ln Ln-1 L0 n bits Left Channel Rn R n-1 R3 R2 R1 R0 n bits Right Channel 66 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 12.6.3 Data Transfer: Left Justified Mode Figure 12-8. N-bit Left Justified Mode (FS = 44.1KHz - MCLK = 256 x FS) MCLK LRFS BCLK SDOUT SDIN Ln Ln-1 Ln-2 L0 Rn Rn-1 Rn-2 R3 R2 R1 R0 n bits Left Channel n bits Right Channel 12.6.4 Data Transfer: Right Justified Mode Figure 12-9. N-bit Right Justified Mode (FS = 44.1KHz - MCLK = 256 x FS) MCLK LRFS BCLK SDOUT SDIN Ln Ln-1 Ln-2 L0 n bits Left Channel Rn Rn-1 Rn-2 R3 R2 R1 R0 n bits Right Channel 67 11050A–PMAAC–07-Apr-10 12.6.5 Timing Specifications Figure 12-10. Timing Diagram of data interface (I²S Mode) TLRCLK TLRCLK VIH LRFS VIL VIH BCLK VIL DAI VXH DAO VXL TBCLK TLSDX THSDX LSB MSB LSB MSB LSB Word N-1 Right Channel Word N Left Channel Word N Right Channel Table 12-4. Digital Audio InterfaceTiming Specifications Parameter Symbols Min Typ Max Unit Left/Right Word Cycle Time TLRCLK 1 / (2 x FS) s Bit Clock Period TBCLK TMCLK / 2 s BCLK Posedge to {DAI, DAO and LRFS} Change Hold Time THSDX 5 ns {DAI, DAO and LRFS} Change to BCLK Posedge Setup Time TLSDX 5 ns 12.7 Digital Filters Transfer Function 12.7.1 DAC Frequency Response The following diagrams are referred to FS = 1 (Sampling Frequency). Figure 12-11. DAC Type 0 Frequency Response Overall 68 AT73C246 Ripple 11050A–PMAAC–07-Apr-10 Figure 12-12. DAC Type 1 Frequency Response AT73C246 Overall Figure 12-13. DAC Type 2 Frequency Response Ripple Overall Figure 12-14. DAC Type 3 Frequency Response Ripple Overall Ripple 69 11050A–PMAAC–07-Apr-10 Figure 12-15. DAC Type 4 Frequency Response Overall Ripple 12.7.2 ADC Frequency Response The following diagrams are referred to FS = 1 (Sampling Frequency). Figure 12-16. ADC Type 0 Frequency Response Overall Figure 12-17. ADC Type 1 Frequency Response Ripple Overall 70 AT73C246 Ripple 11050A–PMAAC–07-Apr-10 Figure 12-18. ADC Type 2 Frequency Response AT73C246 Overall Figure 12-19. ADC Type 3 Frequency Response Ripple Overall Figure 12-20. ADC Type 4 Frequency Response Ripple Overall 11050A–PMAAC–07-Apr-10 Ripple 71 12.7.3 De-Emphasis Filter Frequency Response 12.7.3.1 De-Emphasis Filter: Frequency Response & Error (FS = 32kHz) Figure 12-21. De-Emphasis Filter: Frequency Response & Error (FS = 32kHz) Response Error Response (dB) Response (dB) 12.7.3.2 Fequency (Hz) Fequency (Hz) De-Emphasis Filter: Frequency Response & Error (FS = 44.1kHz) Figure 12-22. De-Emphasis Filter: Frequency Response & Error (FS = 44.1kHz) Response Error Response (dB) Response (dB) 12.7.3.3 Fequency (Hz) Fequency (Hz) De-Emphasis Filter: Frequency Response & Error (FS = 48kHz) Figure 12-23. De-Emphasis Filter: Frequency Response & Error (FS = 48kHz) Response Error Response (dB) Response (dB) 72 AT73C246 Fequency (Hz) Fequency (Hz) 11050A–PMAAC–07-Apr-10 AT73C246 12.7.4 Equalizer Frequency Response The following figures show the frequency response of the equalizer function implemented in the D/A channels. Figure 12-24. Bass Filters Response dB Fs Figure 12-25. Medium Filters Response dB 11050A–PMAAC–07-Apr-10 Fs 73 Figure 12-26. Treble Filters Response dB Fs 12.8 Analog Audio Interfaces 12.8.1 Microphone Inputs The following figures show recommended application circuits for microphone inputs configurations: • Mono - single-ended and differential microphone • Stereo - single ended and differential microphone • Long-wires microphone Recommended resistor / capacitor / inductor value may be tuned to the final application, depending on: • the microphone specified load resistance, • the high pass filter desired corner frequency, • the level and frequency of unwanted signals to be rejected. Depending also on desired high frequency filtering: common-mode or differential, the differential suggested application diagrams may be modified. 74 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Figure 12-27. Mono - Single Ended and Differential Microphone Applications VIN4 LDO4 VDD4 AVDD 2k MICBIAS AT73C246 MICL MICLN MICR MICRN 1uF NC NC NC 10uF 2k 10uF M 2.2nF VIN4 LDO4 VDD4 AVDD 2k MICBIAS AT73C246 MICL MICLN MICR MICRN 10uF 1uF 2.2nF 1uF NC NC 1k M 1k 10uF Figure 12-28. Stereo - Single Ended and Differential Microphone Applications VIN4 LDO4 VDD4 AVDD 10uF 470 2k MICBIAS AT73C246 MICL NC 1uF 10uF 2k 2.2nF M MICLN NC 470 10uF MICR MICRN NC 1uF 2.2nF 2k M VIN4 LDO4 VDD4 AVDD 2k MICBIAS AT73C246 MICL MICLN MICR MICRN 10uF 470 NC 1uF 2.2nF 1uF 1k M 1k 470 10uF 1uF 2.2nF 1uF 1k M 1k 10uF Figure 12-29. Long Wires Microphone Applications VIN4 LDO4 VDD4 AVDD 10uF 2k MICBIAS AT73C246 MICL 2k 1uF 10uH 10uF MICLN NC 2.2nF 1nF M long wires MICR NC MICRN NC VIN4 LDO4 VDD4 AVDD 10uF 470 470 2k NC MICBIAS AT73C246 MICL 1uF 10uF 1k 10uH 10uF MICLN 2.2nF 1uF 1nF 10uH 1k M long wires 1uF MICR 1k 10uH MICRN 2.2nF 1uF 1nF M long wires 10uH 1k 75 11050A–PMAAC–07-Apr-10 12.8.2 12.8.3 Aux / Line Inputs Figure 12-30. Aux and Line Input Application Circuits AUXL 3.3uF 10nF AUXR AT73C246 LINL 10nF 3.3uF 3.3uF 10nF LINR 10nF 3.3uF 100k 100k 100 100 100 100 ON-BOARD AUDIO IC SOURCE (FM receiver, ...) jack Line / Headphone Outputs Figure 12-31. AC Coupled Output Application Circuits 3.3uF 100 HPR 330uF HPR 100k 100k AT73C246 HPVCM NC 100k 3.3uF 100 HPL jack line-output AT73C246 HPVCM NC 330uF HPL 100k jack headphone output 16 / 32 Ohms Figure 12-32. DC Coupled (CAPLESS) Application Circuits HPR AT73C246 HPVCM DIFF. IN / DIFF. OUT POWER AMP. HPR AT73C246 HPVCM DIFF. IN / DIFF. OUT HPL POWER AMP. HPL jack headphone output 16 / 32 Ohms 76 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 13. Two Wire Interface and Control Registers 13.1 Two-wire Interface (TWI) Protocol The two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 Kbits per second, based one a byte oriented transfer format. The TWI is slave only and single byte access. The interface adds flexibility to the power supply solution, enabling LDO regulators to be controlled depending on the instantaneous application requirements. The AT73C246 has the following 7-bit address:1001001. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. • TWCK is an input pin for the clock • TWD is an open-drain pin that drives or receives the serial data The data put on the TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be followed by an acknowledgement. Each transfer begins with a START condition and terminates with a STOP condition. • A high-to-low transition on TWD while TWCK is high defines a START condition. • A low-to-high transition on TWD while TWCK is high defines a STOP condition. Figure 13-1. TWI Start/Stop Cycle TWD TWCK Start Stop Figure 13-2. TWI Data Cycle TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop After the host initiates a Start condition, it sends the 7-bit slave address defined above to notify the slave device. A Read/Write bit follows (Read = 1, Write = 0). The device acknowledges each received byte. The first byte sent after device address and R/W bit is the address of the device register the host wants to read or write. For a write operation the data follows the internal address 77 11050A–PMAAC–07-Apr-10 For a read operation a repeated Start condition needs to be generated followed by a read on the device. Figure 13-3. TWD Write Operation TWD S ADDR W A IADDR A DATA A P Figure 13-4. TWD Read Operation TWD S ADDR W A IADDR A S • S = Start • P = Stop • W = Write • R = Read • A = Acknowledge • N = Not Acknowledge • ADDR = Device address • IADDR = Internal address ADDR R A DATA N P 78 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 13.2 PMU Register Tables 13.2.1 Register Mapping Table 13-1. Register Mapping Addr Name 7 6 5 4 3 2 1 0 0x00 PMU_MODES - - - - - STANDBY PWRDOWN RUN 0x01 PMU_WAKEUP_EVENTS - - RTC PWREN WAKEUP3 WAKEUP2 WAKEUP1 WAKEUP0 0x02 PMU_WAKEUP_TRIG - - RTCR PWREN WAKEUP3 WAKEUP2 WAKEUP1 WAKEUP0 0x03 PMU_STANDBY_SUPPLIES - - LP_VDD1 LP_VDD0 VDD3 VDD2 VDD1 VDD0 0x04 PMU_SUPPLY_CTRL - - IN_PHASE DVS_VDD4 DVS_VDD3 DVS_VDD2 DVS_VDD1 DVS_VDD0 0x05 PMU_RST_LEVEL RST_VDD3 RST_VDD2 RST_VDD1 RST_VDD0 0x06 VDD0_CTRL ON_VDD0 LPMODE VDD0_SEL 0x07 VDD1_CTRL ON_VDD1 LPMODE VDD1_SEL 0x08 VDD2_CTRL ON_VDD2 - - VDD2_SEL 0x09 VDD3_CTRL ON_VDD3 - - VDD3_SEL 0x0A VDD4_CTRL ON_VDD4 - - VDD4_SEL 0x0B PMU_LED TON_LED PERIOD_LED BLINK ON_LED 0x0C PMU_MASK - - - - - - RTC_ALARM RTC_IT 0x0D PMU_IT - - - - - - RTC_ALARM RTC_IT 0x0E PMU_WAKEUP_SUPPLIES - - - - VDD0_WUP VDD1_WUP VDD2_WUP VDD3_WUP 0x10 AUTOSTART - ENAC STANDBY PATH_SEL 0x11 AUDIO_CONTROL - BCLKINV DCBLOCK ENCONF CUSTCONF ENASR ASR_TIME 0x12 MIC_CONTROL - - MICLDIFF MICRDIFF MICDET ONMICBIAS MICDET_ST 0x13 DAI_CONTROL - - MASTER MCLKSEL 0x14 FRAME_CONTROL SSCMODE WL DAIMODE SELFS 0x15 MUTE MUTEDACL MUTEDACR MUTEINL MUTEINR MUTEMICL MUTEMICR MUTEHPL MUTEHPR 0x16 MICLVOL - - MICLVOL 0x17 MICRVOL - - MICRVOL 0x18 INLVOL INLBOTH INLVOL 0x19 INRVOL INRBOTH INRVOL 0x1A HPLVOL HPLVOL 0x1B HPRVOL HPRVOL 0x1C HP_CONTROL HPDET_ST LHPBOTH RHPBOTH 0x1D AUDIO_EFFECTS 3DFX_DEPTH ON3DFX SWAP_DAC SWAP_ADC MONO_DAC MONO_ADC ONDEEMP 0x1E INPUT_CONTROL - LINESEL ONMICL ONMICR ONADCL ONADCR ONLINL ONLINR 0x1F OUTPUT_CONTROL - ONSIDETONE ONPLAYBACK ONBYPASS ONHPL ONHPR ONDACL ONDACR 0x20 INPUT_MIXER - - MIXMICL MIXMICR MIXLINEL MIXLINER ONMIXL ONMIXR 0x21 SIDETONE_VOL - - - SIDETONE_VOL 0x22 EQUALIZER - - - - EQ_SEL 0x30 ADC_CTRL ON_ADC ON_BUF TS 0x31 ADC_MUX_1 - VIN - VDD4 VDD3 VDD2 VDD1 VDD0 0x32 ADC_MUX_2 - - - - ANA3 ANA2 ANA1 ANA0 0x33 ADC_ANA0_MSB ADC<9:2> 79 11050A–PMAAC–07-Apr-10 Table 13-1. Register Mapping Addr Name 0x34 ADC_ANA0_LSB 0x35 ADC_ANA1_MSB 0x36 ADC_ANA1_LSB 0x37 ADC_ANA2_MSB 0x38 ADC_ANA2_LSB 0x39 ADC_ANA3_MSB 0x3A ADC_ANA3_LSB 0x3B ADC_VDD0_MSB 0x3C ADC_VDD0_LSB 0x3D ADC_VDD1_MSB 0x3E ADC_VDD1_LSB 0x3F ADC_VDD2_MSB 0x40 ADC_VDD2_LSB 0x41 ADC_VDD3_MSB 0x42 ADC_VDD3_LSB 0x43 ADC_VDD4_MSB 0x44 ADC_VDD4_LSB 0x47 ADC_VIN_MSB 0x48 ADC_VIN_LSB 0x49 ADC_ANA_LSB 0x50 RTC_CTRL 0X51 RTC_ADDR 0x52 RTC_DATA0 0x53 RTC_DATA1 0x54 RTC_DATA2 0x55 RTC_DATA3 0x56 BACKUP_CTRL 0x7F VERSION 7 6 5 4 3 2 1 0 - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC<9:2> - - - - - - ADC<1:0> ADC_ANA3<1:0> ADC_ANA2<1:0> ADC_ANA1<1:0> ADC_ANA0<1:0> - - - - - RTC_WRITE RTC_SEL RTC_EN RTC_ADDR RTC_DATA0 RTC_DATA1 RTC_DATA2 RTC_DATA3 - - - - OSC_UPDT OSC_EN OSC_STAT RST_BKUP SOFTWARE_TAG VERSION 80 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 13.2.2 PMU Control Name: Access: Address: PMU_MODES Read / Write 0x00 7 6 5 4 3 2 1 0 - - - - - STANDBY PWRDOWN RUN Table 13-2. Bit 7:3 2 1 0 PMU_MODES (0x00) Structure Name Description - unused STANDBY STANDBY request 0: Default value. 1: STANDBY request. Reset to 0 at STANDBY exit. PWRDOWN POWERDOWN request 0: Default value. 1: POWERDOWN request. Reset to 0 when POWERDOWN state reached. RUN RUN mode Reset value 00000 0 0 0 Notes: 1. Please refer to Section 11. “PMU Functional Description” on page 25 2. ‘RUN’ bit is read-only. Only ‘STANDBY’ and ‘PWRDOWN’ bits can be written 81 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_WAKEUP_EVENTS Read / Write 0x01 7 6 5 4 3 2 1 0 - - RTC PWREN WAKEUP3 WAKEUP2 WAKEUP1 WAKEUP0 Table 13-3. Bit 7:6 5 4 3 2 1 0 PMU_WAKEUP_EVENTS (0x01) Structure Name Description - unused RTC Wake up by RTC alarm input 0: disabled 1: enabled PWREN Wake up by PWREN input 0: disabled 1: enabled WAKEUP3 Wake up by WAKEUP3 input 0: disabled 1: enabled WAKEUP2 Wake up by WAKEUP2 input 0: disabled 1: enabled WAKEUP1 Wake up by WAKEUP1 input 0: disabled 1: enabled WAKEUP0 Wake up by WAKEUP0 input 0: disabled 1: enabled Reset value 00 0 0 0 0 0 1 Note: Please refer to Section 11. “PMU Functional Description” on page 25 82 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: PMU_WAKEUP_TRIG Read Only 0x02 7 6 5 4 3 2 1 0 - - RTCR PWREN WAKEUP3 WAKEUP2 WAKEUP1 WAKEUP0 Table 13-4. Bit 7:6 5 4 3 2 1 0 PMU_WAKEUP_TRIG (0x02) Structure Name Description - unused RTCR WAKEUP_EVENT trigged on RTC alarm PWREN WAKEUP_EVENT trigged on PWREN WAKEUP3 WAKEUP_EVENT trigged on WAKEUP3 WAKEUP2 WAKEUP_EVENT trigged on WAKEUP2 WAKEUP1 WAKEUP_EVENT trigged on WAKEUP1 WAKEUP0 WAKEUP_EVENT trigged on WAKEUP0 Reset value 00 0 0 0 0 0 0 Note: Please refer to Section 11. “PMU Functional Description” on page 25 83 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_STANDBY_SUPPLIES Read / Write 0x03 7 6 5 4 3 2 - - LP_VDD1 LP_VDD0 VDD3 VDD2 Table 13-5. Bit 7:6 5 4 3 2 1 0 PMU_STANDBY_SUPPLIES (0x03) Structure Name Description - unused LP_VDD1 VDD1 Low power mode in STANDBY 0: Full power (PWM) 1: Low power (PFM) LP_VDD0 VDD0 Low power mode in STANDBY 0: Full power (PWM) 1: Low power (PFM) VDD3 VDD3 in STANDY state 0: OFF 1: ON VDD2 VDD2 in STANDY state 0: OFF 1: ON VDD1 VDD1 in STANDY state 0: OFF 1: ON VDD0 VDD0 in STANDY state 0: OFF 1: ON 1 VDD1 0 VDD0 Reset value 00 1 1 1 0 0 1 84 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: PMU_SUPPLY_CTRL Read / Write 0x04 7 6 5 4 3 2 1 0 - - IN_PHASE DVS_VDD4 DVS_VDD3 DVS_VDD2 DVS_VDD1 DVS_VDD0 Table 13-6. Bit 7:6 5 4 3 2 1 0 PMU_SUPPLY_CTRL (0x04) Structure Name Description - unused IN_PHASE DCDC0 and DCDC1 phase operation 0: out-of phase 1: in-phase DVS_VDD4 DVS function on VDD4 0: OFF 1: ON DVS_VDD3 DVS function on VDD3 0: OFF 1: ON DVS_VDD2 DVS function on VDD2 0: OFF 1: ON DVS_VDD1 DVS function on VDD1 0: OFF 1: ON DVS_VDD0 DVS function on VDD0 0: OFF 1: ON Reset value 00 0 1 1 1 1 1 85 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_RST_LVL Read / Write 0x05 7 6 RST_VDD3 5 4 RST_VDD2 3 2 RST_VDD1 Table 13-7. Bit 7:6 5:4 3:2 1:0 PMU_RST_LVL (0x05) Structure Name Description RST_VDD3 RST level on VDD3 RST_VDD2 RST level on VDD2 RST_VDD1 RST level on VDD1 RST_VDD0 RST level on VDD0 Table 13-8. VDDx Reset Level Selection Table RST_VDDx RST LEVEL 00 0.85 x VDDx 01 0.90 x VDDx 10 0.92 x VDDx 11 0.95 x VDDx 1 0 RST_VDD0 Reset value 01 10 10 11 86 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: VDD0_CTRL Read / Write 0x06 7 6 5 4 3 2 1 0 ON_VDD0 LPMODE VDD0_SEL Table 13-9. Bit 7 6 5:0 VDD0_CTRL (0x06) Structure Name Description ON_VDD0 VDD0 ON/OFF 0: OFF 1: ON LPMODE VDD0 Low power mode 0: Full power (PWM) 1: Low power (PFM) VDD0_SEL VDD0 voltage selection Reset value 0 0 010101 Table 13-10. VDD0 Voltage Selection Table VDD0_SEL VDD0 (V) VDD0_SEL 000000 0.80 010011 000001 0.85 010100 000010 0.90 010101 000011 0.95 010110 000100 1.00 010111 000101 1.05 011000 000110 1.10 011001 000111 1.15 011010 001000 1.20 011011 001001 1.25 011100 001010 1.30 011101 001011 1.35 011110 001100 1.40 011111 001101 1.45 100000 001110 1.50 100001 001111 1.55 100010 010000 1.60 100011 010001 1.65 100100 010010 1.70 100101 VDD0 (V) 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 VDD0_SEL 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 VDD0 (V) 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 87 11050A–PMAAC–07-Apr-10 Name: Access: Address: VDD1_CTRL Read / Write 0x07 7 6 5 4 3 2 1 0 ON_VDD1 LPMODE VDD1_SEL Table 13-11. VDD1_CTRL (0x07) Structure Bit Name Description VDD1 ON / OFF 7 ON_VDD1 0: OFF 1: ON VDD1 Low power mode 6 LPMODE 0: Full power (PWM) 1: Low power (PFM) 5:0 VDD1_SEL VDD1 voltage selection Reset value 0 0 001000 Table 13-12. VDD1 Voltage Selection Table VDD1_SEL VDD1 (V) VDD1_SEL 000000 0.80 010011 000001 0.85 010100 000010 0.90 010101 000011 0.95 010110 000100 1.00 010111 000101 1.05 011000 000110 1.10 011001 000111 1.15 011010 001000 1.20 011011 001001 1.25 011100 001010 1.30 011101 001011 1.35 011110 001100 1.40 011111 001101 1.45 100000 001110 1.50 100001 001111 1.55 100010 010000 1.60 100011 010001 1.65 100100 010010 1.70 100101 VDD1 (V) 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 VDD1_SEL 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 VDD1 (V) 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 88 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: VDD2_CTRL Read / Write 0x08 7 6 5 4 3 ON_VDD2 - - Table 13-13. VDD2_CTRL (0x08) Structure Bit Name Description VDD2 ON / OFF 7 ON_VDD2 0: OFF 1: ON 6:5 - unused 4:0 VDD2_SEL VDD2 voltage selection Table 13-14. VDD2 Voltage Selection Table VDD2_SEL VDD2 (V) 00000 0.80 00001 0.85 00010 0.90 00011 0.95 00100 1.00 00101 1.05 00110 1.10 00111 1.15 01000 1.20 01001 1.25 01010 1.30 01011 1.35 2 VDD2_SEL 1 0 Reset value 0 00 00100 89 11050A–PMAAC–07-Apr-10 Name: Access: Address: VDD3_CTRL Read / Write 0x09 7 6 5 4 3 ON_VDD3 - - Table 13-15. VDD3_CTRL (0x09) Structure Bit Name Description VDD3 ON / OFF 7 ON_VDD3 0: OFF 1: ON 6:5 - unused 4:0 VDD3_SEL VDD3 voltage selection Table 13-16. VDD3 Voltage Selection Table VDD3_SEL VDD3 (V) 00000 2.70 00001 2.75 00010 2.80 00011 2.85 00100 2.90 00101 2.95 00110 3.00 00111 3.05 01000 3.10 01001 3.15 01010 3.20 01011 3.25 01100 3.30 01101 3.35 01110 3.40 01111 3.45 10000 3.50 10001 3.55 10010 3.60 2 VDD3_SEL 1 0 Reset value 0 00 01100 90 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: VDD4_CTRL Read / Write 0x0A 7 6 5 4 3 ON_VDD4 - - Table 13-17. VDD4_CTRL (0x0A) Structure Bit Name Description VDD4 ON / OFF 7 ON_VDD4 0: OFF 1: ON 6:5 - unused 4:0 VDD4_SEL VDD4 voltage selection Table 13-18. VDD4 Voltage Selection Table VDD4_SEL VDD4 (V) 00000 2.70 00001 2.75 00010 2.80 00011 2.85 00100 2.90 00101 2.95 00110 3.00 00111 3.05 01000 3.10 01001 3.15 01010 3.20 01011 3.25 01100 3.30 01101 3.35 01110 3.40 01111 3.45 10000 3.50 10001 3.55 10010 3.60 2 VDD4_SEL 1 0 Reset value 0 00 01100 91 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_LED Read / Write 0x0B 7 6 5 TON_LED 4 3 2 PERIOD_LED Table 13-19. PMU_LED (0x0B) Structure Bit Name Description 7:5 TON_LED LED ‘ON’ time 4:2 PERIOD_LED LED blinking period Blinking function ON / OFF 1 BLINK 0: OFF 1: ON Led ON / OFF 0 ON_LED 0: OFF 1: ON Table 13-20. LED Blinking Function Parameters Selection Table TON_LED LED ‘ON’ Time (ms) PERIOD_LED 000 25 000 001 50 001 010 75 010 011 100 011 100 125 100 101 150 101 110 175 110 111 200 111 1 BLINK 0 ON_LED Reset value 000 010 0 0 BLINKING PERIOD (s) 0.5 1 2 3 4 5 6 8 Note: In case of TON_LED = 175ms, PERIOD_LED=5s and BLINK=1 selection, the LED pin is driven according to the following diagram. During 9 clock periods (internal RC 32kHz oscillator) the pin is driven to 0, and during 1 clock period the pin is configured as ‘input’ with an internal pull up resistor to VINSYS. Figure 13-5. LED Pin Timing Diagram for TON_LED = 175ms and PERIOD_LED=5s Internal RC 32kHz LED Pin Pin forced to ‘0’ 9 x 32kHz clock periods 92 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_MASK Read / Write 0x0C 7 6 5 4 3 - - - - - Table 13-21. PMU_MASK (0x0C) Structure Bit Name Description 7:2 - unused Mask RTC alarm 1 RTC_ALARM 0: not masked 1: masked Mask RTC interrupt 0 RTC_IT 0: not masked 1: masked AT73C246 2 1 0 - RTC_ALA RM RTC_IT Reset value 111111 1 1 Name: Access: Address: PMU_IT Read Only 0x0D 7 6 5 4 3 2 1 0 - - - - - - RTC_ALA RM RTC_IT Table 13-22. PMU_IT (0x0D) Structure Bit Name Description Reset value 7:2 - unused 000000 RTC alarm interrupt 1 RTC_ALARM 0: default value 0 1: RTC alarm has occurred. Reset to 0 at read. RTC interrupt 0 RTC_IT 0: default value 0 1: RTC interrupt has occurred. Reset to 0 at read. 93 11050A–PMAAC–07-Apr-10 Name: Access: Address: PMU_WAKEUP_SUPPLIES Read / Write 0x0E 7 6 5 4 3 2 1 0 - - - - VDD0_WUP VDD1_WUP VDD2_WUP VDD3_WUP Table 13-23. PMU_WAKEUP_SUPPLIES (0x0E) Structure Bit Name Description 7:4 - unused VDD0 Value at WAKEUP 3 VDD0_WUP 0: Programmed value 1: Default value VDD1Value at WAKEUP 2 VDD1_WUP 0: Programmed value 1: Default value VDD2 Value at WAKEUP 1 VDD2_WUP 0: Programmed value 1: Default value VDD3 Value at WAKEUP 0 VDD3_WUP 0: Programmed value 1: Default value Reset value 0000 1 1 1 1 94 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: AUTOSTART Read / Write 0x10 7 6 5 4 3 2 1 0 - ENAC STANDBY PATH_SEL Table 13-24. AUTOSTART (0x10) Structure Bit Name Description 7 - unused Audio Codec ON / OFF 6 ENAC 0: OFF 1: ON Audio STANDBY mode ON / OFF 5 STANDBY 0: Audio codec active 1: Audio codec in standby 4:0 PATH_SEL Audio PATH selection Reset value 0 0 1 00000 Table 13-25. Audio Path Selection Table PATH_SEL AUDIO PATH 00000 No Path 00001 DAC Playback 00010 Mic Sidetone 00011 Aux Bypass 00100 Line Bypass 00101 Mic Record 00110 Aux Record 00111 Line Record 01000 Mic Sidetone + Record 01001 Aux Bypass + Record 01010 Line Bypass + Record 01011 Mic + Aux Record 01100 Mic + Line Record 01101 DAC Playback + Mic Sidetone 01110 DAC Playback + Aux Bypass 01111 DAC Playback + Line Bypass 10000 DAC Playback + Mic Sidetone + Aux Bypass 10001 DAC Playback + Mic Sidetone + Line Bypass 10010 DAC Playback and MIC Record Digital IN - Headphone OUT Microphone IN - Headphone OUT Aux IN - Headphone OUT Line IN - Headphone OUT Mic IN - Digital OUT Aux IN - Digital OUT Line IN - DIGITAL OUT Mic IN - Headphone and Digital OUT Aux IN - Headphone and Digital OUT Line IN - Headphone and Digital OUT Mic + Aux IN - Digital OUT Mic + Line IN - Digital OUT Digital + Mic IN - Headphone OUT Digital + Aux IN - Headphone OUT Digital + Line IN - Headphone OUT Digital + Mic + Aux IN - Headphone OUT Digital + Mic + Line IN - Headphone OUT Digital IN - Headphone OUT Mic IN - Digital OUT 95 Table 13-25. Audio Path Selection Table PATH_SEL AUDIO PATH 10011 DAC Playback and Aux Record 10100 DAC Playback and Line Record 10101 DAC Playback + Mic Sidetone and Mic Record 10110 DAC Playback + Aux Bypass and Aux Record 10111 DAC Playback + Line Bypass and Line Record 11000 DAC Playback + Mic Sidetone + Aux Bypass and Mic + Aux Record 11001 DAC Playback + Mic Sidetone + Line Bypass and Mic + Line Record Digital IN - Headphone OUT Aux IN - Digital OUT Digital IN - Headphone OUT Line IN - Digital OUT Digital + Mic IN - Headphone OUT Mic IN - Digital OUT Digital + Aux IN - Headphone OUT Aux IN - Digital OUT Digital + Line IN - Headphone OUT Line IN - Digital OUT Digital + Mic + Aux IN - Headphone OUT Mic + Aux IN - Digital OUT Digital + Mic + Line IN - Headphone OUT Mic + Line IN - Digital OUT 96 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: AUDIO_CONTROL Read / Write 0x11 7 6 5 4 3 2 - BCLKINV DCBLOCK ENCONF CUST_CO NF ENASR Table 13-26. AUDIO_CONTROL (0x11) Structure Bit Name Description 7 - - Bit clock inversion on I2S port 6 BLCKINV 0: not inverted 1: inverted Headphone output coupling configuration 5 DCBLOCK 0: DC coupled (capless operation) 1: AC coupled Custom configuration enable 4 ENCONF 0: Default value. 1: custom configuration is send to audio controller. Custom audio configuration 3 CUST_CONF 0: Audio path are set with PATH_SEL 1: Custom audio path set by software Gain soft ramping ON / OFF 2 ENASR 0: OFF 1: ON 1:0 ASR_TIME Gain soft ramping timing selection Table 13-27. Gain Soft Ramping Timing Selection Table ASR_TIME Timing 00 MCLK / (32 x 512) 01 MCLK / (64 x 512) 10 MCLK / (128 x 512) 11 MCLK / (256 x 512) 1 0 ASR_TIME Reset value 0 0 0 0 0 1 11 97 11050A–PMAAC–07-Apr-10 Name: Access: Address: MIC_CONTROL Read / Write 0x12 7 6 5 4 3 2 1 0 - - MICLDIFF MICRDIFF MICDET ONMICBIAS MICDET_ST Table 13-28. MIC_CONTROL (0x12) Structure Bit Name Description 7:6 - unused Left microphone differential configuration 5 MICLDIFF 0: Single-ended 1: Differential Right microphone differential configuration 4 MICRDIFF 0: Single-ended 1: Differential 3:2 MICDET Microphone detector threshold Microphone bias generator ON / OFF 1 ONMICBIAS 0: OFF 1: ON MICBIAS pin microphone detector status bit 0 MICDET_ST 0: No microphone detected 1: Microphone detected Reset value 00 0 0 00 0 0 Table 13-29. Microphone Detector Threshold Selection Table MICDET MICBIAS PIN LEVEL (V) 00 AVDD - 0.1 01 AVDD - 0.2 10 AVDD - 0.3 11 AVDD - 0.4 98 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: DAI_CONTROL Read / Write 0x13 7 6 5 4 3 2 1 0 - - - - MASTER MCLKSEL Table 13-30. DAI_CONTROL (0x13) Structure Bit Name Description 7:4 - unused MASTER / SLAVE operation on DAI port 3 MASTER(1) 0: Slave 1: Master 2:0 MCLKSEL Audio Master clock frequency selection Reset value 0000 0 001 Note: 1. The MASTER mode is not provided for 12.0000 MHz clock case and Right-Justified mode on DAI. Table 13-31. Audio Master Clock Selection Table MCLKSEL MCLK (MHz) MCLKSEL MCLK (MHz) 000 12.000 100 16.9344 001 12.288 101 - 010 11.2896 110 - 011 18.432 111 - 99 11050A–PMAAC–07-Apr-10 Name: Access: Address: FRAME_CONTROL Read / Write 0x14 7 6 5 4 3 2 SSCMODE WL DAI_MODE Table 13-32. FRAME_CONTROL (0x14) Structure Bit Name Description SSC mode for DAI 7 SSCMODE 0: DAI according to DAI_MODE bits 1: SSC mode 6:5 WL Word length selection 4:3 DAI_MODE Digital Audio Interface mode control 2:0 SELFS Audio Frame frequency selection Table 13-33. Digital Audio Interface Word Length Selection Table WL MODE 00 16 01 18 10 20 11 24 Table 13-34. Digital Audio Interface Mode Selection Table DAIMODE MODE 00 I2S 01 Left-Justified 10 Right-Justified(1) 11 N/A 1 0 SELFS Reset value 0 11 00 011 Note: 1. The Right-Justified mode is not provided for 12.0000 MHz clock case and MASTER mode on DAI. Table 13-35. Audio Sampling Frequency Selection Table SELFS FS (kHz) SELFS FS (kHz) 000 8 100 96 001 16 101 22.050 010 32 110 44.100 011 48 111 88.200 100 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: MUTE Read / Write 0x15 7 MUTEDACL 6 MUTEDAC R 5 MUTEINL 4 3 2 1 0 MUTEINR MUTEMICL MUTEMICR MUTEHPL MUTEHPR Table 13-36. MUTE (0x15) Structure Bit Name Description DAC Left mute 7 MUTEDACL 0: active 1: muted DACR Right mute 6 MUTEDACR 0: active 1: muted AUX / LINE Left mute 5 MUTEINL 0: active 1: muted AUX / LINE Right mute 4 MUTEINR 0: active 1: muted MIC Left mute 3 MUTEMICL 0: active 1: muted MIC Right mute 2 MUTEMICR 0: active 1: muted Headphone Left mute 1 MUTEHPL 0: active 1: muted Headphone Right mute 0 MUTEHPR 0: active 1: muted Reset value 1 1 1 1 1 1 1 1 11050A–PMAAC–07-Apr-10 101 Name: Access: Address: MICLVOL Read / Write 0x16 7 6 5 4 3 2 1 0 - - MICLVOL Table 13-37. MICLVOL (0x16) Structure Bit Name Description 7:6 - unused 5:0 MICLVOL Microphone Left volume selection Reset value 00 000000 Table 13-38. Microphone Left Volume Selection Table MICLVOL GAIN(dB) MICLVOL GAIN(dB) 000000 0 010000 16 000001 1 010001 17 000010 2 010010 18 000011 3 010011 19 000100 4 010100 20 000101 5 010101 21 000110 6 010110 22 000111 7 010111 23 001000 8 011000 24 001001 9 011001 25 001010 10 011010 26 001011 11 011011 27 001100 12 011100 28 001101 13 011101 29 001110 14 011110 30 001111 15 011111 31 MICLVOL 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 Other values GAIN(dB) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 46 102 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: MICRVOL Read / Write 0x17 7 6 5 4 3 2 1 0 - - MICRVOL Table 13-39. MICRVOL (0x17) Structure Bit Name Description 7:6 - unused 5:0 MICRVOL Microphone Right volume selection Reset value 0 000000 Table 13-40. Microphone Right Volume Selection Table MICRVOL GAIN(dB) MICRVOL GAIN(dB) 000000 0 010000 16 000001 1 010001 17 000010 2 010010 18 000011 3 010011 19 000100 4 010100 20 000101 5 010101 21 000110 6 010110 22 000111 7 010111 23 001000 8 011000 24 001001 9 011001 25 001010 10 011010 26 001011 11 011011 27 001100 12 011100 28 001101 13 011101 29 001110 14 011110 30 001111 15 011111 31 MICRVOL 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 Other values GAIN(dB) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 46 11050A–PMAAC–07-Apr-10 103 Name: Access: Address: INLVOL Read / Write 0x18 7 6 5 4 3 2 1 0 INLBOTH INLVOL Table 13-41. INLVOL (0x18) Structure Bit Name Description AUX / LINE Left volume controls Right channel 7 INLBOTH 0: inactive 1: active. Prioritary bit over INRBOTH. 6:0 INLVOL AUX / LINE input Left volume selection Reset value 1 0000000 Table 13-42. AUX / LINE Left Volume Selection Table INLVOL GAIN(dB) INLVOL GAIN(dB) ≤1011100 MUTE 1101101 -19 1011101 -35 1101110 -18 1011110 -34 1101111 -17 1011111 -33 1110000 -16 1100000 -32 1110001 -15 1100001 -31 1110010 -14 1100010 -30 1110011 -13 1100011 -29 1110100 -12 1100100 -28 1110101 -11 1100101 -27 1110110 -10 1100110 -26 1110111 -9 1100111 -25 1111000 -8 1101000 -24 1111001 -7 1101001 -23 1111010 -6 1101010 -22 1111011 -5 1101011 -21 1111100 -4 1101100 -20 1111101 -3 INLVOL 1111110 1111111 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 >=0101111 GAIN(dB) -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 104 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: INRVOL Read / Write 0x19 7 6 5 4 3 2 1 0 INRBOTH INRVOL Table 13-43. INRVOL (0x19) Structure Bit Name Description AUX / LINE Right volume controls left channel 7 INRBOTH 0: inactive 1: active. 6:0 INRVOL AUX / LINE input Right volume selection Reset value 0 0000000 Table 13-44. AUX / LINE Right Volume Selection Table INLVOL GAIN(dB) INLVOL GAIN(dB) ≤1011100 MUTE 1101101 -19 1011101 -35 1101110 -18 1011110 -34 1101111 -17 1011111 -33 1110000 -16 1100000 -32 1110001 -15 1100001 -31 1110010 -14 1100010 -30 1110011 -13 1100011 -29 1110100 -12 1100100 -28 1110101 -11 1100101 -27 1110110 -10 1100110 -26 1110111 -9 1100111 -25 1111000 -8 1101000 -24 1111001 -7 1101001 -23 1111010 -6 1101010 -22 1111011 -5 1101011 -21 1111100 -4 1101100 -20 1111101 -3 INLVOL 1111110 1111111 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 >=0101111 GAIN(dB) -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 11050A–PMAAC–07-Apr-10 105 Name: Access: Address: HPLVOL Read / Write 0x1A 7 6 5 4 3 2 1 0 HPLVOL Table 13-45. HPLVOL (0x1A) Structure Bit Name Description 7:0 HPLVOL Headphone Left volume selection Reset value 00000000 Table 13-46. Headphone Left Volume Selection Table HPLVOL GAIN (dB) HPLVOL GAIN (dB) HPLVOL ≤10110010 MUT E 11001000 -56 11011110 10110011 -77 11001001 -55 11011111 10110100 -76 11001010 -54 11100000 10110101 -75 11001011 -53 11100001 10110110 -74 11001100 -52 11100010 10110111 -73 11001101 -51 11100011 10111000 -72 11001110 -50 11100100 10111001 -71 11001111 -49 11100101 10111010 -70 11010000 -48 11100110 10111011 -69 11010001 -47 11100111 10111100 -68 11010010 -46 11101000 10111101 -67 11010011 -45 11101001 10111110 -66 11010100 -44 11101010 10111111 -65 11010101 -43 11101011 11000000 -64 11010110 -42 11101100 11000001 -63 11010111 -41 11101101 11000010 -62 11011000 -40 11101110 11000011 -61 11011001 -39 11101111 11000100 -60 11011010 -38 11110000 11000101 -59 11011011 -37 11110001 11000110 -58 11011100 -36 11110010 11000111 -57 11011101 -35 11110011 GAIN (dB) HPLVOL GAIN (dB) -34 11110100 -12 -33 11110101 -11 -32 11110110 -10 -31 11110111 -9 -30 11111000 -8 -29 11111001 -7 -28 11111010 -6 -27 11111011 -5 -26 11111100 -4 -25 11111101 -3 -24 11111110 -2 -23 11111111 -1 -22 00000000 0 -21 00000001 1 -20 00000010 2 -19 00000011 3 -18 00000100 4 -17 00000101 5 -16 >=00000110 6 -15 -14 -13 106 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: HPRVOL Read / Write 0x1B 7 6 5 4 3 2 1 0 HPRVOL Table 13-47. HPRVOL (0x1B) Structure Bit Name Description 7:0 HPRVOL HEADSET Right volume selection Reset value 00000000 Table 13-48. Headphone Right Volume Selection Table HPRVOL GAIN (dB) HPRVOL GAIN (dB) HPRVOL ≤10110010 MUTE 11001000 -56 11011110 10110011 -77 11001001 -55 11011111 10110100 -76 11001010 -54 11100000 10110101 -75 11001011 -53 11100001 10110110 -74 11001100 -52 11100010 10110111 -73 11001101 -51 11100011 10111000 -72 11001110 -50 11100100 10111001 -71 11001111 -49 11100101 10111010 -70 11010000 -48 11100110 10111011 -69 11010001 -47 11100111 10111100 -68 11010010 -46 11101000 10111101 -67 11010011 -45 11101001 10111110 -66 11010100 -44 11101010 10111111 -65 11010101 -43 11101011 11000000 -64 11010110 -42 11101100 11000001 -63 11010111 -41 11101101 11000010 -62 11011000 -40 11101110 11000011 -61 11011001 -39 11101111 11000100 -60 11011010 -38 11110000 11000101 -59 11011011 -37 11110001 11000110 -58 11011100 -36 11110010 11000111 -57 11011101 -35 11110011 GAIN (dB) -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 HPRVOL 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 00000000 00000001 00000010 00000011 00000100 00000101 >=00000110 GAIN (dB) -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 11050A–PMAAC–07-Apr-10 107 Name: Access: Address: HP_CONTROL Read / Write 0x1C 7 6 5 4 3 2 1 0 - - - - - HPDET_ST LHPBOTH RHPBOTH Table 13-49. HP_CONTROL (0x1C) Structure Bit Name Description 7:3 - unused Headphone plug in-out detector 2 HPDET_ST 0: OFF 1: ON Right Headphone volume follows left 1 LHPBOTH 0: inactive 1: active. Prioritary bit over RHPBOTH. Left Headphone volume follows right 0 RHPBOTH 0: inactive 1: active Reset value 00000 0 1 0 108 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: AUDIO_EFFECTS Read / Write 0x1D 7 6 3DFX_DEPTH 5 ON3DFX 4 3 2 1 0 SWAP_DAC SWAP_ADC MONO_DAC MONO_ADC ONDEEMP Table 13-50. AUDIO_EFFECTS (0x1D) Structure Bit Name Description 7:6 3DFX_DEPTH 3D effect depth control 3D effect 5 ON3DFX 0: OFF 1: ON DAC Left / Right channel swap 4 SWAP_DAC 0: Left / Right inputs on Left / Right outputs 1: Left / Right inputs on Right / Left outputs ADC Left / Right channel swap 3 SWAP_ADC 0: Left / Right inputs on Left / Right outputs 1: Left / Right inputs on Right / Left outputs (Left + Right) / 2 on Left and Right channels 2 MONO_DAC 0: inactive 1: active Left ADC output on both Left and Right channels 1 MONO_ADC 0: inactive 1: active De-emphasis filter 0 ONDEEMP 0: OFF 1: ON Reset value 00 0 0 0 0 0 0 Table 13-51. 3-D Effect Depth Control Table 3DFX_DEPTH Attenuation 00 0dB 01 -6dB 10 -12dB 11 -18dB 11050A–PMAAC–07-Apr-10 109 Name: Access: Address: INPUT_CONTROL Read / Write. This register is modified by Audio Controller at audio path change. 0x1E 7 6 5 4 3 - LINESEL ONMICL ONMICR ONADCL Table 13-52. INPUT_CONTROL (0x1E) Structure Bit Name Description 7 unused LINE / AUX input selection 6 LINESEL 0: Aux input selected 1: Line input selected Left microphone amplifier 5 ONMICL 0: OFF 1: ON Right microphone amplifier 4 ONMICR 0: OFF 1: ON Left ADC 3 ONADCL 0: OFF 1: ON Right ADC 2 ONADCR 0: OFF 1: ON Left line input amplifier 1 ONLINL 0: OFF 1: ON Right line input amplifier 0 ONLINR 0: OFF 1: ON 2 ONADCR 1 ONLINL 0 ONLINR Reset value 0 1 0 0 0 0 0 0 110 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: OUTPUT_CONTROL Read / Write This register is modified by Audio Controller at audio path change. 0x1F 7 6 5 4 3 2 1 0 - ONSIDETONE ONPLAYBACK ONBYPASS ONHPL ONHPR ONDACL ONDACR Table 13-53. OUTPUT_CONTROL (0x1F) Structure Bit Name Description 7 unused Sidetone switch 6 ONSIDETONE 0: muted 1: enabled Playback switch 5 ONPLAYBACK 0: muted 1: enabled Bypass switch 4 ONBYPASS 0: muted 1: enabled Left headphone amplifier 3 ONHPL 0: OFF 1: ON Right headphone amplifier 2 ONHPR 0: OFF 1: ON Left DAC 1 ONDACL 0: OFF 1: ON Right DAC 0 ONDACR 0: OFF 1: ON Reset value 0 0 0 0 0 0 0 0 11050A–PMAAC–07-Apr-10 111 Name: Access: Address: INPUT_MIXER Read / Write This register is modified by Audio Controller at audio path change. 0x20 7 6 5 4 3 2 - - MIXMICL MIXMICR MIXLINEL MIXLINER Table 13-54. INPUT_MIXER (0x20) Structure Bit Name Description 7:6 - unused Left microphone input mixer switch 5 MIXMICL 0: muted 1: enabled Right microphone input mixer switch 4 MIXMICR 0: muted 1: enabled Left line / aux input mixer switch 3 MIXLINEL 0: muted 1: enabled Right line / aux input mixer switch 2 MIXLINER 0: muted 1: enabled Left input mixer ON / OFF 1 ONMIXL 0: muted 1: enabled Right input mixer ON / OFF 0 ONMIXR 0: muted 1: enabled 1 ONMIXL 0 ONMIXR Reset value 00 0 0 0 0 0 0 112 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: SIDETONE_VOL Read / Write 0x21 7 6 5 4 3 2 1 0 - - - SIDETONE_VOL Table 13-55. SIDETONE_VOL (0x21) Structure Bit Name Description 7:5 unused 4:0 SIDETONE_VOL Left / Right sidetone path attenuation Reset value 000 01011 Table 13-56. Left / Right Sidetone Path Attenuation Selection Table SIDETONE_VOL ATT(dB) SIDETONE_VOL ATT(dB) SIDETONE_VOL 00000 0 00100 12 01000 00001 3 00101 15 01001 00010 6 00110 18 01010 00011 9 00111 21 >=01011 ATT(dB) 24 27 30 30 11050A–PMAAC–07-Apr-10 113 Name: Access: Address: EQUALIZER Read / Write 0x22 7 6 5 4 3 - - - - Table 13-57. EQUALIZER (0x22) Structure Bit Name Description 7:4 3:0 EQ_SEL Equalizer selection Table 13-58. Equalizer Selection Table(0x22) Structure EQ_SEL Description 0000 Flat Response 0001 Bass boost +12dB 0010 Bass boost +6dB 0011 Bass cut -12dB 0100 Bass cut -6dB 0101 Medium boost +3dB 0110 Medium boost +8dB 0111 Medium cut -3dB 1000 Medium cut -8dB 1001 Treble boost +12dB 1010 Treble boost +6dB 1011 Treble cut -12dB 1100 Treble cut -6dB Other value Flat response. 2 1 0 EQ_SEL Reset value 0 0000 114 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_CTRL Read / Write 0x30 7 6 5 4 3 ON_ADC ON_BUF - - - Table 13-59. ADC_CTRL (0x30) Structure Bit Name Description ADC function 7 ON_ADC 0: OFF 1: ON Analog buffer 6 ON_BUF 0: OFF 1: ON 5:3 unused - 2:0 TS Sampling period Table 13-60. ADC Sampling Period Selection Table TS SAMPLING PERIOD (s) 000 0.01 001 0.02 010 0.1 011 1 100 2 101 3 110 4 111 Max speed AT73C246 2 1 0 TS Reset value 0 0 000 000 11050A–PMAAC–07-Apr-10 115 Name: Access: Address: ADC_MUX_1 Read / Write 0x31 7 6 5 4 3 - VIN - VDD4 VDD3 Table 13-61. ADC_MUX1 (0x31) Structure Bit Name Description 7 unused - VIN channel selection 6 VIN 0: Not selected 1: Selected 5 unused - VDD4 channel selection 4 VDD4 0: Not selected 1: Selected VDD3 channel selection 3 VDD3 0: Not selected 1: Selected VDD2 channel selection 2 VDD2 0: Not selected 1: Selected VDD1 channel selection 1 VDD1 0: Not selected 1: Selected VDD0 channel selection 0 VDD0 0: Not selected 1: Selected 2 VDD2 1 VDD1 0 VDD0 Reset value 0 1 1 1 1 1 1 1 116 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: ADC_MUX_2 Read / Write 0x32 7 6 5 4 3 - - - - ANA3 Table 13-62. ADC_MUX2 (0x32) Structure Bit Name Description 7:4 unused - ANA3 channel selection 3 ANA3 0: Not selected 1: Selected ANA2 channel selection 2 ANA2 0: Not selected 1: Selected ANA1 channel selection 1 ANA1 0: Not selected 1: Selected ANA0 channel selection 0 ANA0 0: Not selected 1: Selected 2 ANA2 1 ANA1 0 ANA0 Reset value 0000 1 1 1 1 11050A–PMAAC–07-Apr-10 117 Name: Access: Address: ADC_ANA0_MSB Read Only 0x33 7 6 5 4 3 2 ADC<9:2> Table 13-63. ADC_ANA0_MSB (0x33) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for ANA0 Channel Name: Access: Address: ADC_ANA0_LSB Read Only 0x34 7 6 5 4 3 2 Table 13-64. ADC_ANA0_LSB (0x34) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for ANA0 Channel 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 118 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_ANA1_MSB Read Only 0x35 7 6 5 4 3 2 ADC<9:2> Table 13-65. ADC_ANA1_MSB (0x35) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for ANA1 Channel Name: Access: Address: ADC_ANA1_LSB Read Only 0x36 7 6 5 4 3 2 Table 13-66. ADC_ANA1_LSB (0x36) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for ANA1 Channel AT73C246 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 11050A–PMAAC–07-Apr-10 119 Name: Access: Address: ADC_ANA2_MSB Read Only 0x37 7 6 5 4 3 2 ADC<9:2> Table 13-67. ADC_ANA2_MSB (0x37) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for ANA2 Channel Name: Access: Address: ADC_ANA2_LSB Read Only 0x38 7 6 5 4 3 2 Table 13-68. ADC_ANA2_LSB (0x38) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for ANA2 Channel 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 120 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_ANA3_MSB Read Only 0x39 7 6 5 4 3 2 ADC<9:2> Table 13-69. ADC_ANA3_MSB (0x39) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for ANA3 Channel Name: Access: Address: ADC_ANA3_LSB Read Only 0x3A 7 6 5 4 3 2 Table 13-70. ADC_ANA3_LSB (0x3A) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for ANA3 Channel AT73C246 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 11050A–PMAAC–07-Apr-10 121 Name: Access: Address: ADC_VDD0_MSB Read Only 0x3B 7 6 5 4 3 2 ADC<9:2> Table 13-71. ADC_VDD0_MSB (0x3B) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for VDD0 Channel Name: Access: Address: ADC_VDD0_LSB Read Only 0x3C 7 6 5 4 3 2 Table 13-72. ADC_VDD0_LSB (0x3C) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VDD0 Channel 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 122 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_VDD1_MSB Read Only 0x3D 7 6 5 4 3 2 ADC<9:2> Table 13-73. ADC_VDD1_MSB (0x3D) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for VDD1 Channel Name: Access: Address: ADC_VDD1_LSB Read Only 0x3E 7 6 5 4 3 2 Table 13-74. ADC_VDD1_LSB (0x3E) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VDD1 Channel AT73C246 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 11050A–PMAAC–07-Apr-10 123 Name: Access: Address: ADC_VDD2_MSB Read Only 0x3F 7 6 5 4 3 2 ADC<9:2> Table 13-75. ADC_VDD2_MSB (0x3F) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for VDD2 Channel Name: Access: Address: ADC_VDD2_LSB Read Only 0x40 7 6 5 4 3 2 Table 13-76. ADC_VDD2_LSB (0x40) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VDD2 Channel 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 124 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_VDD3_MSB Read Only 0x41 7 6 5 4 3 2 ADC<9:2> Table 13-77. ADC_VDD3_MSB (0x41) Structure Bit Name Description 7:2 ADC<9:2> ADC_OUT<9:2> for VDD3 Channel Name: Access: Address: ADC_VDD3_LSB Read Only 0x42 7 6 5 4 3 2 Table 13-78. ADC_VDD3_LSB (0x42) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VDD3 Channel AT73C246 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 11050A–PMAAC–07-Apr-10 125 Name: Access: Address: ADC_VDD4_MSB Read Only 0x43 7 6 5 4 3 2 ADC<9:2> Table 13-79. ADC_VDD4_MSB (0x43) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for VDD4 Channel Name: Access: Address: ADC_VDD4_LSB Read Only 0x44 7 6 5 4 3 2 Table 13-80. ADC_VDD4_LSB (0x44) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VDD4 Channel 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 126 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: ADC_VIN_MSB Read Only 0x47 7 6 5 4 3 2 ADC<9:2> Table 13-81. ADC_VIN_MSB (0x47) Structure Bit Name Description 7:0 ADC<9:2> ADC_OUT<9:2> for VIN Channel Name: Access: Address: ADC_VIN_LSB Read Only 0x48 7 6 5 4 3 2 Table 13-82. ADC_VIN_LSB (0x48) Structure Bit Name Description 7:2 - unused 1:0 ADC<1:0> ADC_OUT<1:0> for VIN Channel AT73C246 1 0 Reset value 00000000 1 0 ADC<1:0> Reset value 00 11050A–PMAAC–07-Apr-10 127 Name: Access: Address: ADC_ANA_LSB Read Only 0x49 7 6 ADC_ANA3<1:0> 5 4 ADC_ANA2<1:0> 3 2 ADC_ANA1<1:0> Table 13-83. ADC_ANA_LSB (0x49) Structure Bit Name Description 7:6 ADC_ANA3<1:0> ADC_OUT<1:0:> for ANA3 Channel 5:4 ADC_ANA2<1:0> ADC_OUT<1:0:> for ANA2 Channel 3:2 ADC_ANA1<1:0> ADC_OUT<1:0:> for ANA1 Channel 1:0 ADC_ANA0<1:0> ADC_OUT<1:0:> for ANA0 Channel 1 0 ADC_ANA0<1:0> Reset value 00 00 00 00 Name: Access: Address: RTC_CTRL Read / Write 0x50 7 6 5 4 3 2 1 0 - - RTC_WRITE RTC_SEL RTC_EN Table 13-84. RTC_CTRL (0x50) Structure Bit Name Description 7:3 - unused RTC read/write: 2 RTC_WRITE RTC_WRITE = 0: Read mode RTC_WRITE = 1: Write mode RTC block select: 1 RTC_SEL RTC_SEL = 0: Not Selected RTC_SEL = 1: Selected RTC block enable: 0 RTC_EN RTC_EN = 0: Disabled RTC_EN = 1: Enabled Reset value 0 0 0 128 AT73C246 11050A–PMAAC–07-Apr-10 Name: Access: Address: RTC_ADDR Read / Write 0x51 7 6 5 4 3 RTC_ADDR Table 13-85. RTC_ADDR (0x51) Structure Bit Name Description 7:0 RTC_ADDR RTC address Name: Access: Address: RTC_DATA0 Read / Write 0x52 7 6 5 4 3 RTC_DATA0 Table 13-86. RTC_DATA0 (0x52) Structure Bit Name Description 7:0 RTC_DATA0 RTC DATA 0 AT73C246 2 1 0 Reset value 0000 2 1 0 Reset value 0000000 11050A–PMAAC–07-Apr-10 129 Name: Access: Address: RTC_DATA1 Read / Write 0x53 7 6 5 4 3 2 1 0 RTC_DATA1 Table 13-87. RTC_DATA1 (0x53) Structure Bit Name Description 7:0 RTC_DATA1 RTC DATA 1 Reset value 0000000 Name: Access: Address: RTC_DATA2 Read / Write 0x54 7 6 5 4 3 2 1 0 RTC_DATA2 Table 13-88. RTC_DATA2 (0x54) Structure Bit Name Description 7:0 RTC_DATA2 RTC DATA 2 Reset value 0000000 Name: Access: Address: RTC_DATA3 Read / Write 0x55 7 6 5 4 3 2 1 0 RTC_DATA3 Table 13-89. RTC_DATA3 (0x55) Structure Bit Name Description 7:0 RTC_DATA3 RTC DATA 3 Reset value 0000000 130 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 Name: Access: Address: BACKUP_CTRL Read / Write 0x56 7 6 5 4 3 2 1 0 - - - - OSC_UPDT OSC_EN OSC_STAT RST_BKUP Table 13-90. BACKUP_CTRL (0x56) Structure Bit Name Description 7:4 - unused RTC Oscillator update 3 OSC_UPDT 0: No action. 1: Update RTC oscillator with OSC_EN RTC Oscillator enable request 2 OSC_EN 0: Oscillator off. 1: Oscillator on. RTC Oscillator status (read only) 1 OSC_STAT 0: Oscillator off. 1: Oscillator on. Reset of the Backup Area 0 RST_BKUP 0: Backup area active 1: Backup area in reset state Reset value 0000 0 0 0 0 Name: Access: Address: VERSION Read 0x7F 7 6 5 4 3 2 1 0 SOFTWARE_TAG VERSION Table 13-91. VERSION (0x7F) Structure Bit Name Description Software Tag to identify product specificities as 7:4 SOFTWARE_TAG described in Section 17. “Ordering Information” on page 154. ‘0001’: Rev. C samples 3:0 VERSION ‘0010’: Rev. D samples Reset value XXXX XXXX 11050A–PMAAC–07-Apr-10 131 14. PMU and Audio Soft Control: Quick Start 14.1 RTC Examples 14.1.1 RTC Oscillator POWER-ON // Set OSC_EN = 1 and OSC_UPDT = 1 TWI_WRITE 0x0C @BACKUP_CTRL // Wait > 200us. WAIT 200us // Set OSC_UPDT = 0 TWI_WRITE 0x04 @BACKUP_CTRL // Read BACKUP_CTRL to verify OSC_STAT bit. Result = 0x06. TWI_READ @BACKUP_CTRL 14.1.2 RTC Oscillator POWER-OFF // Set OSC_EN = 0 and OSC_UPDT = 1 TWI_WRITE 0x08 @BACKUP_CTRL // Wait 200us WAIT 200us // Set OSC_UPDT = 0 TWI_WRITE 0x00 @BACKUP_CTRL // Read BACKUP_CTRL to verify OSC_STAT bit. Result = 0x00. TWI_READ @BACKUP_CTRL 14.1.3 RTC Domain RESET // Set RST_BKUP = 1 TWI_WRITE 0x01 @BACKUP_CTRL // Wait 200s WAIT 200us // Set RST_BKUP = 0 TWI_WRITE 0x00 @BACKUP_CTRL 14.1.4 Note: Reset of the RTC domain powers off the RTC oscillator. RTC Write Operation The following example makes a generic 32-bit write operation into the RTC macro. The 32-bit data is split into 4 bytes, that are successively sent over the TWI. unsigned int RTC_DATA; char DATA0 = (char) (RTC_DATA); // LSBs char DATA1 = (char) (RTC_DATA >> 8); char DATA2 = (char) (RTC_DATA >> 16); char DATA3 = (char) (RTC_DATA >> 24); // MSBs // Select RTC_ADDR = ADDR. ADDR is the RTC macro register to write, TWI_WRITE ADDR @RTC_ADDR // Set RTC_DATA0 to RTC_DATA4 registers. TWI_WRITE DATA0 @RTC_DATA0 TWI_WRITE DATA1 @RTC_DATA1 132 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 14.1.5 14.1.6 TWI_WRITE DATA2 @RTC_DATA2 TWI_WRITE DATA3 @RTC_DATA3 // Set RTC_WRITE = 1 (write) and RTC_SEL = 1 TWI_WRITE 0x06 @ RTC_CTRL // Pulse RTC_EN TWI_WRITE 0x07 @ RTC_CTRL TWI_WRITE 0x06 @ RTC_CTRL // Disable RTC access TWI_WRITE 0x00 @ RTC_CTRL RTC Read Operation The following example makes a generic 32-bit read operation into the RTC macro. The 32-bit RTC data is split into 4 bytes, that are successively read over the TWI. // Select RTC_ADDR = ADDR. ADDR is the RTC macro register to read, TWI_WRITE ADDR @RTC_ADDR // Set RTC_WRITE = 0 (read) and RTC_SEL = 1 TWI_WRITE 0x02 @ RTC_CTRL // Pulse RTC_EN TWI_WRITE 0x03 @ RTC_CTRL TWI_WRITE 0x02 @ RTC_CTRL // Read RTC_DATA0 to RTC_DATA4 registers. TWI_READ @RTC_DATA0 // LSBs TWI_READ @RTC_DATA1 TWI_READ @RTC_DATA2 TWI_READ @RTC_DATA3 // MSBs // Disable RTC access TWI_WRITE 0x00 @ RTC_CTRL RTC Date and Time Update In the following example, the RTC date and time is set to “12 October 2004, 08h 49min 59s”. The WRITE_RTC and READ_RTC functions operate as described in the previous sections. // Disable RTC interrupt MASK TWI_WRITE 0xFE @PMU_MASK // Enable RTC ACKUPD IT @RTC_IER (RTC_ADDR 0x20). WRITE_RTC 0x00000001 @RTC_IER // Set UPDTIME and UPDCAL @RTC_CR (RTC_ADDR 0x00). WRITE_RTC 0x00000003 @RTC_CR // Wait ITB low. This ensures that the RTC is ready to be updated. // Reset IT by read operation, result is 0x01. TWI_READ @PMU_IT // Read in RTC_SR that ACKUPD = 1 (RTC_ADDR = 0x18) READ_RTC @RTC_SR // Disable ACKUPD IT @RTC_IDR (RTC_ADDR = 0x24) WRITE_RTC 0x00000001 @RTC_IDR // Write Date @RTC_CALR (RTC_ADDR = 0x0C) (12 October 2004) WRITE_RTC 0x12300420 @RTC_CALR 11050A–PMAAC–07-Apr-10 133 // Write Time @RTC_TIMR (RTC_ADDR = 0x08) (08h 49min 59s) WRITE_RTC 0x00084959 @RTC_TIMR // Start RTC @RTC_CR (RTC_ADDR = 0x00) WRITE_RTC 0x00000000 @RTC_CR 14.2 Audio Examples 14.2.1 Basic Audio Codec Setting Using Automatic Path Control The following example demonstrates an automatic audio path setting. Assuming that the audio codec is supplied by the LDO4, the sequence is the following: • Make the codec interface configuration, • Set the Digital-IN to Headphone-OUT path, • Put the audio codec in standby mode, • Release the standby mode to re-activate the selected path, • Change the path on-the-fly, • Shutdown the codec. // Start LDO4 @3.3V TWI_WRITE 0x8C @ VDD4_CTRL // Digital Audio Interface configuration // Master clock = 12.288MHz, Master / Slave = slave. // DAI mode = I2S mode, Word length = 24 bits, FS = 48kHz TWI_WRITE 0x01 @ DAI_CONTROL TWI_WRITE 0x63 @ FRAME_CONTROL // Analog interface configuration // Mic. config: L & R single ended, Micbias = OFF, Mic. detection = OFF. // Headphone config: AC coupled, // Automatic Soft Ramping = ON, ASR timing = 11 (~10ms / step) TWI_WRITE 0x00 @ MIC_CONTROL TWI_WRITE 0x27 @ AUDIO_CONTROL // Analog gain // Headphone (L & R) gain: -20dB. (LHPBOTH set by default in HP_CONTROL) // Mic L & R gain: +26 dB. // Unmute all gains. No power-up is performed. TWI_WRITE 0xEC @ HPLVOL TWI_WRITE 0x1A @ MICLVOL TWI_WRITE 0x1A @ MICRVOL TWI_WRITE 0x00 @ MUTE // Audio Start // ENAC = 1, STANDBY = 1. PATH = 1 (DAC playback) // At the first start, VMID capacitor is charged. 134 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 // Wait (3.tau) = 300ms with 1uF before standby release. (VMID will be // discharged only when ENAC = 0.) // From this point Audio Data can be sent over the Digital audio interface. TWI_WRITE 0x61 @ AUTOSTART. WAIT 300ms // Release standby. The audio codec starts silently, the gains are slowly // ramped up from mute to the register gains. The codec is active. TWI_WRITE 0x41 @ AUTOSTART // Codec Pause by Standby // All gains are softly ramped down to mute. The codec functions are // shut down. Current consumption is reduced to a few hundreds of micro// amps. VMID remains charged TWI_WRITE 0x61 @ AUTOSTART // Pause out: Standby release. The codec softly re-starts. TWI_WRITE 0x41 @ AUTOSTART // On-the-fly path change // PATH = 19: Digital IN to Headphone OUT + Mic IN to Digital OUT. // The codec controller powers up automatically the new path. The DAC // playback is not affected by starting the Mic. recording. TWI_WRITE 0x52 @ AUTOSTART 14.2.2 // Codec Shutdown. ENAC = 0, STANDBY = 1. The codec turns off smoothly. // In case of AC Coupling output configuration, HPR & HPL will slowly // discharge following VMID time constant. TWI_WRITE 0x20 @ AUTOSTART WAIT 600ms // Disable DCBLOCK bit. TWI_WRITE 0x07 @ AUDIO_CONTROL // LDO4 shutdown. TWI_WRITE 0x0C @ VDD4_CONTROL Basic Audio Codec Setting Using Custom Path Control The following example demonstrates a custom audio path setting. Assuming that the audio codec is supplied by the LDO4, the sequence is the following: • Make the codec analog and digital interfaces configuration, • Enter the custom path mode and configure a path with DAC input and Headphone Amplifier output, • Put the audio codec in standby mode, • Release the standby mode to re-activate the selected path, • Change the path on-the-fly to add the microphone inputs to the DAC signal, • Shutdown the codec. 11050A–PMAAC–07-Apr-10 135 // Start LDO4 @3.3V TWI_WRITE 0x8C @ VDD4_CTRL // Digital Audio Interface configuration // Master clock = 12.288MHz, Master / Slave = slave. // DAI mode = I2S mode, Word length = 24 bits, FS = 48kHz TWI_WRITE 0x01 @ DAI_CONTROL TWI_WRITE 0x63 @ FRAME_CONTROL // Analog interface configuration // Mic. config: L & R single ended, Micbias = OFF, Mic. detection = OFF. // Headphone config: AC coupled, // Automatic Soft Ramping = ON, ASR timing = 11 (~10ms / step) TWI_WRITE 0x00 @ MIC_CONTROL TWI_WRITE 0x27 @ AUDIO_CONTROL // Analog gain // Headphone (L & R) gain: -20dB. (LHPBOTH set by default in HP_CONTROL) // Mic L & R gain: +26 dB. // Unmute all gains. No power-up is performed. TWI_WRITE 0xEC @ HPLVOL TWI_WRITE 0x1A @ MICLVOL TWI_WRITE 0x1A @ MICRVOL TWI_WRITE 0x00 @ MUTE // Enter the custom path configuration mode TWI_WRITE 0x2F @ AUDIO_CONTROL // Audio Start // ENAC = 1, STANDBY = 1. PATH = 0 (Not read by the audio controller) // At the first start, VMID capacitor is charged. // Wait (3.tau) = 300ms with 1uF before standby release. (VMID will be // discharged only when ENAC = 0.) // From this point Audio Data can be sent over the Digital audio interface. TWI_WRITE 0x60 @ AUTOSTART. WAIT 300ms // Audio path definition: DAC input to Headphone output. The software sets // the bits: ONDACL, ONDACR, ONHPL, ONHPR and PLAYBACK by writing // the registers INPUT_CONTROL, OUTPUT_CONTROL, and INPUT_MIXER. // The changes are not taken immediately into account (ENCONF = 0). TWI_WRITE 0x40 @ INPUT_CTRL TWI_WRITE 0x2F @ OUTPUT_CTRL TWI_WRITE 0x00 @ INPUT_MIXER // ENCONF pulse: the audio controller takes the requested changes into 136 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 // account. TWI_WRITE 0x3F @ AUDIO_CONTROL TWI_WRITE 0x2F @ AUDIO_CONTROL // STANDBY release. The codec softly starts. TWI_WRITE 0x40 @ AUTOSTART. // Codec Pause by Standby // All gains are softly ramped down to mute. The codec functions are // shut down. Current consumption is reduced to a few hundreds of micro// amps. VMID remains charged TWI_WRITE 0x60 @ AUTOSTART // Pause out: Standby release. The codec softly re-starts. TWI_WRITE 0x40 @ AUTOSTART // On-the-fly path change: the stereo microphone inputs are added to the // DAC playback. The software sets: ONMICL, ONMICR, and ONSIDETONE. TWI_WRITE 0x70 @ INPUT_CTRL TWI_WRITE 0x6F @ OUTPUT_CTRL TWI_WRITE 0x00 @ INPUT_MIXER // Sidetone gain TWI_WRITE 0x00 @ SIDETONE_VOL // ENCONF pulse: the audio controller takes the requested changes into // account. The path modification is here immediate because STANDBY=0. TWI_WRITE 0x3F @ AUDIO_CONTROL TWI_WRITE 0x2F @ AUDIO_CONTROL // Codec Shutdown. ENAC = 0, STANDBY = 1. The codec turns off smoothly. // In case of AC Coupling output configuration, HPR & HPL will slowly // discharge following VMID time constant. TWI_WRITE 0x20 @ AUTOSTART WAIT 600ms // Disable DCBLOCK bit. TWI_WRITE 0x07 @ AUDIO_CONTROL // LDO4 shutdown. TWI_WRITE 0x0C @ VDD4_CONTROL 11050A–PMAAC–07-Apr-10 137 138 AT73C246 11050A–PMAAC–07-Apr-10 15. Typical Performance Characteristics 15.1 PMU: Power Supply Sequences Figure 15-1. Powerdown State to Run State Supplies Start-Up AT73C246 Powerdown to Run State SEQUENCE A Figure 15-2. Run Sate to Powerdown State Supplies Shut-Down Powerdown to Run State SEQUENCE B Run to Powerdown State SEQUENCE A 11050A–PMAAC–07-Apr-10 Run to Powerdown State SEQUENCE B 139 Figure 15-3. Detailed Supplies Start-Up Detailed Supplies Start-Up SEQUENCE A Figure 15-4. Detailed Supplies Shutdown Detailed Supplies Start-Up SEQUENCE B Detailed Supplies Shutdown SEQUENCE A Detailed Supplies shutdown SEQUENCE B 140 AT73C246 11050A–PMAAC–07-Apr-10 Figure 15-5. Run State to Standby State AT73C246 Run To Standby State (default setting) SEQUENCE A Figure 15-6. Standby To Run State Run To Standby State (default setting) SEQUENCE B Standby To Run State (default setting) SEQUENCE A Standby To Run State (default setting) SEQUENCE B 11050A–PMAAC–07-Apr-10 141 15.2 DCDC0 and DCDC1 Unless otherwise noted, the reported measurement were performed at room temperature. External components are those described in Section 5. “Application Block Diagram” on page 8. Figure 15-7. DCDC0 Transient Load Regulation Performance DCDC0 - VIN = 3.3V - VOUT = 1.85V Load Step 0 To 600mA / 1us DCDC0 - VIN = 3.3V - VOUT = 1.85V Load Step 600 To 0mA / 1us DCDC0 - VIN = 5.5V - VOUT = 1.85V Load Step 0 To 600mA / 1us 142 AT73C246 DCDC0 - VIN = 5.5V - VOUT = 1.85V Load Step 600 To 0mA / 1us 11050A–PMAAC–07-Apr-10 Figure 15-8. DCDC0 Ripple and Efficency Performance AT73C246 DCDC0 - VOUT = 1.8V Efficiency in PFM and PWM modes DCDC0 - VIN = 5.5V - VOUT = 1.8V Output Voltage Ripple 11050A–PMAAC–07-Apr-10 143 Figure 15-9. DCDC1Transient Load Regulation Performance DCDC0 - VIN = 3.3V - VOUT = 1.2V Load Step 0 To 600mA / 1us DCDC0 - VIN = 3.3V - VOUT = 1.2V Load Step 600 To 0mA / 1us DCDC0 - VIN = 5.5V - VOUT = 1.2V Load Step 0 To 600mA / 1us DCDC0 - VIN = 5.5V - VOUT = 1.2V Load Step 600 To 0mA / 1us 144 AT73C246 11050A–PMAAC–07-Apr-10 Figure 15-10. DCDC0 Ripple and Efficiency Performance AT73C246 DCDC1 - VOUT = 1.2V Efficiency in PFM and PWM modes DCDC1 - VIN = 5.5V - VOUT = 1.2V Output Voltage Ripple 11050A–PMAAC–07-Apr-10 145 15.3 LDO2 Unless otherwise noted, the reported measurement were performed at room temperature. External components are those described in Section 5. “Application Block Diagram” on page 8. Figure 15-11. LDO2 Tansient and Static Load Regulation Performance LDO2- VIN = 1.8V - VOUT = 1V Load Step 0 To 300mA / 1us LDO2 - VIN = 1.8V - VOUT = 1V Load Step 300 To 0mA / 1us LDO2 - VIN = 1.8V - VOUT = 1V Static Load Regulation - 0 To 300mA LDO2 - VIN = 1.7V - VOUT = 1.2V Static Load Regulation - 0 To 300mA 146 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 15.4 LDO3 Unless otherwise noted, the reported measurement were performed at room temperature. External components are those described in Section 5. “Application Block Diagram” on page 8. Figure 15-12. LDO3 Transient and Static Load Regulation Performance LDO3- VIN = 5.5V - VDD3 = 3.3V Load Step 0 To 200mA / 1us LDO3 - VIN = 5.5V - VDD3 = 3.3V Load Step 200 To 0mA / 1us LDO3 - VIN = 3.6V - VDD3 = 3.3V Static Load Regulation - 0 To 200mA LDO3 - VDD3 = 3.3V - 200mA output load Drop Out Characteristic. (VDD3REG = VDD3 with VIN3 > VDD3 + 300mV) 11050A–PMAAC–07-Apr-10 147 15.5 AUDIO Unless otherwise noted, the reported measurement were performed at room temperature with AVDD = 3.3V supplied from LDO4. Typical components as described in Section 5. “Application Block Diagram” on page 8 are used. Figure 15-13. Microphone Recording Waveforms Differential Microphone Recording ( Path 5) -1dBV / 1kHz Input - Fs = 48kHz - 16kpts FFT Differential Microphone Recording ( Path 5) -60dBV / 1kHz Input - Fs = 48kHz - 16kpts FFT Differential Microphone Recording ( Path 5) THD+N Ratio Versus Input Level 148 AT73C246 11050A–PMAAC–07-Apr-10 Figure 15-14. DAC Playback Waveforms AT73C246 DAC playback ( Path 1) - Load 10k 0 dBFs / 1kHz Input - Fs = 48kHz - 32kpts FFT DAC playback ( Path 1) - Load 10k -60 dBFs / 1kHz Input - Fs = 48kHz - 32kpts FFT DAC playback ( Path 1) - Load 10k THD+N Ratio Versus Input Level DAC playback ( Path 1) - Load 32 Ohms AC coupled 20mW Ouput Power - Fs = 48kHz - 32kpts FFT 11050A–PMAAC–07-Apr-10 149 Figure 15-15. Line Record Waveforms Line Record (path 7) -1 dBV / 1kHz Input - Fs = 48kHz - 32kpts FFT Line Record (path 7) -60 dBV / 1kHz Input - Fs = 48kHz - 32kpts FFT Line Record (path 7) THD+N Ratio Versus Input Level 150 AT73C246 11050A–PMAAC–07-Apr-10 Figure 15-16. Line Bypass Waveforms AT73C246 Line Bypass (path 5) 0 dBV / 1kHz Input - 10k load - 16kpts FFT Line Bypass (path 5) -60 dBV / 1kHz Input - 10k load - 16kpts FFT Line Record (path 5) - 10k load THD+N Ratio Versus Input Level 11050A–PMAAC–07-Apr-10 151 152 AT73C246 11050A–PMAAC–07-Apr-10 16. Package Information Figure 16-1. Mechanical Package Drawing for 64-lead Quad Flat No Lead Package AT73C246 11050A–PMAAC–07-Apr-10 153 17. Ordering Information Table 17-1. Ordering Information Ordering Code and Marking Package AT73C246 QFN64 7.5 x7.5mm Green AT73C246-A QFN64 7.5 x7.5mm Green AT73C246-B QFN64 7.5 x7.5mm Green Temperature Operating Range -40°C to +85°C -40°C to +85°C -40°C to +85°C Supplies Default Values VDD0 = 1.85V VDD1 = 1.20V VDD2 = 1.00V VDD3 = 3.30V VDD4 = 3.30V VDD0 = 1.80V VDD1 = 1.20V VDD2 = 1.20V VDD3 = 3.30V VDD4 = 3.30V VDD0 = 1.80V VDD1 = 1.00V VDD2 = 1.00V VDD3 = 3.30V VDD4 = 3.30V Power Sequence Type(2) A B B Software Tag(1) 0000 0001 0010 Notes: 1. See “VERSION” (0x7F) register definition. 2. See “Power Manager State Description” on page 29 and “Typical Performance Characteristics” on page 139. 154 AT73C246 11050A–PMAAC–07-Apr-10 18. Revision History Table 18-1. Revision History Doc. Rev 11050A Date 07-Apr-10 Comments First issue AT73C246 Change Request Ref. 11050A–PMAAC–07-Apr-10 155 156 AT73C246 11050A–PMAAC–07-Apr-10 AT73C246 1 Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 Package and Pinout ................................................................................. 4 4 Pin Description ......................................................................................... 5 5 Application Block Diagram ..................................................................... 8 6 Absolute Maximum Ratings .................................................................. 11 7 Recommended Operating Conditions .................................................. 11 8 Power Dissipation Ratings .................................................................... 11 9 PMU Electrical Characteristics ............................................................. 12 9.1Current Consumption Versus Modes ......................................................................12 9.2Supply Monitor Thresholds ......................................................................................12 9.3Digital I/Os DC Characteristics ................................................................................13 9.4DCDC0 and DCDC1 ................................................................................................14 9.5LDO2 .......................................................................................................................16 9.6LDO3 .......................................................................................................................17 9.7LDO4 .......................................................................................................................18 9.8LDO5 .......................................................................................................................19 9.9Measurement Bridge and 10-bit ADC .....................................................................20 9.10RTC Crystal Oscillator ...........................................................................................21 9.11Die Temperature Sensor .......................................................................................21 10 Audio Codec Electrical Characteristics ............................................... 22 11 PMU Functional Description ................................................................. 25 11.1Power Manager State Diagram .............................................................................25 11.2PMU Startup and Shutdown State Diagram ..........................................................26 11.3Power Manager Conditional Transitions ................................................................27 11.4Power Manager State Description .........................................................................29 11.5DCDC0 and DCDC1 Functional Description .........................................................36 11.6LDO2 Functional Description .................................................................................37 11.7LDO3 and LDO4 Functional Description ...............................................................37 11.8Power Fail Detectors .............................................................................................38 11.9Measurement Bridge and 10-bit ADC ....................................................................38 11.10Real Time Clock (RTC) User Interface ................................................................40 11.11Die Temperature Sensor .....................................................................................54 i 11050A–PMAAC–07-Apr-10 12 Audio Codec Functional Description ................................................... 55 12.1Description .............................................................................................................55 12.2Audio Codec Block Diagram ..................................................................................55 12.3Audio Codec Controls ............................................................................................56 12.4Audio Controller .....................................................................................................57 12.5Audio Codec Power Consumption Versus Programmed Audio Path ....................63 12.6Digital Audio Interface ...........................................................................................66 12.7Digital Filters Transfer Function .............................................................................68 12.8Analog Audio Interfaces ........................................................................................74 13 Two Wire Interface and Control Registers ........................................... 77 13.1Two-wire Interface (TWI) Protocol .........................................................................77 13.2PMU Register Tables ............................................................................................79 14 PMU and Audio Soft Control: Quick Start ......................................... 132 14.1RTC Examples ....................................................................................................132 14.2Audio Examples ...................................................................................................134 15 Typical Performance Characteristics ................................................. 139 15.1PMU: Power Supply Sequences .........................................................................139 15.2DCDC0 and DCDC1 ............................................................................................142 15.3LDO2 ...................................................................................................................146 15.4LDO3 ...................................................................................................................147 15.5AUDIO .................................................................................................................148 16 Package Information ............................................................................ 153 17 Ordering Information ........................................................................... 154 18 Revision History ................................................................................... 155 ii AT73C246 11050A–PMAAC–07-Apr-10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com www.atmel.com/PowerManage Technical Support pmaac@atmel.com Atmel Techincal Support Literature Requests www.atmel.com/literature Sales Contacts www.atmel.com/contacts/ Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 11050A–PMAAC–07-Apr-10

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