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Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory (ATmega48PA/88PA/168PA/328P) – 256/512/512/1K Bytes EEPROM (ATmega48PA/88PA/168PA/328P) – 512/1K/1K/2K Bytes Internal SRAM (ATmega48PA/88PA/168PA/328P) – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Programming Lock for Software Security • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel 10-bit ADC in TQFP and QFN/MLF package Temperature Measurement – 6-channel 10-bit ADC in PDIP Package Temperature Measurement – Programmable Serial USART – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Serial Interface (Philips I2C compatible) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby • I/O and Packages – 23 Programmable I/O Lines – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF • Operating Voltage: – 1.8 - 5.5V for ATmega48PA/88PA/168PA/328P • Temperature Range: – -40°C to 85°C • Speed Grade: – 0 - 20 MHz @ 1.8 - 5.5V • Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48PA/88PA/168PA/328P: – Active Mode: 0.2 mA – Power-down Mode: 0.1 µA – Power-save Mode: 0.75 µA (Including 32 kHz RTC) 8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48PA ATmega88PA ATmega168PA ATmega328P Summary Rev. 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 1. Pin Configurations Figure 1-1. Pinout ATmega48PA/88PA/168PA/328P TQFP Top View PDIP 32 PD2 (INT0/PCINT18) 31 PD1 (TXD/PCINT17) 30 PD0 (RXD/PCINT16) 29 PC6 (RESET/PCINT14) 28 PC5 (ADC5/SCL/PCINT13) 27 PC4 (ADC4/SDA/PCINT12) 26 PC3 (ADC3/PCINT11) 25 PC2 (ADC2/PCINT10) (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 24 PC1 (ADC1/PCINT9) 23 PC0 (ADC0/PCINT8) 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 (SCK/PCINT5) (PCINT14/RESET) PC6 1 (PCINT16/RXD) PD0 2 (PCINT17/TXD) PD1 3 (PCINT18/INT0) PD2 4 (PCINT19/OC2B/INT1) PD3 5 (PCINT20/XCK/T0) PD4 6 VCC 7 GND 8 (PCINT6/XTAL1/TOSC1) PB6 9 (PCINT7/XTAL2/TOSC2) PB7 10 (PCINT21/OC0B/T1) PD5 11 (PCINT22/OC0A/AIN0) PD6 12 (PCINT23/AIN1) PD7 13 (PCINT0/CLKO/ICP1) PB0 14 28 PC5 (ADC5/SCL/PCINT13) 27 PC4 (ADC4/SDA/PCINT12) 26 PC3 (ADC3/PCINT11) 25 PC2 (ADC2/PCINT10) 24 PC1 (ADC1/PCINT9) 23 PC0 (ADC0/PCINT8) 22 GND 21 AREF 20 AVCC 19 PB5 (SCK/PCINT5) 18 PB4 (MISO/PCINT4) 17 PB3 (MOSI/OC2A/PCINT3) 16 PB2 (SS/OC1B/PCINT2) 15 PB1 (OC1A/PCINT1) (PCINT21/OC0B/T1) PD5 9 (PCINT22/OC0A/AIN0) PD6 10 (PCINT23/AIN1) PD7 11 (PCINT0/CLKO/ICP1) PB0 12 (PCINT1/OC1A) PB1 13 (PCINT2/SS/OC1B) PB2 14 (PCINT3/OC2A/MOSI) PB3 15 (PCINT4/MISO) PB4 16 28 MLF Top View 32 MLF Top View 32 PD2 (INT0/PCINT18) 31 PD1 (TXD/PCINT17) 30 PD0 (RXD/PCINT16) 29 PC6 (RESET/PCINT14) 28 PC5 (ADC5/SCL/PCINT13) 27 PC4 (ADC4/SDA/PCINT12) 26 PC3 (ADC3/PCINT11) 25 PC2 (ADC2/PCINT10) 28 PD2 (INT0/PCINT18) 27 PD1 (TXD/PCINT17) 26 PD0 (RXD/PCINT16) 25 PC6 (RESET/PCINT14) 24 PC5 (ADC5/SCL/PCINT13) 23 PC4 (ADC4/SDA/PCINT12) 22 PC3 (ADC3/PCINT11) (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. 21 PC2 (ADC2/PCINT10) 20 PC1 (ADC1/PCINT9) 19 PC0 (ADC0/PCINT8) 18 GND 17 AREF 16 AVCC 15 PB5 (SCK/PCINT5) (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 NOTE: Bottom pad should be soldered to ground. 24 PC1 (ADC1/PCINT9) 23 PC0 (ADC0/PCINT8) 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 (SCK/PCINT5) (PCINT21/OC0B/T1) PD5 9 (PCINT22/OC0A/AIN0) PD6 10 (PCINT23/AIN1) PD7 11 (PCINT0/CLKO/ICP1) PB0 12 (PCINT1/OC1A) PB1 13 (PCINT2/SS/OC1B) PB2 14 (PCINT3/OC2A/MOSI) PB3 15 (PCINT4/MISO) PB4 16 (PCINT22/OC0A/AIN0) PD6 8 (PCINT23/AIN1) PD7 9 (PCINT0/CLKO/ICP1) PB0 10 (PCINT1/OC1A) PB1 11 (PCINT2/SS/OC1B) PB2 12 (PCINT3/OC2A/MOSI) PB3 13 (PCINT4/MISO) PB4 14 2 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 76 and ”System Clock and Clock Options” on page 26. 1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 28-3 on page 308. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 79. 1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 3 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 1.1.7 1.1.8 1.1.9 The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 82. AVCC AREF AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. AREF is the analog reference pin for the A/D Converter. ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 4 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 2. Overview The ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48PA/88PA/168PA/328P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram GND VCC Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation EEPROM Power Supervision POR / BOD & RESET Flash debugWIRE PROGRAM LOGIC SRAM CPU 8bit T/C 0 8bit T/C 2 16bit T/C 1 Analog Comp. 2 A/D Conv. Internal 6 Bandgap AVCC AREF GND USART 0 SPI TWI DATABUS 8161DS–AVR–10/09 PORT D (8) PORT B (8) PORT C (7) PD[0..7] PB[0..7] PC[0..6] ADC[6..7] RESET XTAL[1..2] The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting 5 ATmega48PA/88PA/168PA/328P architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega48PA/88PA/168PA/328P provides the following features: 4/8/16/32K bytes of InSystem Programmable Flash with Read-While-Write capabilities, 256/512/512/1K bytes EEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega48PA/88PA/168PA/328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48PA/88PA/168PA/328P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison Between ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P The ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the three devices. Table 2-1. Memory Size Summary Device Flash EEPROM ATmega48PA 4K Bytes 256 Bytes ATmega88PA 8K Bytes 512 Bytes ATmega168PA 16K Bytes 512 Bytes ATmega328P 32K Bytes 1K Bytes RAM 512 Bytes 1K Bytes 1K Bytes 2K Bytes Interrupt Vector Size 1 instruction word/vector 1 instruction word/vector 2 instruction words/vector 2 instruction words/vector ATmega88PA, ATmega168PA and ATmega328P support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48PA, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. 6 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 7 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 5. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – UMSEL01 Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – UMSEL00 Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – UPM01 Bit 4 Bit 3 Bit 2 Bit 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – USART I/O Data Register USART Baud Rate Register High USART Baud Rate Register Low – – – – UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 Bit 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – UCPOL0 8161DS–AVR–10/09 Page 189 193 193 191/206 8 ATmega48PA/88PA/168PA/328P Address (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) Name UCSR0B UCSR0A Reserved Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A Bit 7 RXCIE0 RXC0 – – TWAM6 TWINT TWA6 TWS7 – – – FOC2A COM2A1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – FOC1A ICNC1 COM1A1 Bit 6 TXCIE0 TXC0 – – TWAM5 TWEA TWA5 TWS6 EXCLK – FOC2B COM2A0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – FOC1B ICES1 COM1A0 Bit 5 Bit 4 Bit 3 Bit 2 UDRIE0 RXEN0 TXEN0 UCSZ02 UDRE0 FE0 DOR0 UPE0 – – – – – – – – TWAM4 TWAM3 TWAM2 TWAM1 TWSTA TWSTO TWWC TWEN 2-wire Serial Interface Data Register TWA4 TWA3 TWA2 TWA1 TWS5 TWS4 TWS3 – 2-wire Serial Interface Bit Rate Register – – – – AS2 TCN2UB OCR2AUB OCR2BUB – – – – Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8-bit) – – WGM22 CS22 COM2B1 COM2B0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte – – – – – – – – – WGM13 WGM12 CS12 COM1B1 COM1B0 – – Bit 1 RXB80 U2X0 – – TWAM0 – TWA0 TWPS1 – TCR2AUB – CS21 WGM21 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – CS11 WGM11 Bit 0 TXB80 MPCM0 – – – TWIE TWGCE TWPS0 – TCR2BUB – CS20 WGM20 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – CS10 WGM10 8161DS–AVR–10/09 Page 190 189 239 236 238 239 238 236 158 156 156 156 155 152 132 132 132 132 133 133 132 132 131 130 128 9 ATmega48PA/88PA/168PA/328P Address (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) Name DIDR1 DIDR0 Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved Reserved ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 Bit 7 – – – REFS1 – ADEN – – – – – – – – – – PCINT23 – PCINT7 – – – – – PRTWI – – CLKPCE WDIF I – SP7 – – – – – SPMIE – – – – – – ACD – SPIF SPIE – FOC0A COM0A1 TSM – Bit 6 – – – REFS0 ACME ADSC – – – – – – – – – – PCINT22 PCINT14 PCINT6 – – – – – PRTIM2 – – – WDIE T – SP6 – – – – – (RWWSB)5. – BODS – – – – ACBG – WCOL SPE – FOC0B COM0A0 – – Bit 5 Bit 4 Bit 3 Bit 2 – – – – ADC5D ADC4D ADC3D ADC2D – – – – ADLAR – MUX3 MUX2 – – – ADTS2 ADATE ADIF ADIE ADPS2 ADC Data Register High byte ADC Data Register Low byte – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – OCIE2B ICIE1 – – OCIE1B – – – OCIE0B PCINT21 PCINT20 PCINT19 PCINT18 PCINT13 PCINT12 PCINT11 PCINT10 PCINT5 PCINT4 PCINT3 PCINT2 – – – – – – ISC11 ISC10 – – – PCIE2 – – – – Oscillator Calibration Register – – – – PRTIM0 – PRTIM1 PRSPI – – – – – – – – – – CLKPS3 CLKPS2 WDP3 WDCE WDE WDP2 H S V N – – – (SP10) 5. SP5 SP4 SP3 SP2 – – – – – – – – – – – – – – – – – – – – – (RWWSRE)5. BLBSET PGWRT – – – – BODSE PUD – – – – WDRF BORF – – SM2 SM1 – – – – – – – – ACO ACI ACIE ACIC – – – – SPI Data Register – – – – DORD MSTR CPOL CPHA General Purpose I/O Register 2 General Purpose I/O Register 1 – – – – Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8-bit) – – WGM02 CS02 COM0B1 COM0B0 – – – – – – (EEPROM Address Register High Byte) 5. EEPROM Address Register Low Byte EEPROM Data Register EEPM1 EEPM0 EERIE EEMPE General Purpose I/O Register 0 Bit 1 AIN1D ADC1D – MUX1 ADTS1 ADPS1 Bit 0 AIN0D ADC0D – MUX0 ADTS0 ADPS0 – – – – – – – OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 – ISC01 PCIE1 – – – – – – – – TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 – ISC00 PCIE0 – – PRUSART0 – – CLKPS1 WDP1 Z SP9 SP1 – – – – – PGERS – IVSEL EXTRF SM0 – – ACIS1 – – PRADC – – CLKPS0 WDP0 C SP8 SP0 – – – – – SELFPRGEN – IVCE PORF SE – – ACIS0 – – SPR1 SPI2X SPR0 – – CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC EEPE EERE Page 244 261 257 260 258 260 260 157 133 105 68 68 68 65 37 42 37 54 9 12 12 284 44/62/86 54 40 242 169 168 167 25 25 137/159 21 21 21 21 25 10 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1D (0x3D) EIMSK – – – – – – INT1 INT0 66 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 66 0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 157 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 134 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33) Reserved – – – – – – – – 0x12 (0x32) Reserved – – – – – – – – 0x11 (0x31) Reserved – – – – – – – – 0x10 (0x30) Reserved – – – – – – – – 0x0F (0x2F) Reserved – – – – – – – – 0x0E (0x2E) Reserved – – – – – – – – 0x0D (0x2D) Reserved – – – – – – – – 0x0C (0x2C) Reserved – – – – – – – – 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 87 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 87 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 87 0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 86 0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 86 0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 86 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 86 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 86 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 86 0x02 (0x22) Reserved – – – – – – – – 0x01 (0x21) Reserved – – – – – – – – 0x0 (0x20) Reserved – – – – – – – – Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for ATmega88PA. 11 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 6. Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed MULSU Rd, Rr Multiply Signed with Unsigned FMUL Rd, Rr Fractional Multiply Unsigned FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP JMP(1) k Indirect Jump to (Z) Direct Jump RCALL k Relative Subroutine Call ICALL CALL(1) k Indirect Call to (Z) Direct Subroutine Call RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared 8161DS–AVR–10/09 Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← k PC ← PC + k + 1 PC ← Z PC ← k PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 12 ATmega48PA/88PA/168PA/328P Mnemonics Operands BRIE k BRID k BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM LPM Rd, Z LPM Rd, Z+ SPM IN Rd, P OUT P, Rr PUSH Rr Description Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack 8161DS–AVR–10/09 Operation if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Flags None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 13 ATmega48PA/88PA/168PA/328P Mnemonics Operands POP Rd MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK Description Pop Register from Stack No Operation Sleep Watchdog Reset Break Operation Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Flags None None None None None #Clocks 2 1 1 1 N/A 14 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 7. Ordering Information 7.1 ATmega48PA Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range 20(3) 1.8 - 5.5 ATmega48PA-AU ATmega48PA-MMH(4) ATmega48PA-MU ATmega48PA-PU 32A 28M1 32M1-A 28P3 Industrial (-40°C to 85°C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See ”Speed Grades” on page 306. 4. NiPdAu Lead Finish. 32A 28M1 32M1-A 28P3 Package Type 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 15 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 7.2 ATmega88PA Speed (MHz) 20(3) Power Supply 1.8 - 5.5 Ordering Code(2) ATmega88PA-AU ATmega88PA-MMH(4) ATmega88PA-MU ATmega88PA-PU Package(1) 32A 28M1 32M1-A 28P3 Operational Range Industrial (-40°C to 85°C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See ”Speed Grades” on page 306. 4. NiPdAu Lead Finish. 32A 28M1 32M1-A 28P3 Package Type 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 16 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 7.3 ATmega168PA Speed (MHz)(3) 20 Power Supply 1.8 - 5.5 Ordering Code(2) ATmega168PA-AU ATmega168PA-MMH(4) ATmega168PA-MU ATmega168PA-PU Package(1) 32A 28M1 32M1-A 28P3 Operational Range Industrial (-40°C to 85°C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See ”Speed Grades” on page 312. 4. NiPdAu Lead Finish. 32A 28M1 32M1-A 28P3 Package Type 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 17 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 7.4 ATmega328P Speed (MHz) 20(3) Power Supply 1.8 - 5.5 Ordering Code(2) ATmega328P- AU ATmega328P- MU ATmega328P- PU Package(1) 32A 32M1-A 28P3 Operational Range Industrial (-40°C to 85°C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See Figure 28-1 on page 316. 32A 28P3 32M1-A Package Type 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 18 8161DS–AVR–10/09 8. Packaging Information 8.1 32A ATmega48PA/88PA/168PA/328P PIN 1 e PIN 1 IDENTIFIER B E1 E D1 D C 0˚~7˚ A1 A2 L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.05 A2 0.95 D 8.75 D1 6.90 E 8.75 E1 6.90 B 0.30 C 0.09 L 0.45 e NOM – – 1.00 9.00 7.00 9.00 7.00 – – – 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 10/5/2001 DRAWING NO. REV. 32A B 19 8161DS–AVR–10/09 8.2 28M1 ATmega48PA/88PA/168PA/328P D 1 2 Pin 1 ID 3 E C SIDE VIEW TOP VIEW K D2 A1 A y R 0.20 0.45 1 2 3 E2 b L 0.4 Ref (4x) e BOTTOM VIEW Note: The terminal #1 ID is a Laser-marked Feature. SYMBOL A A1 b C D D2 E E2 e L y K COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX 0.80 0.90 1.00 0.00 0.02 0.05 0.17 0.22 0.27 0.20 REF 3.95 4.00 4.05 2.35 2.40 2.45 3.95 4.00 4.05 2.35 2.40 2.45 0.45 0.35 0.40 0.45 0.00 – 0.08 0.20 – – NOTE Package Drawing Contact: packagedrawings@atmel.com TITLE 28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZBV 10/24/08 DRAWING NO. REV. 28M1 B 20 8161DS–AVR–10/09 8.3 32M1-A D D1 1 2 3 Pin 1 ID ATmega48PA/88PA/168PA/328P 0 E1 E SIDE VIEW P P TOP VIEW A2 K A D2 Pin #1 Notch (0.20 R) 1 2 3 E2 K b e L BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e L P 0 K MIN 0.80 – – 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.30 – – 0.20 NOM 0.90 0.02 0.65 0.20 REF 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.40 – – – MAX 1.00 0.05 1.00 0.30 5.10 4.80 3.25 5.10 4.80 3.25 0.50 0.60 12o – NOTE TITLE 2325 Orchard Parkway 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, R San Jose, CA 95131 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) 5/25/06 DRAWING NO. REV. 32M1-A E 21 8161DS–AVR–10/09 8.4 28P3 ATmega48PA/88PA/168PA/328P D PIN 1 E1 A SEATING PLANE L e A1 B2 B1 B (4 PLACES) E C 0º ~ 15º REF eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.508 D 34.544 E 7.620 E1 7.112 B 0.381 B1 1.143 B2 0.762 L 3.175 C 0.203 eB – e NOM MAX NOTE – 4.5724 – – – 34.798 Note 1 – 8.255 – 7.493 Note 1 – 0.533 – 1.397 – 1.143 – 3.429 – 0.356 – 10.160 2.540 TYP TITLE 2325 Orchard Parkway 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual R San Jose, CA 95131 Inline Package (PDIP) 09/28/01 DRAWING NO. REV. 28P3 B 22 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 9. Errata 9.1 Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA device. 9.1.1 Rev. D No known errata. 9.2 Errata ATmega88PA The revision letter in this section refers to the revision of the ATmega88PA device. 9.2.1 Rev. F No known errata. 9.3 Errata ATmega168PA The revision letter in this section refers to the revision of the ATmega168PA device. 9.3.1 Rev E No known errata. 9.4 Errata ATmega328P The revision letter in this section refers to the revision of the ATmega328P device. 9.4.1 Rev D No known errata. 9.4.2 Rev C Not sampled. 9.4.3 Rev B • Unstable 32 kHz Oscillator 1. Unstable 32 kHz Oscillator The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asynchronous timer is inaccurate. Problem Fix/ Workaround None 9.4.4 Rev A • Unstable 32 kHz Oscillator 1. Unstable 32 kHz Oscillator The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asynchronous timer is inaccurate. Problem Fix/ Workaround None 23 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 10. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Rev. 8161D – 10/09 1. Inserted Table 8-8 on page 32, Capacitance for Low-frequency Crystal Oscillator. 10.2 Rev. 8161C – 05/09 1. Updated ”Features” on page 1 for ATmega48PA/88PA/168PA/328P. 2. Updated ”Overview” on page 5 included the Table 2-1 on page 6. 3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted Figure 7-1 on page 17. 4. Updated ”Register Description” on page 44. 5. Updated ”System Control and Reset” on page 46. 6. Updated ”Interrupts” on page 57. 7. Updated ”External Interrupts” on page 70. 8. Updated ”Boot Loader Support – Read-While-Write Self-Programming, ATmega88PA, ATmega168PA and ATmega328P” on page 277. 9. Inserted ”ATmega168PA DC Characteristics” on page 315. 10. Inserted ”ATmega328P DC Characteristics” on page 316. 11. Inserted ”ATmega168PA Typical Characteristics” on page 375. 12. Inserted ”ATmega328P Typical Characteristics” on page 399. 13. Inserted Ordering Information for ”ATmega168PA” on page 432. 14. Inserted Ordering Information for ”ATmega328P” on page 433. 15. Inserted ”Errata ATmega328P” on page 438. 16. Editing updates. 10.3 Rev. 8161B – 01/09 1. Updated ”Features” on page 1 for ATmega48PA and updated the book accordingly. 2. Updated ”Overview” on page 5 included the Table 2-1 on page 6. 3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted Figure 7-1 on page 17. 4. Updated ”Register Description” on page 44. 5. Updated ”System Control and Reset” on page 46. 6. Updated ”Interrupts” on page 57. 24 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 7. Updated ”External Interrupts” on page 70. 8. Inserted Typical characteristics for ”ATmega48PA Typical Characteristics” on page 327. 9. Updated figure names in Typical characteristics for ”ATmega88PA Typical Character- istics” on page 351. 10. Inserted ”ATmega48PA DC Characteristics” on page 314. 11. Updated Table 28-1 on page 317 by removing the footnote from Vcc/User calibration 12. Updated Table 28-7 on page 323 by removing Max value (2.5 LSB) from Absolute accuracy, VREF = 4V, VCC = 4V, ADC clock = 200 kHz. 13. Inserted Ordering Information for ”ATmega48PA” on page 430. 10.4 Rev. 8161A – 11/08 1. Initial revision (Based on the ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08). 2. Changes done compared to ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08: – Updated ”DC Characteristics” on page 313 with new typical values for ICC. – Updated ”Speed Grades” on page 316. – New graphics in ”Typical Characteristics” on page 326. – New ”Ordering Information” on page 430. 25 8161DS–AVR–10/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8161DS–AVR–10/09

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