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    标    签:时序分析约束

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    altera 的时序分析流程,让你一步一步知道时序约束

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    Quartus® II Software Design Series: Timing Analysis © 2009 Altera Corporation 1 Objectives n Build SDC files for constraining PLD designs n Verify timing on simple & complex designs using TimeQuest TA © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 Timing Analysis Agenda n TimeQuest basics n Timing constraints n Example © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 TimeQuest GUI Report Pane Menu access to all TimeQuest features View Pane Tasks Pane Console Pane © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5 SDC File Editor = Quartus II Text Editor n Use Quartus II editor to create and/or edit SDC n SDC editing unique features (for .sdc files) - Access to GUI dialog boxes for constraint entry (Edit Þ Insert Constraint) - Syntax coloring - Tooltip syntax help TimeQuest File menu Þ New/Open SDC File Quartus II File menu Þ New Þ Other Files Place cursor over command to see tooltip © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 6 SDC File Editor (cont.) Construct an SDC file using TimeQuest graphical constraint creation tools Constraints inserted at cursor location © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7 Basic Steps to Using TimeQuest TA 1. Generate timing netlist 2. Enter SDC constraints a. Create and/or read in SDC file (recommended method) or b. Constrain design directly in console 3. Update timing netlist 4. Generate timing reports 5. Save timing constraints (optional) © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8 Using TimeQuest TA in Quartus II Flow Synthesize Quartus II project Use TimeQuest TA to specify timing requirements Enable TimeQuest TA in Quartus II project Perform full compilation (run Fitter) Verify timing in TimeQuest TA © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9 Timing Analysis Agenda n TimeQuest basics n Timing constraints n Example © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10 Importance of Constraining n Timing analysis tells how a circuit WILL behave n Providing timing constraints tells tools how you WANT the design to behave - Constraints paint picture of how design should operate l Based on design specs & specs from other devices on PCB - Provide goals for fitter to target during compilation - Provide values to which to compare timing results n TimeQuest TA performs limited analysis without timing constraints © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11 Timing Requirements: Enter Constraints n All constraints discussed can be easily accessed in TimeQuest GUI - Constraints menu of TimeQuest - Edit Þ Insert Constraint menu of SDC File Editor © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12 SDC Netlist Terminology Term Cell Pin Net Port Definition Device building blocks (e.g. look-up tables, registers, embedded multipliers, memory blocks, I/O elements, PLLs, etc.) Input or outputs of cells Connections between pins Top-level inputs and outputs (e.g. device pins) © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13 SDC Netlist Example cell ina inb cell=atom/wysiwyg pin = iterm combout inrega datain clk inregb pin = oterm regout ab datac datad combout outreg port = I/O out datain inclk[0] clk clk~clkctrl outclk net Sample Pin Names: ina|combout inrega|datain inrega|clk inrega|regout ab|combout ab|datac Sample Net Names: ina~combout ab clk~clkctrl inrega n Paths defined in constraints by targeted endpoints (pins or ports) © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14 Collections n Searches and returns from the design netlist with a list of names meeting criteria n Used in SDC commands - Some collections searched automatically during a command’s usage and may not need to be specified n Examples - get_ports - get_pins - get_clocks - all_clocks - all_registers See “TimeQuest Timing Analyzer” chapter of the Quartus II Software Handbook (Volume 3) for a complete list & description of each - all_inputs - all_outputs © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15 SDC Timing Constraints n Clocks n I/O n False paths n Multicycle paths © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 16 What are clocks in SDC? n Defined, repeating signal characteristics applied to a point anywhere in the design - Internal: applied to a specific node being used as a clock in design (port or pin) - “Virtual”: No real source in, or direct interaction with design l Example: Clocks on external devices that feed or are fed by the FPGA design, required for I/O analysis n Name clocks after node to which they are applied or something more meaningful n Similar to clock settings in older Quartus II timing engine (Classic timing analyzer) © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 17 Clocks in SDC (cont.) n Two types - Clock l Absolute or base clock - Generated clock l Timing derived from another clock in design - Must have defined relation with source clock l Apply to output of logic function that modifies clock input - PLLs, clock dividers, output clocks, ripple clocks, etc. - Clock inversions automatically detected unless derived from more complex logic structure n All clocks are related by default - Cross-domain transfers analyzed © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 18 Clock Constraints n Create clock n Create generated clock n PLL clocks n Automatic clock detection & creation n Default constraints n Clock latency n Clock uncertainty n Common clock path pessimism removal © 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 19 Creating a Clock n Command: create_clock n Options [-name ] -period

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