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qca8334 datasheet

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NOTICE l Effective October 1, 2012, QUALCOMM Incorporated completed a corporate reorganization in which the assets of certain of its businesses and groups, as well as the stock of certain of its ia direct and indirect subsidiaries, were contributed to Qualcomm Technologies, Inc. (QTI), a whollyt owned subsidiary of QUALCOMM Incorporated that was created for purposes of the reorganization. en Qualcomm Technology Licensing (QTL), the Company’s patent licensing business, continues id to be operated by QUALCOMM Incorporated, which continues to own the vast majority of the Company’s patent portfolio. Substantially all of the Company’s products and services businesses, f including QCT, as well as substantially all of the Company’s engineering, research and n development functions, are now operated by QTI and its direct and indirect subsidiaries1. Neither QTI nor any of its subsidiaries has any right, power or authority to grant any licenses or other o rights under or to any patents owned by QUALCOMM Incorporated. C No use of this website and/or documentation, including but not limited to the downloading of any software, programs, manuals or other materials of any kind or nature whatsoever, and no s purchase or use of any products or services, grants any licenses or other rights, of any kind or o nature whatsoever, under or to any patents owned by QUALCOMM Incorporated or any of its r subsidiaries. A separate patent license or other similar patent-related agreement from QUALCOMM Incorporated is needed to make, have made, use, sell, import and dispose of any e products or services that would infringe any patent owned by QUALCOMM Incorporated in the h absence of the grant by QUALCOMM Incorporated of a patent license or other applicable rights At under such patent. m Any copyright notice referencing QUALCOMM Incorporated, Qualcomm Incorporated, QUALCOMM Inc., Qualcomm Inc., Qualcomm or similar designation, and which is associated with any of the products or services businesses or the engineering, research or development groups which are now operated by QTI and its direct and indirect subsidiaries, should properly reference, and shall be read to reference, QTI. Qualcom 1 The products and services businesses, and the engineering, research and development groups, which are now operated by QTI and its subsidiaries include, but are not limited to, QCT, Qualcomm Mobile & Computing (QMC), Qualcomm Atheros (QCA), Qualcomm Internet Services (QIS), Qualcomm Government Technologies (QGOV), Corporate Research & Development, Qualcomm Corporate Engineering Services (QCES), Office of the Chief Technology Officer (OCTO), Office of the Chief Scientist (OCS), Corporate Technical Advisory Group, Global Market Development (GMD), Global Business Operations (GBO), Qualcomm Ventures, Qualcomm Life (QLife), Quest, Qualcomm Labs (QLabs), Snaptracs/QCS, Firethorn, Qualcomm MEMS Technologies (QMT), Pixtronix, Qualcomm Innovation Center (QuIC), Qualcomm iSkoot, Qualcomm Poole and Xiam. ntial QCA8334 Four-port Gigabit Ethernet eSwitch idData Sheet f80-Y0619-1 Rev. A n October 15, 2012 Atheros Co Confidential and Proprietary – Qualcomm Atheros, Inc. m Restricted Distribution. Not to be distributed to anyone who is not an employee of either Qualcomm or a subsidiary of Qualcomm without the express approval of Qualcomm’s Configuration Management. m Not to be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the express written permission of Qualcomm Atheros, Inc. o QUALCOMM is a registered trademark of QUALCOMM Incorporated. ATHEROS is a registered trademark of lc Qualcomm Atheros, Inc. All other registered and unregistered trademarks are the property of QUALCOMM Incorporated, Qualcomm Atheros, Inc., or their respective owners and used with permission. Registered marks owned by QUALCOMM Incorporated and Qualcomm Atheros, Inc. are registered in the United States of America and may abe registered in other countries. uThis technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion Qcontrary to U.S. and international law is strictly prohibited. Qualcomm Atheros, Inc. 1700 Technology Drive San Jose, CA 95110-1383 U.S.A. Copyright © 2012 Qualcomm Atheros, Inc. All rights reserved. Revision history l Revision Date Description ia 1.0 May 14, 2012 Initial release Atheros Confident A October 15, 2012 System change from SharePoint to Agile based on MKG-17791 Qualcomm 80-Y0619-1 Rev. A 2 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION Contents ntial 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 e 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 id 1.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 f 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 n 2.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 o 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 C 3.1 Basic switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 s 3.1.1 Lookup engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.2 Automatic address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 o 3.1.3 Automatic address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 r 3.1.4 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 e 3.1.5 ARL table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 h 3.1.6 Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 t 3.2 QoS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 A 3.2.1 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.2 Ingress rate limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.3 Egress rate limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 m 3.2.4 Head-of-line blocking (HOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.5 Egress queue remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 m 3.3 VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 Port-based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 o3.3.2 802.1q VLANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 lc 3.3.3 VLAN security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 Port isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 a 3.3.5 Leaky VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 u 3.3.6 VLAN translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.7 Egress mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Q 3.3.8 VLAN table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1 ACL rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.2 Action definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 80-Y0619-1 Rev. A 3 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 3.4.3 MAC pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.4 IPv4 pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.5 IPv6 pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 3.4.6 Window pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.7 Enhanced MAC pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 l 3.5 IGMP/MLD snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ia 3.5.1 IEEE 802.3 reserved group addresses filtering control . . . . . . . . . . . . . . . . . . . 52 t 3.5.2 802.1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.3 Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 n 3.5.4 MAC limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 e 3.6 Atheros header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 id 3.6.1 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.2 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 f 3.6.3 Header for read/write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 n 3.7 MIB/statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.8 LED control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 o 3.9 EEPROM programming format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 C 3.10 MDC/MDIO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.11 IEEE 802.3az and energy efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 s 3.11.1 IEEE 802.3az LPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 o 3.12 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 r Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 e 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 h 4.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 t 4.3 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 A 4.4 SerDes and SGMII characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 Power-on strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 m 4.6.1 RGMII DC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.6.2 Power-on-reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 m 4.7 AC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.7.1 XTLI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 o4.7.2 MII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 lc 4.7.3 RMII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.7.4 RGMII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a 4.7.5 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 u 4.7.6 MDIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Q 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Register address space (offset range: 0x0000–0x0E98) . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2 Global control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2.1 MASK_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2.2 PORT0_PAD_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 80-Y0619-1 Rev. A 4 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.2.3 PORT5_PAD_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2.4 PORT6_PAD_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 5.2.15 5.2.16 5.2.17 5.2.18 5.2.19 5.2.20 5.2.21 5.2.22 5.2.23 5.2.24 5.2.25 5.2.26 5.2.27 5.2.28 5.2.29 PWS_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 GLOBAL_INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 GLOBAL_INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 l GLOBAL_INT0_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ia GLOBAL_INT1_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 t MODULE_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 n INTERFACE_HIGH_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 e MDIO master control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 id BIST_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 BIST_RECOVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 f SERVICE_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 n LED_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 LED_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 o LED_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 C LED_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 GOL_MAC_ADDR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 s GOL_MAC_ADDR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 o MAX_FRAME_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 r PORT0_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PORT2_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 e PORT3_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 h PORT6_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 t HEADER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A PORT0_HEADER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.2.30 PORT2_HEADER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.2.31 PORT3_HEADER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 m 5.2.32 PORT6_HEADER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2.33 SGMII debug 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 m5.2.34 SGMII_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 o5.2.35 MAC_PWR_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3 EEE control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 lc 5.3.1 EEE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.2 EEE_LOC_VALUE_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 a 5.3.3 EEE_REM_VALUE_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 u 5.3.4 EEE_RES_VALUE_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Q 5.3.5 EEE_LOC_VALUE_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.6 EEE_REM_VALUE_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.7 EEE_RES_VALUE_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.4 Parser control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.4.1 NORMALIZE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.4.2 NORMALIZE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.3 NORMALIZE_LEN_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.4.4 FRAM_ACK_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.5 5.4.5 FRAM_ACK_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.4.6 WIN_RULE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 l 5.4.7 WIN_RULE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ia 5.4.8 WIN_RULE_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 t 5.4.9 WIN_RULE_CTRL6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.4.10 WIN_RULE_CTRL7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 n 5.4.11 WIN_RULE_CTRL9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 e 5.4.12 WIN_RULE_CTRL10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 id 5.4.13 WIN_RULE_CTRL13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.4.14 TRUNK_HASH_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 f ACL control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 n 5.5.1 ACL_FUNC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.5.2 ACL_FUNC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 o 5.5.3 ACL_FUNC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 C 5.5.4 ACL_FUNC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.5.5 ACL_FUNC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 s 5.5.6 ACL_FUNC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 o 5.5.7 VLAN_TRANS_TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 r 5.5.8 PORT0_VLAN_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.5.9 PORT0_VLAN_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 e 5.5.10 PORT2_VLAN_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 h 5.5.11 PORT2_VLAN_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 t 5.5.12 PORT3_VLAN_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A 5.5.13 PORT3_VLAN_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.5.14 PORT6_VLAN_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.5.15 PORT6_VLAN_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 m 5.5.16 IPV4_PRI_BASE_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.5.17 IPV4_PRI_BASE_ADDR_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 m 5.6 Lookup control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 o5.6.1 ATU_DATA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.6.2 ATU_DATA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 lc 5.6.3 ATU_DATA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.6.4 ATU_FUNC_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 a 5.6.5 VTU_FUNC_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 u 5.6.6 VTU_FUNC_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Q 5.6.7 ARL_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.6.8 GLOBAL_FW_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.6.9 GLOBAL_FW_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.6.10 GOL_LEARN_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.6.11 TOS_PRI_MAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.6.12 TOS_PRI_MAP_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.6.13 TOS_PRI_MAP_REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 5.6.24 5.6.25 5.6.26 5.6.27 5.6.28 5.6.29 5.6.30 5.6.31 5.6.32 5.6.33 5.6.34 5.6.35 5.6.36 5.6.37 5.6.38 TOS_PRI_MAP_REG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 TOS_PRI_MAP_REG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 TOS_PRI_MAP_REG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 l TOS_PRI_MAP_REG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ia TOS_PRI_MAP_REG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 t VLAN_PRI_MAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 LOOP_CHECK_RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 n PORT0_LOOKUP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 e PORT0_PRI_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 id PORT0_LEARN_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 PORT2_LOOKUP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 f PORT2_PRI_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 n PORT2_LEARN_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PORT3_LOOKUP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 o PORT3_PRI_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 C PORT3_LEARN_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 PORT6_LOOKUP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 s PORT6_PRI_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 o PORT6_LEARN_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 r GOL_TRUNK_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 GOL_TRUNK_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 e GOL_TRUNK_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 h ACL_FWD_SRC_FLTR_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 t ACL_FWD_SRC_FLTR_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 A ACL_FWD_SRC_FLTR_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.7 QM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 5.7.1 GLOBAL_FLOW_THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 m 5.7.2 QM_CTRL_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.7.3 WAN_QUEUE_MAP_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 m5.7.4 LAN_QUEUE_MAP_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 o5.7.5 PORT0_WRR_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.7.6 PORT2_WRR_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 lc 5.7.7 PORT3_WRR_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.7.8 PORT6_WRR_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 a 5.7.9 PORT0_EG_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 u 5.7.10 PORT0_EG_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Q 5.7.11 PORT0_EG_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.7.12 PORT0_EG_RATE_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.7.13 PORT0_EG_RATE_CTRL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.7.14 PORT0_EG_RATE_CTRL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.7.15 PORT0_EG_RATE_CTRL6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.7.16 PORT0_EG_RATE_CTRL7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.7.17 PORT2_EG_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.7.18 5.7.19 5.7.20 5.7.21 5.7.22 5.7.23 5.7.24 5.7.25 5.7.26 5.7.27 5.7.28 5.7.29 5.7.30 5.7.31 5.7.32 5.7.33 5.7.34 5.7.35 5.7.36 5.7.37 5.7.38 5.7.39 5.7.40 5.7.41 5.7.42 PORT2_EG_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 PORT2_EG_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 PORT2_EG_RATE_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 l PORT2_EG_RATE_CTRL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ia PORT2_EG_RATE_CTRL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 t PORT3_EG_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 PORT3_EG_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 n PORT3_EG_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 e PORT3_EG_RATE_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 id PORT3_EG_RATE_CTRL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 PORT3_EG_RATE_CTRL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 f PORT6_EG_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 n PORT6_EG_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PORT6_EG_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 o PORT6_EG_RATE_CTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 C PORT6_EG_RATE_CTRL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 PORT6_EG_RATE_CTRL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 s PORT6_EG_RATE_CTRL6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 o PORT6_EG_RATE_CTRL7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 r PORT0_HOL_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 PORT0_HOL_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 e PORT2_HOL_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 h PORT2_HOL_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 t PORT3_HOL_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 A PORT3_HOL_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 5.7.43 5.7.44 m 5.7.45 5.7.46 m5.7.47 o5.7.48 5.7.49 lc 5.7.50 5.7.51 a 5.7.52 u 5.7.53 Q 5.7.54 PORT6_HOL_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 PORT6_HOL_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 PORT0_FLOW_THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 PORT2_FLOW_THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 PORT3_FLOW_THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 PORT6_FLOW_THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ACL_POLICY_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ACL_COUNTER_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ACL_CNT_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ACL_RATE_CTRL0_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 ACL_RATE_CTRL1_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 ACL_RATE_CTRL0_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.7.55 ACL_RATE_CTRL1_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.7.56 ACL_RATE_CTRL0_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.7.57 ACL_RATE_CTRL1_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.7.58 ACL_RATE_CTRL0_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.7.59 ACL_RATE_CTRL1_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.7.60 ACL_RATE_CTRL0_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.7.61 5.7.62 5.7.63 5.7.64 5.7.65 5.7.66 5.7.67 5.7.68 5.7.69 5.7.70 5.7.71 5.7.72 5.7.73 5.7.74 5.7.75 5.7.76 5.7.77 5.7.78 5.7.79 5.7.80 5.7.81 5.7.82 5.7.83 5.7.84 5.7.85 ACL_RATE_CTRL1_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 ACL_RATE_CTRL0_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 ACL_RATE_CTRL1_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 l ACL_RATE_CTRL0_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 ia ACL_RATE_CTRL1_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 t ACL_RATE_CTRL0_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ACL_RATE_CTRL1_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 n ACL_RATE_CTRL0_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 e ACL_RATE_CTRL1_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 id ACL_RATE_CTRL0_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ACL_RATE_CTRL1_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 f ACL_RATE_CTRL0_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 n ACL_RATE_CTRL1_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ACL_RATE_CTRL0_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 o ACL_RATE_CTRL1_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 C ACL_RATE_CTRL0_12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ACL_RATE_CTRL1_12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 s ACL_RATE_CTRL0_13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 o ACL_RATE_CTRL1_13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 r ACL_RATE_CTRL0_14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ACL_RATE_CTRL1_14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 e ACL_RATE_CTRL0_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 h ACL_RATE_CTRL1_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 t ACL_RATE_CTRL0_16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 A ACL_RATE_CTRL1_16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 5.7.86 5.7.87 m 5.7.88 5.7.89 m5.7.90 o5.7.91 5.7.92 lc 5.7.93 5.7.94 a 5.7.95 u 5.7.96 Q 5.7.97 ACL_RATE_CTRL0_17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ACL_RATE_CTRL1_17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ACL_RATE_CTRL0_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 ACL_RATE_CTRL1_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 ACL_RATE_CTRL0_19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 ACL_RATE_CTRL1_19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 ACL_RATE_CTRL0_20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 ACL_RATE_CTRL1_20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 ACL_RATE_CTRL0_21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ACL_RATE_CTRL1_21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ACL_RATE_CTRL0_22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 ACL_RATE_CTRL1_22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.7.98 ACL_RATE_CTRL0_23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.7.99 ACL_RATE_CTRL1_23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.7.100 ACL_RATE_CTRL0_24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.7.101 ACL_RATE_CTRL1_24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.7.102 ACL_RATE_CTRL0_25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.7.103 ACL_RATE_CTRL1_25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.7.104 5.7.105 5.7.106 5.7.107 5.7.108 5.7.109 5.7.110 5.7.111 5.7.112 5.7.113 5.7.114 5.7.115 5.7.116 5.7.117 5.7.118 5.7.119 5.7.120 5.7.121 5.7.122 5.7.123 5.7.124 5.7.125 5.7.126 5.7.127 5.7.128 ACL_RATE_CTRL0_26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 ACL_RATE_CTRL1_26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 ACL_RATE_CTRL0_27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 l ACL_RATE_CTRL1_27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 ia ACL_RATE_CTRL0_28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 t ACL_RATE_CTRL1_28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 ACL_RATE_CTRL0_29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 n ACL_RATE_CTRL1_29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 e ACL_RATE_CTRL0_30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 id ACL_RATE_CTRL1_30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 ACL_RATE_CTRL0_31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 f ACL_RATE_CTRL1_31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 n PORT0_ING_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 PORT0_ING_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 o PORT0_ING_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 C PORT2_ING_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 PORT2_ING_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 s PORT2_ING_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 o PORT3_ING_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 r PORT3_ING_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 PORT3_ING_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 e PORT6_ING_RATE_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 h PORT6_ING_RATE_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 t PORT6_ING_RATE_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 A CPU_GROUP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.8 PKT edit control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.8.1 PKT_EDIT_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 m 5.8.2 PORT0_QUEUE_REMAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.8.3 PORT0_QUEUE_REMAP_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 m5.8.4 PORT2_QUEUE_REMAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 o5.8.5 PORT3_QUEUE_REMAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.8.6 PORT6_QUEUE_REMAP_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 lc 5.8.7 PORT6_QUEUE_REMAP_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 5.8.8 Router default VID register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 a 5.8.9 Router default VID register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 u 5.8.10 Router default VID register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Q 5.8.11 Router egress VLAN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 5.9 PHY control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 5.9.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 5.9.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 5.9.3 PHY identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.9.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.9.5 Auto-negotiation advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.9.6 Link partner ability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 5.10 5.9.7 Auto-negotiation expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 5.9.8 Next page transmit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 l 5.9.9 Link partner next page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 ia 5.9.10 1000BASE-T control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 t 5.9.11 1000BASE-T status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 5.9.12 MMD access control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 n 5.9.13 MMD access address data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 e 5.9.14 Extended status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 id 5.9.15 Function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 5.9.16 PHY-specific status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 f 5.9.17 Interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 n 5.9.18 Interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 5.9.19 Smart speed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 o 5.9.20 Receive error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 C 5.9.21 Virtual cable tester control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 5.9.22 Debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 s 5.9.23 Debug port 2 (R/W port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 o Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 r 5.10.1 Analog test control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 5.10.2 System mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 e 5.10.3 System control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 h 5.10.4 HIB control and auto-negotiation test register . . . . . . . . . . . . . . . . . . . . . . . . 271 t 5.10.5 RGMII mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 A 5.10.6 Green feature configure register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 5.11 MMD3 — PCS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 5.11.1 PCS control1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 m 5.11.2 PCS status1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 5.11.3 EEE capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 m5.11.4 EEE wake error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 o5.11.5 AZ control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 5.11.6 AZ debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 lc 5.11.7 PHY cable diagnostics code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 5.11.8 PHY cable diagnostics pair A length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 a 5.11.9 PHY cable diagnostics pair B length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 u 5.11.10 PHY cable diagnostics pair C length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Q 5.11.11 PHY cable diagnostics pair D length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 5.11.12 CLD16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 5.12 MMD7 — auto-negotiation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 5.12.1 AN control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 5.12.2 AN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents 5.12.3 AN status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 5.12.4 AN XNP transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 5.12.5 AN XNP transmit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 6 7 8 5.12.6 5.12.7 l 5.12.8 ia 5.12.9 t 5.12.10 5.12.11 n 5.12.12 AN XNP transmit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 AN LP XNP ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 AN LP XNP ability1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 AN LP XNP ability2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 EEE advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 EEE LP advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 EEE ability auto-negotiation result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 e Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 fid Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Atheros Con Top-Side Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Qualcomm 80-Y0619-1 Rev. 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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Figures Figure 1-1 QCA8334 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 2-1 QCA8334 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 3-1 Read/write register command frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 l Figure 3-2 EEPROM programming format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ia Figure 3-3 MDC/MDIO access format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 t Figure 3-4 Operating power modes—802.3az LIP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 4-1 Power-on-reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 n Figure 4-2 XTLI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 e Figure 4-3 MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 id Figure 4-4 RMII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 4-5 RGMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 f Figure 4-6 EEPROM interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 n Figure 4-7 MDIO timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 6-1 88-pin QFN package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Atheros Co Figure 8-1 QCA8334 top-side marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Qualcomm 80-Y0619-1 Rev. A 13 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Tables Table 2-1 Signal to pin descriptions (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3-1 ARL table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 3-2 Reserved ATU entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 l Table 3-3 Egress queue remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ia Table 3-4 Ingress VLAN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 t Table 3-5 802.q mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3-6 VLAN translation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 n Table 3-7 VLAN egress mode — tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 e Table 3-8 VLAN egress mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 id Table 3-9 VLAN table format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 3-10 ACL patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 f Table 3-11 Action definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 n Table 3-12 MAC pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 3-13 MAC pattern mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 o Table 3-14 IPv4 pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 C Table 3-15 IPv4 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 3-16 IPv6 pattern 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 s Table 3-17 IPv6 pattern 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 o Table 3-18 IPv6 pattern 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 r Table 3-19 IPv6 mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 3-20 IPv6 mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 e Table 3-21 IPv6 mask 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 h Table 3-22 Window pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 t Table 3-23 Window pattern mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 A Table 3-24 Enhanced MAC pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 3-25 Enhanced MAC pattern mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 3-26 Type definition for Atheros header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 m Table 3-27 Atheros header transmit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 3-28 Atheros header receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 m Table 3-29 Command format for read/write register using Atheros header . . . . . . . . . . . . . . . . 55 o Table 3-30 MIB counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 3-31 LED control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 lcTable 3-32 LED rule default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 3-33 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 aTable 4-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 u Table 4-2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Q Table 4-3 Total system power (1000BASE-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 4-4 Driver DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 4-5 Receiver DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 4-6 Driver AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 4-7 Power-on-strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 80-Y0619-1 Rev. A 14 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 4-8 2.5V digital I/O DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 4-9 RGMII DC characteristics under 1.8V/1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 4-10 External clock input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 4-11 Recommended crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 4-12 MII timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 l Table 4-13 RMII timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ia Table 4-14 RGMII timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 t Table 4-15 EEPROM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 4-16 MDIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 n Table 5-1 Register address space summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 e Table 5-2 Global control registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 id Table 5-3 MASK_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 5-4 PORT0_PAD_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 f Table 5-5 PORT5_PAD_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 n Table 5-6 PORT6_PAD_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5-7 PWS_REG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 o Table 5-8 GLOBAL_INT0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 C Table 5-9 GLOBAL_INT1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 5-10 GLOBAL_INT0_MASK bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 s Table 5-11 GLOBAL_INT1_MASK bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 o Table 5-12 MODULE_EN bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 r Table 5-13 MIB bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 5-14 INTERFACE_HIGH_ADDR bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 e Table 5-15 MDIO master control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 h Table 5-16 BIST_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 t Table 5-17 BIST_RECOVER bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 A Table 5-18 SERVICE_TAG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 5-19 LED_CTRL 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 5-20 LED_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 m Table 5-21 LED_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 5-22 LED_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 m Table 5-23 GOL_MAC_ADDR0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 o Table 5-24 GLOL_MAC_ADDR1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 5-25 MAX_FRAME__SIZE bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 lcTable 5-26 PORT0_STATUS bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 5-27 PORT2_STATUS bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 aTable 5-28 PORT 3_STATUS bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 u Table 5-29 PORT 6_STATUS bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Q Table 5-30 HEADER_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 5-31 PORT0_HEADER_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 5-32 PORT 2_HEADER_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 5-33 PORT3_HEADER_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 5-34 PORT6_HEADER_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 80-Y0619-1 Rev. A 15 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-35 SGMII debug 1 register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 5-36 SGMII_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 5-37 MAC_PWR_SEL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 5-38 EEE control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 5-39 EEE_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 l Table 5-40 EEE_LOC_VALUE_2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ia Table 5-41 EEE_REM_VALUE_2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 t Table 5-42 EEE_RES_VALUE_2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 5-43 EEE_LOC_VALUE_3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 n Table 5-44 EEE_REM_VALUE_3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 e Table 5-45 EEE_RES_VALUE_3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 id Table 5-46 Parser register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 5-47 NORMALIZE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 f Table 5-48 NORMALIZE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 n Table 5-49 NORMALIZE_LEN_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 5-50 FRAM_ACK_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 o Table 5-51 FRAM_ACK_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 C Table 5-52 WIN_RULE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 5-53 WIN_RULE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 s Table 5-54 WIN_RULE_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 o Table 5-55 WIN_RULE_CTRL6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 r Table 5-56 WIN_RULE_CTRL7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 5-57 WIN_RULE_CTRL9 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 e Table 5-58 WIN_RULE_CTRL10 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 h Table 5-59 WIN_RULE_CTRL13 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 t Table 5-60 TRUNK_HASH_EN bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 A Table 5-61 ACL register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 5-62 ACL_FUNC0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 5-63 ACL_FUNC1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 m Table 5-64 ACL_FUNC2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 5-65 ACL_FUNC3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 m Table 5-66 ACL_FUNC4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 o Table 5-67 ACL_FUNC5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 5-68 VLAN_TRANS_TEST bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 lcTable 5-69 PORT0_VLAN_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 5-70 PORT0_VLAN_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 aTable 5-71 PORT2_VLAN_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 u Table 5-72 PORT2_VLAN_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Q Table 5-73 PORT3_VLAN_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 5-74 PORT3_VLAN_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 5-75 PORT6_VLAN_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 5-76 PORT6_VLAN_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 5-77 IPV4_PRI_BASE_ADDR bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 80-Y0619-1 Rev. A 16 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-78 IPV4_PRI_BASE_ADDR_MASK bit description . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 5-79 Lookup register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 5-80 ATU_DATA0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 5-81 ATU_DATA1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 5-82 TU_DATA2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 l Table 5-83 ATU_FUNC_REG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ia Table 5-84 VTU_FUNC_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 t Table 5-85 VTU_FUNC_REG1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 5-86 ARL_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 n Table 5-87 GLOBAL_FW_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 e Table 5-88 GLOBAL_FW_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 id Table 5-89 GLOBAL_FW_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 5-90 TOS_PRI_MAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 f Table 5-91 TOS_PRI_MAP_REG1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 n Table 5-92 TOS_PRI_MAP_REG2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 5-93 TOS_PRI_MAP_REG3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 o Table 5-94 TOS_PRI_MAP_REG4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 C Table 5-95 TOS_PRI_MAP_REG5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 5-96 TOS_PRI_MAP_REG6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 s Table 5-97 TOS_PRI_MAP_REG7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 o Table 5-98 VLAN_PRI_MAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 r Table 5-99 LOOP_CHECK_RESULT bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 5-100 PORT0_LOOKUP_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 e Table 5-101 PORT0_PRI_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 h Table 5-102 PORT0_LEARN_LIMIT bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 t Table 5-103 PORT2_LOOKUP_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 A Table 5-104 PORT2_PRI_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 5-105 PORT2_LEARN_LIMIT bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 5-106 PORT3_LOOKUP_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 m Table 5-107 PORT3_PRI_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 5-108 PORT3_LEARN_LIMIT bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 m Table 5-109 PORT6_LOOKUP_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 o Table 5-110 PORT6_PRI_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 5-111 PORT6_LEARN_LIMIT bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 lcTable 5-112 GOL_TRUNK_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 5-113 GOL_TRUNK_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 aTable 5-114 GOL_TRUNK_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 u Table 5-115 ACL_FWD_SRC_FLTR_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 153 Q Table 5-116 ACL_FWD_SRC_FLTR_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 5-117 ACL_FWD_SRC_FLTR_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 5-118 QM register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 5-119 GLOBAL_FLOW_THD bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 5-120 QM_CTRL_REG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 80-Y0619-1 Rev. A 17 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-121 WAN_QUEUE_MAP_REG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 5-122 LAN_QUEUE_MAP_REG bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 5-123 PORT0_WRR_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 5-124 PORT2_WRR_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 5-125 PORT3_WRR_CTR bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 l Table 5-126 PORT6_WRR_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ia Table 5-127 PORT0_EG_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 t Table 5-128 PORT0_EG_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 5-129 PORT0_EG_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 n Table 5-130 PORT0_EG_RATE_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 e Table 5-131 PORT0_EG_RATE_CTRL4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 id Table 5-132 PORT0_EG_RATE_CTRL5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 5-133 PORT0_EG_RATE_CTRL6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 f Table 5-134 PORT0_EG_RATE_CTRL7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 n Table 5-135 PORT2_EG_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 5-136 PORT2_EG_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 o Table 5-137 PORT2_EG_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 C Table 5-138 PORT2_EG_RATE_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 5-139 PORT2_EG_RATE_CTRL4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 s Table 5-140 PORT2_EG_RATE_CTRL5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 o Table 5-141 PORT3_EG_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 r Table 5-142 PORT3_EG_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 5-143 PORT3_EG_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 e Table 5-144 PORT3_EG_RATE_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 h Table 5-145 PORT3_EG_RATE_CTRL4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 t Table 5-146 PORT3_EG_RATE_CTRL5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 A Table 5-147 PORT6_EG_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 5-148 PORT6_EG_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 5-149 PORT6_EG_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 m Table 5-150 PORT6_EG_RATE_CTRL3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 5-151 PORT6_EG_RATE_CTRL4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 m Table 5-152 PORT6_EG_RATE_CTRL5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 o Table 5-153 PORT6_EG_RATE_CTRL6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 5-154 PORT6_EG_RATE_CTRL7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 lcTable 5-155 PORT0_HOL_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 5-156 PORT0_HOL_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 aTable 5-157 PORT2_HOL_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 u Table 5-158 PORT2_HOL_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Q Table 5-159 PORT3_HOL_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 5-160 PORT3_HOL_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 5-161 PORT6_HOL_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 5-162 PORT6_HOL_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 5-163 PORT0_FLOW_THD bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 80-Y0619-1 Rev. A 18 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-164 PORT2_FLOW_THD bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 5-165 PORT3_FLOW_THD bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 5-166 PORT6_FLOW_THD bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 5-167 ACL_POLICY_MODE bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 5-168 ACL_COUNTER_MODE bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 l Table 5-169 ACL_CNT_RESET bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ia Table 5-170 ACL_RATE_CTRL0_0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 t Table 5-171 ACL_RATE_CTRL1_0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 5-172 ACL_RATE_CTRL0_1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 n Table 5-173 ACL_RATE_CTRL1_1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 e Table 5-174 ACL_RATE_CTRL0_2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 id Table 5-175 ACL_RATE_CTRL1_2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 5-176 ACL_RATE_CTRL0_3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 f Table 5-177 ACL_RATE_CTRL1_3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 n Table 5-178 ACL_RATE_CTRL0_4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 5-179 ACL_RATE_CTRL1_4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 o Table 5-180 ACL_RATE_CTRL0_5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 C Table 5-181 ACL_RATE_CTRL1_5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 5-182 ACL_RATE_CTRL0_6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 s Table 5-183 ACL_RATE_CTRL1_6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 o Table 5-184 ACL_RATE_CTRL0_7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 r Table 5-185 ACL_RATE_CTRL1_7 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 5-186 ACL_RATE_CTRL0_8 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 e Table 5-187 ACL_RATE_CTRL1_8 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 h Table 5-188 ACL_RATE_CTRL0_9 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 t Table 5-189 ACL_RATE_CTRL1_9 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 A Table 5-190 ACL_RATE_CTRL0_10 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 5-191 ACL_RATE_CTRL1_10 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 5-192 ACL_RATE_CTRL0_11 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 m Table 5-193 ACL_RATE_CTRL1_11 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 5-194 ACL_RATE_CTRL0_12 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 m Table 5-195 ACL_RATE_CTRL1_12 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 o Table 5-196 ACL_RATE_CTRL0_13 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 5-197 ACL_RATE_CTRL1_13 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 lcTable 5-198 ACL_RATE_CTRL0_14 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 5-199 ACL_RATE_CTRL1_14 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 aTable 5-200 ACL_RATE_CTRL0_15 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 u Table 5-201 ACL_RATE_CTRL1_15 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Q Table 5-202 ACL_RATE_CTRL0_16 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 5-203 ACL_RATE_CTRL1_16 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 5-204 ACL_RATE_CTRL1_17 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 5-205 ACL_RATE_CTRL1_17 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 5-206 ACL_RATE_CTRL0_18 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 80-Y0619-1 Rev. A 19 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-207 ACL_RATE_CTRL1_18 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 5-208 ACL_RATE_CTRL0_19 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 5-209 ACL_RATE_CTRL1_19 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 5-210 ACL_RATE_CTRL0_20 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 5-211 ACL_RATE_CTRL1_20 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 l Table 5-212 ACL_RATE_CTRL0_21 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ia Table 5-213 ACL_RATE_CTRL1_21 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 t Table 5-214 ACL_RATE_CTRL0_22 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 5-215 ACL_RATE_CTRL1_22 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 n Table 5-216 ACL_RATE_CTRL0_23 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 e Table 5-217 ACL_RATE_CTRL1_23 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 id Table 5-218 ACL_RATE_CTRL0_24 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 5-219 ACL_RATE_CTRL1_24 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 f Table 5-220 ACL_RATE_CTRL0_25 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 n Table 5-221 ACL_RATE_CTRL1_25 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 5-222 ACL_RATE_CTRL0_26 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 o Table 5-223 ACL_RATE_CTRL1_26 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 C Table 5-224 ACL_RATE_CTRL0_27 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 5-225 ACL_RATE_CTRL1_27 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 s Table 5-226 ACL_RATE_CTRL0_28 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 o Table 5-227 ACL_RATE_CTRL1_28 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 r Table 5-228 ACL_RATE_CTRL0_29 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 5-229 ACL_RATE_CTRL1_29 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 e Table 5-230 ACL_RATE_CTRL0_30 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 h Table 5-231 ACL_RATE_CTRL1_30 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 t Table 5-232 ACL_RATE_CTRL0_31 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 A Table 5-233 ACL_RATE_CTRL1_31 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 5-234 PORT0_ING_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 5-235 PORT0_ING_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 m Table 5-236 PORT0_ING_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 5-237 PORT2_ING_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 m Table 5-238 PORT2_ING_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 o Table 5-239 PORT2_ING_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 5-240 PORT3_ING_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 lcTable 5-241 PORT3_ING_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 5-242 PORT3_ING_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 aTable 5-243 PORT6_ING_RATE_CTRL0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 u Table 5-244 PORT6_ING_RATE_CTRL1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Q Table 5-245 PORT6_ING_RATE_CTRL2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 5-246 CPU_GROUP_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 5-247 Packet editor register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 5-248 PKT_EDIT_CTRL bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 5-249 PORT0_QUEUE_REMAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . 237 80-Y0619-1 Rev. A 20 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-250 PORT0_QUEUE_REMAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 5-251 PORT2_QUEUE_REMAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 5-252 PORT3_QUEUE_REMAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 5-253 PORT6_QUEUE_REMAP_REG0 bit description . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 5-254 PORT6_QUEUE_REMAP_REG1 bit description . . . . . . . . . . . . . . . . . . . . . . . . 240 l Table 5-255 Router default VID register 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ia Table 5-256 Router default VID register 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 t Table 5-257 Router default VID register 3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 5-258 Router egress VLAN mode bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 n Table 5-259 PHY control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 e Table 5-260 PHY control register summary — MMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 id Table 5-261 PHY control register summary — MMD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 5-262 Control register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 f Table 5-263 Status registers bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 n Table 5-264 PHY Identifier bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 5-265 PHY Identifier 2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 o Table 5-266 Auto-negotiation advertisement register bit description . . . . . . . . . . . . . . . . . . . . 248 C Table 5-267 Link partner ability bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table 5-268 Auto-negotiation expansion bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 s Table 5-269 Next page transmit register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 o Table 5-270 link partner next page bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 r Table 5-271 1000BASE-T control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Table 5-272 1000BASE-T status bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 e Table 5-273 MMD access control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 h Table 5-274 MMD access address data register bit description . . . . . . . . . . . . . . . . . . . . . . . . 257 t Table 5-275 Extended status register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 A Table 5-276 Function control register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Table 5-277 PHY-specific status register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Table 5-278 Interrupt enable register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 m Table 5-279 Interrupt status register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Table 5-280 Smart speed register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 m Table 5-281 Status register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 o Table 5-282 Virtual cable tester control register bit description . . . . . . . . . . . . . . . . . . . . . . . . 266 Table 5-283 Debug port (address offset 0x1d, or 0d29) bit description . . . . . . . . . . . . . . . . . . 266 lcTable 5-284 Debug port 2 (R/W port) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Table 5-285 Analog test control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 aTable 5-286 System mode control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 u Table 5-287 System control mode bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Q Table 5-288 HIB control and auto-negotiation test register bit description . . . . . . . . . . . . . . . 271 Table 5-289 RGMII mode selection bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 5-290 Green feature configure register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Table 5-291 PCS control1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 5-292 PCS status1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 80-Y0619-1 Rev. A 21 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Contents Table 5-293 EEE capability register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Table 5-294 EEE wake error counter bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 5-295 AZ control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 5-296 AZ debug bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 5-297 PHY cable diagnostics bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 l Table 5-298 PHY cable diagnostics pair A length bit description . . . . . . . . . . . . . . . . . . . . . . 279 ia Table 5-299 PHY cable diagnostics pair B length bit description . . . . . . . . . . . . . . . . . . . . . . . 279 t Table 5-300 PHY cable diagnostics pair C length bit description . . . . . . . . . . . . . . . . . . . . . . . 279 Table 5-301 PHY cable diagnostics pair D length bit description . . . . . . . . . . . . . . . . . . . . . . 280 n Table 5-302 AZ control bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 e Table 5-303 AN control 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 id Table 5-304 AN package bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Table 5-305 AN status bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 f Table 5-306 AN XNP transmit bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 n Table 5-307 AN XNP transmit1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Table 5-308 AN XNP transmit2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 o Table 5-309 AN LP XNP ability bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 C Table 5-310 AN LP XNP ability1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 5-311 AN LP XNP ability2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 s Table 5-312 EEE advertisement bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 o Table 5-313 EEE LP advertisement bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 r Table 5-314 EEE ability auto-negotiation result bit description . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 6-1 Package dimensions (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 e Table 7-1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Ath Table 8-1 Top-side marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Qualcomm 80-Y0619-1 Rev. A 22 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 1 General Description tial The QCA8334 is a highly integrated four-port Gigabit Ethernet switch with non-blocking switch n fabric, a high-performance lookup unit with 2048 MAC addresses, and a four-traffic class Quality e of Service (QoS) engine. The QCA8334 switch has the flexibility to support various networking applications. The QCA8334 is designed for cost-sensitive switch applications in VoIP phone, id PLC/EOC bridge and IPTV platform. f The QCA8334 integrates all the functions of a high-speed switch system, including packet buffer, n PHY transceivers, media access controllers, address management, and a non-blocking switch fabric into a single 55 nm CMOS device. It complies with 10BASE-Te, and 1000BASE-T o specifications, including MAC control, pause frame, and auto-negotiation subsections, providing compatibility with all industry standard Ethernet, Fast Ethernet and Gigabit Ethernet. C The QCA8334 device contains two full-duplex 10BASE-Te/100BASE-Tx/1000BASE-T s transceivers and 10BASE-Te /100BASE-Tx can run at half-duplex, each of which performs all of the physical layer interface functions for 10BASE-Te Ethernet on category 5 unshielded twisted- o pair (UTP) cable and Fast/Gigabit Ethernet on category 5 UTP cable. r The remaining two ports feature a standard GMII/RGMII/MII/SerDes interface to allow e connection to host CPU in PON/xDSL/cable/Wi-Fi/fiber routers. The media access controllers on h the QCA8334 also support jumbo frames which are typically used for high-performance t connections to servers because they offer a smaller percentage of overhead on the link for more A efficiency. m SPI or EEPROM interfaces provide easy programming of the on-chip 802.1p QoS and/or DiffServ/TOS. This allows switch traffic to be given different classes of priority or service — for example, voice traffic for IP phone applications, video traffic for multimedia applications, or data traffic for email applications. m Up to 4K virtual LANs (VLANs) can be set up via the SPI port for separation of different users or groups on the network. ACL feature can reduce CPU effort for VLAN/QoS/DSCP/forward o mapping and remapping based on layer 1 to layer 4 information. PPPoE header add/removal can lcincrease video quality and offload CPU loading. Hardware IGMP V1/V2/V3 is an innovation for IPTV service. Green ETHOS® power saving technologies can increase energy efficiency for no alink or idle state. u The QCA8334 supports the following configuration: Q  2 *10/100/1000BASE-T + RGMII/MII/RMII + SerDes/SGMII 1.1 Features  Support 9 KB jumbo frame; 80-Y0619-1 Rev. A 23 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet General Description  Support internal/external loopback;  Support 100/1000 FX auto-sensing on SerDes port;  ACL mask rule from L1 to L4;  96 ACL mask rule for pass/drop, VLAN/QoS/DSCP mapping/translation; l  Flow-based bandwidth control and monitor; ia  User-defined ACL, up to 48 bytes depth in L4/L3/L2; t  QinQ function for S-VLAN & C-VLAN translation; n  Support VLAN translation and mapping with 64 translation entries; e  Port-based VLAN and 4 K IEEE802.1q VLAN group; id  Weighted Round Robin (WRR), Strict Priority (SP) queueing and combined WRR+SP; f  Independent VLAN learning (IVL) and Shared VLAN Learning (SVL); n  IGMP snooping V1/V2 /V3. IPv6 MLD V1/V2 forwarded to CPU; o  Support light hardware IGMP snooping V1/V2/V3, MLD V1/V2 and smart leave;  Port mirror, 802.1X security, Rapid Spanning Tree; C  2K MAC table, edit, search, add & delete; s  Hardware looping detection; o  IP packet/PPPoE bypass to reduce CPU loading on video packet; r  16 PPPoE session support/PPP session header removal/addition; e  41 MIBs counter/port and port status; h  1 Mbit packet buffer; At  Scalable ingress/egress bandwidth control; m  Rule-based bandwidth control;  Half power mode for cable length less than 30 m (for home installations);  Support reduced AFE circuit;  MAC limit by port/chip/VLAN; m  Trunking function; o  Support auto-failover; lc IEEE 802.3az power management support; a Power saving on cable no link, short cable and 10BASE-Te idle; u  Programmable Wake-on-LAN (WoL); Q  Built-in switching regulator for reduced BOM with single 3.3 V power only;  Support power-on cable diagnostic LED display; 80-Y0619-1 Rev. A 24 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet 1.2 System block diagram General Description Configuration MIB/statistics l registers counters LED controller MDC/MDIO QCA8334 ia Four-port Gigabit Ethernet Switch Engine nt QoS engine Buffer memory VLAN table Queue manager e Lookup engine MAC table memory Bandwidth control EEPROM LED MDC/MDIO fid Port 0 GMAC on RGMII/ MII/RMII Port 2 GMAC Port 3 GMAC 10/100/1000 BASE-T PHY 10/100/1000 BASE-T PHY Port 6 GMAC SerDes Atheros C Figure 1-1 QCA8334 block diagram Qualcomm 80-Y0619-1 Rev. A 25 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2 Pin Description tial This section includes package pinout and signal descriptions. en Nomenclatures for signal names id NC No signal connection from this pin _L Signal name suffix indicating active low signals f _p Signal name suffix indicating the positive side of a differential signal n _n Signal name suffix indicating the negative side of a differential signal o Nomenclatures for signal types C D Open drain for digital pads s IA Analog input signal o I Digital input signal r IH Input signals with weak internal pull-up to prevent signals from floating when left open e IL Input signals with weak internal pull-down to prevent signals from floating when left open h Digital bidirectional signal t I/O I/O pins include source end termination of 50 Ω impedance match and thus do not need external termination resistors. A Leave unused pins float OA m Analog output signal Digital output signal O Output pins include source end termination of 50 Ω impedance match and thus do not need external termination resistors. m Leave unused pins float o P Power or ground signal lcPD Internal weak pull-down QuaPU Internal weak pull-up 80-Y0619-1 Rev. A 26 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet 2.1 Pinout diagram Pin Description GND 1 XTLI 2 XTLO 3 AVDD 4 AVDD 5 VDD27_REG0 6 VREF 7 AVDD33 8 RBIAS 9 AVDDVCO_0 10 AVDD 11 CH1_TRXP0 12 CH1_TRXN0 13 AVDD 14 CH1_TRXP1 15 CH1_TRXN1 16 AVDD33 17 CH1_TRXP2 18 CH1_TRXN2 19 AVDD 20 CH1_TRXP3 21 CH1_TRXN3 22 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 EP66A89D 67 LED_LINK1000n_2 LED_LINK100n_2 LED_LINK10n_2 LED_LINK1000n_1 LED_LINK100n_1 LED_LINK10n_1 DVDD27 INTn DVDD SIP SIN AVDD SOP SON TEST_MODE DVDD POS_SWREG VDD15_REG1 GND LX VDD33_SWR GND EPAD QCA8334 QFN 88 Top View s Exposed Ground Pad on AtheroBottom ential 66 VDD27_REG1 65 DVDD id64 FILCAP_15D_0 63 TXD3_0 f62 TXD2_0 61 TXD1_0 n60 TXD0_0 59 GTXCLK_0/TXCLK_0 o 58 TXEN_0 57 RXD3_0 C 56 RXD2_0 55 VDD15_REG0 54 RXD1_0 53 RXD0_0 52 RXCLK_0 51 RXDV_0 50 DVDD 49 UART_RXD/MDC 48 UART_TXD/MDIO 47 SPI_CLK 46 SPI_CS 45 DVDD27 DVDD 23 CH2_TRXP0 24 CH2_TRXN0 25 AVDD 26 CH2_TRXP1 27 CH2_TRXN1 28 AVDD33 29 CH2_TRXP2 30 CH2_TRXN2 31 AVDD 32 CH2_TRXP3 33 CH2_TRXN3 34 AVDD 35 AVDD 36 AVDDVCO_1 37 FLCAP_27A_0 38 AVDD 39 AVDD 40 DVDD 41 RESETn 42 SPI_DI 43 SPI_DO 44 m Qualcom Figure 2-1 QCA8334 pinout diagram 80-Y0619-1 Rev. A 27 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet 2.2 Pin description Pin Description Table 2-1 Signal to pin descriptions (QFN) Signal name Pin l Media-dependent interface ia CH1_TRXN0 13 t CH1_TRXP0 12 n CH1_TRXN1 16 CH1_TRXP1 15 e CH1_TRXN2 19 id CH1_TRXP2 18 f CH1_TRXN3 22 n CH1_TRXP3 21 o CH2_TRXN0 25 CH2_TRXP0 24 C CH2_TRXN1 28 CH2_TRXP1 27 s CH2_TRXN2 31 o CH2_TRXP2 30 r CH2_TRXN3 34 e CH2_TRXP3 33 th RGMII/MII/RMII interface 0 A GTXCLK_0/TXCLK_0 59 Type Description IA,OA IA,OA IA,OA Media-dependent interface, MDI[3:0]: Transmitter output positive/negative Connect directly to transformer without any pull-down terminators, such as resistors or capacitors, required. IA,OA IA,OA IA,OA IA,OA IA,OA IA,OA IA,OA IA,OA Media-dependent interface, MDI[3:0]: Transmitter output positive/negative Connect directly to transformer without any pull-down terminators, such as resistors or capacitors, required. IA,OA IA,OA IA,OA IA,OA IA,OA I/O RGMII transmit clock, 125 MHz, 25 MHz or configurable. This is the reference clock for RGMII/MII mode. In RGMII/MII mode, when RXCLK_0 m52 RXDV_0 m RXD0_0 o RXD1_0 lcRXD2_0 RXD3_0 aTXEN_0 Qu TXD0_0 51 53 54 56 57 58 60 TXD1_0 61 interface with 3.3 V source, insert a 200 ohm resister to this pin. I/O RGMII receive clock. This is the reference clock for RGMII/ MII/RMII mode. Reserve several resistors for EMI control. I/O,PU RGMII/MII/RMII received data valid. This is output signal for MAC controller. I/O, PD RGMII/MII/RMII receive data or configuration. The reference clock I/O, PD for these output signals is RXCLK_0 (pin 52). RXD[3:2]_0 are used as data output when operating in RGMII or I/O, PU MII mode. I/O, PD RXD[1:0]_0 are used as data output when operating in RMII mode. I RGMII/MII/RMII transmit enable. This is input signal for the MAC controller. I RGMII/MII/RMII transmit data. These are input signals for MAC I controller. The reference clock for these input signals is GTXCLK_ 0(pin59). TXD2_0 TXD3_0 62 I TXD[3:2]_0 are used as data input when operating in RGMII or MII 63 I mode; TXD[1:0]_0 are used as data input when operating in RMII mode. 80-Y0619-1 Rev. A 28 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Pin Description Table 2-1 Signal to pin descriptions (QFN) (cont.) Signal name Pin Type Description LED LED_LINK10n_1 tial LED_LINK10n_2 83 O,D LED_LINK10n_[2:1] 86 O,D Parallel LED output for 10BASE-Te link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending on the power-on strapping setup. The LED behaviour can be configurable, see the LED control registers (0x0050– 0x005C). The register offset 0x0058 is for 10BASE-Te. n LED_LINK100n_1 fide LED_LINK100n_2 84 O,D LED_LINK100n_[2:1] 87 O,D Parallel LED output for 100BASE-Tx link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending on the power-on strapping. The LED behaviour can be configured, see the LED control registers (0x0050–0x005C). The register offset 0x0054 is for 100BASE-Te. LED_LINK1000n_1 Con LED_LINK1000n_2 85 O,D LED_LINK1000n_[2:1] 88 O,D Parallel LED output for 1000BASE-T link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending on the power-on strapping setup. The LED behaviour can be configured, see the LED control registers (0x0050– 0x005C). The register offset 0x0050 is for 1000BASE-T. UART/MDIO and SPI EEPROM s SPI_CLK 47 I/O, PD SPI clock o SPI_CS 46 I/O, PD SPI chip selection r SPI_DI 43 I, PD SPI data input e SPI_DO 44 I/O, PU SPI data output h UART_RXD/MDC 49 I, PD Management data clock reference t UART_TXD/MDIO 48 I/O Management data A SerDes interface SOP 76 SON 75 m SIP 79 m SIN 78 Miscellaneous o RBIAS 9 lcRESETn 42 QuaTEST_MODE 74 OA SerDes differential output pair OA IA SerDes differential input pair IA OA Connect 2.4 kΩ resistor to GND. The resistor value is adjustable, depending on PCB. IH Chip reset, active low. The active low duration must be greater than 10 ms. I Test mode: 0 = Normal operation 1 = Test mode 80-Y0619-1 Rev. A 29 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Pin Description Table 2-1 Signal to pin descriptions (QFN) (cont.) Signal name Pin Type Description XTLI XTLO INTn VREF POS_SWREG Power DVDD AVDD 2 3 81 7 72 23 41 50 65 73 80 4 5 11 14 20 26 32 35 36 IA Crystal oscillator input, connect a 27 pF capacitor to GND. An external 25 MHz clock with swing from 0-1 V can be injected to this pin. When an external clock source is used, the 27 pF capacitor l should be removed from this pin and the 27 pF capacitor at XTLO should be maintained. ia OA Crystal oscillator output, connect a 27 pF capacitor to GND t O, PU Interrupt, active low. See the global interrupt registers (0x0020–0x0024). n OA Reference voltage, put a 1 nF cap to GND e I/O, PU Control switch regulator output voltage fid P 1.2 V digital power input Atheros Con P 1 V analog power input m39 40 77 GND lcom AVDD33 aVDD33_SWR Qu DVDD27 1 67 70 EPAD 8 17 29 68 45 82 P P P P Ground 3.3 V analog power input 3.3 V power for internal switching regulator 2.7 V power input for I/O PAD excluding RGMII interface. LX 69 OA Internal switching regulator output; connect to an inductor 4.7 μH, 1 A to generate 1.2 V power. VDD27_REG0 6 P 2.7 V power output for analog; connect to an external capacitor 1 μF for power supply stabilization. 80-Y0619-1 Rev. A 30 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Pin Description Table 2-1 Signal to pin descriptions (QFN) (cont.) Signal name VDD27_REG1 VDD15_REG0 VDD15_REG1 AVDDVCO_0 AVDDVCO_1 FILCAP_27A_0 FILCAP_15D_0 Pin Type Description 66 55 71 10 37 38 64 P 2.7 V power output for DVDD27; connect to an external capacitor 1 μF for power supply stabilization. P RGMII interface 0 power source. It can be connected to external l 2.7 V power or only connect an external capacitor 1 μF and using ia internal LDO for 1.8 V or 1.5 V interface power. t P RGMII interface 1 power source. It can be connected to external 2.7 V power or only connect an external capacitor 0.1 μF and n using internal LDO for 1.8 V or 1.5 V interface power. e P Analog 1.2 LDO output filter pin for VCO P id P Connect to an external capacitor 0.1 μF Atheros Conf P Qualcomm 80-Y0619-1 Rev. A 31 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 3 Functional Description tial The QCA8334 supports operating modes that can be configured using a low-cost serial EEPROM n and/or the MDC/MDIO interface. The QCA8334 also supports a CPU header mode that appends e two bytes to each frame. id The CPU can deheader frame with header to configure the switch register, the address lookup table, and VLAN and receive auto-cast MIB frames. The QCA8334 supports single PHY interface f as a WAN port. n The first port (port0) supports a MAC interface that can be configured in RGMI/MII/RMII-PHY o mode to connect to an external management CPU or an integrated CPU in a routing or xDSL engine. C The QCA8334 contains a 2K entry address lookup table that employs three entries per bucket to avoid hash collision and maintain non-blocking forwarding performance. The table also provides s read/write accesses from the serial and CPU interfaces; each entry can be configured as a static o entry. The QCA8334 supports 4K VLAN entries configurable as port-based VLANs or 802.1q tagr based VLANs. e To provide non-blocking switching performance in all traffic environments, the QCA8334 supports several types of QoS function with four-level priority queues based on port, IEEE 802.1p, h IPv4 DSCP, IPv6 TC, 802.1q VID, or MAC address. Back pressure and IEEE 802.3x pause framet based flow control schemes are included to support zero packet loss under temporary traffic A congestion. m Meeting current service provider requirements, the QCA8334 switch uses the latest Qualcomm Atheros QoS switch architecture that supports ingress policing and egress rate limiting. The QCA8334 device supports IPv4 IGMP snooping and IPv6 MLD snooping to significantly improve the performance of streaming media and other bandwidth-intensive IP multicast applications. m A broadcast storm control mechanism prevents the packets from flooding into other parts of the o network. The QCA8334 device has an intelligent switch engine to prevent head-of-line blocking problems on per-CoS basis for each port. alc 3.1 Basic switch function u The QCA8334 automatically learns the port number of an attached end station by looking at the Q source MAC address of all incoming packets at wire speed. If the source address is not found in the address table, the QCA8334 device adds it to the table. Once the MAC address/port number mapping is learned, all packets directed to that end station's MAC address are forwarded to the learned port number only. 80-Y0619-1 Rev. A 32 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description When the QCA8334 device receives incoming packets from one of its ports, it searches in its address table for the destination MAC address, then forwards the packet to the appropriate port within the VLAN group. If the destination MAC address is not found (i.e. a new, unlearned MAC address), the QCA8334 handles the packet as a broadcast packet and transmits it to all ports within the VLAN group, except to the port where it comes in. ial 3.1.1 Lookup engine t The QCA8334 lookup engine or ARL (Address Resolution Logic) retrieves the DA and SA from n each frame received from each port. The ARL performs all address searching, learning, and aging functions at wire speed. The ARL engine uses a hashing algorithm for fast storage and retrieval of e address entries. To avoid hash collision, the QCA8334 uses a three-entry bin per hash location that id stores up to three MAC addresses at each hash location. The address database is stored in the embedded SRAM and has a size of 2048 entries. nf 3.1.2 Automatic address learning o Up to 2048 MAC address/port number mappings can be stored in the address table. A three-way C hash algorithm allows a maximum of three different addresses with the same hash key to be stored simultaneously. The QCA8334 searches for the SA of an incoming packet in the address table. s If the SA is not found, the address is hashed and stored in the first empty bin found at the hashed o location. If all address bins are full, each entry's age time is examined to select the least recently r used bin. e If the SA is found, the aging value of the corresponding entry is reset to 0x7. If the DA is dropped due to error or pause frame, the QCA8334 does not perform learning process for this frame. Ath 3.1.3 Automatic address aging m Address aging supports network topology changes such as an end station disconnecting from the network or an address moving from one port to another. An address is removed (aged-out) from the address database after a specified amount of time since the last time it appears in an incoming frame source address. The QCA8334 has a default aging time of 5 minutes, and can be set in 7- m second increments to a maximum of 10,000 minutes. lco 3.1.4 Flow control aThe QCA8334 device supports IEEE 802.3x full-duplex flow control, force-mode full-duplex flow control, and half-duplex backpressure. u If the link partner supports auto-negotiation, the 802.3x full-duplex flow control is auto-negotiated Q between the remote node and the QCA8334. If the full-duplex flow control is enabled, when the buffer number used for specific port exceed the per port buffer threshold or total buffer used exceeds global based buffer threshold, the QCA8334 sends out an IEEE 802.3x compliant pause frame to stop the remote device from sending more frames. 80-Y0619-1 Rev. A 33 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Half-duplex flow control regulates the remote station to avoid dropping packets in network congestion. Backpressure is supported for half-duplex operations. When the free buffer space is almost empty, the QCA8334 device transmits a jam pattern on the port and forces a collision. If the half-duplex flow control mode is not set, the incoming packet is dropped if there is no buffer space available. ial 3.1.5 ARL table t The address database is stored in the embedded SRAM and has a size of 2048 entries with a n default aging time of about 300 seconds or 5 minutes. e The ARL table supports: id  Search one address in the table f  Use Get Next to read out whole table n  Load and purge an entry in the ARL table  Flush entries: o  All entries C  All non-static entries s  One port's all entries o  One port's all non-static entries r All registers and counters can be accessed (read and written) through the UART/MDIO interface e and CPU port frames. Interrupts may be asserted upon access completion. th Table 3-1 ARL table A Bits Name Description 83:72 VID 71 RESERVED m 70 COPY_TO_CPU m 69 REDIRECT_TO_CPU lco68 LEAKY_EN Qua67:64 STATUS The VID group indicates to which the MAC address belongs. 1 = Packets received with this address should be copied to the CPU port 1 = Packets received with this address should be redirected to the CPU port. If no CPU is connected to the switch, this frame should be discarded. 1 = Use leaky VLAN enable for this MAC address. This bit can be used for unicast and multicast frame controlled by ARL_UNI_LEAKY_ EN AND ARL_MULTI_LEAKY_EN. 4’h0 = Empty entry 4’h1–4’h7 = Dynamic and valid entry 4’h8–4’hE = Reserved 4’F = Entry is static and is not aged out or changed by hardware. 63 RESERVED 62 SA_DROP_EN Drop packet enable when source address is in this entry. If this bit is set to 1, the packet with SA of this entry are dropped. 80-Y0619-1 Rev. A 34 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-1 ARL table (cont.) Bits Name Description 61 MIRROR_EN 0 = Packets should only be sent to destination port 1 = Packets should be sent to mirror port and destination port. ial 60 PRI_EN Priority override enable 1 = PRIORITY (ATU[58:56]) can override any other priority determined by the frame’s data. t 59 SVL_ENTRY 0 = IVL learned 1 = SVL learned en 58:56 PRIORITY The priority bits may be used as the frame’s priority when PRI_ OVER_EN (bit[60]) is set to 1. id 55 CROSS_PORT_STATE_EN 0 = Cross port state disable 1 = Cross port state enable onf 54:48 DES_PORT Indicate which ports are associated with this MAC address when they are set to 1. E.g. bit[48] is assigned to port0, bit[50] to port2, etc. If all bits are set to 0 and the entry is static, the packet should be dropped. For multicast address and unicast for link aggregation, more than one bit is set to 1. C 47:0 ADDRESS 48-bit MAC address s Table 3-2 Reserved ATU entry ro Bit Name 64 STATUS he 63 COPY_TO_CPU At 62 REDIRECT_TO_CPU Description 0 = Invalid 1 = Static and valid 1 = Packets received with the address should be copied to the CPU port 1 = Packets received with this address should be redirected to the CPU port. If no CPU is connected to the switch, the packet is dropped. m 61 LEAKY_EN 1 = Use leaky VLAN enable for this MAC address. This bit can be used for unicast and multicast frames, controlled by ARL_UNI_LEAKY_EN and ARL_MULTI_LEAKY_EN. m 60 MIRROR_EN 0 = Packets should be sent only to the destination port 1 = Packets should be sent to the mirror port and the destination port lco59 PRI_OVER_EN Priority override enable 1 = PRIORITY (ATU[58:56]) can override any other priority determined by the frame’s data a58:56 PRI This priority bit may be used as a frame’s priority when PRI_OVER_ EN is set to 1. u 55 CROSS_PORT_STATE_EN 1 = Cross port state enabled Q 54:48 DES_PORT These bits indicate which ports are associated with this MAC address when they are set to 1. E.g.bit[48] is assigned to port0, bit[50] to port2, etc. 47:0 ADDRESS 48-bit MAC address 80-Y0619-1 Rev. A 35 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.1.6 Mirroring Mirroring monitors traffic for information gathering or troubleshooting higher layer protocol operations. User can specify a desired mirrored port (sniffer port) to receive a copy of all traffic passing through a designated mirrored port. l The QCA8334 supports mirror frames that: ia  Come from an ingress-specified port (ingress mirroring) t  Destined for egress-specified port (egress mirroring) n  Mirror all ingress and egress traffic to a designated port e  Mirror frames when configuring the ARL table with mirror enabled id  ACL mirror nf 3.2 QoS Co 3.2.1 Scheduling For the QCA8334, ports MAC0, MAC5, and MAC6 support six queues and ports MAC1, MAC2, s MAC3 and MAC4 support four queues. This egress queue scheduling mechanism can be o configured to one of the following modes: r  Strict Priority (SP) e  Weighted Fair Queuing (WFQ) h  Mixed mode: The highest one or two queues use Strict Priority; other queues use wEighted t Fair Queuing scheme. A The scheduling mode is configurable per port basis. The QCA8334 recognizes the QoS information of ingress frames and maps to different egress m priority levels. The QCA8334 determines the priority of the frames based on DA, TOS/TC, VLAN, and port. Each has an enable bit that can be applied. When more than one type of priority is selected, the order in which the frame priority should be applied can be determined. Priority m enable bits and select order bits are set on a per port basis at the port's base address. lco 3.2.2 Ingress rate limit aIn triple-play applications, the switch needs to limit the rate for all frames but continue to maintain QoS policy. The QCA8334 supports ingress and egress rate limiting requirements on a per port u basis by configuring the port rate limit register. Q Ingress rate limit can include or exclude the consideration of management frames and registered multicast frames. The QCA8334 can limit all frames and support rate limits from 32 Kbps to 1 Gbps, at 32 Kbps granularity. Ingress rate limit supports one of the following mode on a per port basis. 80-Y0619-1 Rev. A 36 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description  Two single rate mode  Two rate three color mode: QCA8334 can support color aware or color blind mode In color aware mode, QCA8334 can recognize the color with DEI bit if S-tagged frame or configured DEI bit in registers (register 0x0630–0x0650) for tagged priority or DSCP. l  When DEI is 0, the frame is declared Green. The long term average bit rate of Service Frames ia that are declared Green is bounded by CIR + EIR. t  While DEI is 1, the frame is declared Yellow. The long term average bit rate of Service Frames that are declared Yellow is bounded by EIR if Green is not using EIR bucket. n QCA8334 also supports Coupling Flag (CF). The choice of the value for CF has the effect of e controlling the volume of the Service Frames that are declared Yellow. id  When CF is set to 0, the long term average bit rate of Service Frames that are declared Yellow f is bounded by EIR.  When CF is set to 1, the long term average bit rate of Service Frames that are declared Yellow n is bounded by CIR + EIR, depending on the volume of offered Service Frames that are o declared Green. C In color blind mode, the long term average bit rate of Service Frames is bounded by CIR + EIR, among which frames using CIR bucket is declared Green and frames using EIR bucket is declared Yellow. ros 3.2.3 Egress rate limit e The QCA8334 can also support per port or per queue based egress rate limiting. The QCA8334 h can support egress rate limits from 32 Kbps to 1 Gbps, at 32 Kbps granularity. At 3.2.4 Head-of-line blocking (HOL) The QCA8334 supports ingress port buffer and egress port/queue buffer control to handle head-of- m line blocking. The maximum queue depth for per port or per queue is configurable. To avoid HOL, each port has dedicated buffer resource that can be configured per queue and/or per m port basis for egress port. When the egress queue depth exceeds the configured number, the ingress frame destination to this queue is dropped if the flow control of source port is disabled; the pause o frame is sent out to prohibit more frames from coming in if flow control of source port is enabled. lcWhen queue limit reaches 3/4 of the HOL threshold, the ingress packets are dropped according to the RED algorithm. If color aware mode is configured, Yellow packets are dropped if the queue areaches 3/4 of the queue HOL threshold, while Green packets are dropped according to the RED Qu algorithm. 3.2.5 Egress queue remap The QCA8334 supports priority remap that can modify DSCP or 802.1Q priority tag in the egress frames. This feature is configured per egress queue. There are 16 entries of egress queue remap 80-Y0619-1 Rev. A 37 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description table in total and the entry offset is 0x10 with base address 0x5AE00. Table 3-3 shows the entry format of egress queue remap. 3.3 Table 3-3 Egress queue remap l Bit ia 23 t 22 21:16 n 15:14 e 13:8 id 7 f 6:4 n 3 2:0 Field DSCP_REMARK_EN PRI_REMARK_EN DSCP_GREEN RESERVED DSCP_YELLOW RESERVED PRI_GREEN RESERVED PRI_YELLOW Description Remapped DSCP enable Remapped priority enable Remapped DSCP for green Remapped DSCP for yellow Remapped priority for green Remapped priority for yellow Co VLAN s The QCA8334 switch supports many VLAN options, including IEEE 802.1q and port-based o VLANs. The QCA8334 supports 4096 IEEE 802.1q VLAN groups and 4K VLAN table entries. r The QCA8334 device checks VLAN port membership from the translation VID. e Table 3-5 shows the QCA8334 supported 802.1q modes. The port-based VLAN is enabled h according to the user-defined port VID value. The QCA8334 supports optional discard of tagged, t untagged, and priority tagged frames. The QCA8334 supports untagging of the VLAN ID for packets going out on untagged ports on a per-port basis. The QCA8334 also supports double A tagging frame which is S-Tag and C-Tag. The QCA8334 can lookup the 4K VLAN table by S-Tag or C-Tag, depending on the configuration m mode. There are also 64 entries in VLAN translation table to support the VLAN operation. m 3.3.1 Port-based VLAN o The QCA8334 switch supports port-based VLAN functionality used for non-management frames lcwhen 802.1q is disabled on the ingress port. When FORCE_PORT_VLAN_EN is enabled, non- management frames conform to port-based configurations even if 802.1q is enabled on the ingress aport. Each ingress port contains a register that restricts the output (or egress) ports to which it can send frames. This port-based VLAN register has a field PORT_VID_MEM that contains the port- u based setting. If bit[0] of a port's PORT_VID_MEM is set to 1, the port is allowed to send frames Q to port 0, and so on. At reset, the PORT_VID_MEM for each port is set to all 1s, except for each port's own bit, which clears to 0. Note that the CPU port is port 0. 80-Y0619-1 Rev. A 38 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.3.2 802.1q VLANs The QCA8334 supports a maximum of 4096 entries in the VLAN table. The device supports 4096 VLAN ID, ranging from 0 to 4095. The QCA8334 supports both shared and independent VLAN learning (SVL and IVL). This means that forwarding decisions are based on the frame's l destination MAC address, which should be unique among all VLANs. tia 3.3.3 VLAN security n The QCA8334 checks the ingress packets based on the VLAN operation mode and decide whether to forward or drop the packets. There are two sets of configuration: one is the ingress VLAN e mode, see Table 3-4; another is 802.1q mode, see Table 3-5. The ingress VLAN mode is for id checking whether the ingress frame is tagged or not. The 802.1q mode is for checking if the ingress VID is valid and if the ingress port belongs to the member. nf Table 3-4 Ingress VLAN mode o ING_VLAN_MODE 00 C 01 s 10 o 11 Frame with tag Forward Forward Drop Forward Frame with priority tag Forward Drop Forward Forward Frame without tag Forward Drop Forward Forward er Table 3-5 802.q mode h 802.1q At Secure VID miss Drop VLAN member violation Drop No violation Forward Use VLAN table result Check mDrop Forward Use VLAN table result Forward Use VLAN table result Fallback om Disable Forward Use port-based VLAN Forward Use VLAN table result Forward Use port-based VLAN Forward Use VLAN table result alc 3.3.4 Port isolation u When FORCE_PORT_VLAN_EN is enabled on the ingress port, except for VLAN member Q check, non-management frames conform to port-based VLAN member check. 80-Y0619-1 Rev. A 39 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.3.5 Leaky VLAN The QCA8334 supports leaky VLAN to enable specific frames to be forwarded across VLAN boundary. Three types of frames can be leaked across VLAN boundary: unicast, multicast and ARP. Unicast and multicast are port or MAC address based, and ARP is port-based. ial 3.3.6 VLAN translation t The QCA8334 supports VLAN translation function. The QCA8334 lookups the VLAN translation n table when packets arrive at the ingress port and packets transmit at the egress port. e The VLAN translation table allows user to modify the C-VID and/or S-VID, see Table 3-6. id Table 3-6 VLAN translation table f Bits Name Description n 48 ONE_TO_ONE_MODE 0 = Disable 1:1 VLAN o 1 = Enable 1:1 VLAN 47 C_VID_EN 1 = C-VID enable C 46 S_VID_EN 1 = S-VID enable s 45 O_VID_C 0 = Use S-VID 1 = Use C-VID ro 44:38 PORT_BIT_MAP Source port when frame received; destination port when frame send out. the 37:36 ENTRY_MODE 00 = Invalid entry 01 = Forward lookup enable (o -> s,c) 10 = Reverse lookup enable (s,c -> o) 11 = Forward & reverse lookup both enabled A 35:24 C_VID Custom VID 23:12 S_VID 11:0 O_VID m Service VID Original VID m 3.3.7 Egress mode o The QCA8334 supports per port egress VLAN mode: lc Tagged a Untagged  Unmodified Qu  Untouched Frames sent out with tagged or untagged depend on the egress mode setting, see Table 3-7. 80-Y0619-1 Rev. A 40 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-7 VLAN egress mode — tagging EG_VLAN_MODE Egress VID = Untagged Egress VID = Priority tagged Egress VID = Tagged Tagged l Unmodified ia Untagged Untouched Egress port default VID Egress port default VID Untagged Priority untagged Untagged Untagged Original packet’s encapsulation Egress VID Egress VID Untagged nt The egress mode can be defined by the different operation modes, see Table 3-8. ide Table 3-8 VLAN egress mode 802.1q disabled on egress port f Edge port S-Tag mode n C-Tag mode o Core port S-Tag mode S-Tag C C-Tag C-Tag mode S-Tag s C-Tag Port-based egress VLAN mode Port-based egress VLAN mode VLAN-based egress VLAN mode VLAN-based egress VLAN mode Keep translation result Keep translation result VLAN-based egress VLAN mode ro 3.3.8 VLAN table e The QCA8334 supports 4K VLAN membership table. It also supports the following commands to th access the VLAN table. A  Read one entry m  Use Get Next to read out whole table  Load and purge of an entry  Flush all entries, flush all of one port's entries m Table 3-9 VLAN table format lcoBits Name 20 VALID Qua 19 IVL_EN Description 0 = Entry is empty 1 = Entry is valid 0 = VID is used to SVL; VID replaced by 0 when search MAC address. 1 = VID is used to IVL 18 LEARN_LOOKUP_ DIS 0 = Normal operation about learn and final DP 1 = Not learn and not use ARL table DP to calculate final DP, but use UNI flood DP as ARL DP to calculate DP 80-Y0619-1 Rev. A 41 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-9 VLAN table format (cont.) Bits Name Description 3.4 17:4 EG_VLAN_MODE tial 3 PRI_OVER_EN en 2:0 PRI E.g. bits[5:4] for port0, …bits[17:16] for port6 00 = Unmodified 01 = Untagged 10 = Tagged 11 = Not member Priority overwrite enable 0 = Keep the original VLAN priority 1 = Overwrite the VLAN priority with bits[2:0] of this entry Used as frame's VLAN priority when the PRI_OVER_EN (bit[3]) is set to 1. nfid ACL o The QCA8334 supports up to 96 ACL rule table entries. Each rule can support filtering or re- direction of the incoming packets based on the following field in the packet. C  Source MAC address s  Destination MAC address  VID ro  EtherType e  Source IP address h  Destination IP address t  Protocol A  Source TCP/UDP port number  Destination TCP/UDP port number m  Physical port number  User-defined window pattern m When the incoming packets match an entry in the rules table, the following action can be taken o defined in the result field. lc Change C-Tag or S-Tag  Drop or redirect the packet a Configure rate limit based on flow Qu  Change priority The QCA8334 can bind multiple keys and support up to 2 matches per packet to support different functions such as QoS, forwarding, routing, rate measuring/limiting, etc. 80-Y0619-1 Rev. A 42 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.4.1 ACL rule The ACL rule is constructed from a packet pattern, pattern mask and action. The pattern can be defined as MAC layer or layer 3 (IPv4 or IPv6) or user-defined window. The ACL pattern types supported by the QCA8334 are listed in Table 3-10. ial Table 3-10 ACL patterns t Value 1 n 2 e 3 id 4 f 5 n 6 7 o 0 MAC pattern IPv4 pattern IPv6 pattern 1 IPv6 pattern 2 IPv6 pattern 3 Window pattern Enhanced MAC pattern Invalid pattern Description s C 3.4.2 Action definition o The action is taken when the defined pattern is matched. r In the ACL rule matching, the QCA8334 supports two match consolidations. If the key of ingress e frame is matched with two entries in the ACL, these two actions consolidate. The basic rule for h consolidation is that the first action is the first priority if the related bit is active. If the related bit of t the first entry is inactive, the second entry is used. But for ACL_MATCH_INT_EN, ACL_DP_ A ACT and MIRROR_EN field is the OR operation between two actions. m Table 3-11 Action definition Bits Name 80 ACL_MATCH_INT_EN m 79 ACL_EG_TRNAS_BYPASS o78 ACL_RATE_EN lc77:73 ACL_RATE_SEL Qua72:70 ACL_DP_ACT Description Generate interrupt Bypass egress QinQ result 0 = Not use ACL rate limit 1 = Use ACL rate limit Select ACL rate limit (index) 111 = Drop 011 = Redirect 001 = Copy to CPU 000 = Forward 69 MIRROR_EN 1 = Mirror packet to mirror port 68 DES_PORT_OVER_EN 1 = Use DES_PORT to determine packet destination port. It can cross VLAN. 80-Y0619-1 Rev. A 43 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-11 Action definition (cont.) Bits Name Description 67:61 DES_PORT If DES_PORT_EN is set to 1, these bits are used to determine destination port. 60 ENQUEUE_PRI_OVER_EN 1 = Use ENQUEUE_PRI to determine enqueue priority l 59:57 ENQUEUE_PRI Enqueue priority ia 56 ARP_WCMP 1 = Select hash t 55:49 ARP_INDEX Index of ARP table n 48 ARP_INDEX_OVER_EN Overwrite the router's result fide 47:46 FORCE_L3_MODE 00 = No force 01 = SNAT 10 = DNAT 11 = Reserved n 45 LOOKUP_VID_CHANGE_EN 1 = Lookup use VID in S-Tag or C-Tag, determined by switch tag mode. For S-Tag mode, use S-Tag; for C-Tag mode, use C-Tag. o 44 TRANS_CTAG_CHANGE_EN Enqueue egress translation key change enable 43 TRANS_STAG_CHANGE_EN Enqueue egress translation key change enable C 42 CTAG_DEI_CHANGE_EN 1 = Frame should be send out by C-Tag; CFI changed to C-Tag[12] s 41 CTAG_PRI_REMAP_EN 1 = Frame should be send out by C-Tag; priority changed to CTag[15:13] o 40 STAG_DEI_CHANGE_EN 1 = Frame should be send out by S-Tag; CFI changed to S-Tag[12] er 39 STAG_PRI_REMAP_EN 1 = Frame should be send out by S-Tag; priority changed to STag[15:13] Ath 38 DSCP_REMAP_EN Modify the DSCP of packet 0 = Unmodified 1 = Modified 37:32 DSCP 31:16 CTAG omm 15:0 STAG DSCP value [15:13] C-Tag priority [12] CFI [11:0] C-Tag VID [15:13] S-Tag priority [12] DEI [11:0] S-Tag VID alc 3.4.3 MAC pattern Qu The action is taken when the MAC pattern is matched. 80-Y0619-1 Rev. A 44 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-12 MAC pattern Byte Name Description 16 ial 15:14 t 13:12 iden 11:4 f 3:0 [7] RULE RESULT INVERSE EN [6:0] SOURCE PORT TYPE VLAN[15:13] PRIORITY [12] CFI [11:0] VID/VID LOW SA DA 0 = Apply action on the rule entry matches 1 = Apply action on the rule entry does not match Enable rule for physical source port EtherType field VLAN priority bits VLAN CFI bit This field can be VID or VID_LOW, depending on the VID_MASK_ OPTION. Source address Destination address on Table 3-13 MAC pattern mask C Byte 16 Name [7:6] RULE VALID ros [5] FRAME WITH TAG MASK he [4] FRAME_WITH_TAG At [3] VID MASK Description 00 = Start 01 = Continue 10 = End 11 = Start & end 0 = Ignore FRAME_WITH_TAG 1 = Consider FRAME_WITH_TAG 0 = Untagged frame 1 = Tagged frame 0 = Range m [2:0] RULE TYPE 15:14 13:12 lcom 11:6 5:0 TYPE MASK VLAN [15:13] PRIORITY MASK [12] CFI MASK [11:0] VID MASK/VID HIGH SA MASK DA MASK Qua3.4.4 IPv4 pattern 1 = Mask These three bits must be 001 to indicate the MAC rule. Enable check mask for EtherType Enable check mask for VLAN priority Enable check mask for VLAN CFI Enable check mask for VID to define VID upper boundary Enable check mask for SA Enable check mask for DA The action is taken when the IPv4 rule is matched. 80-Y0619-1 Rev. A 45 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-14 IPv4 pattern Byte Name Description 16 [7] RULE RESULT INVERSE EN 0 = Apply action on frames that match the rule 1 = Apply action on frames that do not match the rule l [6:0] SOURCE PORT Enable rule for physical source port ia 15 [7:6] RESERVED t [5:0] TCP FLAGS TCP control bits n 14 [7] RESERVED e [6] DHCPv4 DHCPv4 frame id [5] RIPv1 RIPv1frame f [4]SPORT_FIELD_TYPE 0 = TCP/UDP sport 1 = ICMP type/code n [3:0] RESERVED o 13:12 TCP/UDP SOURCE PORT/ TCP/UDP SOURCE PORT LOW C OR ICMP TYPE CODE TCP/UDP source port number or low bound port number. See mask byte 14 bit[0]. 11:10 TCP/UDP DESTINATION PORT/ TCP/UDP destination port number or low bound port s TCP/UDP DESTINATION PORT LOW number. See mask byte 14 bit[1]. o 9 DSCP DSCP field r 8 IP PROTOCOL IP protocol e 7:4 SIP Source IP address Ath 3:0 DIP Destination IP address Table 3-15 IPv4 mask Byte Name m 16 [7:6] RULE VALID om [5:3] RESERVED lc [2:0] RULE TYPE 15 [7:6] RESERVED Qua [5:0] TCP FLAGS MASK 00 = Start 01 = Continue 10 = End 11 = Start & end Description These three bits must be 010 to indicate the IPv4 rule. Enable check mask for TCP control bits 80-Y0619-1 Rev. A 46 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-15 IPv4 mask (cont.) Byte Name Description 3.4.5 14 [7] RESERVED [6] DHCPV4 MASK Enable check for DHCPv4 frame l [5] RIPv1 MASK Enable check for RIPv4 frame ia [4:2] RESERVED nt [1] TCP/UDP DESTINATION MASK Indicates the definition of bytes 11 and 10. 0 = Range 1 = Mask ide [0] TCP/UDP SOURCE MASK Indicates the definition of bytes 13 and 12. 0 = Range 1 = Mask f 13:12 TCP/UDP SOURCE PORT MASK/ n TCP/UDP SOURCE PORT HIGH OR ICMP TYPE CODE MASK This can be mask or high definition. See byte 14, bit[0]. o 11:10 TCP/UDP DESTINATION PORT MASK/ This can be mask or high definition. See byte 14, bit[1]. TCP/UDP DESTINATION PORT HIGH C 9 DSCP MASK Enable check for DSCP bits s 8 IP PROTOCOL MASK Enable check for IP protocol bits o 7:4 SIP MASK Enable check for SIP r 3:0 DIP MASK Enable check for DIP Athe IPv6 pattern Table 3-16 IPv6 pattern 1 Byte m 16 Name [7] RULE RESULT INVERSE EN m[6:0] SOURCE PORT o15:0 DIP lcTable 3-17 IPv6 pattern 2 a Byte Name Qu 16 [7] RULE RESULT INVERSE EN Description 0 = Apply action on the rule entry matches 1 = Apply action on the rule entry does not match Enable rule for physical source port Destination IP address Description 0 = Apply action on the rule entry matches 1 = Apply action on the rule entry does not match [6:0] SOURCE PORT Enable rule for physical source port 15:0 SIP Source IP address. 80-Y0619-1 Rev. A 47 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-18 IPv6 pattern 3 Byte 16 15 14 13:12 11:10 9 8:6 5:2 1 0 Name Description l [7] RULE RESULT INVERSE EN 0 = Apply action on the rule entry matches 1 = Apply action on the rule entry does not match ia [6:0] SOURCE PORT Enable rule for physical source port [7:6] RESERVED t [5:0] TCP FLAGS TCP control bits n [7] RESERVED e [6] DHCPv6 DHCPv6 frame id [5] RESERVED f [4]SPORT_FIELD_TYPE 0 = TCP/UDP SPORT 1 = ICMP TYPE/CODE n [3:0] RESERVED o TCP/UDP SOURCE PORT/ TCP/UDP SOURCE PORT LOW C or ICMP TYPE CODE TCP/UDP source port number or the low bound port number. See mask byte 14 bit[0]. ICMP type code, see byte 14 bit[4]. TCP/UDP DESTINATION PORT/ TCP/UDP destination port number or the low bound port s TCP/UDP DESTINATION PORT LOW number, see mask byte 14 bit[1]. o RESERVED r [23:20] RESERVED e [19:0] IPV6 FLOW LABEL IPv6 flow label h RESERVED t DSCP DSCP field A IP PROTOCOL IP protocol m Table 3-19 IPv6 mask 1 Byte Name m 16 [7:6] RULE VALID alco[5:3] RESERVED [2:0] RULE TYPE Qu 15:0 DIP MASK 00 = Start 01 = Continue 10 = End 11 = Start & end Description These three bits must be 011 to indicate the IPv6 rule 1. Enable check for destination IP address 80-Y0619-1 Rev. A 48 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-20 IPv6 mask 2 Byte Name Description 16 [7:6] RULE VALID tial [5:3] RESERVED n [2:0] RULE TYPE 15:0 SIP MASK 00 = Start 01 = Continue 10 = End 11 = Start & end These three bits must be 100 to indicate the IPv6 rule 2 Enable check for source IP address ide Table 3-21 IPv6 mask 3 f Byte Name n 16 [7:6] RULE VALID Co [5:3] RESERVED s [2:0] RULE TYPE o 15 [7:6] RESERVED r [5:0] TCP FLAGS MASK e 14 [7] FORWARD TYPE MASK h [6] DHCPV6 MASK At [5] RESERVED 00 = Start 01 = Continue 10 = End 11 = Start & end Description These three bits must be 101 to indicate the IPv6 rule 3. Enable check mask for TCP control bits Enable check for DHCPv6 frame [4:2] RESERVED m [1] TCP/UDP DESTINATION MASK 0 = Range 1 = Mask [0] TCP/UDP SOURCE MASK m 13:12 TCP/UDP SOURCE PORT/ oTCP/UDP SOURCE PORT HIGH lc or ICMP TYPE CODE MASK 11:10 TCP/UDP DESTINATION PORT/ a TCP/UDP DESTINATION PORT HIGHMASK u 9 RESERVED Q 8:6 [23:20] RESERVED 0 = Range 1 = Mask Enable check for TCP/IP source port or TCP/IDP source port upper bound; Enable check for ICMP type code. Enable check for TCP/UDP destination port or TCP/UDP destination port upper bound. [19:0] IPV6 FLOW LABEL MASK Enable check for IPv6 flow label 5:2 RESERVED 80-Y0619-1 Rev. A 49 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-21 IPv6 mask 3 (cont.) Byte Name Description 1 DSCP MASK 0 IP PROTOCOL MASK Enable check for DSCP Enable check for IP protocol ial 3.4.6 Window pattern nt Table 3-22 Window pattern e Byte id 16 Name [7] RULE RESULT INVERSE EN f [6:0] SOURCE PORT n 15:0 DATA Description 0 = Apply action on frames that match the rule 1 = Apply action on frames that do not match the rule Enable rule for physical source port Data pattern Co Table 3-23 Window pattern mask Byte s 16 Name [7:6] RULE VALID ero [2:0] RULE TYPE Ath 15:0 DATA MASK Description 00 = Start 01 = Continue 10 = End 11 = Start & end These three bits must be 110 to indicate the window rule. Enable check for data pattern m 3.4.7 Enhanced MAC pattern Table 3-24 Enhanced MAC pattern m Byte o16 Name [7] RULE RESULT INVERSE EN Qualc [6:0] SOURCE PORT Description 0 = Apply action on frames that match the rule 1 = Apply action on frames that do not match the rule Enable rule for physical source port 80-Y0619-1 Rev. A 50 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-24 Enhanced MAC pattern (cont.) Byte Name Description 15 [7] FRAME WITH STAG MASK l [6] FRAME_WITH_STAG ia [5:2] RESERVED t [1] DA_SEL en [0] SVID MASK id 14:13 f 12:11 Con 10:9 ros 8:6 e 5:0 TYPE CTAG [15:13] PRIORITY [12] CFI [11:0] VID/VID LOW STAG [15:13] PRIORITY [12] CFI [11:0] VID/VID LOW SA_LOW3/DA_LOW3 DA/SA 0 = Ignore FRAME_WITH_STAG 1 = Consider FRAME_WITH_STAG 0 = Frame without S-Tag 1 = Frame with S-Tag 0 = SA & DA[23:0] 1 = DA & SA[23:0] 0 = Range 1 = Mask EtherType C-Tag Priority CFI bit VID or VID low bound S-Tag Priority CFI bit VID or VID low bound SA[23:0] or DA[23:0], see byte 15 bit[1]. Destination or source address, see byte 15 bit[1] Ath Table 3-25 Enhanced MAC pattern mask Byte 16 mName [7:6] RULE VALID m[5] FRAME WITH CTAG MASK lco[4] FRAME_WITH_CTAG a [3] CVID MASK Qu [2:0] RULE TYPE Description 00 = Start 01 = Continue 10 = End 11 = Start & end 0 = Ignore FRAME_WITH_CTAG 1 = Consider FRAME_WITH_CTAG 0 = Frame without C-Tag 1 = Frame with C-Tag 0 = Range 1 = Mask These three bits must be 111 to indicate the enhanced MAC rule. 15 RESERVED 14:13 TYPE MASK Enable check for EtherType field 80-Y0619-1 Rev. A 51 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-25 Enhanced MAC pattern mask (cont.) Byte Name Description 3.5 12:11 tial 10:9 iden 8:6 f 5:0 CTAG MASK [15:13] PRIORITY MASK [12] CFI MASK [11:0] VIDMASK/VID HIGH STAG MASK [15:13] PRIORITY MASK [12] CFI MASK [11:0] VID MASK/VID HIGH SA_LOW3/DA_LOW3 MASK DA/SA MASK Enable check for C-Tag Enable check for priority Enable check for CFI bit Enable check for VID or VID upper bound Enable check for S-Tag Enable check for priority Enable check for CFI bit Enable check for VID or VID upper bound Enable check for SA[23:0] or DA[23:0] Enable check for destination or source address on IGMP/MLD snooping C The QCA8334 switch supports IPv4 IGMP snooping (v1/v2/v3 supported) and IPv6 MLD snooping. By setting the IGMP_MLD_EN bit in the FRAM_ACK_CTRL0/1 register, the s QCA8334 can look inside IPv4 and IPv6 packets and redirect IGMP/MLD frames to the CPU for processing. ro The QCA8334 also supports hardware IGMP join and fast leave functions. By setting IGMP_ e JOIN_EN and IGMP_LEAVE_EN bits in the port control register, the QCA8334 updates the ARL table automatically when the QCA8334 receives IGMP Join or Leave packets, and then forward h them to the router port directly in case the CPU is not acting as a router or when enabling multicast t VLAN_LEAKY to bypass multicast traffic directly from WAN to LAN. A The hardware join/fast leave supports the following packets:  IGMPv1 join m  IGMPv2/MLDv1 join/leave  IGMPv3/MLDv2 report excluding NONE or including NONE om 3.5.1 IEEE 802.3 reserved group addresses filtering control lcThe QCA8334 supports the ability to drop, redirect, copy 802.1D specified reserved group MAC aaddresses 01-80-C2-00-00-04 to 01-80-C2-00-00-0F by adding the addresses to the ARL table. Qu3.5.2 802.1x The QCA8334 supports identifying EAPOL frames by their reserved group addresses. Combined with port security feature, the QCA8334 can implement port-based or MAC-based access control. 80-Y0619-1 Rev. A 52 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.5.3 Forwarding The QCA8334 can be configured to prevent the forwarding of unicast frames and multicast frames with unregistered destination MAC address on a per-port basis. This can be done by setting UNI_ FLOOD_DP and MULTI_FLOOD_DP where a bit represents a port of the QCA8334. ial 3.5.4 MAC limit t The QCA8334 supports MAC limit on a per-port basis or a global basis. When the number of n learned MAC address limit is reached, the QCA8334 can be configured to forward a frame with a new source MAC address to the CPU or it can be dropped. ide 3.6 Atheros header nf The QCA8334 support proprietary Qualcomm Atheros header that can indicate the packet information and allow CPU to control the packet forwarding. The header can be 2 bytes or 4 bytes o with additional 2 bytes identifier. For 2 bytes header, each packet sent out or received must include header. For 4 bytes header, header can exist only in the management frame and there is no header C in the normal frame. The Atheros header also supports read/write register through the CPU port. s Table 3-26 shows the type in the Atheros header. ro Table 3-26 Type definition for Atheros header e Type h 5'h0 At 5'h1 Packet type NORMAL MIB Description Normal packet The packet includes MIB counter for the source port number in the header. 5'h2 m READ_WRITE_REG_ACK 5'h3 5'h4 m 5'h5 o5'h6 lc5'h7 5'h8 a 5'h9 u 5'hA Q 5'hB 802.1x RESERVED MAC ADDR RIPv1 DHCP PPPoE DISCOVERY ARP RESERVED IGMP MLD This packet indicates the register data for read register command or acknowledge for write register command. See “Atheros header receive” on page 55. 802.1x Reserved ARL RIPv1 DHCP PPPoE discovery ARP (If ARP not found, change this type to 5'h13) Reserved for RARP IGMP packets MLD packets 5'hC RESERVED Reserved for neighbor discovery 5'hD Redirect to CPU ACL_REDIRECT_TO_CPU, ARL_REDIRECT_TO_CPU offload match redirect to CPU 5'hE Normalization The frame does not comply with normal TCP/IP flow. 80-Y0619-1 Rev. A 53 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-26 Type definition for Atheros header (cont.) Type Packet type Description 5'hF 5'h10 ial 5'h11 5'h12 t 5'h13 n 5'h14 e 5'h15 id 5'h16 f 5'h17 on 5'h18 C 5'h19 os 5'h1A Learn limit IPv4 NAT to CPU IP frame: SIP not found NAT not found ARP not found IP frame: Routing not found TTL exceed MTU exceed Copy to CPU Mirror to CPU Flooding to CPU Forwarding to CPU The MAC address reaches the learning limit. Doing NAT and TCP special status; Doing NAT and frame is IP fragment. The SIP in IP frame does not pass the source check. NAT not found The ARP frame does not pass the source check. The frame DIP is not found in the routing table. The router tries to forward one frame, but the TTL is 0 after decrease 1 and the destination is not CPU. The frame length exceeds the MTU. ACL_COPY_TO_CPU, ARL_COPY_TO_CPU, Offload match copy to CPU ACL_MIRROR_TO_CPU, ARL_MIRROR_TO_CPU, PORT_ MIRROR_TO_CPU, Offload match mirror Broadcast flooding to CPU, unknown unicast/multicast flooding to CPU Bridging to CPU(ARL DP), routing to CPU (offload match), IGMP hardware join/leave forwarding to CPU, special DIP header/ACL assigned DP her 3.6.1 Transmit t The QCA8334 sends out the frame with Atheros header when header is enabled. The header A indicates the source port of the frame, frame type and priority. The detailed format of Atheros m header is shown in Table 3-27. Table 3-27 Atheros header transmit format Bits m 15:14 o13:11 lc10:6 5:4 a3 Qu 2:0 Name VERSION PRIORITY TYPE RESERVED FRAME_WITH_TAG SOURCE_PORT_NUM Description The value is 10. Frame priority Frame type. See “Type definition for Atheros header” on page 53. The ingress frame is tagged. The ingress port number 3.6.2 Receive The QCA8334 recognizes the Atheros header on receive when the header is enabled. The format is depicted in Table 3-28. 80-Y0619-1 Rev. A 54 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-28 Atheros header receive Bit Name Description 15:14 VERSION The version must be 10. l 13:11 PRIORITY Frame priority ntia 10:8 CONTROL 0 = Normal 1 = Read/write register 2 = Disable learn 3 = Disable offload 4 = Disable learn & offload e 7 FROM_CPU The bit indicates the forwarding method. id 0 = The forwarding is based on the lookup result. f 1 = The forwarding is based on DP_BIT_MAP and bypass lookup. 6:0 DP_BIT_MAP These bits indicate the forwarding port map. See the description in FROM_CPU. on 3.6.3 Header for read/write register C The QCA8334 supports the read/write register through the Atheros header. Figure 3-1 shows the s frame format of the read/write register command. ero 8 byte Ath command 4 byte 2 byte data header data Data: 0~16byte padding 4 byte crc m Figure 3-1 Read/write register command frame format Table 3-29 Command format for read/write register using Atheros header m Bit Name o 63:32 SEQ_NUM lc31:29 CHECK_CODE 28 CMD ua27:24 RESERVED Q 23:20 LENGTH Description The sequence number can be checked by CPU. Must be 101, otherwise the command would be ignored. 0 = Write 1 = Read The data length for read/write register. Maximum is 16 bytes. 18:0 ADDR The starting register address for the read/write command. The address must be boundary of word address. 80-Y0619-1 Rev. A 55 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.7 MIB/statistics counters The statistics counter block maintains a set of forty MIB counters per port. These counters provide a set of Ethernet statistics for frames received on ingress and transmitted on egress. A register interface allows the CPU to capture, read, or clear the counter values. l The counters support: ia  RMON MIB t  Ethernet-like MIB n  MIB II e  Bridge MIB id  RFC2819 f The CPU interface supports: n  Autocast MIB counters after half-full o  Autocast MIB counters after timeout  Autocast MIB counters when requested C  Clearing all MIB counters s Table 3-30 describes the statistics counter for each port. ro Table 3-30 MIB counters e Counter h RxBroad At RxPause Width 32-bit 32-bit Offset 0x00 0x04 Description The number of good broadcast frames received The number of pause frames received RxMulti 32-bit 0x08 The number of good multicast frames received RxFcsErr m32-bit 0x0c The total number of frames received with a valid length, but an invalid FCS and an integral number of octets RxAllignErr 32-bit m RxUndersize 32-bit o RxFragment 32-bit lcRx64Byte 32-bit uaRx128Byte 32-bit Q Rx256Byte 32-bit 0x10 0x14 0x18 0x1C 0x20 0x24 The total number of frames received with a valid length that do not have an integral number of octets and an invalid FCS The number of frames received that are less than 64 bytes long and have a good FCS The number of frames received that are less than 64 bytes long and have a bad FCS The number of frames received that are exactly 64 bytes long, including those with errors The number of frames received whose length is between 65 and 127 bytes, including those with errors The number of The number of frames received whose length is between 128 and 255 bytes, including those with errors Rx512Byte 32-bit 0x28 The number of frames received whose length is between 256 and 511 bytes, including those with errors 80-Y0619-1 Rev. A 56 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-30 MIB counters (cont.) Counter Width Offset Description Rx1024Byte Rx1518Byte RxMaxByte RxTooLong RxGoodByte RXBadByte RxOverFlow Filtered TxBroad TxPause TxMulti TxUnderRun Tx64Byte Tx128Byte Tx256Byte Tx512Byte 32-bit 32-bit 32-bit 32-bit 64-bit 64-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 0x2C 0x30 ial 0x34 t 0x38 en 0x3C 0x40 id 0x44 f 0x48 n 0x4C 0x50 o 0x54 C 0x58 0x5C s 0x60 ro 0x64 e 0x68 th 0x6C A0x70 The number of frames received whose length is between 512 and 1023 bytes, including those with errors The number of frames received whose length is between 1024 and 1518 bytes, including those with errors The number of frames received whose length is between 1519 and max length, including those with errors (jumbo) The number of frames received whose length exceeds max length, including those with FCS errors Total data octets received in a frame with a valid FCS. All frame sizes are included. Total data octets received in frame with and invalid FCS. All frame sizes are included. Pause frame is included with a valid FCS Total valid frames received that are discarded due to lack of buffer space Port disabled and unknown VID Total good frames transmitted with a broadcast destination address Total good PAUSE frames transmitted Total good frames transmitted with a multicast destination address Total valid frames discarded that were not transmitted due to transmit FIFO buffer underflow Total frames transmitted with a length of exactly 64 bytes, including errors Total frames transmitted with a length between 65 and 127 bytes, including those with errors Total frames truncated with a length between 128 and 255 bytes, including those with errors Total frames truncated with a length between 256 and 511 bytes, including Tx1024Byte m32-bit 0x74 Tx1518Byte 32-bit m TxMaxByte 32-bit lco TxOverSize TxByte 32-bit 64-bit uaTxCollision Q TxAbortCol 32-bit 32-bit 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90 those with errors Total frames truncated with a length between 512 and 1023 bytes, including those with errors Total frames transmitted with length between 1024 and 1518, including those with errors (jumbo) Total frames transmitted with length between 1519 and Maxlength, including those with errors (jumbo) Total frames over Maxlength but transmitted truncated with bad FCS Total data octets transmitted from counted, including those with a bad FCS Total collisions experienced by a port during packet transmission Total number of frames not transmitted because the frame experienced 16 transmission attempts and is discarded TxMultiCol 32-bit 0x94 Total number of successfully transmitted frames that experienced more than one collision TxSingleCol 32-bit 0x98 Total number of successfully transmitted frames that experienced exactly one collision 80-Y0619-1 Rev. A 57 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-30 MIB counters (cont.) Counter Width Offset Description 3.8 TxExcDefer TxDefer l TXLateCol tia RXUnicast n TXunicast 32-bit 32-bit 32-bit 32-bit 32-bit 0x9C 0xA0 0xA4 0xA8 0xAC The number of frames that deferred for an excessive period of time Total frames whose transmission was delayed on its first attempt because the medium way is busy Total number of times a collision is detected later than 512 bit times into the transmission of a frame Total number of received good unicast frame Total number of transmitted good unicast frame ide LED control f There are totally six LED control rules. Three of them are used to control the LEDs of PHY 0 to n PHY 3. The others are used to control the LEDs of PHY4. Each port has three LEDs. The default behaviors of the LEDs are 1000_LINK_ACTIVITY, 100_LINK_ACTIVITY and 10_LINK_ o ACTIVITY. C The LED output is open-drain output, so two or three of them can be connected together to indicate OR operation of the original LEDs. To achieve this operation, another method is to s modify the LED control register. These LEDs also can be individually configured On or Off by register. ro Each LED can be controlled by the 16 bits shown in Table 3-31. he Table 3-31 LED control t Bits Name A 15:14 PATTERN_EN 00 = LED always off Description 01 = LED blinking at 4 Hz 10 = LED always on m 11 = LED controlled by the following bits 13 FULL_LIGHT_EN 1 = LED lights when link up in full-duplex m 12 HALF_LIGHT_EN 1 = LED lights when link up in half-duplex o11 POWER_ON_LIGHT_EN 1 = Module should enter POWER_ON_RESET status after reset. lc10 LINK_1000M_LIGHT_EN 1 = LED lights when link up at 1000 Mbps 9 LINK_100M_LIGHT_EN 1 = LED lights when link up at 100 Mbps a 8 LINK_10M_LIGHT_EN 1 = LED lights when link up at 10 Mbps u 7 COL_BLINK_EN 1 = LED blinks when collision is detected Q 6 RESERVED Must be set to 0. 5 RX_BLINK_EN 1 = LED blinks when receiving frame 4 TX_BLINK_EN 1 = LED blinks when transmitting frame 3 RESERVED Must be set to 0. 80-Y0619-1 Rev. A 58 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-31 LED control (cont.) Bits Name Description 2 LINKUP_OVER_EN ential 1:0 LED_BLINK_FREQ 0 = RX/TX blinking ignores the linkup speed. 1 = RX/TX blinking should check with linkup speed, Linkup LED is ON, allow blinking; otherwise, Off. LED blink frequency select: 00 = 2 Hz 01 = 4 Hz 10 = 8 Hz 11 = If link up at 1000Mbps, use 8 Hz. If link up at 100Mbps, use 4 Hz. If link up at 10 Mbps, use 2 Hz. id Table 3-32 LED rule default value f Bits on 15:14 C 13 12 s 11 o 10 r 9 e 8 h 7 t 6 A 5 Name Default Value PATTERN_EN FULL_LIGHT_EN HALF_LIGHT_EN POWER_ON_LIGHT_EN LINK_1000M_LIGHT_EN LINK_100M_LIGHT_EN LINK_10M_LIGHT_EN COL_BLINK_EN RESERVED RX_BLINK_EN LED_RULE_0/1 LED_RULE_2/3 LED_RULE_4/5 0xCC35 0xCA35 0xC935 11 11 11 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 4 3 m TX_BLINK_EN RESERVED 1 1 1 0 0 0 2 LINKUP_OVER_EN m 1:0 LED_BLINK_RFREQ 1 01: 4 Hz 1 01: 4 Hz 1 01: 4 Hz lco 3.9 EEPROM programming format aFigure 3-2 shows the EEPROM programming format. Note that the last register should be at Qu address 0, and the LOAD_EEPROM bit is written to 0 to stop loading EEPROM state machine. 80-Y0619-1 Rev. A 59 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 0 Code 1 Checksum[15:0] l 2 ia High address 1 10'b0 High address[4:0] ent Switch register 4'b0 Address [13:2] Data[15:0] Data[31:16] id Figure 3-2 EEPROM programming format onf 3.10 MDC/MDIO access Figure 3-3 shows the detail format and procedure to access the internal register by MDC/MDIO. C Basically, there are two steps to access the register. s  Write the high address. This step can be omitted if the high address is unchanged. o  Read or write the register data. It is allowed to access 16-bit data once instead of twice if the r upper or lower 16-bit data is unchanged. When the operation code is B10 for write operation Athe and 01B for read operation. Qualcomm 80-Y0619-1 Rev. A 60 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Standard MDIO access format S TOP PHY REG TA DATA 16b tial Write high address Operation code = 01 (write) Register address of register A[18:0] A 1 8 A 1 7 A 1 6 A 1 5 AA 11 43 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 en 0 1 0 1 1 1 0 0 0 0 0 0 0 0 T A 0 0 0 0 0 0 A 1 8 A 1 7 A 1 6 A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 id Read/write data f Operation code is read or write on 0 1 OP 1 0 A 8 A 7 A 6 A 5 A 4 A 4 A 3 A 2 0 T A D 1 5 DD 11 43 DD 11 21 D 1 0 D 9 D 8 D 7 D 6 DDDDDD 543210 s C 0 1 O P 1 0 A 8 A 7 A 6 A 5 A 4 A 4 A 3 A 2 1 T A D 3 1 D 3 0 D 2 9 D 2 8 D 2 7 D 2 6 D 2 5 D 2 4 D 2 3 D 2 2 D 2 1 D 2 0 D 1 9 D 1 8 D 1 7 D 1 6 roConstruct 32-bit data from two 16-bit data e D h 3 t 1 D 3 0 D 2 9 D 2 8 D 2 7 D 2 6 D 2 5 D 2 4 D 2 3 D 2 2 D 2 1 D 2 0 D 1 9 D 1 8 D 1 7 D 1 6 D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A Figure 3-3 MDC/MDIO access format m 3.11 IEEE 802.3az and energy efficient Ethernet m IEEE 802.3az provides a mechanism to greatly save the power consumption during data packets burst. The link partners enter low power idle state by sending short refresh signals to maintain the o link. lcThere are two operating states: active state for normal data transfer, and low-power state during data packet bursts. aIn the low-power state, the QCA8334 shuts off most of the analog and digital blocks to conserve u energy. Due to the bursty traffic nature of Ethernet, system stays in low-power mode for most of Q the time, thus the power saving can be more than 90%. At the link start up, both link partners exchange information via auto-negotiation to determine if both parties are capable of entering LPI mode. Legacy Ethernet products are supported, and this is made transparent to the user. 80-Y0619-1 Rev. A 61 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description 3.11.1 IEEE 802.3az LPI mode QCA8334 works in the following modes when 802.3az feature is turned on:  Active: The regular mode to transfer data  Sleep: Send special signal to inform remote link of entry into low-power state l  Quiet: No signal transmitted on media. Most of the analog and digital blocks are turned off to ia reduce energy. t  Refresh: Send periodically special training signal to maintain timing recovery and equalizer n coefficients e  Wake: Send special wake-up signal to remote link to inform of the entry back into active. id The QCA8334 supports both 1000BASE-Tx EEE and 1000BASE-T EEE. f 100BASE-Tx EEE requires asymmetrical operation, meaning each link partner to enter the LPI mode independent of the other partner. n 1000BASE-T EEE requires symmetrical operation, meaning both link partners must enter the LPI o mode simultaneously. C Figure 3-4 shows the 802.3az operating power modes—802.3az for the QCA8334. s Td Ts Tq Tr Tw Active Wake Refresh Refresh Sleep Active Athero Active Quiet Quiet Quiet Low-Power Active Figure 3-4 m Operating power modes—802.3az LIP mode 3.12 Memory map om Table 3-33 Memory map lc Offset range 0x00000–0x000FF a 0x00100–0x00AFF u 0x00200–0x003FF Q 0x00400–0x005FF Global register EEE register Parser register ACL register Register sets 0x00600–0x007FF Lookup register 0x00800–0x00BFF QM register 0x00C00–0x00DFF PKT edit register 80-Y0619-1 Rev. A 62 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Functional Description Table 3-33 Memory map (cont.) Offset range Register sets 0x00E00–0x00FFF 0x01000–0x010A7 l 0x01200–0x012A7 ia 0x01300–0x013A7 t 0x01600–0x016A7 0x02000–0x0207F n 0x02100–0x021FF e 0x02200–0x022FF id 0x1C000–0x1C0FF f 0x2A000–0x2A03F n 0x3C000–0x3C1FF 0x58000–0x58FFF o 0x59000–0x59FFF C 0x5A000–0x5A7FF 0x5AA00–0x5AAFF s 0x5A900–0x5A97F o 0x5AC00–0x5ADFF r 0x5AE00–0x5AEFF Athe 0x5F000–0x5F03F Offload register Port 0 MIB counter Port 2 MIB counter Port 3 MIB counter Port 6 MIB counter Router MAC Public IP PPPoE session ACL match counter Public IP Reserved MAC address ACL rule ACL mask ACL action Public IP Router MAC VLAN translation table Egress queue remap table PPPoE session Qualcomm 80-Y0619-1 Rev. A 63 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 4 4.1 4.2 Electrical Characteristics tial Absolute maximum ratings en Operation in conditions beyond the absolute maximum ratings can cause permanent damage or adversely affect the long-term reliability of the device; such conditions must be avoided. fid Table 4-1 Absolute maximum ratings n Symbol Parameter Max. Unit o DVDD 1.2 V digital power supply for core 1.6 V AVDD 1.2 V analog power supply for core 1.6 V C DVDD27 2.7 V digital power supply for core 3.0 V s AVDD33 3.3 V analog power supply for core 4.0 V Tstore Storage temperature1 -65 to 150 °C ro HBM ESD human body model ±2 kV e CDM ESC charge device model TBD V 1. The storage temperature is the case surface temperature measured on the center top side of the chip. Ath Recommended operating conditions m Table 4-2 lists the recommended operating conditions for the QCA8334. Table 4-2 Recommended operating conditions m Symbol o DVDD lcAVDD aDVDD27 u AVDD33 Q TA Parameter 1.2 V digital power supply for core 1.2 V analog power supply for core 2.7 V digital power supply for core 3.3 V analog power supply for core Ambient temperature (commercial) Min Typ Max Unit 1.14 1.20 1.26 V 1.14 1.20 1.26 V 2.57 2.70 2.83 V 3.14 3.30 3.46 V – 25 – °C TJ-OPER Junction temperature 0 – 120 °C ψJT Junction to top of package temperature – 2.1 – °C/W 80-Y0619-1 Rev. A 64 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics 4.3 Power consumption This section provides power consumption at typical operation supply. 4.4 DVDD/AVDD = 1.2 V; AVDD33 = 3.3 V; TA = 25 °C l Table 4-3 describes typical power drain on each of the on-chip power supply domains as a function ia of the QCA8334’s operating mode. t Table 4-3 Total system power (1000BASE-T) n Link type Link status e No link id 1000M Two ports active f One ports active n 100M Two ports active One ports active o 10M Two ports active C One ports active 1000MF All ports 802.3az active s 100MF All ports 802.3az active 3.3 V (mA) 26 126 76 51 38 60 24 38 33 1.2 V (mA) 42 264 148 90 66 50 44 70 60 Power consumption (W) 0.1362 0.7326 0.4284 0.2763 0.2046 0.258 0.132 0.2094 0.1809 ero SerDes and SGMII characteristics Ath Table 4-4 shows the driver DC characteristics. Table 4-4 Driver DC characteristics Symbol Parameter m Voh Output voltage high Vol Output voltage low m Vring Output ringing o |Vod| Output differential voltage lcVos Output offset voltage Ro Output impedance (single-ended) 50 Ohm termination a Output impedance (single-ended) 75 Ohm termination u Delta Ro Mismatch in a pair Q Delta VOD Change in VOD between “0” and “1” Min Typ Max Unit – 950 1050 mV 500 650 – mV – – 10 % Programmable 300 (default) mV 750 800 850 mV 40 50 60 Ohm 60 75 90 Ohm – – 10 % – – 25 mV Delta Vos Change in VOS between “0” and “1” – – 25 mV Isa,Isb Output current on short to GND – – 40 mA Isab Output current when a, b are shorted – – 12 mA 80-Y0619-1 Rev. A 65 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics Table 4-4 Driver DC characteristics (cont.) Symbol Parameter Min Typ Max Unit Ixa,Ixb Power off leakage current – – Output differential voltage can be configured by SGMII_CTRL register 0x00e0 bits[12:10]. l Table 4-5 shows the receiver DC characteristics. 10 mA tia Table 4-5 Receiver DC characteristics n Symbol Parameter e Vio Internal offset voltage id Vih Input single voltage high f Vil Input single voltage low Vidth Input differential threshold n Vhyst Input differential hysteresis o Rin Receiver differential input impedance 50 Ohm termination C Receiver differential input impedance 75 Ohm termination s Table 4-6 shows the driver AC characteristics. Min Typ Max Unit 730 825 930 mV – 1050 1150 mV 500 600 – mV -50 – +50 mV 25 – – mV 80 100 120 Ohm 120 150 180 Ohm ro Table 4-6 Driver AC characteristics e Symbol Parameter h tfall Vod fall time (20%-80%) t trise Vod rise time (20%-80%) A Tskew Skew1 between two members of a differential pair Min Max Unit 100 200 ps 100 200 ps – 20 ps m 1. Skew measured at 50% of the transition. 4.5 Power-on strapping m Table 4-7 lists the power-on strapping configurations. lco Table 4-7 Power-on-strapping a Pin name RXD0_0 Qu RXD1_0 QFN 53 54 Power-on configuration Description SPI_EN 0 = No EEPROM connected 1 = EEPROM connected SPI_SIZE 0 = 1K 1 = 4K or 2K RXD2_0 56 LED_OPEN_EN 0 = Driver 1 = Open drain 80-Y0619-1 Rev. A 66 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics Table 4-7 Power-on-strapping (cont.) Pin name QFN Power-on configuration Description RXD3_0 57 CABLE_DIAG 0 = Disable power-on cable diagnostic 1 = Enable power-on cable diagnostic l SPI_DO 44 MDIO_EN 0 = UART interface 1 = MDC/MDIO interface ia RXDV_0 nfident INTn 51 CONTROL_DAC_HW0 11 = Follow DSP setting (default); the maximum 81 CONTROL_DAC_HW1 power is high for cable > 110 m; 10 = Bypass half_amp; set real_half_amp =0; follow DSP half_bias setting. Lose half amplitude capability with short cable and the maximum power is high for cable > 100 m; 01 = Half amplitude follow DSP, bypass half_ bias; set real_half_bias = 1; Use half amplitude capability with short cable and the power = 100m or >110m cable; 00 = Everything is full no matter the cable length. This gives the worse power. o POS_SWREG 72 SWR_SEL 0 = Use external 1.2 V regulator 1 = 1.2 V s C 4.6 DC electrical specifications ro This section lists the general DC electrical characteristics under typical voltage input unless e otherwise specified. th 4.6.1 RGMII DC electrical specification A Table 4-8 describes RGMII DC electrical specification. m Table 4-8 2.5V digital I/O DC characteristics Symbol Parameter Min m VIH Input high level 1.7 o VIL Input low level – lcVOH Output high level 2.2 VOL Output low level – aIIH Input high current – Qu IIL Input low current 0.4 Max 3.6 0.7 – 0.4 -0.4 – Unit V V V V mA mA 80-Y0619-1 Rev. A 67 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics Table 4-9 RGMII DC characteristics under 1.8V/1.5V Symbol Parameter Min Max Unit VIH Input high level 0.75 * VDD1 – V l VIL Input low level – 0.25 * VDD V ia VOH Output high level 0.8 * VDD – V t VOL Output low level – 0.2 * VDD V n 1. VDD is the I/O power 1.8V or 1.5V. ide 4.6.2 Power-on-reset timing f Figure 4-1 shows the power-on-reset timing diagram. Con DVDD/AVDD os 3.3 V power er RESET_L Ath XTLI 1.0 V 2.0 V >= 0 ns >= 10 ms < 2 ms m Figure 4-1 Power-on-reset timing diagram m 4.7 AC electrical specifications o This section lists the AC electrical characteristics under typical voltage unless otherwise specified. alc 4.7.1 XTLI characteristics Qu Figure 4-2 shows the XTLI timing diagram when using external clock input. 80-Y0619-1 Rev. A 68 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics tXI_PER tXI_HI tXI_LO tial vIH_XI n vIL_XI ide tXI_RISE tXI_FALL f Figure 4-2 XTLI timing diagram on Table 4-10 External clock input characteristics C Symbol Parameter tXI_PER XI/OSCI clock period s tXI_HI XI/OSCI clock high ro tXI_LO XI/OSCI clock low e tXI_RISE XI/OSCI clock rise time, VIL (max) to VIH (min) tXI_FALL XI/OSCI clock fall time, VIL (max) to VIH (min) th vIH_XI XTLI input high level voltage A vIL_XI XTLI input low level voltage Min Typ Max Unit 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns 14 20.0 – ns 14 20.0 – ns – – 4 ns – – 4 ns 0.8 – 1.4 V -0.3 – 0.15 V m Table 4-11 Recommended crystal parameters Symbol Parameter m Ff Crystal fundamental frequency o Fs Frequency stability over operating temperature at 0–70°C lcFt Frequency tolerance at 25°C Fo Oscillation frequency aCs Shunt capacitance u Cl Load capacitance Q Vo I/O voltage level (for driver level evaluation) Min Typ Max Unit – 25 – MHz -30 ppm – +30 ppm MHz -30 ppm – +30 ppm MHz -50 ppm – +50 ppm MHz – 7 – pF – 15 – pF – 1.2 – V DL Driver level – 300 – μW ESR Equivalent series resistance – 30 50 Ω 80-Y0619-1 Rev. A 69 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics 4.7.2 MII timing Figure 4-3 shows the MII timing diagram. tmiick ial TXCLK/RXCLK t ttxsu n TXEN TXD[3:0] ide trxdly RXDV f RXD[3:0] n Figure 4-3 MII timing diagram ttxhold Co Table 4-12 MII timing parameter Symbol Parameter Min Typ Max Unit s tmiick TXCLK/RXCLK period – 40 – ns o ttxsu TXEN and TXD to TXCLK rising setup 10 – – ns r ttxhold TXEN and TXD to TXCLK rising hold 10 – – ns e trxdly RXCLK falling to RXDV, and RXD output delay 0 – 8 ns Ath 4.7.3 RMII timing m Figure 4-4 shows the RMI timing diagram. m RXCLK_0 lcoTXEN_0 TXD[1:0]_0 ua RXDV_0 Q RXD[1:0]_0 tclk tsu thold tdly Figure 4-4 RMII timing 80-Y0619-1 Rev. A 70 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics Table 4-13 RMII timing parameter Symbol Parameter Min tck REFCLK period – l tsu TXEN and TXD to RXCLK_0 rising setup time 4 ia thold TXEN and TXD to RXCLK_0 rising hold time 2 t tdly RXCLK_0 to RX_DV, and RXD output delay 3 en 4.7.4 RGMII timing id Figure 4-5 shows the RGMII timing diagram. nf At receiver (PHY mode) o GTXCLK C TXCTL s TXD[3:0] o At transmitter (PHY mode) r RXCLK the RXCTL A RXD[3:0] TskewR TskewT Type 20 – – – Max Unit – ns – ns – ns 14 ns m Figure 4-5 RGMII timing diagram Table 4-14 RGMII timing parameter m Symbol TskewT o TskewR Parameter Data to clock output skew Data to clock input skew alc 4.7.5 SPI timing Qu Figure 4-6 shows the SPI timing diagram. Min Typ Max Unit -0.5 – 0.5 ns 1 – 2.6 ns 80-Y0619-1 Rev. A 71 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics SPI_CS tspil SPI_CLK ial SPI_DO tdodly tspih t SPI_DI en Figure 4-6 EEPROM interface timing diagram id Table 4-15 EEPROM interface timing nf Symbol Parameter o tspick tspil C tspih s tdisu o tdihold r tdodly SPI_CLK period SPI_CLK low period SPI_CLK high period SPI_DI to SPI_CLK rising setup time SPI_DI to SPI_CLK rising hold time SPI_CLK falling to SPI_DO output delay time the 4.7.6 MDIO timing A Figure 4-7 shows the MDIO timing diagram. tspick tdisu Min Typ – – – – – – 10 – 10 – – – tdihold Max Unit – ns – ns – ns – ns – ns 20 ns mtmdc m MDC lco MDIO tmdch tmdcl tmdsu tmdhold QuaFigure 4-7 MDIO timing diagram 80-Y0619-1 Rev. A 72 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Electrical Characteristics Table 4-16 MDIO timing Symbol tmdc tmdcl tmdch tmdsu tmdhold Parameter Min Typ Max Unit MDC period 100 – – ns l MDC low period 40 – – ns ia MDC high period 40 – – ns t MDIO to MDC rising setup time 10 – – ns Atheros Confiden MDIO to MDC rising hold time 10 – – ns Qualcomm 80-Y0619-1 Rev. A 73 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 5 5.1 Register Description ntial The register bit types include: e Register field with latching high function. If status is high, then the register is set to a one and id LH remains set until a read operation is performed through the management interface or a reset occurs. f Register field with latching low function. If status is low, then the register is cleared to a zero and n LL remains cleared until a read operation is performed through the management interface or a reset occurs. o Retain Register value holds. C SC Self-Clear. Writing a one to this register causes the desired function to be immediately executed, then the register field is cleared to zero when the function is complete. os Update Value written to the register field does not take effect until a software reset is executed. The register bits can be read after write operation. r RO Read only e R/W Read/Write Ath Register address space (offset range: 0x0000–0x0E98) m Table 5-1 summarizes address space occupied by the registers. m Table 5-1 Register address space summary Offset range o0x0000–0x00E0 lc0x0100–0x0168 a 0x0200–0x0270 0x0400–0x0454 Qu 0x0600–0x0718 Name “Global control registers” on page 75 “EEE control registers” on page 100 “Parser control registers” on page 103 “ACL control registers” on page 113 “Lookup control registers” on page 122 0x0800–0x0B70 “QM control registers” on page 154 0x0C00–0x0C80 “PKT edit control registers” on page 235 0x00–0x1E “PHY control registers” on page 242 80-Y0619-1 Rev. A 74 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.2 Global control registers Table 5-2 summarizes the global control registers. Table 5-2 Global control registers summary l Offset range ia 0x0000 t 0x0004 n 0x000C e 0x0010 id 0x0020–0x0024 0x0028–0x002C f 0x0030 n 0x0034 o 0x0038 C 0x003C 0x0040 s 0x0044 o 0x0048 r 0x0050–0x005C e 0x0060–0x0064 h 0x0078 t 0x007C A 0x0084 Mask control register Port 0 pad mode control register Port 6 pad mode control register Power-on-strapping register Global interrupt register Global interrupt mask register Module enable control register MIB function register Interface high address register MDIO master control register BIST control register BIST recover register Service tag register LED control register Global MAC address Maximum frame size register Port0 status register Port2 status register Name 0x0088 0x0094 mPort3 status register Port6 status register 0x0098 0x009C m 0x00A4 o0x00A8 lc0x00B4 0x00E0 Header control register Port0 header control register Port2 header control register Port3 header control register Port6 header control register SGMII control register Qua5.2.1 MASK_CTRL Address offset: 0x0000 Table 5-3 summarizes the mask control register. 80-Y0619-1 Rev. A 75 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-3 MASK_CTRL bit description Bits R/W Initial value Mnemonic Description 31 W/SC ial 30:17 RO t 16 R/W en 15:8 RO 7:0 RO 0 0 0 0x13 0x01 SOFT_RET 1 = Software reset This bit is set by the software to initiate the hardware. It is self-cleared by the hardware after the initialization is done. RESERVED LOAD_EEPROM Load EEPROM enable. This bit is set to automatically load registers from EEPROM. It is cleared after the loading is complete. DEVICE_ID Device identifier REV_ID Revision identifier nfid 5.2.2 PORT0_PAD_CTRL o Address offset: 0x0004 C Table 5-4 summarizes the port 0 pad mode control register. s Table 5-4 PORT0_PAD_CTRL bit description o Bits R/W Initial value Mnemonic r 31 R/W 0 MAC06_EXCHANGE_EN e 30 R/W 0 MAC0_M_RMII_EN h 29 R/W 0 MAC0_S_RMII_EN t 28 R/W 0 MAC0_RMII_SEL A 27 R/W 0 MAC0_RMII_PIPE_RXCLK_SEL Description Exchange MAC0 and MAC6 RMII master RMII slave RMII clock inverse RMII clock edge for rxpipe 26 R/W 0 MAC0_RGMII_EN 1 = MAC0 connected to CPU through RGMII interface m 25 R/W 0 MAC0_RGMII_TXCLK_DELAY_EN 1 = RGMII interface TXCLK (input from CPU) is delayed. m Delay value depends on bits[23:22]. 24 R/W 0 Reserved o 23:22 R/W 0 MAC0_RGMII_TXCLK_DELAY_SEL Control the delay value of RGMII lc interface TXCLK. 11 = maximum delay a21:20 R/W 0 MAC0_RGMII_RXCLK_DELAY_SEL Control the delay value of RGMII interface RXCLK. u 11 = maximum delay Q 19 R/W 0 SGMII_CLK125M_RX_SEL Configure the receive clock phase for MAC interface and must be set when using SerDes or SGMII module. 0 = Rising edge 1 = Falling edge 80-Y0619-1 Rev. A 76 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-4 PORT0_PAD_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 18 R/W 17 R/W 16 R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l SGMII_CLK125M_TX_SEL Configure the transmit clock phase for SerDes interface 0 = Rising edge 1 = Falling edge ia FX100_EN Enable 100BASE-FX interface t RESERVED n RESERVED e MAC0_PHY_GMII_EN 1 = MAC0 connected to CPU through GMII interface, PHY mode id MAC0_PHY_GMII_TXCLK_SEL 1 = Select invert clock input for port0 PHY mode, GMII interface TXCLK nf MAC0_PHY_GMII_RXCLK_SEL 1 = Select invert clock output for port0 PHY mode, GMII interface RXCLK MAC0_PHY_MII_PIPE_RXCLK_SEL 1 = Select clock edge for rxpipe; default ois invert. C MAC0_PHY_MII_EN 1 = MAC0 connected to CPU through MII interface, PHY mode s MAC0_PHY_MII_TXCLK_SEL 1 = Select invert clock output for port0 PHY mode, MII interface TXCLK ro MAC0_PHY_MII_RXCLK_SEL 1 = Select invert clock output for port0 PHY mode, MII interface RXCLK e MAC0_SGMII_EN Enable SGMII interface h MAC0_MAC_GMII_EN 1 = MAC0 connected to CPU through GMII interface, MAC mode. At MAC0_MAC_GMII_TXCLK_SEL 1 = Select invert clock output for port0 MAC mode, GMII interface TXCLK 4 R/W m0 MAC0_MAC_GMII_RXCLK_SEL 3 RO 0 RESERVED 2 R/W 0 MAC0_MAC_MII_EN om 1 R/W 0 MAC0_MAC_MII_TXCLK_SEL lc0 R/W 0 MAC0_MAC_MII_RXCLK_SEL Qua5.2.3 PORT5_PAD_CTRL Address offset: 0x0008 1 = Select invert clock input for port0 MAC mode, GMII interface RXCLK 1 = MAC0 connected to CPU through MII interface, MAC mode 1 = Select invert clock input for port0 MAC mode, MII interface TXCLK 1 = Select invert clock input for port0 MAC mode, MII interface RXCLK Table 5-5 summarizes the port 5 pad mode control register. 80-Y0619-1 Rev. A 77 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-5 PORT5_PAD_CTRL bit description Bits R/W Initial value Mnemonic Description 31:27 RO 26 R/W 25 R/W 24 R/W 23:22 R/W 21:20 R/W 19:12 RO 11 R/W 10 R/W 9 R/W 0 0 0 0 0 0 0 0 0 0 RESERVED l MAC5_RGMII_EN 1 = MAC5 connected to CPU through RGMII interface tia MAC5_RGMII_TXCLK_DELAY_EN 1 = CPU RGMII interface TXCLK (input from CPU) is delayed. Delay value depends on bits[23:22]. fiden MAC_RGMII_RXCLK_DELAY_EN This bit controls all RGMII interface (MAC0, MAC5 and MAC6) 1 = RGMII interface RXCLK is delayed. 1000M = Delay 2 ns output to CPU 10M/100M: Delay value depends on bits[21:20]. n MAC5_RGMII_TXCLK_DELAY_SEL Control the delay value of RGMII interface TXCLK. o11 = maximum delay C MAC5_RGMII_RXCLK_DELAY_SEL Control the delay value of RGMII interface RXCLK. 11 = maximum delay s RESERVED o MAC5_PHY_MII_PIPE_RXCLK_SEL 1 = Select clock edge for rxpipe. Default r is invert. e MAC5_PHY_MII_EN 1 = MAC5 connected to CPU through MII interface, PHY mode Ath MAC5_PHY_MII_TXCLK_SEL 1 = Select invert clock output for port5 PHY mode, MII interface TXCLK 8 R/W 0 MAC5_PHY_MII_RXCLK_SEL 1 = Select invert clock output for port5 7:3 R/W m0 RESERVED PHY mode, MII interface RXCLK 2 R/W 0 MAC5_MAC_MII_EN m 1 R/W 0 MAC5_MAC_MII_TXCLK_SEL o0 R/W 0 MAC5_MAC_MII_RXCLK_SEL ualc 5.2.4 PORT6_PAD_CTRL Q Address offset: 0x000C 1 = MAC5 connected to CPU through MII interface, MAC mode 1 = Select invert clock input for port5 MAC mode, MII interface TXCLK 1 = Select invert clock input for port5 MAC mode, MII interface RXCLK Table 5-6 summarizes the port 6 pad mode control register. 80-Y0619-1 Rev. A 78 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-6 PORT6_PAD_CTRL bit description Bits R/W Initial value Mnemonic Description 31:27 RO 26 R/W 25 R/W 24 R/W 23:22 R/W 21:20 R/W 19:18 RO 17 R/W 16:12 RO 11 R/W 10 R/W 9 R/W 8 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED l MAC6_RGMII_EN 1 = MAC6 connected to CPU through RGMII interface tia MAC6_RGMII_TXCLK_DELAY_EN 1 = RGMII interface TXCLK (input from CPU) is delayed. Delay value depends on bits[23:22]. n Reserved e MAC6_RGMII_TXCLK_DELAY_SEL Control the delay value of RGMII interface TXCLK. id 11 = maximum delay f MAC6_RGMII_RXCLK_DELAY_SEL Control the delay value of RGMII interface RXCLK. n 11 = maximum delay o RESERVED C PHY4_RGMII_EN 1 = PHY4 connected to CPU through RGMII interface. RESRVED s MAC6_PHY_MII_PIPE_RXCLK_SEL 1 = Select clock edge for rxpipe. Default o is invert. er MAC6_PHY_MII_EN 1 = MAC6 connected to CPU through MII interface, PHY mode. h MAC6_PHY_MII_TXCLK_SEL 1 = Select invert clock output for port6 PHY mode, MII interface TXCLK. At MAC6_PHY_MII_RXCLK_SEL 1 = Select invert clock output for port6 PHY mode, MII interface RXCLK. 7 R/W 6:3 RO m0 MAC6_SGMII_EN 0 RESERVED 2 R/W 0 MAC6_MAC_MII_EN m 1 R/W 0 MAC6_MAC_MII_TXCLK_SEL o0 R/W 0 MAC6_MAC_MII_RXCLK_SEL ualc 5.2.5 PWS_REG Q Address offset: 0x0010 1 = MAC6 connected to CPU through MII interface, MAC mode. 1 = Select invert clock input for port6 MAC mode, MII interface TXCLK. 1 = Select invert clock input for port6 MAC mode, MII interface RXCLK. Table 5-7 summarizes the power-on-strapping register. 80-Y0619-1 Rev. A 79 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-7 PWS_REG bit description Bits R/W Initial value Mnemonic Description 31 R/W 30:29 RO 28 R/W 27 R/W 26 R/W 25 R/W 24 R/W 23:22 R/W 21 R/W 20:19 R/W 18:17 R/W 16:13 R/W 12 R/W 11:10 R/W 9:8 R/W 7 R/W 6 R/W 5 R/W 0 0 0 0 0 0 0 0 1 0 3 0 1 0 3 0 0 1 POWER_ON_SEL Power-on-strapping select l RESERVED ia PACKAGEMIN_EN 1 = Select 88-pin package pinout INPUT_MODE 1 = GMII interface digital PAD work at input mode t RESERVED n SPI_EN_CSR 1 = EEPROM is connected to the switch e LED_OPEN_EN_CSR 0 = LED pad is in driver mode id 1 = LED pad is in open drain mode RESERVED f RESERVED n RESERVED o RESERVED RESERVED C RESERVED s RESERVED o RESERVED er SERDES_AEN SerDes auto-negotiation: 0 = Enable auto-negotiation 1 = Disable auto-negotiation h RESERVED At RESERVED 4:0 R/W 0 RESERVED m 5.2.6 GLOBAL_INT0 m Address offset: 0x0020 o Table 5-8 summarizes the global interrupt 0 register. lcTable 5-8 GLOBAL_INT0 bit description a Bits R/W Initial value Mnemonic u 31:30 RO 0 RESERVED Q 29 R/W1C 0 ACL_INI_INT Description Interrupt when ACL memory initial done. 28 R/W1C 0 LOOKUP_INI_INT Interrupt when address table initial done (including ARL, reserved ARL, VLAN). 27 R/W1C 0 QM_INI_INT Interrupt when QM memory initial done. 26 R/W1C 0 MIB_INI_INT Interrupt when MIB memory initial done. 80-Y0619-1 Rev. A 80 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-8 GLOBAL_INT0 bit description (cont.) Bits R/W Initial value Mnemonic Description 25 R/W1C 24 R/W1C 23 R/W1C 22 R/W1C 21 R/W1C 20 R/W1C 19 R/W1C 18 R/W1C 17 R/W1C 16 R/W1C 15:12 RO 11 R/W1C 10 R/W1C 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFLOAD_INI_INT HARDWARE_INI_DONE l ACL_MATCH_INT tia ARL_DONE_INT n ARL_CPU_FULL_INT ide VT_DONE_INT f MIB_DONE_INT n ACL_DONE_INT OFFLOAD_DONE_INT Co OFFLOAD_CPU_FULL_ DONE_INT s RESERVED o ARL_LEARN_CREATE_INT Ather ARL_LEARN_CHANGE_INT Interrupt when offload memory initial done. Interrupt when hardware memory initial done. Interrupt when ACL match (and ACL_ MATCH_INT_EN in ACL result is 1). Interrupt when address table access is done by CPU. Interrupt when CPU loads a new address in address table, but the address's two entries are all valid. VLAN table access is done by CPU. MIB access done by CPU. Interrupt when ACL access done by CPU Interrupt when offload table access done by CPU Interrupt when CPU load a new entry in HNAT table, but the offload's entries are all valid. Create new entry. ARL learn a new address: auto learn, add a new address to ARL. IGMP/MLD join a new entry: add new IGMP/MLD multicast entry to ARL Change an existing entry. ARL learn: auto learn, address exists. m m 9 R/W1C 0 alco8 R/W1C 0 Qu 7 RO 0 ARL_DELETE_INT ARL_LEARN_FULL_INT RESERVED Change to new port IGMP/MLD join new port: add source port to IGMP/MLD multicast entry IGMP/MLD leave port: one port remove from the IGMP/MLD entry Delete an existing entry Age: Age one entry from ARL (including UNI/MUL/IGMP…) IGMP/MLD leave port: one IGMP/MLD entry is removed from ARL Interrupt when learn a new address in address table, but the address's two entries are all valid. 6 R/W1C 0 NAPT_AGE_DELETE_INT NAPT age interrupt 5 R/W1C 0 ARP_LEARN_CREATE_INT Create new entry ARP learn a new address: auto learn, add a new address to ARP table 80-Y0619-1 Rev. A 81 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-8 GLOBAL_INT0 bit description (cont.) Bits R/W Initial value Mnemonic Description 4 R/W1C 0 ARP_LEARN_CHANGE_INT Change an existed entry ARP learn: auto learn, address exists. Change to new port l 3 R/W1C 0 ARP_AGE_DELETE_INT Interrupt when entry removed by hardware ia age t 2 R/W1C 0 ARP_LEARN_FULL_INT Interrupt when learning a new address in ARP table, but table is full. n 1 R/W1C 0 VT_MISS_VIO_INT Interrupt when the VID is not in VLAN table. e 0 R/W1C 0 VT_MEM_VIO_INT Interrupt when the VID is in VLAN table, but source port is not the member of the VID. fid 5.2.7 GLOBAL_INT1 n Address offset: 0x0024 o Table 5-9 summarizes the global interrupt 1 register. s C Table 5-9 GLOBAL_INT1 bit description o Bits R/W Initial value Mnemonic r 31:24 RO 0 RESERVED e 23:20 RO 0 RESERVED 19 R/W1C 0 THERM_INT th 18 R/W1C 0 EEPROM_ERR_INT A 17 R/W1C 0 EEPROM_INT Description Thermal meter input Interrupt when error occurs during load EEPROM Interrupt when EEPROM load done 16 R/W1C 15 R/W1C m0 0 MDIO_DONE_INT PHY_INT 14 R/W1C 0 QM_ERR_INT 13 R/W1C 0 LOOKUP_ERR_INT m 12 R/W1C 0 LOOP_CHECK_INT o11:8 RO 0 RESERVED lc7:1 R/W1C 0 LINK_CHG_INT_EN 0 R/W 0 BIST_DONE_INT Qua5.2.8 GLOBAL_INT0_MASK Address offset: 0x0028 MDIO access switch register done interrupt Physical layer interrupt Interrupt when QM detect error Interrupt when lookup detect error Interrupt when loop checked by hardware Link status change interrupt enable Interrupt when BIST done Table 5-10 summarizes the global interrupt 0 mask register. 80-Y0619-1 Rev. A 82 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-10 GLOBAL_INT0_MASK bit description Bits R/W Initial value Mnemonic Description 31:30 RO 29 R/W 28 R/W 27 R/W 26 R/W 25 R/W 24 R/W 23 R/W 22 R/W 21 R/W 20 R/W 19 R/W 18 R/W 17 R/W 16 R/W 15:12 R/W 11 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED l ACL_INI_INT_EN ia LOOKUP_INI_INT_EN t QM_INI_INT_EN n MIB_INI_INT_EN e OFFLOAD_INI_INT_EN id HARDWARE_INI_DONE_ EN f ACL_MATCH_INT_EN n ARL_DONE_INT_EN o ARL_CPU_FULL_INT_EN C VT_DONE_INT_EN s MIB_DONE_INT_EN ACL_DONE_INT_EN ro OFFLOAD_DONE_INT_EN OFFLOAD_CPU_FULL_ e DONE_INT_EN h RESERVED t ARL_LEARN_CREATE_ AINT_EN Enable interrupt when ACL memory initial done Enable interrupt when address table initial done (including ARL, reserved ARL, VLAN). Enable interrupt when QM memory initial done Enable interrupt when MIB memory initial done Enable interrupt when offload memory initial done Enable interrupt when hardware memory initial done Enable interrupt when ACL match Enable interrupt when address table access is done by CPU Enable interrupt for ARL_CPU_FULL_INT Enable interrupt for VT_DONE_INT Enable interrupt for MIB_DONE_INT Enable interrupt for ACL_DONE_INT Enable interrupt for OFFLOAD_DONE_INT Enable interrupt for OFFLOAD_CPU_FULL_ DONE_INT Enable interrupt for ARL_LEARN_CREATE_INT 10 R/W 0 ARL_LEARN_CHANGE_ INT_EN m 9 R/W 0 ARL_DELETE_INT_EN 8 R/W 0 ARL_LEARN_FULL_INT_ EN m 7 R/W 0 RESERVED o6 R/W 0 NAPT_AGE_DELETE_INT_ lc EN 5 R/W 0 ARP_LEARN_CREATE_ a INT_EN u 4 R/W 0 ARP_LEARN_CHANGE_ INT_EN Q 3 R/W 0 ARP_AGE_DELETE_INT_ EN Enable interrupt for ARL_LEARN_CHANGE_INT Enable interrupt for ARL_DELETE_INT Enable interrupt for ARL_LEARN_FULL_INT Enable interrupt for NAPT_AGE_DELETE_INT Enable interrupt for ARP_LEARN_CREATE_INT Enable interrupt for ARP_LEARN_CHANGE_INT Enable interrupt for ARP_AGE_DELETE_INT 2 R/W 0 ARP_LEARN_FULL_INT_ Enable interrupt for ARP_LEARN_FULL_INT EN 80-Y0619-1 Rev. A 83 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-10 GLOBAL_INT0_MASK bit description (cont.) Bits R/W Initial value Mnemonic Description 1 R/W 0 VT_MISS_VIO_INT_EN Enable interrupt for VT_MISS_VIO_INT 0 R/W 0 VT_MEM_VIO_INT_EN Enable interrupt for VT_MEM_VIO_INT ial 5.2.9 GLOBAL_INT1_MASK t Address offset: 0x002C n Table 5-11 summarizes the global interrupt 1 mask register. ide Table 5-11 GLOBAL_INT1_MASK bit description f Bits R/W Initial value Mnemonic n 31:24 RO 0 RESERVED o 23:20 RO 0 RESERVED 19 R/W 0 THERM_INT_EN C 18 R/W 0 EEPROM_ERR_INT_EN s 17 R/W 0 EEPROM_INT_EN 16 R/W 0 MDIO_DONE_INT_EN ro 15 R/W 0 PHY_INT_EN 14 R/W 0 QM_ERR_INT_EN e 13 R/W 0 LOOKUP_ERR_INT_EN th 12 R/W 0 LOOP_CHECK_INT_EN A 11:1 RO 0 RESERVED Description Thermal meter interrupt enable Enable interrupt for EEPROM_ERR_INT Enable interrupt for EEPROM_INT Enable interrupt for MDIO_DONE_INT Enable interrupt for PHY_INT Enable interrupt for QM_ERR_INT Enable interrupt for LOOKUP_ERR_INT Enable interrupt for LOOP_CHECK_INT 0 R/W m0 BIST_DONE_INT_EN Enable interrupt for BIST_DONE_INT 5.2.10 MODULE_EN m Address offset: 0x0030 o Table 5-12 summarizes the module enable register. lcTable 5-12 MODULE_EN bit description a Bits R/W Initial value Mnemonic u 31:11 RO 0 RESERVED Q 10 R/W 1 SPECIAL_DIP_EN Description Enable special DIP (224.0.0.x or ff02::1) broadcast 0 = Use multicast DP 1 = Use broadcast DP 9 R/W 1 RESERVED 80-Y0619-1 Rev. A 84 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-12 MODULE_EN bit description (cont.) Bits R/W Initial value Mnemonic Description 8 R/W 1 RESERVED 7:3 R/W 0 RESERVED l 2 R/W 0 L3_EN ia 1 R/W 0 ACL_EN t 0 R/W 0 MIB_EN 1 = Layer 3 offload enable 1 = ACL module enable 0 = MIB count disable 1 = MIB count enable en 5.2.11 MIB fid Address offset: 0x0034 n Table 5-13 summarizes the MIB function register. o Table 5-13 MIB bit description C Bits R/W Initial value Mnemonic Description 31:27 RO 0 RESERVED heros 26:24 R/W 0 MIB_FUNC 000 = No operation 001 = Flush all counters for all ports 010 = Flush all MIB counters of appointed port 011 = Capture all counters for all ports and auto-cast to CPU port 1xx = Reserved At 23:21 R/W 0 MIB_FLUSH_PORT Flush all MIB counters of this port 20 R/W 0 MIB_CPU_KEEP 0 = Clear MIB counter to 0 after read 19:18 RO m0 RESERVED 1 = Do not clear MIB counter after it has been read. 17 R/W SC 0 om 16 R/W 0 Qualc15:0 R/W 15’h0 MIB_BUSY 0 = MIB module is empty, and can access new command. 1 = MIB module is busy, and can not access another new command. MIB_AT_HALF_EN MIB auto-cast enable due to half flow. 1 = MIB is auto-cast when any counter's highest bit count to 1. MIB_TIMER MIB auto-cast timer. 0 = MIB does not auto-cast due to timer times out. The time is times of 8.4 ms; recommended value is 'h100. 5.2.12 INTERFACE_HIGH_ADDR Address offset: 0x0038 80-Y0619-1 Rev. A 85 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-14 summarizes the interface high address register. Table 5-14 INTERFACE_HIGH_ADDR bit description Bits R/W Initial value Mnemonic Description ial 31 RO 0 SPI_SPEED 0 = Normal operation mode 1 = Fast speed for test t 30:28 R/W 0 RESERVED en 27:24 R/W 0Xf RELOAD_TIMER Reload EEPROM timer If the EEPROM can not be read out, EEPROM is reloaded when the timer done. It's times 8 ms. 0 = No need to reload EEPROM id 23:20 R/W 0 RESERVED f 19 R/W 0 SGMII_CLK125M_RX_SEL SGMII interface Rx clock selection n 1 = Inverse clock 18 R/W 0 SGMII_CLK125M_TX_SEL SGMII interface Tx clock selection o 1 = Inverse clock C 17:10 R/W 0 RESERVED 9:0 R/W 0 RESERVED ros 5.2.13 MDIO master control e Address offset: 0x003C h Table 5-15 summarizes the MDIO master control register. At Table 5-15 MDIO master control bit description Bits R/W Initialvalue Mnemonic Description mm 31 R/W 0 MDIO_BUSY 1 = Internal MDIO interface is busy. This bit is set to 1 when CPU read or write PHY register through internal MDIO interface, and is cleared after hardware finish the command. o30 RO 0 MDIO_MASTER_EN 1 = Use MDIO master to configure PHY register. MDC is changed to internal MDC to PHY. lc29:28 R/W 0 RESERVED a 27 RO 0 MDIO_CMD 0 = Write 1 = Read u 26 R/W 0 MDIO_SUP_PRE 0 = With 32 bits preamble Q 1 = Suppress preamble enable 25:21 RO 0 PHY_ADDR PHY address 80-Y0619-1 Rev. A 86 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-15 MDIO master control bit description (cont.) Bits R/W Initialvalue Mnemonic Description 20:16 R/W 0 REG_ADDR l 15:0 R/W 0 MDIO_DATA PHY register address When write, these bits are data written to PHY register. When read, these bits are data read out from PHY register. tia 5.2.14 BIST_CTRL n Address offset: 0x0040 e Table 5-16 summarizes the BIST control register. fid Table 5-16 BIST_CTRL bit description n Bits R/W Initial value Mnemonic Description Co 31 R/W 0 BIST_BUSY This bit is written to 1 to begin BIST test and is cleared to 0 by hardware after test done. 0 = BIST done or idle 1 = BIST test os 30 RO 0 BIST_WITH_ONE_ERR 1 = BIST test one error in data memory and can be recovered. r 29 RO 0 BIST_PASS All memory is OK, or only one error in data memory. e 28:24 RO 0 RESERVED h 23 R/W 0 BIST_CRITICAL Enable critical pattern for BIST test t 22 R/W 1 BIST_PTN_EN_2 1 = Enable pattern 2 for BIST test A 21 R/W 1 BIST_PTN_EN_1 1 = Enable pattern 1 for BIST test 20 R/W 19:0 RO m1 BIST_PTN_EN_0 0 RESERVED 1 = Enable pattern 0 for BIST test m 5.2.15 BIST_RECOVER o Address offset: 0x0044 lcTable 5-17 summarizes the BIST recover register. uaTable 5-17 BIST_RECOVER bit description Q Bits R/W Initial value Mnemonic Description 31 R/W 0 BIST_RECOVER_EN 1 = Enable hardware recover data memory MBIST error. 30:13 RO 0 RESERVED 12:0 R/W 0 BIST_RECOVER_ADDR BIST test error address of memory. 80-Y0619-1 Rev. A 87 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.2.16 SERVICE_TAG Address offset: 0x0048 Table 5-18 summarizes the service tag register. l Table 5-18 SERVICE_TAG bit description ia Bits R/W Initial value Mnemonic t 31:18 R/W 0 RESERVED n 17 R/W 0 SWITCH_S-TAG_ e MODE id 16 RO nf 15:0 R/W 0 0x88A8 RESERVED SERVICE_TAG Description Select switch work VLAN mode. 0 = C-Tag mode 1 = S-Tag mode Identify the service tagged frame when core port is enabled. Co 5.2.17 LED_CTRL0 Address offset: 0x0050 s Table 5-19 summarizes the LED control 0 register. ro Table 5-19 LED_CTRL 0 bit description e Bits R/W th 31:16 R/W A 15:0 R/W Initial value 0xCC35 0xCC35 Mnemonic LED_CTRL_RULE_1 LED_CTRL_RULE_0 Description PHY4 LED0 control rule PHY0–PHY3 LED0 control rule m 5.2.18 LED_CTRL1 Address offset: 0x0054 m Table 5-20 summarizes the LED control 1 register. lco Table 5-20 LED_CTRL1 bit description Bits R/W a 31:16 R/W Qu 15:0 R/W Initial value 0xCA35 0xCA35 Mnemonic LED_CTRL_RULE_3 LED_CTRL_RULE_2 Description PHY4 LED1 control rule PHY0–PHY3 LED1 control rule 5.2.19 LED_CTRL2 Address offset: 0x0058 80-Y0619-1 Rev. A 88 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-21 summarizes the LED control 2 register. Table 5-21 LED_CTRL2 bit description Bits R/W l 31:16 R/W ia 15:0 R/W Initial value 16’hC935 16'hC935 Mnemonic LED_CTRL_RULE_5 LED_CTRL_RULE_4 Description PHY4 LED2 control rule PHY0–PHY3 LED2 control rule nt 5.2.20 LED_CTRL3 e Address offset: 0x005C id Table 5-22 summarizes the LED control 3 register. nf Table 5-22 LED_CTRL3 bit description o Bits R/W Initial value Mnemonic Description 31:26 R/W 0 RESERVED C 25:24 R/W 11 LED_PATTERN_EN_32 Pattern enable for port3 LED2 s 23:22 R/W 11 LED_PATTERN_EN_31 Pattern enable for port3 LED1 21:20 R/W 11 LED_PATTERN_EN_30 Pattern enable for port3 LED0 ro 19:18 R/W 11 LED_PATTERN_EN_22 Pattern enable for port2 LED2 e 17:16 R/W 11 LED_PATTERN_EN_21 Pattern enable for port2 LED1 15:14 R/W 11 LED_PATTERN_EN_20 Pattern enable for port2 LED0 th 13:12 RO 0 RESERVED A 11:10 RO 0 RESERVED 9:8 RO 7:2 RO m0 RESERVED 0 RESERVED 1:0 R/W 0 BLINK_HIGH_TIME ualcom 5.2.21 GOL_MAC_ADDR0 Q Address offset: 0x0060 When LED blinking, these bits determine LED light time. 00 = 50% of blinking period. 250 ms for 2 Hz, 125 ms for 4 Hz, 62.5 ms for 8 Hz. 01 = 12.5% of blinking period 10 = 25% of blinking period 11 = 75% of blinking period Table 5-23 summarizes the global MAC address 0 register. 80-Y0619-1 Rev. A 89 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-23 GOL_MAC_ADDR0 bit description Bits R/W Initial value Mnemonic Description 31:16 R/W l 15:8 R/W ia 7:0 R/W 0 0 0x01 RESERVED MAC_ADDR_BYTE4 Station address of switch, used as source address in pause frame or other management frames. MAC_ADDR_BYTE5 Station MAC address nt 5.2.22 GOL_MAC_ADDR1 e Address offset: 0x0064 id Table 5-24 summarizes the global MAC address 1 register. nf Table 5-24 GLOL_MAC_ADDR1 bit description o Bits R/W Initial value Mnemonic C 31:0 R/W 0 MAC_ADDR_BYTE0 Description Station MAC address s 5.2.23 MAX_FRAME_SIZE ro Address offset: 0x0078 e Table 5-25 summarizes the maximum frame size register. Ath Table 5-25 MAX_FRAME__SIZE bit description Bits R/W Initial value Mnemonic Description 31:21 RO 0 RESERVED mm 20 R/W 0 TEST_PAUSE Test for MAC send out pause frames. MAC sends out pause on frame on positive edge of this signal and pause off frame on negative edge. lco19 R/W 0 IPG_DEC_EN 0 = Normal IPG 96 bit time 1 = MAC decreases two bytes of IPG when send out frame and receive check. 18 RO 0 RESERVED a 17 RO 0 RESERVED u 16 R/W 0 MAC_CRC_RESERVE_EN 0 = MAC removes 4 byte CRC when received Q frame, and add CRC when transmit out frame; 1 = MAC does not remove 4 byte CRC when received frame, and does not add CRC when transmit out frame. 80-Y0619-1 Rev. A 90 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-25 MAX_FRAME__SIZE bit description (cont.) Bits R/W Initial value Mnemonic Description 15:14 RO tial 13:0 R/W 0 ‘H5EE RESERVED MAX_FRAME_SIZE Maximum frame size can be received and transmitted by MAC. If a packet's size is larger than MAX_FRAME_SIZE, it is dropped by MAC. The value is for normal packet, it is added 4 by MAC if support VLAN, added 8 for double VLAN, and added 2 for Atheros header. en 5.2.24 PORT0_STATUS id Address offset: 0x007C f Table 5-26 summarizes the port 0 status register. on Table 5-26 PORT0_STATUS bit description Bits R/W Initial value Mnemonic Description C 31:13 RO 0 RESERVED s 12 R/W 1 FLOW_LINK_EN_0 PHY link mode enable 0 = MAC can be configured by software. ro1 = Enable MAC flow control configure autonegotiation with PHY e 11 RO 0 AUTO_RX_FLOW_EN_0 Transmit flow control enable after auto-negotiation. h 10 RO 0 AUTO_TX_FLOW_EN_0 Transmit flow control enable after auto-negotiation. At 9 R/W 0 LINK_EN_0 PHY link mode enable 0 = MAC can be configured by software 8 RO m0 LINK_0 m 7 R/W 1 o6 R/W 0 alc5 R/W 0 u 4 R/W 0 Q 3 RO 0 TX_HALF_FLOW_EN_0 DUPLEX_MODE_0 RX_FLOW_EN_0 TX_FLOW_EN_0 RXMAC_EN_0 1 = Enable MAC auto-negotiation with PHY Link status: 0 = PHY link down 1 = PHY link up 1 = Transmit flow control enable in half-duplex mode. Duplex mode: 0 = Half-duplex mode 1 = Full-duplex mode Rx MAC flow control enable Tx MAC flow control enable Rx MAC enable 80-Y0619-1 Rev. A 91 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-26 PORT0_STATUS bit description (cont.) Bits R/W Initial value Mnemonic Description 2 R/W 0 TXMAC_EN_0 tial 1:0 R/W 0 SPEED_0 Tx MAC enable Speed mode: 00 = 10M 01 = 100M 10 = 1000M 11 = Error speed mode en 5.2.25 PORT2_STATUS id Address offset: 0x0084 f Table 5-27 summarizes the port 2 status register. on Table 5-27 PORT2_STATUS bit description C Bits R/W Initial value Mnemonic Description 31:13 RO 0 RESERVED s 12 R/W 1 FLOW_LINK_EN_2 PHY link mode enable o0 = MAC can be configured by software. r 1 = Enable MAC flow control configure autonegotiation with PHY e 11 RO 0 AUTO_RX_FLOW_EN_2 Transmit flow control enable after auto-negotiation. h 10 RO 0 AUTO_TX_FLOW_EN_2 Transmit flow control enable after auto-negotiation. At 9 R/W 0 LINK_EN_2 PHY link mode enable. 0 = MAC can be configured by software. 8 RO m0 LINK_2 m 7 R/W 1 lco6 R/W 0 a 5 R/W 0 u 4 R/W 0 Q 3 RO 0 TX_HALF_FLOW_EN_2 DUPLEX_MODE_4 RX_FLOW_EN_2 TX_FLOW_EN_2 RXMAC_EN_2 1 = Enable MAC auto-negotiation with PHY Link status: 0 = PHY link down 1 = PHY link up 1 = Transmit flow control enable in half-duplex mode. Duplex mode 0 = Half-duplex mode 1 = Full-duplex mode Rx MAC flow control enable Tx MAC flow control enable Rx MAC enable 80-Y0619-1 Rev. A 92 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-27 PORT2_STATUS bit description (cont.) Bits R/W Initial value Mnemonic Description 2 R/W 0 TXMAC_EN_2 tial 1:0 R/W 0 SPEED_2 Tx MAC enable Speed mode: 00 = 10M 01 = 100M 10 = 1000M 11 = Error speed mode en 5.2.26 PORT3_STATUS id Address offset: 0x0088 f Table 5-28 summarizes the port 3 status register. on Table 5-28 PORT 3_STATUS bit description C Bits R/W Initial value Mnemonic Description 31:13 RO 0 RESERVED s 12 R/W 1 FLOW_LINK_EN_3 PHY link mode enable o0 = MAC can be configured by software. r 1 = Enable MAC flow control configure autonegotiation with PHY e 11 RO 0 AUTO_RX_FLOW_EN_3 RX flow control enable after auto-negotiation. h 10 RO 0 AUTO_TX_FLOW_EN_3 TX low control enable after auto-negotiation. At 9 R/W 0 LINK_EN_3 PHY link mode enable 0 = MAC can be configure by software. 8 RO m0 LINK_3 m 7 R/W 1 lco6 R/W 0 a 5 R/W 0 Qu 4 R/W 0 TX_HALF_FLOW_EN_3 DUPLEX_MODE_3 RX_FLOW_EN_3 TX_FLOW_EN_3 3 RO 0 RXMAC_EN_3 1 = Enable MAC auto-negotiation with PHY Link status: 1 = PHY link up 0 = PHY link down 1 = Transmit flow control enable in half-duplex mode. Duplex mode: 0 = Half-duplex mode 1 = Full-duplex mode Rx MAC flow control enable Tx MAC flow control enable Rx MAC enable 80-Y0619-1 Rev. A 93 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-28 PORT 3_STATUS bit description (cont.) Bits R/W Initial value Mnemonic Description 2 R/W 0 TXMAC_EN_3 tial 1:0 R/W 0 SPEED_3 Tx MAC enable Speed mode: 00 = 10M 01 = 100M 10 = 1000M 11 = Error speed mode en 5.2.27 PORT6_STATUS id Address offset: 0x0094 f Table 5-29 summarizes the port 6 status register. on Table 5-29 PORT 6_STATUS bit description C Bits R/W Initial value Mnemonic Description 31:13 RO 0 RESERVED s 12 R/W 1 FLOW_LINK_EN_6 PHY link mode enable o0 = MAC can be configured by software. r 1 = Enable MAC flow control configure autonegotiation with PHY e 11 RO 0 AUTO_RX_FLOW_EN_6 Rx flow control enable after auto-negotiation. h 10 RO 0 AUTO_TX_FLOW_EN_6 Tx flow control enable after auto-negotiation. At 9 R/W 0 LINK_EN_6 PHY link mode enable 0 = MAC can be configure by software. 8 RO m0 LINK_6 m 7 R/W 1 o6 R/W 0 alc5 R/W 0 u 4 R/W 0 Q 3 RO 0 TX_HALF_FLOW_EN_6 DUPLEX_MODE_6 RX_FLOW_EN_6 TX_FLOW_EN_6 RXMAC_EN_6 1 = Enable MAC auto-negotiation with PHY Link status: 0 = PHY link down 1 = PHY link up 1 = Transmit flow control enable in half-duplex mode. Duplex mode: 0 = Half-duplex mode 1 = Full-duplex mode Rx MAC flow control enable Tx MAC flow control enable Rx MAC enable. 80-Y0619-1 Rev. A 94 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-29 PORT 6_STATUS bit description (cont.) Bits R/W Initial value Mnemonic Description 2 R/W 0 TXMAC_EN_6 tial 1:0 R/W 0 SPEED_6 Tx MAC enable Speed mode: 00 = 10M 01 = 100M 10 = 1000M 11 = Error speed mode en 5.2.28 HEADER_CTRL id Address offset: 0x0098 f Table 5-30 summarizes the header control register. on Table 5-30 HEADER_CTRL bit description C Bits R/W Initial value Mnemonic Description 31:17 RO 0 RESERVED s 16 R/W 0 HEADER_LENGTH_SEL 0 = 2-byte header o1 = 4-byte header r 15:0 R/W 0 HEADER_TYPE_VALUE 2-byte header type added between SA & header field the 5.2.29 PORT0_HEADER_CTRL A Address offset: 0x009C m Table 5-31 summarizes the port 0 header control register. Table 5-31 PORT0_HEADER_CTRL bit description m Bits R/W Initial value Mnemonic o 31:6 RO 0 RESERVED lc5 R/W 0 IPG_DEC_EN_0 Qua 4 R/W 0 MAC_LOOP_BACK_0 Description 0 = Normal IPG 96 bit time 1 = MAC decreases two bytes of IPG when send out frame and receive check. 1 = Enable MAC loop back at GMII/MII interface 80-Y0619-1 Rev. A 95 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-31 PORT0_HEADER_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 3:2 R/W 0 RX_HEADER_MODE_0 0x0 = No header; 0x1 = Only management with header, must be under 4 bytes header mode. l 0x2 = All frame with header; ia 0x3 = Reserved t 1:0 R/W 0 TX_HEADER_MODE_0 0x0 = No header; 0x1 = Only management with header; must be under 4 n bytes header mode. 0x2 =All frame with header; e 0x3 = Reserved fid 5.2.30 PORT2_HEADER_CTRL n Address offset: 0x00A4 o Table 5-32 summarizes the port 2 header control register. C Table 5-32 PORT 2_HEADER_CTRL bit description s Bits R/W Initial value Mnemonic Description ro 31:6 RO 0 RESERVED he 5 R/W 0 IPG_DEC_EN_2 0 = Normal IPG 96 bit time 1 = MAC decreases two bytes of IPG when send out frame and receive check. t 4 R/W 0 MAC_LOOP_BACK_2 1 = Enable MAC loop back at GMII/MII interface A 3:2 R/W 0 RX_HEADER_MODE_2 0x0 = No header; 0x1 = Only management with header, must be under 4 bytes header mode. m 0x2 = All frame with header; 0x3 = Reserved m 1:0 R/W 0 TX_HEADER_MODE_2 0x0 = No header; 0x1 = Only management with header; must be under 4 o bytes header mode. lc 0x2 = All frame with header; 0x3 = Reserved ua5.2.31 PORT3_HEADER_CTRL Q Address offset: 0x00A8 Table 5-33 summarizes the port 3 header control register. 80-Y0619-1 Rev. A 96 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-33 PORT3_HEADER_CTRL bit description Bits R/W Initial value Mnemonic Description 31:6 RO 0 RESERVED ial 5 R/W 0 IPG_DEC_EN_3 0 = Normal IPG 96 bit time 1 = MAC decreases two bytes of IPG when send out frame and receive check. t 4 R/W 0 MAC_LOOP_BACK_3 1 = Enable MAC loop back at GMII/MII interface n 3:2 R/W 0 RX_HEADER_MODE_3 0x0 = No header; 0x1 = Only management with header, must be under 4 e bytes header mode. id 0x2 = All frame with header; 0x3 = Reserved f 1:0 R/W 0 TX_HEADER_MODE_3 0x0 = No header; n 0x1 = Only management with header; must be under 4 bytes header mode. o 0x2 = All frame with header; 0x3 = Reserved s C 5.2.32 PORT6_HEADER_CTRL ro Address offset: 0x00B4 e Table 5-34 summarizes the port 6 header control register. th Table 5-34 PORT6_HEADER_CTRL bit description A Bits R/W Initial value Mnemonic Description 31:6 RO 5 R/W m0 RESERVED 0 IPG_DEC_EN_6 0 = Normal IPG 96 bit time m 4 R/W 0 o3:2 R/W 0 Qualc1:0 R/W 0 1 = MAC decreases two bytes of IPG when send out frame and receive check. MAC_LOOP_BACK_6 1 = Enable MAC loop back at GMII/MII interface RX_HEADER_MODE_6 0x0 = No header; 0x1 = Only management with header, must be under 4 bytes header mode. 0x2 = All frame with header; 0x3 = Reserved TX_HEADER_MODE_6 0x0 = No header; 0x1 = Only management with header; must be under 4 bytes header mode. 0x2 = All frame with header; 0x3 = Reserved 80-Y0619-1 Rev. A 97 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.2.33 SGMII debug 1 register Address offset: 0x00bc Table 5-35 summarizes the SGMII debug 1 register. l Table 5-35 SGMII debug 1 register bit description ia Bits R/W t 31:10 R/O n 9 R/W ide 8:7 R/O f 6 R/W on 5:0 R/O Initial value Mnemonic 0 RESERVED 0 SERDES_SYNC_STATUS 0 RESERVED 0 SERDES_AN_COMPLETE 0 RESERVED Description SerDes interface synchronization status: 1 = Synchronization works fine 0 = No synchronization SerDes interface autonegotiation: 1 = Autonegotiation completed 0 = Autonegotiation is not completed s C 5.2.34 SGMII_CTRL o Address offset: 0x00E0 r Table 5-36 summarizes the SGMII control register. he Table 5-36 SGMII_CTRL bit description At Bits R/W Initial value Mnemonic Description 31 R/W 1 FULL_DUPLEX_25M 30 R/W 1 HALF_DUPLEX_25M m 29:28 R/W 00 REMOTE_FAULT_25M om 27 R/W 0 NEXT_PAGE_25M lc26 R/W 1 PAUSE_25M Qua 25 R/W 1 ASYM_PAUSE_25M Full-duplex in the base-page of base-x for autonegotiation. Half-duplex in the base-page of base-x for autonegotiation. REMOTE_FAULT[1:0] in the base-page of base-x for auto-negotiation. Generated by the remote_fault logic internal MAC. NEXT_PAGE index in the base-page of base-x and SGMII PHY/MAC for auto-negotiation. Pause in the base-page of base-x and SGMIIPHY/MAC for auto-negotiation. This part is not included in the standard for SGMII. ASYM_PAUSE in the base-page of base-x and SGMII-PHY/MAC for auto-negotiation. This part is not included in the standard for SGMII. 24 R/W 1 PAUSE_SG_TX_EN_ Enable transmitting pause in the base-page of base-x 25M and SGMII-PHY/MAC for auto-negotiation. 80-Y0619-1 Rev. A 98 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-36 SGMII_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 23:22 R/W 21 R/W 20 R/W 19 R/W 18 R/W 17 R/W 16 R/W 15 R/W 14:13 R/W 12:10 R/W 0 0 0 0 0 0 1 0 11 001 MODE_CTRL_25M l MR_LOOPBACK, ia FORCE_SPEED MR_REG4_CH_25M t AUTO_LPI_25M en PRBS_EN SGMII_TH_LOS[1] onfid DIS_AUTO_LPI_25M C SGMII_TH_LOS[0] s SGMII_CDR_BW Athero SGMII_TXDR_CTRL MODE_CTRL signal for mode selection among BASE-X (2'h0), SGMII-PHY (2'h1), and SGMII-MAC (2'h2). Indicate loopback from MII register of cooper PHY and force speed control signal. Indicate register 4 has changed. When RX_LPI_ACTIVE active for once, the register latches this to indicate that the link-partner. Enable SerDes PRBS test function Combined with bit[15], Signal detection threshold setting control 00 = Default 01 = -2dB 10 = +2dB 11 = +2dB Disable the auto-detect link-partner's az ability. Same as bit[17] CDR digital accumulator length control 00 = 0 01 = ±2 10 = ±4 11 = ±8 Default value is 001. 000 = Driver output Vdiff,pp=500 mV 001 = 600 mV 010 = 700 mV m m 9:8 R/W 0 alco7 R/W 1 Qu 6 R/W 1 SGMII_FIBER_MODE SGMII_SEL_CLK125M SGMII_PLL_BW 011 = 800 mV 100 = 900 mV 101 = 1 V 110 = 1.1V 111 = 1.2 V 00 = Not in fiber mode 01 = 100BASE-FX mode 10 = Reserved 11 = 1000BASE-FX mode 0 = sgmii_clk125m_rx_delay is not delayed 1 = sgmii_clk125m_rx_delay is delayed by 2 ns 0 = SGMII PLL bandwidth is low 1 = SGMII PLL bandwidth is high (default) 5 R/W 0 SGMII_HALFTX 0 = TX driver amplitude is normal (default) 1 = TX driver amplitude is half 80-Y0619-1 Rev. A 99 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-36 SGMII_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 4 R/W 0 SGMII_EN_SD 0 = Signal detection disabled and SGMII_FB_SDO = 0 1 = Signal detection enabled ial 3 R/W 0 SGMII_EN_TX 0 = TX driver is in idle and kept in 900 mV 1 = TX driver enabled nt 2 R/W 0 SGMII_EN_RX 0 = RX chain disabled, CLK125M_RX and DOUT_RX could be any logic of 1 or 0 1 = RX chain enabled ide 1 R/W 0 SGMII_EN_PLL 0 = SGMII PLL disabled 1 = DSGMII PLL enabled f 0 R/W 0 SGMII_EN_LCKDT 0 = Disabled (default) 1 = SGMII VCO control voltage detector and lock n detector enabled Co 5.2.35 MAC_PWR_SEL s Address offset: 0x0e4 o Table 5-37 summarizes the MAC_PWR_SEL register. er Table 5-37 MAC_PWR_SEL bit description h Bits R/W Initial value Mnemonic Description t 31:20 R/O 0 RESERVED A 19 R/W 0 PWR_RGMII_0 For MAC0 RGMII interface power source selection when using m 18 R/W lcom 17:0 R/W 0 00x2a545 internal regulator: 0 = 1.5 V 1 = 1.8 V PWR_RGMII_1 For MAC5/6 RGMII interface power source selection when using internal regulator: 0 = 1.5 V 1 = 1.8 V RESERVED ua5.3 EEE control registers Q Table 5-38 summarizes the EEE control registers. 80-Y0619-1 Rev. A 100 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-38 EEE control register summary Offset range Name 0x0100 l 0x0130–0x0018 ia 0x0140–0x0148 EEE control register Port2 EEE variable register Port3 EEE variable register nt 5.3.1 EEE_CTRL e Address offset: 0x0100 id Table 5-39 summarizes the EEE control register. nf Table 5-39 EEE_CTRL bit description Bits R/W Initialvalue Mnemonic o 31:14 RO 0 RESERVED C 13 R/W 0 RESERVED 12 RO 1 RESERVED s 11 R/W 0 RESERVED o 10 RO 1 RESERVED r 9 R/W 0 RESERVED e 8 R/W 1 LPI_EN_3 h 7 R/W 0 RESERVED At 6 R/W 1 LPI_EN_2 Description LPI enable for port3 LPI enable for port2 5 R/W 0 RESERVED 4 RO 0 RESERVED m 3 R/W 0 EEE_CPU_CHANGE_EN 1 = CPU can set the resolved value 2 R/W 0 EEE_LLDP_TO_CPU_EN 0 = EEE LLDP packet to deheader m 1 = EEE LLDP packet to CPU o1 R/W 0 EEE_EN 1 = Support LLDP auto-negotiation PHY wake-up time lc0 RO 0 RESERVED ua5.3.2 EEE_LOC_VALUE_2 Q Address offset: 0x0130 Table 5-40 summarizes the port 2 EEE variable register 0. 80-Y0619-1 Rev. A 101 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-40 EEE_LOC_VALUE_2 bit description Bits R/W Initial value Mnemonic Description 31:16 R/W l 15:0 R/W 0x11 0x11 LOC_RX_VALUE_2 LOC_TX_VALUE_2 tia 5.3.3 EEE_REM_VALUE_2 n Address offset: 0x0134 e Table 5-41 summarizes the port 2 EEE variable register 1. fid Table 5-41 EEE_REM_VALUE_2 bit description n Bits R/W 31:16 R/W o 15:0 R/W Initial value 0 0 Mnemonic ECHO_RX_VALUE_2 ECHO_TX_VALUE_2 s C 5.3.4 EEE_RES_VALUE_2 o Address offset: 0x0138 r Table 5-42 summarizes the port 2 EEE variable register 2. the Table 5-42 EEE_RES_VALUE_2 bit description A Bits R/W Initial value Mnemonic LocRxSystemValue LocTxSystemValue Description LocRxSystemValueEcho LocTxSystemValueEcho Description 31:16 RO 15:0 RO m0x24 0x24 LOC_RESOLVED_RX_VALUE_2 LOC_RESOLVED_TX_VALUE_2 m 5.3.5 EEE_LOC_VALUE_3 o Address offset: 0x0140 lcTable 5-43 summarizes the port 3 EEE variable register 0. aTable 5-43 EEE_LOC_VALUE_3 bit description u Bits R/W Q 31:16 R/W Initial value 0x11 Mnemonic LOC_RX_VALUE_3 LocResolvedRxSystemValueEcho LocResolvedTxSystemValueEcho Description LocRxSystemValue 15:0 R/W 0x11 LOC_TX_VALUE_3 LocTxSystemValue 80-Y0619-1 Rev. A 102 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.3.6 EEE_REM_VALUE_3 Address offset: 0x0144 Table 5-44 summarizes the port 3 EEE variable register 1. l Table 5-44 EEE_REM_VALUE_3 bit description ia Bits R/W t 31:16 R/W n 15:0 R/W Initial value 0 0 Mnemonic ECHO_RX_VALUE_3 ECHO_TX_VALUE_3 Description LocRxSystemValueEcho LocTxSystemValueEcho ide 5.3.7 EEE_RES_VALUE_3 f Address offset: 0x0148 n Table 5-45 summarizes the port 3 EEE variable register 2. Co Table 5-45 EEE_RES_VALUE_3 bit description Bits R/W Initial value Mnemonic s 31:16 RO 0x24 LOC_RESOLVED_RX_VALUE_3 o 15:0 RO 0x24 LOC_RESOLVED_TX_VALUE_3 Description LocResolvedRxSystemValueEcho LocResolvedTxSystemValueEcho her 5.4 Parser control registers At Table 5-46 summarizes the parser registers. m Table 5-46 Parser register summary Offset range 0x0200–0x0204 m 0x0208 o0x0210–0x0214 lc0x0218–0x024C 0x0270 Name Normalize control register Normalize length control register Frame acknowledge control register Window rule control register Trunk hash enable register Qua5.4.1 NORMALIZE_CTRL0 Address offset: 0x0200 Table 5-47 summarizes the normalize control 0 register. 80-Y0619-1 Rev. A 103 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-47 NORMALIZE_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31:30 RO 29 R/W0 28 R/W0 27 R/W0 26 R/W 25 R/W 24 R/W 23 R/W 22 R/W 21 R/W 20 R/W 19 RO 18 RO 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED l TCP_PSH1_ACK0_DROP_EN ia TCP_FIN1_ACK0_DROP_EN t TCP_RST1_WITH_DATA_ n DROP_EN e TCP_SYN1_WITH_DATA_ DROP_EN id TCP_RST1_DROP_EN f TCP_SYN0_ACK0_RST0_ n DROP_EN o TCP_SYN1_FIN1_DROP_EN C TCP_SYN1_RST1_DROP_EN s TCP_NULLSCAN_DROP_EN ro TCP_XMASSCAN_DROP_EN e TCP_SYN1_ACK1_PSH1_ h DROP_EN AtTCP_SYN1_PSH1_DROP_EN 1 = Frame with PUSH=1 & ACK=0 is dropped. 1 = Frame with FIN=1 & ACK=0 is dropped. 1 = Frame with RST=1 and IP_LEN - IP_ HDR_LEN - TCP_OFFSET > 0 is dropped. 1 = Frame with SYN=1 and IP_LEN - IP_ HDR_LEN - TCP_OFFSET > 0 is dropped. 1 = Frame with RST=1 is dropped. 1 = Frame with SYN=0 & ACK=0 & RST=0 is dropped. 1 = Frame with SYN=1 & FIN=1 is dropped. 1 = Frame with SYN=1 & RST=1 is dropped. 1 = Frame with Seq_Num=0 and all TCP FLAG zero is dropped. 1 = Frame with Seq_Num=0, FIN=1, URG=1, and PSH=1 is dropped 1 = Frame with SYN=1 & ACK=1 & PSH=1 is dropped. 1 = Frame with SYN=1 & PSH=1 is dropped. 17 RO m 16 RO 15 RO 0 TCP_SYN1_URG1_DROP_EN 0 TCP_SYN_ERR_DROP_EN 0 TCP_HDR_MIN_DROP_EN om 14 R/W lc13 R/W Qua 12 R/W 0 TCP_SAME_PORT_DROP_EN 0 IPV4_CHECKSUM_DROP_EN 0 IPV4_DIP_ERR_DROP_EN 11 R/W 0 IPV4_SIP_ERR_DROP_EN 1 = Frame with SYN=1 & URG=1 is dropped. 1 = Frame with SYN=1 & ACK=0 & SP<1024 is dropped 1 = If frame with TCP header length less than TCP_HDR_MIN_SIZE, but not first of fragment, is dropped 1 = TCP frame with SP equal to DP is dropped. 1 = Frame with IPv4 checksum error is dropped. 1 = Frame is dropped if with DIP all zero, or DIP[31:24] is 0x7F. 1 = Frame is dropped if with SIP[31:24] more than 0xE0 and less than 0xF0, or equal to 0x7F, or SIP[31:0] is 0x32'hFFFFFFFF. 80-Y0619-1 Rev. A 104 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-47 NORMALIZE_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 10 R/W l 9 R/W 8 R/W tia 7 R/W n 6 R/W ide 5 R/W f 4 R/W n 3 RO Co 2 R/W 1 R/W os 0 R/W 0 IPV4_FRAG_LEN_DROP_EN 1 = Frame with IPv4 fragment length check error is dropped. 0 IPV4_FRAG_MAX_DROP_EN 0 IPV4_FRAG_MIN_DROP_EN 1 = Frame with offset length less than minimum is dropped 0 IPV4_DF_DROP_EN 1 = Frame with DF=1 and offset or MF not zero, is dropped 0 IP_LEN_DROP_EN 1 = Frame with IP length field error is dropped, IPv4 and IPv6 included. 0 IPV4_HDR_LEN_CHECK_EN 1 = Check the IP options. If frame is with options, drop or send to CPU 0 IPV4_HDR_LEN_DROP_EN Forward or drop frame when IPv4 header length check fails. 0 IPV4_HDR_LEN_MIN_DROP_ 0 = Frame is dropped if the leangth of IPv4 EN header check fails. 0 IP_SAME_PORT_DROP_EN 1 = Frame is dropped if SIP equals to DIP. 0 IP_VER_DROP_EN 1 = Frame is dropped if the version field is not equal to 0x4 or 0x6 in IP header. 1 VID_4095_DROP_EN 1 = Frame is dropped if VID equals to 4095. her 5.4.2 NORMALIZE_CTRL1 At Address offset: 0x0204 Table 5-48 summarizes the normalize control 1 register. m Table 5-48 NORMALIZE_CTRL1 bit description Bits R/W Initial value Mnemonic m 31:24 R/W 0 IPV4_FRAG_MIN o 23:21 R/O lc20 R/W a 19 R/W Qu 18 R/W 0 RESERVED 0 INVALID_MAC_SRC_ADDR_ DROP_EN 0 IPV4_MIN_PKT_LEN_DROP_ EN 0 IPV6_MIN_PKT_LEN_DROP_ EN Description Define the minimum length of IPv4 frame with fragment SA is broadcast or multicast address. The frame is dropped by the switch. If the frame length is less than the minimum IPv4 frame size. If the frame length is less than the minimum IPv6 frame size 17 R/W 0 INVALID_SIP6_DROP_EN Drop Invalid Source IP for IPv6 IP is ::1 or ff00::/8 80-Y0619-1 Rev. A 105 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-48 NORMALIZE_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 16 R/W 15:12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 0x5 0 0 0 0 0 0 0 0 0 0 0 INVALID_DIP6_DROP_EN Drop Invalid Destination IP for IPv6 \ IP is ::1 or ::/128 l TCP_HDR_MIN_SIZE Defined the minimum size of TCP header ia ICMP_CHECKSUM_DROP_EN Drop the ICMP checksum error t ICMPV6_FRAG_DROP_EN 1 = Frame with fragment ICMPv6 is dropped. n ICMPV4_FRAG_DROP_EN 1 = Frame with fragment ICMPv4 is dropped. e ICMPV6_MAX_LEN_DROP_EN 1 = Frame with un-fragment ICMPv6 length id larger than ICMPV6_MAX_LEN is dropped. f ICMPV4_MAX_LEN_DROP_EN 1 = Frame with un-fragment ICMPv4 length larger than ICMPV4_MAX_LEN is n dropped. o UDP_CHECKSUM_DROP_EN 1 = Frame with UDP checksum error is dropped. C UDP_LEN_DROP_EN 1 = Frame with UDP length check error is dropped. s UDP_SAME_PORT_DROP_EN 1 = UDP frame with SP equal to DP is dropped. ro TCP_OPTION_DROP_EN 1 = Frame with SYN=0 and IP header larger than 20 byte, is dropped. e TCP_URG0_PTR_ERR_DROP_ 1 = Frame with URG=0 but pointer not EN zero is dropped. Ath TCP_CHECKSUM_DROP_EN 1 = Frame with TCP checksum error is dropped. 0 R/W m0 TCP_URG1_ACK0_DROP_EN 1 = Frame with URG=1 & ACK=0 is dropped. 5.4.3 NORMALIZE_LEN_CTRL m Address offset: 0x0208 o Table 5-49 summarizes the normalize length control register. alcTable 5-49 NORMALIZE_LEN_CTRL bit description u Bits R/W Initial value Mnemonic Q 31:30 RO 0 RESERVED Description 29:16 R/W 0x40 ICMPV6_MAX_LEN Defined the maximum IP payload length of ICMPv6 frame 15:14 RO 0 RESERVED 13:0 R/W 0x40 ICMPV4_MAX_LEN Defined the maximum IP payload length of ICMPv4 frame 80-Y0619-1 Rev. A 106 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.4.4 FRAM_ACK_CTRL0 Address offset: 0x00210 Table 5-50 summarizes the frame ACK control 0 register. l Table 5-50 FRAM_ACK_CTRL0 bit description tia Bits R/W Initial value Mnemonic n 31 RO 0 RESERVED e 30 R/W 0 ARP_REQ_EN_3 See bit[6] id 29 R/W 0 ARP_ACK_EN_3 See bit[5] 28 R/W 0 DHCP_EN_3 See bit[4] f 27 R/W 0 EAPOL_EN_3 See bit[3] n 26 R/W 0 IGMP_LEAVE_EN_3 See bit[2] o 25 R/W 0 IGMP_JOIN_EN_3 See bit[1] 24 R/W 0 IGMP_MLD_EN_3 See bit[0] C 23 RO 0 RESERVED s 22 R/W 0 ARP_REQ_EN_2 See bit[6] o 21 R/W 0 ARP_ACK_EN_2 See bit[5] r 20 R/W 0 DHCP_EN_2 See bit[4] e 19 R/W 0 EAPOL_EN_2 See bit[3] 18 R/W 0 IGMP_LEAVE_EN_2 See bit[2] th 17 R/W 0 IGMP_JOIN_EN_2 See bit[1] A 16 R/W 0 IGMP_MLD_EN_2 See bit[0] Description 15 RO 14 R/W 0 0 mRESERVED ARP_REQ_EN_1 See bit[6] 13 R/W 0 ARP_ACK_EN_1 See bit[5] 12 R/W 0 DHCP_EN_1 See bit[4] m 11 R/W 0 EAPOL_EN_1 See bit[3] o10 R/W 0 IGMP_LEAVE_EN_1 See bit[2] lc9 R/W 0 IGMP_JOIN_EN_1 See bit[1] 8 R/W 0 IGMP_MLD_EN_1 See bit[0] a 7 RO 0 RESERVED u 6 R/W 0 ARP_REQ_EN_0 ARP request frame acknowledge enable Q 5 R/W 0 ARP_ACK_EN_0 ARP response frame acknowledge enable 4 R/W 0 DHCP_EN_0 0 = Acknowledge DHCP frame disable 1 = Acknowledge DHCP frame enable 80-Y0619-1 Rev. A 107 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-50 FRAM_ACK_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 3 R/W 0 EAPOL_EN_0 1 = Hardware acknowledge 802.1x frame, and send frame copy or redirect to CPU controlled by EAPAL_REDIRECT_EN l 2 R/W 0 IGMP_LEAVE_EN_0 1 = Enable IGMP/MLD hardware fast leave ia 1 R/W 0 IGMP_JOIN_EN_0 1 = Enable IGMP/MLD hardware join t 0 R/W 0 IGMP_MLD_EN_0 IGMP/MLD snooping enable. If this bit is set to 1, the port examines all received frames and copy or redirect to CPU port n controlled by IGMP_COPY_EN. ide 5.4.5 FRAM_ACK_CTRL1 f Address offset: 0x00214 n Table 5-51 summarizes the frame ACK control 1 register. Co Table 5-51 FRAM_ACK_CTRL1 bit description Bits R/W Initial value Mnemonic s 31:26 RO 0 RESERVED o 25 R/W 0 PPPOE_EN er 24 R/W 0 IGMP_V3_EN th 23 RO 0 RESERVED A 22 R/W 0 ARP_REQ_EN_6 Description 0 = PPPoE package acknowledge disable 1 = PPPoE package acknowledge enable 0 = IGMPv3 or MLDv2 acknowledge disable 1 = IGMPv3 or MLDv2 acknowledge enable See bit[6] 21 R/W 20 R/W m0 ARP_ACK_EN_6 0 DHCP_EN_6 See bit[5] See bit[4] 19 R/W 0 18 R/W 0 m 17 R/W 0 o16 R/W 0 lc15 RO 0 14 R/W 0 a 13 R/W 0 u 12 R/W 0 Q 11 R/W 0 EAPOL_EN_6 See bit[3] IGMP_LEAVE_EN_6 See bit[2] IGMP_JOIN_EN_6 See bit[1] IGMP_MLD_EN_6 See bit[0] RESERVED ARP_REQ_EN_5 See bit[6] ARP_ACK_EN_5 See bit[5] DHCP_EN_5 See bit[4] EAPOL_EN_5 See bit[3] 10 R/W 0 IGMP_LEAVE_EN_5 See bit[2] 9 R/W 0 IGMP_JOIN_EN_5 See bit[1] 8 R/W 0 IGMP_MLD_EN_5 See bit[0] 80-Y0619-1 Rev. A 108 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-51 FRAM_ACK_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 7 RO 0 RESERVED 6 R/W 0 ARP_REQ_EN_4 ARP request frame acknowledge enable l 5 R/W 0 ARP_ACK_EN_4 ARP response frame acknowledge enable ia 4 R/W 0 DHCP_EN_4 0 = Acknowledge DHCP frame disable 1 = Acknowledge DHCP frame enable nt 3 R/W 0 EAPOL_EN_4 1 = Hardware acknowledge 802.1x frame, and send frame copy or redirect to CPU controlled by EAPAL_ REDIRECT_EN. e 2 R/W 0 IGMP_LEAVE_EN_4 1 = Enable IGMP/MLD hardware fast leave id 1 R/W 0 IGMP_JOIN_EN_4 1 = Enable IGMP/MLD hardware join f 0 R/W 0 IGMP_MLD_EN_4 IGMP/MLD snooping enable. If this bit is set to 1, the port n examines all received frames and copies or redirects to CPU port controlled by IGMP_COPY_EN. Co 5.4.6 WIN_RULE_CTRL0 s Address offset: 0x0218 o Table 5-52 summarizes the window rule control 0 register. er Table 5-52 WIN_RULE_CTRL0 bit description h Bits R/W Initial value Mnemonic Description t 31:28 RO 0 RESERVED A 27:24 R/W 0 L4_LENGTH_0 These bits indicate that window rule in port0 to select length of L4, from L4_OFFSET_0. 23:20 R/W 0 L3_LENGTH_0 These bits indicate that window rule in port0 to select length of m L3, from L3_OFFSET_0. 19:16 R/W 0 L2_LENGTH_0 These bits indicate that window rule in port0 to select length of L2, from L2_OFFSET_0. m 15 RO 0 RESERVED o 14:10 R/W 0 L4_OFFSET_0 These bits indicate that window rule in port0 to select offset of lc L3, from TCP/UDP header. 9:5 R/W 0 L3_OFFSET_0 These bits indicate that window rule in port0 to select offset of a L3, from IP header. u 4:0 R/W 0 L2_OFFSET_0 These bits indicate that window rule in port0 to select offset of Q L2, from MAC DA. 5.4.7 WIN_RULE_CTRL2 Address offset: 0x0220 80-Y0619-1 Rev. A 109 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-53 summarizes the window rule control 2 register. Table 5-53 WIN_RULE_CTRL2 bit description Bits R/W Initial value Mnemonic Description l 31:28 RO 0 RESERVED ia 27:24 R/W 0 L4_LENGTH_2 These bits indicate that window rule in port2 to select length of L4, from L4_OFFSET_2. t 23:20 R/W 0 L3_LENGTH_2 These bits indicate that window rule in port2 to select length of n L3, from L3_OFFSET_2. e 19:16 R/W 0 L2_LENGTH_2 These bits indicate that window rule in port2 to select length of L2, from L2_OFFSET_2. id 15 R/W 0 RESERVED f 14:10 R/W 0 L4_OFFSET_2 These bits indicate that window rule in port2 to select offset of L3, from TCP/UDP header. n 9:5 R/W 0 L3_OFFSET_2 These bits indicate that window rule in port2 to select offset of o L3, from IP header. 4:0 R/W 0 L2_OFFSET_2 These bits indicate that window rule in port2 to select offset of C L2, from MAC DA. s 5.4.8 WIN_RULE_CTRL3 ro Address offset: 0x0224 e Table 5-54 summarizes the window rule control 3 register. Ath Table 5-54 WIN_RULE_CTRL3 bit description Bits R/W Initial value Mnemonic Description 31:28 RO 0 RESERVED m 27:24 R/W 0 L4_LENGTH_3 These bits indicate that window rule in port3 to select length of L4, from L4_OFFSET_3. 23:20 R/W 0 L3_LENGTH_3 These bits indicate that window rule in port3 to select length of m L3, from L3_OFFSET_3. o 19:16 R/W 0 L2_LENGTH_3 These bits indicate that window rule in port3 to select length of L2, from L2_OFFSET_3. lc15 R/W 0 RESERVED a14:10 R/W 0 L4_OFFSET_3 These bits indicate that window rule in port3 to select offset of L3, from TCP/UDP header. u 9:5 R/W 0 L3_OFFSET_3 These bits indicate that window rule in port3 to select offset of Q L3, from IP header. 4:0 R/W 0 L2_OFFSET_3 These bits indicate that window rule in port3 to select offset of L2, from MAC DA. 80-Y0619-1 Rev. A 110 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.4.9 WIN_RULE_CTRL6 Address offset: 0x0230 Table 5-55 summarizes the window rule control 6 register. l Table 5-55 WIN_RULE_CTRL6 bit description ia Bits R/W Initial value Mnemonic Description t 31:28 RO 0 RESERVED n 27:24 R/W 0 L4_LENGTH_6 These bits indicate that window rule in port6 to select length of e L4, from L4_OFFSET_6. 23:20 R/W 0 L3_LENGTH_6 These bits indicate that window rule in port6 to select length of id L3, from L3_OFFSET_6. f 19:16 R/W 0 L2_LENGTH_6 These bits indicate that window rule in port6 to select length of L2, from L2_OFFSET_6. n 15 R/W 0 RESERVED o 14:10 R/W 0 L4_OFFSET_6 These bits indicate that window rule in port6 to select offset of L3, from TCP/UDP header. C 9:5 R/W 0 L3_OFFSET_6 These bits indicate that window rule in port6 to select offset of L3, from IP header. s 4:0 R/W 0 L2_OFFSET_6 These bits indicate that window rule in port6 to select offset of o L2, from MAC DA. er 5.4.10 WIN_RULE_CTRL7 th Address offset: 0x0234 A Table 5-56 summarizes the window rule control 7 register. m Table 5-56 WIN_RULE_CTRL7 bit description Bits R/W Initial value Mnemonic Description m 31:24 RO 0 RESERVED 23:20 R/W 0 L3_LENGTH1_0 These bits indicate that window rule in port0 to select length o of L3, from L3_OFFSET1_0. lc19:16 R/W 0 L2_LENGTH1_0 These bits indicate that window rule in port0 to select length of L2, from L2_OFFSET1_0. a15:10 R/W 0 RESERVED u 9:5 R/W 0 L3_OFFSET1_0 These bits indicate that window rule in port0 to select offset of L3, from IP header. Q 4:0 R/W 0 L2_OFFSET1_0 These bits indicate that window rule in port0 to select offset of L2, from the end of snap. 80-Y0619-1 Rev. A 111 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.4.11 WIN_RULE_CTRL9 Address offset: 0x023C Table 5-57 summarizes the window rule control 9 register. l Table 5-57 WIN_RULE_CTRL9 bit description ia Bits R/W Initial value Mnemonic Description t 31:24 RO 0 RESERVED n 23:20 R/W 0 L3_LENGTH1_2 These bits indicate that window rule in port2 to select length e of L3, from L3_OFFSET1_0. 19:16 R/W 0 L2_LENGTH1_2 These bits indicate that window rule in port2 to select length id of L2, from L2_OFFSET1_0. f 15:10 RO 0 RESERVED n 9:5 R/W 0 L3_OFFSET1_2 These bits indicate that window rule in port2 to select offset of L3, from IP header. o 4:0 R/W 0 L2_OFFSET1_2 These bits indicate that window rule in port2 to select offset of L2, from the end of snap. s C 5.4.12 WIN_RULE_CTRL10 o Address offset: 0x0240 er Table 5-58 summarizes the window rule control 10 register. th Table 5-58 WIN_RULE_CTRL10 bit description A Bits R/W Initial value Mnemonic Description 31:24 RO 0 RESERVED 23:20 R/W 0 L3_LENGTH1_3 These bits indicate that window rule in port3 to select length m of L3, from L3_OFFSET1_0. 19:16 R/W 0 L2_LENGTH1_3 These bits indicate that window rule in port3 to select length m of L2, from L2_OFFSET1_0. 15:10 R/W 0 RESERVED o9:5 R/W 0 L3_OFFSET1_3 These bits indicate that window rule in port3 to select offset of lc L3, from IP header. 4:0 R/W 0 L2_OFFSET1_3 These bits indicate that window rule in port3 to select offset of a L2, from the end of snap. Qu5.4.13 WIN_RULE_CTRL13 Address offset: 0x024C Table 5-59 summarizes the window rule control 13 register. 80-Y0619-1 Rev. A 112 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-59 WIN_RULE_CTRL13 bit description Bits R/W Initial value Mnemonic Description 31:24 RO 0 RESERVED l 23:20 R/W 0 L3_LENGTH1_6 These bits indicate that window rule in port6 to select length of L3, from L3_OFFSET1_0. ia 19:16 R/W 0 L2_LENGTH1_6 These bits indicate that window rule in port6 to select length t of L2, from L2_OFFSET1_0. 15:10 R/W 0 RESERVED n 9:5 R/W 0 L3_OFFSET1_6 These bits indicate that window rule in port6 to select offset of e L3, from IP header. id 4:0 R/W 0 L2_OFFSET1_6 These bits indicate that window rule in port6 to select offset of L2, from the end of snap. nf 5.4.14 TRUNK_HASH_EN o Address offset: 0x0270 C Table 5-60 summarizes the trunk hash enable register. os Table 5-60 TRUNK_HASH_EN bit description r Bits R/W e 31:4 RO h 3 R/W t 2 R/W A 1 R/W Initial value 0 1 1 1 Mnemonic RESERVED TRUNK_HASH_SIP_EN TRUNK_HASH_DIP_EN TRUNK_HASH_SA_EN Description SIP join the trunk hash DIP join the trunk hash SA join the trunk hash m 0 R/W 1 TRUNK_HASH_DA_EN 5.5 ACL control registers m Table 5-61 summarizes the ACL registers. lco Table 5-61 ACL register summary a Offset range 0x0400–0x0414 Qu 0x0418 ACL function register VLAN translation test register 0x0420–0x0424 Port0 VLAN control register DA join the trunk hash Name 0x0430–0x0434 Port2 VLAN control register 0x0438–0x043C Port3 VLAN control register 0x0450–0x0454 Port6 VLAN control register 80-Y0619-1 Rev. A 113 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.5.1 ACL_FUNC0 Address offset: 0x0400 Table 5-62 summarizes the ACL function 0 register. l Table 5-62 ACL_FUNC0 bit description ia Bits R/W Initial value Mnemonic Description ent 31 R/W 0 ACL_BUSY Depend: ACL_DONE_INT, ACL table busy. This bit must be set to 1 to start a ACL operation and cleared to 0 after operation done. If this bit is set to 1, CPU can not request another operation. id 30:11 RO 0 RESERVED f 10 R/W 0 ACL_FUNC 0 = Write 1 = Read n 9:8 R/W 0 ACL_RULE_SEL ACL rule selection: o 00 = Rule 01 = Mask C 10 = Result 11 = Reserved s 7 RO 0 RESERVED o 6:0 R/W 0 ACL_FUNC_INDEX ACL rule index er 5.5.2 ACL_FUNC1 th Address offset: 0x0404 A Table 5-63 summarizes the ACL function 1 register. Table 5-63 m ACL_FUNC1 bit description Bits R/W Initial value Mnemonic m 31:0 R/WW 0 ACL_RULE_DATA_0 lco 5.5.3 ACL_FUNC2 aAddress offset: 0x0408 Qu Table 5-64 summarizes the ACL function 2 register. Description ACL rule: byte[3:0] Table 5-64 ACL_FUNC2 bit description Bits R/W Initial value Mnemonic 31:0 R/WW 0 ACL_RULE_DATA_1 Description ACL rule: byte[7:4] 80-Y0619-1 Rev. A 114 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.5.4 ACL_FUNC3 Address offset: 0x040C Table 5-65 summarizes the ACL function 3 register. l Table 5-65 ACL_FUNC3 bit description ia Bits R/W Initial value Mnemonic t 31:0 R/WW 0 ACL_RULE_DATA_2 en 5.5.5 ACL_FUNC4 fid Address offset: 0x0410 n Table 5-66 summarizes the ACL function 4 register. o Table 5-66 ACL_FUNC4 bit description C Bits R/W Initial value Mnemonic 31:0 R/W\W 0 ACL_RULE_DATA_3 ros 5.5.6 ACL_FUNC5 e Address offset: 0x0414 Ath Table 5-67 summarizes the ACL function 5 register. Description ACL rule: byte[11:8] Description ACL rule: byte[15:12] m Table 5-67 ACL_FUNC5 bit description Bits R/W Initial value Mnemonic 31:8 R/W 7:0 R/WW 0 RESERVED 0 ACL_RULE_DATA_4 om 5.5.7 VLAN_TRANS_TEST lcAddress offset: 0x0418 aTable 5-68 summarizes the VLAN translation test register. Qu Table 5-68 VLAN_TRANS_TEST bit description Description ACL rule: byte[16] Bits R/W Initial value Mnemonic Description 31 R/W 0 VLAN_TRANS_TEST_EN 30:2 RO 0 RESERVED 80-Y0619-1 Rev. A 115 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-68 VLAN_TRANS_TEST bit description (cont.) Bits R/W Initial value Mnemonic Description 1 R/W 0 EG_TRANS_FLTR_BYPASS_EN Translation filter bypass enable Only valid for not 1:1 entry when doing second QinQ lookup. If it's valid, the l forwarding member is set to 0x7f. tia 0 R/W 0 NET_ISOLATE_EN 1 = Isolate private net and public net. The packet is dropped at layer forwarding when DIP is private IP but SIP is not private IP. en 5.5.8 PORT0_VLAN_CTRL0 id Address offset: 0x0420 f Table 5-69 summarizes the port 0 VLAN control 0 register. on Table 5-69 PORT0_VLAN_CTRL0 bit description Bits R/W Initial value Mnemonic Description C 31:29 R/W 0 ING_PORT_CPRI_0 Port default CVLAN priority for received frames. s 28 RO 0 RESERVED o 27:16 R/W 0x1 PORT_DEFAULT_CVID_0 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from r this port. e 15:13 R/W 0 ING_PORT_SPRI_0 Port default SVLAN priority for received frames. h 12 RO 0 RESERVED t 11:0 R/W 0x1 PORT_DEFAULT_SVID_0 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from A this port. m 5.5.9 PORT0_VLAN_CTRL1 m Address offset: 0x0424 o Table 5-70 summarizes the port 0 VLAN control 1 register. lcTable 5-70 PORT0_VLAN_CTRL1 bit description a Bits R/W Initial value Mnemonic u 31:15 RO 0 RESERVED Q 14 R/W 0 EG_VLAN_TYPE_0 Description 0 = All frames can be sent out. 1 = Only tagged frames can be sent out. 80-Y0619-1 Rev. A 116 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-70 PORT0_VLAN_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 13:12 R/W 11 RO 10 RO 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3:2 R/W 11 0 0 0 0 0 1 0 0 0 ial EG_VLAN_MODE_0 Egress VLAN mode 00 = Egress transmits frames unmodified 01 = Egress transmits frames without VLAN 10 = Egress transmits frames with VLAN 11 = Untouched t RESERVED SPCHECK_EN_0 1 = L3 source port check enable en CORE_PORT_EN_0 0 = Edge port 1 = Core port id FORCE_DEFAULT_VID_EN_0 0 = Use frame tag only. f 1 = Force to use port default VID and priority for received frame, when 802.1q mode is not n disable. o PORT_TLS_MODE_0 0 = Port work at NON-TLS mode 1 = Port work at TLS mode C PORT_VLAN_PROP_EN_0 1 = Enable part-based VLAN propagate function. s PORT_CLONE_EN_0 0 = Enable port replace 1 = Enable port clone o VLAN_PRI_PRO_EN_0 1 = VLAN priority propagation enable Ather ING_VLAN_MODE_0 00 = All frame can be received by this port, including untagged and tagged frames. 01 = Only frame with tag can be received by this port. 10 = Only frame untagged can be received by this port, including no VLAN and priority VLAN. 1:0 RO m0 RESERVED 11 = Reserved m 5.5.10 PORT2_VLAN_CTRL0 o Address offset: 0x0430 lcTable 5-71 summarizes the port 2 VLAN control 0 register. aTable 5-71 PORT2_VLAN_CTRL0 bit description u Bits R/W Initial value Mnemonic Q 31:29 R/W 0 ING_PORT_CPRI_2 Description Port default CVLAN priority for received frames. 28 RO 0 RESERVED 27:16 R/W 0X1 PORT_DEFAULT_CVID_2 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from this port. 80-Y0619-1 Rev. A 117 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-71 PORT2_VLAN_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 15:13 R/W 0 ING_PORT_SPRI_2 Port default SVLAN priority for received frames. 12 RO 0 RESERVED l 11:0 R/W 0X1 PORT_DEFAULT_SVID_2 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from ia this port. nt 5.5.11 PORT2_VLAN_CTRL1 e Address offset: 0x0434 id Table 5-72 summarizes the port 2 VLAN control 1 register. nf Table 5-72 PORT2_VLAN_CTRL1 bit description o Bits R/W Initial value Mnemonic 31:15 RO 0 RESERVED C 14 R/W 0 EG_VLAN_TYPE_2 s 13:12 R/W 3 EG_VLAN_MODE_2 thero 11 RO 0 RESERVED A 10 R/W 0 SPCHECK_EN_2 Description 0 = All frames can be sent out. 1 = Only tagged frames can be sent out. Egress VLAN mode. 00 = Egress transmits frames unmodified 01 = Egress transmits frames without VLAN 10 = Egress transmits frames with VLAN 11 =Untouched 1 = L3 source port check enable 9 R/W 0 CORE_PORT_EN_2 0 = Edge port 1 = Core port m 8 R/W 0 FORCE_DEFAULT_VID_EN_2 0 = Use frame tag only. 1 = Force to use port default VID and priority for received frame, when 802.1q mode is not m disable. lco7 R/W 0 PORT_TLS_MODE_2 0 = Port work at NON-TLS mode 1 = Port work at TLS mode 6 R/W 1 PORT_VLAN_PROP_EN_2 1 = Enable part-based VLAN propagate function. ua 5 R/W 0 PORT_CLONE_EN_2 0 = Enable port replace 1 = Enable port clone Q 4 R/W 0 VLAN_PRI_PRO_EN_2 1 = VLAN priority propagation enable 80-Y0619-1 Rev. A 118 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-72 PORT2_VLAN_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 3:2 R/W 0 ING_VLAN_MODE_2 ntial 0 RO 0 RESERVED 00 = All frame can be received by this port, including untagged and tagged frames. 01 = Only frame with tag can be received by this port. 10 = Only frame untagged can be received by this port, including no VLAN and priority VLAN. 11 = Reserved ide 5.5.12 PORT3_VLAN_CTRL0 f Address offset: 0x0438 n Table 5-73 summarizes the port 3 VLAN control 0 register. o Table 5-73 PORT3_VLAN_CTRL0 bit description C Bits R/W Initial value Mnemonic Description s 31:29 R/W 0 ING_PORT_CPRI_3 Port default CVLAN priority for received frames. o 28 RO 0 RESERVED r 27:16 R/W 0X1 PORT_DEFAULT_CVID_3 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from e this port. h 15:13 R/W 0 ING_PORT_SPRI_3 Port default SVLAN priority for received frames. t 12 RO 0 RESERVED A 11:0 R/W 0X1 PORT_DEFAULT_SVID_3 Port default VID. This field is used as tagged VID m added to untagged frames when transmitted from this port. 5.5.13 PORT3_VLAN_CTRL1 m Address offset: 0x043C lco Table 5-74 summarizes the port 3 VLAN control 1 register. aTable 5-74 PORT3_VLAN_CTRL1 bit description u Bits R/W Initial value Mnemonic Q 31:15 RO 0 RESERVED Description 14 R/W 0 EG_VLAN_TYPE_3 0 = All frames can be sent out. 1 = Only tagged frames can be sent out. 80-Y0619-1 Rev. A 119 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-74 PORT3_VLAN_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 13:12 R/W 11 RO 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3:2 R/W 3 0 0 0 0 0 1 0 0 0 ial EG_VLAN_MODE_3 Egress VLAN mode. 00 = Egress transmits frames unmodified 01 = Egress transmits frames without VLAN 10 = Egress transmits frames with VLAN 11 = Untouched t RESERVED SPCHECK_EN_3 1 = L3 Source port check enable en CORE_PORT_EN_3 0 = Edge port 1 = Core port id FORCE_DEFAULT_VID_EN_3 0 = Use frame tag only. f 1 = Force to use port default VID and priority for received frame, when 802.1q mode is not n disable. o PORT_TLS_MODE_3 0 = Port work at NON-TLS mode 1 = Port work at TLS mode C PORT_VLAN_PROP_EN_3 1 = Enable part-based VLAN propagate function. s PORT_CLONE_EN_3 0 = Enable port replace 1 = Enable port clone o VLAN_PRI_PRO_EN_3 1 = VLAN priority propagation enable Ather ING_VLAN_MODE_3 00 = All Frame can be received by this port, including untagged and tagged frames. 01 = Only frame with tag can be received by this port. 10 = Only frame untagged can be received by this port, including no VLAN and priority VLAN. 0 RO m0 RESERVED 11 = Reserved m 5.5.14 PORT6_VLAN_CTRL0 o Address offset: 0x0450 lcTable 5-75 summarizes the port 6 VLAN control 0 register. aTable 5-75 PORT6_VLAN_CTRL0 bit description u Bits R/W Initial value Mnemonic Q 31:29 R/W 0 ING_PORT_CPRI_6 Description Port default CVLAN priority for received frames. 28 RO 0 RESERVED 27:16 R/W 0X1 PORT_DEFAULT_CVID_6 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from this port. 80-Y0619-1 Rev. A 120 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-75 PORT6_VLAN_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 15:13 R/W 0 ING_PORT_SPRI_6 Port default SVLAN priority for received frames. 12 RO 0 RESERVED l 11:0 R/W 0X1 PORT_DEFAULT_SVID_6 Port default VID. This field is used as tagged VID added to untagged frames when transmitted from ia this port. nt 5.5.15 PORT6_VLAN_CTRL1 e Address offset: 0x0454 id Table 5-76 summarizes the port 6 VLAN control 1 register. nf Table 5-76 PORT6_VLAN_CTRL1 bit description o Bits R/W Initial value Mnemonic 31:15 RO 0 RESERVED C 14 R/W 0 EG_VLAN_TYPE_6 s 13:12 R/W 3 EG_VLAN_MODE_6 thero 11 RO 0 RESERVED A 10 R/W 0 SPCHECK_EN_6 Description 0 = All Frames can be sent out. 1 = Only tagged frames can be sent out. Egress VLAN mode. 00 = Egress transmits frames unmodified 01 = Egress transmits frames without VLAN 10 = Egress transmits frames with VLAN 11 = Untouched 1 = L3 source port check enable 9 R/W 0 CORE_PORT_EN_6 0 = Edge port 1 = Core port m 8 R/W 0 FORCE_DEFAULT_VID_ 0 = Use frame tag only. EN_6 1 = Force to use port default VID and priority for received frame, when 802.1q mode is not disable. om 7 R/W 0 PORT_TLS_MODE_6 0 = Port work at NON-TLS mode 1 = Port work at TLS mode lc6 R/W 1 PORT_VLAN_PROP_EN_6 1 = Enable part-based VLAN propagate function. a 5 R/W 0 PORT_CLONE_EN_6 0 = Enable port replace 1 = Enable port clone Qu 4 R/W 0 VLAN_PRI_PRO_EN_6 1 = VLAN priority propagation enable 80-Y0619-1 Rev. A 121 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-76 PORT6_VLAN_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 3:2 R/W 0 ING_VLAN_MODE_6 ntial 0 RO 0 RESERVED 00 = All frame can be received by this port, including untagged and tagged frames. 01 = Only frame with tag can be received by this port. 10 = Only frame untagged can be received by this port, including no VLAN and priority VLAN. 11 = Reserved ide 5.5.16 IPV4_PRI_BASE_ADDR f Address offset: 0x0470 n Table 5-77 summarizes the IPv4 private base address register. o Table 5-77 IPV4_PRI_BASE_ADDR bit description C Bits R/W Initial value Mnemonic Description s 31:0 R/W 32'hC0A80000 IPV4_PRI_BASE_ADDR Private IPv4 base address ro 5.5.17 IPV4_PRI_BASE_ADDR_MASK e Address offset: 0x0474 Ath Table 5-78 summarizes the IPv4 private base address mask register. Table 5-78 IPV4_PRI_BASE_ADDR_MASK bit description Bits R/W Initial value Mnemonic Description m 31:0 R/W 32'hFFFF0000 IPV4_PRI_BASE_ADDR_MASK Private IPv4 subnet mask om 5.6 Lookup control registers lcTable 5-79 summarizes the lookup registers. uaTable 5-79 Lookup register summary Q Offset range Name 0x0600–0x0608 ATU data register 0x060C ATU function register 0x0610–0x0614 VTU function register 80-Y0619-1 Rev. A 122 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-79 Lookup register summary (cont.) Offset range Name 0x0618 0x0620–0x0624 0x0628 0x0630–0x064C 0x0650 0x0654 0x0660 0x0664 0x0668 0x0678 0x067C 0x0680 0x0684 0x0688 0x068C 0x06A8 0x06AC 0x06B0 Trunk control registers 0x0700 0x0704 0x0708 ARL control register Global forward control register l Global learn limit control ia TOS priority mapping register t VLAN priority to priority map register Loop check result n Port0 lookup control register e Port0 priority control register id Port0 learn limit control register f Port2 lookup control register n Port2 priority control register Port2 learn limit control register o Port3 lookup control register C Port3 priority control register Port3 learn limit control register s Port6 lookup control register o Port6 priority control register r Port6 learn limit control register heTrunk control0 register tTrunk control1 register A Trunk control2 register m ACL registers 0x0710 ACL forward source filter register 0 0x0714 m0x0718 ACL forward source filter register 1 ACL forward source filter register 2 lco 5.6.1 ATU_DATA0 aAddress offset: 0x0600 Qu Table 5-80 summarizes the ATU data 0 register. Table 5-80 ATU_DATA0 bit description Bits R/W Initial value Mnemonic 31:0 R/WW 0 ATU_MAC_ADDR0 Description MAC address bits[31:0] 80-Y0619-1 Rev. A 123 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.6.2 ATU_DATA1 Address offset: 0x0604 Table 5-81 summarizes the ATU data 1 register. l Table 5-81 ATU_DATA1 bit description ia Bits R/W Initial value Mnemonic Description t 31 R/WW 0 ATU_HASH_HIGH_ MAC hash address maximum bit use for Get Next n ADDR e 30 R/WW 0 ATU_SA_DROP_EN Drop packet enable when source address is in this entry. If this bit is set to 1, the packet with SA of this id entry is dropped. 29 R/WW 0 ATU_MIRROR_EN 0 = Packets is send to destination port only. f 1 = Packets is send to mirror and destination port. n 28 R/WW 0 ATU_PRI_OVER_EN Priority override enable o 1 = ATU_PRI can override any other priority determined by the frame's data. C 27 R/WW 0 ATU_SVL_ENTRY 0 = IVL learned 1 = SVL learned s 26:24 R/WW 0 ATU_PRI This priority bits may be used as frame's priority when PRI_OVER_EN is set to one. ro 23 R/WW 0 ATU_CROSS_ 1 = ATU_CROSS_PORT_STATE enable PORT_STATE_EN e 22:16 R/WW 0 ATU_DES_PORT These bits indicate which ports are associated with this MAC address when they are set to 1. Ath 15:0 R/WW 0 ATU_MAC_ADDR1 MAC address bits[47:32] 5.6.3 ATU_DATA2 m Address offset: 0x0608 Table 5-82 summarizes the ATU data 2 register. om Table 5-82 TU_DATA2 bit description lcBits R/W Initial value Mnemonic a31:21 R/W 0 RESERVED Qu 20 R/W 0 WHITE_LIST_EN Description If the ARL entry is white list (ATU_STATUS = 4'hf and WHITE_LIST_EN is 1'b1), this entry can be updated when this source MAC address coming from other port. 19:8 R/W 0 ATU_VID This MAC address is the member of ATU_VID group. 7 R/W 0 ATU_SHORT_LOOP If learn engine find source port mismatch then set to 1, loop check engine clear it. 80-Y0619-1 Rev. A 124 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-82 TU_DATA2 bit description (cont.) Bits R/W Initial value Mnemonic Description 6 R/W 0 ATU_COPY_TO_CPU 1 = Packet received with this address is copied to CPU port. 5 R/W 0 ATU_REDIRECT_TO_ 1 = Packet received with this address is redirected to l CPU CPU port. If no CPU connected to switch, this frame is ia discarded. 4 R/W 0 ATU_LEAKY_EN 1 = Use leaky VLAN enable for this MAC address t This bit can be used for unicast and multicast frame, n control by ARL_UNI_LEAKY_EN and ARL_MULTI_ LEAKY_EN. nfide 3:0 R/W 0 ATU_STATUS 4'h0: Entry is empty 4'h1–4'h7: Entry is dynamic and valid. 4'h8–4'hE: Entry is dynamic and valid, can be age but can not be changed by any other address. 4'hF: Entry is static and is not aged or changed by hardware. Co 5.6.4 ATU_FUNC_REG s Address offset: 0x060C o Table 5-83 summarizes the ATU function register. er Table 5-83 ATU_FUNC_REG bit description h Bits R/W Initial value Mnemonic At 31 R/WSC 0 AT_BUSY Description Depend: AT_DONE, address table busy. This bit must be set to 1 to start an AT operation and cleared to 0 by hardware after the operation is done. If this bit 30:25 RO m0 24:22 R/W 0 m 21 RO 0 o 20:16 R/W 0 lc15 R/W 0 Qua 14 R/W 0 is 1 on read, CPU can not request another operation. RESERVED TRUNK_PORT_NUM Trunk port number. When CPU function is change trunk port, the AT_PORT_NUM in ARL bitmap is changed to TRUNK_PORT_NUM. RESERVED ATU_INDEX If ATU_TYPE is reserved ATU entry, this index is the address of reserved ATU entry. AT_VID_EN 1 = When CPU function is Get Next, the VID in the valid ARL entry must be equal to the VID set. AT_PORT_EN 1 = When CPU function is Get Next, the AT_PORT_ NUM must be in the destination port in the valid ARL entry. 13 R/W 0 AT_MULTI_EN 0 = All entries. 1 = When CPU function is Get Next, the high bytes of MAC address in the valid ARL entry must be 0x01005E or 0x3333. 80-Y0619-1 Rev. A 125 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-83 ATU_FUNC_REG bit description (cont.) Bits R/W Initial value Mnemonic Description 12 R/W 11:8 R/W 7:6 RO 5 R/W 4 R/W 3:0 R/W 0 0 0 0 0 0 AT_FULL_VIO ial AT_PORT_NUM nt RESERVED e ATU_TYPE id FLUSH_STATIC_EN Atheros Conf AT_FUNC ARL table full violation. This bit is set to 1 if the ARL table is full when CPU want to add a new entry to ARL table, and also be set to 1 if the ARL table is empty when CPU want to purge an entry to ARL table. Port number to be flushed. If AT_FUNC is set to 0101, lookup module must flush all unicast entries for the port. (or flush the port from ARL table) 0 = Normal ATU entry 1 = Reserved ATU entry 1 = When AT_FUNC set to 101, static entry in ARL table can be flushed. 0 = When AT_FUNC set to 101, only flush dynamic entry in ARL table. Address table operate function: 0000 = No operation. 0001 = Flush all entries. 0010 = Load an entry. If these bits are set to 010, CPU want to load an entry into ARL table. 0011 = Purge an entry. If these bits are set to 011, CPU want to purge an entry from ARL table. 0100 = Flush all unlocked entries in ARL. 0101 = Flush one port from ARL table 0110 =Get next valid or static entry in ARL table. If address and AT_STATUS and VID are all zero, hardware searches the first valid entry from entry0. If address is set to zero and AT_STATUS is not zero, m hardware searches next valid entry from entry which address is 48'h0. If hardware return back with address and AT_ STATUS and VID all zero, there's no other next valid entry in ARL table. m 0111 = Search MAC address 1000 = Change trunk port lco 5.6.5 VTU_FUNC_REG0 aAddress offset: 0x0610 Qu Table 5-84 summarizes the VTU function register 0. 80-Y0619-1 Rev. A 126 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-84 VTU_FUNC_REG0 bit description Bits R/W Initial value Mnemonic Description 31:21 RO 0 RESERVED l 20 R/WW 0 VTU_VALID 0 = Entry is empty 1 = Entry is valid tia 19 R/WW 0 VTU_IVL_EN 0 = VID is used to SVL, VID replaced by 0 when search MAC address. 1 = VID is used to IVL n 18 R/WW 0 VTU_LEARN_LOOKUP_ 0 = Normal operation about learn and final DP e DIS 1 = Not learn and not use ARL table DP to calculate final DP, but use UNI flood DP as ARL id DP to calculate DP f 17:4 R/WW 0 VTU_EG_VLAN_MODE E.g. bits[5:4] for port0, …bits[17:16] for port6 00 = Unmodified n 01 = Untagged o 10 = Tagged 11 = Not member C 3 R/WW 0 VTU_PRI_OVER_EN VLAN priority override enable s 2:0 R/WW 0 VTU_PRI This priority bits may be used as frame's priority when VTU_PRI_OVER_EN set to 1. ero 5.6.6 VTU_FUNC_REG1 h Address offset: 0x0614 At Table 5-85 summarizes the VTU function register 1. Table 5-85 VTU_FUNC_REG1 bit description m Bits R/W Initial value Mnemonic Description om 31 R/WSC 0 VT_BUSY Depend: VT_DONE, VLAN table busy. This bit must be set to 1 to start a VT operation and cleared to zero after operation done. If this bit is set to 1, CPU can not request another operation. 30:28 RO 0 RESERVED lc27:16 R/WW 0 VID Depend: VT_DONE,VT_CSR_VID[11:0], value of VLAN ID to be added or purged. a15:12 RO 0 RESERVED u 11:8 R/W 0 VT_PORT_NUM Port number Q 7:5 RO 0 RESERVED 4 R/OC 0 VT_FULL_VIO VLAN table full violation. This bit is set to 1 if the VLAN table is full when CPU want to add a new VID to VLAN table. 80-Y0619-1 Rev. A 127 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-85 VTU_FUNC_REG1 bit description (cont.) Bits R/W Initial value Mnemonic Description 3 RO onfidential 2:0 R/W 0 RESERVED 0 VT_FUNC VLAN table operate function. 000 = No operation. 001 = Flush all entries. 010 = Load an entry. If these bits are set to 3'b010, CPU loads an entry into VLAN table. 011 = Purge an entry. If these bits are set to 3'b011, CPU purges an entry from VLAN table. 100 = Remove an port from VLAN table. The port number which needs to be removed is indicated in VT_PORT_ NUM. 101 = Get next If VID is 12'b0 and VT_BUSY is set by software, hardware searches the first valid entry in VLAN table. If VID is 12'b0 and VT_BUSY is reset by hardware, there's no valid entry from VID set by software. 110 = Read one entry s C 5.6.7 ARL_CTRL o Address offset: 0x0618 r Table 5-86 summarizes the ARL control register. he Table 5-86 ARL_CTRL bit description At Bits R/W Initial value Mnemonic Description 31 R/W 1 INVALID_VLAN_IVL_SVL m 30 R/W 1 lcom 29 R/W 0 Qua 28 R/W 1 LEARN_CHANGE_EN IGMP_JOIN_LEAKY_EN IGMP_JOIN_NEW_EN 0 = SVL mode 1 = IVL mode The ARL searching mode when VLAN entry lookup is invalid. 0 = If hash violation occur when learning, no new address be learned to ARL. 1 = Enable new MAC address change old one if hash violation occur when learning IGMP join address leaky VLAN enable 0 = IGMP join address needn't be set to LEAKY_ EN in ARL table, bit[68] in ATU entry is set to 0. 1 = IGMP join address is set to LEAKY_EN in ARL table, bit[68] in ATU entry is set to 1. 1 = Enable hardware add new address to ARL table when received IGMP/MLD join frame, and remove address from ARL when received IGMP/MLD leave frame. 27 R/W 0 IGMP_JOIN_PRI_ REMAP_EN Use for IGMP packet learn in ARL table, define DA priority remap enable (ATU[60]) 80-Y0619-1 Rev. A 128 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-86 ARL_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 26:24 R/W 23:20 R/W ial 19 R/W nt 18:16 R/W Confide 15:0 R/W 3’b0 IGMP_JOIN_PRI 4’hE IGMP_JOIN_STATUS 1 AGE_EN 0 LOOP_CHECK_TIMER ‘h2B AGE_TIME Use for IGMP packet learn in ARL table, define DA priority (ATU[59:57]) Use for IGMP packet learn in ARL table, define the status (ATU[67:64]) Enable age operation 1 = Lookup module can age the address in the address table. 3'h0 = Disable loop back check 3'h1 = 1 ms 3'h2 = 10 ms 3'h3 = 100 ms 3'h4 = 500 ms 3'h5–3'h7 = Reserved Address table age timer. These bits determine the time that each entry remains valid in the address table, since last accessed. For the time is times 7s, maximum age time is about 10,000 minutes. The default value is 'h2B for five minutes. If AGE_ EN is set to 1, these bits shouldn't be set to zero. os 5.6.8 GLOBAL_FW_CTRL0 er Address offset: 0x0620 h Table 5-87 summarizes the global forward control 0 register. At Table 5-87 GLOBAL_FW_CTRL0 bit description Bits R/W Initial value Mnemonic 31:28 RO 0 RESERVED m 27:26 R/W 0 ARP_FORWARD_ACT om 25:24 R/W 0 SP_NOT_FOUND_ACT Qualc23:22 R/W 0 ARP_SP_NOT_FOUND_ACT Description 0 = Redirect to CPU 1 = Copy to CPU 2 = Forward For IP packet 0 = Forward 1 = Drop 2 = To CPU For ARP packet 0 = Forward 1 = Drop 2 = To CPU 21 RO 0 RESERVED 80-Y0619-1 Rev. A 129 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-87 GLOBAL_FW_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 20 R/W 19 R/W 18 RO 17 R/W 16 RO 15 RO 14 R/W 13 R/W 12 R/W 1 0 0 0 0 0 0 0 0 HASH_MODE Hash mode for MAC address 0 = crc_16 1 = crc_10 ial ARP_REQ_UNI The destination port of ARP request is only ROUTER_DP in ARP table. t RESERVED n NAT_NOT_FOUND_DROP_EN 0 = To CPU 1 = Drop e RESERVED id RESERVED Conf IGMP_LEAVE_DROP_EN IGMP/MLD leave packet. After updated the port map of ARL (IGMP/MLD group address). If port map in ARL is not empty, 0 = Forward to IGMP_JOIN_LEAVE_DP 1 = Drop this packet eros ARL_UNI_LEAKY_EN 0 = Ignore LEAKY_EN bit in ARL table to control unicast frame leaky VLAN. Only use port-based UNI_LEAKY_EN to control unicast frame leaky VLAN. 1 = Use LEAKY_EN bit in ARL table to control unicast frame leaky VLAN, and ignore UNI_ LEAKY_EN. Ath ARL_MULTI_LEAKY_EN 0 = Ignore LEAKY_EN bit in ARL table to control multicast frame leaky VLAN. Only use port-based MULTI_LEAKY_EN to control multicast frame leaky VLAN. m 1 = Use LEAKY_EN bit in ARL table to control multicast frame leaky VLAN, and ignore MULTI_LEAKY_EN. 11 R/W 0 om 10 R/W 0 alc9 RO 0 Qu 8 R/W 0 MANAGE_VID_VIO_DROP_EN 0 = Management frame transmit out if VLAN violation occurs. 1 = Management frame is drop if VLAN violation occurs. CPU_PORT_EN 0 = No CPU connect to switch 1 = CPU is connected to port0 If this bit is set to 1, HEAD_EN of MAC0 is set to 1. RESERVED PPPOE_REDIRECT_EN PPPoE discovery frame redirect to CPU enable. 1 = PPPoE discovery frame is redirected to CPU port. 0 = PPPoE discovery frame is transmitted as normal frame. 80-Y0619-1 Rev. A 130 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-87 GLOBAL_FW_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 7:4 R/W 0xF MIRROR_PORT_NUM ial 3 R/W 0 IGMP_COPY_EN ent 2 R/W 0 RIP_COPY_EN id 1 R/W 0 RESERVED nf 0 R/W 0 EAPOL_REDIRECT_EN Port number which packet is mirrored to. 4'h0 is port0, etc. If value is more than 6, no mirror port connected to switch. 0 = QM redirects IGMP/MLD frame to CPU port. 1 = QM copies IGMP/MLD frame to CPU port. This IGMP does not include the IGMP join/leave packet 0 = Do not copy RIPv1 frame to CPU 1 = Copy RIPv1 frame to CPU 0 = 802.1x frame copy to CPU 1 = 802.1x frame redirect to CPU Co 5.6.9 GLOBAL_FW_CTRL1 s Address offset: 0x0624 o Table 5-89 summarizes the global forward control 1 register. er Table 5-88 GLOBAL_FW_CTRL1 bit description h Bits R/W Initial value Mnemonic t 31 RO 0 RESERVED A 32:24 R/W 7'b0 IGMP_JOIN_LEAVE_DP Description If MAC receive IGMP/MLD, fast join or leave m 23 RO m 22:16 R/W 0 7'h7E o15 RO lc14:8 R/W 0 7'h7E ua 7 RO Q 6:0 R/W 0 7'h7E RESERVED BROAD_DP RESERVED MULTI_FLOOD_DP RESERVED UNI_FLOOD_DP frame is sent due to these bits map destination port. Notes: CPU port can cross VLAN if port bit map set to 1. If MAC receives broadcast frame, use these bits to determine destination port. If MAC receives unknown multicast frame whose DA is not contained in ARL table, use these bits to determine destination port. If MAC receives unknown unicast frame whose DA is not contained in ARL table, use these bits to determine destination port. 80-Y0619-1 Rev. A 131 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.6.10 GOL_LEARN_LIMIT Address offset: 0x0628 Table 5-89 summarizes the global learn limit control register. l Table 5-89 GLOBAL_FW_CTRL1 bit description ia Bits R/W Initial value Mnemonic Description t 31:14 RO 0 RESERVED n 13 R/W 0 GOL_SA_LEARN_LIMIT_DROP_EN 1 = If SA is not in ARL table, packet is e dropped when global learned MAC address counter is equal to GOL_SA_ id LEARN_CNT; 0 = If SA is not in ARL table or SA in ARL f but port member is not the source port, packet is redirected to CPU when n learned MAC address counter is equal to GOL_SA_LEARN_CNT. o 12 R/W 0 GOL_SA_LEARN_LIMIT_EN 1 = Global SA learn limit enable C 11:0 R/W 0 GOL_SA_LEARN_CNT Global MAC address can be learned to ARL. When learn new MAC address + 1, age - 1. ros 5.6.11 TOS_PRI_MAP_REG0 e Address offset: 0x0630 Ath Table 5-90 summarizes the TOS/TC priority mapping register 0. m Table 5-90 TOS_PRI_MAP_REG0 bit description Bits R/W Initial value Mnemonic 31:28 R/W 27:24 R/W m 23:20 R/W o19:16 R/W lc15:12 R/W 11:8 R/W a 7:4 R/W Qu 3:0 R/W 0 0 0 0 0 0 0 0 TOS_MAP_0X1C TOS_MAP_0X18 TOS_MAP_0X14 TOS_MAP_0X10 TOS_MAP_0X0C TOS_MAP_0X08 TOS_MAP_0X04 TOS_MAP_0X00 Description See bits[3:0] Bit[3]: DEI Bits[2:0] Priority 5.6.12 TOS_PRI_MAP_REG1 Address offset: 0x0634 80-Y0619-1 Rev. A 132 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-91 summarizes the TOS/TC priority mapping register 1. Table 5-91 TOS_PRI_MAP_REG1 bit description Bits R/W Initial value Mnemonic l 31:28 R/W 0x1 TOS_MAP_0X3C ia 27:24 R/W 0x1 TOS_MAP_0X38 t 23:20 R/W 0x1 TOS_MAP_0X34 19:16 R/W 0x1 TOS_MAP_0X30 n 15:12 R/W 0x1 TOS_MAP_0X2C e 11:8 R/W 0x1 TOS_MAP_0X28 id 7:4 R/W 0x1 TOS_MAP_0X24 f 3:0 R/W 0x1 TOS_MAP_0X20 Description See bits[3:0] of TOS_PRI_MAP_REG0 on 5.6.13 TOS_PRI_MAP_REG2 C Address offset: 0x0638 Table 5-92 summarizes the TOS/TC priority mapping register 2. ros Table 5-92 TOS_PRI_MAP_REG2 bit description e Bits R/W Initial value Mnemonic 31:28 R/W 0x2 TOS_MAP_0X5C th 27:24 R/W 0x2 TOS_MAP_0X58 A 23:20 R/W 0x2 TOS_MAP_0X54 Description See bits[3:0] of TOS_PRI_MAP_REG0 19:16 15:12 R/W R/W m0x2 0x2 TOS_MAP_0X50 TOS_MAP_0X4C 11:8 R/W 7:4 R/W m 3:0 R/W 0x2 TOS_MAP_0X48 0x2 TOS_MAP_0X44 0x2 TOS_MAP_0X40 lco 5.6.14 TOS_PRI_MAP_REG3 aAddress offset: 0x063C Qu Table 5-93 summarizes the TOS/TC priority mapping register 3. 80-Y0619-1 Rev. A 133 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-93 TOS_PRI_MAP_REG3 bit description Bits R/W Initial value Mnemonic Description 31:28 R/W l 27:24 R/W ia 23:20 R/W 19:16 R/W t 15:12 R/W n 11:8 R/W e 7:4 R/W id 3:0 R/W 0x3 TOS_MAP_0X7C See bits[3:0] of TOS_PRI_MAP_REG0 0x3 TOS_MAP_0X78 0x3 TOS_MAP_0X74 0x3 TOS_MAP_0X70 0x3 TOS_MAP_0X6C 0x3 TOS_MAP_0X68 0x3 TOS_MAP_0X64 0x3 TOS_MAP_0X60 nf 5.6.15 TOS_PRI_MAP_REG4 o Address offset: 0x0640 C Table 5-94 summarizes the TOS/TC priority mapping register 4. s Table 5-94 TOS_PRI_MAP_REG4 bit description o Bits r 31:28 e 27:24 h 23:20 At 19:16 R/W Initial value Mnemonic R/W 0x4 TOS_MAP_0X9C R/W 0x4 TOS_MAP_0X98 R/W 0x4 TOS_MAP_0X94 R/W 0x4 TOS_MAP_0X90 Description See bits[3:0] of TOS_PRI_MAP_REG0 15:12 R/W 0x4 TOS_MAP_0X8C 11:8 R/W m 7:4 R/W 3:0 R/W 0x4 TOS_MAP_0X88 0x4 TOS_MAP_0X84 0x4 TOS_MAP_0X80 om 5.6.16 TOS_PRI_MAP_REG5 lcAddress offset: 0x0644 QuaTable 5-95 summarizes the TOS/TC priority mapping register 5. 80-Y0619-1 Rev. A 134 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-95 TOS_PRI_MAP_REG5 bit description Bits R/W Initial value Mnemonic Description 31:28 R/W l 27:24 R/W ia 23:20 R/W 19:16 R/W t 15:12 R/W n 11:8 R/W e 7:4 R/W id 3:0 R/W 0x5 TOS_MAP_0XBC See bits[3:0] of TOS_PRI_MAP_REG0 0x5 TOS_MAP_0XB8 0x5 TOS_MAP_0XB4 0x5 TOS_MAP_0XB0 0x5 TOS_MAP_0XAC 0x5 TOS_MAP_0XA8 0x5 TOS_MAP_0XA4 0x5 TOS_MAP_0XA0 nf 5.6.17 TOS_PRI_MAP_REG6 o Address offset: 0x0648 C Table 5-96 summarizes the TOS/TC priority mapping register 6. s Table 5-96 TOS_PRI_MAP_REG6 bit description o Bits R/W Initial value Mnemonic r 31:28 R/W 0x6 TOS_MAP_0XDC e 27:24 R/W 0x6 TOS_MAP_0XD8 h 23:20 R/W 0x6 TOS_MAP_0XD4 At 19:16 R/W 0x6 TOS_MAP_0XD0 Description See bits[3:0] of TOS_PRI_MAP_REG0 15:12 R/W 0x6 TOS_MAP_0XCC 11:8 R/W m 7:4 R/W 3:0 R/W 0x6 TOS_MAP_0XC8 0x6 TOS_MAP_0XC4 0x6 TOS_MAP_0XC0 om 5.6.18 TOS_PRI_MAP_REG7 lcAddress offset: 0x064C QuaTable 5-97 summarizes the TOS/TC priority mapping register 7. 80-Y0619-1 Rev. A 135 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-97 TOS_PRI_MAP_REG7 bit description Bits R/W Initial value Mnemonic Description 31:28 R/W l 27:24 R/W ia 23:20 R/W 19:16 R/W t 15:12 R/W n 11:8 R/W e 7:4 R/W id 3:0 R/W 0x7 TOS_MAP_0XFC 0x7 TOS_MAP_0XF8 0x7 TOS_MAP_0XF4 0x7 TOS_MAP_0XF0 0x7 TOS_MAP_0XEC 0x7 TOS_MAP_0XE8 0x7 TOS_MAP_0XE4 0x7 TOS_MAP_0XE0 See bits[3:0] of TOS_PRI_MAP_REG0 nf 5.6.19 VLAN_PRI_MAP_REG0 o Address offset: 0x0650 C Table 5-98 summarizes the VLAN priority to priority mapping register 0. s Table 5-98 VLAN_PRI_MAP_REG0 bit description o Bits r 31:28 e 27:24 h 23:20 At 19:16 R/W Initial value Mnemonic R/W 7 VLAN_MAP_0X7 R/W 6 VLAN_MAP_0X6 R/W 5 VLAN_MAP_0X5 R/W 4 VLAN_MAP_0X4 Description See bits[3:0] of VLAN_PRI_MAP_REG0 15:12 R/W 3 VLAN_MAP_0X3 11:8 R/W m 7:4 R/W 3:0 R/W 2 VLAN_MAP_0X2 1 VLAN_MAP_0X1 0 VLAN_MAP_0X0 om 5.6.20 LOOP_CHECK_RESULT lcAddress offset: 0x0654 aTable 5-99 summarizes the loop check result register. Qu Table 5-99 LOOP_CHECK_RESULT bit description Bits R/W Initial value Mnemonic Description 31:8 RO 0 RESERVED 80-Y0619-1 Rev. A 136 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-99 LOOP_CHECK_RESULT bit description (cont.) Bits R/W Initial value Mnemonic Description 7:4 RO l 3:0 RO 0 PORT_NUM_NEW When hardware checked loop occur, these bits indicate MAC address new port number. 0 PORT_NUM_OLD When hardware checked loop occur, these bits indicate MAC address old port number. tia 5.6.21 PORT0_LOOKUP_CTRL n Address offset: 0x0660 e Table 5-100 summarizes the port 0 lookup control register. fid Table 5-100 PORT0_LOOKUP_CTRL bit description n Bits R/W Initial value Mnemonic Description o 31 R/W 0 MULTICAST_DROP_ 1 = Drop the multicast packet from this port. Do not drop EN_0 IGMP/MLD join/leave and special DIP packet. C 30:29 RO 0 RESERVED 28 R/W 0 UNI_LEAKY_EN_0 Unicast frame leaky VLAN enable. sUse ARL_UNI_LEAKY_EN and LEAKY_EN bit in ARL otable to control unicast leaky VLAN. rWhen ARL_UNI_LEAKY_EN is set to zero, only UNI_ LEAKE_EN control unicast frame leaky VLAN. e If ARL_UNI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be h forward as leaky VLAN, ignore UNI_LEAKY_EN. t If MAC receives unicast frame from this port which forwards as leaky VLAN, the frame could be switched to A destination port defined in ARL table and cross all VLAN 27 R/W 0 MULTI_LEAKY_EN_ m0 Qualcom 26 R/W 0 ARP_LEAKY_EN_0 (include part-based and 802.1q). Use ARL_MULTI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_MULTI_LEAKY_EN is set to zero, only MULTI_LEAKY_EN control multicast frame leaky VLAN. If ARL_MULTI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore MULTI_LEAKY_EN. If MAC receives multicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based VLAN and 802.1q). 0 = ARP frame can not cross VLAN ingress port mirror. If this bit is set to 1, all packets received from this port are copied to mirror port. 1 = If MAC receive ARP frame from this port, it can cross all VLAN (include part-based VLAN and 802.1q). 25 R/W 0 NG_MIRROR_EN_0 Ingress port mirror. If this bit is set to 1, all packets received from this port is copied to mirror port. 80-Y0619-1 Rev. A 137 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-100 PORT0_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 24 RO 23 RO 22 RO 21 R/W 20 R/W 19 RO 18:16 R/W 0 0 0 0 1 0 3'h4 RESERVED RESERVED l RESERVED ia PORT_LOOPBACK_ t EN_0 0 = Normal forwarding 1 = Loop back. Packet sent in from this port is sent out from the same port. This packet is not sent to other ports. iden LEARN_EN_0 Enable learn operation 0 = Do not learn new MAC address to ARL table 1 = Enable hardware learn new MAC address into ARL table. f RESERVED Atheros Con PORT_STATE_0 Port state.These bits are used to manage the port to determine what kind of frames are allowed to enter or leave the port for simple bridge loop detection or 803.1D Spanning Tree. 000 = Disable mode. The port is completely disabled, and can not receive or transmit any frames. 001 = Blocking mode. In this state, the port forwards received management frames to the designed port only. Any other frames can not be transmitted or received by the port, and without learning any SA address. 010 = Listening mode. In this state, the port receives and transmits only management frames, but without learning any SA address. Any other frames can not be transmitted or received by the port. 011 = Learning mode. In this state, the port learns all SA, and discards all frames except management frames, and only management frames allowed to be m 15 RO 0 m 14:12 RO 0 11 RO 0 Qualco10 R/W 0 RESERVED RESERVED RESERVED FORCE_PORT_ VLAN_EN_0 transmitted out. 100 = Forward mode. In this state, the port learns all SA, transmits and receives all frames like normal. 1 = Force to use port-based VLAN enable. If this bit is set to 1, use port-based VLAN & VLAN table result to determine destination port. 80-Y0619-1 Rev. A 138 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-100 PORT0_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description ential 9:8 R/W 00 VLAN_MODE_0 802.1q mode for this port. 00 = 802.1q disable. Use port-based VLAN only. 01 = Fallback. Enable 802.1q for all received frames. Do not discard ingress membership violation and use the port-based VLAN if the frame's VID is not contained in VLAN table. 10 = Check. Enable 802.1q for all received frames. Do not discard ingress membership violation but discard frames which VID is not contained in VLAN table. 11 = Secure. Enable 802.1q for all received frames. Discard frames with ingress membership violation or whose VID is not contained in the VLAN table. id 7 RO 0 RESERVED f 6:0 R/W 'h7E PORT_VID_MEM_0 Port-based VLAN member. Each bit restricts which port n can send frames to. To send frames to port0, bit[16] must be set to 1, etc. These bits are set to 1 after reset o except the port's bit. This prevents frames going out the port they received in. s C 5.6.22 PORT0_PRI_CTRL o Address offset: 0x0664 r Table 5-101 summarizes the port 0 priority control register. he Table 5-101 PORT0_PRI_CTRL bit description At Bits R/W Initial value Mnemonic Description 31:21 RO 20 R/W m0 0 19 RO m 18 R/W 17 R/W o16 R/W lc15:8 RO Qua 7:6 R/W 0 0 0 0 0 0 RESERVED EG_MAC_BASE_ VLAN_EN_0 RESERVED DA_PRI_EN_0 VLAN_PRI_EN_0 IP_PRI_EN_0 RESERVED DA_PRI_SEL_0 Enable egress MAC-based VLAN 1 = DA priority can be used for QoS. 1= VLAN priority can be used for QoS. 1 = TOS/TC can be used for QoS. DA priority selected level for QoS. There are five levels of priority for QoS. The highest is priority in packet header. The others are selected by these bits. If these bits are set to zero, DA priority is selected after header. If these bits are set to n, DA priority is selected after the priority set to n-1. 5:4 R/W 1 VLAN_PRI_SEL_0 VLAN priority selected level for QoS. 80-Y0619-1 Rev. A 139 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-101 PORT0_PRI_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 3:2 R/W 1:0 RO 2 IP_PRI_SEL_0 IP priority selected level for QoS. 0 RESERVED ial 5.6.23 PORT0_LEARN_LIMIT t Address offset: 0x0668 n Table 5-102 summarizes the port 0 learn limit control register. ide Table 5-102 PORT0_LEARN_LIMIT bit description f Bits R/W Initial value Mnemonic Description n 31:30 RO 0 RESERVED o 29 R/W 0 IGMP_LEARN_LIMIT_ DROP_EN_0 Drop or redirect the ingress frame to CPU when new group address coming but learned group address already reach the limitation C 28 R/W 0 SA_LEARN_LIMIT_DROP_ Drop or redirect the ingress frame to CPU when EN_0 new SA coming but learned SA already reach the slimitation o 27 R/W 0 IGMP_LEARN_LIMIT_EN_0 1 = IGMP Learn Limit enable. er 26:16 R/W 0 IGMP_JOIN_CNT_0 Hardware join IGMP. When join new entry or new port to IGMP + 1, leave or age - 1. 15:12 R/W 7 SA_LEARN_STATUS_0 If less than 0x7, dynamic can be fresh to setting h value and age. t 11 R/W 0 SA_LEARN_LIMIT_EN_0 1 = SA learn limit enable A 10:0 R/W 0 SA_LEARN_CNT_0 The MAC address can be learned and written to the ARL table — only dynamic entry is counted 0: Indicate the MAC limit number is 0 m 1: Indicate the MAC limit number is 1 2: Indicate the MAC limit number is 2 m ... and so on... until: 1024: Indicate the MAC limit is 1024 lco 5.6.24 PORT2_LOOKUP_CTRL aAddress offset: 0x0678 Qu Table 5-103 summarizes the port 2 lookup control register. 80-Y0619-1 Rev. A 140 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-103 PORT2_LOOKUP_CTRL bit description Bits R/W Initial value Mnemonic Description 31 R/W 30:29 RO 28 R/W 27 R/W 26 R/W 0 0 0 0 0 MULTICAST_ DROP_EN_2 1 = Drop the multicast packet from this port. Do not drop IGMP/MLD join/leave and special DIP packet. l RESERVED nfidentia UNI_LEAKY_EN_2 Unicast frame leaky VLAN enable. Also use ARL_UNI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_UNI_LEAKY_EN is set to zero, only UNI_ LEAKE_EN control unicast frame leaky VLAN. If ARL_UNI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore UNI_LEAKY_EN. If MAC receive unicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based and 802.1q). o MULTI_LEAKY_ theros C EN_2 Multicast frame leaky VLAN enable. Also use ARL_MULTI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_MULTI_LEAKY_EN is set to zero, only MULTI_LEAKY_EN control multicast frame leaky VLAN. If ARL_MULTI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore MULTI_LEAKY_EN. If MAC receive multicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based VLAN and 802.1q). ARP_LEAKY_EN_ 0 = ARP frame can not cross VLAN A2 1 = If MAC receive ARP frame from this port, it can cross 25 R/W m0 ING_MIRROR_ all VLAN (include part-based VLAN and 802.1q). Ingress port mirror. If this bit is set to 1, all packets 24:22 RO 0 m 21 R/W 0 lco20 R/W 1 Qua 19 RO 0 EN_2 received from this port is copied to mirror port. RESERVED PORT_ 0 = Normal forwarding LOOPBACK_EN_2 1 = Loop back. Packet sent in from this port is sent out from the same port. This packet is not sent to other ports LEARN_EN_2 Enable learn operation 0 = Not learn new MAC address to ARL table 1 = Enable hardware learn new MAC address into ARL table. RESERVED 80-Y0619-1 Rev. A 141 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-103 PORT2_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 18:16 R/W 15 RO 14:12 RO 11 RO 10 R/W 9:8 R/W 3'h4 0 0 0 0 00 PORT_STATE_2 Confidential RESERVED s RESERVED o RESERVED r FORCE_PORT_ VLAN_EN_2 Athe VLAN_MODE_2 Port state. These bits are used to manage the port to determine what kind of frames are allowed to enter or leave the port for simple bridge loop detection or 803.1D spanning tree. 3'b000 = Disable mode. The port is completely disable, and cannot receive or transmit any frames. 3'b001 = Blocking mode. In this state, the port forwards received management frames to the designed port only. Any other frames cannot be transmitted or received by the port, and without learning any SA address. 3'b010 = Listening mode. In this state, the port receives and transmits only management frames, but without learning any SA address. Any other frames cannot be transmitted or received by the port. 3'b011 = Learning mode. In this state, the port learns all SA, and discards all frames except management frames, and only management frames are allowed to be transmitted out. 3'b100 = Forward mode. In this state, the port learns all SA, transmits and receives all frames like normal. 1 = Force to use port-based VLAN enable. If this bit is set to 1, use port-based VLAN and VLAN table result to determine destination port. 802.1q mode for this port. 00 = 802.1q disable. Use part-based VLAN only. 01 = Fallback. Enable 802.1q for all received frames. Do not discard ingress membership violation and use the m lcom 7 R/W 0' Qua 6:0 R/W h7B RESERVED PORT_VID_MEM_ 2 part-based VLAN if the frame's VID is not contained in VLAN table. 10 = Check. Enable 802.1q for all received frames. Do not discard ingress membership violation but discard frames which VID is not contained in VLAN table. 11 = Secure. Enable 802.1q for all received frames. Discard frames with ingress membership violation or whose VID is not contained in the VLAN table. Port-based VLAN member. Each bit restricts which port can send frames to.To send frames to port0, bit[16] must be set to 1, etc. These bits are set to one after reset except the port's bit. This prevents frames going out the port they received in. 5.6.25 PORT2_PRI_CTRL Address offset: 0x067C 80-Y0619-1 Rev. A 142 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-104 summarizes the port 2 priority control register. Table 5-104 PORT2_PRI_CTRL bit description Bits R/W Initial value Mnemonic Description l 31:21 RO 0 RESERVED ia 20 R/W 0 EG_MAC_BASE_ Enable egress MAC-based VLAN VLAN_EN_2 t 19 RO 0 RESERVED n 18 R/W 0 DA_PRI_EN_2 1 = DA priority can be used for QoS. e 17 R/W 0 VLAN_PRI_EN_2 1 = VLAN priority can be used for QoS. id 16 R/W 0 IP_PRI_EN_2 1 = TOS/TC can be used for QoS. 15:8 RO 0 RESERVED f 7:6 R/W 0 DA_PRI_SEL_2 DA priority selected level for QoS. n There are five levels of priority for QoS.The highest is priority in packet header. The others are selected by these o bits. If these bits are set to zero, DA priority is selected after header. If these bits are set to n, DA priority is selected after C the priority set to n-1. 5:4 R/W 1 VLAN_PRI_SEL_2 VLAN priority selected level for QoS. s 3:2 R/W 2 IP_PRI_SEL_2 IP priority selected level for QoS. o 1:0 RO 0 RESERVED er 5.6.26 PORT2_LEARN_LIMIT th Address offset: 0x0680 A Table 5-105 summarizes the port 2 learn limit control register. m Table 5-105 PORT2_LEARN_LIMIT bit description Bits R/W Initial value Mnemonic m 31:30 RO 0 RESERVED o29 R/W 0 IGMP_LEARN_LIMIT_DROP_EN_ 2 alc28 R/W 0 SA_LEARN_LIMIT_DROP_EN_2 Qu 27 R/W 0 IGMP_LEARN_LIMIT_EN_2 Description Drop or redirect the ingress frame to CPU when new group address coming but learned group address already reach the limitation Drop or redirect the ingress frame to CPU when new SA coming but learned SA already reach the limitation 1 = IGMP learn limit enable. 26:16 R/W 0 IGMP_JOIN_CNT_2 Hardware join IGMP. When join new entry or new port to IGMP + 1, leave or age - 1. 15:12 R/W 7 SA_LEARN_STATUS_2 If less than 0x7, dynamic can be fresh to setting value and age. 80-Y0619-1 Rev. A 143 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-105 PORT2_LEARN_LIMIT bit description (cont.) Bits R/W Initial value Mnemonic Description 11 R/W 0 SA_LEARN_LIMIT_EN_2 ntial 10:0 R/W 0 SA_LEARN_CNT_2 1 = SA Learn Limit enable. The MAC address can be learned and written to the ARL table — only dynamic entry is counted 0: Indicate the MAC limit number is 0 1: Indicate the MAC limit number is 1 2: Indicate the MAC limit number is 2 ... and so on... until: 1024: Indicate the MAC limit is 1024 fide 5.6.27 PORT3_LOOKUP_CTRL n Address offset: 0x0684 o Table 5-106 summarizes the port 3 lookup control register. C Table 5-106 PORT3_LOOKUP_CTRL bit description s Bits R/W Initial value Mnemonic o 31 R/W 0 MULTICAST_DROP_ EN_3 r 30:29 RO 0 RESERVED Athe 28 R/W 0 UNI_LEAKY_EN_3 Description 1 = Drop the multicast packet from this port. Do not drop IGMP/MLD join/leave and Special DIP packet. Unicast frame leaky VLAN enable. Also use ARL_UNI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_UNI_LEAKY_EN is set to zero, only UNI_ LEAKE_EN control unicast frame leaky VLAN. m Qualcom 27 R/W 0 MULTI_LEAKY_EN_3 If ARL_UNI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore UNI_LEAKY_EN. If MAC receive unicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based and 802.1q). Multicast frame leaky VLAN enable. Also use ARL_MULTI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_MULTI_LEAKY_EN is set to zero, only MULTI_LEAKY_EN control multicast frame leaky VLAN. If ARL_MULTI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore MULTI_LEAKY_EN. If MAC receive multicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based VLAN and 802.1q). 80-Y0619-1 Rev. A 144 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-106 PORT3_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 26 R/W 25 R/W 24 RO 23 RO 22 RO 21 R/W 20 R/W 19 RO 18:16 R/W 0 0 0 0 0 0 1 0 3'h4 ARP_LEAKY_EN_3 l ING_MIRROR_EN_3 tia RESERVED RESERVED n RESERVED e PORT_LOOPBACK_ id EN_3 nf LEARN_EN_3 Co RESERVED Atheros PORT_STATE_3 0 = ARP frame can not cross VLAN 1 = If MAC receive ARP frame from this port, it can cross all VLAN (include part-based VLAN and 802.1q). Ingress port mirror. If this bit is set to 1, all packets received from this port is copied to mirror port. 0 = Normal forwarding 1 = Loop back. Packet sent in from this port is sent out from the same port. This packet is not sent to other ports. Enable learn operation 0 = Do not learn new MAC address to ARL table 1 = Enable hardware learn new MAC address into ARL table. Port state. These bits are used to manage the port to determine what kind of frames are allowed to enter or leave the port for simple bridge loop detection or 803.1D Spanning Tree. 000 = Disable mode. The port is completely disabled, and can not receive or transmit any frames. 001 = Blocking mode. In this state, the port forwards received management frames to the designed port only. Any other frames can not be transmitted or received by the port, and without learning any SA address. m lcom 15 RO 0 a14:12 RO 0 u 11 RO 0 Q 10 R/W 0 RESERVED RESERVED RESERVED FORCE_PORT_ VLAN_EN_3 010 = Listening mode. In this state, the port receives and transmits only management frames, but without learning any SA address. Any other frames can not be transmitted or received by the port. 011 = Learning mode. In this state, the port learns all SA, and discards all frames except management frames, and only management frames allowed to be transmitted out. 100 = Forward mode. In this state, the port learns all SA, transmits and receives all frames like normal. 1 = Force to use part-based VLAN enable. If this bit is set to 1, use part-based VLAN & VLAN table result to determine destination port. 80-Y0619-1 Rev. A 145 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-106 PORT3_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 9:8 R/W idential 7 R/W onf 6:0 R/W 00 0 0x77 VLAN_MODE_3 RESERVED PORT_VID_MEM_3 802.1q mode for this port. 00 = 802.1q disable. Use part-based VLAN only. 01 = Fallback. Enable 802.1q for all received frames. Do not discard ingress membership violation and use the part-based VLAN if the frame's VID is not contained in VLAN table. 10 = Check. Enable 802.1q for all received frames. Do not discard ingress membership violation but discard frames which VID is not contained in VLAN table. 11 = Secure. Enable 802.1q for all received frames. Discard frames with ingress membership violation or whose VID is not contained in the VLAN table. Port-based VLAN member. Each bit restricts which port can send frames to. To send frames to port0, bit[16] must be set to 1, etc.These bits are set to one after reset except the port's bit. This prevents frames going out the port they received in. s C 5.6.28 PORT3_PRI_CTRL o Address offset: 0x0688 r Table 5-107 summarizes the port 3 priority control register. he Table 5-107 PORT3_PRI_CTRL bit description At Bits R/W Initial value Mnemonic Description 31:21 RO 20 R/W m0 RESERVED 0 EG_MAC_BASE_ VLAN_EN_3 19 RO 0 m 18 R/W 0 17 R/W 0 o16 R/W 0 lc15:8 RO 0 Qua 7:6 R/W 0 RESERVED DA_PRI_EN_3 VLAN_PRI_EN_3 IP_PRI_EN_3 RESERVED DA_PRI_SEL_3 Enable egress MAC-based VLAN 1 = DA priority can be used for QoS. 1 = VLAN priority can be used for QoS. 1 = TOS/TC can be used for QoS. DA priority selected level for QoS. There are five levels of priority for QoS.The highest is priority in packet header. The others are selected by these bits. If these bits are set to zero, DA priority is selected after header. If these bits are set to n, DA priority is selected after the priority set to n-1. 5:4 R/W 1 VLAN_PRI_SEL_3 VLAN priority selected level for QoS. 80-Y0619-1 Rev. A 146 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-107 PORT3_PRI_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 3:2 R/W 2 IP_PRI_SEL_3 1:0 RO 0 RESERVED IP priority selected level for QoS. ial 5.6.29 PORT3_LEARN_LIMIT t Address offset: 0x068C n Table 5-108 summarizes the port 3 learn limit control register. ide Table 5-108 PORT3_LEARN_LIMIT bit description f Bits R/W Initial value Mnemonic Description n 31:30 RO 0 RESERVED o 29 R/W 0 IGMP_LEARN_LIMIT_ DROP_EN_3 Drop or redirect the ingress frame to CPU when new group address coming but learned group address already reach the limitation C 28 R/W 0 SA_LEARN_LIMIT_DROP_ Drop or redirect the ingress frame to CPU when EN_3 new SA coming but learned SA already reach sthe limitation o 27 R/W 0 IGMP_LEARN_LIMIT_EN_3 1 = IGMP learn limit enable. er 26:16 R/W 0 IGMP_JOIN_CNT_3 Hardware join IGMP. When join new entry or new port to IGMP + 1, leave or age - 1. 15:12 R/W 7 SA_LEARN_STATUS_3 If less than 0x7, dynamic can be fresh to setting h value and age. t 11 R/W 0 SA_LEARN_LIMIT_EN_3 1 = SA learn limit enable. A 10:0 R/W 0 SA_LEARN_CNT_3 The MAC address can be learned and written to the ARL table — only dynamic entry is counted 0: Indicate the MAC limit number is 0 m 1: Indicate the MAC limit number is 1 2: Indicate the MAC limit number is 2 m ... and so on... until: 1024: Indicate the MAC limit is 1024 lco 5.6.30 PORT6_LOOKUP_CTRL aAddress offset: 0x06A8 Qu Table 5-109 summarizes the port 6 lookup control register. 80-Y0619-1 Rev. A 147 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-109 PORT6_LOOKUP_CTRL bit description Bits R/W Initial value Mnemonic Description 31 R/W 30:29 RO 28 R/W 27 R/W 26 R/W 0 0 0 0 0 MULTICAST_ DROP_EN_6 1 = Drop the multicast packet from this port. Do not drop IGMP/MLD join/leave and Special DIP packet. l RESERVED nfidentia UNI_LEAKY_EN_6 Unicast frame leaky VLAN enable. Also use ARL_UNI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_UNI_LEAKY_EN is set to zero, only UNI_ LEAKE_EN control unicast frame leaky VLAN. If ARL_UNI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore UNI_LEAKY_EN. If MAC receive unicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based and 802.1q). o MULTI_LEAKY_ theros C EN_6 Multicast frame leaky VLAN enable. Also use ARL_MULTI_LEAKY_EN and LEAKY_EN bit in ARL table to control unicast leaky VLAN. When ARL_MULTI_LEAKY_EN is set to zero, only MULTI_LEAKY_EN control multicast frame leaky VLAN. If ARL_MULTI_LEAKY_EN is set to 1, only frame with DA in ARL table and LEAKY_EN bit is set to 1 can be forward as leaky VLAN, ignore MULTI_LEAKY_EN. If MAC receive multicast frame from this port which forwards as leaky VLAN, the frame could be switched to destination port defined in ARL table and cross all VLAN (include part-based VLAN and 802.1q). AARP_LEAKY_EN_6 0 = ARP frame can not cross VLAN 1 = If MAC receive ARP frame from this port, it can cross 25 R/W m all VLAN (include part-based VLAN and 802.1q). 0 ING_MIRROR_EN_ Ingress port mirror. If this bit is set to 1, all packets 24 RO 0 m 23 RO 0 o22 RO 0 lc21 R/W 0 Qua 20 R/W 1 6 received from this port is copied to mirror port. RESERVED RESERVED RESERVED PORT_ 0 = Normal forwarding LOOPBACK_EN_6 1 = Loop back. Packet sent in from this port is sent out from the same port. This packet is not sent to other ports. LEARN_EN_6 Enable learn operation 0 = Do not learn new MAC address to ARL table 1 = Enable hardware learn new MAC address into ARL table 19 RO 0 RESERVED 80-Y0619-1 Rev. A 148 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-109 PORT6_LOOKUP_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 18:16 RO 15 RO 14:12 RO 11 R/W 10 R/W 9:8 R/W 3'h4 0 0 0 0 2'0 PORT_STATE_6 Confidential RESERVED RESERVED s RESERVED o FORCE_PORT_ r VLAN_EN_6 Athe VLAN_MODE_6 Port state. These bits are used to manage the port to determine what kind of frames are allowed to enter or leave the port for simple bridge loop detection or 803.1d Spanning Tree. 000 = Disable mode. The port is completely disable, and can not receive or transmit any frames. 001 = Blocking mode. In this state, the port forwards received management frames to the designed port only. Any other frames can not be transmitted or received by the port, and without learning any SA address. 010 = Listening mode. In this state, the port receives and transmits only management frames, but without learning any SA address. Any other frames can not be transmitted or received by the port. 011 = Learning mode. In this state, the port learns all SA, and discards all frames except management frames, and only management frames allowed to be transmitted out. 100 = Forward mode. In this state, the port learns all SA, transmits and receives all frames like normal. 1 = Force to use part-based VLAN enable. If this bit is set to 1, use part-based VLAN & VLAN table result to determine destination port. 802.1q mode for this port. 00 = 802.1q disable. Use part-based VLAN only. 01 = Fallback. Enable 802.1q for all received frames. Do not discard ingress membership violation and use the part-based VLAN if the frame's VID is not contained in m om 7 RO 'h6F Qualc6:0 R/W 0x3f RESERVED PORT_VID_MEM_ 6 VLAN table. 10 = Check. Enable 802.1q for all received frames. Do not discard ingress membership violation but discard frames which VID is not contained in VLAN table. 11 = Secure. Enable 802.1q for all received frames. Discard frames with ingress membership violation or whose VID is not contained in the VLAN table. Port -based VLAN member. Each bit restricts which port can send frames to. To send frames to port0, bit[16] must be set to 1, etc. These bits are set to 1 after reset except the port's bit. This prevents frames going out the port they received in. 5.6.31 PORT6_PRI_CTRL Address offset: 0x06AC 80-Y0619-1 Rev. A 149 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-110 summarizes the port 6 priority control register. Table 5-110 PORT6_PRI_CTRL bit description Bits R/W Initial value Mnemonic l 31:21 RO 0 RESERVED ia 20 R/W 0 EG_MAC_BASE_ VLAN_EN_6 t 19 RO 0 RESERVED n 18 R/W 0 DA_PRI_EN_6 nfide 17 R/W 0 VLAN_PRI_EN_6 16 R/W 0 IP_PRI_EN_6 o 15:8 RO 0 RESERVED C 7:6 R/W 0 DA_PRI_SEL_6 ros 5:4 R/W 1 VLAN_PRI_SEL_6 e 3:2 R/W 2 IP_PRI_SEL_6 Ath 1:0 RO 0 RESERVED Description Enable egress MAC-based VLAN DA priority selected level for QoS. There are five levels of priority for QoS. The highest is priority in packet header. The others are selected by these bits. If these bits are set to zero, DA priority is selected after header. If these bits are set to n, DA priority is selected after the priority set to n-1. VLAN priority selected level for QoS. IP priority selected level for QoS. DA priority selected level for QoS. There are five levels of priority for QoS. The highest is priority in packet header. The others are selected by these bits. If these bits are set to zero, DA priority is selected after header. If these bits are set to n, DA priority is selected after the priority set to n-1. DA priority selected level for QoS. IP priority selected level for QoS. 5.6.32 PORT6_LEARN_LIMIT m Address offset: 0x06B0 Table 5-111 summarizes the port 6 learn limit control register. om Table 5-111 PORT6_LEARN_LIMIT bit description lcBits R/W Initial value Mnemonic Description 31:30 RO 0 RESERVED a 29 R/W 0 IGMP_LEARN_LIMIT_ Drop or redirect the ingress frame to CPU when u DROP_EN_6 new group address coming but learned group address already reach the limitation Q 28 R/W 0 SA_LEARN_LIMIT_DROP_ Drop or redirect the ingress frame to CPU when EN_6 new SA coming but learned SA already reach the limitation 27 R/W 0 IGMP_LEARN_LIMIT_EN_ 1 = IGMP learn limit enable. 6 80-Y0619-1 Rev. A 150 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-111 PORT6_LEARN_LIMIT bit description (cont.) Bits R/W Initial value Mnemonic Description 26:16 R/W 0 IGMP_JOIN_CNT_6 Hardware join IGMP. When join new entry or new port to IGMP + 1, leave or age - 1. 15:12 R/W 7 SA_LEARN_STATUS_6 If less than 0x7, dynamic can be fresh to setting l value and age. ia 11 R/W 0 SA_LEARN_LIMIT_EN_6 1 = SA learn limit enable. fident 10:0 R/W 0 SA_LEARN_CNT_6 The MAC address can be learned and written to the ARL table — only dynamic entry is counted 0: Indicate the MAC limit number is 0 1: Indicate the MAC limit number is 1 2: Indicate the MAC limit number is 2 ... and so on... until: 1024: Indicate the MAC limit is 1024 on 5.6.33 GOL_TRUNK_CTRL0 C Address offset: 0x0700 Table 5-112 summarizes the global trunk control 0 register. os Table 5-112 GOL_TRUNK_CTRL0 bit description r Bits R/W e 31 R/W h 30:24 R/W At 23 R/W Initial value 0 0 0 Mnemonic TRUNK3_EN TRUNK3_MEM TRUNK2_EN Description Trunk 3 enable Trunk 3 member bitmap Trunk 2 enable 22:16 R/W 0 TRUNK2_MEM Trunk 2 member bitmap 15 R/W m 14:8 R/W 7 R/W m 6:0 R/W 0 TRUNK1_EN 0 TRUNK1_MEM 0 TRUNK0_EN 0 TRUNK0_MEM lco 5.6.34 GOL_TRUNK_CTRL1 aAddress offset: 0x0704 Qu Table 5-113 summarizes the global trunk control 1 register. Trunk 1 enable Trunk 1 member bitmap Trunk 0 enable Trunk 0 member bitmap 80-Y0619-1 Rev. A 151 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-113 GOL_TRUNK_CTRL1 bit description Bits R/W Initial value Mnemonic Description 31 R/W l 30:28 R/W ia 27 R/W 26:24 R/W t 23 R/W n 22:20 R/W e 19 R/W id 18:16 R/W f 15 R/W 14:12 R/W n 11 R/W o 10:8 R/W C 7 R/W 6:4 R/W s 3 R/W o 2:0 R/W 0 TRUNK1_MEM3_EN 0 TRUNK1_MEM3_NUM 0 TRUNK1_MEM2_EN 0 TRUNK1_MEM2_NUM 0 TRUNK1_MEM1_EN 0 TRUNK1_MEM1_NUM 0 TRUNK1_MEM0_EN 0 TRUNK1_MEM0_NUM 0 TRUNK0_MEM3_EN 0 TRUNK0_MEM3_NUM 0 TRUNK0_MEM2_EN 0 TRUNK0_MEM2_NUM 0 TRUNK0_MEM1_EN 0 TRUNK0_MEM1_NUM 0 TRUNK0_MEM0_EN 0 TRUNK0_MEM0_NUM Trunk 1 member 3 enable Trunk 1 member 3 port number Trunk 1 member 2 enable Trunk 1 member 2 port number Trunk 1 member 1 enable Trunk 1 member 1 port number Trunk 1 member 0 enable Trunk 1 member 0 port number Trunk 0 member 3 enable Trunk 0 member 3 port number Trunk 0 member 2 enable Trunk 0 member 2 port number Trunk 0 member 1 enable Trunk 0 member 1 port number Trunk 0 member 0 enable Trunk 0 member 0 port number er 5.6.35 GOL_TRUNK_CTRL2 th Address offset: 0x0708 A Table 5-114 summarizes the global trunk control 2 register. Table 5-114 GOL_TRUNK_CTRL2 bit description m Bits R/W Initial value Mnemonic m 31 R/W 0 TRUNK3_MEM3_EN o30:28 R/W 0 TRUNK3_MEM3_NUM lc27 R/W 26:24 R/W a 23 R/W u 22:20 R/W Q 19 R/W 0 TRUNK3_MEM2_EN 0 TRUNK3_MEM2_NUM 0 TRUNK3_MEM1_EN 0 TRUNK3_MEM1_NUM 0 TRUNK3_MEM0_EN Description Trunk 3 member 3 enable Trunk 3 member 3 port number Trunk 3 member 2 enable Trunk 3 member 2 port number Trunk 3 member 1 enable Trunk 3 member 1 port number Trunk 3 member 0 enable 18:16 R/W 0 TRUNK3_MEM0_NUM Trunk 3 member 0 port number 15 R/W 0 TRUNK2_MEM3_EN Trunk 2 member 3 enable 14:12 R/W 0 TRUNK2_MEM3_NUM Trunk 2 member 3 port number 11 R/W 0 TRUNK2_MEM2_EN Trunk 2 member 2 enable 80-Y0619-1 Rev. A 152 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-114 GOL_TRUNK_CTRL2 bit description (cont.) Bits R/W Initial value Mnemonic Description 10:8 R/W 7 R/W l 6:4 R/W ia 3 R/W t 2:0 R/W 0 TRUNK2_MEM2_NUM 0 TRUNK2_MEM1_EN 0 TRUNK2_MEM1_NUM 0 TRUNK2_MEM0_EN 0 TRUNK2_MEM0_NUM Trunk 2 member 2 port number Trunk 2 member 1 enable Trunk 2 member 1 port number Trunk 2 member 0 enable Trunk 2 member 0 port number en 5.6.36 ACL_FWD_SRC_FLTR_CTRL0 id Address offset: 0x0710 f Table 5-115 summarizes the ACL forward source filter 0 register. on Table 5-115 ACL_FWD_SRC_FLTR_CTRL0 bit description Bits R/W Initial value Mnemonic C 31:0 R/W 32'hFFFFFFFF ACL_FWD_SRC_FLTR_ s CTRL0 Description For ACL rule [31:0] source filter control bit 0 = Disable source filter 1 = Enable source filter ero 5.6.37 ACL_FWD_SRC_FLTR_CTRL1 h Address offset: 0x0714 At Table 5-116 summarizes the ACL forward source filter 1 register. Table 5-116 ACL_FWD_SRC_FLTR_CTRL1 bit description m Bits R/W Initial value Mnemonic Description 31:0 R/W 32'hFFFFFFFF ACL_FWD_SRC_FLTR_ For ACL rule [63:32] source filter control bit m CTRL1 0 = Disable source filter 1 = Enable source filter lco 5.6.38 ACL_FWD_SRC_FLTR_CTRL2 aAddress offset: 0x0718 Qu Table 5-116 summarizes the ACL forward source filter 2 register. 80-Y0619-1 Rev. A 153 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-117 ACL_FWD_SRC_FLTR_CTRL2 bit description 5.7 Bits R/W Initial value Mnemonic Description 31:0 R/W 32'hFFFFFFFF ACL_FWD_SRC_FLTR_ For ACL rule [95:64] source filter control bit CTRL2 0 = Disable source filter l 1 = Enable source filter QM control registers entia Table 5-118 summarizes the QM registers. id Table 5-118 QM register summary f Offset range n 0x0800 o 0x0808 C 0x0810 0x0814 s 0x0830 o 0x0838 r 0x083C e 0x0848 h 0x0890–0x08AC t 0x08D0–0x08EC A 0x08F0–0x090C Name Global flow control threshold register QM control register WAN priority to queue mapping register LAN priority to queue mapping register Port0 WRR control register Port2 WRR control register Port3 WRR control register Port6 WRR control register Port0 egress rate limit control register Port2 egress rate limit control register Port3 egress rate limit control register m 0x0950–0x096C 0x0970–0x0974 Port6 egress rate limit control register Port0 HOL control register 0x0980–0x0984 0x0988–0x098C m 0x09A0–0x09A4 o0x09B0 lc 0x09B8 0x09BC a 0x09C8 u 0x09F0 Q 0x09F4 Port2 HOL control register Port3 HOL control register Port6 HOL control register Port0 flow control threshold register Port2 flow control threshold register Port3 flow control threshold register Port6 flow control threshold register ACL policy mode register ACL counter mode register 0x09F8 ACL policy counter reset register 0x0A00–0x0A04 ACL0 rate limit control register 0x0A08–0x0A0C ACL1 rate limit control register 80-Y0619-1 Rev. A 154 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-118 QM register summary (cont.) Offset range Name 0x0A10–0x0A14 0x0A18–0x0A1C 0x0A20–0x0A24 0x0A28–0x0A2C 0x0A30–0x0A34 0x0A38–0x0A3C 0x0A40–0x0A44 0x0A48–0x0A4C 0x0A50–0x0A54 0x0A58–0x0A5C 0x0A60–0x0A64 0x0A68–0x0A6C 0x0A70–0x0A74 0x0A78–0x0A7C 0x0A80–0x0A84 0x0A88–0x0A8C 0x0A90–0x0A94 0x0A98–0x0A9C 0x0AA0–0x0AA4 0x0AA8–0x0AAC 0x0AB0–0x0AB4 0x0AB8–0x0ABC ACL2 rate limit control register ACL3 rate limit control register ACL4 rate limit control register ACL5 rate limit control register ACL6 rate limit control register ACL7 rate limit control register ACL8 rate limit control register ACL9 rate limit control register ACL10 rate limit control register ACL11 rate limit control register ACL12 rate limit control register ACL13 rate limit control register ACL14 rate limit control register ACL15 rate limit control register ACL16 rate limit control register s ACL17 rate limit control register o ACL18 rate limit control register r ACL19 rate limit control register e ACL20 rate limit control register h ACL21 rate limit control register tACL22 rate limit control register AACL23 rate limit control register Confidential m 0x0AC0–0x0AC4 0x0AC8–0x0ACC ACL24 rate limit control register ACL25 rate limit control register 0x0AD0–0x0AD4 m 0x0AD8–0x0ADC 0x0AE0–0x0AE4 o0x0AE8–0x0AEC lc0x0AF0–0x0AF4 a 0x0AF8–0x0AFC 0x0B00–0x0B08 Qu 0x0B20–0x0B28 ACL26 rate limit control register ACL27 Rate limit control register ACL28 rate limit control register ACL29 rate limit control register ACL30 rate limit control register ACL31 rate limit control register Port0 ingress rate limit control register Port2 ingress rate limit control register 0x0B30–0x0B38 Port3 ingress rate limit control register 0x0B60–0x0B68 Port6 ingress rate limit control register 0x0B70 To CPU frame remap priority control register 80-Y0619-1 Rev. A 155 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.1 GLOBAL_FLOW_THD Address offset: 0x0800 Table 5-119 summarizes the global flow control register. l Table 5-119 GLOBAL_FLOW_THD bit description ia Bits R/W Initial value Mnemonic Description t 31:25 RO 0 RESERVED iden 24:16 R/W 'h120 GOL_XON_THRES Global base transmit on threshold. When block memory used by all ports less than this value, MAC sends out pause off frame, and link partner starts transmitting frame out. 15:9 RO 0 RESERVED onf 8:0 R/W 'h188 GOL_XOFF_THRES Global base transmit off threshold. When block memory used by all ports more than this value, MAC sends out pause on frame, and link partner stops transmitting frame out. C 5.7.2 QM_CTRL_REG s Address offset: 0x0808 ro Table 5-120 summarizes the QM control register. he Table 5-120 QM_CTRL_REG bit description t Bits R/W Initial value Mnemonic A 31:30 RO 0 RESERVED Description 29:28 RO 27:26 RO m0 RESERVED 0 RESERVED 25:23 RO m 22:16 R/W 0 7'h7F o 15:11 RO 0 lc10 R/W 0 9 R/W 0 a 8 RO 0 Qu 7 R/W 0 RESERVED GOL_FLOW_EN RESERVED QM_FUNC_TEST MS_FC_EN RESERVED RATE_DROP_EN Global flow control enable when global threshold is reached. E.g. bit[16] for port0; . 1 = Function test, QM drops all packets from port2,3 Multicast server flow control enable Drop packet enable due to rate limit. 0 = Switch uses flow control to the source port due to rate limit; if the port does not stop, switch drops frame from that port. 1 = Switch drops frames due to rate limit. 80-Y0619-1 Rev. A 156 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-120 QM_CTRL_REG bit description (cont.) Bits R/W Initial value Mnemonic Description 6 R/W 0 FLOW_DROP_EN 0 = Switch does not drop packets due to flow control. 1 = Packet could be dropped due to flow control except the highest priority packet. l 5:0 R/W 'hE FLOW_DROP_CNT Maximum free queue could be use after the port has been ia flow control. Then packets is drop except the highest priority. t Default value 'hE is set to normal packets which length is no more than 1518 bytes. For jumbo frame, 'd33 is n commanded. ide 5.7.3 WAN_QUEUE_MAP_REG f Address offset: 0x0810 n Table 5-121 summarizes the WAN port priority to queue mapping register. Co Table 5-121 WAN_QUEUE_MAP_REG bit description Bits R/W Initial value Mnemonic Description s 31 RO 0 RESERVED o 30:28 R/W 5 WAN_PRI_QUEUE_0X7 The destination queue for priority value 0x7 in port 0, r and 6 e 27 RO 0 RESERVED h 26:24 R/W 4 WAN_PRI_QUEUE_0X6 The destination queue for priority value 0x6 in port 0, and 6 At 23 RO 0 RESERVED 22:20 R/W 19 RO m3 WAN_PRI_QUEUE_0X5 The destination queue for priority value 0x5 in port 0, and 6 0 RESERVED 18:16 R/W 3 m 15 RO 0 o 14:12 R/W 2 lc11 RO 0 a10:8 R/W 2 u 7 RO 0 Q 6:4 R/W 0 WAN_PRI_QUEUE_0X4 The destination queue for priority value 0x4 in port 0, and 6 RESERVED WAN_PRI_QUEUE_0X3 The destination queue for priority value 0x3 in port 0, and 6 RESERVED WAN_PRI_QUEUE_0X2 The destination queue for priority value 0x2 in port 0, and 6 RESERVED WAN_PRI_QUEUE_0X1 The destination queue for priority value 0x1 in port 0, and 6 3 RO 0 RESERVED 2:0 R/W 1 WAN_PRI_QUEUE_0X0 The destination queue for priority value 0x0 in port 0, and 6 80-Y0619-1 Rev. A 157 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.4 LAN_QUEUE_MAP_REG Address offset: 0x0814 Table 5-122 summarizes the LAN port priority to queue mapping register. l Table 5-122 LAN_QUEUE_MAP_REG bit description ia Bits R/W Initial value Mnemonic t 31:30 RO 0 RESERVED n 29:28 R/W 3 LAN_PRI_QUEUE_0X7 e 27:26 RO id 25:24 R/W 0 RESERVED 3 LAN_PRI_QUEUE_0X6 nf 23:22 RO 21:20 R/W 0 RESERVED 2 LAN_PRI_QUEUE_0X5 Co 19:18 RO 17:16 R/W 0 RESERVED 2 LAN_PRI_QUEUE_0X4 s 15:14 RO ro 13:12 R/W 0 RESERVED 1 LAN_PRI_QUEUE_0X3 e 11:10 RO h 9:8 R/W 0 RESERVED 1 LAN_PRI_QUEUE_0X2 At 7:6 RO 0 RESERVED Description The destination queue for priority value 0x7 in port 2, 3 The destination queue for priority value 0x6 in port2, 3 The destination queue for priority value 0x5 in port 2, 3 The destination queue for priority value 0x4 in port2, 3 The destination queue for priority value 0x3 in port 2, 3 The destination queue for priority value 0x2 in port 2, 3 5:4 R/W m 3:2 RO 1:0 R/W 0 LAN_PRI_QUEUE_0X1 The destination queue for priority value 0x1 in port 2, 3 0 RESERVED 0 LAN_PRI_QUEUE_0X0 The destination queue for priority value 0x0 in port 2, 3 lcom 5.7.5 PORT0_WRR_CTRL Address offset: 0x0830 QuaTable 5-123 summarizes the port 0 WRR control register. 80-Y0619-1 Rev. A 158 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-123 PORT0_WRR_CTRL bit description Bits R/W Initial value Mnemonic Description 31:30 R/W 00 WEIGHT_PRI_ CTRL_0 ntial 29:25 RO 8 WRR_PRI5_1 e 24:20 RO 8 WRR_PRI4_1 id 19:15 R/W 8 WRR_PRI3_0 f 14:10 R/W 4 WRR_PRI2_0 n 9:5 R/W 2 WRR_PRI1_0 4:0 R/W 1 WRR_PRI0_0 00 = Strict priority 01 = Only highest queue use strict priority; others use weighted fair queuing scheme 10 = The highest two queues use strict priority; other two queues use weighted fair queuing scheme. 11 = All queues use weighted fair queuing scheme which defined in WRR_PRI3/2/1/0. WRR setting for priority 5 WRR setting for priority 4 WRR setting for priority 3 WRR setting for priority 2 WRR setting for priority 1 WRR setting for priority 0 Co 5.7.6 PORT2_WRR_CTRL s Address offset: 0x0838 o Table 5-124 summarizes the port 2 WRR control register. er Table 5-124 PORT2_WRR_CTRL bit description th Bits R/W Initial value Mnemonic 31:30 R/W 00 WEIGHT_PRI_ ACTRL_2 Description 00 = Strict priority 01 = Only highest queue use strict priority; others use m m 29:25 RO 0 o 24:20 RO 0 lc19:15 R/W 8 14:10 R/W 4 a 9:5 R/W 2 Qu 4:0 R/W 1 RESERVED RESERVED WRR_PRI3_2 WRR_PRI2_2 WRR_PRI1_2 WRR_PRI0_2 weighted fair queuing scheme 10 = The highest two queues use strict priority; other two queues use weighted fair queuing scheme. 11 = All Queues use weighted fair queuing scheme which defined in WRR_PRI3/2/1/0. WRR setting for priority 3 WRR setting for priority 2 WRR setting for priority 1 WRR setting for priority 0 5.7.7 PORT3_WRR_CTRL Address offset: 0x083C 80-Y0619-1 Rev. A 159 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-125 summarizes the port 3 WRR control register. Table 5-125 PORT3_WRR_CTR bit description Bits R/W Initial value Mnemonic l 31:30 R/W 00 WEIGHT_PRI_ CTRL_3 entia 29:25 R/W 0 RESERVED id 24:20 R/W 0 RESERVED f 19:15 R/W 8 WRR_PRI3_3 n 14:10 R/W 4 WRR_PRI2_3 o 9:5 R/W 2 WRR_PRI1_3 4:0 R/W 1 WRR_PRI0_3 Description 00 = Strict priority 01 = Only highest queue use strict priority; others use weighted fair queuing scheme 10 = The highest two queues use strict priority, other two queues use weighted fair queuing scheme. 11 = All queues use weighted fair queuing scheme which defined in WRR_PRI3/2/1/0. WRR setting for priority 3 WRR setting for priority 2 WRR setting for priority 1 WRR setting for priority 0 s C 5.7.8 PORT6_WRR_CTRL o Address offset: 0x0848 er Table 5-126 summarizes the port 6 WRR control register. th Table 5-126 PORT6_WRR_CTRL bit description A Bits R/W Initial value Mnemonic Description 31:30 R/W 00 WEIGHT_PRI_CTRL_6 00 = Strict priority 01 = Only highest queue use strict priority; others use m weighted fair queuing scheme 10 = The highest two queues use strict priority, other two queues use weighted fair queuing scheme. m 11 = All Queues use weighted fair queuing scheme which defined in WRR_PRI3/2/1/0. o 29:25 R/W 8 WRR_PRI5_6 WRR setting for priority 5 lc24:20 R/W 8 WRR_PRI4_6 WRR setting for priority 4 a19:15 R/W 8 WRR_PRI3_6 WRR setting for priority 3 14:10 R/W 4 WRR_PRI2_6 WRR setting for priority 2 u 9:5 R/W 2 WRR_PRI1_6 WRR setting for priority 1 Q 4:0 R/W 1 WRR_PRI0_6 WRR setting for priority 0 80-Y0619-1 Rev. A 160 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.9 PORT0_EG_RATE_CTRL0 Address offset: 0x0890 Table 5-127 summarizes the port 0 rate limit control 0 register. l Table 5-127 PORT0_EG_RATE_CTRL0 bit description ia Bits R/W Initial value Mnemonic Description t 31 RO 0 RESERVED iden 30:16 R/W 0x7FFF EG_PRI1_CIR_0 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from port 0. f 15 RO 0 RESERVED Con 14:0 R/W 0x7FFF EG_PRI0_CIR_0 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from port 0. os 5.7.10 PORT0_EG_RATE_CTRL1 r Address offset: 0x0894 he Table 5-128 summarizes the port 0 rate limit control 1 register. At Table 5-128 PORT0_EG_RATE_CTRL1 bit description Bits 31 m R/W Initial value Mnemonic RO 0 RESERVED 30:16 R/W 0x7FFF lcom 15 RO Qua14:0 R/W 0 0x7FFF EG_PRI3_CIR_0 RESERVED EG_PRI2_CIR_0 Description Egress rate limit for priority 3. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from port 0. Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from port 0. 5.7.11 PORT0_EG_RATE_CTRL2 Address offset: 0x0898 80-Y0619-1 Rev. A 161 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-129 summarizes the port 0 rate limit control 2 register. Table 5-129 PORT0_EG_RATE_CTRL2 bit description Bits R/W Initial value Mnemonic l 31 RO 0 RESERVED ia 30:16 R/W 0x7FFF EG_PRI5_CIR_0 ent 15 RO nfid 14:0 R/W 0 0x7FFF RESERVED EG_PRI4_CIR_0 Description Egress rate limit for priority 5. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 5. If these bits are set to 15'h0, no priority 5 frame is send out from port 0. Egress rate limit for priority 4. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 4. If these bits are set to 15'h0, no priority 4 frame is send out from port 0. Co 5.7.12 PORT0_EG_RATE_CTRL3 s Address offset: 0x089C o Table 5-130 summarizes the port 0 rate limit control 3 register. er Table 5-130 PORT0_EG_RATE_CTRL3 bit description h Bits R/W Initial value Mnemonic At 31 RO 0 RESERVED Description 30:16 R/W 0x7FFF EG_PRI1_EIR_0 Egress rate limit for priority 1. mm 15 RO lco14:0 R/W 0 0x7FFF Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. RESERVED EG_PRI0_EIR_0 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. Qua5.7.13 PORT0_EG_RATE_CTRL4 Address offset: 0x08A0 Table 5-131 summarizes the port 0 rate limit control 4 register. 80-Y0619-1 Rev. A 162 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-131 PORT0_EG_RATE_CTRL4 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI3_EIR_0 Egress rate limit for priority 3. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. RESERVED EG_PRI2_EIR_0 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. on 5.7.14 PORT0_EG_RATE_CTRL5 C Address offset: 0x08A4 s Table 5-132 summarizes the port 0 rate limit control 5 register. ro Table 5-132 PORT0_EG_RATE_CTRL5 bit description e Bits R/W Initial value Mnemonic h 31 RO 0 RESERVED At 30:16 R/W 0x7FFF EG_PRI5_EIR_0 Description Egress rate limit for priority 5. Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 5. If these bits are set to 15'h0, no priority 5 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI4_EIR_0 Egress rate limit for priority 4. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 4. If these bits are set to 15'h0, no priority 4 frame is send out from this port. a5.7.15 PORT0_EG_RATE_CTRL6 Qu Address offset: 0x08A8 Table 5-133 summarizes the port 0 rate limit control 6 register. 80-Y0619-1 Rev. A 163 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-133 PORT0_EG_RATE_CTRL6 bit description Bits R/W Initial value Mnemonic Description 31 RO 30:28 R/W 27 RO 26:24 R/W 0 0 0 0 RESERVED l EG_PRI3_CBS_0 ros Confidentia RESERVED Athe EG_PRI3_EBS_0 Committed burst size for priority 3 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 3 Excess burst size: 0: 0k bytes 1: 2k bytes Qualcomm 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 23 RO 0 RESERVED 80-Y0619-1 Rev. A 164 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-133 PORT0_EG_RATE_CTRL6 bit description (cont.) Bits R/W Initial value Mnemonic Description 22:20 R/W 19 RO 18:16 R/W 0 0 0 EG_PRI2_CBS_0 s Confidential RESERVED Athero EG_PRI2_EBS_0 Committed burst size for priority 2 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 2 Excess burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes m Qualcom 15 RO 0 RESERVED 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 80-Y0619-1 Rev. A 165 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-133 PORT0_EG_RATE_CTRL6 bit description (cont.) Bits R/W Initial value Mnemonic Description 14:12 R/W 11 RO 10:8 R/W 0 0 0 EG_PRI1_CBS_0 s Confidential RESERVED Athero EG_PRI1_EBS_0 Committed burst size for priority 1 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 1 Excess burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes m Qual7coRO m0 RESERVED 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 80-Y0619-1 Rev. A 166 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-133 PORT0_EG_RATE_CTRL6 bit description (cont.) Bits R/W Initial value Mnemonic Description 6:4 R/W 3 RO 2:0 R/W 0 0 0 EG_PRI0_CBS_0 s Confidential RESERVED Athero EG_PRI0_EBS_0 Committed burst size for priority 0 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 0 Excess burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes Qualcomm 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 5.7.16 PORT0_EG_RATE_CTRL7 Address offset: 0x08AC 80-Y0619-1 Rev. A 167 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-134 summarizes the port0 rate limit control 7 register. Table 5-134 PORT0_EG_RATE_CTRL7 bit description Bits R/W Initial value Mnemonic l 31 RO 0 RESERVED ia 30:28 R/W 0 EG_PRI5_CBS_0 eros Confident 27 RO 0 RESERVED Ath 26:24 R/W 0 EG_PRI5_EBS_0 Description Committed burst size for priority 5 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 5 Excess burst size: 0: 0k bytes Qualcomm 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 23 RO 0 RESERVED 80-Y0619-1 Rev. A 168 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-134 PORT0_EG_RATE_CTRL7 bit description (cont.) Bits R/W Initial value Mnemonic Description 22:20 R/W 19 RO 18:16 R/W 0 0 0 EG_PRI4_CBS_0 s Confidential RESERVED Athero EG_PRI4_EBS_0 Committed burst size for priority 4 Commit burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets Excess burst size for priority 4 Excess burst size: 0: 0k bytes 1: 2k bytes 2: 4k bytes 3: 8k bytes 4: 16k bytes m Qualcom 15:14 RO 0 RESERVED 5: 32k bytes 6: 128k bytes 7: 512k bytes For packet mode: 0: 0k packets 1: 2k packets 2: 4k packets 3: 16k packets 4: 64k packets 5: 256k packets 6: 512k packets 7: 1024k packets 13 R/W 0 EG_PRI5_RATE_ Rate limit unit for queue 5: UNIT_0 0 = Bytes 1 = Packets 80-Y0619-1 Rev. A 169 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-134 PORT0_EG_RATE_CTRL7 bit description (cont.) Bits R/W Initial value Mnemonic Description 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7:5 RO 4 R/W 3 R/W 2:0 R/W 0 0 0 0 0 0 0 0 3’h2 EG_PRI4_RATE_ UNIT_0 Rate limit unit for queue 4: 0 = Bytes 1 = Packets l EG_PRI3_RATE_ tia UNIT_0 Rate limit unit for queue 3: 0 = Bytes 1 = Packets EG_PRI2_RATE_ en UNIT_0 Rate limit unit for queue 2: 0 = Bytes 1 = Packets id EG_PRI1_RATE_ f UNIT_0 Rate limit unit for queue 1: 0 = Bytes 1 = Packets n EG_PRI0_RATE_ o UNIT_0 Rate limit unit for queue 0: 0 = Bytes 1 = Packets C RESERVED EGRESS_MANAGE_ Enable management frame to be calculate to egress s RATE_EN_0 rate limit. o EGRESS_RATE_EN_0 Enable part-based rate limit. Rate is set at EG_PRIO_ CIR rEnable port-based maximum burst size. Max burst e size is set at EG_PRIO_CBS Ath EG_TIME_SLOT_0 Egress rate limit time slot control register. 3'h0: 1/128 ms 3'h1: 1/64 ms 3'h2: 1/32 ms 3'h3: 1/16 ms 3'h4: 1/4 ms m 3'h5: 1 ms 3'h6: 10 ms m 3'h7: 100 ms lco 5.7.17 PORT2_EG_RATE_CTRL0 Address offset: 0x08D0 QuaTable 5-135 summarizes the port 2 rate limit control 0 register. 80-Y0619-1 Rev. A 170 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-135 PORT2_EG_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI1_CIR_2 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. RESERVED EG_PRI0_CIR_2 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. on 5.7.18 PORT2_EG_RATE_CTRL1 C Address offset: 0x08D4 s Table 5-136 summarizes the port 2 rate limit control 1 register. ro Table 5-136 PORT2_EG_RATE_CTRL1 bit description e Bits R/W Initial value Mnemonic Description h 31 RO 0 RESERVED t 30:16 R/W 0x7FFF EG_PRI3_CIR_2 Egress rate limit for priority 3. A Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI2_CIR_2 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. a5.7.19 PORT2_EG_RATE_CTRL2 Qu Address offset: 0x08DC Table 5-137 summarizes the port 2 rate limit control 2 register. 80-Y0619-1 Rev. A 171 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-137 PORT2_EG_RATE_CTRL2 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI1_EIR_2 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. RESERVED EG_PRI0_EIR_2 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. on 5.7.20 PORT2_EG_RATE_CTRL3 C Address offset: 0x08E0 s Table 5-138 summarizes the port 2 rate limit control 3 register. ro Table 5-138 PORT2_EG_RATE_CTRL3 bit description e Bits R/W Initial value Mnemonic Description h 31 RO 0 RESERVED t 30:16 R/W 0x7FFF EG_PRI3_EIR_2 egress rate limit for priority 3. A Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI2_EIR_2 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. a5.7.21 PORT2_EG_RATE_CTRL4 Qu Address offset: 0x08E8 Table 5-139 summarizes the port 2 rate limit control 4 register. 80-Y0619-1 Rev. A 172 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-139 PORT2_EG_RATE_CTRL4 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:28 R/W ia 27 RO 26:24 R/W t 23 RO n 22:20 R/W e 19 RO id 18:16 R/W f 15 RO 14:12 R/W n 11 RO o 10:8 R/W C 7 RO 6:4 R/W s 3 RO o 2:0 R/W 0 RESERVED 0 EG_PRI3_CBS_2 0 RESERVED 0 EG_PRI3_EBS_2 0 RESERVED 0 EG_PRI2_CBS_2 0 RESERVED 0 EG_PRI2_EBS_2 0 RESERVED 0 EG_PRI1_CBS_2 0 RESERVED 0 EG_PRI1_EBS_2 0 RESERVED 0 EG_PRI0_CBS_2 0 RESERVED 0 EG_PRI0_EBS_2 Committed burst size for priority 3 Excess burst size for priority 3 Committed burst size for priority 2 Excess burst size for priority 2 Committed burst size for priority 1 Excess burst size for priority 1 Committed burst size for priority 0 Excess burst size for priority 0 er 5.7.22 PORT2_EG_RATE_CTRL5 th Address offset: 0x08EC A Table 5-140 summarizes the port 2 rate limit control 5 register. Table 5-140 PORT2_EG_RATE_CTRL5 bit description m Bits R/W Initial value Mnemonic m 31 RO 0 RESERVED o 30:12 RO 0 RESERVED Description lc11 R/W 0 EG_PRI3_RATE_UNIT_2 Rate limit unit for queue 3: 0 = Bytes 1 = Packets a 10 R/W 0 EG_PRI2_RATE_UNIT_2 Rate limit unit for queue 2: u 0 = Bytes Q 1 = Packets 9 R/W 0 EG_PRI1_RATE_UNIT_2 Rate limit unit for queue 1: 0 = Bytes 1 = Packets 80-Y0619-1 Rev. A 173 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-140 PORT2_EG_RATE_CTRL5 bit description (cont.) Bits R/W Initial value Mnemonic Description 8 R/W 0 EG_PRI0_RATE_UNIT_2 Rate limit unit for queue 0: 0 = Bytes 1 = Packets l 7:5 RO 0 RESERVED ia 4 R/W 0 EGRESS_MANAGE_ Enable management frame to be calculate to t RATE_EN_2 egress rate limit. n 3 R/W 0 EGRESS_RATE_EN_2 Enable port-based rate limit. Rate is set at EG_ PRIO_CIR e Maximum burst size is also set at EG_PRIO_CBS Confid 2:0 R/W 3'h2 EG_TIME_SLOT_2 Egress rate limit time slot control register. 3'h0: 1/128 ms 3'h1: 1/64 ms 3'h2: 1/32 ms 3'h3: 1/16 ms 3'h4: 1/4 ms 3'h5: 1 ms 3'h6: 10 ms 3'h7: 100 ms ros 5.7.23 PORT3_EG_RATE_CTRL0 e Address offset: 0x08F0 Ath Table 5-141 summarizes the port 3 rate limit control 0 register. Table 5-141 PORT3_EG_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description m 31 RO 0 RESERVED om 30:16 R/W 0x7FFF EG_PRI1_CIR_3 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. lc15 RO 0 RESERVED Qua14:0 R/W 0x7FFF EG_PRI0_CIR_3 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. 80-Y0619-1 Rev. A 174 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.24 PORT3_EG_RATE_CTRL1 Address offset: 0x08F4 Table 5-142 summarizes the port 3 rate limit control 1 register. l Table 5-142 PORT3_EG_RATE_CTRL1 bit description ia Bits R/W Initial value Mnemonic Description t 31 RO 0 RESERVED iden 30:16 R/W 0x7FFF EG_PRI3_CIR_3 Egress rate limit for priority 3. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. f 15 RO 0 RESERVED Con 14:0 R/W 0x7FFF EG_PRI2_CIR_3 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. os 5.7.25 PORT3_EG_RATE_CTRL2 r Address offset: 0x08FC he Table 5-143 summarizes the port 3 rate limit control 2 register. At Table 5-143 PORT3_EG_RATE_CTRL2 bit description Bits 31 m R/W Initial value Mnemonic RO 0 RESERVED Description 30:16 R/W 0x7FFF lcom 15 RO Qua14:0 R/W 0 0x7FFF EG_PRI1_EIR_3 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. RESERVED EG_PRI0_EIR_3 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. 5.7.26 PORT3_EG_RATE_CTRL3 Address offset: 0x0900 80-Y0619-1 Rev. A 175 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-144 summarizes the port 3 rate limit control 3 register. Table 5-144 PORT3_EG_RATE_CTRL3 bit description Bits R/W Initial value Mnemonic Description l 31 RO 0 RESERVED ntia 30:16 R/W 0x7FFF EG_PRI3_EIR_3 Egress rate limit for priority 3. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. e 15 RO 0 RESERVED nfid 14:0 R/W 0x7FFF EG_PRI2_EIR_3 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. Co 5.7.27 PORT3_EG_RATE_CTRL4 s Address offset: 0x0908 o Table 5-145 summarizes the port 3 rate limit control 4 register. er Table 5-145 PORT3_EG_RATE_CTRL4 bit description h Bits R/W Initial value Mnemonic At 31 RO 0 RESERVED Description 30:28 R/W 0 EG_PRI3_CBS_3 Committed burst size for priority 3 27 RO 0 m 26:24 R/W 0 23 RO 0 m 22:20 R/W 0 o19 RO 0 18:16 R/W 0 lc15 RO 0 a 14:12 R/W 0 u 11 RO 0 Q 10:8 R/W 0 RESERVED EG_PRI3_EBS_3 RESERVED EG_PRI2_CBS_3 RESERVED EG_PRI2_EBS_3 RESERVED EG_PRI1_CBS_3 RESERVED EG_PRI1_EBS_3 Excess burst size for priority 3 Committed burst size for priority 2 Excess burst size for priority 2 Committed burst size for priority 1 Excess burst size for priority 1 7 RO 0 RESERVED 6:4 R/W 0 EG_PRI0_CBS_3 Committed burst size for priority 0 3 RO 0 RESERVED 2:0 R/W 0 EG_PRI0_EBS_3 Excess burst size for priority 0 80-Y0619-1 Rev. A 176 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.28 PORT3_EG_RATE_CTRL5 Address offset: 0x090C Table 5-146 summarizes the port 3 rate limit control 5 register. l Table 5-146 PORT3_EG_RATE_CTRL5 bit description ia Bits R/W Initial value Mnemonic t 31 RO 0 RESERVED n 30:12 RO 0 RESERVED e 11 R/W 0 EG_PRI3_RATE_ UNIT_3 fid 10 R/W 0 EG_PRI2_RATE_ n UNIT_3 o 9 R/W 0 EG_PRI1_RATE_ C UNIT_3 s 8 R/W 0 EG_PRI0_RATE_ UNIT_3 ro 7:5 RO 0 RESERVED e 4 R/W 0 EGRESS_ h MANAGE_RATE_ t EN_3 3 R/W 0 EGRESS_RATE_ AEN_3 Description Rate limit unit for queue 3: 0 = Bytes 1 = Packets Rate limit unit for queue 2: 0 = Bytes 1 = Packets Rate limit unit for queue 1: 0 = Bytes 1 = Packets Rate limit unit for queue 0: 0 = Bytes 1 = Packets Enable management frame to be calculate to egress rate limit. Enable port-based rate limit. Rate is set at EG_PRIO_ CIR m Qualcom 2:0 R/W 3'h2 EG_TIME_SLOT_3 Enable Max burst size also. Max burst size is set at EG_ PRIO_CBS Egress rate limit time slot control register. 3'h0: 1/128 ms 3'h1: 1/64 ms 3'h2: 1/32 ms 3'h3: 1/16 ms 3'h4: 1/4 ms 3'h5: 1 ms 3'h6: 10 ms 3'h7: 100 ms 5.7.29 PORT6_EG_RATE_CTRL0 Address offset: 0x0950 Table 5-147 summarizes the port 6 rate limit control 0 register. 80-Y0619-1 Rev. A 177 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-147 PORT6_EG_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI1_CIR_6 Egress rate limit for priority 1. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. RESERVED EG_PRI0_CIR_6 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. on 5.7.30 PORT6_EG_RATE_CTRL1 C Address offset: 0x0954 s Table 5-148 summarizes the port 6 rate limit control 1 register. ro Table 5-148 PORT6_EG_RATE_CTRL1 bit description e Bits R/W Initial value Mnemonic Description h 31 RO 0 RESERV6ED t 30:16 R/W 0x7FFF EG_PRI3_CIR_6 Egress rate limit for priority 3. A Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI2_CIR_6 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. a5.7.31 PORT6_EG_RATE_CTRL2 Qu Address offset: 0x0958 Table 5-149 summarizes the port 6 rate limit control 2 register. 80-Y0619-1 Rev. A 178 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-149 PORT6_EG_RATE_CTRL2 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI5_CIR_6 Egress rate limit for priority 5. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 5. If these bits are set to 15'h0, no priority 5 frame is send out from this port. RESERVED EG_PRI4_CIR_6 Egress rate limit for priority 4. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 4. If these bits are set to 15'h0, no priority 4 frame is send out from this port. on 5.7.32 PORT6_EG_RATE_CTRL3 C Address offset: 0x095C s Table 5-150 summarizes the port 6 rate limit control 3 register. ro Table 5-150 PORT6_EG_RATE_CTRL3 bit description e Bits R/W Initial value Mnemonic Description h 31 RO 0 RESERVED t 30:16 R/W 0x7FFF EG_PRI1_EIR_6 Egress rate limit for priority 1. A Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 1. If these bits are set to 15'h0, no priority 1 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI0_EIR_6 Egress rate limit for priority 0. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 0. If these bits are set to 15'h0, no priority 0 frame is send out from this port. a5.7.33 PORT6_EG_RATE_CTRL4 Qu Address offset: 0x0960 Table 5-151 summarizes the port 6 rate limit control 4 register. 80-Y0619-1 Rev. A 179 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-151 PORT6_EG_RATE_CTRL4 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:16 R/W ntia 15 RO fide 14:0 R/W 0 0x7FFF 0 0x7FFF RESERVED EG_PRI3_EIR_6 Egress rate limit for priority 3. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 3. If these bits are set to 15'h0, no priority 3 frame is send out from this port. RESERVED EG_PRI2_EIR_6 Egress rate limit for priority 2. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no priority 2 frame is send out from this port. on 5.7.34 PORT6_EG_RATE_CTRL5 C Address offset: 0x0964 s Table 5-152 summarizes the port 6 rate limit control 5 register. ro Table 5-152 PORT6_EG_RATE_CTRL5 bit description e Bits R/W Initial value Mnemonic Description h 31 RO 0 RESERVED t 30:16 R/W 0x7FFF EG_PRI5_EIR_6 Egress rate limit for priority 5. A Rate is limited to times of 32 kbps. m Default 15'h7FFF is for disable rate limit for egress priority 5. If these bits are set to 15'h0, no priority 5 frame is send out from this port. 15 RO lcom 14:0 R/W 0 0x7FFF RESERVED EG_PRI4_EIR_6 Egress rate limit for priority 4. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 4. If these bits are set to 15'h0, no priority 4 frame is send out from this port. a5.7.35 PORT6_EG_RATE_CTRL6 Qu Address offset: 0x0968 Table 5-153 summarizes the port 6 rate limit control 6 register. 80-Y0619-1 Rev. A 180 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-153 PORT6_EG_RATE_CTRL6 bit description Bits R/W Initial value Mnemonic Description 31 RO l 30:28 R/W ia 27 RO 26:24 R/W t 23 RO n 22:20 R/W e 19 RO id 18:16 R/W f 15 RO 14:12 R/W n 11 RO o 10:8 R/W C 7 RO 6:4 R/W s 3 RO o 2:0 R/W 0 RESERVED 0 EG_PRI3_CBS_6 0 RESERVED 0 EG_PRI3_EBS_6 0 RESERVED 0 EG_PRI2_CBS_6 0 RESERVED 0 EG_PRI2_EBS_6 0 RESERVED 0 EG_PRI1_CBS_6 0 RESERVED 0 EG_PRI1_EBS_6 0 RESERVED 0 EG_PRI0_CBS_6 0 RESERVED 0 EG_PRI0_EBS_6 Committed burst size for priority 3 Excess burst size for priority 3 Committed burst size for priority 2 Excess burst size for priority 2 Committed burst size for priority 1 Excess burst size for priority 1 Committed burst size for priority 0 Excess burst size for priority 0 er 5.7.36 PORT6_EG_RATE_CTRL7 th Address offset: 0x096C A Table 5-154 summarizes the port 6 rate limit control 7 register. Table 5-154 PORT6_EG_RATE_CTRL7 bit description m Bits R/W Initial value Mnemonic m 31 RO 0 RESERVED o 30:28 R/W 0 EG_PRI5_CBS_6 Description Committed burst size for priority 5 lc27 RO 0 RESERVED 26:24 R/W 0 EG_PRI5_EBS_6 a 23 RO 0 RESERVED u 22:20 R/W 0 EG_PRI4_CBS_6 Q 19 RO 0 RESERVED Excess burst size for priority 5 Committed burst size for priority 4 18:16 R/W 0 EG_PRI4_EBS_6 Excess burst size for priority 4 15:14 RO 0 RESERVED 80-Y0619-1 Rev. A 181 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-154 PORT6_EG_RATE_CTRL7 bit description (cont.) Bits R/W Initial value Mnemonic Description 13 R/W 12 R/W 11 RO 10 R/W 9 R/W 8 R/W 7:5 RO 4 R/W 3 RO 0 0 0 0 0 0 0 0 0 EG_PRI5_RATE_UNIT_6 Rate limit unit for queue 5: 0 = Bytes 1 = Packets tial EG_PRI4_RATE_UNIT_6 Rate limit unit for queue 4: 0 = Bytes 1 = Packets en EG_PRI3_RATE_UNIT_6 Rate limit unit for queue 3: 0 = Bytes 1 = Packets fid EG_PRI2_RATE_UNIT_6 Rate limit unit for queue 2: 0 = Bytes 1 = Packets on EG_PRI1_RATE_UNIT_6 Rate limit unit for queue 1: 0 = Bytes 1 = Packets s C EG_PRI0_RATE_UNIT_6 Rate limit unit for queue 0: 0 = Bytes 1 = Packets o RESERVED r EGRESS_MANAGE_RATE_EN_6 Enable management frame to be calculate to egress rate limit. Athe EGRESS_RATE_EN_6 Enable Port-based rate limit. Rate is set at EG_PRIO_CIR Enable Port-based Max burst size also. Max burst size is set at EG_PRIO_CBS 2:0 R/W 3’h2 EG_TIME_SLOT_6 Egress rate limit time slot control register. m 3'h0: 1/128 ms 3'h1: 1/64 ms ualcom 5.7.37 PORT0_HOL_CTRL0 Q Address offset: 0x0970 3'h2: 1/32 ms 3'h3: 1/16 ms 3'h4:1/4 ms 3'h5: 1 ms 3'h6: 10 ms 3'h7: 100 ms Table 5-155 summarizes the port 0 HOL control 0 register. 80-Y0619-1 Rev. A 182 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-155 PORT0_HOL_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31:30 RO l 29:24 R/W entia 23:20 R/W id 19:16 R/W f 15:12 R/W n 11:8 R/W o 7:4 R/W ros C 3:0 R/W 0 0x28 0 0 0 0 0 0 RESERVED EG_PORT_QUEUE_NUM_0 Most buffer can be used for this port. Buffer number is times of 8. 6'h0: 0 6'h1: No more than 8 6'h2: No more than 16 …… 6'h3F: No more than 504 EG_PRI5_QUEUE_NUM_0 See bits[3:0]. This is for priority queue 5. EG_PRI4_QUEUE_NUM_0 See bits[3:0]. This is for priority queue 4. EG_PRI3_QUEUE_NUM_0 See bits[3:0]. This is for priority queue 3. EG_PRI2_QUEUE_NUM_0 See bits[3:0]. This is for priority queue 2. EG_PRI1_QUEUE_NUM_0 See bits[3:0]. This is for priority queue 1. EG_PRI0_QUEUE_NUM_0 Most buffer can be used for priority 0 queue. Buffer number is times of 8. 4'h0: 0 4'h1: No more than 8 4'h2: No more than 16 …… 4'hF: No more than 240 the 5.7.38 PORT0_HOL_CTRL1 A Address offset: 0x0974 m Table 5-156 summarizes the port 0 HOL control 1 register. Table 5-156 PORT0_HOL_CTRL1 bit description m Bits R/W Initial value Mnemonic Description o 31:17 RO 0 RESERVED lc16 R/W 0 EG_MIRROR_EN_0 Egress port mirror. If this bit is set to 1, all packets send out through this port is copied to mirror port. a15:9 RO 0 RESERVED 8 R/W 1 PORT_RED_EN_0 WRED enable u 7 R/W 0x1 EG_PORT_QUEUE_ 1 = Enable use PORT_QUEUE_NUM to control queue Q CTRL_EN_0 depth in this port. 6 R/W 0x1 EG_PRI_QUEUE_ 1 = Enable use PRI*_QUEUE_NUM to control queue CTRL_EN_0 depth in this port. 80-Y0619-1 Rev. A 183 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-156 PORT0_HOL_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 5:4 RO 0 RESERVED 3:0 R/W 0x0 ING_BUF_NUM_0 Buffer number is times of 8. l 4'h0: 0 4'h1: No more than 8 ia 4'h2: No more than 16 t …… 4'hF: No more than 240 en 5.7.39 PORT2_HOL_CTRL0 fid Address offset: 0x0980 n Table 5-157 summarizes the port 2 HOL control 0 register. o Table 5-157 PORT2_HOL_CTRL0 bit description C Bits R/W Initial value Mnemonic Description s 31:30 RO 0 RESERVED thero 29:24 R/W 0x28 EG_PORT_QUEUE_NUM_2 Most buffer can be used for this port. Buffer number is times of 8. 6'h0: 0 6'h1: No more than 8 6'h2: No more than 16 …… 6'h3F: No more than 504 A 23:20 R/W 0 RESERVED 19:16 R/W 15:12 R/W m0 RESERVED 0 EG_PRI3_QUEUE_NUM_2 11:8 R/W 0 m 7:4 R/W 0 Qualco3:0 R/W 0 EG_PRI2_QUEUE_NUM_2 EG_PRI1_QUEUE_NUM_2 EG_PRI0_QUEUE_NUM_2 See bits[3:0]. This is for priority queue 3. See bits[3:0]. This is for priority queue 2. See bits[3:0]. This is for priority queue 1. Most buffer can be used for priority 0 queue. Buffer number is times of 8. 4'h0: 0 4'h1: No more than 8 4'h2: No more than 16 …… 4'hF: No more than 240 5.7.40 PORT2_HOL_CTRL1 Address offset: 0x0984 80-Y0619-1 Rev. A 184 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-158 summarizes the port 2 HOL control 1 register. Table 5-158 PORT2_HOL_CTRL1 bit description Bits R/W Initial value Mnemonic Description l 31:17 RO 0 RESERVED ia 16 R/W 0 EG_MIRROR_EN_2 Egress port mirror. If this bit is set to 1, all packets send out through this port are copied to mirror port. t 15:9 RO 0 RESERVED n 8 R/W 1 PORT_RED_EN_1 WRED enable e 7 R/W 0x1 EG_PORT_QUEUE_ 1 = Enable use PORT_QUEUE_NUM to control queue CTRL_EN_2 depth in this port. id 6 R/W 0x1 EG_PRI_QUEUE_ 1 = Enable use PRI*_QUEUE_NUM to control queue f CTRL_EN_2 depth in this port. n 5:4 RO 0 RESERVED 3:0 R/W 0x2 ING_BUF_NUM_2 Buffer number is times of 8. o 4'h0: 0 4'h1: No more than 8 C 4'h2: No more than 16 …… s 4'hF: No more than 240 ero 5.7.41 PORT3_HOL_CTRL0 h Address offset: 0x0988 At Table 5-159 summarizes the port 3 HOL control 0 register. Table 5-159 PORT3_HOL_CTRL0 bit description m Bits R/W Initial value Mnemonic 31:30 RO 0 RESERVED m 29:24 R/W 0x28 EG_PORT_QUEUE_NUM_3 ualco 23:20 R/W 0 RESERVED Q 19:16 R/W 0 RESERVED Description Most buffer can be used for this port. Buffer number is times of 8. 6'h0: 0 6'h1: No more than 8 6'h2: No more than 16 …… 6'h1F: No more than 504 15:12 R/W 0 EG_PRI3_QUEUE_NUM_3 See bits[3:0]. This is for priority queue 3. 11:8 R/W 0 EG_PRI2_QUEUE_NUM_3 See bits[3:0]. This is for priority queue 2. 80-Y0619-1 Rev. A 185 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-159 PORT3_HOL_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 7:4 R/W 0 EG_PRI1_QUEUE_NUM_3 See bits[3:0]. This is for priority queue 1. 3:0 R/W 0 EG_PRI0_QUEUE_NUM_3 Most buffer can be used for priority 0 queue. Buffer number is times of 8. l 4'h0: 0 ia 4'h1: No more than 8 t 4'h2: No more than 16 …… n 4'hF: No more than 240 ide 5.7.42 PORT3_HOL_CTRL1 f Address offset: 0x098c n Table 5-160 summarizes the port 3 HOL control 1 register. Co Table 5-160 PORT3_HOL_CTRL1 bit description Bits R/W Initial value Mnemonic Description s 31:17 RO 0 RESERVED o 16 R/W 0 EG_MIRROR_EN_3 Egress port mirror. If this bit is set to 1, all packets send rout through this port are copied to mirror port. e 15:9 RO 0 RESERVED 8 R/W 1 PORT_RED_EN_1 WRED enable th 7 R/W 0x1 EG_PORT_QUEUE_ 1 = Enable use PORT_QUEUE_NUM to control queue ACTRL_EN_3 depth in this port. 6 R/W 0x1 EG_PRI_QUEUE_ 1 = Enable use PRI*_QUEUE_NUM to control queue 5:4 RO mCTRL_EN_3 0 RESERVED depth in this port. 3:0 R/W 0x2 ING_BUF_NUM_3 ualcom 5.7.43 PORT6_HOL_CTRL0 Q Address offset: 0x09A0 Buffer number is times of 8. 4'h0: 0 4'h1: No more than 8 4'h2: No more than 16 …… 4'hF: No more than 240 Table 5-161 summarizes the port 6 HOL control 0 register. 80-Y0619-1 Rev. A 186 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-161 PORT6_HOL_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31:30 RO l 29:24 R/W entia 23:20 R/W id 19:16 R/W f 15:12 R/W n 11:8 R/W o 7:4 R/W ros C 3:0 R/W 0 0x28 0 0 0 0 0 0 RESERVED EG_PORT_QUEUE_NUM_ 6 Most buffer can be used for this port. Buffer number is times of 8. 6'h0: 0 6'h1: No more than 8 6'h2: No more than 16 …… 6'h3F: No more than 504 EG_PRI5_QUEUE_NUM_6 See bits[3:0]. This is for priority queue 5. EG_PRI4_QUEUE_NUM_6 See bits[3:0]. This is for priority queue 4. EG_PRI3_QUEUE_NUM_6 See bits[3:0]. This is for priority queue 3. EG_PRI2_QUEUE_NUM_6 See bits[3:0]. This is for priority queue 2. EG_PRI1_QUEUE_NUM_6 See bits[3:0]. This is for priority queue 1. EG_PRI0_QUEUE_NUM_6 Most buffer can be used for priority 0 queue. Buffer number is times of 8. 4'h0: 0 4'h1: No more than 8 4'h2: No more than 16 …… 4'hF: No more than 240 the 5.7.44 PORT6_HOL_CTRL1 A Address offset: 0x09A4 m Table 5-162 summarizes the port 6 HOL control 1 register. Table 5-162 PORT6_HOL_CTRL1 bit description m Bits R/W Initial value Mnemonic o 31:17 RO 0 RESERVED lc16 R/W 0 EG_MIRROR_EN_6 a15:9 RO 0 RESERVED 8 R/W 1 PORT_RED_EN_1 u 7 R/W 0x1 EG_PORT_QUEUE_ Q CTRL_EN_6 Description Egress port mirror. If this bit is set to 1, all packets send out through this port are copied to mirror port. WRED enable 1 = Enable use PORT_QUEUE_NUM to control queue depth in this port. 6 R/W 0x1 EG_PRI_QUEUE_ 1 = Enable use PRI*_QUEUE_NUM to control queue CTRL_EN_6 depth in this port. 80-Y0619-1 Rev. A 187 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-162 PORT6_HOL_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 5:4 RO 0 RESERVED 3:0 R/W 0x0 ING_BUF_NUM_6 Buffer number is times of 8. l 4'h0: 0 4'h1: No more than 8 ia 4'h2: No more than 16 t …… 4'hF: No more than 240 en 5.7.45 PORT0_FLOW_THD fid Address offset: 0x09B0 n Table 5-163 summarizes the port 0 flow control threshold control register. o Table 5-163 PORT0_FLOW_THD bit description C Bits R/W Initial value Mnemonic Description s 31:24 RO 0 RESERVED 23:16 R/W 'h3A PORT_XON_THRES_0 Port-based transmit on threshold. When block omemory used by one port is less than this value, r MAC sends out pause off frame, and link partner starts transmitting frame out. e 15:8 RO 0 RESERVED h 7:0 R/W 'h4A PORT_XOFF_THRES_0 Port-based transmit off threshold. When block t memory used by one port is more than this value, MAC sends out pause on frame, and link partner A stops transmitting frame out. m 5.7.46 PORT2_FLOW_THD m Address offset: 0x09B8 o Table 5-164 summarizes the port 2 flow control threshold register. lcTable 5-164 PORT2_FLOW_THD bit description a Bits R/W Initial value Mnemonic u 31:24 RO 0 RESERVED Q 23:16 R/W 'h3A PORT_XON_THRES_2 Description Port-based transmit on threshold. When block memory used by one port is less than this value, MAC sends out pause off frame, and link partner starts transmitting frame out. 80-Y0619-1 Rev. A 188 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-164 PORT2_FLOW_THD bit description (cont.) Bits R/W Initial value Mnemonic Description 15:8 RO 0 RESERVED 7:0 R/W 'h4B PORT_XOFF_THRES_2 Port-based transmit off threshold. When block memory used by one port is more than this value, l MAC sends out pause on frame, and link partner ia stops transmitting frame out. nt 5.7.47 PORT3_FLOW_THD e Address offset: 0x09BC id Table 5-165 summarizes the port 3 flow control threshold control register. nf Table 5-165 PORT3_FLOW_THD bit description o Bits R/W Initial value Mnemonic Description 31:24 RO 0 RESERVED C 23:16 R/W 'h3A PORT_XON_THRES_3 Port-based transmit on threshold. When block memory used by one port is less than this value, sMAC sends out pause off frame, and link partner starts transmitting frame out. o 15:8 RO 0 RESERVED r 7:0 R/W 'h4A PORT_XOFF_THRES_3 Port-based transmit off threshold. When block e memory used by one port is more than this value, MAC sends out pause on frame, and link partner Ath stops transmitting frame out. m 5.7.48 PORT6_FLOW_THD Address offset: 0x09C8 Table 5-166 summarizes the port 6 flow control threshold control register. om Table 5-166 PORT6_FLOW_THD bit description lcBits R/W Initial value Mnemonic 31:24 RO 0 RESERVED Qua23:16 R/W 'h3A PORT_XON_THRES_6 Description Port-based transmit on threshold. When block memory used by one port is less than this value, MAC sends out pause off frame, and link partner starts transmitting frame out. 15:8 RO 0 RESERVED 7:0 R/W 'h4A PORT_XOFF_THRES_6 Port-based transmit off threshold. When block memory used by one port is more than this value, MAC sends out pause on frame, and link partner stops transmitting frame out. 80-Y0619-1 Rev. A 189 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.49 ACL_POLICY_MODE Address offset: 0x09F0 Table 5-167 summarizes the ACL policy register. Table 5-167 ACL_POLICY_MODE bit description Bits R/W Initial value Mnemonic 31 R/W 0 ACL_SEL_31 30 R/W 0 ACL_SEL_30 29 R/W 0 ACL_SEL_29 28 R/W 0 ACL_SEL_28 27 R/W 0 ACL_SEL_27 26 R/W 0 ACL_SEL_26 25 R/W 0 ACL_SEL_25 24 R/W 0 ACL_SEL_24 23 R/W 22 R/W 21 R/W 20 R/W 19 R/W 18 R/W 17 R/W 16 R/W 15 R/W 0 ACL_SEL_23 0 ACL_SEL_22 s 0 ACL_SEL_21 o 0 ACL_SEL_20 r 0 ACL_SEL_19 e 0 ACL_SEL_18 h 0 ACL_SEL_17 t0 ACL_SEL_16 A0 ACL_SEL_15 14 13 m R/W 0 R/W 0 12 R/W m 11 R/W 10 R/W o9 R/W lc8 R/W a7 R/W 6 R/W u5 R/W Q4 R/W 0 0 0 0 0 0 0 0 0 ACL_SEL_14 ACL_SEL_13 ACL_SEL_12 ACL_SEL_11 ACL_SEL_10 ACL_SEL_9 ACL_SEL_8 ACL_SEL_7 ACL_SEL_6 ACL_SEL_5 ACL_SEL_4 tial See bit[0] n See bit[0] e See bit[0] id See bit[0] f See bit[0] See bit[0] n See bit[0] oSee bit[0] CSee bit[0] Description See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] 3 R/W 0 ACL_SEL_3 See bit[0] 2 R/W 0 ACL_SEL_2 See bit[0] 80-Y0619-1 Rev. A 190 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-167 ACL_POLICY_MODE bit description (cont.) Bits R/W Initial value Mnemonic Description 1 R/W l 0 R/W 0 ACL_SEL_1 0 ACL_SEL_0 See bit[0] 0 = ACL rate limit 1 = ACL counter tia 5.7.50 ACL_COUNTER_MODE n Address offset: 0x09F4 e Table 5-168 summarizes the ACL counter mode register. fid Table 5-168 ACL_COUNTER_MODE bit description n Bits R/W Initial value Mnemonic 31 R/W 0 ACL_CNT_MODE_31 o 30 R/W 0 ACL_CNT_MODE_30 C 29 R/W 0 ACL_CNT_MODE_29 28 R/W 0 ACL_CNT_MODE_28 s 27 R/W 0 ACL_CNT_MODE_27 o 26 R/W 0 ACL_CNT_MODE_26 r 25 R/W 0 ACL_CNT_MODE_25 e 24 R/W 0 ACL_CNT_MODE_24 h 23 R/W 0 ACL_CNT_MODE_23 At 22 R/W 0 ACL_CNT_MODE_22 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] Description 21 R/W 0 ACL_CNT_MODE_21 See bit[0] 20 R/W 0 m 19 R/W 0 18 R/W 0 m 17 R/W 0 o16 R/W 0 15 R/W 0 lc14 R/W 0 a 13 R/W 0 u 12 R/W 0 Q 11 R/W 0 ACL_CNT_MODE_20 ACL_CNT_MODE_19 ACL_CNT_MODE_18 ACL_CNT_MODE_17 ACL_CNT_MODE_16 ACL_CNT_MODE_15 ACL_CNT_MODE_14 ACL_CNT_MODE_13 ACL_CNT_MODE_12 ACL_CNT_MODE_11 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] 10 R/W 0 ACL_CNT_MODE_10 See bit[0] 9 R/W 0 ACL_CNT_MODE_9 See bit[0] 8 R/W 0 ACL_CNT_MODE_8 See bit[0] 7 R/W 0 ACL_CNT_MODE_7 See bit[0] 80-Y0619-1 Rev. A 191 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-168 ACL_COUNTER_MODE bit description (cont.) Bits R/W Initial value Mnemonic Description 6 R/W 5 R/W l 4 R/W ia 3 R/W t 2 R/W 1 R/W en 0 R/W 0 ACL_CNT_MODE_6 0 ACL_CNT_MODE_5 0 ACL_CNT_MODE_4 0 ACL_CNT_MODE_3 0 ACL_CNT_MODE_2 0 ACL_CNT_MODE_1 0 ACL_CNT_MODE_0 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] 0 = Frame counter 1 = Byte counter fid 5.7.51 ACL_CNT_RESET n Address offset: 0x09F8 o Table 5-169 summarizes the ACL counter reset register. C Table 5-169 ACL_CNT_RESET bit description s Bits R/W Initial value Mnemonic o 31 R/W 0 ACL_CNT_RST_31 r 30 R/W 0 ACL_CNT_RST_30 e 29 R/W 0 ACL_CNT_RST_29 h 28 R/W 0 ACL_CNT_RST_28 At 27 R/W 0 ACL_CNT_RST_27 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] Description 26 R/W 0 ACL_CNT_RST_26 See bit[0] 25 R/W 0 m 24 R/W 0 23 R/W 0 m 22 R/W 0 o21 R/W 0 20 R/W 0 lc19 R/W 0 a 18 R/W 0 u 17 R/W 0 Q 16 R/W 0 ACL_CNT_RST_25 ACL_CNT_RST_24 ACL_CNT_RST_23 ACL_CNT_RST_22 ACL_CNT_RST_21 ACL_CNT_RST_20 ACL_CNT_RST_19 ACL_CNT_RST_18 ACL_CNT_RST_17 ACL_CNT_RST_16 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] 15 R/W 0 ACL_CNT_RST_15 See bit[0] 14 R/W 0 ACL_CNT_RST_14 See bit[0] 13 R/W 0 ACL_CNT_RST_13 See bit[0] 12 R/W 0 ACL_CNT_RST_12 See bit[0] 80-Y0619-1 Rev. A 192 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-169 ACL_CNT_RESET bit description (cont.) Bits R/W Initial value Mnemonic Description 11 R/W 10 R/W l 9 R/W ia 8 R/W t 7 R/W 6 R/W n 5 R/W e 4 R/W id 3 R/W f 2 R/W n 1 R/W 0 R/W 0 ACL_CNT_RST_11 0 ACL_CNT_RST_10 0 ACL_CNT_RST_9 0 ACL_CNT_RST_8 0 ACL_CNT_RST_7 0 ACL_CNT_RST_6 0 ACL_CNT_RST_5 0 ACL_CNT_RST_4 0 ACL_CNT_RST_3 0 ACL_CNT_RST_2 0 ACL_CNT_RST_1 0 ACL_CNT_RST_0 See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] See bit[0] 1 = Clear counter Co 5.7.52 ACL_RATE_CTRL0_0 s Address offset: 0x0A00 o Table 5-170 summarizes the ACL 0 rate control 0 register. er Table 5-170 ACL_RATE_CTRL0_0 bit description th Bits R/W Initial value Mnemonic A 31:18 RO 0 RESERVED Description 17:15 R/W m 14:0 R/W 0 0x7FFF ACL_CBS_0 Committed burst size for ingress rate limit ACL_CIR_0 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. om 5.7.53 ACL_RATE_CTRL1_0 lcAddress offset: 0x0A04 aTable 5-171 summarizes the ACL0 rate control 1 register. Qu Table 5-171 ACL_RATE_CTRL1_0 bit description Bits R/W Initial value Mnemonic 31:24 RO 0 RESERVED 23 R/W 0 ACL_BORROW_EN_0 Description Borrow enable 80-Y0619-1 Rev. A 193 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-171 ACL_RATE_CTRL1_0 bit description (cont.) Bits R/W Initial value Mnemonic Description 22 R/W l 21 R/W ia 20 R/W 19:18 R/W fident 17:15 R/W Con 14:0 R/W 0 0 0 01 0 0x7FFF ACL_RATE_UNIT_0 0 = Bytes 1 = Packets ACL_CF_0 Coupling flag for ingress rate limit ACL_CM_0 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_0 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. ACL_EBS_0 Excess burst size for ingress rate limit ACL_EIR_0 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. os 5.7.54 ACL_RATE_CTRL0_1 r Address offset: 0x0A08 e Table 5-172 summarizes the ACL 1 rate control 0 register. Ath Table 5-172 ACL_RATE_CTRL0_1 bit description m Bits R/W Initial value Mnemonic 31:18 RO 0 RESERVED Description 17:15 R/W om 14:0 R/W 0 0x7FFF ACL_CBS_1 Committed burst size for ingress rate limit ACL_CIR_1 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. alc 5.7.55 ACL_RATE_CTRL1_1 u Address offset: 0x0A0C Q Table 5-173 summarizes the ACL 1 rate control 1 register. 80-Y0619-1 Rev. A 194 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-173 ACL_RATE_CTRL1_1 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_1 Borrow enable ACL_RATE_UNIT_1 0 = Bytes 1 = Packets ACL_CF_1 Coupling flag for ingress rate limit ACL_CM_1 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_1 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_1 Excess burst size for ingress rate limit ACL_EIR_1 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.56 ACL_RATE_CTRL0_2 th Address offset: 0x0A10 A Table 5-174 summarizes the ACL 2 rate control 0 register. m Table 5-174 ACL_RATE_CTRL0_2 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_2 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_2 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.57 ACL_RATE_CTRL1_2 Address offset: 0x0A14 Table 5-175 summarizes the ACL 2 rate control 1 register. 80-Y0619-1 Rev. A 195 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-175 ACL_RATE_CTRL1_2 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_2 Borrow enable ACL_RATE_UNIT_2 0 = Bytes 1 = Packets ACL_CF_2 Coupling flag for ingress rate limit ACL_CM_2 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_2 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_2 Excess burst size for ingress rate limit ACL_EIR_2 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.58 ACL_RATE_CTRL0_3 th Address offset: 0x0A18 A Table 5-176 summarizes the ACL 3 rate control 0 register. m Table 5-176 ACL_RATE_CTRL0_3 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_3 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_3 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.59 ACL_RATE_CTRL1_3 Address offset: 0x0A1C Table 5-177 summarizes the ACL 3 rate control 1 register. 80-Y0619-1 Rev. A 196 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-177 ACL_RATE_CTRL1_3 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_3 Borrow enable ACL_RATE_UNIT_3 0 = Bytes 1 = Packets ACL_CF_3 Coupling flag for ingress rate limit ACL_CM_3 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_3 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_3 Excess burst size for ingress rate limit ACL_EIR_3 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.60 ACL_RATE_CTRL0_4 th Address offset: 0x0A20 A Table 5-178 summarizes the ACL 4 rate control 0 register. m Table 5-178 ACL_RATE_CTRL0_4 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_4 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_4 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.61 ACL_RATE_CTRL1_4 Address offset: 0x0A24 Table 5-179 summarizes the ACL 4 rate control 1 register. 80-Y0619-1 Rev. A 197 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-179 ACL_RATE_CTRL1_4 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_4 Borrow enable ACL_RATE_UNIT_4 0 = Bytes 1 = Packets ACL_CF_4 Coupling flag for ingress rate limit ACL_CM_4 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_4 ACL ingress rate limit control timer slot. 00 = 100 μs 01 =1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. ACL_EBS_4 Excess burst size for ingress rate limit ACL_EIR_4 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.62 ACL_RATE_CTRL0_5 th Address offset: 0x0A28 A Table 5-180 summarizes the ACL 5 rate control 0 register. m Table 5-180 ACL_RATE_CTRL0_5 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_5 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_5 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.63 ACL_RATE_CTRL1_5 Address offset: 0x0A2C Table 5-181 summarizes the ACL 5 rate control 1 register. 80-Y0619-1 Rev. A 198 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-181 ACL_RATE_CTRL1_5 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_5 Borrow enable ACL_RATE_UNIT_5 0 = Bytes 1 = Packets ACL_CF_5 Coupling flag for ingress rate limit ACL_CM_5 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_5 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. ACL_EBS_5 Excess burst size for ingress rate limit ACL_EIR_5 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.64 ACL_RATE_CTRL0_6 th Address offset: 0x0A30 A Table 5-182 summarizes the ACL 6 rate control 0 register. m Table 5-182 ACL_RATE_CTRL0_6 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_6 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_6 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.65 ACL_RATE_CTRL1_6 Address offset: 0x0A34 Table 5-183 summarizes the ACL 6 rate control 1 register. 80-Y0619-1 Rev. A 199 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-183 ACL_RATE_CTRL1_6 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_6 ACL_RATE_UNIT_6 ACL_CF_6 ACL_CM_6 ACL_RATE_TIME_ SLOT_6 ACL_EBS_6 ACL_EIR_6 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96kbps, do not select 100us as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.66 ACL_RATE_CTRL0_7 th Address offset: 0x0A38 A Table 5-184 summarizes the ACL 7 rate limit control 0 register. m Table 5-184 ACL_RATE_CTRL0_7 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_7 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_7 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.67 ACL_RATE_CTRL1_7 Address offset: 0x0A3C Table 5-185 summarizes the ACL 7 rate control 1 register. 80-Y0619-1 Rev. A 200 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-185 ACL_RATE_CTRL1_7 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_7 Borrow enable ACL_RATE_UNIT_7 0 = Bytes 1 = Packets ACL_CF_7 Coupling flag for ingress rate limit ACL_CM_7 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_7 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_7 Excess burst size for ingress rate limit ACL_EIR_7 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.68 ACL_RATE_CTRL0_8 th Address offset: 0x0A40 A Table 5-186 summarizes the ACL 8 rate control 0 register. m Table 5-186 ACL_RATE_CTRL0_8 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_8 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_8 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.69 ACL_RATE_CTRL1_8 Address offset: 0x0A44 Table 5-187 summarizes the ACL8 rate control 1 register. 80-Y0619-1 Rev. A 201 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-187 ACL_RATE_CTRL1_8 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_8 Borrow enable ACL_RATE_UNIT_8 0 = Bytes 1 = Packets ACL_CF_8 Coupling flag for ingress rate limit ACL_CM_8 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_8 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_8 Excess burst size for ingress rate limit ACL_EIR_8 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.70 ACL_RATE_CTRL0_9 th Address offset: 0x0A48 A Table 5-188 summarizes the ACL 9 rate control 0 register. m Table 5-188 ACL_RATE_CTRL0_9 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_9 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_9 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.71 ACL_RATE_CTRL1_9 Address offset: 0x0A4C Table 5-189 summarizes the ACL 9 rate control 1 register. 80-Y0619-1 Rev. A 202 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-189 ACL_RATE_CTRL1_9 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_9 Borrow enable ACL_RATE_UNIT_9 0 = Bytes 1 = Packets ACL_CF_9 Coupling flag for ingress rate limit ACL_CM_9 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_9 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_9 Excess burst size for ingress rate limit ACL_EIR_9 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.72 ACL_RATE_CTRL0_10 th Address 0x0A50 A Table 5-190 summarizes the ACL 10 rate control 0 register. m Table 5-190 ACL_RATE_CTRL0_10 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_10 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_10 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.73 ACL_RATE_CTRL1_10 Address offset: 0x0A54 Table 5-191 summarizes the ACL 10 rate control 1 register. 80-Y0619-1 Rev. A 203 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-191 ACL_RATE_CTRL1_10 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_10 Borrow enable ACL_RATE_UNIT_10 0 = Bytes 1 = Packets ACL_CF_10 Coupling flag for ingress rate limit ACL_CM_10 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_10 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_10 Excess burst size for ingress rate limit ACL_EIR_10 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.74 ACL_RATE_CTRL0_11 th Address offset: 0x0A58 A Table 5-192 summarizes the ACL 11 rate control 0 register. m Table 5-192 ACL_RATE_CTRL0_11 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_11 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_11 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.75 ACL_RATE_CTRL1_11 Address offset: 0x0A5C Table 5-193 summarizes the ACL 11 rate control 1 register. 80-Y0619-1 Rev. A 204 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-193 ACL_RATE_CTRL1_11 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_11 Borrow enable ACL_RATE_UNIT_11 0 = Bytes 1 = Packets ACL_CF_11 Coupling flag for ingress rate limit ACL_CM_11 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_11 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_11 Excess burst size for ingress rate limit ACL_EIR_11 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.76 ACL_RATE_CTRL0_12 th Address offset: 0x0A60 A Table 5-194 summarizes the ACL 12 rate control 0 register. m Table 5-194 ACL_RATE_CTRL0_12 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_12 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_12 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.77 ACL_RATE_CTRL1_12 Address offset: 0x0A64 Table 5-195 summarizes the ACL 12 rate control 1 register. 80-Y0619-1 Rev. A 205 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-195 ACL_RATE_CTRL1_12 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_12 Borrow enable ACL_RATE_UNIT_12 0 = Bytes 1 = Packets ACL_CF_12 Coupling flag for ingress rate limit ACL_CM_12 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_12 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. ACL_EBS_12 Excess burst size for ingress rate limit ACL_EIR_12 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.78 ACL_RATE_CTRL0_13 th Address offset: 0x0A68 A Table 5-196 summarizes the ACL 13 rate control 0 register. m Table 5-196 ACL_RATE_CTRL0_13 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_13 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_13 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.79 ACL_RATE_CTRL1_13 Address offset: 0x0A6C Table 5-197 summarizes the ACL 13 rate control 1 register. 80-Y0619-1 Rev. A 206 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-197 ACL_RATE_CTRL1_13 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_13 ACL_RATE_UNIT_13 ACL_CF_13 ACL_CM_13 ACL_RATE_TIME_ SLOT_13 ACL_EBS_13 ACL_EIR_13 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.80 ACL_RATE_CTRL0_14 th Address offset: 0x0A70 A Table 5-198 summarizes the ACL 14 rate control 0 register. m Table 5-198 ACL_RATE_CTRL0_14 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_14 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_14 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.81 ACL_RATE_CTRL1_14 Address offset: 0x0A74 Table 5-199 summarizes the ACL 14 rate control 1 register. 80-Y0619-1 Rev. A 207 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-199 ACL_RATE_CTRL1_14 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_14 Borrow enable ACL_RATE_UNIT_14 0 = Bytes 1 = Packets ACL_CF_14 Coupling flag for ingress rate limit ACL_CM_14 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_14 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. ACL_EBS_14 Excess burst size for ingress rate limit ACL_EIR_14 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.82 ACL_RATE_CTRL0_15 th Address offset: 0x0A78 A Table 5-200 summarizes the ACL 15 rate limit control 0 register. m Table 5-200 ACL_RATE_CTRL0_15 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_15 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_15 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.83 ACL_RATE_CTRL1_15 Address offset: 0x0A7C Table 5-201 summarizes the ACL 15 rate limit control 1 register. 80-Y0619-1 Rev. A 208 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-201 ACL_RATE_CTRL1_15 bit description Bits R/W Initial value Mnemonic Description 31:24 RO 0 RESERVED l 23 R/W 0 ACL_BORROW_EN_15 Borrow enable ia 22 R/W 0 ACL_RATE_UNIT_15 0 = Bytes 1 = Packets t 21 R/W 0 ACL_CF_15 Coupling flag for ingress rate limit n 20 R/W 0 ACL_CM_15 Color mode for ingress rate limit e 19:18 R/W 01 ACL_RATE_TIME_ onfid SLOT_15 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot 17:15 R/W 0 ACL_EBS_15 Excess burst size for ingress rate limit os C 14:0 R/W 0x7FFF ACL_EIR_15 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. her 5.7.84 ACL_RATE_CTRL0_16 At Address offset: 0x0A80 Table 5-202 summarizes the ACL 16 rate limit control 0 register. m Table 5-202 ACL_RATE_CTRL0_16 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_16 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_16 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.85 ACL_RATE_CTRL1_16 Address offset: 0x0A84 Table 5-203 summarizes the ACL 16 rate limit control 1 register. 80-Y0619-1 Rev. A 209 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-203 ACL_RATE_CTRL1_16 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_16 Borrow enable ACL_RATE_UNIT_16 0 = Bytes 1 = Packets ACL_CF_16 Coupling flag for ingress rate limit ACL_CM_16 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_16 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_16 Excess burst size for ingress rate limit ACL_EIR_16 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.86 ACL_RATE_CTRL0_17 th Address offset: 0x0A88 A Table 5-204 summarizes the ACL 17 rate limit control 0 register. m Table 5-204 ACL_RATE_CTRL1_17 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_17 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_17 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.87 ACL_RATE_CTRL1_17 Address offset: 0x0A8C Table 5-205 summarizes the ACL 17 rate limit control 1 register. 80-Y0619-1 Rev. A 210 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-205 ACL_RATE_CTRL1_17 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_17 Borrow enable ACL_RATE_UNIT_17 0 = Bytes 1 = Packets ACL_CF_17 Coupling flag for ingress rate limit ACL_CM_17 Color mode for ingress rate limit ACL_RATE_TIME_SLOT_ 17 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_17 Excess burst size for ingress rate limit ACL_EIR_17 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.88 ACL_RATE_CTRL0_18 th Address offset: 0x0A90 A Table 5-206 summarizes the ACL 18 rate limit control 0 register. m Table 5-206 ACL_RATE_CTRL0_18 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_18 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_18 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.89 ACL_RATE_CTRL1_18 Address offset: 0x0A94 Table 5-207 summarizes the ACL 18 rate limit control 1 register. 80-Y0619-1 Rev. A 211 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-207 ACL_RATE_CTRL1_18 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_18 ACL_RATE_UNIT_18 ACL_CF_18 ACL_CM_18 ACL_RATE_TIME_ SLOT_18 ACL_EBS_18 ACL_EIR_18 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.90 ACL_RATE_CTRL0_19 th Address offset: 0x0A98 A Table 5-208 summarizes the ACL 19 rate limit control 0 register. m Table 5-208 ACL_RATE_CTRL0_19 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_19 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_19 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.91 ACL_RATE_CTRL1_19 Address offset: 0x0A9C Table 5-209 summarizes the ACL 19 rate limit control 1 register. 80-Y0619-1 Rev. A 212 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-209 ACL_RATE_CTRL1_19 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_19 ACL_RATE_UNIT_19 ACL_CF_19 ACL_CM_19 ACL_RATE_TIME_ SLOT_19 ACL_EBS_19 ACL_EIR_19 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.92 ACL_RATE_CTRL0_20 th Address offset: 0x0AA0 A Table 5-210 summarizes the ACL 20 rate limit control 0 register. m Table 5-210 ACL_RATE_CTRL0_20 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_20 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_20 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.93 ACL_RATE_CTRL1_20 Address offset: 0x0AA4 Table 5-211 summarizes the ACL 20 rate limit control 1 register. 80-Y0619-1 Rev. A 213 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-211 ACL_RATE_CTRL1_20 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_20 ACL_RATE_UNIT_20 ACL_CF_20 ACL_CM_20 ACL_RATE_TIME_ SLOT_20 ACL_EBS_20 ACL_EIR_20 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.94 ACL_RATE_CTRL0_21 th Address offset: 0x0AA8 A Table 5-212 summarizes the ACL 21 rate limit control 0 register. m Table 5-212 ACL_RATE_CTRL0_21 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_21 Committed burst size for ingress rate limit lc14:0 R/W 0 ACL_CIR_21 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. a Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.95 ACL_RATE_CTRL1_21 Address offset: 0x0AAC Table 5-213 summarizes the ACL 21 rate limit control 1 register. 80-Y0619-1 Rev. A 214 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-213 ACL_RATE_CTRL1_21 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_21 Borrow enable ACL_RATE_UNIT_21 0 = Bytes 1 = Packets ACL_CF_21 Coupling flag for ingress rate limit ACL_CM_21 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_21 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_21 Excess burst size for ingress rate limit ACL_EIR_21 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.96 ACL_RATE_CTRL0_22 th Address offset: 0x0AB0 A Table 5-214 summarizes the ACL 22 rate limit control 0 register. m Table 5-214 ACL_RATE_CTRL0_22 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_22 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_22 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.97 ACL_RATE_CTRL1_22 Address offset: 0x0AB4 Table 5-215 summarizes the ACL 22 rate limit control 1 register. 80-Y0619-1 Rev. A 215 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-215 ACL_RATE_CTRL1_22 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0X7FFF RESERVED ACL_BORROW_EN_22 Borrow enable ACL_RATE_UNIT_22 0 = Bytes 1 = Packets ACL_CF_22 Coupling flag for ingress rate limit ACL_CM_22 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_22 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_22 Excess burst size for ingress rate limit ACL_EIR_22 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.98 ACL_RATE_CTRL0_23 th Address offset: 0x0AB8 A Table 5-216 summarizes the ACL 23 rate limit control 0 register. m Table 5-216 ACL_RATE_CTRL0_23 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_23 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_23 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.99 ACL_RATE_CTRL1_23 Address offset: 0x0ABC Table 5-217 summarizes the ACL 23 rate limit control 1 register. 80-Y0619-1 Rev. A 216 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-217 ACL_RATE_CTRL1_23 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_23 Borrow enable ACL_RATE_UNIT_23 0 = Bytes 1 = Packets ACL_CF_23 Coupling flag for ingress rate limit ACL_CM_23 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_23 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_23 Excess burst size for ingress rate limit ACL_EIR_23 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.100 ACL_RATE_CTRL0_24 th Address offset: 0x0AC0 A Table 5-218 summarizes the ACL 24 rate limit control 0 register. m Table 5-218 ACL_RATE_CTRL0_24 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_24 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_24 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.101 ACL_RATE_CTRL1_24 Address offset: 0x0AC4 Table 5-219 summarizes the ACL 24 rate limit control 1 register. 80-Y0619-1 Rev. A 217 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-219 ACL_RATE_CTRL1_24 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_24 Borrow enable ACL_RATE_UNIT_24 0 = Bytes 1 = Packets ACL_CF_24 Coupling flag for ingress rate limit ACL_CM_24 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_24 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_24 Excess burst size for ingress rate limit ACL_EIR_24 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.102 ACL_RATE_CTRL0_25 th Address offset: 0x0AC8 A Table 5-220 summarizes the ACL 25 rate limit control register 0. m Table 5-220 ACL_RATE_CTRL0_25 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_25 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_25 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.103 ACL_RATE_CTRL1_25 Address offset: 0x0ACC Table 5-221 summarizes the ACL 25 rate limit control 1 register. 80-Y0619-1 Rev. A 218 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-221 ACL_RATE_CTRL1_25 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 RO onfid 17:15 R/W os C 14:0 RO 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_25 ACL_RATE_UNIT_25 ACL_CF_25 ACL_CM_25 ACL_RATE_TIME_ SLOT_25 ACL_EBS_25 ACL_EIR_25 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.104 ACL_RATE_CTRL0_26 th Address offset: 0x0AD0 A Table 5-222 summarizes the ACL 26 rate limit control 0 register. m Table 5-222 ACL_RATE_CTRL0_26 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_26 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_26 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.105 ACL_RATE_CTRL1_26 Address offset: 0x0AD4 Table 5-223 summarizes the ACL 26 rate limit control 1 register. 80-Y0619-1 Rev. A 219 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-223 ACL_RATE_CTRL1_26 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_26 ACL_RATE_UNIT_26 ACL_CF_26 ACL_CM_26 ACL_RATE_TIME_ SLOT_26 ACL_EBS_26 ACL_EIR_26 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.106 ACL_RATE_CTRL0_27 th Address offset: 0x0AD8 A Table 5-224 summarizes the ACL 27 rate limit control 0 register. m Table 5-224 ACL_RATE_CTRL0_27 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_27 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_27 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.107 ACL_RATE_CTRL1_27 Address offset: 0x0ADC Table 5-225 summarizes the ACL 27 rate limit control 1 register. 80-Y0619-1 Rev. A 220 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-225 ACL_RATE_CTRL1_27 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_27 ACL_RATE_UNIT_27 ACL_CF_27 ACL_CM_27 ACL_RATE_TIME_ SLOT_27 ACL_EBS_27 ACL_EIR_27 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.108 ACL_RATE_CTRL0_28 th Address offset: 0x0AE0 A Table 5-226 summarizes the ACL 28 rate limit control 0 register. m Table 5-226 ACL_RATE_CTRL0_28 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_28 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_28 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.109 ACL_RATE_CTRL1_28 Address offset: 0x0AE4 Table 5-227 summarizes the ACL 28 rate limit control 1 register. 80-Y0619-1 Rev. A 221 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-227 ACL_RATE_CTRL1_28 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_28 Borrow enable ACL_RATE_UNIT_28 0 = Bytes 1 = Packets ACL_CF_28 Coupling flag for ingress rate limit ACL_CM_28 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_28 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_28 Excess burst size for ingress rate limit ACL_EIR_28 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.110 ACL_RATE_CTRL0_29 th Address offset: 0x0AE8 A Table 5-228 summarizes the ACL 29 rate limit control 0 register. m Table 5-228 ACL_RATE_CTRL0_29 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_29 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_29 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.111 ACL_RATE_CTRL1_29 Address offset: 0x0AEC Table 5-229 summarizes the ACL 29 rate limit control 1 register. 80-Y0619-1 Rev. A 222 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-229 ACL_RATE_CTRL1_29 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_29 Borrow enable ACL_RATE_UNIT_29 0 = Bytes 1 = Packets ACL_CF_29 Coupling flag for ingress rate limit ACL_CM_29 Color mode for ingress rate limit ACL_RATE_TIME_ SLOT_29 ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot ACL_EBS_29 Excess burst size for ingress rate limit ACL_EIR_29 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.112 ACL_RATE_CTRL0_30 th Address offset: 0x0AF0 A Table 5-230 summarizes the ACL 30 rate limit control 0 register. m Table 5-230 ACL_RATE_CTRL0_30 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_30 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_30 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.113 ACL_RATE_CTRL1_30 Address offset: 0x0AF4 Table 5-231 summarizes the ACL 30 rate limit control 1 register. 80-Y0619-1 Rev. A 223 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-231 ACL_RATE_CTRL1_30 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_30 ACL_RATE_UNIT_30 ACL_CF_30 ACL_CM_30 ACL_RATE_TIME_ SLOT_30 ACL_EBS_30 ACL_EIR_30 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.114 ACL_RATE_CTRL0_31 th Address offset: 0x0AF8 A Table 5-232 summarizes the ACL 31 rate limit control 0 register. m Table 5-232 ACL_RATE_CTRL0_31 bit description Bits R/W Initial value Mnemonic Description m 31:18 RO 0 RESERVED o 17:15 R/W 0 ACL_CBS_31 Committed burst size for ingress rate limit alc14:0 R/W 0x7FFF ACL_CIR_31 Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Qu5.7.115 ACL_RATE_CTRL1_31 Address offset: 0x0AFC Table 5-233 summarizes the ACL 31 rate limit control 1 register. 80-Y0619-1 Rev. A 224 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-233 ACL_RATE_CTRL1_31 bit description Bits R/W Initial value Mnemonic Description 31:24 RO l 23 R/W ia 22 R/W t 21 R/W n 20 R/W e 19:18 R/W onfid 17:15 R/W os C 14:0 R/W 0 0 0 0 0 01 0 0x7FFF RESERVED ACL_BORROW_EN_31 ACL_RATE_UNIT_31 ACL_CF_31 ACL_CM_31 ACL_RATE_TIME_ SLOT_31 ACL_EBS_31 ACL_EIR_31 Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit ACL ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.116 PORT0_ING_RATE_CTRL0 th Address offset: 0x0B00 A Table 5-234 summarizes the port 0 ingress rate limit control 0 register. m Table 5-234 PORT0_ING_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description m 31:24 R/W ‘h18 ADD_RATE_BYTE_0 Byte number is added to frame when calculate rate limit. o Default is 24 bytes for IPG, preamble, CRC and SFD. lc23:22 R/W 01 ING_RATE_C_ Qua TIME_SLOT_0 Committed Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. 21 RO 0 RESERVED 20 R/W 0 ING_RATE_MODE_0 0 = Two single rate 1 = One two-rate three-color 80-Y0619-1 Rev. A 225 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-234 PORT0_ING_RATE_CTRL0 bit description (cont.) Bits R/W Initial value Mnemonic Description 19:18 RO 17:15 /W tial 14:0 R/W 0 0 0x7FFF RESERVED ING_CBS_0 ING_CIR_0 Committed burst size for ingress rate limit Committed Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. en 5.7.117 PORT0_ING_RATE_CTRL1 id Address offset: 0x0B04 nf Table 5-235 summarizes the port 0 ingress rate limit control 1 register. o Table 5-235 PORT0_ING_RATE_CTRL1 bit description C Bits R/W Initial value Mnemonic Description 31:24 RO 0 RESERVED s 23 R/W 0 ING_BORROW_EN_0 Borrow enable ro 22 R/W 0 ING_RATE_UNIT_0 0 = Bytes 1 = Packets e 21 R/W 0 ING_CF_0 Coupling flag for ingress rate limit h 20 R/W 0 ING_CM_0 Color mode for ingress rate limit t 19:18 R/W 01 ING_RATE_E_TIME_SLOT_0 Excess Ingress rate limit control timer slot. A 00 = 100 μs m m 17:15 R/W o14:0 R/W 0 0x7FFF ING_EBS_0 ING_EIR_0 Qualc 5.7.118 PORT0_ING_RATE_CTRL2 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Excess Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. Address offset: 0x0B08 Table 5-236 summarizes the port 0 ingress rate limit control 2 register. 80-Y0619-1 Rev. A 226 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-236 PORT0_ING_RATE_CTRL2 bit description Bits R/W Initial value Mnemonic Description 31:16 RO 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED l ING_C_MULTI_RATE_EN_0 Ingress committed rate limit enable to count the multicast frames tia ING_C_UNI_RATE_EN_0 Ingress committed rate limit enable to count the unicast frames ING_C_UNK_MULTI_RATE_EN_0 Ingress committed rate limit enable to n count the unknown multicast frames e ING_C_UNK_UNI_RATE_EN_0 Ingress committed rate limit enable to count the unknown unicast frames fid ING_C_BROAD_RATE_EN_0 Ingress committed rate limit enable to count the broadcast frames n ING_C_MANAGE_RATE_EN_0 Ingress committed rate limit enable to count the management frames o ING_C_TCP_CTRL_RATE_EN_0 Ingress committed rate limit enable to count the TCP control frames C ING_C_ING_MIRROR_RATE_EN_0 Ingress committed rate limit enable to count the ingress mirror frames s ING_E_MULTI_RATE_EN_0 Ingress excess rate limit enable to count the multicast frames ro ING_E_UNI_RATE_EN_0 Ingress excess rate limit enable to count the unicast frames e ING_E_UNK_MULTI_RATE_EN_0 Ingress excess rate limit enable to count the unknown multicast frames Ath ING_E_UNK_UNI_RATE_EN_0 Ingress excess rate limit enable to count the unknown unicast frames 3 R/W 0 ING_E_BROAD_RATE_EN_0 Ingress excess rate limit enable to count 2 R/W m0 ING_E_MANAGE_RATE_EN_0 the broadcast frames Ingress excess rate limit enable to count the management frames 1 R/W 0 ING_E_TCP_CTRL_RATE_EN_0 Ingress excess rate limit enable to count m the TCP control frames o0 R/W 0 ING_E_ING_MIRROR_RATE_EN_0 Ingress excess rate limit enable to count the ingress mirror frames alc 5.7.119 PORT2_ING_RATE_CTRL0 u Address offset: 0x0B20 Q Table 5-237 summarizes the port 2 ingress rate limit control 0 register. 80-Y0619-1 Rev. A 227 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-237 PORT2_ING_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31:24 R/W ial 23:22 R/W fident 21 RO 20 R/W on 19:18 RO 17:15 R/W ros C 14:0 R/W 'h18 01 0 0 0 0 0x7FFF ADD_RATE_BYTE_2 Byte number is added to frame when calculate rate limit. Default is 24 bytes for IPG, preamble, CRC and SFD. ING_RATE_C_TIME_ SLOT_2 Committed Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. RESERVED ING_RATE_MODE_2 0 = Two single rate 1 = One two-rate three-color RESERVED ING_CBS_2 Committed burst size for ingress rate limit ING_CIR_2 Committed Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no frame is received in from this port. he 5.7.120 PORT2_ING_RATE_CTRL1 At Address offset: 0x0B24 m Table 5-238 summarizes the port 2 ingress rate limit control 1 register. Table 5-238 PORT2_ING_RATE_CTRL1 bit description Bits R/W Initial value Mnemonic m 31:24 RO 0 RESERVED o23 R/W 0 ING_BORROW_EN_2 lc22 R/W 0 ING_RATE_UNIT_2 a 21 R/W 0 ING_CF_2 Qu 20 R/W 0 ING_CM_2 Description Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit 80-Y0619-1 Rev. A 228 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-238 PORT2_ING_RATE_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 19:18 R/W 01 ING_RATE_E_TIME_ SLOT_2 ntial 17:15 R/W fide 14:0 R/W 0 0x7FFF ING_EBS_2 ING_EIR_2 Excess Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Excess Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. on 5.7.121 PORT2_ING_RATE_CTRL2 C Address offset: 0x0B28 s Table 5-239 summarizes the port 2 ingress rate limit control 2 register. ro Table 5-239 PORT2_ING_RATE_CTRL2 bit description e Bits R/W Initial value Mnemonic h 31:16 RO 0 RESERVED At 15 R/W 0 ING_C_MULTI_RATE_EN_2 Description Ingress committed rate limit enable to count the multicast frames 14 R/W 0 ING_C_UNI_RATE_EN_2 Ingress committed rate limit enable to count the unicast frames m 13 R/W 0 ING_C_UNK_MULTI_RATE_EN_2 Ingress committed rate limit enable to count the unknown multicast frames 12 R/W 0 ING_C_UNK_UNI_RATE_EN_2 Ingress committed rate limit enable to m count the unknown unicast frames o11 R/W 0 ING_C_BROAD_RATE_EN_2 Ingress committed rate limit enable to count the broadcast frames lc10 R/W 0 ING_C_MANAGE_RATE_EN_2 Ingress committed rate limit enable to count the management frames a 9 R/W 0 ING_C_TCP_CTRL_RATE_EN_2 Ingress committed rate limit enable to u count the TCP control frames 8 R/W 0 ING_C_ING_MIRROR_RATE_EN_2 Ingress committed rate limit enable to Q count the ingress mirror frames 7 R/W 0 ING_E_MULTI_RATE_EN_2 Ingress excess rate limit enable to count the multicast frames 6 R/W 0 ING_E_UNI_RATE_EN_2 Ingress excess rate limit enable to count the unicast frames 80-Y0619-1 Rev. A 229 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-239 PORT2_ING_RATE_CTRL2 bit description (cont.) Bits R/W Initial value Mnemonic Description 5 R/W 0 ING_E_UNK_MULTI_RATE_EN_2 Ingress excess rate limit enable to count the unknown multicast frames l 4 R/W 0 ING_E_UNK_UNI_RATE_EN_2 Ingress excess rate limit enable to count the unknown unicast frames ia 3 R/W 0 ING_E_BROAD_RATE_EN_2 Ingress excess rate limit enable to count the broadcast frames t 2 R/W 0 ING_E_MANAGE_RATE_EN_2 Ingress excess rate limit enable to count n the management frames e 1 R/W 0 ING_E_TCP_CTRL_RATE_EN_2 Ingress excess rate limit enable to count the TCP control frames id 0 R/W 0 ING_E_ING_MIRROR_RATE_EN_2 Ingress excess rate limit enable to count f the ingress mirror frames on 5.7.122 PORT3_ING_RATE_CTRL0 C Address offset: 0x0B30 Table 5-240 summarizes the port 3 ingress rate limit control 0 register. os Table 5-240 PORT3_ING_RATE_CTRL0 bit description r Bits R/W Initial value Mnemonic e 31:24 R/W ‘h18 ADD_RATE_ h BYTE_3 t 23:22 R/W 01 ING_RATE_C_ ATIME_SLOT_3 Description Byte number is added to frame when calculate rate limit. Default is 24 bytes for IPG, preamble, CRC and SFD. Committed Ingress rate limit control timer slot. 00 = 100 μs m m 21 RO 0 o20 R/W 0 lc19:18 RO a17:15 R/W Qu 14:0 R/W 0 0 0x7FFF RESERVED ING_RATE_ MODE_3 RESERVED ING_CBS_3 ING_CIR_3 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. 0 = Two single rate 1 = One two-rate three-color Committed burst size for ingress rate limit Committed Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no frame is received in from this port. 80-Y0619-1 Rev. A 230 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.7.123 PORT3_ING_RATE_CTRL1 Address offset: 0x0B34 Table 5-241 summarizes the port 3 ingress rate limit control 1 register. l Table 5-241 PORT3_ING_RATE_CTRL1 bit description ia Bits R/W Initial value Mnemonic t 31:24 RO 0 RESERVED n 23 R/W 0 ING_BORROW_EN_3 e 22 R/W 0 ING_RATE_UNIT_3 id 21 R/W 0 ING_CF_3 f 20 R/W 0 ING_CM_3 n 19:18 R/W 01 ING_RATE_E_TIME_ o SLOT_3 os C 17:15 R/W Ather 14:0 R/W 0 0x7FFF ING_EBS_3 ING_EIR_3 Description Borrow enable 0 = Bytes 1 = Packets Coupling flag for ingress rate limit Color mode for ingress rate limit Excess Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Excess Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. m 5.7.124 PORT3_ING_RATE_CTRL2 Address offset: 0x0B38 m Table 5-242 summarizes the port 3 ingress rate limit control 2 register. lco Table 5-242 PORT3_ING_RATE_CTRL2 bit description Bits R/W Initial value Mnemonic a31:16 RO 0 RESERVED Qu 15 R/W 0 ING_C_MULTI_RATE_EN_3 Description Ingress committed rate limit enable to count the multicast frames 14 R/W 0 ING_C_UNI_RATE_EN_3 Ingress committed rate limit enable to count the unicast frames 13 R/W 0 ING_C_UNK_MULTI_RATE_EN_3 Ingress committed rate limit enable to count the unknown multicast frames 80-Y0619-1 Rev. A 231 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-242 PORT3_ING_RATE_CTRL2 bit description (cont.) Bits R/W Initial value Mnemonic Description 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 ING_C_UNK_UNI_RATE_EN_3 ING_C_BROAD_RATE_EN_3 ial ING_C_MANAGE_RATE_EN_3 t ING_C_TCP_CTRL_RATE_EN_3 en ING_C_ING_MIRROR_RATE_EN_3 id ING_E_MULTI_RATE_EN_3 f ING_E_UNI_RATE_EN_3 on ING_E_UNK_MULTI_RATE_EN_3 C ING_E_UNK_UNI_RATE_EN_3 s ING_E_BROAD_RATE_EN_3 o ING_E_MANAGE_RATE_EN_3 er ING_E_TCP_CTRL_RATE_EN_3 Ath ING_E_ING_MIRROR_RATE_EN_3 Ingress committed rate limit enable to count the unknown unicast frames Ingress committed rate limit enable to count the broadcast frames Ingress committed rate limit enable to count the management frames Ingress committed rate limit enable to count the TCP control frames Ingress committed rate limit enable to count the ingress mirror frames Ingress excess rate limit enable to count the multicast frames Ingress excess rate limit enable to count the unicast frames Ingress excess rate limit enable to count the unknown multicast frames Ingress excess rate limit enable to count the unknown unicast frames Ingress excess rate limit enable to count the broadcast frames Ingress excess rate limit enable to count the management frames Ingress excess rate limit enable to count the TCP control frames Ingress excess rate limit enable to count the ingress mirror frames m 5.7.125 PORT6_ING_RATE_CTRL0 Address offset: 0x0B60 Qualcom Table 5-243 summarizes the port 6 ingress rate limit control 0 register. 80-Y0619-1 Rev. A 232 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-243 PORT6_ING_RATE_CTRL0 bit description Bits R/W Initial value Mnemonic Description 31:24 R/W l 23:22 R/W identia 21 RO f 20 R/W n 19:18 RO o 17:15 R/W os C 14:0 R/W 'h18 01 0 0 0 0 0x7FFF ADD_RATE_BYTE_6 Byte number is added to frame when calculate rate limit. Default is 24 bytes for IPG, preamble, CRC and SFD. ING_RATE_C_TIME_ SLOT_6 Committed Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. RESERVED ING_RATE_MODE_6 0 = Two single rate 1 = One two-rate three-color RESERVED ING_CBS_6 Committed burst size for ingress rate limit ING_CIR_6 Committed Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for egress priority 2. If these bits are set to 15'h0, no frame is received in from this port. er 5.7.126 PORT6_ING_RATE_CTRL1 th Address offset: 0x0B64 A Table 5-244 summarizes the port 6 ingress rate limit control 1 register. Table 5-244 PORT6_ING_RATE_CTRL1 bit description m Bits R/W Initial value Mnemonic m 31:24 RO 'h18 RESERVED o23 R/W 0 ING_BORROW_EN_6 Borrow enable Description lc22 R/W 0 ING_RATE_UNIT_6 0 = Bytes 1 = Packets a 21 R/W 0 ING_CF_6 Coupling flag for ingress rate limit Qu 20 R/W 0 ING_CM_6 Color mode for ingress rate limit 80-Y0619-1 Rev. A 233 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-244 PORT6_ING_RATE_CTRL1 bit description (cont.) Bits R/W Initial value Mnemonic Description 19:18 R/W ntial 17:15 R/W fide 14:0 R/W 01 0 0x7FFF ING_RATE_E_TIME_ SLOT_6 ING_EBS_6 ING_EIR_6 Excess Ingress rate limit control timer slot. 00 = 100 μs 01 = 1 ms 10 = 10 ms 11 = 100 ms Note: If port rate limit set to less than 96 kbps, do not select 100 μs as time slot. Excess burst size for ingress rate limit Excess Ingress rate limit for all priority. Rate is limited to times of 32 kbps. Default 15'h7FFF is for disable rate limit for ingress. If these bits are set to 15'h0, no frame is received in from this port. on 5.7.127 PORT6_ING_RATE_CTRL2 C Address offset: 0x0B68 s Table 5-245 summarizes the port 6 ingress rate limit control 2 register. ro Table 5-245 PORT6_ING_RATE_CTRL2 bit description e Bits R/W Initial value Mnemonic h 31:16 RO 0 RESERVED At 15 R/W 0 ING_C_MULTI_RATE_EN_6 Description Ingress committed rate limit enable to count the multicast frames 14 R/W 13 R/W m0 ING_C_UNI_RATE_EN_6 0 ING_C_UNK_MULTI_RATE_EN_6 Ingress committed rate limit enable to count the unicast frames Ingress committed rate limit enable to 12 R/W 0 om 11 R/W 0 lc10 R/W 0 a 9 R/W 0 Qu 8 R/W 0 count the unknown multicast frames ING_C_UNK_UNI_RATE_EN_6 Ingress committed rate limit enable to count the unknown unicast frames ING_C_BROAD_RATE_EN_6 Ingress committed rate limit enable to count the broadcast frames ING_C_MANAGE_RATE_EN_6 Ingress committed rate limit enable to count the management frames ING_C_TCP_CTRL_RATE_EN_6 Ingress committed rate limit enable to count the TCP control frames ING_C_ING_MIRROR_RATE_EN_6 Ingress committed rate limit enable to count the ingress mirror frames 7 R/W 0 ING_E_MULTI_RATE_EN_6 Ingress excess rate limit enable to count the multicast frames 6 R/W 0 ING_E_UNI_RATE_EN_6 Ingress excess rate limit enable to count the unicast frames 80-Y0619-1 Rev. A 234 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-245 PORT6_ING_RATE_CTRL2 bit description (cont.) Bits R/W Initial value Mnemonic Description 5 R/W 0 ING_E_UNK_MULTI_RATE_EN_6 Ingress excess rate limit enable to count the unknown multicast frames 4 R/W 0 ING_E_UNK_UNI_RATE_EN_6 Ingress excess rate limit enable to count l the unknown unicast frames ia 3 R/W 0 ING_E_BROAD_RATE_EN_6 Ingress excess rate limit enable to count the broadcast frames t 2 R/W 0 ING_E_MANAGE_RATE_EN_6 Ingress excess rate limit enable to count n the management frames e 1 R/W 0 ING_E_TCP_CTRL_RATE_EN_6 Ingress excess rate limit enable to count the TCP control frames id 0 R/W 0 ING_E_ING_MIRROR_RATE_EN_6 Ingress excess rate limit enable to count the ingress mirror frames onf 5.7.128 CPU_GROUP_CTRL Address offset: 0x0B70 C Table 5-246 summarizes the CPU packet remap priority control register. os Table 5-246 CPU_GROUP_CTRL bit description r Bits R/W e 31 R/W h 30:23 RO t 22:20 R/W A 19 RO Initial value Mnemonic 0 CPU_GROUP_REMAP_EN 0 RESERVED 0 CPU_GROUP5_PRI 0 RESERVED Description Remap the packet (to CPU) priority Header type 5'h19–5'h1A 18:16 R/W 1 15 RO 0 m 14:12 R/W 2 m 11 RO 0 o10:8 R/W 3 7 RO 0 lc6:4 R/W 4 a 3 RO 0 Qu 2:0 R/W 5 CPU_GROUP4_PRI RESERVED CPU_GROUP3_PRI RESERVED CPU_GROUP2_PRI RESERVED CPU_GROUP1_PRI RESERVED CPU_GROUP0_PRI Header type 5'h17–5'h18 Header type 5'hE–5'h16 Header type 5'h5–5'hD Header type 5'h3,5'h4 Header type 5'h1,5'h2. 5'h1C 5.8 PKT edit control registers Table 5-247 summarizes the packet editor registers. 80-Y0619-1 Rev. A 235 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-247 Packet editor register summary Offset range Name 0x0C00 l 0x0C40–0x0C44 ia 0x0C4C 0x0C50 t 0x0C60–0x0C64 n 0x0C70-0x0C7C e 0x0C80 PKT edit control register Port0 queue remap register Port2 queue remap register Port3 queue remap register Port6 queue remap register Router default VID register Router egress VLAN mode register fid 5.8.1 PKT_EDIT_CTRL n Address offset: 0x0C00 o Table 5-248 summarizes the PKT edit control register. C Table 5-248 PKT_EDIT_CTRL bit description s Bits R/W Initial value Mnemonic Description o 31:27 RO 0 RESERVED r 26 R/W 0 VLAN_PRI_REMAP_EN_6 1 = Frame sent out from port6; remap priority e based on frame priority. h 25 RO 0 RESERVED t 24 RO 0 RESERVED A 23 R/W 0 VLAN_PRI_REMAP_EN_3 1 = Frame sent out from port3; remap priority based on frame priority. 22 R/W 0 VLAN_PRI_REMAP_EN_2 1 = Frame sent out from port2; remap priority based on frame priority. m 21 RO 0 RESERVED m 20 R/W 0 VLAN_PRI_REMAP_EN_0 1 = Frame sent out from port0; remap priority based on frame priority. o 19:12 R/W 0 IP_TTL lc11 R/W 0 IP_TTL_CHANGE_EN 1 = Frame TTL change to IP_TTL. 10 R/W 0 IPV4_ID_RANDOM_EN 1 = Frame sent out with random ID. a 9 R/W 0 IPV4_DF_CLEAR_EN 1 = IPv4 DF field cleared to zero. u 8 RO 0 RESERVED Q 7 RO 0 RESERVED 6:2 RO 0 RESERVED 80-Y0619-1 Rev. A 236 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-248 PKT_EDIT_CTRL bit description (cont.) Bits R/W Initial value Mnemonic Description 1 R/W 0 TO_CPU_VID_CHG_EN The VID option for the TO CPU frames. 0 = Keep original VID 1 = Change to internal VID l 0 R/W 0 RM_RTD_PPPOE_EN When packet is routed, and the PPPOE_CMD in ia ARP table is zero. t 0 = Do nothing. 1 = Remove PPPoE header if the packet has n PPPoE header. ide 5.8.2 PORT0_QUEUE_REMAP_REG0 f Address offset: 0x0C40 n Table 5-249 summarizes the port 0 queue remap register 0. Co Table 5-249 PORT0_QUEUE_REMAP_REG0 bit description Bits R/W s 31 R/W o 30:28 RO r 27:24 R/W e 23 R/W h 22:20 RO t 19:16 R/W A 15 R/W Initial value 0 0 0 0 0 0 0 Mnemonic PORT0_QUEUE3_EN RESERVED PORT0_QUEUE3_IDX PORT0_QUEUE2_EN RESERVED PORT0_QUEUE2_IDX PORT0_QUEUE1_EN Description Enable queue 3 remap Queue 3 remap table index Enable queue 2 remap Queue 2 remap table index Enable queue 1 remap 14:12 RO 11:8 R/W m0 0 RESERVED PORT0_QUEUE1_IDX 7 R/W 6:4 RO m 3:0 R/W 0 PORT0_QUEUE0_EN 0 RESERVED 0 PORT0_QUEUE0_IDX lco 5.8.3 PORT0_QUEUE_REMAP_REG1 aAddress offset: 0x0C44 Qu Table 5-250 summarizes the port 0 queue remap register 1. Queue 1 remap table index Enable queue 0 remap Queue 0 remap table index 80-Y0619-1 Rev. A 237 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-250 PORT0_QUEUE_REMAP_REG0 bit description Bits R/W Initial value Mnemonic Description 31:16 RO l 15 R/W ia 14:12 RO 11:8 R/W t 7 R/W n 6:4 RO e 3:0 R/W 0 RESERVED 0 PORT0_QUEUE5_EN Enable queue 5 remap 0 RESERVED 0 PORT0_QUEUE5_IDX Queue 5 remap table index 0 PORT0_QUEUE4_EN Enable queue 4 remap 0 RESERVED 0 PORT0_QUEUE4_IDX Queue 4 remap table index fid 5.8.4 PORT2_QUEUE_REMAP_REG0 n Address offset: 0x0C4C o Table 5-251 summarizes the port 2 queue remap register 0. C Table 5-251 PORT2_QUEUE_REMAP_REG0 bit description s Bits R/W o 31 R/W r 30:28 RO e 27:24 R/W h 23 R/W At 22:20 RO Initial value Mnemonic 0 PORT2_QUEUE3_EN 0 RESERVED 0 PORT2_QUEUE3_IDX 0 PORT2_QUEUE2_EN 0 RESERVED Description Enable queue 3 remap Queue 3 remap table index Enable queue 2 remap 19:16 R/W 0 PORT2_QUEUE2_IDX Queue 2 remap table index 15 R/W m 14:12 RO 11:8 R/W m 7 R/W o6:4 RO lc3:0 R/W 0 PORT2_QUEUE1_EN 0 RESERVED 0 PORT2_QUEUE1_IDX 0 PORT2_QUEUE0_EN 0 RESERVED 0 PORT2_QUEUE0_IDX a5.8.5 PORT3_QUEUE_REMAP_REG0 Qu Address offset: 0x0C50 Enable queue 1 remap Queue 1 remap table index Enable queue 0 remap Queue 0 remap table index Table 5-252 summarizes the port 3 queue remap register 0. 80-Y0619-1 Rev. A 238 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-252 PORT3_QUEUE_REMAP_REG0 bit description Bits R/W Initial value Mnemonic Description 31 R/W l 30:28 RO ia 27:24 R/W 23 R/W t 22:20 RO n 19:16 R/W e 15 R/W id 14:12 RO f 11:8 R/W 7 R/W n 6:4 RO o 3:0 R/W 0 PORT3_QUEUE3_EN Enable queue 3 remap 0 RESERVED 0 PORT3_QUEUE3_IDX Queue 3 remap table index 0 PORT3_QUEUE2_EN Enable queue 2 remap 0 RESERVED 0 PORT3_QUEUE2_IDX Queue 2 remap table index 0 PORT3_QUEUE1_EN Enable queue 1 remap 0 RESERVED 0 PORT3_QUEUE1_IDX Queue 1 remap table index 0 PORT3_QUEUE0_EN Enable queue 0 remap 0 RESERVED 0 PORT3_QUEUE0_IDX Queue 0 remap table index s C 5.8.6 PORT6_QUEUE_REMAP_REG0 o Address offset: 0x0C60 r Table 5-253 summarizes the port 6 queue remap register 0. he Table 5-253 PORT6_QUEUE_REMAP_REG0 bit description At Bits R/W Initial value Mnemonic Description 31 R/W 0 PORT6_QUEUE3_EN Enable queue 3 remap 30:28 RO 0 m 27:24 R/W 0 23 R/W 0 m 22:20 RO 0 o19:16 R/W 0 lc15 R/W 0 14:12 RO 0 a 11:8 R/W 0 Qu 7 R/W 0 RESERVED PORT6_QUEUE3_IDX PORT6_QUEUE2_EN RESERVED PORT6_QUEUE2_IDX PORT6_QUEUE1_EN RESERVED PORT6_QUEUE1_IDX PORT6_QUEUE0_EN Queue 3 remap table index Enable queue 2 remap Queue 2 remap table index Enable queue 1 remap Queue 1 remap table index Enable queue 0 remap Queue 0 remap table index Enable queue 0 remap 6:4 RO 0 RESERVED 3:0 R/W 0 PORT6_QUEUE0_IDX Queue 0 remap table index 80-Y0619-1 Rev. A 239 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.8.7 PORT6_QUEUE_REMAP_REG1 Address offset: 0x0C64 Table 5-254 summarizes the port 6 queue remap register 1. l Table 5-254 PORT6_QUEUE_REMAP_REG1 bit description ia Bits t 31:16 n 15 e 14:12 id 11:8 f 7 6:4 n 3:0 R/W Initial value Mnemonic RO 0 RESERVED R/W 0 PORT6_QUEUE5_EN RO 0 RESERVED R/W 0 PORT6_QUEUE5_IDX RO 0 PORT6_QUEUE4_EN RO 0 RESERVED R/W 0 PORT6_QUEUE4_IDX Description Enable queue 5 remap Queue 5 remap table index Enable queue 4 remap Queue 4 remap table index Co 5.8.8 Router default VID register 0 s Address offset: 0x0C70 o Table 5-255 summarizes the router default VID register 0. er Table 5-255 Router default VID register 0 bit description h Bits At 31:28 R/W Initial value Mnemonic RO 0 RESERVED Description 27:16 RO 1 RESERVED 15:12 RO m 11:0 R/W 0 RESERVED 1 ROUTER_DEFAULT_VID0 Port 0 default VID for router m 5.8.9 Router default VID register 1 o Address offset: 0x0C74 lcTable 5-256 summarizes the router default VID register 1. uaTable 5-256 Router default VID register 1 bit description Q Bits R/W Initial value Mnemonic Description 31:28 RO 0 Reserved 27:16 R/W 1 ROUTER_DEFAULT_VID3 Port 3 default VID for router 80-Y0619-1 Rev. A 240 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-256 Router default VID register 1 bit description (cont.) Bits R/W Initial value Mnemonic Description 15:12 RO 11:0 R/W 0 Reserved 1 ROUTER_DEFAULT_VID2 Port 2 default VID for router ial 5.8.10 Router default VID register 3 t Address offset: 0x0C7C n Table 5-257 summarizes the router default VID register 3. ide Table 5-257 Router default VID register 3 bit description f Bits R/W Initial value Mnemonic Description n 31:12 RO 0 Reserved o 11:0 R/W 1 ROUTER_DEFAULT_VID6 Port 6 default VID for router C 5.8.11 Router egress VLAN mode s Address offset: 0x0C80 ro Table 5-258 summarizes the router default VID register 3. e Table 5-258 Router egress VLAN mode bit description th Bits R/W Initial value Mnemonic A 31:26 RO 0 RESERVED Description 25:24 R/W 23:22 RO m0 ROUTER_EG_VLAN_MODE6 Router egress VLAN mode of port 6 0 RESERVED 21:20 RO 0 19:18 RO 0 m 17:16 RO 0 o 15:14 RO 0 lc13:12 R/W 0 11:10 RO 0 a 9:8 R/W 0 u 7:6 RO 0 Q 5:4 RO 0 RESERVED RESERVED RESERVED RESERVED ROUTER_EG_VLAN_MODE3 Router egress VLAN mode of port 3 RESERVED ROUTER_EG_VLAN_MODE2 Router egress VLAN mode of port 2 RESERVED RESERVED 80-Y0619-1 Rev. A 241 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-258 Router egress VLAN mode bit description (cont.) Bits R/W Initial value Mnemonic Description 5.9 3:2 RO 0 RESERVED 1:0 R/W 0 ROUTER_EG_VLAN_MODE0 Router egress VLAN mode of port 0 l 00 = Egress transmits frames unmodified 01 = Egress transmits frames without VLAN ia 10 = Egress transmits frames with VLAN t 11 = Untouched en PHY control registers id Table 5-259 summarizes the PHY control registers. nf Table 5-259 PHY control register summary o Offset (Hex) 0 Control register C 1 Status register s 2 PHY identifier Description o 3 PHY identifier 2 r 4 Auto-negotiation advertisement register e 5 Link partner ability register 6 Auto-negotiation expansion register th 7 Next page transmit register A 8 Link partner next page register 9 A m 1000BASE-T control register 1000BASE-T status register B Reserved C Reserved m D Reserved oE Reserved lcF Extended status register 10 PHY-specific control register a 11 PHY-specific status register u 12 Interrupt enable register Q 13 Interrupt status register 14 Extended PHY-specific register 15 Receive error counter register 16 Virtual cable tester control register 80-Y0619-1 Rev. A 242 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-259 PHY control register summary (cont.) Offset (Hex) Description 17 Reserved 18 Reserved l 19 Reserved ia 1A Reserved t 1B Reserved 1D Debug port 1 (address offset) n 1E Debug port 2 (data port) e 1F Reserved id Table 5-260 summarizes the registers in MMD3 (MDIO manageable device address 3 for PCS). nf Table 5-260 PHY control register summary — MMD3 o Offset (Hex) C 0 1 s E o 16 PCS control register PCS status register EEE capability EEE wake error counter Description er Table 5-261 summarizes the registers in MMD7 (MDIO manageable device address 7 for PCS). th Table 5-261 PHY control register summary — MMD7 A Offset Description 0 1 mAN control AN status 5 AN package register 2 AN XNP transmit m17 AN XNP transmit1 o18 AN XNP transmit2 lc 19 ANXNP ability 1A ANXNP ability1 a 1B ANXNP ability2 u 3C EEE advertisement Q 3D EEE LP advertisement 8000 EEE ability auto-negotiation result 80-Y0619-1 Rev. A 243 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.9.1 Control register Address offset: 0x00 Table 5-262 summarizes the control registers. l Table 5-262 Control register bit description ia Bits Symbol t 15 RESET iden 14 LOOPBACK onf 13 SPEED SELECTION os C 12 AUTO-NEGOTIATION Ather 11 POWER DOWN Type Mode R/W HW Rst 0 SW Rst SC Mode R/W HW Rst 0 SW Rst 0 Mode HW Rst SW Rst R/W 0 Retain Mode HW Rst SW Rst Mode HW Rst SW Rst R/W 1 Retain R/W 0 0 Description PHY Software Reset. Writing a 1 to this bit causes the PHY the reset operation is done, this bit is cleared to 0 automatically. The reset occurs immediately. 0 = Normal operation 1 = PHY reset When loopback is activated, the transmitter data presented on TXD is looped back to RXD internally. Link is broken when loopback is enabled. 0 = Disable loopback 1 = Enable loopback 11 = Reserved 10 = 1000 Mb/s 01 = 100 Mb/s 00 = 10 Mb/s 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process When the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (bit[15]) and restart auto-negotiation (bit[9]) are not set by the user. m 10 ISOLATE om 9 RESTART AUTOlcNEGOTIATION Qua 8 DUPLEX MODE 0 = Normal operation 1 = Power down Mode R/W The GMII/MII output pins are tristated when this bit is HW Rst 0 set to 1. The GMII/MII inputs are ignored. 0 = Normal operation SW Rst 0 1 = Isolate Mode HW Rst SW Rst R/W, SC 0 SC Auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (bit[9]) is set. 0 = Normal operation 1 = Restart auto-negotiation process Mode R/W, SC 0 = Half-duplex HW Rst 1 1 = Full-duplex SW Rst Retain 80-Y0619-1 Rev. A 244 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-262 Control register bit description (cont.) Bits Symbol Type Description 7 COLLISION TEST ial 6 SPEED SELECTION (MSB) ident 5:0 RESERVED Mode R/W Setting this bit to 1 causes the COL pin to assert HW Rst 0 whenever the TX_EN pin is asserted. 0 = Disable COL signal test SW Rst 0 1 = Enable COL signal test Mode R/W See bit[13] HW Rst See Desc. SW Rst Mode RO Always be 00000. HW Rst 000000 SW Rst 00000 nf 5.9.2 Status Register o Address offset: 0x01, or 0d01 C Table 5-263 summarizes the status registers. s Table 5-263 Status registers bit description ro Bits Symbol the 15 100BASE-T4 Type Description Mode RO 100BASE-T4 HW Rst Always 0 This protocol is not available. SW Rst Always 0 0 = PHY not able to perform 100BASE-T4 A 14 100BASE-X FULL Mode RO Capable of 100BASE-Tx full-duplex operation m 13 100BASE-X HALF om 12 10 MBPS FULL-DUPLEX Qualc11 10 MBPS HALF-DUPLEX HW Rst Always 1 SW Rst Always 1 Mode RO Capable of 100BASE-Tx half-duplex operation HW Rst Always 1 SW Rst Always 1 Mode RO Capable of 10BASE-Te full duplex operation HW Rst Always 1 SW Rst Always 1 Mode RO Capable of 10 Mbps half duplex operation HW Rst Always 1 SW Rst Always 1 10 100BASE-T2 FULLDUPLEX Mode RO Not able to perform 100BASE-T2 HW Rst Always 0 SW Rst Always 0 80-Y0619-1 Rev. A 245 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-263 Status registers bit description (cont.) Bits Symbol Type Description 9 8 7 6 5 4 3 2 100BASE-T2 HALFDUPLEX EXTENDED STATUS RESERVED MF PREAMBLE SUPPRESSION AUTO-NEGOTIATION COMPLETE REMOTE FAULT AUTO-NEGOTIATION ABILITY LINK STATUS Mode RO Not able to perform 100BASE-T2 HW Rst Always 0 l SW Rst Always 0 ia Mode RO Extended status information in the extended status t HW Rst Always 0 register SW Rst Always 0 n Mode RO Always be 0. e HW Rst Always 0 id SW Rst Always 0 f Mode RO PHY accepts management frames with preamble n HW Rst Always 1 suppressed SW Rst Always 1 o Mode RO 0 = Auto-negotiation process incomplete C HW Rst 0 1 = Auto-negotiation process complete SW Rst 0 s Mode RO, LH 0 = Remote fault condition not detected o HW Rst 0 1 = Remote fault condition detected r SW Rst 0 e Mode RO 1 = PHY able to perform auto-negotiation hHW Rst Always 1 tSW Rst Always 1 AMode RO, LL This register bit indicates whether the link was lost m m 1 JABBER DETECT Qualco0 EXTENDED CAPABILITY HW Rst 0 since the last read. For the current link status, read bit[10] of PHY-specific status register. SW Rst 0 0 = Link is down 1 = Link is up Mode RO, LH 0 = Jabber condition not detected HW Rst 0 1 = Jabber condition detected SW Rst 0 Mode RO 1 = Extended register capabilities HW Rst Always 1 SW Rst Always 1 5.9.3 PHY identifier Address offset: 0x02 or 0d02 80-Y0619-1 Rev. A 246 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-264 summarizes the PHY identifier. Table 5-264 PHY Identifier bit description Bits Symbol Type Description l 15:0 ONI[18:3] Mode RO Organizationally unique identifier bits[18:3] ia HW Rst Always 16’h004d t SW Rst Always 16’h004d en 5.9.4 PHY Identifier 2 id Address offset: 0x3 f Table 5-265 summarizes the PHY identifiers 2. on Table 5-265 PHY Identifier 2 bit description Bits Symbol C 15:10 ONI[24:19] ros 9:4 MODEL NUMBER e 3:0 REVISION NUMBER Type Description Mode RO Organizationally unique identifier HW Rst Always 16’hd035 bits[24:19] SW Rst Always 16’hd035 Mode RO Model Number Mode RO Revision Number Ath 5.9.5 Auto-negotiation advertisement register m Address offset: 0x04, or 0d04 Table 5-266 summarizes the auto-negotiation advertisement register. Qualcom 80-Y0619-1 Rev. A 247 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-266 Auto-negotiation advertisement register bit description Bits Symbol Type Description 15 14 13 12 11 ial NEXT PAGE Mode HW Rst SW Rst nfident ACK Co REMOTE FAULT ros RESERVED the ASYMMETRIC m A PAUSE Mode HW Rst SW Rst Mode HW Rst SW Rst Mode HW Rst SW Rst Mode HW Rst SW Rst R/W 0 Update RO Always 0 Always 0 R/W Always 0 Always 0 RO Always 0 Always 0 R/W 1 Update The value of this bit is updated immediately after writing this register, but the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down If 1000BASE-T is advertised then the required next pages are automatically transmitted. Register is set to 0 if no additional next pages are needed. 0 = Not advertised 1 = Advertise Must be 0 0 = Do not set remote fault bit 1 = Set remote fault bit Always 0 The value of this bit is updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control Qualcom register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = No asymmetric pause 1 = Asymmetric pause Note: This bit has added the pad control and can be set from the F001 top. Its default value is one. 80-Y0619-1 Rev. A 248 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-266 Auto-negotiation advertisement register bit description (cont.) Bits Symbol Type Description 10 PAUSE 9 100BASE-T4 8 100BASE -TX 7 100BASE-TX Mode HW Rst l SW Rst fidentia Mode n HW Rst o SW Rst C Mode HW Rst s SW Rst Athero Mode R/W 1 Update RO Always 0 Always 0 R/W 1 Update R/W The value of this bit is updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = MAC PAUSE not implemented 1 = MAC PAUSE implemented Note: This bit has added the pad control and can be set from the F001 top, its default value is one. Not able to perform 100BASE-T4 The value of this bit is updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertise The value of this bit is updated immediately after writing m HALF DUPLEX HW Rst SW Rst Qualcom 1 Update this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertise 80-Y0619-1 Rev. A 249 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-266 Auto-negotiation advertisement register bit description (cont.) Bits Symbol Type Description 5.9.6 6 10BASE-TE FULL DUPLEX idential 5 10BASE-TE f HALF DUPLEX ros Con 4:0 SELECTOR e FIELD Mode HW Rst SW Rst R/W 1 Update The value of this bit is updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertise Mode HW Rst SW Rst R/W 1 Update The value of this bit is updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertise Mode RO Selector field mode HW Rst Always 00001 00001 = 802.3 SW Rst Always 00001 Ath Link partner ability register m Address offset: 0x05, or 0d05 Table 5-267 summarizes the link partner ability register. m Table 5-267 Link partner ability bit description o Bits Symbol alc15 NEXT PAGE Type Mode RO HW Rst 0 SW Rst 0 Description Received code word bit[15] 0 = Link partner not capable of next page 1 = Link partner capable of next page Qu 14 ACK Mode RO Acknowledge HW Rst 0 Received code word bit[14] SW Rst 0 0 = Link partner does not have next page ability 1 = Link partner received link code word 80-Y0619-1 Rev. A 250 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-267 Link partner ability bit description (cont.) Bits Symbol Type Description 13 REMOTE FAULT 12 RESERVED 11 ASYMMETRIC PAUSE 10 PAUSE 9 100BASE-T4 8 100BASE-TX FULL DUPLEX 7 100BASE-TX HALF DUPLEX Mode RO Remote fault HW Rst 0 Received code word bit[13] l SW Rst 0 0 = Link partner has not detected remote fault 1 = Link partner detected remote fault ia Mode RO Technology ability field t HW Rst 0 Received code word bit[12] n SW Rst 0 e Mode RO Technology ability field HW Rst 0 Received code word bit[11] fid SW Rst 0 0 = Link partner does not request asymmetric pause 1 = Link partner requests asymmetric pause Mode RO Technology ability field n HW Rst 0 Received code word bit[0] o SW Rst 0 0 = Link partner is not capable of pause operation 1 = Link partner is capable of pause operation C Mode RO Technology ability field HW Rst 0 Received code word bit[9] os SW Rst 0 0 = Link partner is not 100BASE-T4 capable 1 = Link partner is 100BASE-T4 capable r Mode RO Technology ability field e HW Rst 0 Received code word bit[8] h SW Rst 0 0 = Link partner is not 100BASE-Tx full-duplex capable 1 = Link partner is 100BASE-Tx full-duplex capable t Mode RO Technology ability field AHW Rst 0 Received code word bit[7] m 6 10BASE-TE FULL DUPLEX om 5 10BASE-TE lcHALF DUPLEX ua4:0 SELECTOR Q FIELD SW Rst 0 0 = Link partner is not 100BAse-TX half-duplex capable 1 = Link partner is 100BASE-Tx half-duplex capable Mode RO Technology ability field HW Rst 0 Received code word bit[6] SW Rst 0 0 = Link partner is not 10BASE-Te full-duplex capable 1 = Link partner is 10BASE-Te full-duplex capable Mode RO Technology ability field HW Rst 0 Received code word bit[5] SW Rst 0 0 = Link partner is not 10BASE-Te half-duplex capable 1 = Link partner is 10BASE-Te half-duplex capable Mode RO Selector field HW Rst 00000 Received code word bits[4:0] SW Rst 00000 80-Y0619-1 Rev. A 251 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.9.7 Auto-negotiation expansion register Address offset: 0x06, or 0d06 Table 5-268 summarizes the auto-negotiation expansion register. l Table 5-268 Auto-negotiation expansion bit description ia Bits Symbol t 15:5 RESERVED iden 4 PARALLEL DETECTION f FAULT Type Description Mode RO Reserved. Must be 0 HW Rst Always 0x000 SW Rst Always 0x000 Mode HW Rst RO, LH 0 0 = No fault has been detected 1 = A fault has been detect SW Rst 0 on 3 LINK PARTNER NEXT PAGE ABLE Mode HW Rst C SW Rst 2 LOCAL NEXT PAGE ABLE Mode s HW Rst o SW Rst r 1 PAGE RECEIVED Mode e HW Rst hSW Rst t 0 LINK PARTNER AUTOA NEGOTIATION ABLE Mode HW Rst m SW Rst RO 0 0 R/W 1 1 RO, LH 0 0 RO 0 0 0 = Link partner is not next page able 1 = Link partner is Next page able 1 = Local device is next page able 0 = No new page has been received 1 = A new page has been received 0 = Link partner is not auto-negotiation enable 1 = Link partner is auto-negotiation enable 5.9.8 Next page transmit register om Address offset: 0x07, or 0d07 lcTable 5-269 summarizes the next page transmit register. aTable 5-269 Next page transmit register bit description u Bits Symbol Q 15 NEXT PAGE Type Description Mode R/W Transmit code word bit[15] HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 252 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-269 Next page transmit register bit description (cont.) Bits Symbol Type Description 14 RESERVED Mode R/W Transmit code word bit[14] HW Rst 0 l SW Rst 0 ia 13 MESSAGE PAGE MODE Mode R/W Transmit code word bit[13] t HW Rst 0 SW Rst 0 n 12 ACK Mode R/W Transmit code word bit[12] e HW Rst 0 id SW Rst 0 f 11 TOGGLE Mode RO Transmit code word bit[11] n HW Rst 0 SW Rst 0 o 10:0 MESSAGE/UNFORMATTE Mode R/W Transmit code word bits[10:0] C D FIELD HW Rst 0x001 SW Rst 0x001 ros 5.9.9 Link partner next page register e Address offset: 0x08, or 0d08 Ath Table 5-270 summarizes the link partner next page register. Table 5-270 link partner next page bit description Bits Symbol m 15 NEXT PAGE om 14 RESERVED Qualc13 MESSAGE PAGE MODE Type Mode RO HW Rst 0 SW Rst 0 Mode RO HW Rst 0 SW Rst 0 Mode RO HW Rst 0 SW Rst 0 Description Transmit code word bit[15] Transmit code word bit[14] Transmit code word bit[13] 12 ACK2 Mode RO Transmit code word bit[12] HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 253 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-270 link partner next page bit description (cont.) Bits Symbol Type Description 11 TOGGLE Mode RO Transmit code word bit[11] HW Rst 0 l SW Rst 0 ia 10:0 MESSAGE/UNFORMATTE Mode R/W Transmit code word bits[10:0] t D FIELD HW Rst 0x000 SW Rst 0x000 iden 5.9.10 1000BASE-T control register f Address offset: 0x09, or 0d09 n Table 5-271 summarizes the 1000BASE-T control register. o Table 5-271 1000BASE-T control bit description C Bits Symbol Atheros 15:13 TEST MODE Type Description Mode R/W TX_TCLK comes from the RX_CLK pin for jitter testing in HW Rst 000 test modes 2 and 3. After exiting the test mode, hardware reset or software reset (control register bit[15]) is issued to SW Rst Retain ensure normal operation. 000 = Normal mode 001 = Test mode 1 — Transmit waveform test 010 = Test mode 2 — Transmit jitter test (master mode) 011 = Test mode 3 —Transmit jitter test (slave mode) 100 = Test mode 4 — Transmit distortion test 101, 110, 111 = Reserved 12 MASTER/SLAVE MANUAL m CONFIGURATION Qualcom ENABLE Mode R/W The value of this bit is updated immediately after writing HW Rst 0 this register, but the value written to this bit does not takes effect until any one of the following occurs: SW Rst Update  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Automatic master/slave configuration 1 = Manual master/slave configuration 80-Y0619-1 Rev. A 254 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-271 1000BASE-T control bit description (cont.) Bits Symbol Type Description 11 MASTER/SLAVE CONFIGURATION 10 PORT TYPE 9 1000BASE-T FULL DUPLEX m om 8 1000BASE-T HALFQualcDUPLEX Mode R/W The value of this bit is updated immediately after writing HW Rst 0 this register, but the value written to this bit does not takes effect until any one of the following occurs: l SW Rst Update  Software reset is asserted (control register bit[15]) ia  Restart auto-negotiation is asserted (control register bit[9]) t  Power down (control register bit[11]) transitions from power down to normal operation n  Link goes down e Bit[11] is ignored if bit[12] is equal to 0. 0 = Manual configure as slave id 1 = Manual configure as master f Mode R/W The value of this bit is updated immediately after writing n HW Rst 0 this register, but the value written to this bit does not takes effect until any one of the following occurs: SW Rst Update  Software reset is asserted (control register bit[15]) o  Restart auto-negotiation is asserted (control register bit[9]) C  Power down (control register bit[11]) transitions from power down to normal operation s  Link goes down Bit[10] is ignored if bit[12] is equal to 1. o0 = Prefer single port device (slave) r1 = Prefer multi-port device (master) e Mode R/W The value of this bit is updated immediately after writing th HW Rst 1 this register, but the value written to this bit does not takes effect until any one of the following occurs: SW Rst Update  Software reset is asserted (control register bit[15]) A  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertised Mode R/W The value of this bit is updated immediately after writing HW Rst 0 this register, but the value written to this bit does not takes effect until any one of the following occurs: SW Rst Update  Software reset is asserted (control register bit[15])  Restart auto-negotiation is asserted (control register bit[9])  Power down (control register bit[11]) transitions from power down to normal operation  Link goes down 0 = Not advertised 1 = Advertised Note: The default setting is no 1000 base/half duplex advertised. 80-Y0619-1 Rev. A 255 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-271 1000BASE-T control bit description (cont.) Bits Symbol Type Description l 7:0 RESERVED Mode R/W HW Rst 0 SW Rst 0 tia 5.9.11 1000BASE-T status register n Address offset: 0x0A, or 0d10 e Table 5-272 summarizes the 1000BASE-T status register. fid Table 5-272 1000BASE-T status bit description n Bits Symbol o 15 MASTER/SLAVE CONFIGURATION FAULT s C 14 MASTER/SLAVE CONFIGURATION o RESOLUTION Ather 13 LOCAL RECEIVER STATUS Type Description Mode HW Rst SW Rst RO, LH 0 0 This register bit is cleared on read 0 = No fault detected 1 = Master/slave configuration fault detected Mode RO This register bit is not valid until bit[1] of the HW Rst 0 auto-negotiation expansion register is 1. 0 = Local PHY configuration resolved to slave SW Rst 0 1 = Local PHY configuration resolved to master Mode RO 0 = Local receiver is not ok HW Rst 0 1 = Local receiver is ok SW Rst 0 12 REMOTE RECEIVER STATUS Mode RO 0 = Remote receiver is not ok m 11 LINK PARTNER 1000BASE-T m FULL DUPLEX CAPABILITY lco10 LINK PARTNER 1000BASE-T Qua HALF DUPLEX CAPABILITY HW Rst SW Rst Mode HW Rst SW Rst Mode HW Rst SW Rst 0 0 RO 0 0 RO 0 0 1 = Remote receiver is ok This register bit is not valid until bit[0] of the auto-negotiation expansion register is 1. 0 = Link Partner is not capable of 1000BASET half duplex 1 = Link Partner is capable of 1000BASE-T half duplex This register bit is not valid until bit[0] of the auto-negotiation expansion register is 1. 0 = Link Partner is not capable of 1000BASET full duplex 1 = Link Partner is capable of 1000BASE-T full duplex 9:8 RESERVED Mode RO HW Rst Always 0 SW Rst Always 0 80-Y0619-1 Rev. A 256 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-272 1000BASE-T status bit description (cont.) Bits Symbol Type Description l 7:0 IDLE ERROR COUNT Mode HW Rst SW Rst RO, SC 0 0 MSB of idle error counter These register bits report the idle error count since the last time this register was read. The counter pegs at 11111111 and does not roll over. tia 5.9.12 MMD access control register en Address offset: 0x0D, or 0d13 id Table 5-273 summarizes the MMD access control register. f Table 5-273 MMD access control bit description n Bits Symbol Type Description s Co 15:14 FUNCTION Mode R/W 00 = Address HW Rst. 00 01 = Data, no post increment SW Rst. Retain 10 = Data, post increment on reads and writes 11 = Data, post increment on writes only 13:5 RESERVED Mode RO ro HW Rst. 0 Athe 4:0 DEVAD SW Rst. 0 Mode R/W Device address HW Rst. 0 SW Rst. Update m 5.9.13 MMD access address data register Address offset: 0x0E, or 0d14 m Table 5-274 summarizes the MMD access address data register. lco Table 5-274 MMD access address data register bit description Bits Symbol a15:0 ADDRESS Qu DATA Type Description Mode R/W If bits[15:14] of the MMD access control register is 00, MMD HW Rst. 00 DEVAD's address register. Otherwise, MMD DEVAD's data register as indicated by the contents of its address register. SW Rst. Retain 80-Y0619-1 Rev. A 257 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.9.14 Extended status register Address offset: 0x0F, or 0d15 Table 5-275 summarizes the extended status register. l Table 5-275 Extended status register bit description ia Bits Symbol Type Description t 15 1000BASE-X Mode RO PHY not able to perform 1000BASE-X full duplex n FULL e DUPLEX HW Rst Always 0 SW Rst Always 0 id 14 1000BASE-X Mode RO PHY not able to perform 1000BASE-X half duplex HALF f DUPLEX HW Rst Always 0 SW Rst Always 0 n 13 1000BASE-T Mode RO PHY able to perform 1000BASE-T full duplex o FULLC DUPLEX HW Rst Always 1 SW Rst Always 1 12 1000BASE-T Mode RO PHY not able to perform 1000BASE-T half duplex s HALFo DUPLEX HW Rst Always 0 SW Rst Always 0 r 11:0 RESERVED Mode RO e HW Rst Always 0 h SW Rst Always 0 At 5.9.15 Function control register m Address offset: 0x10, or 0d16 Table 5-276 summarizes the function control register. om Table 5-276 Function control register bit description lcBits Symbol 15:12 RESERVED ua 11 ASSERT CRS ON Q TRANSMIT Type Mode RO HW Rst 0 SW Rst 0 Mode R/W HW Rst 0 Always 0 Description This bit has effect only in 10BASE-Te half-duplex mode: 0 = Assert on receiving. Do not assert on transmitting SW Rst Retain 1 = Assert on transmitting or receiving 80-Y0619-1 Rev. A 258 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-276 Function control register bit description (cont.) Bits Symbol Type Description 10 9:8 6:5 4:3 2 1 0 RESERVED Mode RO Always 0 HW Rst 0 l SW Rst 0 ia RESERVED Mode RO Always 0 t HW Rst 0 SW Rst 0 n MDI CROSSOVER nfide MODE Mode R/W Changes to these bits are disruptive to the normal HW Rst 11 operation; therefore, any changes to these registers must be followed by a software reset to take effect. SW Rst Update 00 = Manual MDI configuration 01 = Manual MDIX configuration 10 = Reserved 11 = Enable automatic crossover for all modes o RESERVED Mode RO Always 0 HW Rst 0 C SW Rst 0 ros SQE TEST Mode R/W SQE test is automatically disabled in full-duplex mode. HW Rst 0 0 = SQE test disabled SW Rst Retain 1 = SQE test enabled the POLARITY REVERSAL Mode HW Rst SW Rst R/W 0 Retain If polarity is disabled, then the polarity is forced to be normal in 10BASE-Te. 0 = Polarity reversal enabled 1 = Polarity reversal disabled A DISABLE JABBER Mode R/W Jabber has effect only in 10BASE-Te half-duplex mode. m HW Rst 0 0 = Enable jabber function SW Rst Retain 1 = Disable jabber function m 5.9.16 PHY-specific status register o Address offset: 0x11, or 0d17 QualcTable 5-277 summarizes the PHY-specific status register. 80-Y0619-1 Rev. A 259 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-277 PHY-specific status register bit description Bits Symbol Type Description 15:14 SPEED ntial 13 DUPLEX fide 12 PAGE RECEIVED (REAL TIME) on 11 SPEED AND DUPLEX RESOLVED s C 10 LINK (REAL TIME) ero 9:7 RESERVED Ath 6 MDI CROSSOVER Mode RO These status bits are valid when auto-negotiation is HW Rst 00 completed or auto-negotiation is disabled. 11 = Reserved SW Rst Retain 10 = 1000 Mbps 01 = 100 Mbps 00 = 10 Mbps Mode RO This status bit is valid only when auto-negotiation is HW Rst 0 complete or disabled. 0 = Half-duplex SW Rst Retain 1 = Full-duplex Mode RO HW Rst 0 0 = Page not received 1 = Page received SW Rst Retain Mode RO HW Rst 0 SW Rst 0 When auto-negotiation is not enabled for force speed mode. 0 = Not resolved 1 = Resolved Mode RO 0 = Link down HW Rst 0 1 = Link up SW Rst 0 Mode RO Always 0 HW Rst 0 SW Rst 0 Mode RO This status bit is valid only when auto-negotiation is m STATUS 5 WIRESPEED m DOWNGRADE lco4 RESERVED ua 3 TRANSMIT PAUSE Q ENABLED HW Rst 0 completed or auto-negotiation is disabled. 0 = MDI SW Rst Retain 1 = MDIX Mode RO 0 = Not downgrade HW Rst 0 1 = Downgrade SW Rst 0 Mode RO Always 0 HW Rst 0 SW Rst 0 Mode RO This is a reflection of the MAC pause resolution. HW Rst 0 This bit is for information purposes and is not used by the device. SW Rst 0 This status bit is valid only when auto-negotiation is completed or auto-negotiation is disabled. 0 = Transmit pause disabled 1 = Transmit pause enabled 80-Y0619-1 Rev. A 260 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-277 PHY-specific status register bit description (cont.) Bits Symbol Type Description 2 RECEIVE PAUSE ENABLED ntial 1 POLARITY (REAL TIME) nfide 0 JABBER (REAL TIME) Mode RO This is a reflection of the MAC pause resolution. HW Rst 0 This bit is for information purposes and is not used by the device. SW Rst Retain This status bit is valid only when auto-negotiation is completed or auto-negotiation is disabled. 0 = Receive pause disabled 1 = Receive pause enabled Mode RO 0 = Normal HW Rst 0 1 = Reversed SW Rst 0 Mode RO 0 = No jabber HW Rst 0 1 = Jabber SW Rst Retain Co 5.9.17 Interrupt enable register Address offset: 0x12, or 0d18 s Table 5-278 summarizes the interrupt enable register. ero Table 5-278 Interrupt enable register bit description Bits Symbol th 15 AUTO-NEGOTIATION ERROR A INTERRUPT ENABLE Type Description Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable 14 SPEED CHANGED INTERRUPT m ENABLE m 13 DUPLEX CHANGED INTERRUPT oENABLE lc12 PAGE RECEIVED INTERRUPT a ENABLE Qu 11 LINK FAIL INTERRUPT SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain 80-Y0619-1 Rev. A 261 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-278 Interrupt enable register bit description (cont.) Bits Symbol Type Description 10 LINK SUCCESS INTERRUPT ial 9 FLD_INT_BIT1 nt 8 RESERVED fide 7 RESERVED on 6 FLD_INT_BIT0 s C 5 WIRESPEED-DOWNGRADE o INTERRUPT er 4:2 RESERVED Ath 1 RESERVED Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W HW Rst 0 SW Rst Retain Mode R/W HW Rst 0 SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain Mode R/W HW Rst 0 SW Rst Retain Mode R/W m HW Rst 0 SW Rst Retain m 0 JABBER INTERRUPT Mode R/W 0 = Interrupt disable HW Rst 0 1 = Interrupt enable SW Rst Retain lco 5.9.18 Interrupt status register aAddress offset: 0x13, or 0d19 Qu Table 5-279 summarizes the interrupt status register. 80-Y0619-1 Rev. A 262 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-279 Interrupt status register bit description Bits Symbol Type Description 15 14 13 12 11 10 9 ial AUTO-NEGOTIATION ERROR Mode RO, LH An error occurs if master/slave does not resolve, HW Rst 0 parallel detect fault, no common HCD, or link does not come up after negotiation is completed. SW Rst Retain 0 = No auto-negotiation error 1 = Auto-negotiation error nt SPEED CHANGED Mode RO, LH 0 = Speed not changed HW Rst 0 1 = Speed changed e SW Rst Retain id RESERVED Mode RO, LH HW Rst 0 f SW Rst Retain on PAGE RECEIVED Mode RO 0 = Page not received HW Rst 0 1 = Page received C SW Rst Retain s LINK FAIL INTERRUPT Mode RO 0 = Link down HW Rst 0 1 = No link down o SW Rst Retain r LINK SUCCESS INTERRUPT Mode RO, LH 0 = Link up eHW Rst 0 1 = No link up hSW Rst Retain At FLD_INT_BIT1 Mode RO, LH Fast link down interrupt 1 HW Rst 0 {fld_int_bit1,fld_int_bit0} m 8 RESERVED lcom 7 RESERVED Qua 6 FLD_INT_BIT0 SW Rst 0 00 = no fast link down 01 = 10BT fast link down occur 10 = 100BT fast link down occur 11 = 1000BT fast link down occur Mode RO, LH HW Rst 0 SW Rst Retain Mode RO, LH HW Rst 0 SW Rst Retain Mode RO, LH Fast link down interrupt 0 HW Rst 0 SW Rst Retain 80-Y0619-1 Rev. A 263 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-279 Interrupt status register bit description (cont.) Bits Symbol Type Description 5 WIRESPEED-DOWNGRADE INTERRUPT ial 4:2 RESERVED nt 1 RESERVED nfide 0 JABBER INTERRUPT Mode RO, LH 0 = No wirespeed-downgrade HW Rst 0 1 = Wirespeed-downgrade SW Rst Retain Mode RO, LH HW Rst 0 SW Rst Retain Mode RO, LH HW Rst 0 SW Rst Retain Mode RO, LH 0 = No jabber HW Rst 0 1 = Jabber SW Rst Retain Co 5.9.19 Smart speed register s Address offset: 0x14, or 0d20 o Table 5-280 summarizes the smart speed register. er Table 5-280 Smart speed register bit description th Bits A 15:11 Symbol RESERVED Type Mode RO Description Reserved. Must be 00000000. m 10 ANEG_NOW_QUAL om 9 REV_ANEG_QUAL Qualc8 GIGA_DIS_QUAL HW Rst 0 SW Rst 0 Mode HW Rst SW Rst R/W 0 Retain A rise of input pin ANEG_NOW sets this bit to 2, and cause PHY to restart auto-negotiation. Self-cleared. Mode R/W Make PHY to auto-negotiate in reversed HW Rst 0 mode. This bit takes its value from the input pin REV_ANEG upon following: SW Rst Update 1. HW reset (fall of RST_DSP_I); 2. PHY SW reset; 3. Rise of ANEG_NOW. Mode R/W Make PHY to disable Gigabit mode. This bit HW Rst 0 takes its value from the input pin GIGA_DIS upon following: SW Rst Update 1. Hardware reset (fall of RST_DSP_I); 2. PHY software reset; 3. Rise of ANEG_NOW. 80-Y0619-1 Rev. A 264 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-280 Smart speed register bit description (cont.) Bits Symbol Type Description 7 6 5 4:2 1 0 l CFG_PAD_EN Mode RO, LH The default value is zero; if this bit is set to HW Rst 0 one, then the auto-negotiation arbitration FSM bypasses the LINK_STATUS_CHECK SW Rst Retain state when the 10 base/100 base ready signal is asserted. ntia MR_LTDIS Mode R/W The default value is zero; if this bit is set to HW Rst 0 one, then the NLP receive link integrity test FSM stays at the NLP_TEST_PASS state. SW Rst Update fide SMARTSPEED_EN Mode R/W The default value is one; if this bit is set to HW Rst 1 one and cable inhibits completion of the training phase, then after a few failed SW Rst Update attempts, the DSP PHY automatically downgrades the highest ability to the next lower speed: from 1000 to 100 to 10. Con SMARTSPEED_RETRY_LIMIT Mode R/W The default value is three. If these bits are set HW Rst 011 to three, then the DSP PHY attempts five times before downgrading. The number of SW Rst Update attempts can be changed through setting these bits. BYPASS_SMARTSPEED_TIMER Mode R/W The default value is zero. If this bit is set to s HW Rst 0 one, the Smartspeed FSM bypasses the timer used for stability. o SW Rst Update r RESERVED Mode RO Reserved. Must be set to 0. eHW Rst 0 AthSW Rst 0 m 5.9.20 Receive error counter register Address offset: 0x15, or 0d21 Table 5-281 summarizes the status register. om Table 5-281 Status register bit description lcBits Symbol 15:0 RECEIVE ERROR Qua COUNT Type Description Mode RO Counter pegs at 0xFFFF and does not roll over. HW Rst 0x0000 (When RX_DV is valid, count RX_ER numbers) SW Rst Retain (In this version, only for 100BASE-Tx and 1000BASE-T) 5.9.21 Virtual cable tester control register Address offset: 0x16, or 0d22 80-Y0619-1 Rev. A 265 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-282 summarizes the virtual cable tester control register. Table 5-282 Virtual cable tester control register bit description Bits Symbol Type Description l 15 RUN CDT Mode RW When set, hardware automatically disables this bit ia HW Rst 0 when VCT is done. 0 = Disable VCT Test t SW Rst Retain 1 = Enable VCT Test n 14 BP_VCT_EN_PON Mode RW 0 = Enable VCT Test when power on e HW Rst 0 1 = Disable VCT Test when power on SW Rst Retain id 13 DISABLE INTER-PAIR Mode RW 0 = Enable inter-pair short check f SHORT CHECK HW Rst 0 1 = Disable inter-pair short check n SW Rst 0 o 12 RESERVED Mode RO Always 0 HW Rst 0 C SW Rst 0 s 11 CABLE DIAGNOSTICS Mode RO 0 = Complete STATUS HW Rst 0 1 = In progress ro SW Rst 0 10 CABLE LENGTH UNIT Mode RW This bit must be set to 1 for meter unit. e HW Rst 0 thSW Rst 0 A 9:0 MDI PAIR SELECT Mode RO Always 0 m HW Rst 0 SW Rst 0 m 5.9.22 Debug port o Address offset: 0x1D, or 0d29 lcTable 5-283 summarizes the debug port (address offset 0x1d, or 0d29). aTable 5-283 Debug port (address offset 0x1d, or 0d29) bit description u Bits Symbol Q 15:6 RESERVED Type Mode RO Description HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 266 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-283 Debug port (address offset 0x1d, or 0d29) bit description (cont.) Bits Symbol Type Description 5:0 ADDRESS l OFFSET Mode R/W The address index of the register is written or read. HW Rst 0 SW Rst 0 tia 5.9.23 Debug port 2 (R/W port) n Address offset: 0x1E, or 0d30 e Table 5-284 summarizes the debug port 2 — R/W port. fid Table 5-284 Debug port 2 (R/W port) bit description n Bits Symbol o 15:0 DEBUG DATA C PORT Type Description Mode R/W The data port of debug register. HW Rst 0 Before access this register, must set the address offset first. SW Rst 0 os 5.10 Debug register er 5.10.1 Analog test control th Address offset: 0x00, or 0d00 A Table 5-285 summarizes the debug register — analog test control. m Table 5-285 Analog test control bit description Bits Symbol Type Description m 15 SEL_CLK125M_DSP Mode R/W Control bit for RGMII interface Rx clock delay: o HW Rst 1 0 = RGMII Rx clock delay disable lc SW Rst 0 1 = RGMII Rx clock delay enable 14:12 RESERVED Mode R/W a HW Rst 0 u SW Rst Retain Q 11 RESERVED Mode R/W HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 267 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-285 Analog test control bit description (cont.) Bits Symbol Type Description 10 9 8 7:5 4 3:2 1 RESERVED Mode R/W HW Rst 0 l SW Rst Retain ia RESERVED Mode R/W t HW Rst 1 SW Rst Retain n RESERVED Mode R/W e HW Rst 0 id SW Rst Retain f RESERVED Mode R/W n HW Rst 1 SW Rst Retain o RESERVED Mode R/W C HW Rst 1’b1 SW Rst Retain s MANU_SWITCH_ON Mode R/W Control SWR 1000BT output voltage: o HW Rst 2’h3 00 = 2.0 V r SW Rst Retain 10 = 1.8 V 01 = 1.9 V e11 = 1.7 V h RESERVED Mode R/W AtHW Rst 1 SW Rst Retain m 0 RESERVED Mode R/W HW Rst 0 SW Rst Retain om 5.10.2 System mode control lcAddress offset: 0x03 QuaTable 5-286 summarizes the debug register — system mode control. 80-Y0619-1 Rev. A 268 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-286 System mode control bit description Bits Symbol Type Description 15 RESERVED Mode R/W l HW Rst 0 ia SW Rst 0 14 RESERVED Mode R/W t HW Rst 0 n SW Rst Retain e 13:9 RESERVED Mode R/W id HW Rst 1 f SW Rst 0 8 OUT_MDIO_SW Mode R/W Control the MDIO signal when POWER_DOWN mode is high. n HW Rst 1 0 = MDIO is valid, driven by inner state o SW Rst Retain 1 = MDIO is 1 C 7:4 RESERVED Mode R/W HW Rst 4’b1111 s SW Rst Retain o 3:0 RESERVED Mode R/W r HW Rst 4’b1111 e SW Rst Retain h 7:5 RESERVED Mode R/W t HW Rst 1 ASW Rst Retain m 4:3 RESERVED Mode HW Rst R/W 2’h1 2 RESERVED lcom 1 RESERVED Qua 0 RESERVED SW Rst Retain Mode R/W HW Rst 1’b0 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode R/W HW Rst 0 SW Rst Retain 80-Y0619-1 Rev. A 269 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.10.3 System control mode Address offset: 0x05, or 0d05 Table 5-287 summarizes the debug register — system control mode. l Table 5-287 System control mode bit description ia Bits Symbol t 15 RESERVED iden 14 RESERVED nf 13 RESERVED Co 12 RESERVED ros 11 RESERVED Athe 10 RESERVED Type Mode RO HW Rst 0 SW Rst 0 Mode RO HW Rst 0 SW Rst 0 Mode R/W HW Rst 1 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode R/W HW Rst 1 Description 9 m RESERVED SW Rst Retain Mode R/W HW Rst 0 m SW Rst Retain 8 GTXCLK_DELAY Mode R/W RGMII Tx clock delay control bit: o HW Rst 0 0 = RGMII Tx clock delay disable lc SW Rst Retain 1 = RGMII Tx clock delay enable a 7 RESERVED Mode R/W HW Rst 0 u SW Rst Retain Q 6 RESERVED Mode R/W HW Rst 0 SW Rst Retain 80-Y0619-1 Rev. A 270 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-287 System control mode bit description (cont.) Bits Symbol Type Description 5:4 RESERVED ial 3 RESERVED nt 2 RESERVED fide 1 100_CLASSA Con 0 RESERVED Mode R/W HW Rst 00 SW Rst Retain Mode R/W HW Rst 0 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode R/W This bit is 100BASE-Tx Class A and Class AB mode select bit. HW Rst 1 0 = 100BASE-Tx Class AB SW Rst Retain 1 = 100BASE-Tx Class A Mode R/W HW Rst 0 SW Rst Retain ros 5.10.4 HIB control and auto-negotiation test register e Address offset: 0x0B Ath Table 5-288 summarizes the HIB control and auto-negotiation test register. Table 5-288 HIB control and auto-negotiation test register bit description Bits Symbol m 15 PS_HIB_EN om 14 WAKE_MODE Qualc13 EN_ANY_CHANGE Type Description Mode R/W Power hibernation control bit HW Rst 1 0 = Hibernation disable SW Rst Retain 1 = Hibernation enable Mode R/W 0 = PHY wakes up only by energy detect HW Rst 0 1 = PHY wakes up by energy detect or wake-up pin SW Rst Retain Mode R/W 0 = Turn on/off analog end step by step HW Rst 1 1 = Turn on/off analog end at the same time SW Rst Retain 12 HIB_PULSE_SW Mode R/W 0 = PHY does not send NLP pulse but detects HW Rst 1 signal from cables at hibernation state 1 = PHY sends NLP pulse and detects signal SW Rst Retain from cables at hibernation state 80-Y0619-1 Rev. A 271 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-288 HIB control and auto-negotiation test register bit description (cont.) Bits Symbol Type Description ial 11 GATE_25M_EN_SW Mode R/W Always 1 HW Rst 1 0 = The 25 MHz clock of auto-negotiation is not controlled by hibernation SW Rst 1 1 = Shut down the 25 MHz clock of auto- negotiation at hibernation state ent 10 SEL_RST_80U Mode R/W Duration of the reset triggered by speed mode HW Rst 1 change 0 = 240 µs SW Rst Retain 1 = 80/120/160/240 µs (see bits[9:8] of this register) nfid 9:8 SEL_RST_TIMER Mode R/W Duration configuration for reset timer HW Rst 00 00 = 80 µs SW Rst Retain 01 = 120 µs 10 = 160 µs 11 = 240 µs o 7 RESERVED Mode RO Always 0 C HW Rst 0 SW Rst 0 s 6:5 GTX_DLY_VAL Mode R/W GTX clock delay select o HW Rst 10 r SW Rst Retain e 4 BYPASS_BREAK_LINK_TIMER Mode R/W 0 = Auto-negotiation state stays at TRANSMIT_ hHW Rst 0 DISABLE for about 1.2 second when autonegotiation is restarted t SW Rst Retain 1 = BREAL_LINK timer is bypassed when auto- A negotiation is restarted, thus auto-negotiation state stays at TRANSMIT_DISABLE for one cycle m 3 DBG_LINK_OK_100T m 2 DBG_LINK_OK_1000T lco1 DBG_LINK_RDY_100T Qua 0 DBG_EN_EN (40 ns) Mode R/W For link management use. The forced LINK_OK_ HW Rst 0 100BT SW Rst 0 Mode R/W For link management use. The forced LINK_OK_ HW Rst 0 1000BT SW Rst 0 Mode R/W For link management use. The forced LINK_ HW Rst 0 RDY_100BT SW Rst 0 Mode R/W For link management use. When this bit is set, HW Rst 0 the test bits in this register take effect. SW Rst 0 80-Y0619-1 Rev. A 272 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.10.5 RGMII mode selection Address offset: 0x012, or 0d18 Table 5-289 summarizes the debug register — RGMII mode selection. l Table 5-289 RGMII mode selection bit description ia Bits Symbol t 15:14 RESERVED iden 13:12 RESERVED nf 11 RESERVED Co 10 RESERVED ros 9:6 RESERVED Athe 5 RESERVED Type Mode R/W HW Rst 01 SW Rst Retain Mode R/W HW Rst 00 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain Mode RO HW Rst 0 SW Rst 0 Mode R/W HW Rst 0 Description 4 m RESERVED SW Rst 0 Mode R/W HW Rst 0 m SW Rst Retain 3 RGMII_MODE Mode R/W 0 = Select GMII/MII interface with MAC o HW Rst 0 1 = Select RGMII interface with MAC lc SW Rst Retain a 2 RESERVED Mode R/W HW Rst 1 u SW Rst 1 Q 1:0 RESERVED Mode R/W HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 273 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.10.6 Green feature configure register Address offset: 0x3D Table 5-290 summarizes the debug register — green feature configure register. l Table 5-290 Green feature configure register bit description ia Bits Symbol Type Description t 15 RESERVED Mode R/W n HW Rst 0 e SW Rst Retain id 14 RESERVED Mode RO f 13:8 RESERVED Mode R/W HW Rst 6’h28 n SW Rst Retain o 7 RESERVED Mode R/W C HW Rst 1 SW Rst Retain s 6 GATE_CLK_IN1000 Mode R/W 0 = When in 1000BASE-T mode, gate dig100/dig10/vct clk o HW Rst 1 1 = When in 1000BASE-T mode, do not gate dig100/dig10/vct clk r SW Rst Retain e 5:0 RESERVED Mode R/W h HW Rst 6’h20 AtSW Rst Retain m 5.11 MMD3 — PCS register m 5.11.1 PCS control1 o Address offset: 0x00 or 0d00 lcDevice address: 3 QuaTable 5-291 summarizes the PCS control 1 register. 80-Y0619-1 Rev. A 274 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-291 PCS control1 bit description Bits Symbol Type Description ial 15 PCS_RST Mode R/W Reset bit, self-cleared. HW Rst 0 When write this bit to 1, reset the registers (not vender specific) in MMD3/MMD7 and cause software reset in MII SW Rst 0 register0 bit[15]. 14:11 RESERVED Mode RO Always 0 t HW Rst 0 n SW Rst 0 e 10 CLOCK_STOPPABLE Mode R/W Not implemented id HW Rst 1 f SW Rst Retain 9:0 RESERVED Mode R/W Always 0 n HW Rst 1 o SW Rst Retain s C 5.11.2 PCS status1 o Address offset: 0x01 or 0d01 r Device address: 3 e Table 5-292 summarizes the PCS status 1register. Ath Table 5-292 PCS status1 bit description m Bits Symbol 15:12 RESERVED Type Mode R/W Always 0 Description m 11 TX LP IDLE oRECEIVED lc10 RX LP IDLE a RECEIVED Qu 9 TX LP IDLE HW Rst 0 SW Rst 0 Mode RO When read as 1, it indicates that the transmit PCS has HW Rst 0 received low power idle signaling one or more times since the register was last read. Latch high. SW Rst 0 Mode R/W When read as 1, it indicates that the receive PCS has HW Rst 0 received low power idle signaling one or more times since the register was last read. Latch high. SW Rst 0 Mode R/W When read as 1, it indicates that the transmit PCS is currently INDICATION HW Rst 0 receiving low power idle signals. SW Rst 0 80-Y0619-1 Rev. A 275 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-292 PCS status1 bit description (cont.) Bits Symbol Type Description 8 RX LP IDLE INDICATION tial 7:0 RESERVED Mode R/W When read as 1, it indicates that the receive PCS is currently HW Rst 0 receiving low power idle signals. SW Rst 0 Mode RO Always 0 HW Rst 0 SW Rst 0 iden 5.11.3 EEE capability register f Address offset: 0x014 or 0d020 n Device address: 3 o Table 5-293 summarizes the EEE capacity register. C Table 5-293 EEE capability register bit description s Bits Symbol Type Description o 15:3 RESERVED Mode RO Always 0 r HW Rst 0 e SW Rst 0 h 2 1000BT EEE Mode RO EEE is supported for 1000BASE-T. t HW Rst 1 A SW Rst 1 1 100BT EEE mMode HW Rst RO 1 EEE is supported for 100BASE-Tx. SW Rst 1 0 RESERVED Mode R/W Always 0 mHW Rst 0 o SW Rst 0 alc 5.11.4 EEE wake error counter u Address offset: 0x016 or 0d022 Q Device address: 3 Table 5-294 summarizes the EEE wake error register. 80-Y0619-1 Rev. A 276 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-294 EEE wake error counter bit description Bits Symbol Type Description 15:0 EEE WAKE ERROR ial COUNTER Mode RO Count wake time faults where the PHY fails to complete its HW Rst 0 normal wake sequence within the time required for the specific PHY type. SW Rst 0 This counter is clear after read, and hold at all ones in the case of overflow. nt 5.11.5 AZ control e Address offset: 0x8008 (Hex) id Device address: 3 f Table 5-295 summarizes the AZ control register. on Table 5-295 AZ control bit description C Bits Symbol 15:8 SHORT_AZ_ os THRESHOLD Type Description Mode R/W Used for short cable AZ control HW Rst 8'd16 This bit controls a threshold to stop the timing adjusting during the AZ wake up training SW Rst Retain r 7:0 LONG_AZ_ Athe THRESHOLD Mode R/W Used for long cable AZ control HW Rst 8'd29 This bit controls a threshold to stop the timing adjusting during the AZ wake up training SW Rst Retain m 5.11.6 AZ debug Address offset: 0x800D (Hex) Device address: 3 m Table 5-296 summarizes the AZ debug register. lco Table 5-296 AZ debug bit description Bits Symbol Qua 15 RESERVED Type Mode R/W HW Rst 0 SW Rst Retain Description 14 AZ_FULL_AMP_ WAKE Mode R/W 1 = In AZ_WAKE state, PHY sends out signal with the same HW Rst 0 amplitude as non-AZ link. 0 = In AZ_WAKE state, PHY sends out signal always with full SW Rst Retain amplitude. 80-Y0619-1 Rev. A 277 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-296 AZ debug bit description (cont.) Bits Symbol Type Description l 13:0 RESERVED Mode R/W HW Rst 0xb3f SW Rst Retain tia 5.11.7 PHY cable diagnostics code n Address offset: 0x8064 e Device address: 3 id Table 5-297 summarizes the PHY cable diagnostics code register. nf Table 5-297 PHY cable diagnostics bit description o Bits Symbol C 15:12 VCT_PAIR_A_ CODE heros 11:8 VCT_PAIR_B_ At CODE Type Description Mode RO Pair A cable diagnostics code HW Rst 0 0x0 = Invalid; cable diagnostics routine is not completed successfully; SW Rst 0 0x1 = Pair OK, no fault detected 0x2 = Pair open 0x3 = Intra pair short 0x4 = Inter pair short 0x9 = Pair busy Mode RO Pair B cable diagnostics code HW Rst 0 SW Rst 0 7:4 VCT_PAIR_C_ Mode RO Pair C cable diagnostics code CODE HW Rst 0 mSW Rst 0 m 3:0 VCT_PAIR_D_ Mode RO Pair D cable diagnostics code CODE HW Rst 0 o SW Rst 0 alc 5.11.8 PHY cable diagnostics pair A length Qu Address offset: 0x8065 Device address: 3 Table 5-298 summarizes the PHY cable diagnostics pair A length register. 80-Y0619-1 Rev. A 278 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-298 PHY cable diagnostics pair A length bit description Bits Symbol Type Description 15:0 PAIR_A_ ial LENGTH Mode RO Cable length for pair A HW Rst 0 If bit[10] of MII register 0x16 = 1, then cable length unit is meter; else, cable length unit is centimeter SW Rst 0 nt 5.11.9 PHY cable diagnostics pair B length e Address offset: 0x8066 id Device address: 3 f Table 5-299 summarizes the PHY cable diagnostics pair B length register. on Table 5-299 PHY cable diagnostics pair B length bit description Bits Symbol C 15:0 PAIR_B_ s LENGTH Type Description Mode RO Cable length for pair B HW Rst 0 If bit[10] 0f MII register 0x16 = 1, then cable length unit is meter; else, cable length unit is centimeter SW Rst 0 ero 5.11.10 PHY cable diagnostics pair C length th Address offset: 0x8067 A Device address: 3 m Table 5-300 summarizes the PHY cable diagnostics pair C length register. Table 5-300 PHY cable diagnostics pair C length bit description m Bits Symbol o 15:0 PAIR_C_ lcLENGTH Type Description Mode RO Cable length for pair C HW Rst 0 If bit[10] 0f MII register 0x16 = 1, then cable length unit is meter; else, cable length unit is centimeter SW Rst 0 ua5.11.11 PHY cable diagnostics pair D length Q Address offset: 0x8068 Device address: 3 Table 5-301 summarizes the PHY cable diagnostics pair D length register. 80-Y0619-1 Rev. A 279 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-301 PHY cable diagnostics pair D length bit description Bits Symbol Type Description 15:0 PAIR_D_ ial LENGTH Mode RO Cable length for pair D HW Rst 0 If bit[10] 0f MII register 0x16 = 1, then cable length unit is meter; else, cable length unit is centimeter SW Rst 0 nt 5.11.12 CLD16 e Address offset: 0x806E (Hex) id Device address: 3 f Table 5-295 summarizes the AZ control register. on Table 5-302 AZ control bit description Bits Symbol C 15 BP_AUTO_VCT eros 14:0 RESERVED Type Description Mode R/W 1 = Disable detecting cable length via sending pulses and HW Rst 1'b1 receiving reflections on channel 2/3. 0 = Enable detecting cable length via sending pulses and SW Rst Retain receiving reflections on channel 2/3. Mode R/W HW Rst 0x88b SW Rst Retain Ath 5.12 MMD7 — auto-negotiation register m 5.12.1 AN control m Address offset: 0x0 or 0d0 o Device address: 7 lcTable 5-303 summarizes the AN control 1 register. aTable 5-303 AN control 1 bit description u Bits Symbol Q 15 AN_RST Type Mode RO Reset bit, self-clear. Description HW Rst 0 When write this bit 1: SW Rst 0 1. Reset the registers (not vender-specific) in MMD3/MMD7. 2. Cause software reset in MII register0 bit[15]. 80-Y0619-1 Rev. A 280 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-303 AN control 1 bit description (cont.) Bits Symbol Type Description 14 RESERVED Mode RO Always 0 HW Rst 1 l SW Rst 1 ia 13 XNP_CTRL Mode RO If MII register 4 bit[12] is set to 0, setting of this bit shall have no effect. t HW Rst 1 0 = Local device does not intend to enable the exchange of extended next page. n SW Rst 1 1 = Local device intends to enable the exchange of extended next page. e 12:0 RESERVED Mode R/W Always 0 id HW Rst 0 f SW Rst 0 on 5.12.2 AN package C Address offset: 0x05 or 0d05 Device address: 7 s Table 5-304 summarizes the AN package. ro Table 5-304 AN package bit description e Bits Symbol Ath 15:8 RESERVED Type Mode RO Always 0 HW Rst 0 Description 7 m AUTO_NEG_PRESENT SW Rst Mode 0 RO Always 1 m 6:4 RESERVED lco3 PCS PRESENT Qua2:1 RESERVED HW Rst 1 SW Rst 1 Mode RO Always 0 HW Rst 0 SW Rst 0 Mode RO Always 1 HW Rst 1 SW Rst 1 Mode R/W Always 0 HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 281 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-304 AN package bit description (cont.) Bits Symbol Type Description l 0 MII_REG_PRESENT Mode R/W Always 1 HW Rst 1 SW Rst 1 tia 5.12.3 AN status n Address offset: 0x01 or 0d1 e Device address: 7 id Table 5-305 summarizes the AN status. nf Table 5-305 AN status bit description o Bits Symbol Type Description C 15:8 RESERVED Mode RO HW Rst 0 s SW Rst 0 o 7 XNP_STATUS Mode RO 0 = Extended next page shall not be used. r HW Rst 0 1 = Both local device and link partner have indicated support for extended next page. e SW Rst 0 h 6:0 RESERVED Mode RO t HW Rst 0 A SW Rst 0 m 5.12.4 AN XNP transmit Address offset: 0x016 or 0d22 m Device address: 7 o Table 5-306 summarizes the AN XNP transmit register. lc. aTable 5-306 AN XNP transmit bit description u Bits Symbol Type Description Q 15:0 XNP_22 Mode RO Bits[15:0] of extended next page transmits HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 282 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.12.5 AN XNP transmit1 Address offset: 0x017 or 0d23 Device address: 7 l Table 5-307 summarizes the AN XNP transmit 1 register. tia Table 5-307 AN XNP transmit1 bit description Bits Symbol Type Description n 15:0 XNP_23 Mode RO Bits[31:16] of extended next page transmits e HW Rst 0 id SW Rst 0 nf 5.12.6 AN XNP transmit 2 o Address offset: 0x018 or 0d24 C Device address: 7 s Table 5-308 summarizes the AN XNP transmit 2 register. ro Table 5-308 AN XNP transmit2 bit description e Bits Symbol Type Description h 15:0 XNP_23 Mode RO Bits[47:32] of extended next page transmits t HW Rst 0 A SW Rst 0 m 5.12.7 AN LP XNP ability Address offset: 0x019 or 0d25 m Device address: 7 lco Table 5-309 summarizes the AN LP XNP ability register. aTable 5-309 AN LP XNP ability bit description u Bits Symbol Type Description Q 15:0 LP_XNP_1 Mode RO Bits[15:0] of received extended next page from link partner HW Rst 15’h0 SW Rst 15’h0 80-Y0619-1 Rev. A 283 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description 5.12.8 AN LP XNP ability1 Address offset: 0x01A or 0d26 Device address: 7 l Table 5-310 summarizes the AN LP XNP ability 1 register. tia Table 5-310 AN LP XNP ability1 bit description Bits Symbol Type Description n 15:0 LP_XNP_2 Mode RO Latched when LP_XNP_1 is read e HW Rst 15’h0 Bits[31:16] of received extended next page from link partner id SW Rst 15’h0 nf 5.12.9 AN LP XNP ability2 o Address offset: 0x01B or 0d27 C Device address: 7 s Table 5-311 summarizes the AN LP XNP ability2 register. ro Table 5-311 AN LP XNP ability2 bit description e Bits Symbol Type Description h 15:0 LP_XNP_3 Mode RO Latched when LP_XNP_1 is read t HW Rst 15’h0 Bits[47:32] of received extended next page from link partner A SW Rst 15’h0 m 5.12.10 EEE advertisement Address offset: 0x3C (Hex) m Device address: 7 lco Table 5-312 summarizes the EEE advertisement register. aTable 5-312 EEE advertisement bit description u Bits Symbol Q 15:3 RESERVED Type Mode RO Always 0 Description HW Rst 0 SW Rst 0 80-Y0619-1 Rev. A 284 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-312 EEE advertisement bit description (cont.) Bits Symbol Type Description 2 EEE_1000BT Mode R/W If local device supports EEE operation for 1000BASE_T, and EEE HW Rst 1 operation is desired, this bit shall be set to 1. l SW Rst Retain ia 1 EEE_100BT Mode R/W If local device supports EEE operation for 100BASE-Tx, and EEE t HW Rst 1 operation is desired, this bit shall be set to 1. SW Rst Retain n 0 RESERVED Mode RO Always 0 e HW Rst 0 id SW Rst 0 nf 5.12.11 EEE LP advertisement o Address offset: 0x3D (Hex) C Device address: 7 s Table 5-313 summarizes the EEE LP advertisement register. ro Table 5-313 EEE LP advertisement bit description e Bits Symbol Ath 15:3 RESERVED Type Mode RO Always 0 HW Rst 0 SW Rst 0 Description 2 m EEE_1000BT Mode RO If local device supports EEE operation for 1000BASE-T, and EEE HW Rst 0 operation is desired, this bit shall be set to 1. SW Rst 0 1 EEE_100BT Mode RO If local device supports EEE operation for 100BASE-Tx, and EEE m HW Rst 0 operation is desired, this bit shall be set to 1. o SW Rst 0 lc0 RESERVED Mode RO Always 0 HW Rst 0 a SW Rst 0 Qu5.12.12 EEE ability auto-negotiation result Address offset: 0x8000 (Hex) Device address: 7 80-Y0619-1 Rev. A 285 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Register Description Table 5-314 summarizes the EEE ability auto-negotiation result register. Table 5-314 EEE ability auto-negotiation result bit description Bits Symbol Type Description l 15:3 RESERVED Mode RO Always 0 ia HW Rst 0 t SW Rst 0 2 EEE_1000BT_EN Mode RO 0 = 1000BASE-T az disable; either side does not support EEE en HW Rst 0 operation for 1000BT, or EEE operation is not desired. 1 = 1000BASE-T az enable; both sides support EEE operation for SW Rst 0 1000BT, and EEE operation is desired. id 1 EEE_100BT_EN Mode RO 0 = 100BASE-Tx az disable; either side does not support EEE f HW Rst 0 operation for 100BASE-Tx, or EEE operation is not desired. 1 = 100BASE-Tx az enable; both sides support EEE operation for n SW Rst 0 100BASE-Tx, and EEE operation is desired. 0 RESERVED Mode RO Always 0 o HW Rst 0 Atheros C SWRst 0 Qualcomm 80-Y0619-1 Rev. A 286 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 6 Package Dimensions Atheros Confidential m Qualcom Figure 6-1 88-pin QFN package drawing 80-Y0619-1 Rev. A 287 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION QCA8334 Four-port Gigabit Ethernet Switch Data Sheet Package Dimensions Table 6-1 Package dimensions (QFN) Symbol Min. Nom. Max. Unit A 0.80 0.85 0.90 mm l A1 0.00 0.02 0.05 mm ia A2 0.60 0.65 0.70 mm A3 0.20 REF mm t b 0.15 0.20 0.25 mm n D/E 10.00 BSC mm e D1/E1 9.75 BSC mm id D2/E2 5.85 6.00 6.15 mm f e 0.40 BSC mm L 0.30 0.40 0.50 mm n θ 0 – 14 ° o R 0.075 – – mm C K 0.20 – – mm aaa 0.10 mm s bbb 0.07 mm o ccc 0.10 mm r ddd 0.05 mm e eee 0.08 mm h fff 0.10 mm At Reference document: JEDEC MO-220 Qualcomm 80-Y0619-1 Rev. A 288 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 7 Ordering Information tial The order information is listed in Table 7-1. en Table 7-1 Ordering information id Ordering number Atheros Conf QCA8334-AL3C Package QFN 88-pin (10 mm x 10 mm) Ambient temperature Default ordering unit Commercial (0–70 °C ) Tray Qualcomm 80-Y0619-1 Rev. A 289 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 8 Top-Side Marking tial The top-side marking is listed in Figure 8-1. en Table 8-1 Top-side marking id Ordering number f QCA8334-AL3C Marking QCA8334-AL3C ros Con QCA8334-AL3C e h t A Figure 8-1 QCA8334 top-side marking m Qualcom 80-Y0619-1 Rev. A 290 Confidential and Proprietary – Qualcomm Atheros, Inc. MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

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