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Verilog HDL语言:指南数字设计与合成(第二版)

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  • 日期: 2013-09-22
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标签: Verilog

Verilog

HDL语言

HDL语言

指南数字设计与合成

HDL语言

第二版

第二版

Part1.BasicVerilogTopicsChapter1.OverviewofDigitalDesignwithVerilogHDLSection1.1.EvolutionofComputer-AidedDigitalDesignSection1.2.EmergenceofHDLsSection1.3.TypicalDesignFlowSection1.4.ImportanceofHDLsSection1.5.PopularityofVerilogHDLSection1.6.TrendsinHDLsChapter2.HierarchicalModelingConceptsSection2.1.DesignMethodologiesSection2.2.4-bitRippleCarryCounterSection2.3.ModulesSection2.4.InstancesSection2.5.ComponentsofaSimulationSection2.6.ExampleSection2.7.SummarySection2.8.ExercisesChapter3.BasicConceptsSection3.1.LexicalConventionsSection3.2.DataTypesSection3.3.SystemTasksandCompilerDirectivesSection3.4.SummarySection3.5.ExercisesChapter4.ModulesandPortsSection4.1.ModulesSection4.2.PortsSection4.3.HierarchicalNamesSection4.4.SummarySection4.5.ExercisesChapter5.Gate-LevelModelingSection5.1.GateTypesSection5.2.GateDelaysSection5.3.SummarySection5.4.ExercisesChapter6.DataflowModelingSection6.1.ContinuousAssignmentsSection6.2.DelaysSection6.3.Expressions,Operators,andOperandsSection6.4.OperatorTypesSection6.5.ExamplesSection6.6.SummarySection6.7.ExercisesChapter7.BehavioralModelingSection7.1.StructuredProceduresSection7.2.ProceduralAssignmentsSection7.3.TimingControlsSection7.4.ConditionalStatementsSection7.5.MultiwayBranchingSection7.6.LoopsSection7.7.SequentialandParallelBlocksSection7.8.GenerateBlocksSection7.9.ExamplesSection7.10.SummarySection7.11.ExercisesChapter8.TasksandFunctionsSection8.1.DifferencesbetweenTasksandFunctionsSection8.2.TasksSection8.3.FunctionsSection8.4.SummarySection8.5.ExercisesChapter9.UsefulModelingTechniquesSection9.1.ProceduralContinuousAssignmentsSection9.2.OverridingParametersSection9.3.ConditionalCompilationandExecutionSection9.4.TimeScalesSection9.5.UsefulSystemTasksSection9.6.SummarySection9.7.ExercisesPart2.AdvancedVerilogTopicsChapter10.TimingandDelaysSection10.1.TypesofDelayModelsSection10.2.PathDelayModelingSection10.3.TimingChecksSection10.4.DelayBack-AnnotationSection10.5.SummarySection10.6.ExercisesChapter11.Switch-LevelModelingSection11.1.Switch-ModelingElementsSection11.2.ExamplesSection11.3.SummarySection11.4.ExercisesChapter12.User-DefinedPrimitivesSection12.1.UDPbasicsSection12.2.CombinationalUDPsSection12.3.SequentialUDPsSection12.4.UDPTableShorthandSymbolsSection12.5.GuidelinesforUDPDesignSection12.6.SummarySection12.7.ExercisesChapter13.ProgrammingLanguageInterfaceSection13.1.UsesofPLISection13.2.LinkingandInvocationofPLITasksSection13.3.InternalDataRepresentationSection13.4.PLILibraryRoutinesSection13.5.SummarySection13.6.ExercisesChapter14.LogicSynthesiswithVerilogHDLSection14.1.WhatIsLogicSynthesis?Section14.2.ImpactofLogicSynthesisSection14.3.VerilogHDLSynthesisSection14.4.SynthesisDesignFlowSection14.5.VerificationofGate-LevelNetlistSection14.6.ModelingTipsforLogicSynthesisSection14.7.ExampleofSequentialCircuitSynthesisSection14.9.ExercisesChapter15.AdvancedVerificationTechniquesSection15.1.TraditionalVerificationFlowSection15.2.AssertionCheckingSection15.3.FormalVerificationSection15.4.SummaryPart3.AppendicesAppendixA.StrengthModelingandAdvancedNetDefinitionsSectionA.1.StrengthLevelsSectionA.2.SignalContentionSectionA.3.AdvancedNetTypesAppendixB.ListofPLIRoutinesSectionB.1.ConventionsSectionB.2.AccessRoutinesSectionB.3.Utility(tf_)RoutinesAppendixC.ListofKeywords,SystemTasks,andCompilerDirectivesSectionC.1.KeywordsSectionC.2.SystemTasksandFunctionsSectionC.3.CompilerDirectivesAppendixD.FormalSyntaxDefinitionSectionD.1.SourceText Section D.2.  Declarations Section D.3.  Primitive Instances Section D.4.  Module and Generated Instantiation Section D.5.  UDP Declaration and Instantiation Section D.6.  Behavioral Statements Section D.7.  Specify Section Section D.8.  Expressions Section D.9.  General Endnotes  Appendix E.  Verilog Tidbits Origins of Verilog HDL Interpreted, Compiled, Native Compiled Simulators Event-Driven Simulation, Oblivious Simulation Cycle-Based Simulation Fault Simulation General Verilog Web sites Architectural Modeling Tools High-Level Verification Languages Simulation Tools Hardware Acceleration Tools In-Circuit Emulation Tools Coverage Tools Assertion Checking Tools Equivalence Checking Tools Formal Verification Tools Appendix F.  Verilog Examples Section F.1.  Synthesizable FIFO Model Section F.2.  Behavioral DRAM Model Bibliography Manuals Books Quick Reference Guides About the CD-ROM Using the CD-ROM Technical Support

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