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DRV8833 www.ti.com.cn ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 双通道 H 桥电机驱动器 查询样品: DRV8833 特性 1 •2 双通道 H 桥电流控制电机驱动器 – 能够驱动两个直流(DC) 电机或一个步进电机 – 低 MOSFET 导通电阻 HS + LS 360 mΩ • 每个 H 桥的输出电流为 1.5-A RMS、2APP (在 VM = 5V 和 25℃ 条件下) • 产品可以为 3-A RMS, 4-A 平行峰顶 • 宽电源电压范围: 2.7V 至 10.8V • PWM 绕组电流调节/限制 • 耐热性能增强型表面贴装式封装 应用 • 电池供电式玩具 • POS 打印机 • 视频安保摄像机 • 办公自动化设备 • 游戏机 • 机器人 说明 DRV8833 为玩具、打印机及其他机电一体化应用提供了一款双通道桥式电机驱动器解决方案。 该器件具有两个 H 桥驱动器,并能够驱动两个直流 (DC) 电刷电机、一个双极性步进电机、螺线管或其他电感性负 载。 每个 H 桥的输出驱动器模块由 N 沟道功率 MOSFET 组成,这些 MOSFET 被配置成一个H桥,以驱动电机绕组。 每个 H 桥都包括用于调节或限制绕组电流的电路。 借助正确的 PCB 设计,DRV8833 的每个H桥能够连续提供高达 1.5-A RMS (或 DC) 的驱动电流(在 25℃ 和采 用一个 5V VM 电源时)。每个 H 桥可支持高达 2A 的峰值电流。 在较低的 VM 电压条件下,电流供应能力略有下 降。 该器件提供了利用一个故障输出引脚实现的内部关断功能,用于:过流保护、短路保护、欠压闭锁和过热。 另外, 还提供了一种低功耗睡眠模式。 DRV8833 内置于16 引脚HTSSOP 封装或采用 PowerPAD™ 的QFN 封装(绿色环保: RoHS 和无Sb / Br)。 封装 (2) PowerPAD™ (HTSSOP) - PWP PowerPAD™ (QFN) - RTY 订购信息 (1) 可订购部件 号 2000 卷带式包装 DRV8833PWPR Tube of 90 DRV8833PWP 3000 卷带 DRV8833RTYR 卷盘 ( 250 片 ) DRV8833RTYT (1) 如需了解最新的封装及订购信息,敬请查看本文档末的 “封装选项附录”,或查看 TI 网站 www.ti.com.cn。 (2) 封装图样、散热数据和符号可登录 www.ti.com/packaging 获取。 正面 标记 DRV8833 DRV8833 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated English Data Sheet: SLVSAR1 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 DEVICE INFORMATION Functional Block Diagram www.ti.com.cn VM VM 10uF Internal Ref & Regs Charge Pump VM 2.2uF VINT VM VCP 0.01uF AOUT1 Drives 2x DC motor or 1x Stepper AIN1 AIN2 BIN1 BIN2 nSLEEP Gate Drive & VM OCP Logic ISEN VM nFAULT OverTemp Gate Drive & VM OCP ISEN AOUT2 AISEN BOUT1 BOUT2 BISEN DCM Step Motor DCM GND 2 Copyright © 2011, Texas Instruments Incorporated DRV8833 www.ti.com.cn ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 Table 1. TERMINAL FUNCTIONS NAME PIN (PWP) POWER AND GROUND GND 13 PPAD PIN (RTY) 11 PPAD VM 12 10 VINT 14 12 VCP 11 9 CONTROL AIN1 16 14 AIN2 15 13 BIN1 9 7 BIN2 10 8 nSLEEP STATUS nFAULT OUTPUT AISEN 1 15 8 6 3 1 BISEN AOUT1 AOUT2 BOUT1 BOUT2 6 4 2 16 4 2 7 5 5 3 I/O (1) DESCRIPTION - Device ground - Device power supply - Internal supply bypass IO High-side gate drive voltage I Bridge A input 1 I Bridge A input 2 I Bridge B input 1 I Bridge B input 2 I Sleep mode input OD Fault output IO Bridge A ground / Isense IO Bridge B ground / Isense O Bridge A output 1 O Bridge A output 2 O Bridge B output 1 O Bridge B output 2 EXTERNAL COMPONENTS OR CONNECTIONS Both the GND pin and device PowerPAD must be connected to ground Connect to motor supply. A 10-µF (minimum) ceramic bypass capacitor to GND is recommended. Bypass to GND with 2.2-μF, 6.3-V capacitor Connect a 0.01-μF, 16-V (minimum) X7R ceramic capacitor to VM Logic input controls state of AOUT1. Internal pulldown. Logic input controls state of AOUT2. Internal pulldown. Logic input controls state of BOUT1. Internal pulldown. Logic input controls state of BOUT2. Internal pulldown. Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. Internal pulldown. Logic low when in fault condition (overtemp, overcurrent) Connect to current sense resistor for bridge A, or GND if current control not needed Connect to current sense resistor for bridge B, or GND if current control not needed Connect to motor winding A Connect to motor winding B (1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Copyright © 2011, Texas Instruments Incorporated 3 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 nSLEEP 1 AOUT1 2 AISEN 3 AOUT2 4 BOUT2 5 BISEN 6 BOUT1 7 nFAULT 8 PWP PACKAGE (TOP VIEW) GND (PPAD ) RTY PACKAGE (TOP VIEW) 16 AIN1 15 AIN2 14 VINT 13 GND 12 VM 11 VCP 10 BIN2 9 BIN1 16 AOUT1 15 nSLEEP 14 AIN1 13 AIN2 AISEN 1 AOUT2 2 BOUT2 3 BISEN 4 GND (PPAD) 12 VINT 11 GND 10 VM 9 VCP www.ti.com.cn BOUT1 5 nFAULT 6 BIN1 7 BIN2 8 4 Copyright © 2011, Texas Instruments Incorporated DRV8833 www.ti.com.cn ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 ABSOLUTE MAXIMUM RATINGS(1)(2) VALUE UNIT VM Power supply voltage range –0.3 to 11.8 V Digital input pin voltage range –0.5 to 7 V xISEN pin voltage –0.3 to 0.5 V Peak motor drive output current Internally limited A TJ Operating junction temperature range Tstg Storage temperature range –40 to 150 °C –60 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. THERMAL INFORMATION θJA θJCtop θJB ψJT ψJB θJCbot THERMAL METRIC Junction-to-ambient thermal resistance(1) Junction-to-case (top) thermal resistance(2) Junction-to-board thermal resistance(3) Junction-to-top characterization parameter(4) Junction-to-board characterization parameter(5) Junction-to-case (bottom) thermal resistance(6) PWP 16 PINS 40.5 32.9 28.8 0.6 11.5 4.8 RTY 16 PINS 37.2 34.3 15.3 0.3 15.4 3.5 UNITS °C/W (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS TA = 25°C (unless otherwise noted) VM VDIGIN IOUT Motor power supply voltage range(1) Digital input pin voltage range Continuous RMS or DC output current per bridge(2) MIN NOM 2.7 -0.3 (1) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V. (2) VM = 5 V, power dissipation and thermal limits must be observed. MAX 10.8 5.75 1.5 UNIT V V A Copyright © 2011, Texas Instruments Incorporated 5 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS POWER SUPPLY IVM IVMQ VUVLO VHYS VM operating supply current VM sleep mode supply current VM undervoltage lockout voltage VM undervoltage lockout hysteresis VM = 5 V, xIN1 = 0 V, xIN2 = 0 V VM = 5 V VM falling LOGIC-LEVEL INPUTS VIL Input low voltage nSLEEP All other pins VIH Input high voltage nSLEEP All other pins VHYS RPD Input hysteresis Input pull-down resistance nSLEEP All except nSLEEP IIL Input low current IIH Input high current VIN = 0 VIN = 3.3 V, nSLEEP VIN = 3.3 V, all except nSLEEP tDEG Input deglitch time nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IOH Output high leakage current H-BRIDGE FETS IO = 5 mA VO = 3.3 V HS FET on resistance RDS(ON) LS FET on resistance IOFF Off-state leakage current MOTOR DRIVER VM = 5 V, I O = 500 mA, TJ = 25°C VM = 5 V, IO = 500 mA, TJ = 85°C VM = 2.7 V, I O = 500 mA, TJ = 25°C VM = 2.7 V, IO = 500 mA, TJ = 85°C VM = 5 V, I O = 500 mA, TJ = 25°C VM = 5 V, IO = 500 mA, TJ = 85°C VM = 2.7 V, I O = 500 mA, TJ = 25°C VM = 2.7 V, IO = 500 mA, TJ = 85°C VM = 5 V, TJ = 25°C, VOUT = 0 V fPWM Current control PWM frequency tR Rise time tF Fall time tPROP tDEAD Propagation delay INx to OUTx Dead time(1) PROTECTION CIRCUITS Internal PWM frequency VM = 5 V, 16 Ω to GND, 10% to 90% VM VM = 5 V, 16 Ω to GND, 10% to 90% VM VM = 5 V VM = 5 V IOCP Overcurrent protection trip level tDEG OCP Deglitch time tOCP Overcurrent protection period tTSD Thermal shutdown temperature Die temperature (1) Internal dead time. External implementation is not necessary. www.ti.com.cn MIN TYP MAX UNIT 1.7 3 mA 1.6 2.5 μA 2.6 V 90 mV 2.5 2 0.4 500 150 6.6 16.5 450 200 250 160 200 –1 50 180 160 1.1 450 2 3.3 2.25 1.35 150 160 0.5 V 0.7 V V kΩ 1 μA 13 μA 33 ns 0.5 V 1 μA 325 350 mΩ 275 300 1 μA kHz ns ns µs ns A µs ms 180 °C 6 Copyright © 2011, Texas Instruments Incorporated DRV8833 www.ti.com.cn ELECTRICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS CURRENT CONTROL VTRIP xISEN trip voltage tBLANK Current sense blanking time SLEEP MODE tWAKE Startup time nSLEEP inactive high to H-bridge on ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 MIN TYP MAX UNIT 160 200 3.75 240 mV µs 1 ms Copyright © 2011, Texas Instruments Incorporated 7 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 FUNCTIONAL DESCRIPTION www.ti.com.cn PWM Motor Drivers DRV8833 contains two identical H-bridge motor drivers with current-control PWM circuitry. A block diagram of the circuitry is shown below: xIN1 xIN2 VCP, VINT OCP Predrive PWM OCP + REF (200mV) VM VM xOUT1 xOUT 2 DCM xISEN Optional Figure 1. Motor Control Circuitry Bridge Control and Decay Modes The AIN1 and AIN2 input pins control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1 and BIN2 input pins control the state of the BOUT1 and BOUT2 outputs. Table 2 shows the logic. xIN1 0 0 1 1 Table 2. H-Bridge Logic xIN2 xOUT1 xOUT2 0 Z Z 1 L H 0 H L 1 L L FUNCTION Coast/fast decay Reverse Forward Brake/slow decay The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted. To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow decay, one xIN pin is held high. Table 3. PWM Control of Motor Speed xIN1 PWM 1 0 PWM xIN2 0 PWM PWM 1 FUNCTION Forward PWM, fast decay Forward PWM, slow decay Reverse PWM, fast decay Reverse PWM, slow decay 8 Copyright © 2011, Texas Instruments Incorporated DRV8833 www.ti.com.cn Figure 2 shows the current paths in different drive and decay modes. VM ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 VM 1 xOUT1 2 3 1 Forward drive 2 Fast decay 1 xOUT2 3 Slow decay xOUT1 2 3 xOUT2 1 Reverse drive 2 Fast decay 3 Slow decay FORWARD Figure 2. Decay Modes REVERSE Current Control The current through the motor windings may be limited, or controlled, by a fixed-frequency PWM current regulation, or current chopping. For DC motors, current control is used to limit the start-up and stall current of the motor. For stepper motors, current control is often used at all times. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Note that immediately after the current is enabled, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins with a reference voltage. The reference voltage is fixed at 200 mV. The chopping current is calculated in Equation 1. I= CHOP 200 mV ¾ R ISENSE (1) Example: If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA. Once the chopping current threshold is reached, the H-bridge switches to slow decay mode. Winding current is re-circulated by enabling both of the low-side FETs in the bridge. This state is held until the beginning of the next fixed-frequency PWM cycle. Note that if current control is not needed, the xISEN pins should be connected directly to ground. Copyright © 2011, Texas Instruments Incorporated 9 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 www.ti.com.cn nSLEEP Operation Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (up to 1 ms) needs to pass before the motor driver becomes fully operational. To make the board design simple, the nSLEEP can be pulled up to the supply (VM). It is recommended to use a pullup resistor when this is done. This resistor limits the current to the input in case VM is higher than 6.5 V. Internally, the nSLEEP pin has a 500-kΩ resistor to GND. It also has a clamping zener diode that clamps the voltage at the pin at 6.5 V. Currents greater than 250 µA can cause damage to the input structure. Hence the recommended pullup resistor would be between 20 kΩ and 75 kΩ. Protection Circuits The DRV8833 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (tOCP) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally. Overcurrent conditions are detected independently on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, so functions even without presence of the xISEN resistors. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. nFAULT is driven low in the event of an undervoltage condition. 10 Copyright © 2011, Texas Instruments Incorporated DRV8833 www.ti.com.cn ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 APPLICATIONS INFORMATION Parallel Mode The two H-bridges in the DRV8833 can be connected in parallel for double the current of a single H-bridge. The internal dead time in the DRV8833 prevents any risk of cross-conduction (shoot-through) between the two bridges due to timing differences between the two bridges. The drawing below shows the connections. Figure 3. Parallel Mode Copyright © 2011, Texas Instruments Incorporated 11 DRV8833 ZHCS016B – JANUARY 2011 – REVISED AUGUST 2011 THERMAL INFORMATION www.ti.com.cn Maximum Output Current In actual operation, the maximum output current achievable with a motor driver is a function of die temperature. This in turn is greatly affected by ambient temperature and PCB design. Basically, the maximum motor current will be the amount of current that results in a power dissipation level that, along with the thermal resistance of the package and PCB, keeps the die at a low enough temperature to stay out of thermal shutdown. The dissipation ratings given in the datasheet can be used as a guide to calculate the approximate maximum power dissipation that can be expected to be possible without entering thermal shutdown for several different PCB constructions. However, for accurate data, the actual PCB design must be analyzed via measurement or thermal simulation. Thermal Protection The DRV8833 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops by 45°C. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8833 is dominated by the DC power dissipated in the output FET resistance, or RDS(ON). There is additional power dissipated due to PWM switching losses, which are dependent on PWM frequency, rise and fall times, and VM supply voltages. These switching losses are typically on the order of 10% to 30% of the DC power dissipation. The DC power dissipation of one H-bridge can be roughly estimated by Equation 2. PTOT = (HS - RDS(ON) · I )2 OUT(RMS) + (LS - RDS(ON) · I )2 OUT(RMS) (2) where PTOT is the total power dissipation, HS - RDS(ON) is the resistance of the high side FET, LS - RDS(ON) is the resistance of the low side FET, and IOUT(RMS) is the RMS output current being applied to the motor. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 12 Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device DRV8833PW DRV8833PWP DRV8833PWPR DRV8833PWR DRV8833RTYR DRV8833RTYT Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) (1) Drawing Qty (2) (3) ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) ACTIVE HTSSOP PWP 16 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) ACTIVE HTSSOP PWP 16 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) ACTIVE QFN RTY 16 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) ACTIVE QFN RTY 16 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Top-Side Markings (4) 8833PW DRV8833 DRV8833 8833PW DRV8833 DRV8833 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 www.ti.com TAPE AND REEL INFORMATION PACKAGE MATERIALS INFORMATION 4-Mar-2013 *All dimensions are nominal Device Package Package Pins Type Drawing DRV8833PWPR DRV8833PWR DRV8833RTYR DRV8833RTYT HTSSOP PWP 16 TSSOP PW 16 QFN RTY 16 QFN RTY 16 SPQ 2000 2000 3000 250 Reel Reel A0 B0 K0 P1 W Pin1 Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 www.ti.com PACKAGE MATERIALS INFORMATION 4-Mar-2013 *All dimensions are nominal Device DRV8833PWPR DRV8833PWR DRV8833RTYR DRV8833RTYT Package Type HTSSOP TSSOP QFN QFN Package Drawing Pins PWP 16 PW 16 RTY 16 RTY 16 SPQ 2000 2000 3000 250 Length (mm) 367.0 367.0 367.0 210.0 Width (mm) 367.0 367.0 367.0 185.0 Height (mm) 35.0 35.0 35.0 35.0 Pack Materials-Page 2 重要声明 德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改, 并有权根据 JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售 都遵循在订单确认时所提供的TI 销售条款与条件。 TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内,且 TI 认为 有必要时才会使 用测试或其它质量控制技术。除非适用法律做出了硬性规定,否则没有必要对每种组件的所有参数进行测试。 TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险, 客户应提供充分的设计与操作安全措施。 TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权 限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息,不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用 此类信息可能需要获得第三方的专利权或其它知识产权方面的许可,或是 TI 的专利权或其它 知识产权方面的许可。 对于 TI 的产品手册或数据表中 TI 信息的重要部分,仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行 复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。 在转售 TI 组件或服务时,如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分,则会失去相关 TI 组件 或服务的所有明 示或暗示授权,且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。 客户认可并同意,尽管任何应用相关信息或支持仍可能由 TI 提供,但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法 律、法规和安全相关要求。客户声明并同意,他们具备制定与实施安全措施所需的全部专业技术和知识,可预见 故障的危险后果、监测故障 及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而 对 TI 及其代理造成的任何损失。 在某些场合中,为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用 的功能安全性标准和要求的终端产品解决方案。尽管如此,此类组件仍然服从这些条款。 TI 组件未获得用于 FDA Class III(或类似的生命攸关医疗设备)的授权许可,除非各方授权官员已经达成了专门管控此类使 用的特别协议。 只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意,对并非指定面 向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用,其风险由客户单独承担,并且由客户独 力负责满足与此类使用相关的所有 法律和法规要求。 TI 已明确指定符合 ISO/TS16949 要求的产品,这些产品主要用于汽车。在任何情况下,因使用非指定产品而无法达到 ISO/TS16949 要 求,TI不承担任何责任。 产品 应用 数字音频 www.ti.com.cn/audio 通信与电信 www.ti.com.cn/telecom 放大器和线性器件 www.ti.com.cn/amplifiers 计算机及周边 www.ti.com.cn/computer 数据转换器 www.ti.com.cn/dataconverters 消费电子 www.ti.com/consumer-apps DLP® 产品 www.dlp.com 能源 www.ti.com/energy DSP - 数字信号处理器 www.ti.com.cn/dsp 工业应用 www.ti.com.cn/industrial 时钟和计时器 www.ti.com.cn/clockandtimers 医疗电子 www.ti.com.cn/medical 接口 www.ti.com.cn/interface 安防应用 www.ti.com.cn/security 逻辑 www.ti.com.cn/logic 汽车电子 www.ti.com.cn/automotive 电源管理 www.ti.com.cn/power 视频和影像 www.ti.com.cn/video 微控制器 (MCU) www.ti.com.cn/microcontrollers RFID 系统 www.ti.com.cn/rfidsys OMAP应用处理器 www.ti.com/omap 无线连通性 www.ti.com.cn/wirelessconnectivity 德州仪器在线技术支持社区 www.deyisupport.com IMPORTANT NOTICE 邮寄地址: 上海市浦东新区世纪大道1568 号,中建大厦32 楼邮政编码: 200122 Copyright © 2014, 德州仪器半导体技术(上海)有限公司

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