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4099 CMOS 八位可寻址锁存器.pdf

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4099 CMOS 八位可寻址锁存器.pdf

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CD4099BC 8-Bit Addressable Latch October 1987 Revised January 1999 CD4099BC 8-Bit Addressable Latch General Description The CD4099BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D), and eight outputs (Q0–Q7). Data is entered into a particular bit in the latch when that bit is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random (addressable) data entry s Active high demultiplexing capability s Common active high clear Ordering Code: Order Number Package Number Package Description CD4099BCN N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagram Pin Assignments for DIP Truth Table Top View Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Holds Previous Data Holds Previous Data Memory L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear © 1999 Fairchild Semiconductor Corporation DS005984.prf www.fairchildsemi.com CD4099BC Logic Diagram www.fairchildsemi.com 2 CD4099BC Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) −0.5 to +18 VDC −0.5 to VDD +0.5 VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) 3.0 to 15 VDC Input Voltage (VIN) 0 to VDD VDC Operating Temperature Range (TA) −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 2) Symbol Parameter Conditions IDD Quiescent Device VDD = 5V, VIN = VDD or VSS Current VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS VOL LOW Level |IO| ≤ 1µA Output Voltage VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level |IO| ≤ 1 µA Output Voltage VDD = 5V VDD = 10V VDD = 15V VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V Input Voltage VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V Input Voltage VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V IOL LOW Level Output VDD = 5V, VO = 0.4V Current (Note 3) VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V IOH HIGH Level Output VDD = 5V, VO = 4.6V Current (Note 3) VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V IIN Input Current VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 3: IOH and IOL are tested one output at a time. −40°C Min Max 20 40 80 +25°C Min Typ Max 0.02 20 0.02 40 0.02 80 +85°C Min Max 150 300 600 Units µA µA µA 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V 4.95 4.95 5 4.95 V 9.95 9.95 10 9.95 V 14.95 14.95 15 14.95 V 1.5 2.25 1.5 1.5 V 3.0 4.5 3.0 3.0 V 4.0 6.75 4.0 4.0 V 3.5 3.5 2.75 3.5 V 7.0 7.0 5.5 7.0 V 11.0 11.0 8.25 11.0 V 0.52 0.44 0.88 0.36 mA 1.3 1.1 2.25 0.9 mA 3.6 3.0 8.8 2.4 mA −0.52 −0.44 −0.88 −0.36 mA −1.3 −1.1 −2.25 −0.9 mA −3.6 −3.0 −8.8 −2.4 mA −0.30 −10−5 −0.30 −1.0 µA 0.30 10−5 0.30 1.0 µA 3 www.fairchildsemi.com CD4099BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tPHL, tPLH tPLH, tPHL tPHL tTLH, tTHL tTHL, tTLH TWH, TWL tWH, tWL tWH tSU tH tSU tH CPD Propagation Delay Data to Output Propagation Delay Enable to Output Propagation Delay Clear to Output Propagation Delay Address to Output Transition Time (Any Output) Minimum Data Pulse Width Minimum Address Pulse Width Minimum Clear Pulse Width Minimum Set-Up Time Data to E Minimum Hold Time Data to E Minimum Set-Up Time Address to E Minimum Hold Time Address to E Power Dissipation Capacitance VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Per Package (Note 5) 200 400 ns 75 150 ns 50 100 ns 200 400 ns 80 160 ns 60 120 ns 175 350 ns 80 160 ns 65 130 ns 225 450 ns 100 200 ns 75 150 ns 100 200 ns 50 100 ns 40 80 ns 100 200 ns 50 100 ns 40 80 ns 200 400 ns 100 200 ns 65 125 ns 75 150 ns 40 75 ns 25 50 ns 40 80 ns 20 40 ns 15 30 ns 60 120 ns 30 60 ns 25 50 ns −15 50 ns 0 30 ns 0 20 ns −50 15 ns −20 10 ns −15 5 ns 100 pF CIN Input Capacitance Any Input Note 4: AC Parameters are guaranteed by DC correlated testing. 5.0 7.5 pF Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details, see application note AN-90, “54C/74C Family Characteristics”. www.fairchildsemi.com 4 CD4099BC Switching Time Waveforms 5 www.fairchildsemi.com CD4099BC 8-Bit Addressable Latch Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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