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LTC1250 Very Low Noise Zero-Drift Bridge Amplifier UO UO U FEATURES s Very Low Noise: 0.75µVP-P Typ, 0.1Hz to 10Hz s DC to 1Hz Noise Lower Than OP-07 s Full Output Swing into 1k Load s Offset Voltage: 10µV Max s Offset Voltage Drift: 50nV/°C Max s Common-Mode Rejection Ratio: 110dB Min s Power Supply Rejection Ratio: 115dB Min s No External Components Required s Pin-Compatible with Standard 8-Pin Op Amps APPLICATI S s Electronic Scales s Strain Gauge Amplifiers s Thermocouple Amplifiers s High Resolution Data Acquisition s Low Noise Transducers s Instrumentation Amplifiers and LTC are registered trademarks and LT is a trademark of Linear Technology Corporation. DESCRIPTIO The LTC®1250 is a high performance, very low noise zerodrift operational amplifier. The LTC1250’s combination of low front-end noise and DC precision makes it ideal for use with low impedance bridge transducers. The LTC1250 features typical input noise of 0.75µVP-P from 0.1Hz to 10Hz, and 0.2µVP-P from 0.1Hz to 1Hz. The LTC1250 has DC to 1Hz noise of 0.35µVP-P, surpassing that of low noise bipolar parts including the OP-07, OP-77, and LT1012. The LTC1250 uses the industry-standard single op amp pinout, and requires no external components or nulling signals, allowing it to be a plug-in replacement for bipolar op amps. The LTC1250 incorporates an improved output stage capable of driving 4.3V into a 1k load with a single 5V supply; it will swing ±4.9V into 5k with ±5V supplies. The input common mode range includes ground with single power supply voltages above 12V. Supply current is 3mA with a ±5V supply, and overload recovery times from positive and negative saturation are 0.5ms and 1.5ms, respectively. The internal nulling clock is set at 5kHz for optimum low frequency noise and offset drift; no external connections are necessary. The LTC1250 is available in standard 8-pin ceramic and plastic DIPs, as well as an 8-pin SOIC package. TYPICAL APPLICATI Differential Bridge Amplifier 5V 5V 50Ω GAIN TRIM 0.1µF 1000pF 18.2k 350Ω STRAIN GAUGE 2– 7 LTC1250 6 3+ 4 1000pF 18.2k –5V –5V AV = 100 1250 TA01 µV Input Referred Noise 0.1Hz to 10Hz 2 VS = ±5V AV = 10k 1 0 –1 –2 0 2 4 6 8 10 TIME (s) LT1250 TA02 1 LTC1250 U WU U WW W ABSOLUTE AXI U RATI GS Total Supply Voltage (V+ to V –) ............................. 18V Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V) Output Short Circuit Duration ......................... Indefinite Operating Temperature Range LTC1250M..................................... – 55°C to 125°C LTC1250C .......................................... 0°C TO 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C PACKAGE/ORDER I FOR ATIO TOP VIEW NC 1 –IN 2 +IN 3 V– 4 8 NC 7 V+ 6 OUT 5 NC J8 PACKAGE N8 PACKAGE 8-LEAD CERAMIC DIP 8-LEAD PLASTIC DIP S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 150°C, θJA = 100°CW (J8) TJMAX = 110°C, θJA = 130°CW (N8) TJMAX = 110°C, θJA = 200°CW (S8) ORDER PART NUMBER LTC1250MJ8 LTC1250CJ8 LTC1250CN8 LTC1250CS8 S8 PART MARKING 1250 ELECTRICAL CHARACTERISTICS VIN = ±5V, TA = Operating Temperature Range, unless otherwise noted. SYMBOL PARAMETER VOS ∆VOS Input Offset Voltage Average Input Offset Drift Long Term Offset Drift en Input Noise Voltage (Note 2) in Input Noise Current IB Input Bias Current CONDITIONS TA = 25°C (Note 1) (Note 1) TA = 25°C, 0.1Hz to 10Hz TA = 25°C, 0.1Hz to 1Hz f = 10Hz TA = 25°C (Note 3) IOS Input Offset Current TA = 25°C (Note 3) CMRR PSRR AVOL SR GBW IS Common-Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Maximum Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current VCM = – 4V to 3V VS = ±2.375V to ±8V RL = 10k, VOUT = ±4V RL = 1k RL = 100k RL = 10k, CL = 50pF No Load, TA = 25°C fS Internal Sampling Frequency TA = 25°C LTC1250M MIN TYP MAX ±5 ±10 q ±0.01 ±0.05 50 0.75 1.0 0.2 4.0 ±50 ±150 q ±950 ±100 ±300 q ±500 q 110 130 q 115 130 q 125 170 q ±4.0 4.3/–4.7 ±4.92 10 1.5 3.0 4.0 q 7.0 4.75 LTC1250C MIN TYP MAX ±5 ±10 ±0.01 ±0.05 50 0.75 1.0 0.2 4.0 ±50 ±200 ±450 ±100 ±400 ±500 110 130 115 130 125 170 ±4.0 4.3 /–4.7 ±4.95 10 1.5 3.0 4.0 5.0 4.75 UNITS µV µV/ °C nV/√Mo µVP-P µVP-P fA/√Hz pA pA pA pA dB dB dB V V V/µs MHz mA mA kHz VIN = 5V, TA = Operating Temperature Range, unless otherwise noted. SYMBOL PARAMETER VOS ∆VOS en Input Offset Voltage Average Input Offset Drift Input Noise Voltage (Note 2) IB Input Bias Current IOS Input Offset Current CONDITIONS TA = 25°C (Note 1) (Note 1) TA = 25°C, 0.1Hz to 10Hz TA = 25°C, 0.1Hz to 1Hz TA = 25°C (Note 3) TA = 25°C (Note 3) LTC1250M MIN TYP MAX ±2 ±5 q ±0.01 ±0.05 1.0 0.3 ±20 ±100 ±40 ±200 LTC1250C MIN TYP MAX ±2 ±5 ±0.01 ±0.05 1.0 0.3 ±20 ±100 ±40 ±200 UNITS µV µV/°C µVP-P µVP-P pA pA 2 LTC1250 ELECTRICAL CHARACTERISTICS VIN = 5V, TA = Operating Temperature Range, unless otherwise noted. SYMBOL PARAMETER CONDITIONS Maximum Output Voltage Swing RL = 1k RL = 100k IS Supply Current TA = 25°C fS Sampling Frequency TA = 25°C The q denotes specifications which apply over the full operating temperature range. Note 1: These parametes are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels during automated testing. Note 2: 0.1Hz to 10Hz noise is specified DC coupled in a 10s window; 0.1Hz to 1Hz noise is specified in a 100s window with an RC high-pass LTC1250M MIN TYP MAX 4.0 4.3 4.95 1.8 2.5 3 LTC1250C MIN TYP MAX 4.0 4.3 4.95 1.8 2.5 3 UNITS V V mA kHz filter at 0.1Hz. The LTC1250 is sample tested for noise; for 100% tested parts contact LTC Marketing Dept. Note 3: At T ≤ 0°C these parameters are guaranteed by design and not tested. UW INPUT NOISE (µVP-P) TYPICAL PERFOR A CE CHARACTERISTICS Input Noise vs Supply Voltage 1.6 TA = 25°C 1.4 1.2 1.0 0.8 0.1Hz TO 10Hz 0.6 0.4 0.1Hz TO 1Hz 0.2 0 46 8 10 12 14 16 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) LTC1250 G01 Input Noise vs Temperature 1.2 VS = ±5V 1.0 0.8 0.1Hz TO 10Hz 0.6 0.4 0.1Hz TO 1Hz 0.2 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 LTC1250 G04 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) Supply Current vs Supply Voltage 4.0 TA = 25°C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 46 8 10 12 14 16 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) LTC1250 G02 Supply Current vs Temperature 4.5 VS = ±5V 4.0 3.5 3.0 2.5 2.0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 LTC1250 G05 SAMPLING FREQUENCY (kHz) SAMPLING FREQUENCY (kHz) Sampling Frequency vs Supply Voltage 6 TA = 25°C 5 4 3 2 46 8 10 12 14 16 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) LTC1250 G03 Sampling Frequency vs Temperature 8 7 6 VS = ±5V 5 4 3 2 1 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 150 LTC1250 G06 3 INPUT NOISE (µVP-P) VOLTAGE NOISE (nV/√Hz) OUTPUT (V) INPUT (V) LTC1250 TYPICAL PERFOR A CE CHARACTERISTICS UW Voltage Noise vs Frequency 80 VS = ±5V 70 RS = 10Ω 60 50 40 30 20 10 0 1 10 100 1k 10k FREQUENCY (Hz) LTC1250 G11 Overload Recovery 0.2 0 0 –5 500µs/DIV AV = 100, RL = 100k, CL = 50pF, VS = ±5V Transient Response 2V/DIV 1µs/DIV AV = 1, RL = 100k, CL = 50pF, VS = ±5V OUTPUT SWING (±V) INPUT COMMON MODE RANGE (V) GAIN (dB) Gain/Phase vs Frequency 100 80 Bias Current (Magnitude) vs Temperature 100 1000 VS = ±5V 80 BIAS CURRENT (|pA|) PHASE MARGIN (DEG) 60 GAIN PHASE: 60 RL = 100k 40 40 20 VS = ±5V OR 0 SINGLE 5V TA = 25°C CL = 100pF – 20 1k 10k 100k PHASE: 20 RL = 1k 0 – 20 1M 10M FREQUENCY (Hz) LTC1250 G10 Common-Mode Input Range vs Supply Voltage 8 TA = 25°C 6 4 2 0 –2 –4 –6 –8 2 3 4 5 6 7 8 SUPPLY VOLTAGE (±V) LTC1250 G07 Output Swing vs Load Resistance, Dual Supplies 10 9 8 VS = ±8V RL TO GND 7 6 5 VS = ±5V 4 3 VS = ±2.5V 2 NEGATIVE SWING 1 POSITIVE SWING 0 0 1 2 3 4 5 6 7 8 9 10 LOAD RESISTANCE (kΩ) LTC1250 G08 OUTPUT SWING (V) CMRR (dB) 100 10 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 LTC1250 G14 Common-Mode Rejection Ratio vs Frequency 140 VS = ±5V 120 VCM = 1VRMS 100 80 60 40 20 0 1 10 100 1k 10k 100k FREQUENCY (Hz) LTC1250 G12 Output Voltage Swing vs Load Resistance, Single Supply 18 16 VS = 16V 14 12 VS = 10V 10 8 6 VS = 5V 4 2 V– = GND RL TO GND 0 0 1 2 3 4 5 6 7 8 9 10 LOAD RESISTANCE (kΩ) LTC1250 G09 4 TYPICAL PERFOR A CE CHARACTERISTICS LTC1250 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) SHORT-CIRCUIT CURRENT (mA) U W U UO UW Output Swing vs Output Current, ±5V Supply 5 4 VS = ±5V 3 2 1 0 –1 –2 –3 –4 –5 0.01 0.1 1 10 OUTPUT CURRENT (mA) LTC1250 G16 Output Swing vs Output Current, Single 5V Supply 6 VS = SINGLE 5V 5 4 3 2 1 0 0.01 0.1 1 10 OUTPUT CURRENT (mA) LTC1250 G17 Short-Circuit Current vs Temperature 40 VS = ±15V 30 20 VOUT = V – 10 0 –10 – 20 VOUT = V + – 30 – 40 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 LTC1250 G18 TEST CIRCUITS Offset Test Circuit 100pF 100k 5V 2– 7 10Ω LTC1250 6 OUTPUT 3+ 4 –5V 1250 TC01 DC to 10Hz Noise Test Circuit 100pF (for DC to 1Hz Multiply All Capacitor Values by 10) 100k 5V 5V 2– 7 10Ω LTC1250 3+ 4 6 800k 2 –8 1/2 3 LT1057 + 4 1 800k 0.04µF 6 – 800k 1/2 LT1057 5+ 7 OUTPUT –5V 0.02µF –5V 0.01µF 1250 TC02 APPLICATI S I FOR ATIO Input Noise The LTC1250, like all CMOS amplifiers, exhibits two types of low frequency noise: thermal noise and 1/f noise. The LTC1250 uses several design modifications to minimize these noise sources. Thermal noise is minimized by raising the gM of the front-end transistors by running them at high bias levels and using large transistor geometries. 1/f noise is combated by optimizing the zero-drift nulling loop to run at twice the 1/f corner frequency, allowing it to reduce the inherently high CMOS 1/f noise to near thermal levels at low frequencies. The resultant noise spectrum is quite low at frequencies below the internal 5kHz clock VOLTAGE NOISE (nV/√Hz) 80 VS = ±5V 70 RS = 10Ω OP-27 OP-07 60 50 LTC1250 40 30 20 10 0 0.01 0.1 1 FREQUENCY (Hz) LTC1250 F01 Figure 1. Voltage Noise vs Frequency 5 LTC1250 U W U UO APPLICATI S I FOR ATIO frequency, approaching the best bipolar op amps at 10Hz and surpassing them below 1Hz (Figure 1). All this is accomplished in an industry-standard pinout; the LTC1250 requires no external capacitors, no nulling or clock signals, and conforms to industry-standard 8-pin DIP and 8pin SOIC packages. Input Capacitance and Compensation The large input transistors create a parasitic 55pF capacitance from each input to V+. This input capacitance will react with the external feedback resistors to form a pole which can affect amplifier stability. In low gain, high impedance configurations, the pole can land below the unity-gain frequency of the feedback network and degrade phase margin, causing ringing, oscillation, and other unpleasantness. This is true of any op amp, however, the 55pF capacitance at the LTC1250’s inputs can affect stability with a feedback network impedance as low as 1.9k. This effect can be eliminated by adding a capacitor across the feedback resistor, adding a zero which cancels the input pole (Figure 2). The value of this capacitor should be: CF ≥ 55pF AV where AV = closed-loop gain. Note that CF is not dependent on the value of RF. Circuits with higher gain (AV > 50) or low loop impedance should not require CF for stability. CF RIN CP RF – LTC1250 + 1250 F02 Figure 2. CF Cancels Phase Shift Due to Parasitic CP Larger values of CF, commonly used in band-limited DC circuits, may actually increase low frequency noise. The nulling circuitry in the LTC1250 closes a loop that includes the external feedback network during part of its cycle. This loop must settle to its final value within 150µs or it will not fully cancel the 1/f noise spectrum and the low frequency noise of the part will rise. If the loop is underdamped (large RF, no CF) it will ring for more than 150µs and the noise and offset will suffer. The solution is to add CF as above but beware! Too large a value of CF will overdamp the loop, again preventing it from reaching a final value by the 150µs deadline. This condition doesn’t affect the LTC1250’s offset or output stability, but 1/f noise begins to rise. As a rule of thumb, the RFCF feedback pole should be ≥ 7kHz (1/150µs, the frequency at which the loop settles) for best 1/f performance; values between 100pF and 500pF work well with feedback resistors below 100k. This ensures adequate gain at 7kHz for the LTC1250 to properly null. High value feedback resistors (above 1M) may require experimentation to find the correct value because parasitics, both in the LTC1250 and on the PC board, play an increasing role. Low value resistors (below 5k) may not require a capacitor at all. Input Bias Current The inputs of the LTC1250, like all zero-drift op amps, draw only small switching spikes of AC bias current; DC leakage current is negligible except at very high temperatures. The large front-end transistors cause switching spikes 3 to 4 times greater than standard zero-drift op amps: the ±50pA bias current spec is still many times better than most bipolar parts. The spikes don’t match from one input pin to the other, and are sometimes (but not always) of opposite polarity. As a result, matching the impedances at the inputs (Figure 3) will not cancel the bias current, and may cause additional errors. Don’t do it. RF RIN – LTC1250 + 1250 F03 Figure 3. Extra Resistor Will Not Cancel Bias Current Errors 6 LTC1250 U W U UO APPLICATI S I FOR ATIO Output Drive The LTC1250 includes an enhanced output stage which provides nearly symmetrical output source/sink currents. This output is capable of swinging a minimum of ±4V into a 1k load with ±5V supplies, and can sink or source >20mA into low impedance loads. Lightly loaded (RL ≥100k), the LTC1250 will swing to within millivolts of either rail. In single supply applications, it will typically swing 4.3V into a 1k load with a 5V supply. Minimizing External Errors The input noise, offset voltage, and bias current specs for the LTC1250 are all well below the levels of circuit board parasitics. Thermocouples between the copper pins of the LTC1250 and the tin/lead solder used to connect them can overwhelm the offset voltage of the LTC1250, especially if a soldering iron has been around recently. Note also that when the LTC1250’s output is heavily loaded, the chip may dissipate substantial power, raising the temperature of the package and aggravating thermocouples at the inputs. Although the LTC1250 will maintain its specified accuracy under these conditions, care must be taken in the layout to prevent or compensate circuit errors. Be especially careful of air currents when measuring low frequency noise; nearby moving objects (like people) can create very large noise peaks with an unshielded circuit board. For more detailed explanations and advice on how to avoid these errors, see the LTC1051/LTC1053 data sheet. Sampling Behavior The LTC1250’s zero-drift nulling loop samples the input at ≈ 5kHz, allowing it to process signals below 2kHz with no aliasing. Signals above this frequency may show aliasing behavior, although wideband internal circuitry generally keeps errors to a minimum. The output of the LTC1250 will have small spikes at the clock frequency and its harmonics; these will vary in amplitude with different feedback configurations. Low frequency or band-limited systems should not be affected, but systems with higher bandwidth (oversampling A/Ds, for example) may need to filter out these clock artifacts. Output spikes can be minimized with a large feedback capacitor, but this will adversely affect noise performance (see Input Capacitance and Compensation on the previous page). Applications which require spike-free output in addition to minimum noise will need a low-pass filter after the LTC1250; a simple RC will usually do the job (Figure 4). The LTC1051/LTC1053 data sheet includes more information about zero-drift amplifier sampling behavior. CF RF – LTC1250 + 47k 0.01 1250 F04 Figure 4. RC Output Pole Limits Bandwidth to 330Hz Single Supply Operation The LTC1250 will operate with single supply voltages as low as 4.5V, and the output swings to within millivolts of either supply when lightly loaded. The input stage will common mode to within 250mV of ground with a single 5V supply, and will common mode to ground with single supplies above 11V. Most bridge transducers bias their inputs above ground when powered from single supplies, allowing them to interface directly to the LTC1250 in single supply applications. Single-ended, ground-referenced signals will need to be level shifted slightly to interface to the LTC1250’s inputs. Fault Conditions The LTC1250 is designed to withstand most external fault conditions without latch-up or damage. However, unusually severe fault conditions can destroy the part. All pins are protected against faults of ±25mA or 5V beyond either supply, whichever comes first. If the external circuitry can exceed these limits, series resistors or voltage clamp diodes should be included to prevent damage. The LTC1250 includes internal protection against ESD damage. All data sheet parameters are maintained to 1kV ESD on any pin; beyond 1kV, the input bias and offset currents will increase, but the remaining specs are unaffected and the part remains functional to 5kV at the input pins and 8kV at the output pin. Extreme ESD conditions should be guarded against by using standard anti-static precautions. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7 LTC1250 UO TYPICAL APPLICATI S Reference Buffer 15V 7.5k 31 LM399 3+ 7 LTC1250 6 2– 4 42 ±10ppm ERROR AT ±15mA 1µVP-P OUTPUT NOISE 2.5µV/°C DRIFT (DUE TO LM399) 1250 TA03 Differential Thermocouple Ampliifer – TYPE K† VCM C1 100pF R3 1M 0.1% R1 10k 5V 0.1% 2– 7 LTC1250 6 + R2 3+ 4 10k 0.1% R4 1M 0.1% –5V C2 100pF VOUT 100mV/°C R6 7.5k 1% R7 500Ω FULL-SCALE TRIM 5V R8 R5 5k VIN 3k 1% 10mV/°C VOUT LT1025 R9 † FOR BEST ACCURACY, THERMOCOUPLE 33k RESISTANCE SHOULD BE LESS THAN 100Ω GND –5V 1250 TA04 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. J8 Package 8-Lead Ceramic DIP CORNER LEADS OPTION (4 PLCS) 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.300 BSC (0.762 BSC) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.005 (0.127) MIN 0.025 (0.635) RAD TYP 0.405 (10.287) MAX 8 7 6 5 0.220 – 0.310 (5.588 – 7.874) 1 2 3 4 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° 0.385 ± 0.025 (9.779 ± 0.635) 0.045 – 0.068 (1.143 – 1.727) 0.014 – 0.026 (0.360 – 0.660) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS. 0.125 3.175 0.100 ± 0.010 MIN (2.540 ± 0.254) J8 0694 N8 Package 8-Lead Plastic DIP 0.400* (10.160) MAX 8 7 6 5 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 12 0.045 – 0.065 (1.143 – 1.651) 34 0.130 ± 0.005 (3.302 ± 0.127) 0.009 – 0.015 (0.229 – 0.381) 0.065 (1.651) TYP +0.025 0.325 –0.015 ( ) 8.255 +0.635 –0.381 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm). 0.125 (3.175) MIN 0.015 (0.380) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 0694 S8 Package 8-Lead Plastic SOIC 0.010 (0.254 – – 0.020 0.508) × 45° 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC 0.228 – 0.244 (5.791 – 6.197) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 1 2 34 0.150 – 0.157* (3.810 – 3.988) SO8 0294 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 LT/GP 0894 2K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1994

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