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40108 CMOS 4×4多端寄存.pdf

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标签: 40108CMOS4×4多端寄存

40108 CMOS 4×4多端寄存.pdf

CD40108BMS December 1992 CMOS 4 x 4 Multiport Register Features Description • High Voltage Type (20V Rating) • Four 4-Bit Registers • One Input and Two Output Buses • Unlimited Expansion in Bit and Word Directions • Data Lines have latched Inputs • 3-State Outputs • Separate Control of Each Bus, Allowing Simultaneous Independent Reading of Any of Four Registers on Bus A and Bus B and Independent Writing Into Any of the Four Registers • CD40108BMS is Pin-Compatible with Industry Type MC14580 • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-impedance state. The high-impedance third state provides the outputs with the capability of being connected to the bus lines in a bus-organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input. The CD40108BMS is supplied in these 24-lead outline packages: Braze Seal DIP H4V Ceramic Flatpack H4P Applications • Scratch-Pad Memories • Arithmetic Units • Data Storage Pinout CD40108BMS TOP VIEW Q3 B 1 Q2 B 2 3-STATE A 3 Q0 A 4 Q1 A 5 Q2 A 6 Q3 A 7 WRITE 0 8 WRITE 1 9 READ 1B 10 READ 0B 11 VSS 12 24 VDD 23 Q1 B 22 Q0 B 21 3-STATE B 20 D0 19 D1 18 D2 17 D3 16 CLOCK 15 WRITE ENABLE 14 READ 1A 13 READ 0A Functional Diagram WRITE ENABLE 15 DATA INPUTS D0 20 D1 19 D2 18 D3 17 3-STATE A 3 4 Q0 5 Q1 6 Q2 7 Q3 WORD A OUTPUT WRITE 0 8 WRITE 1 9 READ 1A 14 READ 0A 13 VDD = 24 VSS = 12 READ 1B 10 READ 0B 11 16 CLOCK 22 Q0 23 Q1 2 Q2 1 Q3 WORD B OUTPUT 21 3-STATE B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-25 File Number 3356 Specifications CD40108BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja Ceramic DIP and FRIT Package . . . . . 80oC/W θjc 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL CONDITIONS (NOTE 1) IDD VDD = 20V, VIN = VDD or GND Input Leakage Current VDD = 18V, VIN = VDD or GND IIL VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS 1 2 3 1 2 TEMPERATURE +25oC +125oC -55oC +25oC +125oC LIMITS MIN MAX UNITS - 10 µA - 1000 µA - 10 µA -100 - nA -1000 - nA Input Leakage Current VDD = 18V IIH VIN = VDD or GND VDD = 20 Output Voltage VDD = 18V VOL15 VDD = 15V, No Load 3 1 2 3 1, 2, 3 -55oC -100 - nA +25oC - 100 nA +125oC - 1000 nA -55oC - 100 nA +25oC, +125oC, -55oC - 50 mV Output Voltage Output Current (Sink) Output Current (Sink) VOH15 IOL5 IOL10 VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 0.53 - mA 1 +25oC 1.4 - mA Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA N Threshold Voltage P Threshold Voltage Functional Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage Tri-State Output Leakage VNTH VPTH F VIL VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V, VOH > 4.5V, VOL < 0.5V VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VIL VIH IOZL IOZH VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VDD = 20V VOUT = 0V VIN = VDD or GND VOUT = VDD VDD = 18V VDD = 20V VDD = 18V 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC -2.8 -0.7 V +25oC 0.7 2.8 V +25oC VOH > VOL < V +25oC VDD/2 VDD/2 +125oC -55oC +25oC, +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V +25oC, +125oC, -55oC - 4 V +25oC, +125oC, -55oC 11 - V +25oC +125oC -55oC +25oC +125oC -55oC -0.4 - µA -12 - µA -0.4 - µA - 0.4 µA - 12 µA - 0.4 µA NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit implemented. is 0.050V max. 2. Go/No Go test with limits applied to inputs. 7-26 Specifications CD40108BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Propagation Delay Clock TPHL1 VDD = 5V, VIN = VDD or GND or Write Enable to Q TPLH1 (Note 1, 2) Propagation Delay Read TPHL2 VDD = 5V, VIN = VDD or GND or Write Address to Q TPLH2 (Note 1, 2) Propagation Delay 3- TPZH VDD = 5V, VIN = VDD or GND State Disable Delay Time TPHZ (Note 2, 3) Propagation Delay 3- TPZL VDD = 5V, VIN = VDD or GND State Disable Delay Time TPLZ (Note 2, 3) Transition Time TTHL VDD = 5V, VIN = VDD or GND TTLH (Note 1, 2) Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND (Note 1, 2) GROUP A SUBGROUPS TEMPERATURE 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. LIMITS MIN MAX - 720 - 972 - 600 - 810 - 200 - 270 - 260 - 351 - 200 - 270 1.5 - 1.11 - UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL CONDITIONS IDD VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VDD = 5V, No Load VOL VDD = 10V, No Load VOH VDD = 5V, No Load VOH VDD = 10V, No Load IOL5 VDD = 5V, VOUT = 0.4V Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC LIMITS MIN MAX - 5 - 150 - 10 - 300 - 10 - 600 - 50 - 50 4.95 - 9.95 - 0.36 - 0.64 - 0.9 - 1.6 - 2.4 - 4.2 - - -0.36 - -0.64 - -1.15 - -2.0 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA 7-27 Specifications CD40108BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V Propagation Delay Clock or Write Enable to Q Propagation Delay Read or Write Address to Q Propagation Delay 3-State Disable Delay Time Propagation Delay 3-State Disable Delay Time Transition Time Maximum Clock Input Frequency Minimum Data Setup Time Data to Clock Minimum Data Setup Time Write Enable to Clock Minimum Data Setup Time Write Address to Clock Clock Rise and Fall Time Minimum Hold Time Data to Clock Hold Time Write Enable to Clock Write Address to Clock TPLH1 TPHL1 TPHL2 TPLH2 TPZH TPHZ TPZL TPLZ TTLH TTHL FCL TS TS TS TRCL TFCL TH TH TH VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 TEMPERATURE MIN +125oC - -55oC - +125oC - -55oC - +25oC, +125oC, - -55oC +25oC, +125oC, 7 -55oC +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC 3.5 +25oC 4.5 +25oC 0 +25oC 0 +25oC 0 +25oC 250 +25oC 100 +25oC 70 +25oC 250 +25oC 100 +25oC 70 +25oC - +25oC - +25oC - +25oC 220 +25oC 100 +25oC 80 +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX -0.9 -1.6 -2.4 -4.2 3 280 200 240 170 100 80 120 100 100 80 - 15 5 5 270 130 80 330 140 90 UNITS mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7-28 Specifications CD40108BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width Clock or Write Enable Minimum Clock Pulse Width Write Address Input Capacitance SYMBOL CONDITIONS TW VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V CIN Any Input NOTES 3 3 3 3 3 3 1, 2 TEMPERATURE MIN +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX 350 130 90 300 150 90 7.5 UNITS ns ns ns ns ns ns pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE MIN +25oC - +25oC -2.8 +25oC - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A 7-29 Specifications CD40108BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD TEST PRE-IRRAD POST-IRRAD 1 1, 7, 9 Table 4 READ AND RECORD PRE-IRRAD POST-IRRAD 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Static Burn-In 1 1, 2, 4 - 7, 22, 23 3, 8 - 12 24 (Note 1) Static Burn-In 2 1, 2, 4 - 7, 22, 23 2 3, 8 - 11, 13 - 21, (Note 1) 24 Dynamic Burn- - In (Note 1) 2 3, 15, 16, 21, 24 1, 2, 4 - 7, 22, 23 8, 11, 14, 19, 20 9, 10, 13, 17, 18 Irradiation 1, 2, 4 - 7, 22, 23 2 3, 8 - 11, 13 - 21, (Note 2) 24 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 30 CD40108BMS Block Diagram CL WE W0 W1 R0A R1A R0B R1B DEC DEC DEC ENABLE A D0 DATA D1 INPUT D2 D3 4X4 MEMORY Q0 A Q1 A Q2 A Q3 A Q0 B Q1 B Q2 B Q3 B WORD A OUTPUT WORD B OUTPUT FIGURE 1. TRUTH TABLE ENABLE B WRITE WRITE CLOCK ENABLE 1 1 S1 1 S1 X X X 1 0 WRITE 0 S2 S2 X 0 READ 1A S1 S1 X 0 READ 0A S2 S2 X 1 0 0 0 0 1 X X X X 1 0 X X X X X 1 = High Level 0 = Low Level S! and S2 refer to input states of either 1 or 0 READ 1B S1 S1 X 1 1 0 X READ ENABLE ENABLE 0B A B DN QnA QnB S2 1 1 1 1 1 S2 1 1 0 0 0 X 0 0 X Z Z 0 1 1 Dn to word Word 1 Word 2 0 out out 0 1 1 Word 0 Word 1 Word 2 not altered out out 1 1 1 X Word 2 Word 1 out out X 1 1 X NC NC X = Don’t Care Z = High Impedance Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-31 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) CD40108BMS Typical Performance Characteristics (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10V -15V 0 0 -5 -10 -15 -20 -25 -30 -35 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10V -15V 0 0 -5 -10 -15 FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 525 450 SUPPLY VOLTAGE (VDD) = 5V 375 AMBIENT TEMPERATURE (TA) = +25oC 200 300 150 SUPPLY VOLTAGE (VDD) = 5V 225 10V 100 150 10V 75 15V 50 15V 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CL OR WE TO Q) 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSISTION TIME AS A FUNCTION OF LOAD CAPACITANCE POWER DISSIPATION (PD) (µW) 106 8 6 4 2 105 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 2 104 8 6 4 2 103 8 6 4 2 102 1 10V 10V 5V CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 10 102 103 104 INPUT FREQUENCY (fI) (kHz) FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 7-32 FIGURE 9. 7-33 *CLOCK 16 *WRITE ENABLE 15 *W0 8 *W1 9 *D0 20 *D1 19 *D2 18 *D3 17 * 13 R0A C * 14 R1A C * 11 R0B * 10 R1B 3-STATE *A ENABLE 3 C p n C C p n C C p n C C p n C C p n C C p n C C p n C C p n C AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W AB QA D QB W *ALL INPUTS PROTECTED BY COS/MOS INPUT PROTECTION NETWORK 4 Q0A 5 Q1A 6 Q2A 7 Q3A 22 Q0B 23 Q1B 2 Q2B 1 Q3B 21 3-STATE *B ENABLE Schematic Diagram CD40108BMS Schematic Diagram (Continued) CD40108BMS D VDD W VSS p n p n A p n QA B p n QB ENABLE VDD INPUT OUTPUT VSS DETAIL OF MEMORY CELL DETAIL OF 3-STATE OUTPUTS FIGURE 9. (Continued) trCL CL tS(D) Dn WE tfCL tH(D) tW(CL) tH(WE) tS(WE) tH(WA) tS(WA) tW(WA) WA RA tPLH Qn tTLH tPHL tTHL tPHL FIGURE 10. TIMING DIAGRAM 0.1 µF VDD 500 µF ID CL 1 24 2 23 CL CL 3 22 4 21 5 20 CL 6 19 7 18 CL 8 17 CL 9 16 10 15 PULSE 11 14 GEN. 3 12 13 CL CL PULSE GEN. 2 PULSE GEN. 1 P.G. 1 P.G. 2 P.G. 3 Qn A, B tPLH tPHL tPLH (FI) REPETITIVE WAVEFORMS FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS 7-34 CD40108BMS 1 2 3 Q 4 5 1kΩ 6 TO ANY 7 OUTPUT 8 50pF 9 10 11 12 24 PULSE GEN. 2 23 P.G. 1 CL 22 21 20 19 D 18 17 16 PULSE GEN. 1 15 14 P.G. 2 ENABLE INPUT 50% tPLZ Q OUTPUTS tPHZ ENABLE 10% 90% VDD 50% VSS tPZL 90% VDD VOL VOH 10% VSS tPZH 13 TEST VOLTAGE CHAR AT D AT Q tPHZ tPZH VDD VDD VSS VSS tPLZ VSS VDD tPZL VSS VDD FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-35
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$(function(){ var appid = $(".select li a").data("channel"); $(".select li a").click(function(){ var appid = $(this).data("channel"); $('.select dt').html($(this).html()); $('#channel').val(appid); }) })