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4071 CMOS 四2输入端或门.pdf

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标    签: 4071CMOS四2输入端或门

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4071 CMOS 四2输入端或门.pdf

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CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate October 1987 Revised January 1999 CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS. Features s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 5V–10V–15V parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4071BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4071BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4081BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4081BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC CD4071B CD4081B Top View Top View © 1999 Fairchild Semiconductor Corporation DS005977.prf www.fairchildsemi.com CD4071BC • CD4081BC Schematic Diagrams CD4071B CD4081B 1/4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW *All inputs protected by standard CMOS protection circuit. 1/4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 CD4071BC • CD4081BC Absolute Maximum Ratings(Note 1) (Note 2) Voltage at Any Pin Power Dissipation (PD) Dual-In-Line Small Outline VDD Range Storage Temperature (TS) Lead Temperature (TL) (Soldering, 10 seconds) −0.5V to VDD +0.5V 700 mW 500 mW −0.5 VDC to +18 VDC −65°C to +150°C 260°C Recommended Operating Conditions Operating Range (VDD) Operating Temperature Range (TA) CD4071BC, CD4081BC 3 VDC to 15 VDC −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise specified. DC Electrical Characteristics (Note 2) CD4071BC/CD4081BC Symbol Parameter Conditions IDD Quiescent Device VDD = 5V Current VDD = 10V VDD = 15V VOL LOW Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA VDD = 15V VOH HIGH Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA VDD = 15V VIL LOW Level VDD = 5V, VO = 0.5V Input Voltage VDD = 10V, VO = 1.0V VDD = 15V, VO = 1.5V VIH HIGH Level VDD = 5V, VO = 4.5V Input Voltage VDD = 10V, VO = 9.0V VDD = 15V, VO = 13.5V IOL LOW Level Output VDD = 5V, VO = 0.4V Current VDD = 10V, VO = 0.5V (Note 3) VDD = 15V, VO = 1.5V IOH HIGH Level Output VDD = 5V, VO = 4.6V Current VDD = 10V, VO = 9.5V (Note 3) VDD = 15V, VO = 13.5V IIN Input Current VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 3: IOH and IOL are tested one output at a time. −40°C Min Max 1 2 4 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 −0.52 −1.3 −3.6 −0.30 0.30 Min 4.95 9.95 14.95 3.5 7.0 11.0 0.44 1.1 3.0 −0.44 −1.1 −3.0 +25°C Typ 0.004 0.005 0.006 0 0 0 5 10 15 2 4 6 3 6 9 0.88 2.25 8.8 −0.88 −2.25 −8.8 −10−5 10−5 Max 1 2 4 0.05 0.05 0.05 1.5 3.0 4.0 −0.30 0.30 +85°C Min Max 7.5 15 30 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 −0.36 −0.9 −2.4 −1.0 1.0 Units µA µA µA V V V V V V V V V V V V mA mA mA mA mA mA µA µA AC Electrical Characteristics (Note 4) CD4071BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C Symbol Parameter Conditions Typ Max tPHL Propagation Delay Time, VDD = 5V HIGH-to-LOW Level VDD = 10V VDD = 15V tPLH Propagation Delay Time, VDD = 5V LOW-to-HIGH Level VDD = 10V VDD = 15V tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V CIN Average Input Capacitance Any Input CPD Power Dissipation Capacity Any Gate Note 4: AC Parameters are guaranteed by DC correlated testing. 100 250 40 100 30 70 90 250 40 100 30 70 90 200 50 100 40 80 5 7.5 18 Units ns ns ns ns ns ns ns ns ns pF pF 3 www.fairchildsemi.com CD4071BC • CD4081BC AC Electrical Characteristics (Note 5) CD4081BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C Symbol Parameter Conditions Typ Max tPHL Propagation Delay Time, VDD = 5V HIGH-to-LOW Level VDD = 10V VDD = 15V tPLH Propagation Delay Time, VDD = 5V LOW-to-HIGH Level VDD = 10V VDD = 15V tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V CIN Average Input Capacitance Any Input CPD Power Dissipation Capacity Any Gate Note 5: AC Parameters are guaranteed by DC correlated testing. 100 250 40 100 30 70 120 250 50 100 35 70 90 200 50 100 40 80 5 7.5 18 Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Units ns ns ns ns ns ns ns ns ns pF pF Typical Transfer Characteristics Typical Transfer Characteristics www.fairchildsemi.com 4 CD4071BC • CD4081BC Typical Performance Characteristics (Continued) 5 www.fairchildsemi.com CD4071BC • CD4081BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 6 CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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