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4538 CMOS 双精密单稳多谐振荡器.pdf

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标签: 4538CMOS双精密单稳多谐振荡器

4538 CMOS 双精密单稳多谐振荡器.pdf

CD4538BC Dual Precision Monostable October 1987 Revised January 1999 CD4538BC Dual Precision Monostable General Description The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable, and the control inputs are internally latched. Two trigger inputs are provided to allow either rising or falling edge triggering. The reset inputs are active LOW and prevent triggering while active. Precise control of output pulse-width has been achieved using linear CMOS techniques. The pulse duration and accuracy are determined by external components RX and CX. The device does not allow the timing capacitor to discharge through the timing pin on power-down condition. For this reason, no external protection resistor is required in series with the timing pin. Input protection from static discharge is provided on all pins. Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VCC (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s New formula: PWOUT = RC (PW in seconds, R in Ohms, C in Farads) s ±1.0% pulse-width variation from part to part (typ.) s Wide pulse-width range: 1 µs to ∞ s Separate latched reset inputs s Symmetrical output sink and source capability s Low standby current: 5 nA (typ.) @ 5 VDC s Pin compatible to CD4528BC Ordering Code: Order Number Package Number Package Description CD4538BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4538BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body CD4538BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP and SOIC Top View Inputs Outputs Clear A B Q Q L X X L H X H X L H X H H X L ↑ L L H ↓ H H = HIGH Level L = LOW Level ↑ = Transition from LOW-to-HIGH ↓ = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant © 1999 Fairchild Semiconductor Corporation DS006000.prf CD4538BC Block Diagram RX and CX are External Components VDD = Pin 16 VSS = Pin 8 Logic Diagram FIGURE 1. 2 CD4538BC Theory of Operation FIGURE 2. Trigger Operation The block diagram of the CD4538BC is shown in Figure 1, with circuit operation following. As shown in Figure 1 and Figure 2, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD (while inputs B and CD are held to VDD) a valid trigger is recognized, which turns on comparator C1 and N-Channel transistor N1(1). At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from VDD to VSS (while input A is at VSS and input CD is at VDD)(2). It should be noted that in the quiescent state CX is fully charged to VDD, causing the current through resistor RX to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the CD4538BC is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input waveform. Retrigger Operation The CD4538BC is retriggered if a valid trigger occurs(3) followed by another valid trigger(4) before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated(4), the voltage at T2 will again drop to VREF1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. Reset Operation The CD4538BC may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on CD sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor Q1(5). When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the CD input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the CD input, the output pulse T can be made significantly shorter than the minimum pulse width specification. 3 CD4538BC FIGURE 3. Retriggerable Monostables Circuitry FIGURE 4. Non-Retriggerable Monostables Circuitry FIGURE 5. Connection of Unused Sections 4 CD4538BC Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) −0.5 to +18 VDC −0.5V to VDD + 0.5 VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) 3 to 15 VDC Input Voltage (VIN) 0 to VDD VDC Operating Temperature Range (TA) −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 2) Symbol Parameter Conditions IDD Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 3) IOH HIGH Level Output Current (Note 3) IIN Input Current, Pin 2 or 14 VDD = 5V VIH = VDD VDD = 10V VIL = VSS VDD = 15V All Outputs Open VDD = 5V |IO| < 1 µA VDD = 10V VIH = VDD, VIL = VSS VDD = 15V VDD = 5V |IO| < 1 µA VDD = 10V VIH = VDD, VIL = VSS VDD = 15V |IO| < 1 µA VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V |IO| < 1 µA VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VIH = VDD VDD = 10V, VO = 0.5V VIL = VSS VD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VIL = VSS VD = 15V, VO = 13.5V VDD = 15V, VIN = 0V or 15V IIN Input Current Other Inputs VDD = 15V, VIN = 0V or 15V Note 3: IOH and IOL are tested one output at a time. −40°C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 +25°C Min Typ 0.005 0.010 0.015 0 0 0 4.95 5 9.95 10 14.95 15 Max 20 40 80 0.05 0.05 0.05 +85°C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 2.25 1.5 1.5 3.0 4.50 3.0 3.0 4.0 6.75 4.0 4.0 3.5 3.5 2.75 3.5 7.0 7.0 5.50 7.0 11.0 11.0 8.25 11.0 0.52 0.44 0.88 0.36 1.3 1.1 2.25 0.9 3.6 3.0 8.8 2.4 −0.52 −0.44 −0.88 −0.36 −1.3 −1.1 −2.25 −0.9 −3.6 −3.0 −8.8 −2.4 ±0.02 ±10−5 ±0.05 ±0.5 ±0.3 ±10−5 ±0.3 ±1.0 Units µA µA µA V V V V V V V V V V V V mA mA mA mA mA mA µA µA 5 CD4538BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, and tr = tf = 20 ns unless otherwise specified Symbol Parameter Conditions Min Typ Max Units tTLH, tTHL Output Transition Time tPLH, tPHL Propagation Delay Time VDD = 5V VDD = 10V VDD = 15V Trigger Operation— A or B to Q or Q VDD = 5V VDD = 10V VDD = 15V Reset Operation— 100 200 ns 50 100 ns 40 80 ns 300 600 ns 150 300 ns 100 220 ns tWL, tWH tRR CIN Minimum Input Pulse Width A, B, or CD Minimum Retrigger Time Input Capacitance CD to Q or Q VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Pin 2 or 14 Other Inputs 250 500 ns 125 250 ns 95 190 ns 35 70 ns 30 60 ns 25 50 ns 0 ns 0 0 ns 0 ns 10 pF 5 7.5 pF PWOUT Output Pulse Width (Q or Q) (Note: For Typical Distribution, see Figure 6) Pulse Width Match between Circuits in the Same Package CX = 0.1 µF, RX = 100 kΩ Operating Conditions RX = 100 kΩ CX = 0.002 µF RX = 100 kΩ CX = 0.1 µF RX = 100 kΩ CX = 10.0 µF RX = 100 kΩ CX = 0.1 µF VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V 208 226 244 µs 211 230 248 µs 216 235 254 µs 8.83 9.60 10.37 ms 9.02 9.80 10.59 ms 9.20 10.00 10.80 ms 0.87 0.95 1.03 s 0.89 0.97 1.05 s 0.91 0.99 1.07 s ±1 % ±1 % ±1 % RX External Timing Resistance CX External Timing Capacitance Note 4: AC parameters are guaranteed by DC correlated testing. 5.0 (Note 5) kΩ 0 No Limit pF Note 5: The maximum usable resistance RX is a function of the leakage of the Capacitor CX, leakage of the CD4538BC, and leakage due to board layout, surface resistance, etc. 6 CD4538BC Typical Applications FIGURE 6. Typical Normalized Distribution of Units for Output Pulse Width FIGURE 9. Typical Pulse Width Error Versus Temperature FIGURE 7. Typical Pulse Width Variation as a Function of Supply Voltage VDD FIGURE 10. Typical Pulse Width Error Versus Temperature FIGURE 8. Typical Total Supply Current Versus Output Duty Cycle, RX = 100 kΩ, CL = 50 pF, CX = 100 pF, One Monostable Switching Only FIGURE 11. Typical Pulse Width Versus Timing RC Product 7 CD4538BC Test Circuits and Waveforms FIGURE 12. Switching Test Waveforms *CL = 50 pF Input Connections Characteristics tPLH, tPHL, tTLH, tTHL PWOUT, tWH, tWL tPLH, tPHL, tTLH, tTHL PWOUT, tWH, tWL tPLH(R), tPHL(R), tWH, tWL CD A VDD PG1 VDD VSS PG3 PG1 B VDD PG2 PG2 *Includes capacitance of probes, wiring, and fixture parasitic Note: Switching test waveforms for PG1, PG2, PG3 are shown in Figure 12. FIGURE 13. Switching Test Circuit 8 CD4538BC RX = RX′ = 100 kΩ CX = CX′ = 100 pF C1 = C2 = 0.1 µF Duty Cycle = 50% FIGURE 14. Power Dissipation Test Circuit and Waveforms 9 CD4538BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M16B 10 CD4538BC Dual Precision Monostable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.



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