pdf

德州仪器CC253x/41/40无线SoC用户指南

  • 1星
  • 日期: 2018-05-29
  • 大小: 2.03MB
  • 所需积分:1分
  • 下载次数:0
  • favicon收藏
  • rep举报
  • 分享
  • free评论
标签: CC2541

CC2541 是一款针对低能耗以及私有 2.4GHz 应用的功率优化的真正片载系统 (SoC) 解决方案。

CC253X

CC2541 是一款针对低能耗以及私有 2.4GHz 应用的功率优化的真正片载系统 (SoC) 解决方案。

CC2540

CC2540是一个真正的系统单晶片解决方案,结合德州仪器的协议栈、轮廓软体及应用支援, CC2540成为市场上最具有弹性及成本效益的单模式低功率蓝牙解决方案。

ZigBee

Zigbee是基于IEEE802.15.4标准的低功耗个域网协议。根据这个协议规定的技术是一种短距离、低功耗的无线通信技术。这一名称来源于蜜蜂的八字舞,由于蜜蜂(bee)是靠飞翔和“嗡嗡”(zig)地抖动翅膀的“舞蹈”来与同伴传递花粉所在方位信息,也就是说蜜蜂依靠这样的方式构成了群体中的通信网络。其特点是近距离、低复杂度、自组织、低功耗、低数据速率、低成本。主要适合用于自动控制和远程控制领域,可以嵌入各种设备。简而言之,ZigBee就是一种便宜的,低功耗的近距离无线组网通讯技术。

TI培训

TI教室是一个关于TI技术和产品的在线培训中心,是德州仪器(TI)和EEWORLD联合推出的在线培训项目,旨在让工程师由浅入深、从理论到实践学习TI的嵌入式、模拟和无线产品相关知识。TI教室不但能看视频,还能评论、考试,并配有相关资料和代码,帮助您系统学习相关知识,成为优秀的工程师。

" class="eew_tag">德州仪器

德州仪器(Texas Instruments),简称TI,是全球领先的半导体公司,为现实世界的信号处理提供创新的数字信号处理(DSP)及模拟器件技术。除半导体业务外,还提供包括传感与控制、教育产品和数字光源处理解决方案。TI总部位于美国德克萨斯州的达拉斯,并在25多个国家设有制造、设计或销售机构。

TI培训

TI教室是一个关于TI技术和产品的在线培训中心,是德州仪器(TI)和EEWORLD联合推出的在线培训项目,旨在让工程师由浅入深、从理论到实践学习TI的嵌入式、模拟和无线产品相关知识。TI教室不但能看视频,还能评论、考试,并配有相关资料和代码,帮助您系统学习相关知识,成为优秀的工程师。

  The CC253x System-on-Chip solution for 2.4 GHz is suitable for a wide range of applications. These can easily be built on top of the IEEE 802.15.4 based standard protocols (RemoTI™ network protocol, TIMAC nsoftware, and Z-Stack™ software for ZigBee®compliant solutions) or on top of the proprietary SimpliciTI™ network protocol. The usage is, however, not limited to these protocols alone. The CC253x family is, for example, also suitable for 6LoWPAN and Wireless HART implementations.

CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications A CC2540/41 System-on-Chip Solution for 2.4- GHz Bluetooth® low energy Applications User's Guide Literature Number: SWRU191E April 2009–Revised January 2014 Contents 2.3 Preface ...................................................................................................................................... 14 Introduction ...................................................................................................................... 17 1 Overview .................................................................................................................... 18 1.1 1.1.1 CPU and Memory ................................................................................................ 21 1.1.2 Clocks and Power Management ................................................................................ 21 1.1.3 Peripherals ........................................................................................................ 21 1.1.4 Radio ............................................................................................................... 23 Applications ................................................................................................................ 23 1.2 8051 CPU .......................................................................................................................... 24 8051 CPU Introduction .................................................................................................... 25 2.1 Memory ..................................................................................................................... 25 2.2 2.2.1 Memory Map ...................................................................................................... 25 2.2.2 CPU Memory Space ............................................................................................. 27 2.2.3 Physical Memory ................................................................................................. 28 2.2.4 XDATA Memory Access ......................................................................................... 33 2.2.5 Memory Arbiter ................................................................................................... 33 CPU Registers ............................................................................................................. 34 2.3.1 Data Pointers ...................................................................................................... 34 2.3.2 Registers R0–R7 ................................................................................................. 35 2.3.3 Program Status Word ............................................................................................ 35 2.3.4 Accumulator ....................................................................................................... 36 2.3.5 B Register ......................................................................................................... 36 2.3.6 Stack Pointer ...................................................................................................... 36 Instruction Set Summary ................................................................................................. 36 Interrupts .................................................................................................................... 40 2.5.1 Interrupt Masking ................................................................................................. 41 2.5.2 Interrupt Processing .............................................................................................. 45 2.5.3 Interrupt Priority ................................................................................................... 47 Debug Interface ................................................................................................................. 50 Debug Mode ............................................................................................................... 51 3.1 Debug Communication ................................................................................................... 51 3.2 Debug Commands ........................................................................................................ 53 3.3 3.3.1 Debug Configuration ............................................................................................. 55 3.3.2 Debug Status ...................................................................................................... 55 3.3.3 Hardware Breakpoints ........................................................................................... 56 Flash Programming ....................................................................................................... 57 3.4.1 Lock Bits ........................................................................................................... 57 Debug Interface and Power Modes ..................................................................................... 57 3.5 Registers .................................................................................................................... 59 3.6 Power Management and Clocks .......................................................................................... 60 Power Management Introduction ........................................................................................ 61 4.1 4.1.1 Active and Idle Modes ........................................................................................... 62 4.1.2 PM1 ................................................................................................................ 62 4.1.3 PM2 ................................................................................................................ 62 2.4 2.5 3.4 2 3 4 2 Contents Copyright © 2009–2014, Texas Instruments Incorporated SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback www.ti.com 6.3 4.2 4.3 4.4 4.1.4 PM3 ................................................................................................................ 62 Power-Management Control ............................................................................................. 62 Power-Management Registers .......................................................................................... 63 Oscillators and Clocks .................................................................................................... 66 4.4.1 Oscillators ......................................................................................................... 66 4.4.2 System Clock ..................................................................................................... 66 4.4.3 32-kHz Oscillators ................................................................................................ 67 4.4.4 Oscillator and Clock Registers .................................................................................. 67 Timer Tick Generation .................................................................................................... 69 4.5 Data Retention ............................................................................................................. 69 4.6 Reset ............................................................................................................................... 70 Power-On Reset and Brownout Detector .............................................................................. 71 5.1 Clock-Loss Detector ....................................................................................................... 71 5.2 Flash Controller ................................................................................................................ 72 Flash Memory Organization .............................................................................................. 73 6.1 Flash Write ................................................................................................................. 73 6.2 6.2.1 Flash-Write Procedure ........................................................................................... 73 6.2.2 Writing Multiple Times to a Word ............................................................................... 74 6.2.3 DMA Flash Write ................................................................................................. 74 6.2.4 CPU Flash Write .................................................................................................. 75 Flash Page Erase ......................................................................................................... 75 6.3.1 Performing Flash Erase From Flash Memory ................................................................ 76 6.3.2 Different Flash Page Size on CC2533 ......................................................................... 76 Flash DMA Trigger ........................................................................................................ 76 6.4 Flash Controller Registers ................................................................................................ 76 6.5 I/O Ports ........................................................................................................................... 78 Unused I/O Pins ........................................................................................................... 79 7.1 Low I/O Supply Voltage ................................................................................................... 79 7.2 General-Purpose I/O ...................................................................................................... 79 7.3 General-Purpose I/O Interrupts .......................................................................................... 79 7.4 General-Purpose I/O DMA ............................................................................................... 80 7.5 Peripheral I/O .............................................................................................................. 80 7.6 7.6.1 Timer 1 ............................................................................................................. 81 7.6.2 Timer 3 ............................................................................................................. 81 7.6.3 Timer 4 ............................................................................................................. 82 7.6.4 USART 0 ........................................................................................................... 82 7.6.5 USART 1 ........................................................................................................... 82 7.6.6 ADC ................................................................................................................ 83 7.6.7 Operational Amplifier and Analog Comparator ............................................................... 83 Debug Interface ............................................................................................................ 83 7.7 32-kHz XOSC Input ....................................................................................................... 83 7.8 Radio Test Output Signals ............................................................................................... 84 7.9 Power-Down Signal MUX (PMUX) ...................................................................................... 84 7.10 I/O Registers ............................................................................................................... 84 7.11 DMA Controller ................................................................................................................. 92 DMA Operation ............................................................................................................ 93 8.1 DMA Configuration Parameters ......................................................................................... 95 8.2 8.2.1 Source Address ................................................................................................... 95 8.2.2 Destination Address .............................................................................................. 95 8.2.3 Transfer Count .................................................................................................... 95 8.2.4 VLEN Setting ...................................................................................................... 96 8.2.5 Trigger Event ...................................................................................................... 96 5 6 7 8 SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Contents 3 www.ti.com 8.2.6 Source and Destination Increment ............................................................................. 96 8.2.7 DMA Transfer Mode .............................................................................................. 97 8.2.8 DMA Priority ....................................................................................................... 97 8.2.9 Byte or Word Transfers .......................................................................................... 97 8.2.10 Interrupt Mask .................................................................................................... 97 8.2.11 Mode 8 Setting ................................................................................................... 97 DMA Configuration Setup ................................................................................................ 97 8.3 Stopping DMA Transfers ................................................................................................. 98 8.4 DMA Interrupts ............................................................................................................. 98 8.5 DMA Configuration-Data Structure ...................................................................................... 98 8.6 DMA Memory Access ..................................................................................................... 98 8.7 DMA Registers ........................................................................................................... 101 8.8 Timer 1 (16-Bit Timer) ....................................................................................................... 103 16-Bit Counter ............................................................................................................ 104 9.1 Timer 1 Operation ........................................................................................................ 104 9.2 Free-Running Mode ..................................................................................................... 104 9.3 Modulo Mode ............................................................................................................. 105 9.4 Up-and-Down Mode ..................................................................................................... 105 9.5 Channel-Mode Control .................................................................................................. 105 9.6 Input Capture Mode ..................................................................................................... 106 9.7 Output Compare Mode .................................................................................................. 106 9.8 IR Signal Generation and Learning .................................................................................... 111 9.9 9.9.1 Introduction ...................................................................................................... 111 9.9.2 Modulated Codes ............................................................................................... 111 9.9.3 Non-Modulated Codes ......................................................................................... 112 9.9.4 Learning .......................................................................................................... 113 9.9.5 Other Considerations ........................................................................................... 113 Timer 1 Interrupts ........................................................................................................ 113 9.10 Timer 1 DMA Triggers ................................................................................................... 113 9.11 Timer 1 Registers ........................................................................................................ 114 9.12 Accessing Timer 1 Registers as Array ................................................................................ 119 9.13 Timer 3 and Timer 4 (8-Bit Timers) ..................................................................................... 120 8-Bit Timer Counter ...................................................................................................... 121 10.1 Timer 3 and Timer 4 Mode Control .................................................................................... 121 10.2 10.2.1 Free-Running Mode ........................................................................................... 121 10.2.2 Down Mode ..................................................................................................... 121 10.2.3 Modulo Mode ................................................................................................... 121 10.2.4 Up-and-Down Mode ........................................................................................... 121 10.3 Channel Mode Control .................................................................................................. 121 Input Capture Mode ..................................................................................................... 122 10.4 10.5 Output Compare Mode .................................................................................................. 122 Timer 3 and Timer 4 Interrupts ......................................................................................... 122 10.6 Timer 3 and Timer 4 DMA Triggers ................................................................................... 123 10.7 Timer 3 and Timer 4 Registers ......................................................................................... 123 10.8 Sleep Timer ..................................................................................................................... 128 11.1 General .................................................................................................................... 129 Timer Compare ........................................................................................................... 129 11.2 Timer Capture ............................................................................................................ 129 11.3 Sleep Timer Registers ................................................................................................... 130 11.4 ADC ............................................................................................................................... 132 ADC Introduction ......................................................................................................... 133 12.1 ADC Operation ........................................................................................................... 133 12.2 9 10 11 12 4 Contents Copyright © 2009–2014, Texas Instruments Incorporated SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback www.ti.com 13 14 15 12.2.1 ADC Inputs ...................................................................................................... 133 12.2.2 ADC Conversion Sequences ................................................................................. 134 12.2.3 Single ADC Conversion ....................................................................................... 134 12.2.4 ADC Operating Modes ........................................................................................ 134 12.2.5 ADC Conversion Results ..................................................................................... 135 12.2.6 ADC Reference Voltage ...................................................................................... 135 12.2.7 ADC Conversion Timing ...................................................................................... 135 12.2.8 ADC Interrupts ................................................................................................. 135 12.2.9 ADC DMA Triggers ............................................................................................ 135 12.2.10 ADC Registers ................................................................................................ 136 Battery Monitor ................................................................................................................ 139 Functionality and Usage of the Battery Monitor ...................................................................... 140 13.1 13.2 Using the Battery Monitor for Temperature Monitoring ............................................................. 140 Battery Monitor Registers ............................................................................................... 141 13.3 Random-Number Generator .............................................................................................. 143 Introduction ............................................................................................................... 144 14.1 14.2 Random-Number-Generator Operation ............................................................................... 144 14.2.1 Pseudorandom Sequence Generation ...................................................................... 144 14.2.2 Seeding ......................................................................................................... 144 14.2.3 CRC16 ........................................................................................................... 144 14.3 Random-Number-Generator Registers ................................................................................ 145 AES Coprocessor ............................................................................................................ 146 AES Operation ........................................................................................................... 147 15.1 Key and IV ................................................................................................................ 147 15.2 Padding of Input Data ................................................................................................... 147 15.3 Interface to CPU ......................................................................................................... 147 15.4 15.5 Modes of Operation ...................................................................................................... 147 15.6 CBC-MAC ................................................................................................................. 147 15.7 CCM Mode ................................................................................................................ 148 AES Interrupts ............................................................................................................ 150 15.8 AES DMA Triggers ....................................................................................................... 150 15.9 15.10 AES Registers ............................................................................................................ 150 16 Watchdog Timer .............................................................................................................. 152 16.1 Watchdog Mode .......................................................................................................... 153 Timer Mode ............................................................................................................... 153 16.2 16.3 Watchdog Timer Register ............................................................................................... 153 USART ............................................................................................................................ 155 17.1 UART Mode ............................................................................................................... 156 17.1.1 UART Transmit ................................................................................................. 156 17.1.2 UART Receive ................................................................................................. 156 17.1.3 UART Hardware Flow Control ................................................................................ 156 17.1.4 UART Character Format ...................................................................................... 157 SPI Mode .................................................................................................................. 157 17.2.1 SPI Master Operation ......................................................................................... 157 17.2.2 SPI Slave Operation ........................................................................................... 158 SSN Slave-Select Pin ................................................................................................... 158 17.3 Baud-Rate Generation .................................................................................................. 158 17.4 17.5 USART Flushing ......................................................................................................... 159 17.6 USART Interrupts ........................................................................................................ 159 17.7 USART DMA Triggers ................................................................................................... 159 17.8 USART Registers ........................................................................................................ 159 Operational Amplifier ....................................................................................................... 164 17.2 17 18 SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Contents 5
更多简介内容

推荐帖子

评论

登录/注册

意见反馈

求资源

回顶部

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版 版权声明

北京市海淀区知春路23号集成电路设计园量子银座1305 电话:(010)82350740 邮编:100191

电子工程世界版权所有 京ICP证060456号 京ICP备10001474号 电信业务审批[2006]字第258号函 京公海网安备110108001534 Copyright © 2005-2020 EEWORLD.com.cn, Inc. All rights reserved
$(function(){ var appid = $(".select li a").data("channel"); $(".select li a").click(function(){ var appid = $(this).data("channel"); $('.select dt').html($(this).html()); $('#channel').val(appid); }) })