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SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1961 Advance Information 675KB Embedded Display SRAM LCD Display Controller 2This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1961 Rev 1.4 P 1/90 Apr 2012 Copyright © 2012 Solomon Systech Limited Appendix: IC Revision history of SSD1961 Specification Version 0.10 27-Mar-08 0.20 17-Jul-08 0.30 09-Sep-08 0.40 21-Nov-08 0.50 08-Dec-08 1.0 07-May-09 1.1 31-May-10 1.2 11-Nov-10 1st Release Change Items 1. Added Table 6-5. 2. Updated Table 12-1. 3. VSSIO and VSSD are tied together and renamed as VSS. Modified Figure 5-1, Table 5-1 and Table 6-4. 4. Updated package information in Section 13.4. 5. Added Section 13.1. 1. Added Section 11 and 11.1. 2. Updated Figure 13-1, Figure 13-2 and Figure 13-3. 1. Added command descriptions in section 9 2. Added application circuit in section 13.4 3. Added SSD1961G40R part number 4. Added Tape & Reel drawing in section 15 5. Revised the VSS pin # (D5 and E5) in Table 6-4 6. Revised the Tape & Reel drawing in section 15 7. Updated maximum input clock frequency in Table 13-2 8. Updated 6-bit serial RGB in Table 6-5 9. Updated 9-bit interface in Table 7-1 1. Changed the set_pll_mnk to set_pll_mn in section 7.2 2. Change register name in section 8 3. Removed ABC 4. Revised description for REG 0x00, 0x01, 0x0C, 0x0D, 0x0E, 0x10, 0x11, 0x21, 0x26, 0x28, 0x2A, 0x2B, 0x2C, 0x2E, 0x33, 0x34, 0x35, 0x36, 0x37, 0x3A, 0x3C, 0x3E, 0x44, 0x45, 0xA1, 0xB0, 0xB1, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBE, 0xBF, 0xD0, 0xD1, 0xD4, 0xE5. 5. Added max VIH in Table 12-1 6. Added Table 9-1 7. Added Table 11-1 8. Revised Figure 9-19 9. Revised Figure 14-2 10. Revised Figure 13-5 11. Corrected typo for Table 7-2 12. Revised test condition for 12 and 13 1. Changed status to Advance Information 2. Update min/max rating of VDDD and VDDPLL in Table 11-1 3. Added serial RGB interface timing in Section 13.4 4. Revised Section 13.2 5. Added 12 bit in Table 7-1 6. Removed TTL interface 7. Changed the serial TFT interface from 6 bit to 8 bit 8. Revised section 7.1.5 9. Change the title of section 7.2 10. Revised command description in section 8. 11. Removed the command 0x0C and 0x3A 12. Added figures in section 13.4 13. Revised MCU Interface Timing in section 13.2 14. Revised figures in section 13.3 15. Revise Table 6-1 1. Updated Table 7-1 2. Revised section 9.72 3. Add table 13-7 1. Update Section 7.2 reset timing 2. Correct Section 13.4 the serial RGB timing 3. Correct Table 6.1-6.5 Pin Mapping -> Pin description Effective Date 02-Apr-08 28-Jul-08 10-Sep-08 24-Nov-08 10-Dec-08 18-May-09 15-Jul-10 07-Dec-10 Solomon Systech Apr 2012 P 2/90 Rev 1.4 SSD1961 1.3 21-Jul-11 1. Update Section 9.45 SET_PWM_CONF Update Section 9.30 SET_TEAR_SCANLINE 1.4 1. Update Table 13-5 and 13-6 (tPWCSH and tPWCSL typo) 16-Apr-12 25-Jul-11 25-Apr-12 SSD1961 Rev 1.4 P 3/90 Apr 2012 Solomon Systech CONTENTS 1 GENERAL DESCRIPTION ....................................................................................................... 9 2 FEATURES................................................................................................................................... 9 3 ORDERING INFORMATION ................................................................................................... 9 4 BLOCK DIAGRAM .................................................................................................................. 10 5 PIN ARRANGEMENT.............................................................................................................. 11 5.1 64 BALLS TFBGA ...............................................................................................................................................11 6 PIN DESCRIPTIONS ................................................................................................................ 12 7 FUNCTIONAL BLOCK DESCRIPTIONS............................................................................. 14 7.1 MCU INTERFACE.................................................................................................................................................14 7.1.1 6800 Mode ..................................................................................................................................................14 7.1.2 8080 Mode ..................................................................................................................................................14 7.1.3 Register Pin Mapping .................................................................................................................................14 7.1.4 Pixel Data Format ......................................................................................................................................14 7.1.5 Tearing Effect Signal (TE) ..........................................................................................................................15 7.2 SYSTEM CLOCK GENERATION .............................................................................................................................15 7.3 FRAME BUFFER....................................................................................................................................................16 7.4 SYSTEM CLOCK AND RESET MANAGER ...............................................................................................................16 7.5 LCD CONTROLLER ..............................................................................................................................................17 7.5.1 Display Format ...........................................................................................................................................17 7.5.2 General Purpose Input/Output (GPIO) ......................................................................................................17 8 COMMAND TABLE ................................................................................................................. 18 9 COMMAND DESCRIPTIONS................................................................................................. 21 9.1 NOP......................................................................................................................................................................21 9.2 SOFT_RESET.........................................................................................................................................................21 9.3 GET_POWER_MODE..............................................................................................................................................21 9.4 GET_ADDRESS_MODE ..........................................................................................................................................22 9.5 GET_DISPLAY_MODE ...........................................................................................................................................22 9.6 GET_TEAR_EFFECT_STATUS ................................................................................................................................23 9.7 ENTER_SLEEP_MODE ...........................................................................................................................................24 9.8 EXIT_SLEEP_MODE ..............................................................................................................................................24 9.9 ENTER_PARTIAL_MODE .......................................................................................................................................24 9.10 ENTER_NORMAL_MODE .......................................................................................................................................24 9.11 EXIT_INVERT_MODE ............................................................................................................................................25 9.12 ENTER_INVERT_MODE .........................................................................................................................................25 9.13 SET_GAMMA_CURVE ...........................................................................................................................................26 9.14 SET_DISPLAY_OFF ...............................................................................................................................................26 9.15 SET_DISPLAY_ON.................................................................................................................................................26 9.16 SET_COLUMN_ADDRESS ......................................................................................................................................27 9.17 SET_PAGE_ADDRESS............................................................................................................................................27 9.18 WRITE_MEMORY_START......................................................................................................................................28 9.19 READ_MEMORY_START .......................................................................................................................................29 9.20 SET_PARTIAL_AREA.............................................................................................................................................29 9.21 SET_SCROLL_AREA..............................................................................................................................................31 9.22 SET_TEAR_OFF ....................................................................................................................................................33 9.23 SET_TEAR_ON......................................................................................................................................................33 9.24 SET_ADDRESS_MODE...........................................................................................................................................33 9.25 SET_SCROLL_START ............................................................................................................................................36 Solomon Systech Apr 2012 P 4/90 Rev 1.4 SSD1961 9.26 EXIT_IDLE_MODE ................................................................................................................................................37 9.27 ENTER_IDLE_MODE .............................................................................................................................................37 9.28 WRITE_MEMORY_CONTINUE................................................................................................................................38 9.29 READ_MEMORY_CONTINUE .................................................................................................................................39 9.30 SET_TEAR_SCANLINE...........................................................................................................................................40 9.31 GET_SCANLINE ....................................................................................................................................................40 9.32 READ_DDB...........................................................................................................................................................41 9.33 SET_LCD_MODE ...................................................................................................................................................41 9.34 GET_LCD_MODE ..................................................................................................................................................43 9.35 SET_HORI_PERIOD ...............................................................................................................................................44 9.36 GET_HORI_PERIOD...............................................................................................................................................44 9.37 SET_VERT_PERIOD...............................................................................................................................................45 9.38 GET_VERT_PERIOD ..............................................................................................................................................46 9.39 SET_GPIO_CONF...................................................................................................................................................47 9.40 GET_GPIO_CONF ..................................................................................................................................................48 9.41 SET_GPIO_VALUE ................................................................................................................................................49 9.42 GET_GPIO_STATUS...............................................................................................................................................49 9.43 SET_POST_PROC...................................................................................................................................................50 9.44 GET_POST_PROC ..................................................................................................................................................50 9.45 SET_PWM_CONF...................................................................................................................................................51 9.46 GET_PWM_CONF ..................................................................................................................................................52 9.47 SET_LCD_GEN0....................................................................................................................................................54 9.48 GET_LCD_GEN0 ...................................................................................................................................................55 9.49 SET_LCD_GEN1....................................................................................................................................................56 9.50 GET_LCD_GEN1 ...................................................................................................................................................57 9.51 SET_LCD_GEN2....................................................................................................................................................58 9.52 GET_LCD_GEN2 ...................................................................................................................................................59 9.53 SET_LCD_GEN3....................................................................................................................................................60 9.54 GET_LCD_GEN3 ...................................................................................................................................................61 9.55 SET_GPIO0_ROP ...................................................................................................................................................62 9.56 GET_GPIO0_ROP...................................................................................................................................................62 9.57 SET_GPIO1_ROP ...................................................................................................................................................63 9.58 GET_GPIO1_ROP...................................................................................................................................................64 9.59 SET_GPIO2_ROP ...................................................................................................................................................64 9.60 GET_GPIO2_ROP...................................................................................................................................................65 9.61 SET_GPIO3_ROP ...................................................................................................................................................66 9.62 GET_GPIO3_ROP...................................................................................................................................................66 9.63 SET_DBC_CONF....................................................................................................................................................67 9.64 GET_DBC_CONF ...................................................................................................................................................68 9.65 SET_DBC_TH........................................................................................................................................................69 9.66 GET_DBC_TH .......................................................................................................................................................70 9.67 SET_PLL ...............................................................................................................................................................70 9.68 SET_PLL_MN........................................................................................................................................................71 9.69 GET_PLL_MN .......................................................................................................................................................72 9.70 GET_PLL_STATUS ................................................................................................................................................72 9.71 SET_DEEP_SLEEP .................................................................................................................................................72 9.72 SET_LSHIFT_FREQ................................................................................................................................................73 9.73 GET_LSHIFT_FREQ ...............................................................................................................................................73 9.74 SET_PIXEL_DATA_INTERFACE .............................................................................................................................75 9.75 GET_PIXEL_DATA_INTERFACE.............................................................................................................................75 10 MAXIMUM RATINGS.......................................................................................................... 76 11 RECOMMENDED OPERATING CONDITIONS ............................................................. 76 11.1 POWER-UP SEQUENCE ..........................................................................................................................................76 12 DC CHARACTERISTICS..................................................................................................... 77 13 AC CHARACTERISTICS..................................................................................................... 77 SSD1961 Rev 1.4 P 5/90 Apr 2012 Solomon Systech 13.1 CLOCK TIMING ....................................................................................................................................................77 13.2 MCU INTERFACE TIMING ....................................................................................................................................78 13.2.1 Parallel 6800-series Interface Timing ........................................................................................................78 13.2.2 Parallel 8080-series Interface Timing ........................................................................................................80 13.3 PARALLEL LCD INTERFACE TIMING....................................................................................................................82 13.4 SERIAL RGB INTERFACE TIMING ........................................................................................................................83 14 APPLICATION EXAMPLE.................................................................................................. 86 15 PACKAGE INFORMATION................................................................................................ 88 15.1 PACKAGE MECHANICAL DRAWING FOR TFBGA.................................................................................................88 15.2 TAPE & REEL DRAWING FOR TFBGA .................................................................................................................89 Solomon Systech Apr 2012 P 6/90 Rev 1.4 SSD1961 TABLES TABLE 3-1: ORDERING INFORMATION ...................................................................................................................................9 TABLE 5-1: TFBGA PIN ASSIGNMENT TABLE.....................................................................................................................11 TABLE 6-1: MCU INTERFACE PIN DESCRIPTION .................................................................................................................12 TABLE 6-2: LCD INTERFACE PIN DESCRIPTION...................................................................................................................12 TABLE 6-3: CONTROL SIGNAL PIN DESCRIPTION.................................................................................................................13 TABLE 6-4: POWER PIN DESCRIPTION.................................................................................................................................13 TABLE 6-5: LCD INTERFACE PIN MAPPING.........................................................................................................................13 TABLE 7-1: PIXEL DATA FORMAT .......................................................................................................................................14 TABLE 7-2: FRAME BUFFER SETTINGS REGARDING TO SET_ADDRESS_MODE COMMAND 0X36 ...........................................16 TABLE 9-1: ENTER IDLE MODE MEMORY CONTENT VS DISPLAY COLOR ..............................................................................38 TABLE 10-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) ...................................................................................76 TABLE 11-1: RECOMMENDED OPERATING CONDITION........................................................................................................76 TABLE 12-1: DC CHARACTERISTICS....................................................................................................................................77 TABLE 13-1: CLOCK INPUT REQUIREMENTS FOR CLK (PLL-BYPASS) ................................................................................77 TABLE 13-2: CLOCK INPUT REQUIREMENTS FOR CLK (PLL-ENABLED)..............................................................................77 TABLE 13-3: CLOCK INPUT REQUIREMENTS FOR CRYSTAL OSCILLATOR XTAL (PLL-ENABLED) .......................................77 TABLE 13-4: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE CS# AS CLOCK)...................................78 TABLE 13-5: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE E AS CLOCK) .......................................79 TABLE 13-6: PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS.....................................................................80 TABLE 13-7: QUICK REFERENCE TABLE FOR LCD PARAMETER SETTING .............................................................................85 SSD1961 Rev 1.4 P 7/90 Apr 2012 Solomon Systech FIGURES FIGURE 4-1: SSD1961 BLOCK DIAGRAM ............................................................................................................................10 FIGURE 5-1: PINOUT DIAGRAM – 64 BALLS TFBGA (TOP VIEW) ........................................................................................11 FIGURE 7-1: RELATIONSHIP BETWEEN TEARING EFFECT SIGNAL AND MCU MEMORY WRITING........................................15 FIGURE 7-2: CLOCK CONTROL DIAGRAM ............................................................................................................................16 FIGURE 7-3: STATE DIAGRAM OF SSD1961 ........................................................................................................................17 FIGURE 9-1: EXIT INVERT MODE EXAMPLE..........................................................................................................................25 FIGURE 9-2: ENTER INVERT MODE EXAMPLE.......................................................................................................................26 FIGURE 9-3: SET COLUMN ADDRESS EXAMPLE ...................................................................................................................27 FIGURE 9-4: SET PAGE ADDRESS EXAMPLE .........................................................................................................................28 FIGURE 9-5: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN END ROW > START ROW..................30 FIGURE 9-6: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN END ROW > START ROW..................30 FIGURE 9-7: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN START ROW > END ROW..................30 FIGURE 9-8: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN START ROW > END ROW..................31 FIGURE 9-9: SET SCROLL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0.....................................................................32 FIGURE 9-10: SET SCROLL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1...................................................................32 FIGURE 9-11: A[7] PAGE ADDRESS ORDER .........................................................................................................................34 FIGURE 9-12: A[6] COLUMN ADDRESS ORDER....................................................................................................................34 FIGURE 9-13: A[5] PAGE / COLUMN ADDRESS ORDER ........................................................................................................34 FIGURE 9-14: A[3] RGB ORDER..........................................................................................................................................35 FIGURE 9-15: A[1] FLIP HORIZONTAL .................................................................................................................................35 FIGURE 9-16: A[0] FLIP VERTICAL ......................................................................................................................................36 FIGURE 9-17: SET SCROLL START WITH SET_ADDRESS_MODE (0X36) A[4] = 0..................................................................36 FIGURE 9-18: SET SCROLL START WITH SET_ADDRESS_MODE (0X36) A[4] = 1..................................................................37 FIGURE 9-19: PWM SIGNAL ................................................................................................................................................51 FIGURE 11-1: POWER-UP SEQUENCE ...................................................................................................................................76 FIGURE 13-1: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE CS# AS CLOCK)...............................................78 FIGURE 13-2: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE E AS CLOCK) ...................................................79 FIGURE 13-3: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (WRITE CYCLE) .......................................................80 FIGURE 13-4: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (READ CYCLE).........................................................81 FIGURE 13-5: GENERIC TFT PANEL TIMING........................................................................................................................82 FIGURE 13-6: SERIAL RGB INTERFACE TIMING (WITHOUT DUMMY MODE).........................................................................83 FIGURE 13-7: SERIAL RGB INTERFACE TIMING (WITH DUMMY MODE) ...............................................................................84 FIGURE 14-1: APPLICATION CIRCUIT FOR SSD1961 (WITH DIRECT CLOCK INPUT) .............................................................86 FIGURE 14-2: APPLICATION CIRCUIT FOR SSD1961 (WITH CRYSTAL OSCILLATOR INPUT) ..................................................87 Solomon Systech Apr 2012 P 8/90 Rev 1.4 SSD1961 1 GENERAL DESCRIPTION SSD1961 is a display controller of 5,529,600 bit frame buffer to support up to 640 x 480 x 18bit graphics content. It also equips parallel MCU interfaces in different bus width to receive graphics data and command from MCU. Its display interface supports common RAM-less LCD driver of color depth up to 18 bit-perpixel. 2 FEATURES • Display feature − 675kbyte (5,529,600bit) built-in frame buffer. Support up to 640 x 480 at 18bpp display − Support TFT 18 bit generic RGB interface panel − Support 8-bit serial RGB interface − Hardware rotation of 0, 90, 180, 270 degree − Hardware display mirroring − Hardware windowing − Programmable brightness, contrast and saturation control − Dynamic Backlight Control (DBC) via PWM signal • MCU connectivity − 8/9/16/18-bit MCU interface − Tearing effect signal • I/O Connectivity − 4 GPIO pins • Built-in clock generator • Deep sleep mode for power saving • 64 pin BGA package • Core supply power (VDDPLL and VDDD): 1.2V±0.1V • I/O supply power (VDDIO): 1.65V to 3.6V • LCD interface supply power (VDDLCD): 1.65V to 3.6V 3 ORDERING INFORMATION Table 3-1: Ordering Information Ordering Part Number Package Form SSD1961G40 TFBGA-64 (Tray) SSD1961G40R TFBGA-64 (Tape & Reel) SSD1961 Rev 1.4 P 9/90 Apr 2012 Solomon Systech 4 BLOCK DIAGRAM Figure 4-1: SSD1961 Block Diagram Solomon Systech Apr 2012 P 10/90 Rev 1.4 SSD1961 5 PIN ARRANGEMENT 5.1 64 Balls TFBGA Figure 5-1: Pinout Diagram – 64 balls TFBGA (Top view) Pin # A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 Signal Name VDDLCD LDATA16 GAMAS1 TE LSHIFT GPIO3 VSSPLL VDDPLL LDATA15 LDATA14 GAMAS0 PWM LLINE GPIO2 GPIO0 XTAL_OUT Table 5-1: TFBGA Pin Assignment Table Pin # C1 C2 C3 C4 C5 C6 C7 C8 D1 D2 D3 D4 D5 D6 D7 D8 Signal Name LDATA13 LDATA12 LDATA11 LDATA10 LDEN LFRAME GPIO1 XTAL_IN LDATA9 LDATA8 LDATA7 LDATA6 VSS VDDD D[4] LDATA17 Pin # E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 Signal Name LDATA5 LDATA4 LDATA3 LDATA2 VSS R/W#(WR#) D[3] CLK LDATA1 LDATA0 D[13] D[10] D[7] E(RD#) D[2] D[1] Pin # G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Signal Name D[16] D[14] D[12] D[9] D[6] D/C# RESET# D[0] D[17] D[15] D[11] D[8] D[5] CS# CONF VDDIO SSD1961 Rev 1.4 P 11/90 Apr 2012 Solomon Systech 6 PIN DESCRIPTIONS Key: I = Input O =Output IO = Bi-directional (input/output) P = Power pin Hi-Z = High impedance Pin Name CLK XTAL_IN XTAL_OUT CS# D/C# E(RD#) R/W#(WR#) D[17:0] TE Table 6-1: MCU Interface Pin Description Type I I O I I I I IO O Reference Voltage Level VDDIO - VDDIO VDDIO VDDIO VDDIO VDDIO VDDLCD Pin # E8 C8 B8 H6 G6 F6 E6 D7, E7, F3-F5, F7-F8, G1-G5, G8, H1- H5 A4 Description TTL clock input. This pin should be tied to VSS if TTL clock input is not used Crystal oscillator input. This pin should be tied to VSS if not used Crystal oscillator output. This pin should be floating if not used Chip select Data/Command select 6800 mode: E (enable signal) 8080 mode: RD# (read strobe signal) 6800 mode: R/W# 0: Write cycle 1: Read cycle 8080 mode: WR# (write strobe signal) Data bus. Pins not used should be floating Tear effect Table 6-2: LCD Interface Pin Description Pin Name LFRAME LLINE LSHIFT LDEN LDATA[17:0] GPIO[3:0] GAMAS [1:0] PWM Type O O O O O IO O O Reference Voltage Level VDDLCD VDDLCD VDDLCD VDDLCD VDDLCD VDDLCD VDDLCD VDDLCD Pin # C6 B5 A5 C5 A2, B1B2, C1C4, D1D4, D8, E1-E4, F1-F2 A6, B6B7, C7 A3, B3 B4 Description Vertical sync (Frame pulse) Horizontal sync (Line pulse) Pixel clock (Pixel shift signal) Data valid RGB data These pins be configured for display miscellaneous signals or as general purpose I/O. Default as input Gamma selection for panel PWM output for backlight driver Solomon Systech Apr 2012 P 12/90 Rev 1.4 SSD1961 Pin Name RESET# CONF Table 6-3: Control Signal Pin Description Type I Reference Voltage Level VDDIO Pin # G7 I VDDIO H7 Description Master synchronize reset MCU interface configuration 0: 6800 Interface 1: 8080 Interface Pin Name VDDD VDDLCD VDDPLL VDDIO VSS VSSPLL Table 6-4: Power Pin Description Type Pin # Description P D6 Power supply for internal digital circuit P A1 Power supply for LCD interface related pads P A8 Power supply for internal analog circuit and analog I/O pads P H8 Power supply for digital I/O pads P D5, E5 Ground for internal digital circuit P A7 Ground for internal analog circuit and analog I/O pads Table 6-5: LCD Interface Pin Mapping Pin Names LFRAME LLINE LSHIFT LDEN LDATA17 LDATA16 LDATA15 LDATA14 LDATA13 LDATA12 LDATA11 LDATA10 LDATA9 LDATA8 LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 18-bit TFT 8-bit Serial FRAME LINE SHIFT DEN R5 Drive 0 R4 Drive 0 R3 Drive 0 R2 Drive 0 R1 Drive 0 R0 Drive 0 G5 Drive 0 G4 Drive 0 G3 Drive 0 G2 Drive 0 G1 D7 G0 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 Note (1) These pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. SSD1961 Rev 1.4 P 13/90 Apr 2012 Solomon Systech 7 FUNCTIONAL BLOCK DESCRIPTIONS 7.1 MCU Interface The MCU interface connects the MCU and SSD1961 graphics controller. The MCU interface can be configured as 6800 mode and 8080 mode by the CONF pin. By pulling the CONF pin to VSS, the MCU interface will be configured as 6800 mode interface. If the CONF pin is connected to VDDIO, the MCU interface will be configured as 8080 mode. 7.1.1 6800 Mode The 6800 mode MCU interface consist of CS#, D/C#, E, R/W#, D[17:0], and TE signals (Please refer to Table 6-1 for pin multiplexed with 8080 mode). This interface supports both fixed E and clock E scheme to define a read/write cycle. If the E signal is kept high and used as enable signal, the CS# signal acts as a bus clock, the data or command will be latched into the system at the rising edge of CS#. If the user wants to use the E pin as the clock pin, the CS# pin then need to be fixed to logic 0 to select the chip. Then the falling edge of the E signal will latch the data or command. For details, please refer to the timing diagram in chapter 13.2.1. 7.1.2 8080 Mode The 8080 mode MCU interface consist of CS#, D/C#, RD#, WR#, D[17:0] and TE signals (Please refer to Table 6-1 for pin multiplexed with 6800 mode). This interface use WR# to define a write cycle and RD# for read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the rising edge of RD#. The detailed timing will show in the chapter 1.1. 7.1.3 Register Pin Mapping When user access the registers via the parallel MCU interface, only D[7:0] will be used regardless the width of the pixel data is. Therefore, D[17:8] will only be used to address the display data only. This provided the possibility that the pixel data format as shown in Table 7-1 can be configured by command 0xF0. 7.1.4 Pixel Data Format Both 6800 and 8080 support 8 bit, 16 bit, 18 bit data bus. Depending on the width of the data bus, the display data are packed into the data bus in different ways. Table 7-1: Pixel Data Format Interface 18 bits 16 bits (565 format) 16 bits 12 bits 9 bits 8 bits X: Don't Care Cycle D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 1st R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1st R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 1st R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 2nd B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 3rd G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 1st R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 2nd G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 1st R5 R4 R3 R2 R1 R0 G5 G4 G3 2nd G2 G1 G0 B5 B4 B3 B2 B1 B0 1st R7 R6 R5 R4 R3 R2 R1 R0 2nd G7 G6 G5 G4 G3 G2 G1 G0 3rd B7 B6 B5 B4 B3 B2 B1 B0 Solomon Systech Apr 2012 P 14/90 Rev 1.4 SSD1961 7.1.5 Tearing Effect Signal (TE) The Tearing Effect Signal (TE) is a feedback signal from the LCD Controller to MCU. This signal reveals the display status of LCD controller. In the non-display period, the TE signal will go high. Therefore, this signal enables the MCU to send data by observing the non-display period to avoid tearing. Figure 7-1 shows how the TE signal helps to avoid tearing. If the MCU writing speed is slower than the display speed, the display data should be updated after the LCD controller start to scan the frame buffer. Then the LCD controller will always display the old memory content until the next frame. However, if the MCU is faster than the LCD controller, it should start updating the display content in the vertical non-display period (VNDP) to enable the LCD controller will always get the newly updated data. Figure 7-1: Relationship between Tearing Effect Signal and MCU Memory Writing In SSD1961, users can configure the TE signal to reflect the vertical non-display period only or reflect both vertical and horizontal non-display period. With the additional horizontal non-display period information, the MCU can control the refresh action in more accurately by counting the horizontal line scanned by the LCD controller. Usually, a fast MCU will not need horizontal non-display period. But a slow MCU will need it to ensure the frame buffer update process always lags behind the LCD controller. 7.2 System Clock Generation The system clock of SSD1961 is generated by the built-in PLL. The reference clock of the PLL can come from either the CLK pin or the external crystal oscillator. Since the CLK pin and the output of the oscillator was connected to PLL with an “OR” gate, the unused clock must be tied to VSS. Before the PLL output is configured as the system clock by the bit 1 of “set_pll” command 0xE0, the system will be clocked by the reference clock. This enables the user to send the “set_pll_mn” command 0xE2 to the PLL for frequency configuration. When the PLL frequency is configured and the PLL was enabled with the SSD1961 Rev 1.4 P 15/90 Apr 2012 Solomon Systech bit 0 of “set_pll” command 0xE0, the user should still wait for 100us for the PLL to lock. Then the PLL is ready and can be configured as system clock with the bit 1 of “set_pll” command 0xE0. Figure 7-2: Clock Control Diagram set_pll bit 0 CLK OSC XTAL_IN XTAL_OUT EXTERNAL CRYSTAL EN REF PLL FB 1/N set_pll bit 1 1/M 1 0 System Clock 7.3 Frame Buffer There are 5,529,600 bit built-in SRAM inside SSD1961 to use as frame buffer. When the frame buffer is written or read, the “address counter” will automatically increase by one or decrease by one depends on the frame buffer settings. Table 7-2: Frame Buffer Settings regarding to set_address_mode command 0x36 7.4 System Clock and Reset Manager The “System Clock and Reset Manager” distributes the reset signal and clock signal to the entire system. It controls the Clock Generator and contains clock gating circuitry to turn on and off the clock of each functional module. Also, it divides the root clock from Clock Generator to operation clocks for different module. The System Clock and Reset Manager also manage the reset signals to ensure all the module are reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state. Figure 7-3 shows a state diagram of four operation states of SSD1961. Solomon Systech Apr 2012 P 16/90 Rev 1.4 SSD1961 Figure 7-3: State Diagram of SSD1961 7.5 LCD Controller 7.5.1 Display Format The LCD controller reads the frame buffer and generates display signals according to the selected display panel format. SSD1961 supports common RAM-less TFT driver using generic RGB data. 7.5.2 General Purpose Input/Output (GPIO) The GPIO pins can operate in 2 modes, GPIO mode and miscellaneous display signal mode. When the pins are configured as GPIOs, these pins can be controlled directly by MCU. Therefore, user can use these pins to emulate other interface such as SPI or I2C. If these pins are configured as display signals, they will toggle with display periodically according to the signal settings. They can be set to toggle once a frame, once a line or in arbitrary period. Therefore they can be configured as some common signal needed for different panels such as STH or LP. SSD1961 Rev 1.4 P 17/90 Apr 2012 Solomon Systech 8 COMMAND TABLE Hex Code 0x00 0x01 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x20 0x21 0x26 0x28 0x29 0x2A 0x2B 0x2C 0x2E 0x30 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3C 0x3E Command nop soft_reset get_power_mode get_address_mode Reserved get_display_mode get_tear_effect_status Reserved enter_sleep_mode exit_sleep_mode enter_partial_mode enter_normal_mode exit_invert_mode enter_invert_mode set_gamma_curve set_display_off set_display_on set_column_address set_page_address write_memory_start read_memory_start set_partial_area set_scroll_area set_tear_off set_tear_on set_address_mode set_scroll_start exit_idle_mode enter_idle_mode Reserved write_memory_continue read_memory_continue Description No operation Software Reset Get the current power mode Get the frame buffer to the display panel read order Reserved The SSD1961 returns the Display Image Mode. Get the Tear Effect status Reserved Turn off the panel. This command will pull low the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. Turn on the panel. This command will pull high the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. Part of the display area is used for image display. The whole display area is used for image display. Displayed image colors are not inverted. Displayed image colors are inverted. Selects the gamma curve used by the display panel. Blanks the display panel Show the image on the display panel Set the column address Set the page address Transfer image information from the host processor interface to the SSD1961 starting at the location provided by set_column_address and set_page_address Transfer image data from the SSD1961 to the host processor interface starting at the location provided by set_column_address and set_page_address Defines the partial display area on the display panel Defines the vertical scrolling and fixed area on display area Synchronization information is not sent from the SSD1961 to the host processor Synchronization information is sent from the SSD1961 to the host processor at the start of VFP Set the read order from frame buffer to the display panel Defines the vertical scrolling starting point Full color depth is used for the display panel Reduce color depth is used on the display panel. Reserved Transfer image information from the host processor interface to the SSD1961 from the last written location Read image data from the SSD1961 continuing after the last read_memory_continue or read_memory_start Solomon Systech Apr 2012 P 18/90 Rev 1.4 SSD1961 Hex Code Command 0x44 set_tear_scanline 0x45 0xA1 0xA8 0xB0 0xB1 0xB4 0xB5 0xB6 get_scanline read_ddb Reserved set_lcd_mode_ get_lcd_mode set_hori_period get_hori_period set_vert_period 0xB7 get_vert_period 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 set_gpio_conf get_gpio_conf set_gpio_value get_gpio_status set_post_proc get_post_proc set_pwm_conf get_pwm_conf set_lcd_gen0 get_lcd_gen0 set_lcd_gen1 get_lcd_gen1 set_lcd_gen2 get_lcd_gen2 set_lcd_gen3 get_lcd_gen3 set_gpio0_rop 0xC9 get_gpio0_rop 0xCA set_gpio1_rop 0xCB get_gpio1_rop 0xCC set_gpio2_rop Description Synchronization information is sent from the SSD1961to the host processor when the display panel refresh reaches the provided scanline Get the current scan line Read the DDB from the provided location Reserved Set the LCD panel mode and resolution Get the current LCD panel mode, pad strength and resolution Set front porch Get current front porch settings Set the vertical blanking interval between last scan line and next LFRAME pulse Set the vertical blanking interval between last scan line and next LFRAME pulse Set the GPIO configuration. If the GPIO is not used for LCD, set the direction. Otherwise, they are toggled with LCD signals. Get the current GPIO configuration Set GPIO value for GPIO configured as output Read current GPIO status. If the individual GPIO was configured as input, the value is the status of the corresponding pin. Otherwise, it is the programmed value. Set the image post processor Set the image post processor Set the image post processor Set the image post processor Set the rise, fall, period and toggling properties of LCD signal generator 0 Get the current settings of LCD signal generator 0 Set the rise, fall, period and toggling properties of LCD signal generator 1 Get the current settings of LCD signal generator 1 Set the rise, fall, period and toggling properties of LCD signal generator 2 Get the current settings of LCD signal generator 2 Set the rise, fall, period and toggling properties of LCD signal generator 3 Get the current settings of LCD signal generator 3 Set the GPIO0 with respect to the LCD signal generators using ROP operation. No effect if the GPIO0 is configured as general GPIO. Get the GPIO0 properties with respect to the LCD signal generators. Set the GPIO1 with respect to the LCD signal generators using ROP operation. No effect if the GPIO1 is configured as general GPIO. Get the GPIO1 properties with respect to the LCD signal generators. Set the GPIO2 with respect to the LCD signal generators using ROP operation. No effect if the GPIO2 is configured as general GPIO. SSD1961 Rev 1.4 P 19/90 Apr 2012 Solomon Systech Hex Code Command 0xCD get_gpio2_rop 0xCE set_gpio3_rop 0xCF 0xD0 get_gpio3_rop set_dbc_conf Description Get the GPIO2 properties with respect to the LCD signal generators. Set the GPIO3 with respect to the LCD signal generators using ROP operation. No effect if the GPIO3 is configured as general GPIO. Get the GPIO3 properties with respect to the LCD signal generators. Set the dynamic back light configuration 0xD1 get_dbc_conf Get the current dynamic back light configuration 0xD4 0xD5 0xE0 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xF0 0xF1 0xFF set_dbc_th get_dbc_th set_pll set_pll_mn get_pll_mn get_pll_status set_deep_sleep set_lshift_freq get_lshift_freq Reserved Reserved set_pixel_data_interface get_pixel_data_interface Reserved Set the threshold for each level of power saving Get the threshold for each level of power saving Start the PLL. Before the start, the system was operated with the crystal oscillator or clock input Set the PLL Get the PLL settings Get the current PLL status Set deep sleep mode Set the LSHIFT (pixel clock) frequency Get current LSHIFT (pixel clock) frequency setting Reserved Reserved Set the pixel data format of the parallel host processor interface Get the current pixel data format settings Reserved Solomon Systech Apr 2012 P 20/90 Rev 1.4 SSD1961 9 COMMAND DESCRIPTIONS 9.1 nop Command Parameters 0x00 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 0 0 0 0 0 00 Description No operation. . 9.2 soft_reset Command Parameters 0x01 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 0 0 0 0 1 01 Description The SSD1961 performs a software reset. All the configuration register will be reset except command 0xE0 to 0xE5. Note : The host processor must wait 5ms before sending any new commands to a SSD1961 following this command. 9.3 get_power_mode Command Parameters 0x0A 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 0 1 0 1 0 0A Parameter 1 1 0 A6 A5 A4 A3 A2 0 0 xx Description Get the current power mode A[6] : Idle mode on/off (POR = 0) 0 Idle mode off 1 Idle mode on A[5] : Partial mode on/off (POR = 0) 0 Partial mode off 1 Partial mode on A[4] : Sleep mode on/off (POR = 0) 0 Sleep mode on 1 Sleep mode off A[3] : Display normal mode on/off (POR = 1) 0 Display normal mode off SSD1961 Rev 1.4 P 21/90 Apr 2012 Solomon Systech 1 Display normal mode on (partial mode and vertical scroll off) A[2] : Display on/off (POR = 0) 0 Display is off 1 Display is on 9.4 get_address_mode Command Parameters 0x0B 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 0 1 0 1 1 0B Parameter 1 1 A7 A6 A5 A4 A3 A2 0 0 xx Description Get the frame buffer to the display panel read order A[7] : Page address order (POR = 0) 0 Top to bottom 1 Bottom to top A[6] : Column address order (POR = 0) 0 Left to right 1 Right to left A[5] : Page / Column order (POR = 0) 0 Normal mode 1 Reverse mode A[4] : Line address order (POR = 0) 0 LCD refresh top to bottom 1 LCD refresh bottom to top A[3] : RGB / BGR order (POR = 0) 0 RGB 1 BGR A[2] : Display data latch data (POR = 0) 0 LCD refresh left to right 1 LCD refresh right to left 9.5 get_display_mode Command Parameters 0x0D 1 D/C D7 D6 D5 D4 Command 0 0 0 0 0 Parameter 1 1 A7 0 A5 0 Description The SSD1961 returns the Display Image Mode status. A[7] : Vertical scrolling status on/off (POR = 0) 0 Vertical scrolling is off Solomon Systech D3 D2 D1 D0 Hex 1 1 0 1 0D 0 A2 A1 A0 xx Apr 2012 P 22/90 Rev 1.4 SSD1961 1 Vertical scrolling is on A[5] : Invert mode on/off (POR = 0) 0 Inversion is off 1 Inversion is on A[2:0] : Gamma curve selection (POR = 011) 000 Gamma curve 0 001 Gamma curve 1 010 Gamma curve 2 011 Gamma curve 3 100 Reserved 101 Reserved 110 Reserved 111 Reserved 9.6 get_tear_effect_status Command Parameters 0x0E 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 0 1 1 1 0 0E Parameter 1 1 A7 0 0 0 0 0 0 0 xx Description Get the current Tear Effect mode from the SSD1961 A[7] : Tearing effect line mode (POR = 0) 0 Tearing effect off 1 Tearing effect on SSD1961 Rev 1.4 P 23/90 Apr 2012 Solomon Systech 9.7 enter_sleep_mode Command Parameters 0x10 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 1 0 0 0 0 10 Description Turn off the panel. This command causes the SSD1961 to enter sleep mode and pull low the GPIO[0] if set_gpio_conf (0xB8) B0 = 0. If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this command will not affect the GPIO[0]. Note : The host processor must wait 5ms before sending any new commands to a SSD1961 following this command. 9.8 exit_sleep_mode Command Parameters 0x11 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 1 0 0 0 1 11 Description Turn on the panel. This command causes the SSD1961 to exit sleep mode and will pull high the GPIO[0] if set_gpio_conf (0xB8) B0 = 0. If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this command will not affect the GPIO[0]. Note : The host processor must wait 5ms after sending this command before sending another command. **This command will automatic trigger set_display_on (0x29) 9.9 enter_partial_mode Command Parameters 0x12 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 1 0 0 1 0 12 Description Once enter_partial_mode is triggered, the Partial Display Mode window is described by the set_partial_area (0x30). Once enter_normal_mode (0x13) is triggered, partial display mode will end. 9.10 enter_normal_mode Command Parameters 0x13 None Solomon Systech Apr 2012 P 24/90 Rev 1.4 SSD1961 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 0 1 0 0 1 1 13 Description This command causes the SSD1961 to enter the normal mode. Normal mode is defined as partial display and vertical scroll mode are off. That means the whole display area is used for image display. 9.11 exit_invert_mode Command Parameters 0x20 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 0 0 0 0 20 Description This command causes the SSD1961 to stop inverting the image data on the display panel. The frame buffer contents remain unchanged. Figure 9-1: Exit Invert mode example Frame Buffer Display Panel Ö 9.12 enter_invert_mode Command Parameters 0x21 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 0 0 0 1 21 Description This command causes the SSD1961 to invert the image data only on the display panel. The frame buffer contents remain unchanged. SSD1961 Rev 1.4 P 25/90 Apr 2012 Solomon Systech Figure 9-2: Enter Invert mode example Frame Buffer Display Panel Ö 9.13 set_gamma_curve Command Parameters 0x26 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 0 1 1 0 26 Parameter 1 1 0 0 0 0 A3 A2 A1 A0 xx Description Selects the gamma curve used by the display panel. A[3:0] 0000 0001 0010 0100 1000 Others Gamma curve selection (POR = 1000) No gamma curve selected (Same as 0001b) Gamma curve 0 Gamma curve 1 Gamma curve 2 Gamma curve 3 Reserved GAMAS[1] 0 0 0 1 1 GAMAS[0] 0 0 1 0 1 9.14 set_display_off Command Parameters 0x28 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 1 0 0 0 28 Description Blanks the display panel. The frame buffer contents remain unchanged. 9.15 set_display_on Command Parameters 0x29 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 1 0 0 1 29 Description Show the image on the display panel Solomon Systech Apr 2012 P 26/90 Rev 1.4 SSD1961 9.16 set_column_address Command Parameters 0x2A 4 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 1 0 1 0 2A Parameter 1 1 SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 xx Parameter 2 1 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 xx Parameter 3 1 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 xx Parameter 4 1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 xx Description Set the column address of frame buffer accessed by the host processor with the read_memory_continue (0x3E) and write_memorty_continue (0x3C).. SC[15:8] : Start column number high byte (POR = 00000000) SC[7:0] : Start column number low byte (POR = 00000000) EC[15:8] : End column number high byte (POR = 00000000) EC[7:0] : End column number low byte (POR = 00000000) Note : SC[15:0] must always be equal to or less than EC[15:0] Figure 9-3: Set Column Address example SC[15:0 ] EC[15:0] 9.17 set_page_address Command Parameters 0x2B 4 D/C D7 D6 D5 D4 D3 D2 D1 Command 0 0 0 1 0 1 0 0 Parameter 1 1 SP15 SP14 SP13 SP12 SP11 SP10 SP9 Parameter 2 1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 Parameter 3 1 EP15 EP14 EP13 EP12 EP11 EP10 EP9 Parameter 4 1 EP7 EP6 EP5 EP4 EP3 EP2 EP1 D0 Hex 1 2B SP8 xx SP0 xx EP8 xx EP0 xx Description Set the page address of the frame buffer accessed by the host processor with the read_memory_start (0x2C), write_memory_start (0x2E), read_memory_continue (0x3E) and write_memory_continue (0x3C)).. SSD1961 Rev 1.4 P 27/90 Apr 2012 Solomon Systech SP[15:8] : Start page (row) number high byte (POR = 00000000) SP[7:0] : Start page (row) number low byte (POR = 00000000) EP[15:8] : End page (row) number high byte (POR = 00000000) EP[7:0] : End page (row) number low byte (POR = 00000000) Note : SP[15:0] must always be equal to or less than EP[15:0] Figure 9-4: Set Page Address example SP[15:0] EP[15:0] 9.18 write_memory_start Command Parameters 0x2C None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 1 1 0 0 2C Description Transfer image information from the host processor interface to the SSD1961 starting at the location provided by set_column _address (0x2A) and set _page_address (0x2B). If set_address_mode (0x36) A[5] = 0: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixel Data 1 is stored in frame buffer at (SC, SP). The column address is then incremented and pixels are written to the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are written to the frame buffer until the page address equals the End Page (EP) value and the column address equals the EC value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. If set_address_mode (0x36) A[5] = 1: The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixel Data 1 is stored in frame buffer at (SC, SP). The page address is then incremented and pixels are written to the frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are written to the frame buffer until the column address equals the End column (EC) value and the page address equals the EP value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. Solomon Systech Apr 2012 P 28/90 Rev 1.4 SSD1961 9.19 read_memory_start Command Parameters 0x2E None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 0 1 1 1 0 2E Description Transfer image data from the SSD1961 to the host processor interface starting at the location provided by set_column_address (0x2A) and set_page_address (0x2B). If set_address_mode A[5] = 0: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels Data1are read from frame buffer at (SC, SP). The column address is then incremented and pixels read from the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are read from the frame buffer until the page address equals the End Page (EP) value and the column address equals the EC value, or the host processor sends another command. If set_address_mode (0x36) A[5] = 1: The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels Data1are read from frame buffer at (SC, SP). The page address is then incremented and pixels read from the frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are read from the frame buffer until the column address equals the End Column (EC) value and the page address equals the EP value, or the host processor sends another command. 9.20 set_partial_area Command Parameters 0x30 4 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 0 0 0 30 Parameter 1 1 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 xx Parameter 2 1 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 xx Parameter 3 1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 xx Parameter 4 1 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 xx Description This command defines the Partial Display mode’s display area. There are two parameters associated with this command, the first defines the Start Row (SR) and the second the End Row (ER). SR and ER refer to the Frame Buffer Line Pointer. SR[15:8] : Start display row number high byte (POR = 00000000) SR[7:0] : Start display row number low byte (POR = 00000000) ER[15:8] : End display row number high byte (POR = 00000000) ER[7:0] : End display row number low byte (POR = 00000000) Note : SR[15:0] and ER[15:0] cannot be 0000h nor exceed the last vertical line number. SSD1961 Rev 1.4 P 29/90 Apr 2012 Solomon Systech If End Row > Start Row Figure 9-5: Set Partial Area with set_address_mode (0x36) A[4] = 0 when End Row > Start Row SR[15:0] ER[15:0] Partial Area Figure 9-6: Set Partial Area with set_address_mode (0x36) A[4] = 1 when End Row > Start Row ER[15:0] SR[15:0] Partial Area If Start Row > End Row Figure 9-7: Set Partial Area with set_address_mode (0x36) A[4] = 0 when Start Row > End Row ER[15:0] Partial Area SR[15:0] Solomon Systech Partial Area Apr 2012 P 30/90 Rev 1.4 SSD1961 Figure 9-8: Set Partial Area with set_address_mode (0x36) A[4] = 1 when Start Row > End Row SR[15:0] Partial Area ER[15:0] Partial Area 9.21 set_scroll_area Command Parameters 0x33 6 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 0 1 1 33 Parameter 1 1 TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 xx Parameter 2 1 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 xx Parameter 3 1 VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 xx Parameter 4 1 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 xx Parameter 5 1 BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 xx Parameter 6 1 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 xx Description Defines the vertical scrolling and fixed area on display area TFA[15:8] : High byte of Top Fixed Area number in lines from the top of the frame buffer (POR = 00000000) TFA[7:0] : Low byte of Top Fixed Area number in lines from the top of the frame buffer (POR = 00000000) VSA[15:8] : High byte of Vertical scrolling area in number of lines of the frame buffer (POR = 00000000) VSA[7:0] : Low byte of Vertical scrolling area in number of lines of the frame buffer (POR = 00000000) BFA[15:8] : High byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = 00000000) BFA[7:0] : Low byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = 00000000) If set_address_mode (0x36) A[4] = 0 : The TFA[15:0] describes the Top Fixed Area in number of lines from the top of the frame buffer. The top of the frame buffer and top of the display panel are aligned. The VSA[15:0] describes the height of the Vertical Scrolling Area in number of lines of frame buffer from the Vertical Scrolling Start Address. The first line of the Vertical Scrolling Area starts immediately after the bottom most line of the Top Fixed Area. The last line of the Vertical Scrolling Area ends immediately before the top most line of the Bottom Fixed Area. The BFA[15:0] describes the Bottom Fixed Area in number of lines from the bottom of the frame buffer. The bottom of the frame buffer and bottom of the display panel are aligned. TFA, VSA and BFA refer to the Frame Buffer Line Pointer. SSD1961 Rev 1.4 P 31/90 Apr 2012 Solomon Systech (0,0) TFA[15:0] VSA[15:0] Figure 9-9: Set Scroll Area with set_address_mode (0x36) A[4] = 0 Top Fixed Area First line read from memory BFA[15:0] Bottom Fixed Area If set_address_mode (0x36) A[4] = 1 : The TFA[15:0], describes the Top Fixed Area in number of lines from the bottom of the frame buffer. The bottom of the frame buffer and bottom of the display panel are aligned. The VSA[15:0] describes the height of the Vertical Scrolling Area in number of lines of frame buffer from the Vertical Scrolling Start Address. The first line of the Vertical Scrolling Area starts immediately after the top most line of the Top Fixed Area. The last line of the Vertical Scrolling Area ends immediately before the bottom most line of the Bottom Fixed Area. The BFA[15:0] describes the Bottom Fixed Area in number of lines from the top of the frame buffer. The top of the frame buffer and top of the display panel are aligned. TFA, VSA and BFA refer to the Frame Buffer Line Pointer. (0,0) BFA[15:0] Figure 9-10: Set Scroll Area with set_address_mode (0x36) A[4] = 1 Bottom Fixed Area VSA[15:0] TFA[15:0] Top Fixed Area First line read from memory Note : The sum of TFA, VSA and BFA must equal the number of the display panel’s horizontal lines (pages), otherwise Scrolling mode is undefined. In Vertical Scroll Mode, set_address_mode (0x36) A[5] should be set to ‘0’ – this only affects the Frame Buffer Write. Solomon Systech Apr 2012 P 32/90 Rev 1.4 SSD1961 9.22 set_tear_off Command Parameters 0x34 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 1 0 0 34 Description TE signal is not sent from the SSD1961 to the host processor. 9.23 set_tear_on Command Parameters 0x35 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 1 0 1 35 Parameter 1 1 0 0 0 0 0 0 0 A0 xx Description TE signal is sent from the SSD1961 to the host processor at the start of VFP. A[0] : Tearing effect line mode (POR = 0) 0 The tearing effect output line consists of V-blanking information only. 1 The tearing effect output line consists of both V-blanking and H-blanking information by set_tear_scanline (0x44).. The TE signal shall be active low when the display panel is in Sleep mode. 9.24 set_address_mode Command Parameters 0x36 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 1 1 0 36 Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Description Set the read order from host processor to frame buffer by A[7:5] and A[3] and from frame buffer to the display panel by A[2:0] and A[4]. A[7] : Page address order (POR = 0) This bit controls the order that pages of data are transferred from the host processor to the SSD1961’s frame buffer. 0 Top to bottom, pages transferred from SP (Start Page) to EP (End Page). 1 Bottom to top, pages transferred from EP (End Page) to SP (Start Page). SSD1961 Rev 1.4 P 33/90 Apr 2012 Solomon Systech Figure 9-11: A[7] Page Address Order A[7]=0, A[6]=A[5]=0,A[3]=x Host Frame Buffer SP SP A[7]=1, A[6]=A[5]=0,A[3]=x Host Frame Buffer SP EP         EP EP EP SP SC   EC SC   EC SC   EC SC   EC A[6] : Column address order (POR = 0) This bit controls the order that columns of data are transferred from the host processor to the SSD1961’s frame buffer. 0 Left to right, columns transferred from SC (Start Column) to EC (End Column). 1 Right to left, columns transferred from EC (End Column) to SC (Start Column). Figure 9-12: A[6] Column Address Order A[6]=0, A[7]=A[5]=0,A[3]=x Host Frame Buffer SP SP A[6]=1, A[7]=A[5]=0,A[3]=x Host Frame Buffer SP SP         EP EP EP EP SC   EC SC   EC SC   EC EC   SC A[5] : Page / Column order (POR = 0) This bit controls the order that columns of data are transferred from the host processor to the SSD1961’s frame buffer. 0 Normal mode 1 Reverse mode Figure 9-13: A[5] Page / Column Address Order A[5]=0, A[7]=A[6]=0,A[3]=x Host Frame Buffer SP SP A[5]=1, A[7]=A[6]=0,A[3]=x Host Frame Buffer SP SC         EP EP EP EC SC   EC SC   EC SC   EC SP   EP Solomon Systech Apr 2012 P 34/90 Rev 1.4 SSD1961 A[4] : Line address order (POR = 0) This bit controls the display panel’s horizontal line refresh order. The image shown on the display panel is unaffected, regardless of the bit setting. 0 LCD refresh from top line to bottom line. 1 LCD refresh from bottom line to top line. A[3] : RGB / BGR order (POR = 0) This bit controls the RGB data order transferred from the SSD1961’s frame buffer to the display panel. 0 RGB 1 BGR Frame Buffer RGB A[3] = 0   Figure 9-14: A[3] RGB Order Display Panel R GB Frame Buffer RGB A[3] = 1   Display Panel BG R A[2] : Display data latch data (POR = 0) This bit controls the display panel’s vertical line data latch order. The image shown on the display panel is unaffected, regardless of the bit setting. 0 LCD refresh from left side to right side 1 LCD refresh from right side to left side A[1] : Flip Horizontal (POR = 0) This bit flips the image shown on the display panel left to right. No change is made to the frame buffer. 0 Normal 1 Flipped Figure 9-15: A[1] Flip Horizontal A[1]=0, A[4]=A[2]=A[0]=0 Frame Buffer Display Panel 1 1 A[1]=1, A[4]=A[2]=A[0]=0 Frame Buffer Display Panel 1 1         n n n n 1   m 1   m 1   m m  1 SSD1961 Rev 1.4 P 35/90 Apr 2012 Solomon Systech A[0] : Flip Vertical (POR = 0) This bit flips the image shown on the display panel top to bottom. No change is made to the frame buffer. 0 Normal 1 Flipped Figure 9-16: A[0] Flip Vertical A[0]=0, A[4]=A[2]=A[1]=0 Frame Buffer Display Panel 1 1 A[0]=1, A[4]=A[2]=A[1]=0 Frame Buffer Display Panel 1 n         n n n 1 1   m 1   m 1   m 1   m 9.25 set_scroll_start Command Parameters 0x37 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 0 1 1 1 37 Parameter 1 1 VSP15 VSP14 VSP13 VSP12 VSP11 VSP10 VSP9 VSP8 xx Parameter 2 1 VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0 xx Description This command sets the start of the vertical scrolling area in the frame buffer. The vertical scrolling area is fully defined when this command is used with the the set_scroll_area (0x33). VSP[15:8] : High byte of the line number in frame buffer that is written to the display as the first line of the vertical scrolling area (POR = 00000000) VSP[7:0] : Low byte of the line number in frame buffer that is written to the display as the first line of the vertical scrolling area (POR = 00000000) If set_address_mode (0x36) A[4] = 0: Example: When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = YY and VSP = 3. (0,0) Figure 9-17: Set Scroll Start with set_address_mode (0x36) A[4] = 0 Frame Buffer VSP[15:0] Display Panel VSP[15:0] (0,YY-1) (0,YY-1) (0,0) Solomon Systech Apr 2012 P 36/90 Rev 1.4 SSD1961 If set_address_mode (0x36) A[4] = 1: Example: When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = YY and VSP = 3. Figure 9-18: Set Scroll Start with set_address_mode (0x36) A[4] = 1 (0,YY-1) Frame Buffer Display Panel VSP[15:0] (0,0) (0,YY-1) (0,0) VSP[15:0] Note : If set_address_mode, (0x36) A[4] = 0, TFA[15:0] - 1< VSP[15:0] < # of lines in frame buffer - BFA[15:0] If set_address_mode, (0x36) A[4] = 1, BFA[15:0] - 1 < VSP[15:0] < # of lines in frame buffer - TFA[15:0] 9.26 exit_idle_mode Command Parameters 0x38 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 1 0 0 0 38 Description This command causes the SSD1961 to exit Idle Mode. Full color depth is used for the display panel. 9.27 enter_idle_mode Command Parameters 0x39 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 1 0 0 1 39 Description This command causes the SSD1961 to enter Idle Mode. In Idle Mode, color depth is reduced. Colors are shown on the display panel using the MSB of each of the R, G and B color components in the frame buffer. SSD1961 Rev 1.4 P 37/90 Apr 2012 Solomon Systech Color Black Blue Red Magenta Green Cyan Yellow White Table 9-1: Enter Idle Mode memory content vs display color R7 R6 R5 R4 R3 R2 R1 R0 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX G7 G6 G5 G4 G3 G2 G1 G0 0XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX B7 B6 B5 B4 B3 B2 B1 B0 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 9.28 write_memory_continue Command Parameters 0x3C None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 1 1 0 0 3C Description Transfer image information from the host processor interface to the SSD1961 from the last write_memory_continue (0x3C) or write_memory_start (0x2C). If set_address_mode (0x36) A[5] = 0: Data is written continuing from the pixel location after the write range of the previous write_memory_start (0x2C) or write_memory_continue (0x3C). The column address is then incremented and pixels are written to the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are written to the frame buffer until the page address equals the End Page (EP) value and the column register equals the EC value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. If set_address_mode (0x36) A[5] = 1: Data is written continuing from the pixel location after the write range of the previous write_memory_start (0x2C) or write_memory_continue (0x3C). The page address is then incremented and pixels are written to the frame buffer until the page register equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are written to the frame buffer until the column register equals the End column (EC) value and the page address equals the EP value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. Solomon Systech Apr 2012 P 38/90 Rev 1.4 SSD1961 9.29 read_memory_continue Command Parameters 0x3E None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 0 1 1 1 1 1 0 3E Description Read image data from the SSD1961 to host processor continuing after the last read_memory_continue (0x3E) or read_memory_start (0x2E). If set_address_mode (0x36) A[5] = 0: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start (0x2E) or read_memory_continue (0x3E). The column address is then incremented and pixels are read from the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are read from the frame buffer until the page address equals the End Page (EP) value and the column address equals the EC value, or the host processor sends another command. If set_address_mode (0x36) A[5] = 1: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start (0x2E) or read_memory_continue (0x3E). The page address is then incremented and pixels are read from the frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are read from the frame buffer until the column address equals the End Column (EC) value and the page address equals the EP value, or the host processor sends another command. SSD1961 Rev 1.4 P 39/90 Apr 2012 Solomon Systech 9.30 set_tear_scanline Command Parameters 0x44 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 1 0 0 0 1 0 0 44 Parameter 1 1 N15 N14 N13 N12 N11 N10 N9 N8 xx Parameter 2 1 N7 N6 N5 N4 N3 N2 N1 N0 xx Description TE signal is sent from the SSD1961 to the host processor when the display panel refresh reaches the provided scanline, N. N[15:8] : High byte of the scanline (POR = 00000000) N[7:0] : Low byte of the scanline (POR = 00000000) Note : Valid setting for TE signal: 0x0000, 0x0002 to 0xFFFF. The number of Tear Scanline = N[15:0] +1, except N = 0. Set Tear Scanline with N = 0 is equivalent to set_tear_on (0x35) A[0] = 0. When Tear Scanline, N >= Vertical panel size, TE signal will always pull high. Program set_tear_scanline will automatic change the operating mode of set_tear_on (0x35) A[0] = 1. This command takes affect on the frame following the current frame. Therefore, if the Tear Effect (TE) signal is already ON, the TE output shall continue to operate as programmed by the previous set_tear_on (0x35) or set_tear_scanline (0x44) until the end of the frame. 9.31 get_scanline Command Parameters 0x45 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 0 1 0 0 0 1 0 1 45 Parameter 1 1 N15 N14 N13 N12 N11 N10 N9 N8 xx Parameter 2 1 N7 N6 N5 N4 N3 N2 N1 N0 xx Description Get the current scan line, N. N[15:8] : High byte of the current scanline (POR = 00000000) N[7:0] : Low byte of the current scanline (POR = 00000000) Solomon Systech Apr 2012 P 40/90 Rev 1.4 SSD1961 9.32 read_ddb Command Parameters 0xA1 5 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 0 0 0 0 1 A1 Parameter 1 1 SSL15 SSL14 SSL13 SSL12 SSL11 SSL10 SSL9 SSL8 xx Parameter 2 1 SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 xx Parameter 3 1 PROD7 PROD6 PROD5 PROD4 PROD3 PROD2 PROD1 PROD0 xx Parameter 4 1 0 0 0 0 0 REV2 REV 1 REV 0 xx Parameter 5 1 1 1 1 1 1 1 1 1 FF Description Read the DDB (Device Descriptor Block) information of SSD1961. SSL[15:8] : Supplier ID of Solomon Systech Limited high byte, always 01h (POR = 00000001) SSL[7:0] : Supplier ID of Solomon Systech Limited low byte, always 57h (POR = 01010111) PROD[7:0] : Product ID, always 61h (POR = 01100001) REV[2:0] : Revision code, always 01h (POR = 001) Exit code, always FFh (POR = 11111111) 9.33 set_lcd_mode Command Parameters 0xB0 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 0 0 0 0 B0 Parameter 1 1 0 0 0 A4 A3 A2 A1 A0 xx Parameter 2 1 0 B6 B5 0 0 0 0 0 xx Parameter 3 1 0 0 0 0 0 HDP10 HDP9 HDP8 xx Parameter 4 1 HDP7 HDP6 HDP5 HDP4 HDP3 HDP2 HDP1 HDP0 xx Parameter 5 1 0 0 0 0 0 VDP10 VDP9 VDP8 xx Parameter 6 1 VDP7 VDP6 VDP5 VDP4 VDP3 VDP2 VDP1 VDP0 xx Parameter 7 1 0 0 G5 G4 G3 G2 G1 G0 xx Description Set the LCD panel mode and resolution A[4] : TFT color depth enhancement enable (POR = 0) 0 Disable FRC or dithering 1 Enable FRC or dithering for color depth enhancement A[3] : TFT FRC enable (POR = 0) 0 TFT dithering enable 1 TFT FRC enable A[4] A[3] 0 X 1 0 1 1 TFT FRC Disable Disable Enable TFT dithering Disable Enable Disable SSD1961 Rev 1.4 P 41/90 Apr 2012 Solomon Systech A[2] : LSHIFT polarity (POR = 0) Set the dot clock pulse polarity. 0 Data latch in falling edge 1 Data latch in rising edge A[1] : LLINE polarity (POR = 0) Set the horizontal sync pulse polarity. 0 Active low 1 Active high A[0] : LFRAME polarity (POR = 0) Set the vertical sync pulse polarity. 0 Active low 1 Active high B[6:5] : TFT type (POR = 01) 00, 01 TFT mode 10 Serial RGB mode 11 Serial RGB+dummy mode HDP[10:8] : High byte of the horizontal panel size (POR = 010) HDP[7:0] : Low byte of the horizontal panel size (POR = 01111111) Horizontal panel size = (HDP + 1) pixels VDP[10:8] : High byte of the vertical panel size (POR = 001) VDP[7:0] : Low byte of the vertical panel size (POR = 11011111) Vertical panel size = (VDP + 1) lines G[5:3] : Even line RGB sequence for serial TFT interface (POR = 000) 000 RGB 001 RBG 010 GRB 011 GBR 100 BRG 101 BGR 11x Reserved G[2:0] : Odd line RGB sequence for serial TFT interface (POR = 000) 000 RGB 001 RBG 010 GRB 011 GBR 100 BRG 101 BGR 11x Reserved Solomon Systech Apr 2012 P 42/90 Rev 1.4 SSD1961 9.34 get_lcd_mode Command Parameters 0xB1 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 0 0 0 1 B1 Parameter 1 1 0 0 0 A4 A3 A2 A1 A0 xx Parameter 2 1 0 B6 B5 0 0 0 0 0 xx Parameter 3 1 0 0 0 0 0 HDP10 HDP9 HDP8 xx Parameter 4 1 HDP7 HDP6 HDP5 HDP4 HDP3 HDP2 HDP1 HDP0 xx Parameter 5 1 0 0 0 0 0 VDP10 VDP9 VDP8 xx Parameter 6 1 VDP7 VDP6 VDP5 VDP4 VDP3 VDP2 VDP1 VDP0 xx Parameter 7 1 0 0 G5 G4 G3 G2 G1 G0 xx Description Get the current LCD panel mode and resolution A[4] : TFT color depth enhancement enable(POR = 0) 0 Disable FRC or dithering 1 Enable FRC or dithering for color depth enhancement A[3] : TFT FRC enable (POR = 0) 0 TFT dithering enable 1 TFT FRC enable A[2] : LSHIFT polarity (POR = 0) The dot clock pulse polarity. 0 Data latch in falling edge 1 Data latch in rising edge A[1] : LLINE polarity (POR = 0) The horizontal sync pulse polarity. 0 Active low 1 Active high A[0] : LFRAME polarity (POR = 0) The vertical sync pulse polarity. 0 Active low 1 Active high B[6:5] : TFT type(POR = 01) 00, 01 TFT mode 10 Serial RGB mode 11 Serial RGB+dummy mode HDP[10:8] : High byte of the horizontal panel size (POR = 010) HDP[7:0] : Low byte of the horizontal panel size (POR = 01111111) VDP[10:8] : High byte of the vertical panel size (POR = 001) VDP[7:0] : Low byte of the vertical panel size (POR = 11011111) G[5:3] : Even line RGB sequence (POR = 000) 000 RGB 001 RBG 010 GRB 011 GBR SSD1961 Rev 1.4 P 43/90 Apr 2012 Solomon Systech 100 BRG 101 BGR 11x Reserved G[2:0] : Odd line RGB sequence (POR = 000) 000 RGB 001 RBG 010 GRB 011 GBR 100 BRG 101 BGR 11x Reserved 9.35 set_hori_period Command Parameters 0xB4 8 D/C Command 0 Parameter 1 1 Parameter 2 1 Parameter 3 1 Parameter 4 1 Parameter 5 1 Parameter 6 1 Parameter 7 1 Parameter 8 1 D7 1 0 HT7 0 HPS7 0 0 LPS7 0 D6 0 0 HT6 0 HPS6 HPW6 0 LPS6 0 D5 1 0 HT5 0 HPS5 HPW5 0 LPS5 0 D4 1 0 HT4 0 HPS4 HPW4 0 LPS4 0 D3 0 0 HT3 0 HPS3 HPW3 0 LPS3 0 D2 D1 D0 Hex 1 0 0 B4 HT10 HT9 HT8 xx HT2 HT1 HT0 xx HPS10 HPS9 HPS8 xx HPS2 HPS1 HPS0 xx HPW2 HPW1 HPW0 xx LPS10 LPS9 LPS8 xx LPS2 LPS1 LPS0 xx 0 LPSPP1 LPSPP0 xx Description Set front porch and back porch HT[10:8] : HT[7:0] : High byte of horizontal total period (display + non-display) in pixel clock (POR = 010) Low byte of the horizontal total period (display + non-display) in pixel clock (POR = 10101111) Horizontal total period = (HT + 1) pixels HPS[10:8] : HPS[7:0] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first display data. (POR = 000) Low byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first display data. (POR = 00100000) For TFT : Horizontal Sync Pulse Start Position = HPS pixels For Serial TFT : Horizontal Sync Pulse Start Position = HPS pixels + LPSPP subpixels HPW[6:0] : Set the horizontal sync pulse width (LLINE) in pixel clock. (POR = 0000111) Horizontal Sync Pulse Width = (HPW + 1) pixels LPS[10:8] : Set the horizontal sync pulse (LLINE) start location in pixel clock. (POR = 000) LPS[7:0] : Set the horizontal sync pulse width (LLINE) in start. (POR = 00000000) Horizontal Display Period Start Position = LPS pixels LPSPP[1:0] : Set the horizontal sync pulse subpixel start position for serial TFT interface (POR = 00) 9.36 get_hori_period Command Parameters 0xB5 8 Solomon Systech Apr 2012 P 44/90 Rev 1.4 SSD1961 D/C Command 0 Parameter 1 1 Parameter 2 1 Parameter 3 1 Parameter 4 1 Parameter 5 1 Parameter 6 1 Parameter 7 1 Parameter 8 1 D7 1 0 HT7 0 HPS7 0 0 LPS7 0 D6 0 0 HT6 0 HPS6 HPW6 0 LPS6 0 D5 1 0 HT5 0 HPS5 HPW5 0 LPS5 0 Description Get current front porch and back porch settings D4 1 0 HT4 0 HPS4 HPW4 0 LPS4 0 D3 0 0 HT3 0 HPS3 HPW3 0 LPS3 0 D2 D1 D0 Hex 1 0 1 B5 HT10 HT9 HT8 xx HT2 HT1 HT0 xx HPS10 HPS9 HPS8 xx HPS2 HPS1 HPS0 xx HPW2 HPW1 HPW0 xx LPS10 LPS9 LPS8 xx LPS2 LPS1 LPS0 xx 0 LPSPP1 LPSPP0 xx HT[10:8] : High byte of the horizontal total period (display + non-display) in pixel clock (POR = 010) HT[7:0] : Low byte of the horizontal total period (display + non-display) in pixel clock (POR = 10101111) HPS[10:8] : HPS[7:0] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first display data. (POR = 000) Low byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first display data. (POR = 00100000) HPW[6:0] : The horizontal sync pulse width (LLINE) in pixel clock. (POR = 0000111) LPS[10:8] : High byte of the horizontal sync pulse (LLINE) start location in pixel clock. (POR = 000) LPS[7:0] : Low byte of the horizontal sync pulse width (LLINE) in start. (POR = 00000000) LPSPP[1:0] : The horizontal sync pulse subpixel start position (POR = 00) 9.37 set_vert_period Command Parameters 0xB6 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 0 1 1 0 B6 Parameter 1 1 Parameter 2 1 Parameter 3 1 Parameter 4 1 Parameter 5 1 Parameter 6 1 Parameter 7 1 0 0 0 0 0 VT10 VT9 VT8 xx VT7 VT6 VT5 VT4 VT3 VT2 VT1 VT0 xx 0 0 0 0 0 VPS10 VPS9 VPS8 xx VPS7 VPS6 VPS5 VPS4 VPS3 VPS2 VPS1 VPS0 xx 0 VPW6 VPW5 VPW4 VPW3 VPW2 VPW1 VPW0 xx 0 0 0 0 0 FPS10 FPS9 FPS8 xx FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPS0 xx Description Set the vertical blanking interval between last scan line and next LFRAME pulse VT[10:8] : VT[7:0] : High byte of the vertical total (display + non-display) period in lines (POR = 001) Low byte of the vertical total (display + non-display) period in lines (POR = 11101111) Vertical Total = (VT + 1) lines SSD1961 Rev 1.4 P 45/90 Apr 2012 Solomon Systech VPS[10:8] : VPS[7:0] : High byte the non-display period in lines between the start of the frame and the first display data in line. (POR = 000) The non-display period in lines between the start of the frame and the first display data in line. (POR = 00000100) Vertical Sync Pulse Start Position = VPS lines VPW[6:0] : Set the vertical sync pulse width (LFRAME) in lines. (POR = 000001) Vertical Sync Pulse Width = (VPW + 1) lines FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 000) FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 00000000) Vertical Display Period Start Position = FPS lines 9.38 get_vert_period Command Parameters 0xB7 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 0 1 1 1 B7 Parameter 1 1 Parameter 2 1 Parameter 3 1 Parameter 4 1 Parameter 5 1 Parameter 6 1 Parameter 7 1 0 0 0 0 0 VT10 VT9 VT8 xx VT7 VT6 VT5 VT4 VT3 VT2 VT1 VT0 xx 0 0 0 0 0 VPS10 VPS9 VPS8 xx VPS7 VPS6 VPS5 VPS4 VPS3 VPS2 VPS1 VPS0 xx 0 VPW6 VPW5 VPW4 VPW3 VPW2 VPW1 VPW0 xx 0 0 0 0 0 FPS10 FPS9 FPS8 xx FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPS0 xx Description Get the vertical blanking interval between last scan line and next LFRAME pulse VT[10:8] : High byte of the vertical total (display + non-display) period in lines (POR = 001) VT[7:0] : Low byte of the vertical total (display + non-display) period in lines (POR = 01111111) VPS[10:8] : High byte of the non-display period in lines between the start of the frame and the first display data in line. (POR = 000) VPS[7:0] : Low byte of the non-display period in lines between the start of the frame and the first display data in line. (POR = 00000100) VPW[6:0] : The vertical sync pulse width (LFRAME) in lines. (POR = 000001) FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 000) FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 00000000) Solomon Systech Apr 2012 P 46/90 Rev 1.4 SSD1961 9.39 set_gpio_conf Command Parameters 0xB8 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 0 0 0 B8 Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Parameter 2 1 0 0 0 0 0 0 0 B0 xx Description Set the GPIOs configuration. If the GPIOs are not used for LCD, set the direction. Otherwise, they are toggled with LCD signals by 0xC0 – 0xCF. A[7] : GPIO3 configuration (POR = 0) 0 GPIO3 is controlled by host 1 GPIO3 is controlled by LCDC A[6] : GPIO2 configuration (POR = 0) 0 GPIO2 is controlled by host 1 GPIO2 is controlled by LCDC A[5] : GPIO1 configuration (POR = 0) 0 GPIO1 is controlled by host 1 GPIO1 is controlled by LCDC A[4] : GPIO0 configuration (POR = 0) 0 GPIO0 is controlled by host 1 GPIO0 is controlled by LCDC A[3] : GPIO3 direction (POR = 0) 0 GPIO3 is input 1 GPIO3 is output A[2] : GPIO3 direction (POR = 0) 0 GPIO2 is input 1 GPIO2 is output A[1] : GPIO1 direction (POR = 0) 0 GPIO1 is input 1 GPIO1 is output A[0] : GPIO0 direction (POR = 0) 0 GPIO0 is input 1 GPIO0 is output B[0] : GPIO0 direction (POR = 0) 0 GPIO0 is used to control the panel power with Enter Sleep Mode 0x10 or Exit Sleep Mode 0x11. 1 GPIO0 is used as normal GPIO SSD1961 Rev 1.4 P 47/90 Apr 2012 Solomon Systech 9.40 get_gpio_conf Command Parameters 0xB9 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 0 0 1 B9 Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Parameter 2 1 0 0 0 0 0 0 0 B0 xx Description Get the current GPIOs configuration A[7] : GPIO3 configuration (POR = 0) 0 GPIO3 is controlled by host 1 GPIO3 is controlled by LCDC A[6] : GPIO2 configuration (POR = 0) 0 GPIO2 is controlled by host 1 GPIO2 is controlled by LCDC A[5] : GPIO1 configuration (POR = 0) 0 GPIO1 is controlled by host 1 GPIO1 is controlled by LCDC A[4] : GPIO0 configuration (POR = 0) 0 GPIO0 is controlled by host 1 GPIO0 is controlled by LCDC A[3] : GPIO3 direction (POR = 0) 0 GPIO3 is input 1 GPIO3 is output A[2] : GPIO3 direction (POR = 0) 0 GPIO2 is input 1 GPIO2 is output A[1] : GPIO1 direction (POR = 0) 0 GPIO1 is input 1 GPIO1 is output A[0] : GPIO0 direction (POR = 0) 0 GPIO0 is input 1 GPIO0 is output B[0] : GPIO0 direction (POR = 0) 0 GPIO0 is used to control the panel power with enter_sleep_mode (0x10) or exit_sleep_mode (0x11) 1 GPIO0 is used as normal GPIO Solomon Systech Apr 2012 P 48/90 Rev 1.4 SSD1961 9.41 set_gpio_value Command Parameters 0xBA 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 0 1 0 BA Parameter 1 1 0 0 0 0 A3 A2 A1 A0 xx Description Set GPIO value for GPIO configured as output A[3] : GPIO3 value (POR = 0) 0 GPIO3 outputs 0 1 GPIO3 outputs 1 A[2] : GPIO2 value (POR = 0) 0 GPIO2 outputs 0 1 GPIO2 outputs 1 A[1] : GPIO1 value (POR = 0) 0 GPIO1 outputs 0 1 GPIO1 outputs 1 A[0] : GPIO0 value (POR = 0) 0 GPIO0 outputs 0 1 GPIO0 outputs 1 9.42 get_gpio_status Command Parameters 0xBB 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 0 1 1 BB Parameter 1 1 0 0 0 0 A3 A2 A1 A0 xx Description Read current GPIO status. If the individual GPIO was configured as input, the value is the status of the corresponding pin. Otherwise, it is the programmed value. A[3] : GPIO3 value (POR : depends on pad value) 0 GPIO3 is pulled low 1 GPIO3 is pulled high A[2] : GPIO2 value (POR : depends on pad value) 0 GPIO2 is pulled low 1 GPIO2 is pulled high A[1] : GPIO1 value (POR : depends on pad value) 0 GPIO1 is pulled low 1 GPIO1 is pulled high A[0] : GPIO0 value (POR : depends on pad value) 0 GPIO0 is pulled low 1 GPIO0 is pulled high SSD1961 Rev 1.4 P 49/90 Apr 2012 Solomon Systech 9.43 set_post_proc Command Parameters 0xBC 4 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 1 0 0 BC Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Parameter 3 1 C7 C6 C5 C4 C3 C2 C1 C0 xx Parameter 4 1 0 0 0 0 0 0 0 D0 xx Description Set the image post processor A[7:0] : Set the contrast value (POR = 01000000) B[7:0] : Set the brightness value (POR = 10000000) C[7:0] : Set the saturation value (POR = 01000000) D[0] : Post Processor Enable (POR = 0) 0 Disable the postprocessor 1 Enable the postprocessor 9.44 get_post_proc Command Parameters 0xBD 4 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 1 0 1 BD Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Parameter 3 1 C7 C6 C5 C4 C3 C2 C1 C0 xx Parameter 4 1 0 0 0 0 0 0 0 D0 xx Description Get the image post processor A[7:0] : Get the contrast value (POR = 01000000) B[7:0] : Get the brightness value (POR = 10000000) C[7:0] : Get the saturation value (POR = 01000000) D[0] : Post Processor Enable (POR = 0) 0 Disable the postprocessor 1 Enable the postprocessor Solomon Systech Apr 2012 P 50/90 Rev 1.4 SSD1961 9.45 set_pwm_conf Command Parameters 0xBE 6 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 1 1 0 BE Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 1 PWMF7 PWMF6 PWMF5 PWMF4 PWMF3 PWMF2 PWMF1 PWMF0 xx 1 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 xx 1 0 0 0 0 C3 0 0 C0 xx 1 D7 D6 D5 D4 D3 D2 D1 D0 xx 1 E7 E6 E5 E4 E3 E2 E1 E0 xx 1 0 0 0 0 F3 F2 F1 F0 xx Description Set the PWM configuration PWMF[7:0] : Set the PWM frequency in system clock (POR = 00000000) PWM signal frequency = PLL clock / (256 * (PWMF[7:0] + 1)) / 256 PWM[7:0] : Set the PWM duty cycle (POR = 00000000) PWM duty cycle = PWM[7:0] / 256 for DBC disable (0xD0] A0 = 0 If DBC enable (0xD0] A0 = 1, these parameter will be ignored Note : PWM always 0 if PWM[7:0] = 00h Figure 9-19: PWM signal Period = 1/ PWM Freq PWM PWM[7:0]/256 * Period C[3] : PWM configuration (POR = 0) 0 PWM controlled by host 1 PWM controlled by DBC C[0] : PWM enable (POR = 0) 0 PWM disable 1 PWM enable D[7:0] : DBC manual brightness (POR = 00000000) Set the manual brightness level. When Manual Brightness Mode (0xD0) A[6] is enabled, the final DBC duty cycle output will be multiplied by this value / 255. PWM duty cycle = DBC output * D[7:0] / 255 00 Dimmest FF brightest E[7:0] : DBC minimum brightness (POR = 00000000) Set the minimum brightness level. When Manual Brightness Mode (0xD0) A[6] is enabled, DBC duty cycle output will be limited by this value. This will prevent from backlight being too dark or off. 00 Dimmest SSD1961 Rev 1.4 P 51/90 Apr 2012 Solomon Systech FF Brightest F[3:0] : Brightness prescaler (POR = 0000) Set the brightness prescaler to control how gradually the manual brightness is changed between different levels. There is a filter will undergo a number of iterations before the manual brightness saturated. This parameter is valid when Transition Effect enable (0xD0) A5 = 1 The iteration ration = system frequency / Divcode / 32768 F[3:0] Divcode 0000 off 0001 1 0010 2 0011 3 0100 4 0101 6 0110 8 0111 12 1000 16 1001 24 1010 32 1011 48 1100 64 1101 96 1110 128 1111 192 9.46 get_pwm_conf Command Parameters 0xBF 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 1 1 1 BF Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 1 PWMF7 PWMF6 PWMF5 PWMF4 PWMF3 PWMF2 PWMF1 PWMF0 xx 1 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 xx 1 0 0 0 0 C3 0 0 C0 xx 1 D7 D6 D5 D4 D3 D2 D1 D0 xx 1 E7 E6 E5 E4 E3 E2 E1 E0 xx 1 0 0 0 0 F3 F2 F1 F0 xx 1 G7 G6 G5 G4 G3 G2 G1 G0 xx Description Get the PWM configuration PWMF[7:0] : Get the PWM frequency in system clock (POR = 00000000) PWM[7:0] : Get the PWM duty cycle (POR = 00000000) C[3] : PWM configuration (POR = 0) 0 PWM controlled by host 1 PWM controlled by DBC C[0] : PWM enable (POR = 0) 0 PWM disable 1 PWM enable D[7:0] : DBC manual brightness (POR = 00000000) Get the brightness level 00 Dimmest FF brightest Solomon Systech Apr 2012 P 52/90 Rev 1.4 SSD1961 E[7:0] : DBC minimum brightness (POR = 00000000) Get the minimum brightness level. 00 Dimmest FF Brightest F[3:0] : Brightness prescaler (POR = 0000) Get the brightness prescaler G[7:0] : Dynamic backlight duty cycle : Get the current PWM duty cycle controlled by PWM (POR = 00000000) SSD1961 Rev 1.4 P 53/90 Apr 2012 Solomon Systech 9.47 set_lcd_gen0 Command Parameters 0xC0 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 0 0 0 C0 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF010 GF09 GF08 xx Parameter 3 1 GF07 GF06 GF05 GF04 GF03 GF02 GF01 GF00 xx Parameter 4 1 0 0 0 0 0 GR010 GR09 GR08 xx Parameter 5 1 GR07 GR06 GR05 GR04 GR03 GR02 GR01 GR00 xx Parameter 6 1 F7 F6 F5 F4 F3 GP010 GP09 GP08 xx Parameter 7 1 GP07 GP06 GP05 GP04 GP03 GP02 GP01 GP00 xx Description Set the rise, fall, period and toggling properties of LCD signal generator 0 A[7] : Reset LCD generator 0 at every frame start 0 The generator 0 will not reset in the starting point of a frame 1 The generator 0 will reset in the starting point of a frame GF0[10:8] : The highest 3 bits of the generator 0 falling position (POR = 000) GF0[7:0] : The lower byte of the generator 0 falling position (POR = 00000001) GR0[10:8] : The highest 3 bits of the generator 0 rising position (POR = 000) GR0[7:0] : The lower byte of the generator 0 rising position (POR = 00000000) F[7] : Force the generator 0 output to 0 in non-display period 0 generator 0 is normal 1 generator 0 output is forced to 0 in non-display period F[6:5] : Force the generator 0 output to 0 in odd or even lines 00 generator 0 is normal in both odd and even lines 01 generator 0 output is force to 0 in odd lines 10 generator 0 output is force to 0 in even lines 11 generator 0 is normal in both odd and even line F[4:3] : Generator 0 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP0[10:8] : The highest 3 bits of the generator 0 period (POR = 100) GP0[7:0] : The lower byte of the generator 0 period (POR = 00000000) Solomon Systech Apr 2012 P 54/90 Rev 1.4 SSD1961 9.48 get_lcd_gen0 Command Parameters 0xC1 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 0 0 1 C1 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF010 GF09 GF08 xx Parameter 3 1 GF07 GF06 GF05 GF04 GF03 GF02 GF01 GF00 xx Parameter 4 1 0 0 0 0 0 GR010 GR09 GR08 xx Parameter 5 1 GR07 GR06 GR05 GR04 GR03 GR02 GR01 GR00 xx Parameter 6 1 F7 F6 F5 F4 F3 GP010 GP09 GP08 xx Parameter 7 1 GP07 GP06 GP05 GP04 GP03 GP02 GP01 GP00 xx Description Get the rise, fall, period and toggling properties of LCD signal generator 0 A[7] : Reset LCD generator 0 at every frame start 0 The generator 0 will not reset in the starting point of a frame 1 The generator 0 will reset in the starting point of a frame GF0[10:8] : The highest 3 bits of the generator 0 falling position (POR = 000) GF0[7:0] : The lower byte of the generator 0 falling position (POR = 00000001) GR0[10:8] : The highest 3 bits of the generator 0 rising position (POR = 000) GR0[7:0] : The lower byte of the generator 0 rising position (POR = 00000000) F[7] : Force the generator 0 output to 0 in non-display period 0 generator 0 is normal 1 generator 0 output is forced to 0 in non-display period F[6:5] : Force the generator 0 output to 0 in odd or even lines 00 generator 0 is normal in both odd and even lines 01 generator 0 output is force to 0 in odd lines 10 generator 0 output is force to 0 in even lines 11 generator 0 is normal in both odd and even line F[4:3] : Generator 0 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP0[10:8] : The highest 3 bits of the generator 0 period (POR = 100) GP0[7:0] : The lower byte of the generator 0 period (POR = 00000000) SSD1961 Rev 1.4 P 55/90 Apr 2012 Solomon Systech 9.49 set_lcd_gen1 Command Parameters 0xC2 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 0 1 0 C2 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF110 GF19 GF18 xx Parameter 3 1 GF17 GF16 GF15 GF14 GF13 GF12 GF11 GF10 xx Parameter 4 1 0 0 0 0 0 GR110 GR19 GR18 xx Parameter 5 1 GR17 GR16 GR15 GR14 GR13 GR12 GR11 GR10 xx Parameter 6 1 F7 F6 F5 F4 F3 GP110 GP19 GP18 xx Parameter 7 1 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 xx Description Set the rise, fall, period and toggling properties of LCD signal generator 1 A[7] : Reset LCD generator 1 at every frame start 0 The generator 1 will not reset in the starting point of a frame 1 The generator 1 will reset in the starting point of a frame GF1[10:8] : The highest 3 bits of the generator 1 falling position (POR = 000) GF1[7:0] : The lower byte of the generator 1 falling position (POR = 00000001) GR1[10:8] : The highest 3 bits of the generator 1 rising position (POR = 000) GR1[7:0] : The lower byte of the generator 1 rising position (POR = 00000000) F[7] : Force the generator 1 output to 0 in non-display period 0 generator 1 is normal 1 generator 1 output is forced to 0 in non-display period F[6:5] : Force the generator 1 output to 0 in odd or even lines 00 generator 1 is normal in both odd and even lines 01 generator 1 output is force to 0 in odd lines 10 generator 1 output is force to 0 in even lines 11 generator 1 is normal in both odd and even line F[4:3] : Generator 1 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP1[10:8] : The highest 3 bits of the generator 1 period (POR = 100) GP1[7:0] : The lower byte of the generator 1 period (POR = 00000000) Solomon Systech Apr 2012 P 56/90 Rev 1.4 SSD1961 9.50 get_lcd_gen1 Command Parameters 0xC3 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 0 1 1 C3 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF110 GF19 GF18 xx Parameter 3 1 GF17 GF16 GF15 GF14 GF13 GF12 GF11 GF10 xx Parameter 4 1 0 0 0 0 0 GR110 GR19 GR18 xx Parameter 5 1 GR17 GR16 GR15 GR14 GR13 GR12 GR11 GR10 xx Parameter 6 1 F7 F6 F5 F4 F3 GP110 GP19 GP18 xx Parameter 7 1 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 xx Description Get the rise, fall, period and toggling properties of LCD signal generator 1 A[7] : Reset LCD generator 1 at every frame start 0 The generator 1 will not reset in the starting point of a frame 1 The generator 1 will reset in the starting point of a frame GF1[10:8] : The highest 3 bits of the generator 1 falling position (POR = 000) GF1[7:0] : The lower byte of the generator 1 falling position (POR = 00000001) GR1[10:8] : The highest 3 bits of the generator 1 rising position (POR = 000) GR1[7:0] : The lower byte of the generator 1 rising position (POR = 00000000) F[7] : Force the generator 1 output to 0 in non-display period 0 generator 1 is normal 1 generator 1 output is forced to 0 in non-display period F[6:5] : Force the generator 1 output to 0 in odd or even lines 00 generator 1 is normal in both odd and even lines 01 generator 1 output is force to 0 in odd lines 10 generator 1 output is force to 0 in even lines 11 generator 1 is normal in both odd and even line F[4:3] : Generator 1 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP1[10:8] : The highest 3 bits of the generator 1 period (POR = 100) GP1[7:0] : The lower byte of the generator 1 period (POR = 00000000) SSD1961 Rev 1.4 P 57/90 Apr 2012 Solomon Systech 9.51 set_lcd_gen2 Command Parameters 0xC4 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 1 0 0 C4 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF210 GF29 GF28 xx Parameter 3 1 GF27 GF26 GF25 GF24 GF23 GF22 GF21 GF20 xx Parameter 4 1 0 0 0 0 0 GR210 GR29 GR28 xx Parameter 5 1 GR27 GR26 GR25 GR24 GR23 GR22 GR21 GR20 xx Parameter 6 1 F7 F6 F5 F4 F3 GP210 GP29 GP28 xx Parameter 7 1 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 xx Description Set the rise, fall, period and toggling properties of LCD signal generator 2 A[7] : Reset LCD generator 2 at every frame start 0 The generator 2 will not reset in the starting point of a frame 1 The generator 2 will reset in the starting point of a frame GF2[10:8] : The highest 3 bits of the generator 2 falling position (POR = 000) GF2[7:0] : The lower byte of the generator 2 falling position (POR = 00000001) GR2[10:8] : The highest 3 bits of the generator 2 rising position (POR = 000) GR2[7:0] : The lower byte of the generator 2 rising position (POR = 00000000) F[7] : Force the generator 2 output to 0 in non-display period 0 generator 2 is normal 1 generator 2 output is forced to 0 in non-display period F[6:5] : Force the generator 2 output to 0 in odd or even lines 00 generator 2 is normal in both odd and even lines 01 generator 2 output is force to 0 in odd lines 10 generator 2 output is force to 0 in even lines 11 generator 2 is normal in both odd and even line F[4:3] : Generator 2 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP2[10:8] : The highest 3 bits of the generator 2 period (POR = 100) GP2[7:0] : The lower byte of the generator 2 period (POR = 00000000) Solomon Systech Apr 2012 P 58/90 Rev 1.4 SSD1961 9.52 get_lcd_gen2 Command Parameters 0xC5 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 1 0 1 C5 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF210 GF29 GF28 xx Parameter 3 1 GF27 GF26 GF25 GF24 GF23 GF22 GF21 GF20 xx Parameter 4 1 0 0 0 0 0 GR210 GR29 GR28 xx Parameter 5 1 GR27 GR26 GR25 GR24 GR23 GR22 GR21 GR20 xx Parameter 6 1 F7 F6 F5 F4 F3 GP210 GP29 GP28 xx Parameter 7 1 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 xx Description Get the rise, fall, period and toggling properties of LCD signal generator 2 A[7] : Reset LCD generator 2 at every frame start 0 The generator 2 will not reset in the starting point of a frame 1 The generator 2 will reset in the starting point of a frame GF2[10:8] : The highest 3 bits of the generator 2 falling position (POR = 000) GF2[7:0] : The lower byte of the generator 2 falling position (POR = 00000001) GR2[10:8] : The highest 3 bits of the generator 2 rising position (POR = 000) GR2[7:0] : The lower byte of the generator 2 rising position (POR = 00000000) F[7] : Force the generator 2 output to 0 in non-display period 0 generator 2 is normal 1 generator 2 output is forced to 0 in non-display period F[6:5] : Force the generator 2 output to 0 in odd or even lines 00 generator 2 is normal in both odd and even lines 01 generator 2 output is force to 0 in odd lines 10 generator 2 output is force to 0 in even lines 11 generator 2 is normal in both odd and even line F[4:3] : Generator 2 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP2[10:8] : The highest 3 bits of the generator 2 period (POR = 100) GP2[7:0] : The lower byte of the generator 2 period (POR = 00000000) SSD1961 Rev 1.4 P 59/90 Apr 2012 Solomon Systech 9.53 set_lcd_gen3 Command Parameters 0xC6 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 1 1 0 C6 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF310 GF39 GF38 xx Parameter 3 1 GF37 GF36 GF35 GF34 GF33 GF32 GF31 GF30 xx Parameter 4 1 0 0 0 0 0 GR310 GR39 GR38 xx Parameter 5 1 GR37 GR36 GR35 GR34 GR33 GR32 GR31 GR30 xx Parameter 6 1 F7 F6 F5 F4 F3 GP310 GP39 GP38 xx Parameter 7 1 GP37 GP36 GP35 GP34 GP33 GP32 GP31 GP30 xx Description Set the rise, fall, period and toggling properties of LCD signal generator 3 A[7] : Reset LCD generator 3 at every frame start 0 The generator 3 will not reset in the starting point of a frame 1 The generator 3 will reset in the starting point of a frame GF3[10:8] : The highest 3 bits of the generator 3 falling position (POR = 000) GF3[7:0] : The lower byte of the generator 3 falling position (POR = 00000001) GR3[10:8] : The highest 3 bits of the generator 3 rising position (POR = 000) GR3[7:0] : The lower byte of the generator 3 rising position (POR = 00000000) F[7] : Force the generator 3 output to 0 in non-display period 0 generator 3 is normal 1 generator 3 output is forced to 0 in non-display period F[6:5] : Force the generator 3 output to 0 in odd or even lines 00 generator 3 is normal in both odd and even lines 01 generator 3 output is force to 0 in odd lines 10 generator 3 output is force to 0 in even lines 11 generator 3 is normal in both odd and even line F[4:3] : Generator 3 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP3[10:8] : The highest 3 bits of the generator 3 period (POR = 100) GP3[7:0] : The lower byte of the generator 3 period (POR = 00000000) Solomon Systech Apr 2012 P 60/90 Rev 1.4 SSD1961 9.54 get_lcd_gen3 Command Parameters 0xC7 7 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 0 1 1 1 C7 Parameter 1 1 A7 0 0 0 0 0 0 0 xx Parameter 2 1 0 0 0 0 0 GF310 GF39 GF38 xx Parameter 3 1 GF37 GF36 GF35 GF34 GF33 GF32 GF31 GF30 xx Parameter 4 1 0 0 0 0 0 GR310 GR39 GR38 xx Parameter 5 1 GR37 GR36 GR35 GR34 GR33 GR32 GR31 GR30 xx Parameter 6 1 F7 F6 F5 F4 F3 GP310 GP39 GP38 xx Parameter 7 1 GP37 GP36 GP35 GP34 GP33 GP32 GP31 GP30 xx Description Get the rise, fall, period and toggling properties of LCD signal generator 3 A[7] : Reset LCD generator 3 at every frame start 0 The generator 3 will not reset in the starting point of a frame 1 The generator 3 will reset in the starting point of a frame GF3[10:8] : The highest 3 bits of the generator 3 falling position (POR = 000) GF3[7:0] : The lower byte of the generator 3 falling position (POR = 00000001) GR3[10:8] : The highest 3 bits of the generator 3 rising position (POR = 000) GR3[7:0] : The lower byte of the generator 3 rising position (POR = 00000000) F[7] : Force the generator 3 output to 0 in non-display period 0 generator 3 is normal 1 generator 3 output is forced to 0 in non-display period F[6:5] : Force the generator 3 output to 0 in odd or even lines 00 generator 3 is normal in both odd and even lines 01 generator 3 output is force to 0 in odd lines 10 generator 3 output is force to 0 in even lines 11 generator 3 is normal in both odd and even line F[4:3] : Generator 3 toggle mode 00 Disable 01 Toggle by pixel clock (LSHIFT) 10 Toggle by Line (LLINE) 11 Toggle by Frame (LFRAME) GP3[10:8] : The highest 3 bits of the generator 3 period (POR = 100) GP3[7:0] : The lower byte of the generator 3 period (POR = 00000000) SSD1961 Rev 1.4 P 61/90 Apr 2012 Solomon Systech 9.55 set_gpio0_rop Command Parameters 0xC8 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 0 0 0 C8 Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Set the GPIO0 with respect to the LCD signal generators using ROP operation. No effect if the GPIO0 is configured as general GPIO. A[6:5] : Source 1 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[3:2] : Source 2 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO0 (POR = 00000000) Please refer to the Application note for the ROP operation 9.56 get_gpio0_rop Command Parameters 0xC9 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 0 0 1 C9 Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Get the GPIO0 properties with respect to the LCD signal generators. A[6:5] : Source 1 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 Solomon Systech Apr 2012 P 62/90 Rev 1.4 SSD1961 A[3:2] : Source 2 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO0 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO0 (POR = 00000000) Please refer to the Application note for the ROP operation 9.57 set_gpio1_rop Command Parameters 0xCA 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 0 1 0 CA Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Set the GPIO1 with respect to the LCD signal generators using ROP operation. No effect if the GPIO1 is configured as general GPIO. A[6:5] : Source 1 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[3:2] : Source 2 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO1 (POR = 00000000) Please refer to the Application note for the ROP operation SSD1961 Rev 1.4 P 63/90 Apr 2012 Solomon Systech 9.58 get_gpio1_rop Command Parameters 0xCB 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 0 1 1 CB Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Get the GPIO1 properties with respect to the LCD signal generators. A[6:5] : Source 1 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[3:2] : Source 2 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO1 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO1 (POR = 00000000) Please refer to the Application note for the ROP operation 9.59 set_gpio2_rop Command Parameters 0xCC 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 1 0 0 CC Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Set the GPIO2 with respect to the LCD signal generators using ROP operation. No effect if the GPIO2 is configured as general GPIO. A[6:5] : Source 1 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 Solomon Systech Apr 2012 P 64/90 Rev 1.4 SSD1961 A[3:2] : Source 2 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO2 (POR = 00000000) Please refer to the Application note for the ROP operation 9.60 get_gpio2_rop Command Parameters 0xCD 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 1 0 1 CD Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Get the GPIO2 properties with respect to the LCD signal generators. A[6:5] : Source 1 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[3:2] : Source 2 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO2 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO2 (POR = 00000000) Please refer to the Application note for the ROP operation SSD1961 Rev 1.4 P 65/90 Apr 2012 Solomon Systech 9.61 set_gpio3_rop Command Parameters 0xCE 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 1 1 0 CE Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Set the GPIO3 with respect to the LCD signal generators using ROP operation. No effect if the GPIO3 is configured as general GPIO. A[6:5] : Source 1 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[3:2] : Source 2 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO3 (POR = 00000000) Please refer to the Application note for the ROP operation 9.62 get_gpio3_rop Command Parameters 0xCF 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 0 1 1 1 1 CF Parameter 1 1 0 A6 A5 0 A3 A2 A1 A0 xx Parameter 2 1 B7 B6 B5 B4 B3 B2 B1 B0 xx Description Get the GPIO3 properties with respect to the LCD signal generators. A[6:5] : Source 1 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 Solomon Systech Apr 2012 P 66/90 Rev 1.4 SSD1961 A[3:2] : Source 2 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 A[1:0] : Source 3 for GPIO3 when controlled by LCDC (POR = 00) 00 Generator 0 01 Generator 1 10 Generator 2 11 Generator 3 B[7:0] : ROP operation to mux the source 1, 2 and 3 for GPIO3 (POR = 00000000) Please refer to the Application note for the ROP operation 9.63 set_dbc_conf Command Parameters 0xD0 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 1 0 0 0 0 D0 Parameter 1 1 0 A6 A5 0 A3 A2 0 A0 xx Description Set the Dynamic Backlight Control configuration. A[6] : DBC Manual Brightness enable (POR = 1) 0 Enable 1 Disable A[5] : Transition effect (POR = 0) 0 Transition effect disable 1 Transition effect enable Transition effect is used to remove visible backlight flickering. If rapid brightness change is required, it is recommended to enable this bit. A[3:2] : Energy saving selection for DBC (POR = 00) 00 DBC is disable 01 Conservative mode 10 Normal mode 11 Aggressive mode A[0] : Master enable of DBC (POR = 0) 0 DBC disable 1 DBC enable SSD1961 Rev 1.4 P 67/90 Apr 2012 Solomon Systech The hardware pin, PWM is the output signal from SSD1961 to the system backlight driver. So it should configure PWM module before enable DBC. WRITE COMMAND “0xBE” WRITE DATA “0x0E” (set PWM frequency) WRITE DATA “0xFF” (dummy value if DBC is used) WRITE DATA “0x09” (enable PWM controlled by DBC) WRITE DATA “0xFF” WRITE DATA “0x00” WRITE DATA “0x00” WRITE COMMAND “0xD4” WRITE DATA ….. (Define the threshold value) WRITE COMMAND “0xD0” WRITE DATA “0x0D” (Enable DBC with Aggressive mode) 9.64 get_dbc_conf Command Parameters 0xD1 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 1 0 0 0 1 D1 Parameter 1 1 0 A6 A5 0 A3 A2 1 A0 xx Description Get the current dynamic back light configuration. A[6] : DBC Manual Brightness enable (POR = 1) 0 Enable 1 Disable A[5] : Transition effect (POR = 0) 0 Transition effect disable 1 Transition effect enable A[3:2] : Energy saving selection for DBC (POR = 00) 00 DBC is disable 01 Conservative mode 10 Normal mode 11 Aggressive mode A[0] : Master enable DBC (POR = 0) 0 DBC disable 1 DBC enable Solomon Systech Apr 2012 P 68/90 Rev 1.4 SSD1961 9.65 set_dbc_th Command Parameters 0xD4 9 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 1 0 1 0 0 D4 Parameter 1 1 0 0 0 0 0 0 0 DBC_TH116 xx Parameter 2 1 DBC_TH115 DBC_TH114 DBC_TH113 DBC_TH112 DBC_TH111 DBC_TH110 DBC_TH19 DBC_TH18 xx Parameter 3 1 DBC_TH17 DBC_TH16 DBC_TH15 DBC_TH14 DBC_TH13 DBC_TH12 DBC_TH11 DBC_TH10 xx Parameter 4 1 0 0 0 0 0 0 0 DBC_TH216 xx Parameter 5 1 DBC_TH215 DBC_TH214 DBC_TH213 DBC_TH212 DBC_TH211 DBC_TH210 DBC_TH29 DBC_TH28 xx Parameter 6 1 DBC_TH27 DBC_TH26 DBC_TH25 DBC_TH24 DBC_TH23 DBC_TH22 DBC_TH21 DBC_TH20 xx Parameter 7 1 0 0 0 0 0 0 0 DBC_TH316 xx Parameter 8 1 DBC_TH315 DBC_TH314 DBC_TH313 DBC_TH312 DBC_TH311 DBC_TH310 DBC_TH39 DBC_TH38 xx Parameter 9 1 DBC_TH37 DBC_TH36 DBC_TH35 DBC_TH34 DBC_TH33 DBC_TH32 DBC_TH31 DBC_TH30 xx Description Set the threshold for each level of power saving. DBC_TH1[16] : High byte of the threshold setting for the Conservative mode of DBC. (POR = 0) DBC_TH1[15:8] : 2nd byte of the threshold setting for the Conservative mode of DBC. (POR = 00000000) DBC_TH1[7:0] : Low byte of the threshold setting for the Conservative mode of DBC. (POR = 00000000) TH1 = display width * display height * 3 * 0.1 /16 DBC_TH2[16] : High byte of the threshold setting for the Normal mode of DBC. (POR = 0) DBC_TH2[15:8] : 2nd byte of the threshold setting for the Normal mode of DBC. (POR = 00000000) DBC_TH2[7:0] : Low byte of the threshold setting for the Normal mode of DBC. (POR = 00000000) TH2 = display width * display height * 3 * 0.25 /16 DBC_TH3[16] : High byte of the threshold setting for the Aggressive mode of DBC. (POR = 0) DBC_TH3[15:8] : 2nd byte of the threshold setting for the Aggressive mode of DBC. (POR = 00000000) DBC_TH3[7:0] : Low byte of the threshold setting for the Aggressive mode of DBC. (POR = 00000000) TH3 = display width * display height * 3 * 0.6 /16 SSD1961 Rev 1.4 P 69/90 Apr 2012 Solomon Systech 9.66 get_dbc_th Command Parameters 0xD5 9 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 0 1 0 1 0 1 D5 Parameter 1 1 0 0 0 0 0 0 0 DBC_TH116 xx Parameter 2 1 DBC_TH115 DBC_TH114 DBC_TH113 DBC_TH112 DBC_TH111 DBC_TH110 DBC_TH19 DBC_TH18 xx Parameter 3 1 DBC_TH17 DBC_TH16 DBC_TH15 DBC_TH14 DBC_TH13 DBC_TH12 DBC_TH11 DBC_TH10 xx Parameter 4 1 0 0 0 0 0 0 0 DBC_TH216 xx Parameter 5 1 DBC_TH215 DBC_TH214 DBC_TH213 DBC_TH212 DBC_TH211 DBC_TH210 DBC_TH29 DBC_TH28 xx Parameter 6 1 DBC_TH27 DBC_TH26 DBC_TH25 DBC_TH24 DBC_TH23 DBC_TH22 DBC_TH21 DBC_TH20 xx Parameter 7 1 0 0 0 0 0 0 0 DBC_TH316 xx Parameter 8 1 DBC_TH315 DBC_TH314 DBC_TH313 DBC_TH312 DBC_TH311 DBC_TH310 DBC_TH39 DBC_TH38 xx Parameter 9 1 DBC_TH37 DBC_TH36 DBC_TH35 DBC_TH34 DBC_TH33 DBC_TH32 DBC_TH31 DBC_TH30 xx Description Get the threshold for each level of power saving. DBC_TH1[16] : High byte of the threshold setting for the Conservative mode of DBC. (POR = 0) DBC_TH1[15:8] : 2nd byte of the threshold setting for the Conservative mode of DBC. (POR = 00000000) DBC_TH1[7:0] : Low byte of the threshold setting for the Conservative mode of DBC. (POR = 00000000) DBC_TH2[16] : High byte of the threshold setting for the Normal mode of DBC. (POR = 0) DBC_TH2[15:8] : 2nd byte of the threshold setting for the Normal mode of DBC. (POR = 00000000) DBC_TH2[7:0] : Low byte of the threshold setting for the Normal mode of DBC. (POR = 00000000) DBC_TH3[16] : High byte of the threshold setting for the Aggressive mode of DBC. (POR = 0) DBC_TH3[15:8] : 2nd byte of the threshold setting for the Aggressive mode of DBC. (POR = 00000000) DBC_TH3[7:0] : Low byte of the threshold setting for the Aggressive mode of DBC. (POR = 00000000) 9.67 set_pll Command Parameters 0xE0 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 0 0 0 E0 Parameter 1 1 0 0 0 0 0 0 A1 A0 xx Description Start the PLL. Before the start, the system was operated with the crystal oscillator or clock input. A[1] : Lock PLL (POR = 0) After PLL enabled for 100us, can start to lock PLL 0 Use reference clock as system clock 1 Use PLL output as system clock A[0] : Enable PLL (POR = 0) 0 Disable PLL 1 Enable PLL Solomon Systech Apr 2012 P 70/90 Rev 1.4 SSD1961 Before enabling PLL, the PLL setting (“0xE2”) have to be configured first. After PLL enabled for 100us, can start to lock PLL. SSD1961 needed to switch to PLL output as system clock after PLL is locked. The following is the program sequence. WRITE COMMAND “0xE0” WRITE DATA “0x01” Wait 100us to let the PLL stable WRITE COMMAND “0xE0” WRITE DATA “0x03” WRITE COMMAND “0x01” * Note : SSD1961 is operating under reference clock before PLL is locked, registers cannot be set faster than half of the reference clock frequency. For instance, SSD1961 with a 10MHz reference clock is not allowed to be programmed higher than 5M words/s. 9.68 set_pll_mn Command Parameters 0xE2 3 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 0 1 0 E2 Parameter 1 1 M7 M6 M5 M4 M3 M2 M1 M0 xx Parameter 2 1 0 0 1 N4 N3 N2 N1 N0 xx Parameter 3 1 0 0 0 0 0 C2 0 0 xx Description Set the MN of PLL M[7:0] : Multiplier (M) of PLL. (POR = 00101101) N[4:0] : Divider (N) of PLL. (POR = 00011) C[2] : Effectuate MN value (POR = 0) 0 Ignore the multiplier (M) and divider (N) values 1 Effectuate the multiplier and divider value VCO = Reference input clock x (M + 1) PLL frequency = VCO / (N + 1) * Note : 250MHz < VCO < 800MHz For a 10MHz reference clock to obtain 100MHz PLL frequency, user cannot program M = 19 and N = 1. The setting in this situation is setting M=29 and N=2, where 10 x 30 / 3 = 100MHz. WRITE COMMAND “0xE2” WRITE DATA “0x1D” (M=29) WRITE DATA “0x02” (N=2) WRITE DATA “0x54” (Dummy Byte) SSD1961 Rev 1.4 P 71/90 Apr 2012 Solomon Systech 9.69 get_pll_mn Command Parameters 0xE3 3 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 0 1 1 E3 Parameter 1 1 M7 M6 M5 M4 M3 M2 M1 M0 xx Parameter 2 1 0 0 1 N4 N3 N2 N1 N0 xx Parameter 3 1 0 0 0 0 0 C2 0 0 xx Description Get the MN setting of PLL M[7:0] : Multiplier (M) of PLL. (POR = 00101101) N[4:0] : Divider (N) of PLL. (POR = 00011) C[2] : Effectuate MN value (POR = 0) 0 Ignore the multiplier (M) and divider (N) values 1 Effectuate the multiplier and divider value 9.70 get_pll_status Command Parameters 0xE4 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 1 0 0 E4 Parameter 1 1 0 0 0 0 0 A2 0 0 xx Description Get the PLL status A[2] : PLL Lock 0 Not locked 1 Locked 9.71 set_deep_sleep Command Parameters 0xE5 None D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 1 0 1 E5 Description Set deep sleep mode. PLL would be stopped. It needs to issue 2 dummy read to exit Deep Sleep mode. Solomon Systech Apr 2012 P 72/90 Rev 1.4 SSD1961 9.72 set_lshift_freq Command Parameters 0xE6 3 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 1 1 0 E6 Parameter 1 1 0 0 0 0 LCDC_FPR19 LCDC_FPR18 LCDC_FPR17 LCDC_FPR16 xx Parameter 2 1 LCDC_FPR15 LCDC_FPR14 LCDC_FPR13 LCDC_FPR12 LCDC_FPR11 LCDC_FPR10 LCDC_FPR9 LCDC_FPR8 xx Parameter 3 1 LCDC_FPR7 LCDC_FPR6 LCDC_FPR 5 LCDC_FPR4 LCDC_FPR 3 LCDC_FPR2 LCDC_FPR1 LCDC_FPR0 xx Description Set the LSHIFT (pixel clock) frequency LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings. (POR = 0111) LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings. (POR = 11111111) LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings. (POR = 11111111) Configure the pixel clock to PLL freq x ((LCDC_FPR + 1) / 220) To obtain PCLK = 5.3MHz with PLL Frequency = 100MHz, 5.3MHz = 100MHz *( LCDC_FPR + 1) / 220 LCDC_FPR = 55574 WRITE COMMAND “0xE6” WRITE DATA “0x00” (LCDC_FPR = 55574) WRITE DATA “0xD9” WRITE DATA “0x16” For serial LCD interface: Configure the pixel clock to PLL freq x ((LCDC_FPR + 1) / 220) *4 To obtain PCLK = 5.3MHz with PLL Frequency = 100MHz, 5.3MHz = 100MHz * ( ( LCDC_FPR+ 1) / 220 )*4 LCDC_FPR = 13892 WRITE COMMAND “0xE6” WRITE DATA “0x00” (LCDC_FPR = 13892) WRITE DATA “0x36” WRITE DATA “0x44” 9.73 get_lshift_freq Command Parameters 0xE7 3 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 0 0 1 1 1 E7 Parameter 1 1 0 0 0 0 LCDC_FPR19 LCDC_FPR18 LCDC_FPR17 LCDC_FPR16 xx Parameter 2 1 LCDC_FPR15 LCDC_FPR14 LCDC_FPR13 LCDC_FPR12 LCDC_FPR11 LCDC_FPR10 LCDC_FPR9 LCDC_FPR8 xx Parameter 3 1 LCDC_FPR7 LCDC_FPR6 LCDC_FPR 5 LCDC_FPR4 LCDC_FPR 3 LCDC_FPR2 LCDC_FPR1 LCDC_FPR0 xx Description Get the current LSHIFT (pixel clock) frequency setting SSD1961 Rev 1.4 P 73/90 Apr 2012 Solomon Systech LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings. (POR = 0111) LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings. (POR = 11111111) LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings. (POR = 11111111) Solomon Systech Apr 2012 P 74/90 Rev 1.4 SSD1961 9.74 set_pixel_data_interface Command Parameters 0xF0 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 1 0 0 0 0 F0 Parameter 1 1 0 0 0 0 0 A2 A1 A0 xx Description Set the pixel data format to 8-bit / 9-bit / 12-bit / 16-bit / 16-bit(565) / 18-bit in the parallel host processor interface. This command is used for display data only, the command format is always 8 bit. A[2:0] : Pixel Data Interface Format (POR = 101) 000 8-bit 001 12-bit 010 16-bit packed 011 16-bit (565 format) 100 18-bit 110 9-bit Others Reserved * Note : The un-used data bus will be driven to ground by SSD1961, so don’t connect the un-used data bus to MCU. 9.75 get_pixel_data_interface Command Parameters 0xF1 1 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 1 1 1 0 0 0 1 F1 Parameter 1 1 0 0 0 0 0 A2 A1 A0 xx Description Get the current pixel data format settings in the parallel host processor interface. A[2:0] : Pixel Data Interface Format (POR = 101) 000 8-bit 001 12-bit 010 16-bit packed 011 16-bit (565 format) 100 18-bit 110 9-bit Others Reserved SSD1961 Rev 1.4 P 75/90 Apr 2012 Solomon Systech 10 MAXIMUM RATINGS Symbol VDDD VDDPLL VDDLCD VDDIO VIN VOUT TA TSTG Table 10-1: Maximum Ratings (Voltage Referenced to VSS) Parameter Digital Core power supply PLL power supply LCD Interface power supply I/O power supply Input Voltage Output Voltage Solder Temperature / Time Storage temperature Value Unit -0.5 to 1.8 V -0.5 to 1.8 V -0.5 to 4.6 V -0.5 to 4.6 V -0.5 to 4.6 V -0.5 to 4.6 V 225 for 40 sec max at solder ball oC -45 to 125 oC Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VIN and VOUT be constrained to the range VSS < (VIN or VOUT) < VDDIO. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either VSS or VDDIO). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. 11 RECOMMENDED OPERATING CONDITIONS Table 11-1: Recommended Operating Condition Symbol VDDD VDDPLL VDDLCD VDDIO TA Parameter Digital Core power supply PLL power supply LCD Interface power supply I/O power supply Operating temperature Min Typ Max Unit 1.10 1.2 1.30 V 1.10 1.2 1.30 V 1.65 3.3 3.6 V 1.65 3.3 3.6 V -30 25 85 oC 11.1 Power-up sequence Figure 11-1: Power-up Sequence Note Clock reference is only applicable when CLK is used. Solomon Systech Apr 2012 P 76/90 Rev 1.4 SSD1961 12 DC CHARACTERISTICS Conditions: Voltage referenced to VSS VDDD, VDDPLL = 1.2V VDDIO, VDDLCD = 3.3V TA = 25°C Symbol PSTY IIZ IOZ VOH VOL VIH VIL Table 12-1: DC Characteristics Parameter Quiescent Power Input leakage current Output leakage current Output high voltage Output low voltage Input high voltage Input low voltage Test Condition Min -1 -1 0.8VDDIO Typ 300 0.8VDDIO Max Unit 500 uW 1 uA 1 uA V 0.2VDDIO V VDDIO + 0.5 V 0.2VDDIO V 13 AC CHARACTERISTICS Conditions: Voltage referenced to VSS VDDD, VDDPLL = 1.2V VDDIO, VDDLCD = 3.3V TA = 25°C CL = 50pF (Bus/CPU Interface) CL = 0pF (LCD Panel Interface) 13.1 Clock Timing Table 13-1: Clock Input Requirements for CLK (PLL-bypass) Symbol FCLK TCLK Parameter Input Clock Frequency (CLK) Input Clock period (CLK) Min 1/fCLK Max 110 Units MHz ns Table 13-2: Clock Input Requirements for CLK (PLL-enabled) Symbol FCLK TCLK Parameter Input Clock Frequency (CLK) Input Clock period (CLK) Min 2.5 1/fCLK Max 50 Units MHz ns Table 13-3: Clock Input Requirements for crystal oscillator XTAL (PLL-enabled) Symbol FXTAL TXTAL Parameter Input Clock Frequency Input Clock period Min 2.5 1/fXTAL Max 10 Units MHz ns SSD1961 Rev 1.4 P 77/90 Apr 2012 Solomon Systech 13.2 MCU Interface Timing 13.2.1 Parallel 6800-series Interface Timing Table 13-4: Parallel 6800-series Interface Timing Characteristics (Use CS# as clock) Symbol Parameter Min Typ Max fMCLK System Clock Frequency* 1 - 110 tMCLK System Clock Period* 1/ fMCLK - - tPWCSH tPWCSL tAS tAH tDSW tDHW tPLW tPHW tPLWR tACC tDHR tR tF Control Pulse High Width Write Read Control Pulse Low Width Write (next write cycle) Write (next read cycle) Read Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Low Time Write High Time Read Low Time Data Access Time Output Hold time Rise Time Fall Time 13 30 1.5* tMCLK 3.5* tMCLK - 13 1.5* tMCLK 80 9* tMCLK - 80 9* tMCLK 2 - - 2 - - 4 - - 1 - - 14 - - 14 - - 38 - - 32 - - 1 - - - - 0.5 - - 0.5 * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 13-1: Parallel 6800-series Interface Timing Diagram (Use CS# as Clock) D/C R/W VIH VIL VIH tAS VIL CS# tF VIH E VIL D[17:0] (WRITE) D[17:0] (READ) tAH tPLWR / tPLW tR tPWCSH VIH VIL tACC tDSW Valid Data tDHW VOH tDHR Valid Data VOL tPWCSL Solomon Systech Apr 2012 P 78/90 Rev 1.4 SSD1961 Table 13-5: Parallel 6800-series Interface Timing Characteristics (Use E as clock) Symbol Parameter Min Typ Max fMCLK tMCLK tPWCSH tPWCSL tAS tAH tDSW tDHW tPLW tPHW tPLWR tACC tDHR tR tF System Clock Frequency* System Clock Period* Control Pulse High Width Write Read Control Pulse Low Width Write (next write cycle) Write (next read cycle) Read Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Low Time Write High Time Read Low Time Data Access Time Output Hold time Rise Time Fall Time 1 - 110 1/ fMCLK - - 13 30 1.5* tMCLK 3.5* tMCLK - 13 1.5* tMCLK 80 9* tMCLK - 80 9* tMCLK 2 - - 2 - - 4 - - 1 - - 14 - - 14 - - 38 - - 32 - - 1 - - - - 0.5 - - 0.5 * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 13-2: Parallel 6800-series Interface Timing Diagram (Use E as Clock) VIH D/C VIL VIH tAS tAH R/W VIL CS# VIH VIL tPWCSL tF E tPHWR / tPHW VIH VIH D[17:0] (WRITE) VIH tDSW Valid Data VIL tR tDHW D[17:0] (READ) tACC VOH VOL tDHR Valid Data tPWCSH SSD1961 Rev 1.4 P 79/90 Apr 2012 Solomon Systech 13.2.2 Parallel 8080-series Interface Timing Table 13-6: Parallel 8080-series Interface Timing Characteristics Symbol Parameter Min Typ Max fMCLK tMCLK tPWCSH tPWCSL tAS tAH tDSW tDHW tPWLW tDHR tACC tPWLR tR tF tCS tCSH System Clock Frequency* System Clock Period* Control Pulse High Width Write Read Control Pulse Low Width Write (next write cycle) Write (next read cycle) Read Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Write Low Time Read Data Hold Time Access Time Read Low Time Rise Time Fall Time Chip select setup time Chip select hold time to read signal 1 - 110 1/ fMCLK - - 13 30 1.5* tMCLK 3.5* tMCLK - 13 1.5* tMCLK 80 9* tMCLK - 80 9* tMCLK 1 - - 2 - - 4 - - 1 - - 12 - - 1 - - 32 - - 36 - - - - 0.5 - - 0.5 2 - - 3 - - * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CS# D/C# WR# D[17:0] Figure 13-3: Parallel 8080-series Interface Timing Diagram (Write Cycle) V IH V IL t CS VIH VIL t AS V IH VIL t PWCSL AH t F t R t PWLW t DSW t DHW V IH Valid Data VIL t PWCSH Solomon Systech Apr 2012 P 80/90 Rev 1.4 SSD1961 Figure 13-4: Parallel 8080-series Interface Timing Diagram (Read Cycle) t PWCSL CS# D/C# RD# D[17:0] V IH V IL t CS VIH VIL t AS t F t AH t R t V IH PWLR VIL t ACC t CSH t DHR VOH Valid Data VOL t PWCSH SSD1961 Rev 1.4 P 81/90 Apr 2012 Solomon Systech 13.3 Parallel LCD Interface Timing FPS LFRAME LLINE Figure 13-5: Generic TFT Panel Timing VT (= 1 Frame) VPW VPS VDP LDEN LDATA[17:0] LPS LLINE HPW LSHIFT LDEN LDATA[17:0] HPS HT (= 1 Line) HDP Solomon Systech Apr 2012 P 82/90 Rev 1.4 SSD1961 13.4 Serial RGB Interface Timing Figure 13-6: Serial RGB Interface Timing (without dummy mode) VT (= 1 Frame) FPS VPW LFRAME LLINE VPS VDP LDEN LDATA[7:0] LPS LLINE HPW HT (= 1 Line) LSHIFT LDEN LDATA[7:0] HPS HDP RG B RG B SSD1961 Rev 1.4 P 83/90 Apr 2012 Solomon Systech Figure 13-7: Serial RGB Interface Timing (with dummy mode) VT (= 1 Frame) FPS VPW LFRAME LLINE VPS VDP LDEN LDATA[7:0] LPS LLINE HPW HT (= 1 Line) LSHIFT LDEN LDATA[7:0] HPS HDP RG B RG B Solomon Systech Apr 2012 P 84/90 Rev 1.4 SSD1961 Table 13-7: Quick reference table for LCD parameter setting LCD Parameter Corresponding setting Command Register VDP HDP 0xB0 VDP[10:0] HDP[10:0] LPS LPS[10:0] HPW HPS 0xB4 HPW[6:0] HPS[10:0] HT FPS VPW VPS VT 0xB6 HT[10:0] FPS[10:0] VPW[6:0] VPS[10:0] VT[10:0] Maximum Setting Parallel mode Serial mode 2048 Vertical panel size = (VDP + 1) pixels 2048 Horizontal panel size = (HDP + 1) pixels 2047 8188 (2047 x 4) 128 512 (HPW + 1) pixels (128 x4) 2047 8188 (2047 x 4) 2048 Horizontal Total = (HT + 1) lines 2047 128 Vertical Sync Pulse Width = (VPW+1) lines 2047 2048 Vertical Total = (VT + 1) lines SSD1961 Rev 1.4 P 85/90 Apr 2012 Solomon Systech 14 APPLICATION EXAMPLE Figure 14-1: Application circuit for SSD1961 (With Direct clock input) SSD1961 MCU 2.5-10MHz RESET CS# D/C# E(RD#) R/W#(WR#) D[17:0] TE GPIO1 GPIO2 GPIO3 CONF LFRAME LLINE LDEN LSHIFT CLK LDATA[17:12] LDATA[11:6] LDATA[5:0] XTAL_IN GPIO0 PWM Floated XTAL_OUT VDDD VDDPLL VDDIO VDDLCD Dumb Display 1.2V+/-10% SCL SDA CS# VSYNC HSYNC DEN PCLK R[5:0] G[5:0] B[5:0] SHUT PWM 1uF 1.2V+/-10% 1uF 1.65-3.6V 0.1uF 1.65-3.6V 0.1uF Solomon Systech Apr 2012 P 86/90 Rev 1.4 SSD1961 Figure 14-2: Application circuit for SSD1961 (With crystal oscillator input) SSD1961 MCU RESET CS# D/C# E(RD#) R/W#(WR#) D[17:0] TE GPIO1 GPIO2 GPIO3 CONF LFRAME LLINE LDEN LSHIFT CLK LDATA[17:12] LDATA[11:6] LDATA[5:0] GPIO0 XTAL_OUT PWM 120 ohm 2.5-10MHz XTAL_IN VDDD 5pF 5pF VDDPLL VDDIO VDDLCD Dumb Display 1.2V+/-10% SCL SDA CS# VSYNC HSYNC DEN PCLK R[5:0] G[5:0] B[5:0] SHUT PWM 1uF 1.2V+/-10% 1uF 1.65-3.6V 0.1uF 1.65-3.6V 0.1uF SSD1961 Rev 1.4 P 87/90 Apr 2012 Solomon Systech 15 PACKAGE INFORMATION 15.1 Package Mechanical Drawing for TFBGA Symbol A A1 A2 A3 b D E e D1 E1 Solomon Systech Dimension in mm Min Typical Max -- --- 1.1 0.16 --- 0.26 --- 0.21 --- --- 0.54 --- 0.27 --- 0.37 --- 6.00 BSC --- --- 6.00 BSC --- --- 0.65 --- --- 4.55 BSC --- --- 4.55 BSC --- Apr 2012 P 88/90 Rev 1.4 SSD1961 15.2 Tape & Reel Drawing for TFBGA SSD1961 Rev 1.4 P 89/90 Apr 2012 Solomon Systech Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. The product(s) listed in this datasheet comply with Directive 2002/95/EC of the European Parliament and of the council of 27 January 2004 on the restriction of the use of certain hazardous substances in electrical and electronic equipment and People’s Republic of China Electronic Industry Standard SJ/T 11363-2006 “Requirements for concentration limits for certain hazardous substances in electronic information products (电子信息产品中有毒有害物质的限量要求)”. Hazardous Substances test report is available upon request. http://www.solomon-systech.com Solomon Systech Apr 2012 P 90/90 Rev 1.4 SSD1961

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