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pcie_dma文档

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标签: pciedma

Virtex-5 FPGA Integrated Endpoint Block for

PCI Express Designs: DDR2 SDRAM DMA

Initiator Demonstration Platform

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R XAPP859 v11 July 31 2008 Application Note Virtex5 FPGAs Virtex5 FPGA Integrated Endpoint Block for PCI Express Designs DDR2 SDRAM DMA Initiator Demonstration Platform Authors Kraig Lund David Naylor and Steve Trynosky Summary Introduction This application note provides a reference design for endpointinitiated Direct Memory Access DMA data transfers using the LogiCORE Endpoint Block Plus for Virtex5 FPGAs The reference design targets the ML555 hardware platform and uses the onboard DDR2 mem......

R XAPP859 (v1.1) July 31, 2008 Application Note: Virtex-5 FPGAs Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs: DDR2 SDRAM DMA Initiator Demonstration Platform Authors: Kraig Lund, David Naylor, and Steve Trynosky Summary Introduction This application note provides a reference design for endpoint-initiated Direct Memory Access (DMA) data transfers using the LogiCORE™ Endpoint Block Plus for Virtex®-5 FPGAs. The reference design targets the ML555 hardware platform and uses the on-board DDR2 memory for storing DMA data. The design illustrates how to create an 8-lane endpoint design with an interface to a DDR2 memory. The reference design can also target an ML505 hardware platform to showcase DMA performance in a 1-lane endpoint design. A driver and GUI application are provided to allocate and initialize a system memory buffer in the host PC and set up DMA transfers. The design demonstrates how to transmit and receive transaction layer packets as a DMA initiator as well as respond to target transactions. The reference design in this application note provides an interface between the Virtex-5 FPGA integrated Endpoint block for PCI Express® designs and a single-rank, 64-bit, 256 MB DDR2 SDRAM memory. The reference design runs on the Virtex-5 FPGA ML555 development board for PCI Express designs. The reference design has these features: • Supports endpoint-to-root complex DMA full duplex read and write transactions initiated by the Endpoint on the Virtex-5 FPGA ML555 development board for PCI Express designs. The host processor controls and monitors DMA transfers utilizing Programmed Input/Output (PIO) accesses to a register file contained in the endpoint FPGA design. • Uses the LogiCORE Endpoint Block Plus wrapper for PCI Express designs, which includes the Virtex-5 FPGA integrated Endpoint block for PCI Express designs. • Uses a DDR2 small outline dual in-line memory module (SODIMM) memory controller generated by the Xilinx® Memory Interface Generator (MIG) tool. Targets the XC5VLX50T-1FFG1136C production silicon FPGA. • • Requires a PC running Microsoft Windows XP with one available 8-lane PCIe add-in-card • slot (the ML555 board is plugged into this slot). Includes a driver generated by Jungo, Ltd. WinDriver for accessing devices on the PCI bus. • Offers user-controlled DMA initiator control and status functions through a graphical user interface (GUI) application running on the PC. The Virtex-5 FPGA ML555 Development Kit for PCI Express designs includes the ML555 board with an 8-lane PCIe interface used to implement 4-lane or 8-lane designs. Figure 1 shows a block diagram of the system solution. © Copyright 2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. XAPP859 (v1.1) July 31, 2008 www.xilinx.com 1 Reference System X-Ref Target - Figure 1 ML555 GUI Application – Scans PCI System – Allocates Host System Memory Buffer – Initializes Buffer Contents – Displays Buffer Contents – Provides Read and Write Access to Endpoint Register File R CPU Root Complex Host System Memory Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express ML555 User Application 8-Lane PCIe DMA Support Register File MIG DDR2 Controller 256 MB DDR2 SODIMM XC5VLX50T Programmable Clock Source X859_01_040408 Figure 1: System Block Diagram of the Endpoint DMA Initiator for PCI Express Reference System This section describes the system design elements, including: • • • Driver generated by WinDriver and user application software Endpoint bus mastering DMA initiator control and status FPGA reference design elements Endpoint Bus Mastering DMA Initiator Control and Status Control and status of the Endpoint DMA initiator is provided through a GUI. The GUI provides control inputs to the processor and receives status outputs from the endpoint user application. The host processor provides user control over DMA initiator functions, including: • DMA transfer direction: ♦ Read: PC host system memory transfer to ML555 DDR2 memory. ♦ Write: ML555 DDR2 memory transfer to PC host system memory. • DMA transfer size: 128, 256, 512, 1K, 2K, 4K, 8K, 16K, 32K, 64K, 128K, 256K, 512K, or 1M bytes. In full duplex mode, read and write DMA transfer sizes can be different. The hardware supports a DMA transfer size of 128 x m bytes (m = 1 through 8192), while the GUI application software supports 128 x 2n bytes (n = 0 through 13). • Number of DMA transfers: 1, 25, 50, 75, or 100. This parameter denotes the number of • • times to repeat a given transfer. Status display showing the host system memory base address: The base address is automatically determined during the ML555 GUI launch process. The system memory buffer can be initialized with a predefined pattern, and the buffer can be printed to a log window. Selection of host system memory address offset: 0, 128, 256, 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K bytes. XAPP859 (v1.1) July 31, 2008 www.xilinx.com 2 Reference System R • • Selection of ML555 DDR2 Endpoint memory address offset: 0, 128, 256, 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K bytes. Start DMA transfer options: run demonstration, read DMA, write DMA, or full duplex DMA operations. • Display of ML555 Endpoint DMA controller register file contents. • PCI Express configuration space display window: This window shows information relevant to the ML555 board/system PCIe link including maximum read request size, maximum payload size (MPS), read completion boundary (RCB) from the endpoint devices link control register (which can be set by the host processor’s PCI Express configuration software), and negotiated link width (in lanes) of the DMA interface connection. Demonstration mode runs through a complete sequence of read/write DMA transactions and computes DMA performance for each transfer. For a detailed explanation of transaction layer throughput, see “Understanding PCI Express Transaction Layer Throughput,” page 45. Upon completion of a DMA operation, the host PC processor firmware calculates the DMA performance for the requested transaction and prints the result to the GUI log window. The DMA performance does not include any overhead from the software setup of the host system but does include DDR2 memory access latency for DMA writes. DMA performance for reads includes the time to create memory read request packets, the turnaround time from Endpoint to root to Endpoint, and receipt of the last completion packet with data. DMA read performance does not include the time to write data into the ML555 DDR2 memory. FPGA Reference Design Elements This section describes the functions of the main FPGA design elements included in the reference design. The top-level design file is called pcie_dma_top and instantiates several low-level modules: • The LogiCORE Endpoint Block Plus wrapper for PCI Express designs found in the CORE Generator™ software is titled endpoint_blk_plus_. The user application logic wrapper for PCI Express designs is titled pcie_dma_wrapper. The user application logic to DDR2 controller wrapper for PCI Express designs is titled dma_ddr2_if. The MIG DDR2 memory controller top-level design file is titled mem_interface_top. • • • LogiCORE Endpoint Block Plus Wrapper for PCI Express Designs Access to the LogiCORE Endpoint Block Plus wrapper is delivered in simulation-only mode to allow evaluation of the core in a system-level simulation. ISE® software, version 10.1 or higher must be installed on the system. The license to use the Endpoint Block Plus wrapper for PCI Express designs is provided at no-charge. To register, the designer is required to accept the licensing agreement and must be registered to gain access to the protected area lounge. Users need to register and obtain a full license to generate a bitstream. The license request area is password protected, but all licensed Xilinx customers can request access to this area located on the Xilinx website at: http://www.xilinx.com/ipcenter/pcie_blkplus_lounge/pcie_blkplus_registration.htm. For this design, the CORE Generator software is used to create the Virtex-5 FPGA Endpoint Block Plus wrapper for PCI Express. The wrapper configures the integrated transceivers and integrated Endpoint block. It also connects the GTP transceiver to the integrated Endpoint block, and connects block RAM elements for the transmit, receive, and retry buffers. For additional information on this LogiCORE product, please go to the following sites: • • http://www.xilinx.com/products/ipcenter/V5_PCI_Express_Block_Plus.htm http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci- express_v5pciexpressblockplus.htm XAPP859 (v1.1) July 31, 2008 www.xilinx.com 3 Reference System R • http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf The screen captures in Figure 2 to Figure 9 from the CORE Generator software show the parameters created using the Endpoint Block Plus for PCI Express in this reference design. X-Ref Target - Figure 2 Figure 2: Endpoint Block Plus Wrapper for PCI Express, Page 1 of 8 X859_02_041008 X-Ref Target - Figure 3 Figure 3: Endpoint Block Plus Wrapper for PCI Express, Page 2 of 8 X859_03_041008 XAPP859 (v1.1) July 31, 2008 www.xilinx.com 4 Reference System X-Ref Target - Figure 4 R Figure 4: Endpoint Block Plus Wrapper for PCI Express, Page 3 of 8 X859_04_041008 X-Ref Target - Figure 5 Figure 5: Endpoint Block Plus Wrapper for PCI Express, Page 4 of 8 X859_05_041008 XAPP859 (v1.1) July 31, 2008 www.xilinx.com 5
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