首页资源分类电子电路模拟及混合电路 > ad623芯片资料

ad623芯片资料

已有 445176个资源

下载专区

电子电路热门资源

本周本月全部

文档信息举报收藏

标    签:ad623

分    享:

文档简介

ad623芯片详细描述

文档预览

a Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier FEATURES Easy to Use Higher Performance than Discrete Design Single and Dual Supply Operation Rail-to-Rail Output Swing Input Voltage Range Extends 150 mV Below Ground (Single Supply) Low Power, 575 ␮A Max Supply Current Gain Set with One External Resistor Gain Range 1 (No Resistor) to 1,000 HIGH ACCURACY DC PERFORMANCE 0.1% Gain Accuracy (G = 1) 0.35% Gain Accuracy (G > 1) 25 ppm Gain Drift (G = 1) 200 ␮V Max Input Offset Voltage (AD623A) 2 ␮V/؇C Max Input Offset Drift (AD623A) 100 ␮V Max Input Offset Voltage (AD623B) 1 ␮V/؇C Max Input Offset Drift (AD623B) 25 nA Max Input Bias Current NOISE 35 nV/√Hz RTI Noise @ 1 kHz (G = 1) EXCELLENT AC SPECIFICATIONS 90 dB Min CMRR (G = 10); 84 dB Min CMRR (G = 5) (@ 60 Hz, 1K Source Imbalance) 800 kHz Bandwidth (G = 1) 20 ␮s Settling Time to 0.01% (G = 10) APPLICATIONS Low Power Medical Instrumentation Transducer Interface Thermocouple Amplifier Industrial Process Controls Difference Amplifier Low Power Data Acquisition PRODUCT DESCRIPTION The AD623 is an integrated single supply instrumentation amplifier that delivers rail-to-rail output swing on a single supply (+3 V to +12 V supplies). The AD623 offers superior user flexibility by allowing single gain set resistor programming, and conforming to the 8-lead industry standard pinout configuration. With no external resistor, the AD623 is configured for unity gain (G = 1) and with an external resistor, the AD623 can be programmed for gains up to 1,000. The AD623 holds errors to a minimum by providing superior AC CMRR that increases with increasing gain. Line noise, as well as line harmonics, will be rejected since the CMRR remains constant up to 200 Hz. The AD623 has a wide input AD623 CONNECTION DIAGRAM 8-Lead Plastic DIP (N), SOIC (R) and ␮SOIC (RM) Packages ؊RG 1 ؊IN 2 ؉IN 3 ؊VS 4 AD623 8 ؉RG 7 ؉VS 6 OUTPUT 5 REF common-mode range and can amplify signals that have a common-mode voltage 150 mV below ground. Although the design of the AD623 has been optimized to operate from a single supply, the AD623 still provides superior performance when operated from a dual voltage supply (± 2.5 V to ± 6.0 V). Low power consumption (1.5 mW at 3 V), wide supply voltage range, and rail-to-rail output swing make the AD623 ideal for battery powered applications. The rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. The AD623 replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability and reliability in a minimum of space. Until the AD623, this level of instrumentation amplifier performance has not been achieved. CMR – dB 120 110 100 x1000 90 x100 80 70 x10 60 50 x1 40 30 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 1. CMR vs. Frequency, +5 VS, 0 VS REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD623–SPECIFICATIONS SINGLE SUPPLY (typical @ +25؇C Single Supply, VS = +5 V, and RL = 10 k⍀, unless otherwise noted) Model Specification GAIN Gain Range Gain Error1 G=1 G = 10 G = 100 G = 1000 Nonlinearity, G = 1–1000 Gain vs. Temperature G=1 G > 11 VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, VOSO Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range2 Common-Mode Rejection at 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 Conditions G = 1 + (100 k/RG) G1 VOUT = 0.05 V to 3.5 V G > 1 VOUT = 0.05 V to 4.5 V G1 VOUT = 0.05 V to 3.5 V G > 1 VOUT = 0.05 V to 4.5 V Total RTI Error = VOSI + VOSO/G VS = +3 V to +12 V VCM = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V RL = 10 kΩ RL = 100 kΩ VS = +5 V Step Size: 3.5 V Step Size: 4 V, VCM = 1.8 V AD623A Min Typ Max 1 1000 AD623ARM Min Typ Max 1 1000 AD623B Min Typ Max 1 1000 Units 0.03 0.10 0.10 0.35 0.10 0.35 0.10 0.35 0.03 0.10 0.10 0.35 0.10 0.35 0.10 0.35 0.03 0.05 % 0.10 0.35 % 0.10 0.35 % 0.10 0.35 % 50 5 10 50 50 5 10 50 50 5 10 50 ppm ppm/°C ppm/°C 25 200 350 0.1 2 200 1000 1500 2.5 10 200 500 650 0.1 2 500 2000 2600 2.5 10 25 100 160 0.1 1 200 500 1100 2.5 10 µV µV µV/°C µV µV µV/°C 80 100 80 100 80 100 dB 100 120 100 120 100 120 dB 120 140 120 140 120 140 dB 120 140 120 140 120 140 dB 17 25 27.5 25 0.25 2 2.5 5 17 25 27.5 25 0.25 2 2.5 5 17 25 27.5 25 0.25 2 2.5 5 nA nA pA/°C nA nA pA/°C 2ʈ2 2ʈ2 (–VS) – 0.15 2ʈ2 2ʈ2 (+VS) – 1.5 (–VS) – 0.15 2ʈ2 2ʈ2 (+VS) – 1.5 (–VS) – 0.15 (+VS) – 1.5 GΩʈpF GΩʈpF V 70 90 105 105 +0.01 +0.01 80 70 100 90 110 105 110 105 (+VS) – 0.5 +0.01 (+VS) – 0.15 +0.01 80 77 100 94 110 105 110 105 (+VS) – 0.5 +0.01 (+VS) – 0.15 +0.01 86 dB 100 dB 110 dB 110 dB (+VS) – 0.5 V (+VS) – 0.15 V 800 800 800 kHz 100 100 100 kHz 10 10 10 kHz 2 2 2 kHz 0.3 0.3 0.3 V/µs 30 30 30 µs 20 20 20 µs –2– REV. C AD623 DUAL SUPPLIES (typical @ +25؇C Dual Supply, VS = ؎5 V, and RL = 10 k⍀, unless otherwise noted) Model Specification GAIN Gain Range Gain Error1 G=1 G = 10 G = 100 G = 1000 Nonlinearity, G = 1–1000 Gain vs. Temperature G=1 G > 11 Conditions G = 1 + (100 k/RG) G1 VOUT = –4.8 V to 3.5 V G > 1 VOUT = 0.05 V to 4.5 V G1 VOUT = –4.8 V to 3.5 V G > 1 VOUT = –4.8 V to 4.5 V AD623A Min Typ Max 1 1000 0.03 0.10 0.10 0.35 0.10 0.35 0.10 0.35 50 5 10 50 AD623ARM Min Typ Max 1 1000 0.03 0.10 0.10 0.35 0.10 0.35 0.10 0.35 50 5 10 50 AD623B Min Typ Max 1 1000 Units 0.03 0.05 % 0.10 0.35 % 0.10 0.35 % 0.10 0.35 % 50 5 10 50 ppm ppm/°C ppm/°C VOLTAGE OFFSET Total RTI Error = Input Offset, VOSI Over Temperature VOSI + VOSO/G Average TC Output Offset, VOSO Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 80 G = 10 100 G = 100 120 G = 1000 120 25 200 350 0.1 2 200 1000 1500 2.5 10 100 80 120 100 140 120 140 120 200 500 650 0.1 2 500 2000 2600 2.5 10 100 120 140 140 25 100 160 0.1 1 200 500 1100 2.5 10 µV µV µV/°C µV µV µV/°C 80 100 dB 100 120 dB 120 140 dB 120 140 dB INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC 17 25 27.5 25 0.25 2 2.5 5 17 25 27.5 25 0.25 2 2.5 5 17 25 27.5 25 0.25 2 2.5 5 nA nA pA/°C nA nA pA/°C INPUT Input Impedance Differential Common-Mode Input Voltage Range2 VS = +2.5 V to ± 6 V Common-Mode Rejection at 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 VCM = +3.5 V to –5.15 V VCM = +3.5 V to –5.15 V VCM = +3.5 V to –5.15 V VCM = +3.5 V to –5.15 V OUTPUT Output Swing RL = 10 kΩ, VS = ± 5 V RL = 100 kΩ DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 VS = ± 5 V, 5 V Step 2ʈ2 2ʈ2 (–VS) – 0.15 70 80 90 100 105 110 105 110 (–VS) +0. 2 (–VS) + 0.05 800 100 10 2 0.3 30 20 2ʈ2 2ʈ2 (+VS) – 1.5 (–VS) –0.15 (+VS) – 1.5 2ʈ2 2ʈ2 (–VS) – 0.15 70 80 90 100 105 110 105 110 77 86 94 100 105 110 105 110 (+VS) – 0.5 (–VS) + 0.2 (+VS) – 0.15 (–VS) + 0.05 (+VS) – 0.5 (–VS) + 0.2 (+VS) – 0.15 (–VS) + 0.05 800 800 100 100 10 10 2 2 0.3 0.3 30 30 20 20 GΩʈpF GΩʈpF (+VS) – 1.5 V dB dB dB dB (+VS) – 0.5 V (+VS) – 0.15 V kHz kHz kHz kHz V/µs µs µs REV. C –3– AD623–SPECIFICATIONS BOTH DUAL AND SINGLE SUPPLIES Model Specification Conditions AD623A Min Typ Max AD623ARM Min Typ Max AD623B Min Typ Max Units NOISE Voltage Noise, 1 kHz Total RTI Noise =   eni 2  +   eno /G 2   Input, Voltage Noise, eni 35 Output, Voltage Noise, eno 50 RTI, 0.1 Hz to 10 Hz G=1 3.0 G = 1000 1.5 Current Noise f = 1 kHz 100 0.1 Hz to 10 Hz 1.5 35 35 nV/√Hz 50 50 nV/√Hz 3.0 3.0 µV p-p 1.5 1.5 µV p-p 100 100 fA/√Hz 1.5 1.5 pA p-p REFERENCE INPUT RIN IIN Voltage Range Gain to Output VIN+, VREF = 0 100 ± 20% 100 ± 20% 100 ± 20% kΩ +50 +60 +50 +60 +50 +60 µA –VS +VS –VS +VS –VS +VS V 1 ± 0.0002 1 ± 0.0002 1 ± 0.0002 V POWER SUPPLY Operating Range Quiescent Current Over Temperature Dual Supply Single Supply Dual Supply Single Supply ± 2.5 ±6 ± 2.5 ±6 ± 2.5 ±6 V +2.7 +12 +2.7 +12 +2.7 +12 V 375 550 375 550 375 550 µA 305 480 305 480 305 480 µA 625 625 625 µA TEMPERATURE RANGE For Specified Performance –40 to +85 –40 to +85 –40 to +85 °C NOTES 1Does not include effects of external resistor RG. 2One input grounded. G = 1. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 650 mW Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range (N, R, RM) . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C Operating Temperature Range (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . +300°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 8-Lead Plastic DIP Package: θJA = 95°C/W 8-Lead SOIC Package: θJA = 155°C/W 8-Lead µSOIC Package: θJA = 200°C/W ORDERING GUIDE Model AD623AN AD623AR AD623ARM AD623AR-REEL AD623AR-REEL7 AD623ARM-REEL AD623ARM-REEL7 AD623BN AD623BR AD623BR-REEL AD623BR-REEL7 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Plastic DIP 8-Lead SOIC 8-Lead µSOIC 13" Tape and Reel 7" Tape and Reel 13" Tape and Reel 7" Tape and Reel 8-Lead Plastic DIP 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel Package Option N-8 SO-8 RM-8 SO-8 SO-8 RM-8 RM-8 N-8 SO-8 SO-8 SO-8 Brand Code J0A J0A J0A ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD623 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. C Typical Characteristics(@ +25؇C VS = ؎5 V, RL = 10 k⍀ unless otherwise – noted) AD623 UNITS 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 120 140 INPUT OFFSET VOLTAGE – ␮V Figure 2. Typical Distribution of Input Offset Voltage; Package Option N-8, SO-8 UNITS 22 20 18 16 14 12 10 8 6 4 2 0 –600 –500 –400 –300 –200 –100 0 100 200 300 400 500 OUTPUT OFFSET VOLTAGE – ␮V Figure 5. Typical Distribution of Output Offset Voltage, VS = +5, Single Supply, VREF = –0.125 V; Package Option N-8, SO-8 UNITS 480 420 360 300 240 180 120 60 0 –800 –600 –400 –200 0 200 400 600 800 OUTPUT OFFSET VOLTAGE ؊ ␮V Figure 3. Typical Distribution of Output Offset Voltage; Package Option N-8, SO-8 UNITS 210 180 150 120 90 60 30 0 –0.245 –0.24 –0.235 –0.23 –0.225 –0.22 –0.215 –0.21 INPUT OFFSET CURRENT – nA Figure 6. Typical Distribution for Input Offset Current; Package Option N-8, SO-8 UNITS 22 20 18 16 14 12 10 8 6 4 2 0 –80 –60 –40 –20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE – ␮V Figure 4. Typical Distribution of Input Offset Voltage, VS = +5, Single Supply, VREF = –0.125 V; Package Option N-8, SO-8 UNITS 20 18 16 14 12 10 8 6 4 2 0 –0.025 –0.02 –0.015 –0.01 –0.005 0 0.005 0.01 INPUT OFFSET CURRENT – nA Figure 7. Typical Distribution for Input Offset Current, VS = +5, Single Supply, VREF = –0.125 V; Package Option N-8, SO-8 REV. C –5– UNITS AD623 1600 1400 1200 1000 800 600 400 200 0 75 80 85 90 95 100 105 110 115 120 125 130 CMRR ؊ dB Figure 8. Typical Distribution for CMRR (G = 1) 1k IBIAS – nA 30 25 20 15 10 5 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – ؇C Figure 11. IBIAS vs. Temp 1k CURRENT NOISE – fA/ΊHz NOISE – nV/ΊHz, RTI 100 GAIN = 1 100 GAIN = 10 GAIN = 100 GAIN = 1000 10 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 9. Voltage Noise Spectral Density vs. Frequency 10 1 10 100 1k FREQUENCY – Hz Figure 12. Current Noise Spectral Density vs. Frequency IBIAS – nA 21 20 19 18 17 16 15 –5 –4 –2 0 2 4 CMV – Volts Figure 10. IBIAS vs. CMV, VS = ±5 V IBIAS – nA 19.5 19.0 18.5 18.0 17.5 17.0 16.5 –3 –2 –1 0 1 CMV – Volts Figure 13. IBIAS vs. CMV, VS = ±2.5 V –6– REV. C Figure 14. 0.1 Hz to 10 Hz Current Noise (0.71 pA/Div) CMR – dB AD623 120 110 100 x1000 x10 90 x1 80 x100 70 60 50 40 30 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 17. CMR vs. Frequency, ±5 VS RTO RTI Figure 15. 0.1 Hz to 10 Hz RTI Voltage Noise (1 Div = 1 µV p-p) CMR – dB 120 110 100 90 80 70 60 50 40 30 1 x1000 x100 x10 x1 10 100 1k 10k 100k FREQUENCY – Hz Figure 16. CMR vs. Frequency, +5, 0 VS, VREF = 2.5 V 70 60 50 40 GAIN – dB 30 20 10 0 –10 –20 –30 100 1k 10k 100k 1M FREQUENCY – Hz Figure 18. Gain vs. Frequency (VS = +5 V, 0 V), VREF = 2.5 V OUTPUT – Volts 5 4 VS = ؎5 3 2 VS = ؎2.5 1 0 –1 –2 –3 –4 –5 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 COMMON MODE INPUT – Volts Figure 19. Maximum Output Voltage vs. Common Mode, G = 1, RL = 100 kΩ REV. C –7– AD623 5 4 VS = ؎5 3 VS = ؎2.5 2 OUTPUT – Volts 1 0 –1 –2 –3 –4 –5 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 COMMON MODE INPUT – Volts Figure 20. Maximum Output Voltage vs. Common Mode, G ≥ 10, RL = 100 kΩ 5 4 OUTPUT – Volts 3 2 1 0 –1 0 1 2 3 4 5 COMMON MODE INPUT – Volts Figure 21. Maximum Output Voltage vs. Common Mode, G = 1, VS = +5 V, RL = 100 kΩ 5 4 OUTPUT – Volts 3 2 1 0 –1 0 1 2 3 4 5 COMMON MODE INPUT – Volts Figure 22. Maximum Output Voltage vs. Common Mode, G ≥ 10, VS = +5 V, RL = 100 kΩ PSRR – dB 140 G = 1000 120 G = 100 100 80 60 40 G = 10 20 G=1 0 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 23. Positive PSRR vs. Frequency, ±5 VS 140 G = 1000 120 G = 100 100 PSRR – dB 80 60 40 G = 10 20 G=1 0 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 24. Positive PSRR vs. Frequency, +5 VS, 0 VS PSRR – dB 140 G = 1000 120 G = 100 100 80 G = 10 60 G=1 40 20 0 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 25. Negative PSRR vs. Frequency, ±5 VS –8– REV. C V p–p 10 8 6 4 VS = ؎2.5 2 VS = ؎5 0 0 20 40 60 80 100 FREQUENCY – kHz Figure 26. Large Signal Response, G ≤ 10 1000 AD623 Figure 29. Large Signal Pulse Response and Settling Time, G = –10 (0.250 mV = 0.01%), CL = 100 pF 100 SETTLING TIME – ␮s 10 1 1 10 100 1000 GAIN – V/V Figure 27. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output, CL = 100 pF, VS = ±5 V Figure 30. Large Signal Pulse Response and Settling Time, G = 100, CL = 100 pF Figure 28. Large Signal Pulse Response and Settling Time, G = –1 (0.250 mV = 0.01%), CL = 100 pF Figure 31. Large Signal Pulse Response and Settling Time, G = –1000 (5 mV = 0.01%), CL = 100 pF REV. C –9– AD623 Figure 32. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF Figure 35. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF Figure 33. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF Figure 36. Gain Nonlinearity, G = –1 (50 ppm/Div) Figure 34. Small Signal Pulse Response G = 100, RL = 10 kΩ, CL = 100 pF Figure 37. Gain Nonlinearity, G = –10 (6 ppm/Div) –10– REV. C AD623 The output voltage at Pin 6 is measured with respect to the potential at Pin 5. The impedance of the reference pin is 100 kΩ, so in applications requiring V/I conversion, a small resistor between Pins 5 and 6 is all that is needed. Figure 38. Gain Nonlinearity (G = –100, 15 ppm/Div) V+ (V+) –0.5 (V+) –1.5 (V+) –1.5 POS SUPPLY 7 INVERTING 2 4 1 + – 50k⍀ 50k⍀ GAIN 8 7 NONINVERTING 3 50k⍀ – + 4 NEG SUPPLY 50k⍀ 50k⍀ – + 50k⍀ OUT 6 REF 5 Figure 40. Simplified Schematic The bandwidth of the AD623 is reduced as the gain is increased, since all the amplifiers are of voltage feedback type. At unity gain, it is the output amplifier that limits the bandwidth. Therefore even at higher gains the AD623 bandwidth does not roll off as quickly. SWING – Volts (V–) +0.5 V– 0 0.5 1 1.5 2 OUTPUT CURRENT – mA Figure 39. Output Voltage Swing vs. Output Current THEORY OF OPERATION The AD623 is an instrumentation amplifier based on a modified classic three op amp approach, to assure single or dual supply operation even at common-mode voltages at the negative supply rail. Low voltage offsets, input and output, as well as absolute gain accuracy, and one external resistor to set the gain, make the AD623 one of the most versatile instrumentation amplifiers in its class. The input signal is applied to PNP transistors acting as voltage buffers and providing a common-mode signal to the input amplifiers (Figure 40). An absolute value 50 kΩ resistor in each of the amplifiers’ feedback assures gain programmability. The differential output is VO =  1 + 100 kΩ RG   V C The differential voltage is then converted to a single-ended voltage using the output amplifier, which also rejects any commonmode signal at the output of the input amplifiers. Since all the amplifiers can swing to either supply rails, as well as have their common-mode range extended to below the negative supply rail, the range over which the AD623 can operate is further enhanced (Figures 19 and 20). APPLICATIONS Basic Connection Figure 41 shows the basic connection circuit for the AD623. The +VS and –VS terminals are connected to the power supply. The supply can be either bipolar (VS = ± 2.5 V to ± 6 V) or single supply (–VS = 0 V, +VS = 3.0 V to 12 V). Power supplies should be capacitively decoupled close to the devices power pins. For best results, use surface mount 0.1 µF ceramic chip capacitors and 10 µF electrolytic tantalum capacitors. The input voltage, which can be either single-ended (tie either –IN or +IN to ground) or differential is amplified by the programmed gain. The output signal appears as the voltage difference between the Output pin and the externally applied voltage on the REF input. For a ground referenced output, REF should be grounded. GAIN SELECTION The AD623’s gain is resistor programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD623 is designed to offer accurate gains using 0.1%–1% tolerance resistors. Table I shows required values of RG for various gains. Note that for G = 1, the RG terminals are uncon- nected (RG = ϱ). For any arbitrary gain, RG can be calculated by using the formula RG = 100 kΩ/(G – 1) REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output. The reference terminal is also useful when bipolar signals are being amplified as it can be used to provide a virtual ground voltage. The voltage on the reference terminal can be varied from –VS to +VS. REV. C –11– AD623 +VS +2.5V TO +6V 0.1␮F 10␮F +VS +3V TO +12V 0.1␮F 10␮F VIN RG RG OUTPUT RG REF 0.1␮F VOUT REF (INPUT) 10␮F VIN RG RG OUTPUT RG REF VOUT REF (INPUT) –2.5V TO –6V –VS a. Dual Supply b. Single Supply Figure 41. Basic Connections Table I. Required Values of Gain Resistors Desired Gain 2 5 10 20 33 40 50 65 100 200 500 1000 1% Std Table Value of RG, ⍀ 100 k 24.9 k 11 k 5.23 k 3.09 k 2.55 k 2.05 k 1.58 k 1.02 k 499 200 100 Calculated Gain Using 1% Resistors 2 5.02 10.09 20.12 33.36 40.21 49.78 64.29 99.04 201.4 501 1001 INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD623 are attributed to two sources, input and output errors. The output error is divided by the programmed gain when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total VOS for a given gain is calculated as: Total Error RTI = Input Error + (Output Error/G) Total Error RTO = (Input Error × G) + Output Error RTI offset errors and noise voltages for different gains are shown below in Table II. Table II. RTI Error Sources Max Total Input Offset Error Gain ␮V ␮V Max Total Input Offset Drift ␮V/؇C ␮V/؇C Total Input Referred Noise (nV/√Hz) AD623A AD623B AD623A AD623B AD623A & AD623B 1 1200 600 12 2 700 350 7 5 400 200 4 10 300 150 3 20 250 125 2.5 50 220 110 2.2 100 210 105 2.1 1000 200 100 2 11 62 6 45 3 38 2 35 1.5 35 1.2 35 1.1 35 1 35 INPUT PROTECTION Internal supply referenced clamping diodes allow the input, reference, output and gain terminals of the AD623 to safely withstand overvoltages of 0.3 V above or below the supplies. This is true for all gains, and for power on and off. This last case is particularly important since the signal source and amplifier may be powered separately. If the overvoltage is expected to exceed this value, the current through these diodes should be limited to about 10 mA using external current limiting resistors. This is shown in Figure 42. The size of this resistor is defined by the supply voltage and the required overvoltage protection. VOVER VOVER +VS RLIM 1 = 10mA MAX RG AD623 OUTPUT RLIM RLIM = VOVER ؊VS +0.7V 10mA ؊VS Figure 42. Input Protection RF INTERFERENCE All instrumentation amplifiers can rectify high frequency out-ofband signals. Once rectified, these signals appear as dc offset errors at the output. The circuit of Figure 43 provides good RFI suppression without reducing performance within the in amps pass band. Resistor R1 and capacitor C1 (and likewise, R2 and C2) form a low-pass RC filter that has a –3 dB BW equal to: F = 1/(2 π R1C1). Using the component values shown, this filter has a –3 dB bandwidth of approximately 40 kHz. Resistors R1 and R2 were selected to be large enough to isolate the circuit’s input from the capacitors, but not large enough to significantly increase the circuit’s noise. To preserve commonmode rejection in the amplifier’s pass band, capacitors C1 and C2 need to be 5% or better units, or low cost 20% units can be tested and “binned” to provide closely matched devices. Capacitor C3 is needed to maintain common-mode rejection at the low frequencies. R1/R2 and C1/C2 form a bridge circuit whose output appears across the in amp’s input pins. Any mismatch between C1 and C2 will unbalance the bridge and reduce common-mode rejection. C3 ensures that any RF signals –12– REV. C are common mode (the same on both in amp inputs) and are not applied differentially. This second low pass network, R1+R2 and C3, has a –3 dB frequency equal to: 1/(2 π (R1+R2) (C3)). Using a C3 value of 0.047 µF as shown, the –3 dB signal BW of this circuit is approximately 400 Hz. The typical dc offset shift over frequency will be less than 1.5 µV and the circuit’s RF signal rejection will be better than 71 dB. The 3 dB signal bandwidth of this circuit may be increased to 900 Hz by reducing resistors R1 and R2 to 2.2 kΩ. The performance is similar to that using 4 kΩ resistors, except that the circuitry preceding the in amp must drive a lower impedance load. The circuit of Figure 43 should be built using a PC board with a ground plane on both sides. All component leads should be as short as possible. Resistors R1 and R2 can be common 1% metal film units but capacitors C1 and C2 need to be ± 5% tolerance devices to avoid degrading the circuit’s common-mode rejection. Either the traditional 5% silver mica units or Panasonic ± 2% PPS film capacitors are recommended. R1 C1 4.02k⍀ 1000pF 1% 5% –IN R2 C3 4.02k⍀ 0.047␮F 1% +IN C2 1000pF 5% +VS 0.33␮F 0.01␮F RG AD623 VOUT REFERENCE 0.33␮F 0.01␮F LOCATE C1–C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE –VS Figure 43. Circuit to Attenuate RF Interference AD623 In many applications shielded cables are used to minimize noise; for best CMR over frequency the shield should be properly driven. Figure 44 shows an active guard drive that is configured to improve ac common-mode rejection by “bootstrapping” the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. +VS –INPUT RG 100⍀ 2 AD8031 RG AD623 2 +INPUT –VS VOUT REFERENCE Figure 44. Common-Mode Shield Driver GROUNDING Since the AD623 output voltage is developed with respect to the potential on the reference terminal, many grounding problems can be solved by simply by tying the REF pin to the appropriate “local ground.” The REF pin should, however, be tied to a low impedance point for optimal CMR. The use of ground planes is recommended to minimize the impedance of ground returns (and hence the size of dc errors). In order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground returns (Figure 45). All ground pins from mixed signal components such as analog-to-digital converters should be returned through the “high quality” analog ground ANALOG POWER SUPPLY +5V –5V GND DIGITAL POWER SUPPLY GND +5V 0.1␮F 0.1␮F 0.1␮F 0.1␮F AD623 VIN1 VDD AGND DGND VIN2 ADC AD7892-2 12 AGND VDD ␮PROCESSOR Figure 45. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies 0.1␮F POWER SUPPLY +5V GND 0.1␮F 0.1␮F AD623 VDD AGND DGND 12 VDD DGND VIN ADC AD7892-2 ␮PROCESSOR REV. C Figure 46. Optimal Ground Practice in a Single Supply Environment –13– AD623 plane. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. The digital return currents from the ADC, which flow in the analog ground plane will, in general, have a negligible effect on noise performance. If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure 46 shows how to minimize interference between the digital and analog circuitry. As in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). These ground planes should be connected at the power supply’s ground pin. Separate traces should be run from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but these can be shared by a number of devices as long as a single trace is not used to route current to both digital and analog circuitry. Ground Returns for Input Bias Currents Input bias currents are those dc currents that must flow in order to bias the input transistors of an amplifier. These are usually transistor base currents. When amplifying “floating” input sources such as transformers or ac-coupled sources, there must be a direct dc path into each input in order that the bias current can flow. Figure 47 shows how a bias current path can be provided for the cases of transformer coupling, capacitive ac-coupling and for a thermocouple application. In dc-coupled resistive bridge +VS –INPUT RG +INPUT AD623 VOUT REFERENCE LOAD –VS TO POWER SUPPLY GROUND Figure 47a. Ground Returns for Bias Currents with Transformer Coupled Inputs +VS –INPUT RG +INPUT AD623 VOUT REFERENCE LOAD –VS TO POWER SUPPLY GROUND Figure 47b. Ground Returns for Bias Currents with Thermocouple Inputs +VS –INPUT 100k⍀ RG +INPUT 100k⍀ AD623 VOUT REFERENCE LOAD –VS TO POWER SUPPLY GROUND Figure 47c. Ground Returns for Bias Currents with AC Coupled Inputs applications, providing this path is generally not necessary as the bias current simply flows from the bridge supply through the bridge and into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (>10 kΩ), the offset current of the input stage will cause dc errors proportional with the input offset voltage of the amplifier. Output Buffering The AD623 is designed to drive loads of 10 kΩ or greater. If the load is less that this value, the AD623’s output should be buffered with a precision single supply op amp such as the OP113. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 Ω. Table III summarizes the performance of some other buffer op amps. +5V 0.1␮F VIN RG AD623 REF +5V 0.1␮F OP113 VOUT Figure 48. Output Buffering Table III. Buffering Options Op Amp OP113 OP191 OP150 Comments Single Supply, High Output Current Rail-to-Rail Input and Output, Low Supply Current Rail-to-Rail Input and Output, High Output Current A Single Supply Data Acquisition System Interfacing bipolar signals to single supply analog to digital converters (ADCs) presents a challenge. The bipolar signal must be “mapped” into the input range of the ADC. Figure 49 shows how this translation can be achieved. +5V +5V +5V 0.1␮F 0.1␮F ؎10mV RG 1.02k⍀ AD623 REF AD7776 AIN REFOUT REFIN Figure 49. A Single Supply Data Acquisition System The bridge circuit is excited by a +5 V supply. The full-scale output voltage from the bridge (± 10 mV) therefore has a common-mode level of 2.5 V. The AD623 removes the commonmode component and amplifies the input signal by a factor of 100 (RGAIN = 1.02 kΩ). This results in an output signal of ± 1 V. In order to prevent this signal from running into the AD623’s ground rail, the voltage on the REF pin has to be raised to at least 1 V. In this example, the 2 V reference voltage from the AD7776 ADC is used to bias the AD623’s output voltage to 2 V ± 1 V. This corresponds to the input range of the ADC. –14– REV. C AD623 Amplifying Signals with Low Common-Mode Voltage Because the common-mode input range of the AD623 extends 0.1 V below ground, it is possible to measure small differential signals which have low, or no, common mode component. Figure 50 shows a thermocouple application where one side of the J-type thermocouple is grounded. +5V 0.1␮F J-TYPE THERMOCOUPLE RG 1.02k⍀ AD623 REF VOUT 2V Figure 50. Amplifying Bipolar Signals with Low CommonMode Voltage Over a temperature range from –200°C to +200°C, the J-type thermocouple delivers a voltage ranging from –7.890 mV to 10.777 mV. A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a voltage on the AD623 REF pin of 2 V, results in the AD623’s output voltage ranging from 1.110 V to 3.077 V relative to ground. INPUT DIFFERENTIAL AND COMMON-MODE RANGE VS. SUPPLY AND GAIN Figure 51 shows a simplified block diagram of the AD623. The voltages at the outputs of the amplifiers A1 and A2 are given by the equations VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG = VCM + 0.6 V + VDIFF × Gain/2 VA1 = VCM – VDIFF/2 + 0.6 V – VDIFF × RF/RG = VCM + 0.6 V – VDIFF × Gain/2 POS SUPPLY 7 INVERTING 2 VDIFF 2 VCM VDIFF 2 4 1 GAIN RG 8 7 A1 RF 50k⍀ 50k⍀ 50k⍀ RF 50k⍀ 50k⍀ A3 50k⍀ A2 3 NONINVERTING 4 NEG SUPPLY Figure 51. Simplified Block Diagram VOUT 6 REF 5 The voltages on these internal nodes are critical in determining whether or not the output voltage will be clipped. The voltages VA1 and VA2 can swing from about 10 mV above the negative supply (V– or Ground) to within about 100 mV of the positive rail before clipping occurs. Based on this and from the above equations, the maximum and minimum input common-mode voltages are given by the equations VCMMAX = V+ – 0.7 V – VDIFF × Gain/2 VCMMIN = V– – 0.590 V + VDIFF × Gain/2 These equations can be rearranged to give the maximum possible differential voltage (positive or negative) for a particular commonmode voltage, gain, and power supply. Because the signals on A1 and A2, can clip on either rail, the maximum differential voltage will be the lesser of the two equations. |VDIFFMAX| = 2 (V+ – 0.7 V – VCM)/Gain |VDIFFMAX| = 2 (VCM – V– +0.590 V)/Gain However, the range on the differential input voltage range is also constrained by the output swing. So the range of VDIFF may have to be lower according the equation. Input Range ≤ Available Output Swing/Gain For a bipolar input voltage with a common-mode voltage that is roughly half way between the rails, VDIFFMAX will be half the value that the above equations yield because the REF pin will be at midsupply. Note that the available output swing is given for different supply conditions in the Specifications section. The equations can be rearranged to give the maximum gain for a fixed set of input conditions. Again, the maximum gain will be the lesser of the two equations. GainMAX = 2 (V+ – 0.7 V – VCM)/VDIFF GainMAX = 2 (VCM – V– +0.590 V)/VDIFF Again, we must ensure that the resulting gain times the input range is less than the available output swing. If this is not the case, the maximum gain is given by, GainMAX = Available Output Swing/Input Range Also for bipolar inputs (i.e., input range = 2 VDIFF), the maximum gain will be half the value yielded by the above equations because the REF pin must be at midsupply. The maximum gain and resulting output swing for different input conditions is given in Table IV. Output voltages are referenced to the voltage on the REF pin. For the purposes of computation, it is necessary to break down the input voltage into its differential and common-mode component. So when one of the inputs is grounded or at a fixed voltage, the common-mode voltage changes as the differential voltage changes. Take the case of the thermocouple amplifier in Figure 50. The inverting input on the AD623 is grounded. So when the input voltage is –10 mV, the voltage on the noninverting input is –10 mV. For the purposes of signal swing calculations, this input voltage should be considered to be composed of a common-mode voltage of –5 mV (i.e., (+IN + –IN)/2) and a differential input voltage of –10 mV (i.e., +IN – –IN). REV. C –15– AD623 VCM 0V 0V 0V 0V 0V 2.5 V 2.5 V 2.5 V 1.5 V 1.5 V 0V 0V Table IV. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions VDIFF ± 10 mV ± 100 mV ± 10 mV ± 100 mV ±1 V ± 10 mV ± 100 mV ±1 V ± 10 mV ± 100 mV ± 10 mV ± 100 mV REF Pin 2.5 V 2.5 V 0V 0V 0V 2.5 V 2.5 V 2.5 V 1.5 V 1.5 V 1.5 V 1.5 V Supply Voltages +5 V +5 V ±5 V ±5 V ±5 V +5 V +5 V +5 V +3 V +3 V +3 V +3 V Max Gain 118 11.8 490 49 4.9 242 24.2 2.42 142 14.2 118 11.8 Closest 1% Gain Resistor, ⍀ 866 9.31 k 205 2.1 k 26.1 k 422 4.32 k 71.5 k 715 7.68 k 866 9.31 k Resulting Gain 116 11.7 488 48.61 4.83 238 24.1 2.4 141 14 116 11.74 Output Swing ± 1.2 V ± 1.1 V ± 4.8 V ± 4.8 V ± 4.8 V ± 2.3 V ± 2.4 V ± 2.4 V ± 1.4 V ± 1.4 V ± 1.1 V ± 1.1 V 8-Lead Plastic DIP (N-8) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead ␮SOIC (RM-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 1 4 0.325 (8.25) PIN 1 0.060 (1.52) 0.300 (7.62) 0.210 (5.33) 0.015 (0.38) MAX 0.130 0.160 (4.06) (3.30) 0.115 (2.93) MIN 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) SEATING PLANE BSC 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 8-Lead SOIC (SO-8) 0.122 (3.10) 0.114 (2.90) 8 0.122 (3.10) 0.114 (2.90) 1 5 0.199 (5.05) 0.187 (4.75) 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33° 27° 0.028 (0.71) 0.016 (0.41) 0.1968 (5.00) 0.1890 (4.80) 8 0.1574 (4.00) 0.1497 (3.80) 1 5 0.2440 (6.20) 4 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25)؋ 45؇ SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8؇ 0؇ 0.0500 (1.27) 0.0160 (0.41) –16– REV. C This datasheet has been downloaded from: www.EEworld.com.cn Free Download Daily Updated Database 100% Free Datasheet Search Site 100% Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www.EEworld.com.cn All Datasheets Cannot Be Modified Without Permission Copyright © Each Manufacturing Company

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。