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三星闪存规格书K9F4G08U0D K9K8GO8U0D K9K8G08U1D K9WAG08U0D

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Rev.0.2, May. 2010 K9F4G08U0D K9K8G08U0D K9K8G08U1D K9WAG08U1D Advance 4Gb D-die NAND Flash Single-Level-Cell (1bit/cell) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D Revision History Revision No. 0.0 1. Initial issue 0.1 1. Corrected errata. 2. Chapter 1.2 Features revised. 0.2 1. DDP/QDP Part ID are added. datasheet History Advance Rev. 0.2 FLASH MEMORY Draft Date Jan. 12, 2010 May. 03, 2010 Remark Advance Advance Editor - H.K.Kim May. 26, 2010 Advance H.K.Kim The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. -2- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY Table Of Contents 1.0 INTRODUCTION ........................................................................................................................................................ 4 1.1 General Description................................................................................................................................................. 4 1.2 Features .................................................................................................................................................................. 4 1.3 PRODUCT LIST ...................................................................................................................................................... 4 1.4 Pin Configuration (TSOP1) ...................................................................................................................................... 5 1.4.1 PACKAGE DIMENSIONS ................................................................................................................................. 5 1.5 Pin Configuration (TSOP1) ...................................................................................................................................... 6 1.5.1 PACKAGE DIMENSIONS ................................................................................................................................. 6 1.6 Pin Description ........................................................................................................................................................ 7 2.0 PRODUCT INTRODUCTION...................................................................................................................................... 9 2.1 Absolute Maximum Ratings ..................................................................................................................................... 10 2.2 Recommended Operating Conditions ..................................................................................................................... 10 2.3 DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) ..................10 2.4 Valid Block............................................................................................................................................................... 11 2.5 Ac Test Condition .................................................................................................................................................... 11 2.6 Capacitance(TA=25°C, VCC=3.3V, f=1.0MHz) ....................................................................................................... 11 2.7 Mode Selection........................................................................................................................................................ 11 2.8 Program / Erase Characteristics ........................................................................................................................12 2.9 AC Timing Characteristics for Command / Address / Data Input ............................................................................ 12 2.10 AC Characteristics for Operation........................................................................................................................... 13 3.0 NAND Flash Technical Notes .................................................................................................................................... 14 3.1 Initial Invalid Block(s) ............................................................................................................................................... 14 3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 14 3.3 Error in write or read operation................................................................................................................................ 15 3.4 Addressing for program operation ........................................................................................................................... 17 3.5 System Interface Using CE don’t-care. ................................................................................................................... 18 4.0 TIMING DIAGRAMS .................................................................................................................................................. 19 4.1 Command Latch Cycle ........................................................................................................................................... 19 4.2 Address Latch Cycle............................................................................................................................................... 19 4.3 Input Data Latch Cycle ........................................................................................................................................... 20 4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)..................................................................................... 20 4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) .................................................................... 21 4.6 Status Read Cycle .................................................................................................................................................. 21 4.7 Read Operation ...................................................................................................................................................... 22 4.8 Read Operation(Intercepted by CE) ....................................................................................................................... 22 4.9 Random Data Output In a Page ............................................................................................................................. 23 4.10 Page Program Operation...................................................................................................................................... 24 4.11 Page Program Operation with Random Data Input .............................................................................................. 25 4.12 Copy-Back Program Operation ............................................................................................................................ 26 4.13 Copy-Back Program Operation with Random Data Input ..................................................................................... 27 4.14 Two-Plane Page Program Operation ................................................................................................................... 28 4.15 Block Erase Operation.......................................................................................................................................... 29 4.16 Two-Plane Block Erase Operation ....................................................................................................................... 30 4.17 Read ID Operation................................................................................................................................................ 31 5.0 DEVICE OPERATION ................................................................................................................................................ 33 5.1 Page Read............................................................................................................................................................... 33 5.2 Page Program ......................................................................................................................................................... 34 5.3 Copy-back Program................................................................................................................................................. 35 5.4 Block Erase ............................................................................................................................................................. 36 5.5 Two-plane Page Program........................................................................................................................................ 36 5.6 Two-plane Block Erase............................................................................................................................................ 37 5.7 Two-plane Copy-back Program ............................................................................................................................... 37 5.8 Read Status............................................................................................................................................................. 39 5.9 Read ID ................................................................................................................................................................... 40 5.10 Reset ..................................................................................................................................................................... 40 5.11 Ready/Busy ........................................................................................................................................................... 41 5.12 Data Protection & Power Up Sequence ................................................................................................................ 42 -3- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 1.0 INTRODUCTION 1.1 General Description Offered in 512Mx8bit, the K9F4G08U0D is a 4G-bit NAND Flash Memory with spare 128M-bit. The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F4G08U0D′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F4G08U0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 1.2 Features • Voltage Supply - 3.3V Device(K9F4G08U0D) : 2.7V ~ 3.6V • Organization - Memory Cell Array : (512M + 16M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 25μs(Max.) - Serial Access : 25ns(Min.) • Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - ECC Requirement : 1bit/528Byte - Endurance & Data Retention : Please refer to the qualification report • Command Register Operation • Unique ID for Copyright Protection • Package : - K9F4G08U0D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9K8G08U0D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9K8G08U1D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9WAG08U1D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) 1.3 PRODUCT LIST Part Number K9F4G08U0D-S K9K8G08U0D-S K9K8G08U1D-S K9WAG08U1D-S Vcc Range 2.70 ~ 3.60V Organization X8 PKG Type TSOP1 -4- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet 1.4 Pin Configuration (TSOP1) N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 R/B1 7 RE 8 CE1 9 N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE 17 WE 18 WP 19 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 K9F4G08U0D-SCB0/SIB0 K9K8G08U0D-SCB0/SIB0 48-pin TSOP1 Standard Type 12mm x 20mm 48 N.C 47 N.C 46 N.C 45 N.C 44 I/O7 43 I/O6 42 I/O5 41 I/O4 40 N.C 39 N.C 38 N.C 37 Vcc 36 Vss 35 N.C 34 N.C 33 N.C 32 I/O3 31 I/O2 30 I/O1 29 I/O0 28 N.C 27 N.C 26 N.C 25 N.C Advance Rev. 0.2 FLASH MEMORY 1.4.1 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F 20.00±0.20 0.787±0.008 #1 #48 0.10 MAX 0.004 Unit :mm/Inch 0.008-+00..000013 +0.07 -0.03 ) 0.25 0.010 0.20 ( MAX 12.00 0.472 12.40 0.488 0.50 0.0197 #24 0~8° 0.45~0.75 0.018~0.030 0.25 0.010 TYP 18.40±0.10 0.724±0.004 #25 1.00±0.05 0.039±0.002 01..02407MAX 0.05 0.002 MIN 0.005-+00..000013 +0.075 0.035 0.125 ( 0.50 0.020 ) -5- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 1.5 Pin Configuration (TSOP1) datasheet Advance Rev. 0.2 FLASH MEMORY N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 R/B2 6 R/B1 7 RE 8 CE1 9 CE2 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE 17 WE 18 WP 19 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 K9K8G08U1D-SCB0/SIB0 K9WAG08U1D-SCB0/SIB0 48-pin TSOP1 Standard Type 12mm x 20mm 48 N.C 47 N.C 46 N.C 45 N.C 44 I/O7 43 I/O6 42 I/O5 41 I/O4 40 N.C 39 N.C 38 N.C 37 Vcc 36 Vss 35 N.C 34 N.C 33 N.C 32 I/O3 31 I/O2 30 I/O1 29 I/O0 28 N.C 27 N.C 26 N.C 25 N.C 1.5.1 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F Unit :mm/Inch 0.10 MAX 0.004 20.00±0.20 0.787±0.008 #1 #48 0.008-+00..000013 +0.07 -0.03 ) 0.25 0.010 0.20 ( MAX 12.00 0.472 12.40 0.488 0.50 0.0197 #24 0~8° 0.45~0.75 0.018~0.030 0.25 0.010 TYP 18.40±0.10 0.724±0.004 #25 1.00±0.05 0.039±0.002 01..02407MAX 0.05 0.002 MIN 0.005-+00..000013 +0.075 0.035 0.125 ( 0.50 0.020 ) -6- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 1.6 Pin Description Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE ALE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. READ ENABLE RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the fall- ing edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT WP The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT R/B The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. -7- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY VCC VSS A12 - A29 A0 - A11 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE WP 4,096M + 128M Bit NAND Flash ARRAY (2,048 + 64)Byte x 262,144 Data Register & S/A Y-Gating I/O Buffers & Latches VCC VSS Global Buffers Output Driver I/0 0 I/0 7 [Figure 1] K9F4G08U0D Functional Block Diagram 1 Block = 64 Pages (128K + 4K) Byte 256K Pages (=4,096 Blocks) 2K Bytes 64 Bytes 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 4,096 Blocks = 4,224 Mbits 8 bit Page Register 2K Bytes I/O 0 ~ I/O 7 64 Bytes [Figure 2] K9F4G08U0D Array Organization 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle I/O 0 A0 A8 A12 A20 A28 I/O 1 A1 A9 A13 A21 A29 I/O 2 A2 A10 A14 A22 *L I/O 3 A3 A11 A15 A23 *L I/O 4 A4 *L A16 A24 *L NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. I/O 5 A5 *L A17 A25 *L I/O 6 A6 *L A18 A26 *L I/O 7 A7 *L A19 A27 *L Column Address Row Address : Page Address : A12 ~ A17 Plane Address : A18 Block Address : A19 ~ the last Address -8- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 2.0 PRODUCT INTRODUCTION The K9F4G08U0D is a 4,224Mbit(4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F4G08U0D. The K9F4G08U0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M byte physical space requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F4G08U0D. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. [Table 1] Command Sets Function Read Read for Copy Back Read ID Reset Page Program Two-Plane Page Program(2) Copy-Back Program Two-Plane Copy-Back Program(2) Block Erase Two-Plane Block Erase Random Data Input(1) Random Data Output(1) Read Status Read Status 2 1st Cycle 00h 00h 90h FFh 80h 80h---11h 85h 85h---11h 60h 60h---60h 85h 05h 70h F1h NOTE : 1) Random Data Input/Output can be executed in a page. 2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 2nd Cycle 30h 35h 10h 81h---10h 10h 81h---10h D0h D0h E0h Acceptable Command during Busy O O O Caution : Any undefined command inputs are prohibited except for above command set of Table 1. -9- K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 2.1 Absolute Maximum Ratings Parameter Symbol Rating VCC -0.6 to +4.6 Voltage on any pin relative to VSS VIN -0.6 to +4.6 VI/O -0.6 to Vcc + 0.3 (< 4.6V) Temperature Under Bias K9XXG08XXD-XCB0 K9XXG08XXD-XIB0 TBIAS -10 to +125 -40 to +125 Storage Temperature K9XXG08XXD-XCB0 K9XXG08XXD-XIB0 TSTG -65 to +150 Short Circuit Current IOS 5 NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Unit V °C °C mA 2.2 Recommended Operating Conditions (Voltage reference to GND, K9XXG08XXD-XCB0 :TA=0 to 70°C, K9XXG08XXD-XIB0:TA=-40 to 85°C) Parameter Symbol K9F4G08U0D(3.3V) Min Typ. Max Supply Voltage VCC 2.7 3.3 3.6 Supply Voltage VSS 0 0 0 Unit V V 2.3 DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Symbol Test Conditions 3.3V Min Typ Max Unit Operating Current Page Read with Serial Access Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO tRC=50ns, CE=VIL IOUT=0mA CE=VIH, WP=PRE=0V/VCC CE=VCC-0.2, WP=PRE=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) Input High Voltage VIH* - Input Low Voltage, All inputs VIL* - Output High Voltage Level VOH K9F4G08U0D :IOH=-400μA Output Low Voltage Level VOL K9F4G08U0D :IOL=2.1mA Output Low Current(R/B) IOL(R/B) K9F4G08U0D :VOL=0.4V NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc=/3.3V, TA=25°C. Not 100% tested. 3) The typical value of the K9K8G08U1D's ISB2 is 20μA and the maximum value is 100μA. 4) The typical value of the K9K8G08U0D's ISB2 is 20μA and the maximum value is 100μA. 5) The typical value of the K9WAG08U1D's ISB2 is 40μA and the maximum value is 200μA. - 15 30 - 15 30 mA - 15 30 - - 1 - 10 50 μA - - ±10 - - ±10 VCC 2.0 - +0.3 -0.3 - 0.8 V 2.4 - - - - 0.4 8 10 - mA - 10 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 2.4 Valid Block Parameter Symbol Min Typ. Max Unit K9F4G08U0D 4,016 4,096 K9K8G08U0D K9K8G08U1D NVB 8,032 - 8,192 Blocks K9WAG08U1D 16,064 16,384 NOTE : 1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC. 3) The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations. 2.5 Ac Test Condition (K9XXG08UXD-XCB0 :TA=0 to 70°C, K9F4G08UXD-XIB0:TA=-40 to 85°C, K9XXG08UXD: Vcc=2.7V~3.6V unless otherwise noted) Parameter K9XXG08UXD Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 Output Load 1 TTL GATE and CL=50pF 2.6 Capacitance(TA=25°C, VCC=3.3V, f=1.0MHz) Item Symbol Test Condition Min Max Unit Input/Output Capacitance CI/O VIL=0V - CI/O(W)* VIL=0V - 8 pF 5 pF Input Capacitance CIN VIN=0V - CIN(W)* VIN=0V - 8 pF 5 pF NOTE : 1) Capacitance is periodically sampled and not 100% tested. 2) CI/O(W)* and CIN(W)* are tested at wafer level. 2.7 Mode Selection CLE ALE CE WE H L L L H L H L L L H L L L L L L L H X X X X X X X X X X X X X X(1) X X X X H X NOTE : 1) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby. RE WP Mode H X Command Input Read Mode H X Address Input(5clock) H H Command Input Write Mode H H Address Input(5clock) H H Data Input X Data Output H X During Read(Busy) X H During Program(Busy) X H During Erase(Busy) X L Write Protect X 0V/VCC(2) Stand-by - 11 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 2.8 Program / Erase Characteristics Parameter Symbol Min Typ Max Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles tPROG - tDBSY - Nop - 250 750 0.5 1 - 4 Block Erase Time tBERS - 2.0 10 NOTE : 1) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested. 2) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature. Unit μs μs cycles ms 2.9 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min CLE Setup Time tCLS(1) 12 CLE Hold Time tCLH 5 CE Setup Time tCS(1) 20 CE Hold Time tCH 5 WE Pulse Width tWP 12 ALE Setup Time tALS(1) 12 ALE Hold Time tALH 5 Data Setup Time tDS(1) 12 Data Hold Time tDH 5 Write Cycle Time tWC 25 WE High Hold Time tWH 10 Address to Data Loading Time tADL(2) 70 NOTE : 1) The transition of the corresponding control pins must occur only once while WE is held low 2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle Max Unit - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - 12 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet 2.10 AC Characteristics for Operation Parameter Symbol Data Transfer from Cell to Register tR ALE to RE Delay tAR CLE to RE Delay tCLR Ready to RE Low tRR RE Pulse Width tRP WE High to Busy tWB Read Cycle Time tRC RE Access Time tREA CE Access Time tCEA RE High to Output Hi-Z tRHZ CE High to Output Hi-Z tCHZ RE High to Output Hold tRHOH RE Low to Output Hold tRLOH CE High to Output Hold tCOH RE High Hold Time tREH Output Hi-Z to RE Low tIR RE High to WE Low tRHW WE High to RE Low tWHR Device Resetting Time(Read/Program/Erase) tRST NOTE : 1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5μs. Advance Rev. 0.2 FLASH MEMORY Min Max Unit - 25 μs 10 - ns 10 - ns 20 - ns 12 - ns - 100 ns 25 - ns - 20 ns - 25 ns - 100 ns - 30 ns 15 - ns 5 - ns 15 - ns 10 - ns 0 - ns 100 - ns 60 - ns - 5/10/500(1) μs - 13 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 3.0 NAND Flash Technical Notes 3.1 Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC. 3.2 Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) No Initial Invalid Block(s) Table No * Check "FFh" at the column address 2048 of the 1st and 2nd page in the block Check "FFh" Yes Last Block ? Yes End [Figure 3] Flow chart to create initial invalid block table - 14 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 3.3 Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Write Read Failure Mode Erase Failure Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? No or R/B = 1 ? * No Program Error Yes I/O 0 = 0 ? Yes Program Completed * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. - 15 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data I/O 6 = 1 ? No or R/B = 1 ? * No Erase Error Yes I/O 0 = 0 ? Yes Erase Completed ECC Generation No Reclaim the Error Verify ECC Yes Page Read Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement ∼ { 1st (n-1)th nth Block A an error occurs. (page) ∼ { 1st (n-1)th nth (page) Block B 1 Buffer memory of the controller. 2 * Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3 Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4 Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme. - 16 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 3.4 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn’t need to be page 0. Page 63 (64) : Page 31 (32) : Page 2 (3) Page 1 (2) Page 0 (1) Data register From the LSB page to MSB page DATA IN: Data (1) Data (64) Page 63 (64) : Page 31 (1) : Page 2 (3) Page 1 (32) Page 0 (2) Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) - 17 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 3.5 System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 8,628byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time in the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. ≈≈ ≈ ≈ ≈ ≈≈ ≈ ≈ ≈≈ ≈ Program Operation with CE don’t-care CLE CE CE don’t-care WE ALE I/Ox 80h Address(5Cycles) Data Input Data Input 10h tCS tCH tCEA CE CE tWP WE tREA RE I/O0~7 out ≈ ≈≈ ≈ ≈ ≈ Read Operation with CE don’t-care ≈ ≈ ≈≈ ≈ CLE CE RE ALE R/B WE I/Ox tR ≈ 00h Address(5Cycle) 30h CE don’t-care Data Output(serial access) - 18 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.0 TIMING DIAGRAMS 4.1 Command Latch Cycle CLE CE WE ALE I/Ox datasheet tCLS tCS tCLH tCH tWP tALS tALH tDS tDH Command Advance Rev. 0.2 FLASH MEMORY 4.2 Address Latch Cycle CLE CE tCLS tCS tWC tWC tWC tWC WE ALE I/Ox tWP tALS tWH tALH tWP tWP tWP tWH tWH tWH tALS tALH tALS tALH tALS tALH tALS tALH tDS tDH Col. Add1 tDS tDH Col. Add2 tDS tDH Row Add1 tDS tDH Row Add2 tDS tDH Row Add3 - 19 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.3 Input Data Latch Cycle CLE datasheet tCLH ≈ tCH CE ≈ ALE WE I/Ox tWC tALS tWP tWH tDS tDH DIN 0 tWP tDS tDH DIN 1 ≈ ≈ tWP tDS tDH DIN final Advance Rev. 0.2 FLASH MEMORY ≈≈ 4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) CE tRC tREA tREH tREA RE tRHZ I/Ox Dout tRR R/B NOTE : 1) Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2) tRLOH is valid when frequency is higher than 20MHz. tRHOH starts to be valid when frequency is lower than 20MHz. Dout ≈≈ ≈≈ tREA tCHZ tRHZ tRHOH Dout - 20 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet 4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) CE RE I/Ox tRC tRP tREH tREA tCEA tRR tREA tRLOH Dout R/B NOTE : 1) Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2) tRLOH is valid when frequency is higher than 20MHz. tRHOH starts to be valid when frequency is lower than 20MHz. ≈ ≈≈ ≈≈ Advance Rev. 0.2 FLASH MEMORY tCHZ tRHZ tRHOH Dout 4.6 Status Read Cycle CLE CE WE RE I/Ox tCLS tCS tCLH tCLR tCH tWP tWHR tCEA tCHZ tDS tDH 70h/F1h tIR tREA tRHZ tRHOH Status Output - 21 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.7 Read Operation CLE datasheet tCLR Advance Rev. 0.2 FLASH MEMORY CE WE ALE RE I/Ox R/B tWC tWB tAR tR tRC tRR 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Column Address Row Address Busy Dout N Dout N+1 ≈ ≈≈ tRHZ Dout M 4.8 Read Operation(Intercepted by CE) CLE tCLR CE WE ALE RE I/Ox R/B tWB tAR tR tCSD tCHZ tRC 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Column Address Row Address tRR Dout N Dout N+1 Dout N+2 Busy - 22 - - 23 - CLE CE WE ALE RE I/Ox R/B tCLR tWB tAR tR tRC tRHW tWHR tREA tRR 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Column Address Row Address Dout N Dout N+1 05h Col Add1 Col Add2 E0h Column Address Busy Dout M Dout M+1 4.9 Random Data Output In a Page Advance Rev. 0.2 FLASH MEMORY datasheet K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.10 Page Program Operation datasheet Advance Rev. 0.2 FLASH MEMORY CLE ≈ ≈≈ ≈ CE tWC WE ALE tWC tWC tADL tWB tPROG RE I/Ox R/B 80h Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 SerialData Input Command Column Address Row Address Din Din N M 1 up to m Byte Serial Input 10h Program Command NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. tWHR 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program - 24 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.11 Page Program Operation with Random Data Input CLE CE tWC WE ALE tWC tWC ≈ tADL tADL ≈ tWB tPROG tWHR datasheet RE ≈≈ ≈≈ I/Ox 80h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Serial Data Input Command Column Address Row Address R/B Din N Din M 85h Col. Add1 Col. Add2 Serial Input Random Data Column Address Input Command Din Din J K Serial Input 10h Program Command NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. ≈ 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program - 25 - Advance Rev. 0.2 FLASH MEMORY K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.12 Copy-Back Program Operation CLE CE tWC WE ALE RE tWB tR tRC tADL tPROG tWB tWHR ≈ ≈≈ ≈≈ ≈ I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 35h Column Address Row Address Data 1 Data N 85h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Data 1 Column Address Row Address R/B Busy Copy-Back Data Input Command NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. Data N 10h 70h I/Ox Read Status Command Busy I/O0=0 Successful Program I/O0=1 Error in Program datasheet - 26 - Advance Rev. 0.2 FLASH MEMORY K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.13 Copy-Back Program Operation with Random Data Input CLE CE tWC WE ALE RE tWB tR tRC tADL tPROG tWB tWHR ≈ ≈≈ ≈≈ ≈ I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 35h Column Address Row Address Data 1 Data N 85h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Data 1 Column Address Row Address R/B Busy Copy-Back Data Input Command NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. Data N 10h 70h I/Ox Read Status Command Busy I/O0=0 Successful Program I/O0=1 Error in Program datasheet - 27 - Advance Rev. 0.2 FLASH MEMORY ≈ ≈≈ ≈ ≈ ≈≈ ≈ K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.14 Two-Plane Page Program Operation CLE CE tWC WE ALE tDBSY tWB tWB tPROG tWHR datasheet RE I/Ox R/B Din 80h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 N Din M 11h Serial Data Column Address Page Row Address Program 1 up to 8,628 Byte Command Input Command Data Serial Input (Dummy) tDBSY : typ. 500ns max. 1μs 81h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Din N Din M 10h Program Confirm Command (True) 70h/F1h I/O Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program Ex.) Two-Plane Page Program R/B tDBSY tPROG I/O0~7 80h Address & Data Input 11h Col Add1,2 & Row Add 1,2,3 8,628 Byte Data Note NOTE : Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 81h Address & Data Input 10h Col Add1,2 & Row Add 1,2,3 8,628 Byte Data 70h/F1h - 28 - Advance Rev. 0.2 FLASH MEMORY K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.15 Block Erase Operation datasheet CLE CE WE ALE RE I/Ox R/B tWC tWB 60h Row Add1 Row Add2 Row Add3 D0h Row Address Auto Block Erase Setup Command Erase Command ≈ tBERS Busy Advance Rev. 0.2 FLASH MEMORY tWHR 70h I/O 0 I/O0=0 Successful Erase Read Status I/O0=1 Error in Erase Command - 29 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.16 Two-Plane Block Erase Operation CLE CE tWC tWC WE tWB ALE RE I/OX 60h Row Add1 Row Add2 RowDA0dhd3 60h Row Add1 Row Add2 Row Add3 D0h Row Address R/B Block Erase Setup Command1 Row Address Block Erase Setup Command2 Erase Confirm Command tBERS tWHR 70h/F1h I/O 0 Busy I/O 0 = 0 Successful Erase I/O 0 = 1 Error in Erase Read Status Command datasheet - 30 - Ex.) Address Restriction for Two-Plane Block Erase Operation R/B tBERS I/O0~7 60h Address 60h A9AD~d0dAhr2e5ss D0h Row Add1,2,3 Row Add1,2,3 70h/F1h Advance Rev. 0.2 FLASH MEMORY K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D 4.17 Read ID Operation datasheet Advance Rev. 0.2 FLASH MEMORY CLE CE WE tAR ALE RE I/Ox 90h Read ID Command tREA 00h ECh Address 1cycle Maker Code Device Code Device Code 3rd cyc. 4th cyc. 5th cyc. 6th cyc. Device K9F4G08U0D K9K8G08U0D K9K8G08U1D K9WAG08U1D Device Code (2nd Cycle) DCh D3h DCh D3h NOTE : 1) When reading the 6th cycle of Read ID, may acquire the "ECh" vlalue 3rd Cycle 10h 11h 10h 11h 4th Cycle 95h 5th Cycle 54h 58h 54h 58h - 31 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 3rd ID Data Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Cache Program 4th ID Data Page Size (w/o redundant area ) Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization Serial Access Minimum 5th ID Data Plane Number Plane Size (w/o redundant Area) Reserved Description Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 0 1 0 1 00 01 10 11 00 01 10 11 I/O1 I/O0 00 01 10 11 Description 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 x8 x16 50ns/30ns 25ns Reserved Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 00 01 10 11 00 01 10 11 0 1 0 1 0 0 1 1 0 0 1 1 Description 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb I/O7 I/O6 I/O5 I/O4 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 0 I/O3 I/O2 00 01 10 11 I/O1 I/O0 0 0 - 32 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.0 DEVICE OPERATION 5.1 Page Read Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25μs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. CLE CE WE ALE R/B RE I/Ox ≈ ≈ ≈≈ ≈ ≈ tR 00h Address(5Cycle) 30h Col. Add.1,2 & Row Add.1,2,3 Data Output(Serial Access) Data Field Spare Field [Figure 4] Read Operation - 33 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY R/B RE I/Ox tR 00h Address 5Cycles 30h Col. Add.1,2 & Row Add.1,2,3 Data Output 05h Address 2Cycles E0h Col. Add.1,2 Data Output Data Field Spare Field Data Field Spare Field [Figure 5] Random Data Output In a Page 5.2 Page Program The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 6). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. R/B I/Ox tPROG 80h Address & Data Input 10h 70h Col. Add.1,2 & Row Add.1,2,3 Data [Figure 6] Program & Read Status Operation "0" I/O0 Pass "1" Fail - 34 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY tPROG R/B I/Ox 80h Address & Data Input 85h Address & Data Input 10h Col. Add.1,2 & Row Add1,2,3 Data Col. Add.1,2 Data [Figure 7] Random Data Input In a Page "0" 70h I/O0 Pass "1" Fail 5.3 Copy-back Program Copy-Back program with Read for Copy-Back is cond to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy DataInput command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8 & Figure 9). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 9. tR R/B tPROG ≈≈ I/Ox 00h Add.(5Cycles) 35h Data Output 85h Add.(5Cycles) 10h 70h Col. Add.1,2 & Row Add.1,2,3 Source Address Col. Add.1,2 & Row Add.1,2,3 Destination Address [Figure 8] Page Copy-Back Program Operation "0" I/O0 Pass "1" Fail R/B tR tPROG ≈≈ I/Ox 00h Add.(5Cycles) 35h Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 10h 70h Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 Source Address Destination Address There is no limitation for the number of repetition. [Figure 9] Page Copy-Back Program Operation with Random Data Input - 35 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.4 Block Erase The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A18 to A29 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence. R/B I/Ox tBERS 60h Address Input(3Cycle) D0h 70h Row Add 1,2,3 [Figure 10] Block Erase Operation "0" I/O0 Pass "1" Fail 5.5 Two-plane Page Program Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h/F1h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/ O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane Page Program is shown is Figure 11. R/B tDBSY tPROG I/O0 ~ 7 80h Address & Data Input 11h A0 ~ A11 : Valid A12 ~ A17 : Fixed ’Low’ A18 : Fixed ’Low’ A19 ~ A29 : Fixed ’Low’ Note*2 81h Address & Data Input 10h A0 ~ A11 : Valid A12 ~ A17 : Valid A18 : Fixed ’High’ A19 ~ A29 : Valid NOTE :1. It is noticeable that same row address except for A18 is applied to the two blocks 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 70h/F1h 80h 11h 81h 10h Data Input Plane 0 (2048 Block) Plane 1 (2048 Block) Block 0 Block 2 Block 1 Block 3 Block 4092 Block 4094 Block 4093 Block 4095 [Figure 11] Two-Plane Page Program - 36 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.6 Two-plane Block Erase Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/Busy status bit (I/O 6). R/B tBERS I/OX 60h Address (3 Cycle) A12 ~ A17 : Fixed ’Low’ A18 :Fixed ’Low’ A19 ~ A29 : Fixed ’Low’ 60h Address (3 Cycle) D0h A12 ~ A17 : Fixed ’Low’ A18 : Fixed ’High’ A19 ~ A29 : valid [Figure 12] Two-Plane Block Erase Operation 70h/F1h "0" I/O0 Pass "1" Fail 5.7 Two-plane Copy-back Program Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. tR tR R/B ≈≈ ≈≈ I/Ox 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 Data Output 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane1 Data Output 1 R/B tDBSY tPROG I/Ox 85h Add.(5Cycles) 11h 81h Add.(5Cycles) 10h Note2 1 Col. Add.1,2 & Row Add.1,2,3 Destination Address Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Fixed ’Low’ A12 ~ A17 : Fixed ’Low’ A18 : Fixed ’Low’ A19 ~ A29 : Fixed ’Low’ A0 ~ A11 : Fixed ’Low’ A12 ~ A17 : Valid A18 : Fixed ’High’ A19 ~ A29 : Valid 70h/F1h Plane0 Source page Target page (1) (3) Plane1 Source page Target page (2) (3) (1) : Read for Copy Back On Plane0 (2) : Read for Copy Back On Plane1 (3) : Two-Plane Copy-Back Program Data Field Spare Field Data Field Spare Field [Figure 13] Two-Plane Copy-Back Program Operation NOTE : 1) Copy-Back Program operation is allowed only within the same memory plane. 2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh. - 37 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY R/B I/Ox tR tR ≈≈ ≈≈ 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 Data Output 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane1 Data Output 1 tDBSY R/B I/Ox R/B 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 11h 1 Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 Note2 2 Destination Address A0 ~ A11 : Valid A12 ~ A17 : Fixed ’Low’ A18 : Fixed ’Low’ A19 ~ A29 : Fixed ’Low’ tPROG I/Ox 81h Add.(5Cycles) Data 85h Add.(2Cycles) Data 10h Col. Add.1,2 & Row Add.1,2,3 2 Destination Address A0 ~ A11 : Valid A12 ~ A17 : Valid A18 : Fixed ’High’ A19 ~ A29 : Valid Col. Add.1,2 [Figure 14] Two-Plane Copy-Back Program Operation with Random Data Input NOTE: 1) Copy-Back Program operation is allowed only within the same memory plane. 2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh. - 38 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.8 Read Status The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 2 for specific Status Register definitions and Table 3 for specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. [Table 2] Status Register Definition for 70h Command I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect NOTE : 1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed. Pass : "0" Don’t -cared Don’t -cared Don’t -cared Don’t -cared Don’t -cared Busy : "0" Protected : "0" Definition Fail : "1" Ready : "1" Not Protected : "1" [Table 3] Status Register Definition for F1h Command I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Chip Pass/Fail Plane0 Pass/Fail Plane1 Pass/Fail Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Chip Pass/Fail Plane0 Pass/Fail Plane1 Pass/Fail Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect NOTE : 1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed. Pass : "0" Pass : "0" Pass : "0" Don’t -cared Don’t -cared Don’t -cared Busy : "0" Protected : "0" Definition Fail : "1" Fail : "1" Fail : "1" Ready : "1" Not Protected : "1" "1"otected - 39 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.9 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 15 shows the operation sequence. CLE CE WE ALE RE I/OX tCLR tCEA tAR tWHR 90h 00h Address. 1cycle tREA ECh Maker code Device Code 3rd Cyc. Device code 4th Cyc. 5th Cyc. [Figure 15] Read ID Operation Device K9F4G08U0D K9K8G08U0D K9K8G08U1D K9WAG08U1D Device Code (2nd Cycle) DCh D3h DCh D3h NOTE : 1) When reading the 6th cycle of Read ID, may acquire the "ECh" vlalue 3rd Cycle 10h 11h 10h 11h 4th Cycle 95h 5th Cycle 54h 58h 54h 58h 5.10 Reset The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 16 below. R/B I/OX FFh [Table 4] Device Status Operation mode Mode tRST [Figure 16] RESET Operation After Power-up 00h Command is latched After Reset Waiting for next command - 40 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.11 Ready/Busy The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/ B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 17). Its value can be determined by the following guidance. VCC GND Rp ibusy R/B open drain output CL Ready Vcc 3.3V device - VOL : 0.4V, VOH : 2.4V VOH VOL Busy tf tr Device [Figure 17] Rp vs tr ,tf & Rp vs ibusy @ Vcc = 2.7V, Ta = 25°C , CL = 30pF 200n 2.3 Ibusy @ Vcc = 3.3V, Ta = 25°C , CL = 50pF 2.4 2m 200n Ibusy 200 2m 1.1 120 150 1.2 100n tr 60 90 0.75 0.55 1m 100n 100 tr 50 0.8 0.6 1m 30 2.3 tf 2.3 2.3 2.3 3.6 tf 3.6 3.6 3.6 1K 2K 3K 4K Rp(ohm) 1K 2K 3K 4K Rp(ohm) tr,tf [s] Ibusy [A] tr,tf [s] Ibusy [A] Rp value guidance VCC(Max.) - VOL(Max.) Rp(min, 3.3V part) = = IOL + ΣIL 3.2V 8mA + ΣIL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 41 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 5.12 Data Protection & Power Up Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and powerdown. A recovery time of minimum 100μs is required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection. ≈ ~ 2.3V VCC High WP ≈ ~ 2.3V ≈≈ WE Don’t care Ready/Busy 5 ms max 100μs Operation ≈ Invalid NOTE : During the initialization, the device consumes a maximum current of 30mA (ICC1) [Figure 18] AC Waveforms for Power Transition Don’t care - 42 -

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