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stm32f207数据手册

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STM32F205xx STM32F207xx ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet − production data Features ■ Core: ARM 32-bit Cortex™-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) ■ Memories – Up to 1 Mbyte of Flash memory – 512 bytes of OTP memory – Up to 128 + 4 Kbytes of SRAM – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes ■ CRC calculation unit ■ Clock, reset and supply management – From 1.8 to 3.6 V application supply+I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration ■ Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20 × 32 bit backup registers, and optional 4 KB backup SRAM ■ 3 × 12-bit, 0.5 µs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode ■ 2 × 12-bit D/A converters ■ General-purpose DMA: 16-stream controller with centralized FIFOs and burst support ■ 96-bit unique ID ■ Up to 17 timers – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input ■ Debug mode: Serial wire debug (SWD), JTAG, and Cortex-M3 Embedded Trace Macrocell™ FBGA FBGA LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) UFBGA176 WLCSP64+2 (10 × 10 mm) (0.400 mm pitch) ■ Up to 140 I/O ports with interrupt capability: – Up to 136 fast I/Os up to 60 MHz – Up to 138 5 V-tolerant I/Os ■ Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs and 2 UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S to achieve audio class accuracy via audio PLL or external PLL – 2 × CAN interfaces (2.0B Active) – SDIO interface ■ Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII ■ 8- to 14-bit parallel camera interface (48 Mbyte/s max) ■ Analog true random number generator Table 1. Device summary Reference Part number STM32F205xx STM32F207xx STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG, STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF STM32F205VG, STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG, STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG, STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG October 2012 This is information on a product in full production. Doc ID 15818 Rev 9 1/177 www.st.com 1 Contents Contents STM32F20xxx 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 18 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 18 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 21 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 24 2.2.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 30 2.2.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 31 2/177 Doc ID 15818 Rev 9 STM32F20xxx Contents 2.2.29 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 31 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . 32 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 33 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 34 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 67 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 67 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 68 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 89 Doc ID 15818 Rev 9 3/177 Contents STM32F20xxx 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 94 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 141 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 141 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 A.1 Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 A.2 Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . 157 A.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 158 A.4 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 160 A.5 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 A.6 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4/177 Doc ID 15818 Rev 9 STM32F20xxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F205xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32F207xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F20x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 64 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 67 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 67 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 71 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 77 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 77 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Doc ID 15818 Rev 9 5/177 List of tables STM32F20xxx Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 101 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 113 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 113 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 114 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 124 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 125 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 131 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 138 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 141 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 144 WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . 146 LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 147 LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 149 LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data . 151 UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . 153 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Main applications versus package for STM32F2xxx microcontrollers . . . . . . . . . . . . . . . 156 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6/177 Doc ID 15818 Rev 9 STM32F20xxx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F20x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 24 Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 24 STM32F20x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32F20x WLCSP64+2 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32F20x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32F20x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32F20x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32F20x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Number of wait states versus fCPU and VDD range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 73 Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 73 Typical current consumption vs temperature in Sleep mode, peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical current consumption vs temperature in Sleep mode, peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical current consumption vs temperature in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Doc ID 15818 Rev 9 7/177 List of figures STM32F20xxx Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 111 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 119 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 119 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 124 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 125 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 126 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 127 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 131 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 133 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 134 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 136 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 137 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 140 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 140 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 144 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . 146 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 147 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline . . . . . . . . 151 LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline . 153 Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Regulator OFF/ internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 USB OTG FS (full speed) device-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8/177 Doc ID 15818 Rev 9 STM32F20xxx List of figures Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. USB OTG FS (full speed) host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 OTG FS (full speed) connection dual-role with internal PHY . . . . . . . . . . . . . . . . . . . . . . 159 OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Audio player solution using PLL, PLLI2S, USB and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 162 Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Master clock (MCK) used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . . . . 163 Master clock (MCK) not used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . 163 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Doc ID 15818 Rev 9 9/177 Introduction 1 Introduction STM32F20xxx This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document. For information on programming, erasing and protection of the internal Flash memory, please refer to the STM32F20x/STM32F21x Flash programming manual (PM0059). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 10/177 Doc ID 15818 Rev 9 STM32F20xxx 2 Description Description Note: The STM32F20x family is based on the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices also feature an adaptive real-time memory accelerator (ART Accelerator™) which allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. This performance has been validated using the CoreMark benchmark. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true number random generator (RNG). They also feature standard and advanced communication interfaces. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), and a camera interface for CMOS sensors. The devices also feature standard peripherals. ● Up to three I2Cs ● Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization. ● 4 USARTs and 2 UARTs ● A USB OTG high-speed with full-speed capability (with the ULPI) ● A second USB OTG (full-speed) ● Two CANs ● An SDIO interface ● Ethernet and camera interface available on STM32F207xx devices only. The STM32F205xx and STM32F207xx devices operate in the –40 to +105 °C temperature range from a 1.8 V to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is connected to VDD. A comprehensive set of power-saving modes allow the design of low-power applications. STM32F205xx and STM32F207xx devices are offered in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.These features make the STM32F205xx and STM32F207xx microcontroller family suitable for a wide range of applications: ● Motor drive and application control ● Medical equipment ● Industrial applications: PLC, inverters, circuit breakers ● Printers, and scanners ● Alarm systems, video intercom, and HVAC ● Home audio appliances Figure 4 shows the general block diagram of the device family. Doc ID 15818 Rev 9 11/177 Doc ID 15818 Rev 9 12/177 Table 2. STM32F205xx features and peripheral counts Peripherals STM32F205Rx Flash memory in Kbytes SRAM in Kbytes System (SRAM1+SRAM2) Backup FSMC memory controller Ethernet General-purpose Advanced-control Timers Basic IWDG WWDG RTC Random number generator SPI/(I2S) I2C Comm. interfaces USART UART USB OTG FS USB OTG HS CAN Camera interface GPIOs SDIO 128 64 (48+16) 256 96 (80+16) 512 768 1024 128 (112+16) 4 No 51 12-bit ADC Number of channels 16 12-bit DAC Number of channels Maximum CPU frequency Operating voltage STM32F205Vx 128 256 512 768 1024 64 96 (48+16) (80+16) 128 (112+16) 4 Yes(1) No 10 2 2 Yes Yes Yes Yes 3 (2)(2) 3 4 2 Yes Yes 2 No 82 Yes 3 16 Yes 2 120 MHz 1.8 V to 3.6 V(3) STM32F205Zx 256 96 (80+16) 512 768 1024 128 (112+16) 4 114 24 STM32F20xxx Description STM32F20xxx Table 2. STM32F205xx features and peripheral counts (continued) Peripherals STM32F205Rx STM32F205Vx STM32F205Zx Operating temperatures Package LQFP64 Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C LQFP64 WLCSP64 +2 LQFP6 4 LQFP64 WLCSP6 4+2 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD minimum value is 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is set to VDD. Doc ID 15818 Rev 9 Table 3. STM32F207xx features and peripheral counts Peripherals STM32F207Vx STM32F207Zx Flash memory in Kbytes SRAM in Kbytes System (SRAM1+SRAM2) Backup FSMC memory controller Ethernet General-purpose Advanced-control Timers Basic IWDG WWDG RTC 256 512 768 1024 256 512 768 1024 256 128 (112+16) 4 Yes(1) Yes 10 2 2 Yes Yes Yes Random number generator Yes STM32F207Ix 512 768 1024 Description 13/177 Description 14/177 Table 3. STM32F207xx features and peripheral counts (continued) Peripherals STM32F207Vx STM32F207Zx STM32F207Ix Comm. interfaces Camera interface SPI/(I2S) I2C USART UART USB OTG FS USB OTG HS CAN 3 (2)(2) 3 4 2 Yes Yes 2 Yes GPIOs SDIO 12-bit ADC Number of channels 12-bit DAC Number of channels Maximum CPU frequency Operating voltage 82 114 140 Yes 3 16 24 24 Yes 2 120 MHz 1.8 V to 3.6 V(3) Doc ID 15818 Rev 9 Operating temperatures Package LQFP100 Ambient temperatures: –40 to +85 °C/–40 to +105 °C Junction temperature: –40 to + 125 °C LQFP144 LQFP176/ UFBGA176 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD minimum value is 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is set to VDD. STM32F20xxx STM32F20xxx Description 2.1 Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F205xx and STM32F207xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F20x family remains simple as only a few pins are impacted. Figure 3 and Figure 1 provide compatible board designs between the STM32F20x and the STM32F10xxx family. Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package 48 49 47 64 1 VSS VSS 33 32 31 17 16 VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration ai15962b Doc ID 15818 Rev 9 15/177 Description STM32F20xxx Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package 75 76 73 VSS 51 50 49 99 (RFU) 100 1 19 20 26 25 VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration VDD VSS VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx VDD VSS - VDD, VSS, or NC for the STM32F2xx VSS for STM32F10xx VDD for STM32F2xx ai15961c Figure 3. Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package 108 109 106 VSS 73 72 71 143 (RFU) 144 30 31 37 1 36 VDD VSS VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx VDD VSS - VDD, VSS, or NC for the STM32F2xx VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration ai15960c 1. RFU = reserved for future use. 16/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2 Device overview Figure 4. STM32F20x block diagram NJTRST, JTDI, JTCK/SWCLK JTDO/SWD JTDO/TRACESWO TRACECLK TRACED[3:0] MII or RMII as AF MDIO as AF DP, DM ULPI: CK, D(7:0), DIR, STP, NXT SCL/SDA, INTN, ID, VBUS, SOF JTAG & SW ETM MPU NVIC ARM Cortex-M3 120 MHz I-BUS ART accelerator D-BUS S-BUS Ethernet MAC DMA/ 10/100 FIFO USB DMA/ OTG HS FIFO DMA2 8 Streams FIFO DMA1 8 Streams FIFO PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11 :0] GPIO PORT A GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I FIFO 140 AF D[7:0] CMD, CK as AF 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF 2 channels as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF MOSI, MISO SCK, NSS as AF VDDREF_ADC 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 8 analog inputs to ADC3 EXT IT. WKUP SDIO / MMC TIM1 / PWM 16b TIM8 / PWM 16b TIM9 16b TIM10 16b TIM11 16b smcard irDA USART 1 smcard USART 6 irDA SPI1 @VDDA TUeSmApReTra2tuMreBpssensor ADC1 ADC2 IF ADC 3 APBA2P6B02M6H0zMHz PHY AHB bus-matrix 8S7M ACCEL/ CACHE FIFO FIFO PHY External memory controller (FSMC) AHB3 SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash Flash 1 Mbyte RNG SRAM 112 KB SRAM 16 KB AHB2 120 MHz Camera interface USB OTG FS FCLK HCLKx PCLKx AHB1 120 MHz @VDDA RC HS RC LS PLL1&2 Reset & MAclNocAkGT control VDD12 Power managmt Voltage regulator 3.3 V to 1.2 V @VDD POR Reset Int Supply supervision POR/PDR/ BOR PVD @VDDA @VDD XTAL OSC 4- 26 MHz IWDG LS Standby interface @VBAT XTAL 32 kHz RTC AWU Backup register 4 KB BKSPRAM LS DMA2 DMA1 AHB/APB2 AHB/APB1 TIM2 32b TIM3 16b TIM4 16b TIM5 32b TIM12 16b TIM13 16b WWDG TIM14 16b USART2 USART3 smcard irDA smcard irDA UART4 APB1 30MHAzPB1 30MHz FIFO UART5 TIM6 16b TIM7 16b SPI2/I2S2 SPI3/I2S3 I2C1/SMBUS I2C2/SMBUS @VDDA DAC1 ITF DAC2 I2C3/SMBUS bxCAN1 bxCAN2 CLK, NE [3:0], A[23:0] D[31:0], OEN, WEN, NBL[3:0], NL, NREG NWAIT/IORDY, CD NIORD, IOWR, INT[2:3] INTN, NIIS16 as AF HSYNC, VSYNC PIXCLK, D[13:0] DP DM SCL, SDA, INTN, ID, VBUS, SOF VDD = 1.8 to 3.6 V VSS VCAP1, VCAP2 VDDA, VSSA NRST OSC_IN OSC_OUT VBAT = 1.65 to 3.6 V OSC32_IN OSC32_OUT RTC_AF1 RTC_AF1 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels 2 channels as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF RX, TX, CK CTS, RTS as AF RX, TX as AF RX, TX as AF MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF TX, RX TX, RX DAC1_OUT DAC2_OUT as AF as AF ai17614c 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 60 MHz. 2. The camera interface and Ethernet are available only in STM32F207xx devices. Doc ID 15818 Rev 9 17/177 Description STM32F20xxx 2.2.1 2.2.2 2.2.3 2.2.4 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, the STM32F20x family is compatible with all ARM tools and software. Figure 4 shows the general block diagram of the STM32F20x family. Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M3 processors. It balances the inherent performance advantage of the ARM Cortex-M3 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full 150 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. Embedded Flash memory The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 18/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F20x products embed: ● Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0 wait states ● 4 Kbytes of backup SRAM. The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 5. Multi-AHB matrix ARM Cortex-M3 GP DMA1 GP MAC USB OTG DMA2 Ethernet HS I-bus D-bus S-bus DMA_P1 DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ART ACCEL. S0 S1 S2 S3 S4 S5 S6 S7 M0 ICODE M1 DCODE M2 M3 M4 M5 M6 Bus matrix-S Flash memory SRAM 112 Kbyte SRAM 16 Kbyte AHB1 periph AHB2 periph FSMC Static MemCtl APB1 APB2 ai15963c Doc ID 15818 Rev 9 19/177 Description STM32F20xxx 2.2.8 2.2.9 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: ● SPI and I2S ● I2C ● USART and UART ● General-purpose, basic and advanced-control timers TIMx ● DAC ● SDIO ● Camera interface (DCMI) ● ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: ● Write FIFO ● Code execution from external memory except for NAND Flash and PC Card ● Maximum frequency (fHCLK) for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 20/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2.10 2.2.11 2.2.12 Nested vectored interrupt controller (NVIC) The STM32F20x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M3. The NVIC main features are the following: ● Closely coupled NVIC gives low-latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving, higher-priority interrupts ● Support tail chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the system clock. Several prescalers and PLLs allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz. The devices embed a dedicate PLL (PLLI2S) which allow to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. Doc ID 15818 Rev 9 21/177 Description STM32F20xxx 2.2.13 2.2.14 2.2.15 2.2.16 Boot modes At startup, boot pins are used to select one out of three boot options: ● Boot from user Flash ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). Power supply schemes ● VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. On WLCSP package, VDD ranges from 1.7 to 3.6 V. ● VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. ● VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 17: Power supply scheme for more details. Power supply supervisor The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. On devices in WLCSP package, BOR can be inactivated by setting IRROFF to VDD (see Section 2.2.16: Voltage regulator). The devices also feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Voltage regulator The regulator has five operating modes: ● Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down ● Regulator OFF – Regulator OFF/internal reset ON – Regulator OFF/internal reset OFF 22/177 Doc ID 15818 Rev 9 STM32F20xxx Description Regulator ON The regulator ON modes are activated by default on LQFP packages.On WLCSP66 package, they are activated by connecting both REGOFF and IRROFF pins to VSS, while only REGOFF must be connected to VSS on UFBGA176 package (IRROFF is not available). VDD minimum value is 1.8 V(a). There are three regulator ON modes: ● MR is used in nominal regulation mode (Run) ● LPR is used in Stop mode ● Power-down is used in Standby mode: The regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). Regulator OFF ● Regulator OFF/internal reset ON On WLCSP66 package, this mode is activated by connecting REGOFF pin to VDD and IRROFF pin to VSS. On UFBGA176 package, only REGOFF must be connected to VDD (IRROFF not available). The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. The following conditions must be respected: – VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. – If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V(a), then PA0 should be connected to the NRST pin (see Figure 6). Otherwise, PA0 should be asserted low externally during POR until VDD reaches 1.8 V (see Figure 7). In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in OFF. ● Regulator OFF/internal reset OFF On WLCSP66 package, this mode activated by connecting REGOFF to VSS and IRROFF to VDD. IRROFF cannot be activated in conjunction with REGOFF. This mode is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. The following conditions must be respected: – VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains (see Figure 6). – PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V, and until VDD reaches 1.65 V. – NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.65 V (see Figure 7). a. VDD minimum value is 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is set to VDD. Doc ID 15818 Rev 9 23/177 Description STM32F20xxx Figure 6. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR=1.8 V 1.2 V 1.08 V VCAP_1 /VCAP_2 time PA0 tied to NRST NRST time 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 7. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR=1.8 V 1.2 V 1.08 V VCAP_1 /VCAP_2 time PA0 asserted externally NRST time 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: ● The real-time clock (RTC) ● 4 Kbytes of backup SRAM ● 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC 24/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2.18 Note: has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 2.2.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin. Low-power modes The STM32F20x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The RTC, the IWDG, and the corresponding clock sources are not stopped when the device enters the Stop or Standby mode. Doc ID 15818 Rev 9 25/177 Description STM32F20xxx 2.2.19 Note: VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery or an external supercapacitor. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 2.2.20 Timers and watchdogs The STM32F20x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary output Max interface clock Max timer clock Advanced- TIM1, control TIM8 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 Yes 60 MHz 120 MHz TIM2, TIM5 General 32-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 purpose TIM3, TIM4 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 Basic TIM6, TIM7 16-bit Any integer Up between 1 Yes and 65536 0 No 30 MHz 60 MHz No 30 MHz 60 MHz No 30 MHz 60 MHz Any integer TIM9 16-bit Up between 1 No 2 and 65536 No 60 MHz 120 MHz TIM10, TIM11 General 16-bit Any integer Up between 1 No and 65536 1 purpose Any integer TIM12 16-bit Up between 1 No 2 and 65536 No 60 MHz 120 MHz No 30 MHz 60 MHz TIM13, TIM14 16-bit Any integer Up between 1 No and 65536 1 No 30 MHz 60 MHz 26/177 Doc ID 15818 Rev 9 STM32F20xxx Description Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: ● Input capture ● Output compare ● PWM generation (edge- or center-aligned modes) ● One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture. The advanced-control timer can therefore work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F20x devices (see Table 4 for differences). ● TIM2, TIM3, TIM4, TIM5 The STM32F20x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ● TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. ● TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode Doc ID 15818 Rev 9 27/177 Description STM32F20xxx 2.2.21 2.2.22 output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable clock source Inter-integrated circuit interface (I²C) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) The STM32F20x devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to 28/177 Doc ID 15818 Rev 9 STM32F20xxx Description communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at up to 3.75 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 5. USART feature comparison USART name Standard Modem features (RTS/CTS) LIN SPI master irDA Max. baud rate Max. baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) APB mapping USART1 X X XX X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X XX X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X XX X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max. 30 MHz) UART5 X - X - X - 3.75 3.75 APB1 (max. 30 MHz) USART6 X X XX X X 3.75 7.5 APB2 (max. 60 MHz) 2.2.23 2.2.24 Serial peripheral interface (SPI) The STM32F20x devices feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, while SPI2 and SPI3 can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, in half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. Doc ID 15818 Rev 9 29/177 Description STM32F20xxx 2.2.25 2.2.26 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F207xx devices. The STM32F207xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F207xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F207xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F207xx. The STM32F207xx includes the following features: ● Supports 10 and 100 Mbit/s rates ● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F20x and STM32F21x reference manual for details) ● Tagged MAC frame support (VLAN support) ● Half-duplex (CSMA/CD) and full-duplex operation ● MAC control sublayer (control frames) support ● 32-bit CRC generation and removal ● Several address filtering modes for physical and multicast address (multicast and group addresses) ● 32-bit status code for each transmitted or received frame ● Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total ● Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input ● Triggers interrupt when system time becomes greater than target time 30/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2.27 2.2.28 2.2.29 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: ● Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing ● Supports the session request protocol (SRP) and host negotiation protocol (HNP) ● 4 bidirectional endpoints ● 8 host channels with periodic OUT support ● HNP/SNP/IP inside (no need for any external resistor) ● For OTG/Host modes, a power switch is needed in case bus-powered devices are connected ● Internal FS OTG PHY support Universal serial bus on-the-go high-speed (OTG_HS) The STM32F20x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: ● Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing ● Supports the session request protocol (SRP) and host negotiation protocol (HNP) ● 6 bidirectional endpoints ● 12 host channels with periodic OUT support ● Internal FS OTG PHY support ● External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. ● Internal USB DMA ● HNP/SNP/IP inside (no need for any external resistor) ● For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Doc ID 15818 Rev 9 31/177 Description STM32F20xxx 2.2.30 2.2.31 2.2.32 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). Digital camera interface (DCMI) The camera interface is not available in STM32F205xx devices. STM32F207xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It features: ● Programmable polarity for the input pixel clock and synchronization signals ● Parallel data communication can be 8-, 10-, 12- or 14-bit ● Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) ● Supports continuous mode or snapshot (a single frame) mode ● Capability to automatically crop the image True random number generator (RNG) All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers produced by an integrated analog circuit. 32/177 Doc ID 15818 Rev 9 STM32F20xxx Description 2.2.33 2.2.34 2.2.35 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to 120 MHz that leads to a maximum I/O toggling speed of 60 MHz. ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● Simultaneous sample and hold ● Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: ● two DAC converters: one for each output channel ● 8-bit or 12-bit monotonic output ● left or right data alignment in 12-bit mode ● synchronized update capability ● noise-wave generation ● triangular-wave generation ● dual DAC channel independent or simultaneous conversions ● DMA capability for each channel ● external triggers for conversion ● input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. Doc ID 15818 Rev 9 33/177 Description STM32F20xxx 2.2.36 2.2.37 2.2.38 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F20x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 34/177 Doc ID 15818 Rev 9 STM32F20xxx 3 Pinouts and pin description Figure 8. STM32F20x LQFP64 pinout Pinouts and pin description VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA1 5 PA1 4 VBAT PC13-RTC_AF1 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 LQFP64 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD_1 ai15969b Figure 9. STM32F20x WLCSP64+2 ballout 1 2 3 4 A PA14 PA15 PC12 PB3 B VSS_2 PA13 PC10 PB4 C PA12 VCAP_2 PC11 D PC9 PA11 PA10 E VDD_4 PA8 PA9 F VSS_4 G PB15 H PB14 PC7 PC8 PC6 PC5 PB13 PB10 PC4 J PB12 PB11 VCAP_1 PB2 5 6 7 8 9 PB5 PB7 PB9 VDD_2 VBAT PB6 BOOT0 PB8 PC13 PC14 PD2 IRROFF PC15 PC2 VSS_3 VDD_3 PA0 VREF+ PA3 NRST PC1 PH0OSC_IN PH1OSC_OUT PC3 PC0 PA6 PA5 REGOFF PA1 VSS_5 PB1 PB0 PA7 PA4 PA2 1. Top view. ai18470b Doc ID 15818 Rev 9 35/177 Pinouts and pin description Figure 10. STM32F20x LQFP100 pinout STM32F20xxx 100 VDD_3 99 RFU 98 PE1 97 PE0 96 PB9 95 PB8 94 BOOT0 93 PB7 92 PB6 91 PB5 90 PB4 89 PB3 88 PD7 87 PD6 86 PD5 85 PD4 84 PD3 83 PD2 82 PD1 81 PD0 80 PC12 79 PC11 78 PC10 77 PA15 76 PA14 PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-RTC_AF1 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 VSS_5 10 VDD_5 11 PH0-OSC_IN 12 PH1-OSC_OUT 13 NRST 14 PC0 15 PC1 16 PC2 17 PC3 18 VDD_12 19 VSSA 20 VREF+ 21 VDDA 22 PA0-WKUP 23 PA1 24 PA2 25 LQFP100 75 VDD_2 74 VSS_2 73 VCAP_2 72 PA 13 71 PA 12 70 PA 11 69 PA 10 68 PA 9 67 PA 8 66 PC9 65 PC8 64 PC7 63 PC6 62 PD15 61 PD14 60 PD13 59 PD12 58 PD11 57 PD10 56 PD9 55 PD8 54 PB15 53 PB14 52 PB13 51 PB12 PA3 26 VSS_4 27 VDD_4 28 PA4 29 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 PB11 48 VCAP_1 49 VDD_1 50 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. ai15970d 36/177 Doc ID 15818 Rev 9 STM32F20xxx Figure 11. STM32F20x LQFP144 pinout Pinouts and pin description 144 VDD_3 143 RFU 142 PE1 141 PE0 140 PB9 139 PB8 138 BOOT0 137 PB7 136 PB6 135 PB5 134 PB4 133 PB3 132 PG15 131 VDD_11 130 VSS_11 129 PG14 128 PG13 127 PG12 126 PG11 125 PG10 124 PG9 123 PD7 122 PD6 121 VDD_10 120 VSS_10 119 PD5 118 PD4 117 PD3 116 PD2 115 PD1 114 PD0 113 PC12 112 PC11 111 PC10 110 PA15 109 PA14 PA3 37 VSS_4 38 VDD_4 39 PA4 40 PA5 41 PA6 42 PA7 43 PC4 44 PC5 45 PB0 46 PB1 47 PB2 48 PF11 49 PF12 50 VSS_6 51 VDD_6 52 PF13 53 PF14 54 PF15 55 PG0 56 PG1 57 PE7 58 PE8 59 PE9 60 VSS_7 61 VDD_7 62 PE10 63 PE11 64 PE12 65 PE13 66 PE14 67 PE15 68 PB10 69 PB11 70 VCAP_1 71 VDD_1 72 PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-RTC_AF1 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 PF4 14 PF5 15 VSS_5 16 VDD_5 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 PH0-OSC_IN 23 PH1-OSC_OUT 24 NRST 25 PC0 26 PC1 27 PC2 28 PC3 29 VDD_12 30 VSSA 31 VREF+ 32 VDDA 33 PA0-WKUP 34 PA1 35 PA2 36 LQFP144 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 108 VDD_2 107 VSS_2 106 VCAP_2 105 PA13 104 PA12 103 PA11 102 PA10 101 PA9 100 PA8 99 PC9 98 PC8 97 PC7 96 PC6 95 VDD_9 94 VSS_9 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 87 PG2 86 PD15 85 PD14 84 VDD_8 83 VSS_8 82 PD13 81 PD12 80 PD11 79 PD10 78 PD9 77 PD8 76 PB15 75 PB14 74 PB13 73 PB12 ai15971d Doc ID 15818 Rev 9 37/177 PH4 45 PH5 46 PA3 47 VSS_4 48 VDD_4 49 PA4 50 PA5 51 PA6 52 PA7 53 PC4 54 PC5 55 PB0 56 PB1 57 PB2 58 PF11 59 PF12 60 VSS_6 61 VDD_6 62 PF13 63 PF14 64 PF15 65 PG0 66 PG1 67 PE7 68 PE8 69 PE9 70 VSS_7 71 VDD_7 72 PE10 73 PE11 74 PE12 75 PE13 76 PE14 77 PE15 78 PB10 79 PB11 80 VCAP_1 81 VDD_1 82 PH6 83 PH7 84 PH8 85 PH9 86 PH10 87 PH11 88 176 PI7 175 PI6 174 PI5 173 PI4 172 VDD_3 171 RFU 170 PE1 169 PE0 168 PB9 167 PB8 166 BOOT0 165 PB7 164 PB6 163 PB5 162 PB4 161 PB3 160 PG15 159 VDD_11 158 VSS_11 157 PG14 156 PG13 155 PG12 154 PG11 153 PG10 152 PG9 151 PD7 150 PD6 149 VDD_10 148 VSS_10 147 PD5 146 PD4 145 PD3 144 PD2 143 PD1 142 PD0 141 PC12 140 PC11 139 PC10 138 PA15 137 PA14 136 VDD_15 135 VSS_15 134 PI3 133 PI2 Pinouts and pin description Figure 12. STM32F20x LQFP176 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PI8-RTC_AF2 7 PC13-RTC_AF1 8 PC14-OSC32_IN 9 PC15-OSC32_OUT 10 PI9 11 PI10 12 PI11 13 VSS_13 14 VDD_13 15 PF0 16 PF1 17 PF2 18 PF3 19 PF4 20 PF5 21 VSS_5 22 VDD_5 23 PF6 24 PF7 25 PF8 26 PF9 27 PF10 28 PH0-OSC_IN 29 PH1-OSC_OUT 30 NRST 31 PC0 32 PC1 33 PC2 34 PC3 35 VDD_12 36 VSSA 37 VREF+ 38 VDDA 39 PA0-WKUP 40 PA1 41 PA2 42 PH2 43 PH3 44 LQFP176 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. STM32F20xxx 132 PI1 131 PI0 130 PH15 129 PH14 128 PH13 127 VDD_2 126 VSS_2 125 VCAP_2 124 PA13 123 PA12 122 PA11 121 PA10 120 PA9 119 PA8 118 PC9 117 PC8 116 PC7 115 PC6 114 VDD_9 113 VSS_9 112 PG8 111 PG7 110 PG6 109 PG5 108 PG4 107 PG3 106 PG2 105 PD15 104 PD14 103 VDD_8 102 VSS_8 101 PD13 100 PD12 99 PD11 98 PD10 97 PD9 96 PD8 95 PB15 94 PB14 93 PB13 92 PB12 91 VDD_14 90 VSS_14 89 PH12 ai15972d 38/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Figure 13. STM32F20x UFBGA176 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 C VBAT PI7 PI6 PI5 D PC13TAMP1 PI8TAMP2 PI9 PI4 E PC14OSC32_IN PF0 PI10 PI11 F PC15- OSC32_OUT VSS_13 VDD_13 PH2 G PH0OSC_IN VSS_5 VDD_5 PH3 H PH1OSC_OUT PF2 PF1 PH4 J NRST PF3 PF4 PH5 PB7 PB6 PG15 PG12 PG11 PG10 VDD_3 RFU VDD_11 VDD_10 VDD_15 PG9 VSS BOOT0 VSS_11 VSS_10 VSS_15 PD4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PD6 PD0 PC11 PC10 PA12 PD5 PD1 PI3 PI2 PA11 PD3 PD2 PH15 PI1 PA10 PH13 PH14 PI0 PA9 VSS_2 VCAP2 PC9 PA8 VSS_9 VDD_2 PC8 PC7 VSS_14 VDD_9 PG8 PC6 VDD_14 VDD_8 PG7 PG6 K PF7 PF6 PF5 VDD_4 L PF10 PF9 PF8 REGOFF VSS VSS VSS VSS VSS PH12 PG5 PG4 PH11 PH10 PD15 PG3 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS_6 VSS_7 VCAP1 PH6 PH8 PH9 PD14 PD13 PA0- N VREF- PA1 WKUP PA4 PC4 PF13 PG0 VDD_6 VDD_7 VDD_1 PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 ai17293b 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. Top view. Table 6. STM32F20x pin and ball definitions Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) - - 1 1 1 A2 - - 2 2 2 A1 - - 3 3 3 B1 - - 4 4 4 B2 - - 5 5 5 B3 1 A9 6 6 6 C1 PE2 PE3 PE4 PE5 PE6 VBAT I/O FT PE2 I/O FT PE3 I/O FT PE4 I/O FT PE5 I/O FT PE6 S VBAT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT TRACED0/FSMC_A19/ EVENTOUT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6/ EVENTOUT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7/ EVENTOUT Doc ID 15818 Rev 9 39/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) --2 B8 7 3 B9 8 4 C9 9 --- - 7 D2 PI8(4) I/O FT 7 8 D1 PC13(4) I/O FT 8 9 E1 PC14(4)-OSC32_IN(6) I/O FT 9 10 F1 PC15(4)OSC32_OUT(6) I/O FT - 11 D3 PI9 I/O FT - - - - 12 E3 PI10 I/O FT - - - - 13 E4 - - - - 14 F2 - - - - 15 F3 - - - 10 16 E2 PI11 VSS_13 VDD_13 PF0 I/O FT S S I/O FT - - - 11 17 H3 PF1 I/O FT - - - 12 18 H2 - - - 13 19 J2 - - - 14 20 J3 - - - 15 21 K3 - H9 10 16 22 G2 - - 11 17 23 G3 - - - 18 24 K2 PF2 PF3(6) PF4(6) PF5(6) VSS_5 VDD_5 PF6(6) I/O FT I/O FT I/O FT I/O FT S S I/O FT - - - 19 25 K1 PF7(6) I/O FT - - - 20 26 L3 PF8(6) I/O FT - - - 21 27 L2 PF9(6) I/O FT - - - 22 28 L1 5 E9 12 23 29 G1 6 F9 13 24 30 H1 PF10(6) PH0(6)-OSC_IN PH1(6)-OSC_OUT I/O FT I/O FT I/O FT PI8(5) PC13(5) PC14(5) PC15(5) PI9 PI10 PI11 VSS_13 VDD_13 PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 PH0 PH1 EVENTOUT EVENTOUT EVENTOUT RTC_AF2 RTC_AF1 OSC32_IN EVENTOUT OSC32_OUT CAN1_RX / EVENTOUT ETH_MII_RX_ER/ EVENTOUT OTG_HS_ULPI_DIR/ EVENTOUT FSMC_A0 / I2C2_SDA/ EVENTOUT FSMC_A1 / I2C2_SCL/ EVENTOUT FSMC_A2 / I2C2_SMBA/ EVENTOUT FSMC_A3/ EVENTOUT FSMC_A4/ EVENTOUT FSMC_A5/ EVENTOUT ADC3_IN9 ADC3_IN14 ADC3_IN15 TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 TIM11_CH1/FSMC_NREG/ EVENTOUT ADC3_IN5 TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 FSMC_INTR/ EVENTOUT ADC3_IN8 EVENTOUT OSC_IN EVENTOUT OSC_OUT 40/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 7 E8 14 25 31 J1 8 G9 15 26 32 M2 9 F8 16 27 33 M3 10 D7 17 28 34 M4 11 G8 18 29 35 M5 - - 19 30 36 12 - 20 31 37 M1 - - - - - N1 - F7 21 32 38 P1 13 - 22 33 39 R1 14 E7 23 34 40 N3 15 H8 24 35 41 N2 16 J9 25 36 42 P2 - - - - 43 F4 - - - - 44 G4 - - - - 45 H4 - - - - 46 J4 NRST PC0(6) PC1(6) PC2(6) PC3(6) VDD_12 VSSA VREFVREF+ VDDA PA0(7)-WKUP(6) PA1(6) PA2(6) PH2 PH3 PH4 PH5 I/O NRST I/O FT PC0 OTG_HS_ULPI_STP/ EVENTOUT ADC123_ IN10 I/O FT PC1 ETH_MDC/ EVENTOUT ADC123_ IN11 I/O FT PC2 SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2/ EVENTOUT ADC123_ IN12 I/O FT PC3 SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_ IN13 S VDD_12 S VSSA S VREF- S VREF+ S VDDA I/O FT PA0-WKUP USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ ADC123_IN0/ WKUP EVENTOUT I/O FT PA1 USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT ADC123_IN1 I/O FT PA2 USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ADC123_IN2 ETH_MDIO/ EVENTOUT I/O FT PH2 ETH_MII_CRS/ EVENTOUT I/O FT PH3 ETH_MII_COL/ EVENTOUT I/O FT PH4 I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT I/O FT PH5 I2C2_SDA/ EVENTOUT Doc ID 15818 Rev 9 41/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 17 G7 26 37 47 R2 18 F1 27 38 48 - H7 L4 19 E1 28 39 49 K4 20 J8 29 40 50 N4 21 H6 30 41 51 P4 22 H5 31 42 52 P3 23 J7 32 43 53 R3 24 H4 33 44 54 N5 25 G3 34 45 55 P5 26 J6 35 46 56 R5 27 J5 36 47 57 R4 PA3(6) VSS_4 REGOFF VDD_4 PA4(6) PA5(6) PA6(6) PA7(6) PC4(6) PC5(6) PB0(6) PB1(6) I/O FT S I/O S I/O TT I/O TT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PA3 VSS_4 REGOFF VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CHIN/ EVENTOUT ADC12_IN5 /DAC_OUT2 SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 SPI1_MOSI/ TIM8_CH1N / TIM14_CH1 TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / RMII_CRS_DV / EVENTOUT ADC12_IN7 ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 ETH_RMII_RX_D1 / ETH_MII_RX_D1 / EVENTOUT ADC12_IN15 TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT ADC12_IN9 42/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 28 J4 37 48 58 M6 - - - 49 59 R6 - - - 50 60 P6 - - - 51 61 M8 - - - 52 62 N8 - - - 53 63 N6 - - - 54 64 R7 - - - 55 65 P7 - - - 56 66 N7 - - - 57 67 M7 - - 38 58 68 R8 - - 39 59 69 P8 - - 40 60 70 P9 - - - 61 71 M9 - - - 62 72 N9 - - 41 63 73 R9 - - 42 64 74 P10 - - 43 65 75 R10 - - 44 66 76 N11 - - 45 67 77 P11 - - 46 68 78 R11 29 H3 47 69 79 R12 PB2 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 I/O FT PB2-BOOT1 EVENTOUT I/O FT PF11 DCMI_12/ EVENTOUT I/O FT PF12 FSMC_A6/ EVENTOUT S S I/O FT VSS_6 VDD_6 PF13 FSMC_A7/ EVENTOUT I/O FT PF14 FSMC_A8/ EVENTOUT I/O FT PF15 FSMC_A9/ EVENTOUT I/O FT PG0 FSMC_A10/ EVENTOUT I/O FT PG1 FSMC_A11/ EVENTOUT I/O FT PE7 FSMC_D4/TIM1_ETR/ EVENTOUT I/O FT PE8 FSMC_D5/TIM1_CH1N/ EVENTOUT I/O FT PE9 FSMC_D6/TIM1_CH1/ EVENTOUT S S I/O FT VSS_7 VDD_7 PE10 FSMC_D7/TIM1_CH2N/ EVENTOUT I/O FT PE11 FSMC_D8/TIM1_CH2/ EVENTOUT I/O FT PE12 FSMC_D9/TIM1_CH3N/ EVENTOUT I/O FT PE13 FSMC_D10/TIM1_CH3/ EVENTOUT I/O FT PE14 FSMC_D11/TIM1_CH4/ EVENTOUT I/O FT PE15 FSMC_D12/TIM1_BKIN/ EVENTOUT I/O FT PB10 SPI2_SCK/ I2S2_SCK/ I2C2_SCL / USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT Doc ID 15818 Rev 9 43/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 30 J2 48 70 80 R13 31 J3 49 71 81 M10 32 - 50 72 82 N10 - - - - 83 M11 - - - - 84 N12 - - - - 85 M12 - - - - 86 M13 - - - - 87 L13 - - - - 88 L12 - - - - 89 K12 - - - - 90 H12 - - - - 91 J12 33 J1 51 73 92 P12 34 H2 52 74 93 P13 PB11 VCAP_1 VDD_1 PH6 PH7 PH8 PH9 PH10 PH11 PH12 VSS_14 VDD_14 PB12 PB13 I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT PB11 VCAP_1 VDD_1 PH6 PH7 PH8 PH9 PH10 PH11 PH12 VSS_14 VDD_14 PB12 PB13 I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT I2C3_SDA / DCMI_HSYNC/ EVENTOUT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT TIM5_CH1 / DCMI_D1/ EVENTOUT TIM5_CH2 / DCMI_D2/ EVENTOUT TIM5_CH3 / DCMI_D3/ EVENTOUT SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT SPI2_SCK / I2S2_SCK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT OTG_HS_ VBUS 44/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 35 H1 53 75 94 R14 36 G1 54 76 95 R15 - - 55 77 96 P15 - - 56 78 97 P14 - - 57 79 98 N15 - - 58 80 99 N14 - - 59 81 100 N13 - - 60 82 101 M15 - - - 83 102 - - - 84 103 J13 - - 61 85 104 M14 - - 62 86 105 L14 - - - 87 106 L15 - - - 88 107 K15 - - - 89 108 K14 - - - 90 109 K13 - - - 91 110 J15 - - - 92 111 J14 - - - 93 112 H14 - - - 94 113 G12 PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM USART3_RTS/ TIM8_CH2N/ EVENTOUT SPI2_MOSI / I2S2_SD / TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP / RTC_50Hz/ EVENTOUT FSMC_D13 / USART3_TX/ EVENTOUT FSMC_D14 / USART3_RX/ EVENTOUT FSMC_D15 / USART3_CK/ EVENTOUT FSMC_A16/USART3_CTS/ EVENTOUT FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT FSMC_A18/TIM4_CH2/ EVENTOUT FSMC_D0/TIM4_CH3/ EVENTOUT FSMC_D1/TIM4_CH4/ EVENTOUT FSMC_A12/ EVENTOUT FSMC_A13/ EVENTOUT FSMC_A14/ EVENTOUT FSMC_A15/ EVENTOUT FSMC_INT2/ EVENTOUT FSMC_INT3 /USART6_CK/ EVENTOUT USART6_RTS / ETH_PPS_OUT/ EVENTOUT Doc ID 15818 Rev 9 45/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) - - - 95 114 H13 37 G2 63 96 115 H15 38 F2 64 97 116 G15 39 F3 65 98 117 G14 40 D1 66 99 118 F14 41 E2 67 100 119 F15 42 E3 68 101 120 E15 43 D3 69 102 121 D15 44 D2 70 103 122 C15 45 C1 71 104 123 B15 46 B2 72 105 124 A15 47 C2 73 106 125 F13 - B1 74 107 126 F12 48 A8 75 108 127 G13 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13 VCAP_2 VSS_2 VDD_2 S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S S VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMSSWDIO VCAP_2 VSS_2 VDD_2 I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT I2S2_CKIN/ I2S3_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT OTG_FS_ VBUS JTMS-SWDIO/ EVENTOUT 46/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) - - - - 128 E12 - - - - 129 E13 - - - - 130 D13 - - - - 131 E14 - - - - 132 D14 - - - - 133 C14 - - - - 134 C13 - - - - 135 D9 - - - - 136 C9 49 A1 76 109 137 A14 50 A2 77 110 138 A13 51 B3 78 111 139 B14 52 C3 79 112 140 B13 53 A3 80 113 141 A12 - - 81 114 142 B12 - - 82 115 143 C12 PH13 PH14 PH15 PI0 PI1 PI2 PI3 VSS_15 VDD_15 PA14 PA15 PC10 PC11 PC12 PD0 PD1 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PH13 PH14 PH15 PI0 PI1 PI2 PI3 VSS_15 VDD_15 JTCKSWCLK JTDI PC10 PC11 PC12 PD0 PD1 TIM8_CH1N / CAN1_TX/ EVENTOUT TIM8_CH2N / DCMI_D4/ EVENTOUT TIM8_CH3N / DCMI_D11/ EVENTOUT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT SPI2_SCK / I2S2_SCK / DCMI_D8/ EVENTOUT TIM8_CH4 /SPI2_MISO / DCMI_D9/ EVENTOUT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT JTCK-SWCLK/ EVENTOUT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS/ EVENTOUT SPI3_SCK / I2S3_SCK / UART4_TX / SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX/ EVENTOUT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI / I2S3_SD / USART3_CK/ EVENTOUT FSMC_D2/CAN1_RX/ EVENTOUT FSMC_D3 / CAN1_TX/ EVENTOUT Doc ID 15818 Rev 9 47/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 54 C7 83 116 144 D12 - - 84 117 145 D11 - - 85 118 146 D10 - - 86 119 147 C11 - - - 120 148 D8 - - - 121 149 C8 - - 87 122 150 B11 - - 88 123 151 A11 - - - 124 152 C10 - - - 125 153 B10 - - - 126 154 B9 - - - 127 155 B8 - - - 128 156 A8 - - - 129 157 A7 - - - 130 158 D7 - - - 131 159 C7 - - - 132 160 B7 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 TIM3_ETR/UART5_RX SDIO_CMD / DCMI_D11/ EVENTOUT FSMC_CLK/USART2_CTS/ EVENTOUT FSMC_NOE/USART2_RTS / EVENTOUT FSMC_NWE/USART2_TX/ EVENTOUT FSMC_NWAIT/ USART2_RX/ EVENTOUT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT USART6_RX / FSMC_NE2/FSMC_NCE3/ EVENTOUT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT FSMC_NCE4_2 / ETH_MII_TX_EN / ETH _RMII_TX_EN/ EVENTOUT FSMC_NE4 / USART6_RTS/ EVENTOUT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT USART6_CTS / DCMI_D13/ EVENTOUT 48/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) 55 A4 89 133 161 A10 56 B4 90 134 162 A9 57 A5 91 135 163 A6 58 B5 92 136 164 B6 59 A6 93 137 165 B5 60 B6 94 138 166 D6 61 B7 95 139 167 A5 62 A7 96 140 168 B4 - - 97 141 169 A4 - - 98 142 170 A3 - - - - - D5 63 D8 - - - - - 99 143 171 C6 64 D9 100 144 172 C5 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VSS_3 RFU(9) VDD_3 I/O FT JTDO/ TRACESWO JTDO/ TRACESWO/ SPI3_SCK / I2S3_SCK / TIM2_CH2 / SPI1_SCK/ EVENTOUT I/O FT NJTRST NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO/ EVENTOUT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / I/O FT PB5 ETH_PPS_OUT/TIM3_CH2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT I/O FT PB6 I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT I2C1_SDA / FSMC_NL(8) / I/O FT PB7 DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT I BOOT0 VPP I/O FT PB8 I/O FT PB9 TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT SPI2_NSS/ I2S2_WS/ TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT I/O FT PE0 TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT I/O FT PE1 FSMC_NBL1 / DCMI_D3/ EVENTOUT S VSS S VSS_3 S VDD_3 Doc ID 15818 Rev 9 49/177 Pinouts and pin description STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Other functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Type(1) I / O Level(2) - - - - 173 D4 - - - - 174 C4 - - - - 175 C3 - - - - 176 C2 - C8 - - - - PI4 PI5 PI6 PI7 IRROFF I/O FT PI4 I/O FT PI5 I/O FT PI6 I/O FT PI7 I/O IRROFF TIM8_BKIN / DCMI_D5/ EVENTOUT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT TIM8_CH2 / DCMI_D6/ EVENTOUT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant; TT = 3.6 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. 6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used as an internal Reset (active low). 8. FSMC_NL pin is also named FSMC_NADV on memory devices. 9. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. Table 7. FSMC pin definition Pins FSMC CF NOR/PSRAM/S RAM NOR/PSRAM Mux NAND 16 bit LQFP100 PE2 A23 A23 Yes PE3 A19 A19 Yes PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - PF1 A1 A1 - PF2 A2 A2 - PF3 A3 A3 - 50/177 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 7. Pins PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF12 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 FSMC pin definition (continued) FSMC CF A4 A5 NIORD NREG NIOWR CD INTR A6 A7 A8 A9 A10 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 NOR/PSRAM/S RAM A4 A5 NOR/PSRAM Mux A6 A7 A8 A9 A10 A11 D4 DA4 D5 DA5 D6 DA6 D7 DA7 D8 DA8 D9 DA9 D10 DA10 D11 DA11 D12 DA12 D13 DA13 D14 DA14 D15 DA15 A16 A16 A17 A17 A18 A18 D0 DA0 D1 DA1 A12 A13 A14 NAND 16 bit D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLE ALE D0 D1 LQFP100 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - Doc ID 15818 Rev 9 51/177 Pinouts and pin description STM32F20xxx Table 7. Pins PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 FSMC pin definition (continued) FSMC CF NOR/PSRAM/S RAM NOR/PSRAM Mux A15 D2 D3 NOE NWE NWAIT NCE4_1 NCE4_2 D2 D3 CLK NOE NWE NWAIT NE1 NE2 NE3 NE4 A24 A25 NADV NBL0 NBL1 DA2 DA3 CLK NOE NWE NWAIT NE1 NE2 NE3 NE4 A24 A25 NADV NBL0 NBL1 NAND 16 bit INT2 INT3 D2 D3 NOE NWE NWAIT NCE2 NCE3 LQFP100 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 52/177 Doc ID 15818 Rev 9 STM32F20xxx Table 8. Alternate function mapping Port PA0-WKUP PA1 PA2 AF0 SYS AF1 TIM1/2 TIM2_CH1_ETR TIM2_CH2 TIM2_CH3 AF2 TIM3/4/5 TIM 5_CH1 TIM5_CH2 TIM5_CH3 AF3 AF4 AF5 AF6 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 TIM8_ETR TIM9_CH1 AF7 USART1/2/3 USART2_CTS USART2_RTS USART2_TX AF8 AF9 AF10 AF11 AF12 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS UART4_TX UART4_RX ETH_MII_CRS ETH_MII _RX_CLK ETH_RMII _REF_CLK ETH_MDIO AF13 DCMI AF014 AF15 EVENTOUT EVENTOUT EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 PA5 TIM2_CH1_ETR TIM8_CH1N SPI1_NSS SPI1_SCK SPI3_NSS I2S3_WS USART2_RX USART2_CK OTG_HS_ULPI_D0 ETH _MII_COL OTG_HS_SOF DCMI_HSYNC OTG_HS_ULPI_CK EVENTOUT EVENTOUT EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK TIM13_CH1 TIM14_CH1 OTG_FS_SOF ETH_MII _RX_DV ETH_RMII _CRS_DV DCMI_PIXCK EVENTOUT EVENTOUT EVENTOUT PA9 TIM1_CH2 I2C3_SMBA USART1_TX DCMI_D0 EVENTOUT Doc ID 15818 Rev 9 PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMS-SWDIO EVENTOUT PA14 PA15 PB0 JTCK-SWCLK JTDI TIM 2_CH1 TIM 2_ETR TIM1_CH2N TIM3_CH3 TIM8_CH2N SPI1_NSS SPI3_NSS I2S3_WS OTG_HS_ULPI_D1 ETH _MII_RXD2 EVENTOUT EVENTOUT EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 EVENTOUT PB2 PB3 JTDO/ TRACESWO TIM2_CH2 PB4 JTRST PB5 PB6 TIM3_CH1 TIM3_CH2 TIM4_CH1 I2C1_SMBA I2C1_SCL SPI1_SCK SPI1_MISO SPI1_MOSI SPI3_SCK I2S3_SCK SPI3_MISO SPI3_MOSI I2S3_SD USART1_TX CAN2_RX OTG_HS_ULPI_D7 ETH _PPS_OUT CAN2_TX DCMI_D10 DCMI_D5 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT Pinouts and pin description PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYNC EVENTOUT PB8 PB9 PB10 PB11 PB12 PB13 TIM2_CH3 TIM2_CH4 TIM1_BKIN TIM1_CH1N TIM4_CH3 TIM4_CH4 TIM10_CH1 TIM11_CH1 I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA I2C2_SMBA SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK USART3_TX USART3_RX USART3_CK USART3_CTS CAN1_RX ETH _MII_TXD3 SDIO_D4 CAN1_TX SDIO_D5 CAN2_RX CAN2_TX OTG_HS_ULPI_D3 ETH_ MII_RX_ER OTG_HS_ULPI_D4 ETH _MII_TX_EN ETH _RMII_TX_EN OTG_HS_ULPI_D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ULPI_D6 ETH _MII_TXD1 ETH _RMII_TXD1 OTG_HS_ID DCMI_D6 DCMI_D7 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT 53/177 Doc ID 15818 Rev 9 54/177 Table 8. Alternate function mapping (continued) Port PB14 PB15 PC0 AF0 AF1 SYS TIM1/2 RTC_50Hz TIM1_CH2N TIM1_CH3N AF2 TIM3/4/5 AF3 AF4 AF5 AF6 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 TIM8_CH2N TIM8_CH3N SPI2_MISO SPI2_MOSI I2S2_SD AF7 USART1/2/3 USART3_RTS AF8 UART4/5/ USART6 AF9 AF10 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS TIM12_CH1 TIM12_CH2 OTG_HS_ULPI_STP AF11 ETH AF12 FSMC/SDIO/ OTG_HS OTG_HS_DM OTG_HS_DP PC1 ETH_MDC PC2 SPI2_MISO OTG_HS_ULPI_DIR ETH _MII_TXD2 PC3 SPI2_MOSI OTG_HS_ULPI_NXT ETH _MII_TX_CLK PC4 ETH_MII_RXD0 ETH_RMII_RXD0 PC5 ETH _MII_RXD1 ETH _RMII_RXD1 PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 PC9 PC10 PC11 PC12 PC13 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN I2S3_CKIN SPI3_SCK I2S3_SCK SPI3_MISO SPI3_MOSI I2S3_SD USART3_TX USART3_RX USART3_CK UART4_TX UART4_RX UART5_TX SDIO_D1 SDIO_D2 SDIO_D3 SDIO_CK PC14-OSC32_IN PC15-OSC32_OUT PD0 CAN1_RX FSMC_D2 PD1 CAN1_TX FSMC_D3 PD2 TIM3_ETR UART5_RX SDIO_CMD PD3 USART2_CTS FSMC_CLK PD4 USART2_RTS FSMC_NOE PD5 USART2_TX FSMC_NWE PD6 USART2_RX FSMC_NWAIT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 PD8 USART3_TX FSMC_D13 PD9 USART3_RX FSMC_D14 PD10 USART3_CK FSMC_D15 PD11 USART3_CTS FSMC_A16 PD12 TIM4_CH1 USART3_RTS FSMC_A17 PD13 TIM4_CH2 FSMC_A18 AF13 DCMI DCMI_D0 DCMI_D1 DCMI_D2 DCMI_D3 DCMI_D8 DCMI_D4 DCMI_D9 AF014 AF15 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT DCMI_D11 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT STM32F20xxx Pinouts and pin description 55/177 Doc ID 15818 Rev 9 Table 8. Port PD14 PD15 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 TIM4_CH3 TIM4_CH4 TIM4_ETR TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TIM1_ETR TIM1_CH1N TIM1_CH1 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM9_CH1 TIM9_CH2 I2C2_SDA I2C2_SCL I2C2_SMBA TIM10_CH1 TIM11_CH1 AF8 AF9 AF10 AF11 AF12 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS FSMC_D0 FSMC_D1 FSMC_NBL0 FSMC_BLN1 ETH _MII_TXD3 FSMC_A23 FSMC_A19 FSMC_A20 FSMC_A21 FSMC_A22 FSMC_D4 FSMC_D5 FSMC_D6 FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 FSMC_D11 FSMC_D12 FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5 FSMC_NIORD FSMC_NREG TIM13_CH1 FSMC_NIOWR TIM14_CH1 FSMC_CD FSMC_INTR FSMC_A6 FSMC_A7 FSMC_A8 AF13 DCMI DCMI_D2 DCMI_D3 DCMI_D4 DCMI_D6 DCMI_D7 DCMI_D12 AF014 AF15 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT Pinouts and pin description STM32F20xxx Pinouts and pin description 56/177 Table 8. Port PF15 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF7 USART1/2/3 AF8 UART4/5/ USART6 AF9 AF10 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS AF11 ETH AF12 FSMC/SDIO/ OTG_HS FSMC_A9 AF13 DCMI AF014 AF15 EVENTOUT Doc ID 15818 Rev 9 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 - OSC_IN PH1 - OSC_OUT PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 TIM5_CH1 TIM5_CH2 TIM5_CH3 I2C2_SCL I2C2_SDA I2C2_SMBA I2C3_SCL I2C3_SDA I2C3_SMBA TIM8_CH1N USART6_CK USART6_RTS USART6_RX USART6_RTS UART6_CTS USART6_TX USART6_CTS FSMC_A10 FSMC_A11 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3 ETH _PPS_OUT FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 ETH _MII_TX_EN ETH _RMII_TX_EN FSMC_NCE4_2 FSMC_NE4 ETH _MII_TXD0 ETH _RMII_TXD0 ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A24 FSMC_A25 DCMI_D13 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT ETH _MII_CRS ETH _MII_COL OTG_HS_ULPI_NXT TIM12_CH1 ETH _MII_RXD2 ETH _MII_RXD3 TIM12_CH2 CAN1_TX DCMI_HSYNC DCMI_D0 DCMI_D1 DCMI_D2 DCMI_D3 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT STM32F20xxx 57/177 Doc ID 15818 Rev 9 Table 8. Port PH14 PH15 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 PI9 PI10 PI11 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 TIM5_CH4 TIM8_CH2N TIM8_CH3N TIM8_CH4 TIM8_ETR TIM8_BKIN TIM8_CH1 TIM8_CH2 TIM8_CH3 SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK SPI2_MISO SPI2_MOSI I2S2_SD AF7 USART1/2/3 AF8 UART4/5/ USART6 AF9 AF10 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS AF11 ETH AF12 FSMC/SDIO/ OTG_HS AF13 DCMI DCMI_D4 AF014 AF15 EVENTOUT DCMI_D11 EVENTOUT DCMI_D13 EVENTOUT DCMI_D8 EVENTOUT DCMI_D9 EVENTOUT DCMI_D10 EVENTOUT DCMI_D5 EVENTOUT DCMI_VSYNC EVENTOUT DCMI_D6 EVENTOUT DCMI_D7 EVENTOUT CAN1_RX ETH _MII_RX_ER OTG_HS_ULPI_DIR EVENTOUT EVENTOUT EVENTOUT Pinouts and pin description STM32F20xxx Memory mapping 4 Memory mapping The memory map is shown in Figure 14. STM32F20xxx 58/177 Doc ID 15818 Rev 9 STM32F20xxx Figure 14. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC registers 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 0x8000 0000 0x7FFF FFFF & bank4 512-Mbyte block 3 FSMC bank1 0x6000 0000 0x5FFF FFFF & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 0x0000 0000 512-Mbyte block 0 Code Reserved SRAM (16 KB aliased by bit-banding) SRAM (112 KB aliased by bit-banding) 0x2002 0000 - 0x3FFF FFFF 0x2001 C000 - 0x2001 FFFF 0x2000 0000 - 0x2001 BFFF Reserved 0x1FFF C008 - 0x1FFF FFFF Option Bytes 0x1FFF C000 - 0x1FFF C007 Reserved 0x1FFF 7A10 - 0x1FFF 7FFF System memory + OTP 0x1FFF 0000 - 0x1FFF 7A0F Reserved 0x0810 0000 - 0x0FFF FFFF Flash 0x0800 0000 - 0x080F FFFF Reserved 0x0001 C000 - 0x07FF FFFF Aliased to Flash, system memory or SRAM depending 0x0000 0000 - 0x000F FFFF on the BOOT pins Doc ID 15818 Rev 9 Memory mapping Reserved 0xA000 1000 - 0xBFFF FFFF FSMC control register 0xA000 0000 - 0xA000 0FFF FSMC bank4 PC Card 0x9000 0000 - 0x9FFF FFFF FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF Reserved RNG 0x5006 1000 - 0x5FFF FFFF 0x5006 0800 - 0x5006 0FFF Reserved 0x5005 0400 - 0x5006 7FFF DCMI 0x5005 0000 - 0x5005 03FF Reserved 0x5004 0000 - 0x5004 0FFF USB OTG FS 0x5000 0000 - 0x5003 FFFF Reserved 0x4002 9400 - 0x4FFF FFFF USB OTG HS 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 9400 - 0x4003 FFFF ETHERNET 0x4002 8000 - 0x4002 93FF Reserved 0x4002 6800 - 0x4002 7FFF DMA2 0x4002 6400 - 0x4002 67FF DMA1 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF BKPSRAM 0x4002 4000 - 0x4002 4FFF Flash interface 0x4002 3C00 - 0x4002 3FFF Reset clock controller (RCC) 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF CRC 0x4002 3000 - 0x4002 33FF Reserved 0x4002 2400 - 0x4002 2FFF Port I 0x4002 2000 - 0x4002 23FF Port H 0x4002 1C00 - 0x4002 1FFF Port G 0x4002 1800 - 0x4002 1BFF Port F 0x4002 1400 - 0x4002 17FF Port E 0x4002 1000 - 0x4002 13FF Port D 0x4002 0C00 - 0x4002 0FFF Port C 0x4002 0800 - 0x4002 0BFF Port B 0x4002 0400 - 0x4002 07FF Port A 0x4002 0000 - 0x4002 03FF Reserved 0x4001 4C00 - 0x4001 FFFF TIM11 0x4001 4800 - 0x4001 4BFF TIM10 0x4001 4400 - 0x4001 47FF TIM9 0x4001 4000 - 0x4001 43FF EXTI 0x4001 3C00 - 0x4001 3FFF SYSCFG 0x4001 3800 - 0x4001 3BFF Reserved 0x4001 3400 - 0x4001 37FF SPI1 0x4001 3000 - 0x4001 33FF SDIO Reserved Reserved 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF ADC1 - ADC2 - ADC3 0x4001 2000 - 0x4001 23FF Reserved 0x4001 1800 - 0x4001 1FFF USART6 0x4001 1400 - 0x4001 17FF USART1 Reserved 0x4001 1000 - 0x4001 13FF 0x4001 0800 - 0x4001 0FFF TIM8 / PWM2 0x4001 0400 - 0x4001 07FF TIM1 / PWM1 0x4001 0000 - 0x4001 03FF Reserved 0x4000 7800 - 0x4000 FFFF DAC1/DAC2 0x4000 7400 - 0x4000 77FF PWR 0x4000 7000 - 0x4000 73FF Reserved 0x4000 6C00 - 0x4000 6FFF BxCAN2 0x4000 6800 - 0x4000 6BFF BxCAN1 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF I2C3 0x4000 5C00 - 0x4000 5FFF I2C2 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF UART5 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF USART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF Reserved 0x4000 4000 - 0x4000 43FF SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF Reserved 0x4000 3400 - 0x4000 37FF IWDG 0x4000 3000 - 0x4000 33FF WWDG 0x4000 2C00 - 0x4000 2FFF RTC & BKP registers 0x4000 2800 - 0x4000 2BFF Reserved 0x4000 2400 - 0x4000 27FF TIM14 0x4000 2000 - 0x4000 23FF TIM13 0x4000 1C00 - 0x4000 1FFF TIM12 0x4000 1800 - 0x4000 1BFF TIM7 0x4000 1400 - 0x4000 17FF TIM6 0x4000 1000 - 0x4000 13FF TIM5 0x4000 0C00 - 0x4000 0FFF TIM4 0x4000 0800 - 0x4000 0BFF TIM3 0x4000 0400 - 0x4000 07FF TIM2 0x4000 0000 - 0x4000 03FF ai17615c 59/177 Electrical characteristics 5 Electrical characteristics STM32F20xxx 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 15. Pin input voltage The input voltage measurement on a pin of the device is described in Figure 16. Figure 15. Pin loading conditions Figure 16. Pin input voltage C = 50 pF 60/177 STM32F pin OSC_OUT (Hi-Z when using HSE or LSE) MS19011V1 STM32F pin VIN OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 Doc ID 15818 Rev 9 STM32F20xxx 5.1.6 Power supply scheme Figure 17. Power supply scheme VBAT 1.8-3.6 V Power switch Electrical characteristics Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Level shifter GP I/Os 2 × 2.2 μF VVCCAAPP__12 VDD 15 × 100 nF + 1 × 4.7 μF VDD 1/2/...14/15 VSS 1/2/...14/15 O UT IN Voltage regulator IO Logic Kernel logic (CPU, digital & RAM) VDD REGOFF IRROFF VDDA 100 nF + 1 μF VREF 100 nF + 1 μF VREF+ VREF- VSSA Flash memory ADC Analog RCs, PLL, ... ai17527e 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect REGOFF and IRROFF pins, refer to Section 2.2.16: Voltage regulator. 3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. Doc ID 15818 Rev 9 61/177 Electrical characteristics 5.1.7 Current consumption measurement Figure 18. Current consumption measurement scheme IDD_VBAT VBAT STM32F20xxx IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics, Table 10: Current characteristics, and Table 11: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) –0.3 4.0 Input voltage on five-volt tolerant pin(2) VIN Input voltage on any other pin VSS–0.3 VDD+4 V VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins |VSSX − VSS| Variations between all the different ground pins - 50 mV - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 10 for the values of the maximum allowed injected current. 62/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 10. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 120 IVSS Total current out of VSS ground lines (sink)(1) 120 Output current sunk by any I/O and control pin IIO Output current source by any I/Os and control pin 25 25 mA IINJ(PIN) (2) Injected current on five-volt tolerant I/O(3) Injected current on any other pin(4) –5/+0 ±5 ΣIINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 4. In this case HCLK = system clock/2. 70/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 19. Symbol Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM (1) Typ Max(2) Parameter Conditions fHCLK TA = 25 °C TA = TA = Unit 85 °C 105 °C 120 MHz 90 MHz 49 63 72 38 51 61 External clock(3), all peripherals enabled(4) 60 MHz 26 39 49 30 MHz 14 27 37 25 MHz 11 24 34 16 MHz(5) 8 21 30 IDD Supply current in Run mode 8 MHz 4 MHz 2 MHz 120 MHz 5 17 27 3 16 26 2 15 25 mA 21 34 44 External clock(3), all peripherals disabled 90 MHz 60 MHz 30 MHz 25 MHz 16 MHz(5) 8 MHz 4 MHz 17 30 40 12 25 35 7 20 30 5 18 28 4.0 17.0 27.0 2.5 15.5 25.5 2.0 14.7 24.8 2 MHz 1.6 14.5 24.6 1. Code and data processing running from SRAM1 using boot pins. 2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. In this case HCLK = system clock/2. Doc ID 15818 Rev 9 71/177 Electrical characteristics STM32F20xxx Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON 60 IDD(RUN) (mA) 50 105°C 40 85°C 70°C 30 55°C 30°C 20 0°C -45°C 10 0 0 20 40 60 80 100 120 CPU frequnecy (MHz) MS19014V1 Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF IDD(RUN) (mA) 30 25 20 15 10 5 0 0 105°C 85°C 70°C 55°C 30°C 0°C -45°C 20 40 60 80 100 120 CPU Frequency (MHz) MS19015V1 72/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON IDD(RUN) (mA) 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0 105 85 30°C -45°C 20 40 60 80 100 120 CPU frequnecy (MHz) MS19016V1 Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF (mA) I DD(RUN) 45.0 40.0 35.0 30.0 105 25.0 85 30°C 20.0 -45°C 15.0 10.0 5.0 0.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 CPU Frequency (MHz) MS19017V1 Doc ID 15818 Rev 9 73/177 Electrical characteristics STM32F20xxx Table 20. Typical and maximum current consumption in Sleep mode Typ Max(1) Symbol Parameter Conditions fHCLK TA = 25 °C TA = 85 °C TA = 105 °C Unit 120 MHz 38 51 61 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 External clock(2), all peripherals enabled(3) 25 MHz 8 16 MHz 6 25 35 21 31 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 IDD Supply current in Sleep mode 2 MHz 1.9 120 MHz 8 14.9 24.7 mA 21 31 90 MHz 7 20 30 60 MHz 5 18 28 External clock(2), all peripherals disabled 30 MHz 3.5 25 MHz 2.5 16 MHz 2.1 16.0 26.0 16.0 25.0 15.1 25.0 8 MHz 1.7 15.0 25.0 4 MHz 1.5 14.6 24.6 2 MHz 1.4 14.2 24.3 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 74/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 25. Typical current consumption vs temperature in Sleep mode, peripherals ON IDD(SLEEP) (mA) 50 45 40 35 30 25 20 15 10 5 0 0 105°C 85°C 70°C 55°C 30°C 0°C -45°C 20 40 60 80 100 120 CPU Frequency (MHz) MS19018V1 Figure 26. Typical current consumption vs temperature in Sleep mode, peripherals OFF IDD(SLEEP) (mA) 16 14 12 10 8 6 4 2 0 0 105°C 85°C 70°C 55°C 30°C 0°C -45°C 20 40 60 80 100 120 CPU Frequency (MHz) MS19019V1 Doc ID 15818 Rev 9 75/177 Electrical characteristics STM32F20xxx Table 21. Typical and maximum current consumptions in Stop mode(1) Symbol Parameter Conditions Typ TA = 25 °C TA = 25 °C Max TA = 85 °C TA = Unit 105 °C Flash in Stop mode, low-speed and high-speed Supply current internal RC oscillators and high-speed oscillator 0.55 in Stop mode OFF (no independent watchdog) with main Flash in Deep power down mode, low-speed regulator in and high-speed internal RC oscillators and Run mode high-speed oscillator OFF (no independent 0.50 watchdog) IDD_STOP Flash in Stop mode, low-speed and high-speed Supply current internal RC oscillators and high-speed oscillator 0.35 in Stop mode OFF (no independent watchdog) with main regulator in Flash in Deep power down mode, low-speed Low Power mode and high-speed internal RC oscillators and high-speed oscillator OFF (no independent 0.30 watchdog) 1.2 11.00 20.00 1.2 11.00 20.00 mA 1.1 8.00 15.00 1.1 8.00 15.00 1. All typical and maximum values will be further reduced by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes. Figure 27. Typical current consumption vs temperature in Stop mode 10 Idd_stop_mr_flhstop Idd_stop_mr_flhdeep Idd_stop_lp_flhstop Idd_stop_lp_flhdeep 1 IDD(STOP) (mA) 0.1 0.01 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) MS19020V1 1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes 76/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 22. Typical and maximum current consumptions in Standby mode Typ Max(1) Symbol Parameter Conditions TA = 25 °C TA = 85 °C TA = 105 °C Unit VDD = VDD= VDD = 1.8 V 2.4 V 3.3 V VDD = 3.6 V Backup SRAM ON, low-speed oscillator and RTC ON 3.0 3.4 4.0 Supply current Backup SRAM OFF, low- IDD_STBY in Standby speed oscillator and RTC ON 2.4 2.7 3.3 mode Backup SRAM ON, RTC OFF 2.4 2.6 3.0 15.1 12.4 12.5 Backup SRAM OFF, RTC OFF 1.7 1.9 2.2 9.8 25.8 20.5 µA 24.8 19.2 1. Based on characterization, not tested in production. Table 23. Typical and maximum current consumptions in VBAT mode Typ Max(1) Symbol Parameter Conditions TA = 25 °C TA = 85 °C TA = 105 °C Unit VDD = VDD= VDD = 1.8 V 2.4 V 3.3 V VDD = 3.6 V Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 12 Backup Backup SRAM OFF, low-speed IDD_VBAT domain supply oscillator and RTC ON 0.62 0.73 0.96 8 current Backup SRAM ON, RTC OFF 0.79 0.81 0.86 9 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 5 19 10 µA 16 7 1. Based on characterization, not tested in production. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 24. The MCU is placed under the following conditions: Doc ID 15818 Rev 9 77/177 Electrical characteristics STM32F20xxx ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled unless otherwise mentioned ● The given value is calculated by measuring the current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) ● The code is running from Flash memory and the Flash memory access time is equal to 3 wait states at 120 MHz ● Prefetch and Cache ON ● When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2 ● The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 24. Peripheral current consumption Peripheral(1) Typical consumption at 25 °C Unit GPIO A 0.45 GPIO B 0.43 GPIO C 0.46 GPIO D 0.44 GPIO E 0.44 GPIO F 0.42 GPIO G 0.44 GPIO H 0.42 AHB1 GPIO I OTG_HS + ULPI CRC BKPSRAM 0.43 3.64 1.17 mA 0.21 DMA1 2.76 DMA2 2.85 ETH_MAC + ETH_MAC_TX 2.99 ETH_MAC_RX ETH_MAC_PTP OTG_FS 3.16 AHB2 DCMI 0.60 AHB3 FSMC 1.74 78/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 24. Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 °C Unit TIM2 0.61 TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 APB1 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 0.25 0.25 0.25 0.25 mA 0.26 0.25 0.25 0.25 0.20/0.10 SPI3 CAN1 CAN2 DAC channel 1(2) DAC channel 1(3) PWR WWDG 0.18/0.09 0.31 0.30 1.11 1.11 0.15 0.15 Doc ID 15818 Rev 9 79/177 Electrical characteristics STM32F20xxx Table 24. Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 °C SDIO 0.69 TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 APB2 TIM11 ADC1(4) ADC2(4) ADC3(4) 0.39 2.13 2.04 2.12 SPI1 1.20 USART1 0.38 USART6 0.37 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register. Unit mA 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the RC oscillator ● Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 25. Low-power mode wakeup timings Symbol Parameter Min(1) Typ(1) Max(1) Unit tWUSLEEP(2) Wakeup from Sleep mode - 1 - µs Wakeup from Stop mode (regulator in Run mode) - 13 - tWUSTOP(2) Wakeup from Stop mode (regulator in low power mode) - 17 40 µs Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - tWUSTDBY(2)(3) Wakeup from Standby mode 260 375 480 µs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. 80/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 26 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 12. Table 26. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 - 26 MHz VHSEH VHSEL OSC_IN input pin high level voltage OSC_IN input pin low level voltage 0.7VDD - VDD V VSS - 0.3VDD tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 5 - - ns - - 20 - 5 - pF DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 27 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 12. Table 27. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) - 32.768 1000 kHz VLSEH VLSEL OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage 0.7VDD - VDD V VSS - 0.3VDD tw(LSE) tf(LSE) tr(LSE) tf(LSE) Cin(LSE) OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) OSC32_IN input capacitance(1) 450 - - ns - - 50 - 5 - pF DuCy(LSE) Duty cycle 30 - 70 % IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA 1. Guaranteed by design, not tested in production. Doc ID 15818 Rev 9 81/177 Electrical characteristics Figure 28. High-speed external clock source AC timing diagram STM32F20xxx VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) THSE tW(HSE) tW(HSE) t External clock source fHSE_ext OSC _IN IL STM32F Figure 29. Low-speed external clock source AC timing diagram ai17528 VLSEH VLSEL 90% 10% tr(LSE) tf(LSE) TLSE tW(LSE) tW(LSE) t External clock source fLSE_ext OSC32_IN IL STM32F ai17529 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 82/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Note: Table 28. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ IDD HSE current consumption VDD=3.3 V, ESR= 30 Ω, - 449 - CL=5 pF@25 MHz µA VDD=3.3 V, ESR= 30 Ω, - 532 - CL=10 pF@25 MHz gm Oscillator transconductance tSU(HSE(3) Startup time Startup 5 - - mA/V VDD is stabilized - 2 - ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 30. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MH z resonator OSC_IN RF Bias controlled gain CL2 REXT(1) OSC_OU T fHS E STM32F ai17530 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 15818 Rev 9 83/177 Electrical characteristics STM32F20xxx Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 µA gm Oscillator Transconductance tSU(LSE)(2) startup time 2.8 - VDD is stabilized - 2 - µA/V - s 1. Guaranteed by design, not tested in production. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: Note: Caution: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 31). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 31. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 32.768 kH z resonator CL2 OSC32_IN RF OSC32_OU T Bias controlled gain fLSE STM32F ai17531 84/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in Table 30 and Table 31 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. High-speed internal (HSI) RC oscillator Table 30. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency - 16 - MHz User-trimmed with the RCC_CR register(2) - - 1 % ACCHSI Accuracy of the HSI oscillator Factory- calibrated TA = –40 to 105 °C –8 TA = –10 to 85 °C –4 - 4.5 % 4 % TA = 25 °C –1 - 1 % tsu(HSI)(3) HSI oscillator startup time - 2.2 4 µs IDD(HSI) HSI oscillator power consumption - 60 80 µA 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. Figure 32. ACCHSI versus temperature Normalized deviation (%) max 6 avg min 4 2 0 -2 -4 -6 -8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (°C) MS19012V2 Doc ID 15818 Rev 9 85/177 Electrical characteristics Low-speed internal (LSI) RC oscillator Table 31. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Figure 33. ACCLSI versus temperature STM32F20xxx Min Typ Max Unit 17 32 47 kHz - 15 40 µs - 0.4 0.6 µA Normalized deviati on (%) 50 max 40 avg min 30 20 10 0 -10 -20 -30 -40 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperat ure (°C) MS19013V1 5.3.10 PLL characteristics The parameters given in Table 32 and Table 33 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 12. Table 32. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95 (2) 1 2.10(2) MHz fPLL_OUT fPLL48_OUT fVCO_OUT PLL multiplier output clock 48 MHz PLL multiplier output clock PLL VCO output 24 - - - 192 - 120 MHz 48 MHz 432 MHz 86/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 32. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit tLOCK Jitter(3) IDD(PLL)(4) IDDA(PLL)(4) PLL lock time VCO freq = 192 MHz 75 VCO freq = 432 MHz 100 RMS - Cycle-to-cycle jitter System clock 120 MHz peak to - peak RMS - Period Jitter peak to - peak Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - Main clock output (MCO) for MII Cycle to cycle at 25 MHz Ethernet on 1000 samples - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - VCO freq = 192 MHz 0.15 PLL power consumption on VDD VCO freq = 432 MHz 0.45 PLL power consumption on VDDA VCO freq = 192 MHz 0.30 VCO freq = 432 MHz 0.55 25 ±150 15 ±200 32 40 330 - 200 µs 300 - - - - ps - - 0.40 mA 0.75 0.40 mA 0.85 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 33. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions fPLLI2S_IN fPLLI2S_OUT fVCO_OUT PLLI2S input clock(1) PLLI2S multiplier output clock PLLI2S VCO output tLOCK PLLI2S lock time VCO freq = 192 MHz VCO freq = 432 MHz Min Typ 0.95(2) 1 - - 192 - 75 - 100 - Max 2.10(2) 216 432 200 300 Unit MHz MHz MHz µs Doc ID 15818 Rev 9 87/177 Electrical characteristics STM32F20xxx Table 33. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Jitter(3) Master I2S clock jitter Cycle to cycle at RMS - 90 - 12.288 MHz on 48KHz period, N=432, R=5 peak to - peak ±280 - Average frequency of 12.288 MHz N=432, R=5 on 1000 samples - 90 - WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - IDD(PLLI2S)(4) PLLI2S power consumption on VDD IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.40 - 0.45 0.75 0.30 0.40 - 0.55 0.85 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Unit ps ps ps mA mA 88/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 40: EMI characteristics). It is available only on the main PLL. Table 34. SSCG parameters constraint Symbol Parameter fMod md MODEPER * INCSTEP Modulation frequency Peak modulation depth 1. Guaranteed by design, not tested in production. Min - 0.25 - Typ Max(1) Unit - 10 KHz - 2 % - 215−1 - Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round[fPLL_IN ⁄ (4 × fMod)] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: MODEPER = round[106 ⁄ (4 × 103)] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN) As a result: mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.0002%(peak) Doc ID 15818 Rev 9 89/177 Electrical characteristics STM32F20xxx Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 34. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) md F0 md tmode 2*tmode Figure 35. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) Time ai17291 F0 2*md tmode 2*tmode Time ai17292 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 35. Flash memory characteristics Symbol Parameter Conditions IDD Supply current Write / Erase 8-bit mode VDD = 1.8 V Write / Erase 16-bit mode VDD = 2.1 V Write / Erase 32-bit mode VDD = 3.3 V Min Typ Max Unit - 5 - - 8 - mA - 12 - 90/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 36. Flash memory programming Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog Word programming time Program/erase parallelism (PSIZE) = x 8/16/32 - Program/erase parallelism (PSIZE) = x 8 - tERASE16KB Sector (16 KB) erase time Program/erase parallelism (PSIZE) = x 16 - 16 100(2) µs 400 800 300 600 ms Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 tERASE64KB Sector (64 KB) erase time Program/erase parallelism (PSIZE) = x 16 - 700 1400 ms Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 tERASE128KB Sector (128 KB) erase time Program/erase parallelism (PSIZE) = x 16 - Program/erase parallelism (PSIZE) = x 32 - Program/erase parallelism (PSIZE) = x 8 - tME Mass erase time Program/erase parallelism (PSIZE) = x 16 - Program/erase parallelism (PSIZE) = x 32 - 1.3 2.6 s 1 2 16 32 11 22 s 8 16 Vprog Programming voltage 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. Table 37. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Mass erase time Vprog Programming voltage TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - ms - 875 - - 6.9 - s 2.7 - 3.6 V Doc ID 15818 Rev 9 91/177 Electrical characteristics STM32F20xxx 5.3.13 Table 37. Flash memory programming with VPP (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit VPP VPP voltage range 7 - IPP Minimum current sunk on the VPP pin 10 - tVPP(3) Cumulative time during which VPP is applied - - 1. Guaranteed by design, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. 9 V - mA 1 hour Table 38. Flash memory endurance and data retention Symbol Parameter Conditions NEND tRET Endurance Data retention TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 1 kcycle(2) at TA = 85 °C 1 kcycle(2) at TA = 105 °C 10 kcycles(2) at TA = 55 °C 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. Value Min(1) 10 30 10 20 Unit kcycles Years EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. ● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 39. They are based on the EMS levels and classes defined in application note AN1709. 92/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 39. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 °C, fHCLK = 75 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 °C, fHCLK = 75 MHz, conforms to 4A IEC 61000-4-2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Doc ID 15818 Rev 9 93/177 Electrical characteristics STM32F20xxx Table 40. EMI characteristics Symbol Parameter Conditions SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, PLL spread spectrum enabled Monitored frequency band 0.1 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz SAE EMI Level 0.1 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz SAE EMI level Max vs. [fHSE/fCPU] 8/120 MHz 21 28 31 4 21 15 14 3.5 Unit dBµV - dBµV - 5.3.14 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 41. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) VESD(CDM) Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-A114 2 TA = +25 °C conforming to JESD22-C101 II 2000(2) V 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. 94/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 42. Electrical sensitivities Symbol Parameter Conditions LU Static latch-up class TA = +105 °C conforming to JESD78A Class II level A 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 43. Table 43. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Positive Unit injection injection Injected current on all FT pins IINJ Injected current on any other pin –5 +0 mA –5 +5 Doc ID 15818 Rev 9 95/177 Electrical characteristics STM32F20xxx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL compliant. Table 44. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL VIH(1) Input low level voltage TT(2) I/O input high level voltage FT(3) I/O input high level voltage VSS–0.3 - 0.8 TTL ports 2.0 2.7 V ≤ VDD ≤ 3.6 V - VDD+0.3 2.0 - 5.5 VIL Input low level voltage TT I/O input high level voltage VIH(1) FT I/O input high level voltage CMOS ports VSS–0.3 - 0.3VDD V - 3.6(4) 1.8 V ≤ VDD ≤ 3.6 V - 5.2(4) 0.7VDD CMOS ports 2.0 V ≤ VDD ≤ 3.6 V - 5.5(4) I/O Schmitt trigger voltage hysteresis(5) - 200 - Vhys IO FT Schmitt trigger voltage hysteresis(5) 5% VDD(4) - mV - I/O input leakage current (6) Ilkg I/O FT input leakage current (6) VSS ≤ VIN ≤ VDD VIN = 5 V - - ±1 µA - - 3 All pins except for RPU Weak pull-up equivalent PA10 and resistor(7) PB12 VIN = VSS 30 40 50 RPD Weak pull-down equivalent resistor PA10 and PB12 All pins except for PA10 and PB12 VIN = VDD 8 11 15 kΩ 30 40 50 PA10 and PB12 8 11 15 CIO(8) I/O pin capacitance 5 pF 1. If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value. 2. TT = 3.6 V tolerant. 3. FT = 5 V tolerant. 4. With a minimum of 100 mV. 5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 8. Guaranteed by design, not tested in production. 96/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 10). ● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 10). Output voltage levels Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. All I/Os are CMOS and TTL compliant. Table 45. Output voltage characteristics(1) Symbol Parameter Conditions Min Max Unit VOL(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS ports - 0.4 IIO = +8 mA V VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL ports - IIO =+ 8mA VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V 2.4 0.4 V - VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA - 1.3 V VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.7 V < VDD < 3.6 V VDD–1.3 - VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA - 0.4 V VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2 V < VDD < 2.7 V VDD–0.4 - 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Doc ID 15818 Rev 9 97/177 Electrical characteristics STM32F20xxx 4. Based on characterization data, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 46, respectively. Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 46. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(3) 00 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(3) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(3) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Conditions Min CL = 50 pF, VDD > 2.70 V - CL = 50 pF, VDD > 1.8 V - CL = 10 pF, VDD > 2.70 V - CL = 10 pF, VDD > 1.8 V - CL = 50 pF, VDD = 1.8 V to 3.6 V - CL = 50 pF, VDD > 2.70 V - CL = 50 pF, VDD > 1.8 V - CL = 10 pF, VDD > 2.70 V - CL = 10 pF, VDD > 1.8 V - CL = 50 pF, VDD < 2.7 V - CL = 10 pF, VDD > 2.7 V - CL = 50 pF, VDD < 2.7 V - CL = 10 pF, VDD > 2.7 V - CL = 40 pF, VDD > 2.70 V - CL = 40 pF, VDD > 1.8 V - CL = 10 pF, VDD > 2.70 V - CL = 10 pF, VDD > 1.8 V - CL = 50 pF, 2.4 < VDD < 2.7 V - CL = 10 pF, VDD > 2.7 V - CL = 50 pF, 2.4 < VDD < 2.7 V - CL = 10 pF, VDD > 2.7 V - Typ Max Unit - 2 - 2 MHz - TBD - TBD - TBD ns - TBD - 25 - 12.5(4) MHz - 50(4) - TBD - TBD - TBD ns - TBD - TBD - 50(4) - 25 MHz - 100(4) - TBD - TBD - TBD ns - TBD - TBD 98/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 46. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit Fmax(IO)out Maximum frequency(3) CL = 30 pF, VDD > 2.70 V CL = 30 pF, VDD > 1.8 V CL = 10 pF, VDD > 2.70 V - - 100(4) - - 50(4) MHz - - 200(4) CL = 10 pF, VDD > 1.8 V - - TBD 11 tf(IO)out Output high to low level fall time CL = 20 pF, 2.4 < VDD < 2.7 V - CL = 10 pF, VDD > 2.7 V - - TBD - TBD ns tr(IO)out Output low to high level rise time CL = 20 pF, 2.4 < VDD < 2.7 V CL = 10 pF, VDD > 2.7 V - - TBD - TBD Pulse width of external signals - tEXTIpw detected by the EXTI controller 10 - - ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 2. TBD stands for “to be defined”. 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz, the compensation cell should be used. Figure 36. I/O AC characteristics definition 90% 50% 10% 10% 50% 90% EXT ERNAL O UTP UT ON 50pF tr(I O)out tr(I O)out T Maximum fr equency is achieved if (tr + tf) 2/3) T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 Doc ID 15818 Rev 9 99/177 Electrical characteristics STM32F20xxx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 44). Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 47. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) VIH(NRST)(1) VIL(NRST)(1) VIH(NRST)(1) NRST input low level voltage NRST input high level voltage NRST input low level voltage NRST input high level voltage TTL ports VSS−0.3 - 0.8 V 2.7 V ≤ VDD ≤ 3.6 V 2 - VDD+0.3 CMOS ports VSS−0.3 - 0.3VDD V 1.8 V ≤ VDD ≤ 3.6 V 0.7VDD - VDD+0.3 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU VF(NRST)(1) VNF(NRST)(1) Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse VIN = VSS VDD > 2.7 V 30 40 50 kΩ - - 100 ns 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 37. Recommended NRST pin protection External reset circuit(1) VDD NRST(2) RPU 0.1 μF Internal Reset Filter STM32Fxxx ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 47. Otherwise the reset is not taken into account by the device. 100/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Table 48 and Table 49 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 48. Characteristics of TIMx connected to the APB1 domain(1) Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB1 prescaler distinct from 1, fTIMxCLK = 60 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 30 MHz 1 16.7 1 33.3 - tTIMxCLK - ns - tTIMxCLK - ns fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 30 MHz ResTIM Timer resolution - 16/32 bit tCOUNTER 16-bit counter clock period when internal clock is selected fTIMxCLK = 60 MHz APB1= 30 MHz 32-bit counter clock period when internal clock is selected 1 0.0167 1 0.0167 65536 1092 71582788 tTIMxCLK µs tTIMxCLK µs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 71.6 s 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Doc ID 15818 Rev 9 101/177 Electrical characteristics STM32F20xxx Table 49. Characteristics of TIMx connected to the APB2 domain(1) Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 120 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 60 MHz 1 8.3 1 16.7 - tTIMxCLK - ns - tTIMxCLK - ns fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 60 MHz ResTIM tCOUNTER Timer resolution - 16-bit counter clock period fTIMxCLK = 120 MHz 1 when internal clock is APB2 = 60 MHz selected 0.0083 16 65536 546 bit tTIMxCLK µs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 35.79 s 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 5.3.19 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 12. STM32F205xx and STM32F207xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 50. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). 102/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 50. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Min Max Min Max Unit tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time 4.7 - 4.0 - 250 - 0 - 1.3 - µs 0.6 - 100 - 0 900(3) - 1000 20 + 0.1Cb 300 ns - 300 - 300 4.0 - 0.6 - µs 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must achieve fast be at least 2 MHz to achieve mode I2C frequencies, and a standard mode I2C frequencies. It must multiple of 10 MHz to reach the 400 kHz be at least 4 MHz maximum I2C fast to mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. Doc ID 15818 Rev 9 103/177 Electrical characteristics Figure 38. I2C bus AC waveforms and measurement circuit VDD VDD I²C bus 4 .7 kΩ 4 .7 kΩ 100 Ω 100 Ω STM32Fxx SDA SCL STM32F20xxx SD A tf(SDA) S TART S TART REPEATED tsu(STA) S TART tr(SDA) tsu(SDA) th(STA) tw(SCLL) th(SDA) S TOP tw(STO:STA) SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14979b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 51. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2) fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. 104/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 52. SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency SPI1 master/slave mode SPI2/SPI3 master/slave mode - 30 MHz - 15 tr(SCL) tf(SCL) SPI clock rise and fall Capacitive load: C = 30 pF, time fPCLK = 30 MHz DuCy(SCK) SPI slave input clock duty cycle Slave mode tsu(NSS)(1) th(NSS)(1) tw(SCLH)(1) tw(SCLL)(1) NSS setup time Slave mode NSS hold time Slave mode SCK high and low time Master mode, fPCLK = 30 MHz, presc = 2 tsu(MI) (1) tsu(SI)(1) Master mode Data input setup time Slave mode - 8 ns 30 70 % 4tPCLK - 2tPCLK - tPCLK-3 tPCLK+3 5 - 5 - th(MI) (1) th(SI)(1) Data input hold time ta(SO)(1)(2) Data output access time Master mode Slave mode Slave mode, fPCLK = 30 MHz 5 - 4 - ns 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 th(SO)(1) Slave mode (after enable edge) 15 - Data output hold time th(MO)(1) Master mode (after enable edge) 2 - 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 15818 Rev 9 105/177 Electrical characteristics Figure 39. SPI timing diagram - slave mode and CPHA = 0 SCK Input NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tSU(NSS) tc(SCK) tw(SCKH) tw(SCKL) ta(SO) MISO OUT P UT MOSI I NPUT tsu(SI) tv(SO) MS B O UT M SB IN th(SI) th(SO) BI T6 OUT B I T1 IN Figure 40. SPI timing diagram - slave mode and CPHA = 1 STM32F20xxx th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14134c SCK Input NSS input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) MISO OUT P UT MOSI I NPUT ta(SO) tsu(SI) tc(SCK) tv(SO) MS B O UT th(SI) M SB IN th(SO) BI T6 OUT B I T1 IN th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14135 106/177 Doc ID 15818 Rev 9 STM32F20xxx Figure 41. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) SCK Input SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT tsu(MI) MOSI OUTU T tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) BI T6 IN B I T1 OUT th(MO) Electrical characteristics tr(SCK) tf(SCK) LSB IN LSB OUT ai14136 Doc ID 15818 Rev 9 107/177 Electrical characteristics STM32F20xxx Table 53. I2S characteristics Symbol Parameter Conditions Min Max Unit fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) tv(WS) (3) th(WS) (3) tsu(WS) (3) th(WS) (3) tw(CKH) (3) tw(CKL) (3) tsu(SD_MR) (3) tsu(SD_SR) (3) th(SD_MR)(3)(4) th(SD_SR) (3)(4) I2S clock rise and fall time WS valid time WS hold time WS setup time WS hold time CK high and low time Data input setup time Data input hold time tv(SD_ST) (3)(4) Data output valid time Master, 16-bit data, audio frequency = 48 kHz, main clock disabled Slave capacitive load CL = 50 pF Master Master Slave Slave Master fPCLK= 30 MHz Master receiver Slave receiver Master receiver: fPCLK= 30 MHz, Slave receiver: fPCLK= 30 MHz Slave transmitter (after enable edge) 1.23 0 - 0.3 0 3 0 396 45 0 13 0 - 1.24 64FS(1) (2) MHz - - ns - 30 th(SD_ST) (3) Data output hold time Slave transmitter (after enable edge) 10 - tv(SD_MT) (3)(4) Data output valid time Master transmitter (after enable edge) - 6 th(SD_MT) (3) Data output hold time Master transmitter (after enable edge) 0 - 1. FS is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. fCK values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of (I2SDIV+ODD)/(2*I2SDIV+ODD) and FS maximum values for each mode/condition. 2. Refer to Table 46: I/O AC characteristics. 3. Based on design simulation and/or characterization results, not tested in production. 4. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. 108/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 42. I2S slave timing diagram (Philips protocol)(1) tc(CK) CPOL = 0 CK Input CPOL = 1 WS input SDtransmit SDreceive tw(CKH) tw(CKL) th(WS) tsu(WS) LSB transmit(2) tsu(SD_SR) LSB receive(2) MSB transmit MSB receive tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive th(SD_ST) LSB transmit LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 43. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output CPOL = 0 CPOL = 1 WS output SDtransmit SDreceive tc(CK) tw(CKH) tv(WS) tw(CKL) th(WS) tv(SD_MT) LSB transmit(2) MSB transmit Bitn transmit tsu(SD_MR) LSB receive(2) MSB receive th(SD_MR) Bitn receive th(SD_MT) LSB transmit LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Doc ID 15818 Rev 9 109/177 Electrical characteristics STM32F20xxx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 54. USB OTG FS startup time Symbol Parameter tSTARTUP(1) USB OTG FS transceiver startup time 1. Guaranteed by design, not tested in production. Max Unit 1 µs Table 55. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit VDD USB OTG FS operating voltage 3.0(2) - 3.6 V VDI(3) Differential input sensitivity Input I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - levels VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 V VSE(3) Single ended receiver threshold 1.3 - 2.0 Output VOL Static output level low levels VOH Static output level high RL of 1.5 kΩ to 3.6 V(4) - - 0.3 V RL of 15 kΩ to VSS(4) 2.8 - 3.6 PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VDD 17 21 24 0.65 1.1 2.0 kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 RPU PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F205xx and STM32F207xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers 110/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 44. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines VCR S Crossover points VS S tf tr ai14137 Table 56. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) tf Fall time(2) CL = 50 pF 4 CL = 50 pF 4 20 ns 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). USB HS characteristics Table 57 shows the USB HS operating voltage. Table 57. USB HS DC electrical characteristics Symbol Parameter Input level VDD USB OTG HS operating voltage 1. All the voltages are measured from the local ground potential. Min.(1) 2.7 Max.(1) 3.6 Unit V Table 58. Clock timing parameters Parameter(1) Symbol Frequency (first transition) 8-bit ±10% FSTART_8BIT Frequency (steady state) ±500 ppm FSTEADY Duty cycle (first transition) 8-bit ±10% DSTART_8BIT Duty cycle (steady state) ±500 ppm DSTEADY Time to reach the steady state frequency and duty cycle after the first transition TSTEADY Clock startup time after the de-assertion of SuspendM Peripheral Host TSTART_DEV TSTART_HOST PHY preparation time after the first transition of the input clock TPREP 1. Guaranteed by design, not tested in production. Min Nominal Max Unit 54 59.97 40 49.975 60 66 MHz 60 60.03 MHz 50 60 % 50 50.025 % - - 1.4 ms - - 5.6 ms - - - - - - µs Doc ID 15818 Rev 9 111/177 Electrical characteristics Figure 45. ULPI timing diagram Clock tSC Control In (ULPI_DIR, ULPI_NXT) tSD data In (8-bit) Control out (ULPI_STP) data out (8-bit) tHC tHD tDC tDD STM32F20xxx tDC ai17361c Table 59. ULPI timing Symbol Parameter Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time tHC Control in (ULPI_DIR, ULPI_NXT) hold time tSD Data in setup time tHD Data in hold time tDC Control out (ULPI_STP) setup time and hold time tDD Data out available from clock rising edge 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Ethernet characteristics Table 60 shows the Ethernet operating voltage. Table 60. Ethernet DC electrical characteristics Symbol Parameter Input level VDD Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Value(1) Min. Max. Unit - 2.0 - 1.5 0 - - 2.0 ns 0 - - 9.2 - 10.7 Min.(1) 2.7 Max.(1) 3.6 Unit V Table 61 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 46 shows the corresponding timing diagram. 112/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 46. Ethernet SMI timing diagram ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) Table 61. Dynamics characteristics: Ethernet MAC signals for SMI Symbol Rating Min Typ Max tMDC MDC cycle time (2.38 MHz) td(MDIO) MDIO write data valid time tsu(MDIO) Read data setup time th(MDIO) Read data hold time 411 420 425 6 10 13 12 - - 0 - - ai15666d Unit ns ns ns ns Table 62 gives the list of Ethernet MAC signals for the RMII and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tih(RXD) tih(CRS) ai15667 Table 62. Dynamics characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) td(TXEN) td(TXD) Receive data setup time Receive data hold time Carrier sense set-up time Carrier sense hold time Transmit enable valid delay time Transmit data valid delay time 1 - - 1.5 - - 0 - - 2 - - 9 11 13 9 11.5 14 Unit ns Doc ID 15818 Rev 9 113/177 Electrical characteristics STM32F20xxx Table 63 gives the list of Ethernet MAC signals for MII and Figure 47 shows the corresponding timing diagram. Figure 48. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER tih(RXD) tih(ER) tih(DV) MII_TX_CLK MII_TX_EN MII_TXD[3:0] td(TXEN) td(TXD) ai15668 Table 63. Dynamics characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) tih(RXD) tsu(DV) tih(DV) tsu(ER) tih(ER) td(TXEN) td(TXD) Receive data setup time Receive data hold time Data valid setup time Data valid hold time Error setup time Error hold time Transmit enable valid delay time Transmit data valid delay time 7.5 - 1 - 4 - 0 - 3.5 - 0 - - 11 - 11 - ns - ns - ns - ns - ns - ns 14 ns 14 ns CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 114/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 64 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 12. Table 64. ADC characteristics Symbol Parameter Conditions Min Typ Max VDDA Power supply VREF+ Positive reference voltage fADC ADC clock frequency fTRIG(3) External trigger frequency VDDA = 1.8(1) to 2.4 V VDDA = 2.4 to 3.6 V fADC = 30 MHz with 12-bit resolution 1.8(1) 1.8(1)(2) 0.6 0.6 - - - 3.6 - VDDA - 15 - 30 - 1764 - 17 VAIN Conversion voltage range(4) 0 (VSSA or VREFtied to ground) - VREF+ RAIN(3) External input impedance See Equation 1 for details - RADC(3)(5) Sampling switch resistance 1.5 CADC(3) Internal sample and hold capacitor - - 50 - 6 4 - tlat(3) Injection trigger conversion latency fADC = 30 MHz - - 0.100 - 3(6) tlatr(3) Regular trigger conversion latency fADC = 30 MHz - - 0.067 - 2(6) tS(3) Sampling time tSTAB(3) Power-up time fADC = 30 MHz fADC = 30 MHz 12-bit resolution 0.100 3 - 0.5 - 16 - 480 2 3 - 16.40 fADC = 30 MHz 0.43 10-bit resolution - 16.34 tCONV(3) Total conversion time (including sampling time) fADC = 30 MHz 8-bit resolution 0.37 - 16.27 fADC = 30 MHz 0.3 - 16.20 6-bit resolution 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Unit V V MHz MHz kHz 1/fADC V kΩ kΩ pF µs 1/fADC µs 1/fADC µs 1/fADC µs µs µs µs µs 1/fADC Doc ID 15818 Rev 9 115/177 Electrical characteristics STM32F20xxx Table 64. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution - Single ADC Sampling rate fS(3) (fADC = 30 MHz) 12-bit resolution Interleave Dual ADC - mode 12-bit resolution Interleave Triple ADC - mode fADC = 30 MHz 3 sampling time - IVREF+(3) ADC VREF DC current consumption in conversion mode 12-bit resolution fADC = 30 MHz 480 sampling time - 12-bit resolution fADC = 30 MHz 3 sampling time - IVDDA(3) ADC VDDA DC current consumption in conversion mode 12-bit resolution fADC = 30 MHz 480 sampling time - 12-bit resolution - 2 Msps - 3.75 Msps - 6 Msps 300 500 µA - 16 µA 1.6 1.8 mA - 60 µA 1. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature range. 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. Based on characterization, not tested in production. 4. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 5. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 6. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 64. Equation 1: RAIN max formula RAIN = -------------------(--k------–-----0----.--5-----)------------------- fADC × CADC × ln (2N + 2) – RADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. 116/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Note: a Table 65. Symbol ADC accuracy (1) Parameter Test conditions Typ Max(2) Unit ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V ±2 ±1.5 ±1.5 ±1 ±1.5 ±5 ±2.5 ±3 LSB ±2 ±3 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. 3. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature range. ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 49. ADC accuracy characteristics 4095 4094 4093 7 6 5 4 3 2 1 [1LSBIDEAL =VREF+ 4096 (or VDDA depending 4096 on package)] EG (2) ET (3) (1) EO EL ED 1L SBIDEAL 0 1 2 3 456 VSSA 7 4093 4094 4095 4096 VDDA ai14395c 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Doc ID 15818 Rev 9 117/177 Electrical characteristics STM32F20xxx Figure 50. Typical connection diagram using the ADC RAIN(1) AINx VAIN Cparasitic VDD VT 0.6 V VT 0.6 V STM32F Sample and hold ADC converter RADC(1) 12-bit converter IL±1 µA CADC(1) ai17534 1. Refer to Table 64 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 118/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 µF // 10 nF 1 µF // 10 nF V DDA V SSA/V REF(See note 1) ai17535 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai17536 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Doc ID 15818 Rev 9 119/177 Electrical characteristics STM32F20xxx 5.3.21 DAC electrical characteristics Table 66. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA VREF+ VSSA RLOAD(2) Analog supply voltage 1.8(1) Reference supply voltage 1.8(1) Ground 0 Resistive load with buffer ON 5 RO(2) Impedance output with buffer OFF - CLOAD(2) Capacitive load - DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON 0.2 DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - DAC_OUT Higher DAC_OUT voltage max(2) with buffer OFF - - IVREF+(4) DAC DC VREF current consumption in quiescent mode (Standby mode) - - DAC DC VDDA current IDDA(4) consumption in quiescent mode(3) - - 3.6 V - 3.6 V VREF+ ≤ VDDA - 0 V - - kΩ When the buffer is OFF, the - 15 kΩ Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Maximum capacitive load at - 50 pF DAC_OUT pin (when the buffer is ON). It gives the maximum output - - V excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = - VDDA – 0.2 V 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V 0.5 - mV It gives the maximum output excursion of the DAC. - VREF+ – 1LSB V With no load, worst code (0x800) 170 240 at VREF+ = 3.6 V in terms of DC consumption on the inputs µA With no load, worst code (0xF1C) 50 75 at VREF+ = 3.6 V in terms of DC consumption on the inputs 280 380 µA With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) 475 625 µA at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - - - ±0.5 LSB Given for the DAC in 10-bit configuration. ±2 LSB Given for the DAC in 12-bit configuration. 120/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 66. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Integral non linearity (difference between - - INL(4) measured value at Code i and the value at Code i on a line drawn between Code 0 - - and last Code 1023) Offset error - - Offset(4) (difference between measured value at Code - - (0x800) and the ideal value = VREF+/2) - - Gain error(4) Gain error - - Settling time (full scale: for a 10-bit input code transition tSETTLING(4) between the lowest and the highest input codes when - 3 DAC_OUT reaches final value ±4LSB THD(4) Total Harmonic Distortion Buffer ON - - Max frequency for a correct Update rate(2) DAC_OUT change when small variation in the input - - code (from code i to i+1LSB) Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC - –67 measurement) ±1 ±4 ±10 ±3 ±12 ±0.5 LSB Given for the DAC in 10-bit configuration. LSB Given for the DAC in 12-bit configuration. mV Given for the DAC in 12-bit configuration LSB Given for the DAC in 10-bit at VREF+ = 3.6 V LSB Given for the DAC in 12-bit at VREF+ = 3.6 V % Given for the DAC in 12-bit configuration 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 10 µs input code between lowest and highest possible ones. –40 dB No RLOAD, CLOAD = 50 pF 1. If IRROFF is set to VDD, this value can be lowered to 1.7 V when the device operates in the 0 to 70 °C temperature range. 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Doc ID 15818 Rev 9 121/177 Electrical characteristics STM32F20xxx Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) 12-bit digital to analog converter DACx_OUT R LOAD C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.22 Temperature sensor characteristics Table 67. TS characteristics Symbol Parameter Min Typ TL(1) VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) tSTART(2) Voltage at 25 °C Startup time TS_temp(3)(2) ADC sampling time when reading the temperature 1°C accuracy - ±1 - 2.5 - 0.76 - 6 10 - 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Max Unit ±2 °C mV/°C V 10 µs - µs 5.3.23 VBAT monitoring characteristics Table 68. VBAT monitoring characteristics Symbol Parameter Min Typ R Q Er(1) TS_vbat(2)(2) Resistor bridge for VBAT Ratio on VBAT measurement Error on Q ADC sampling time when reading the VBAT 1mV accuracy - 50 - 2 –1 - 5 - 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. Max +1 - Unit KΩ % µs 122/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.24 5.3.25 Embedded reference voltage The parameters given in Table 69 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 69. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage ADC sampling time when TS_vrefint(1) reading the internal reference voltage –40 °C < TA < +105 °C 1.18 10 1.21 - VRERINT_s (2) Internal reference voltage spread over the temperature range VDD = 3 V - 3 TCoeff(2) Temperature coefficient tSTART(2) Startup time - 30 - 6 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 1.24 V - µs 5 mV 50 ppm/°C 10 µs FSMC characteristics Asynchronous waveforms and timings Figure 54 through Figure 57 represent asynchronous waveforms and Table 70 through Table 73 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● AddressSetupTime = 1 ● AddressHoldTime = 1 ● DataSetupTime = 1 ● BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Doc ID 15818 Rev 9 123/177 Electrical characteristics STM32F20xxx Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] tv(A_NE) tv(BL_NE) Address t h(A_NOE) t h(BL_NOE) FSMC_D[15:0] FSMC_NADV(1) t v(NADV_NE) tw(NADV) tsu(Data_NOE) tsu(Data_NE) Data t h(Data_NE) th(Data_NOE) 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. ai14991c Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 2THCLK– 0.5 2THCLK+0.5 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 2.5 ns tw(NOE) FSMC_NOE low time 2THCLK- 1 2THCLK+ 0.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4 ns th(A_NOE) Address hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 0.5 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+ 2.5 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2.5 ns tw(NADV) FSMC_NADV low time - THCLK– 0.5 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 124/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx tw(NE) FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV(1) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) t v(NADV_NE) tw(NADV) th(A_NWE) Address th(BL_NWE) NBL th(Data_NWE) Data t h(NE_NWE) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK– 0.5 THCLK+ 0.5 ns tw(NWE) FSMC_NWE low time THCLK– 0.5 THCLK+ 3 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns th(A_NWE) Address hold time after FSMC_NWE high THCLK- 3 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK– 1 - ns tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+ 5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK+ 1.5 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 15818 Rev 9 125/177 Electrical characteristics STM32F20xxx Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_AD[15:0] FSMC_NADV t w(NOE) tv(A_NE) tv(BL_NE) Address NBL th(A_NOE) th(BL_NOE) t v(A_NE) Address t v(NADV_NE) tw(NADV) tsu(Data_NE) tsu(Data_NOE) Data th(AD_NADV) th(Data_NE) th(Data_NOE) ai14892b Table 72. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK-1 3THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK 2THCLK+0.5 ns tw(NOE) FSMC_NOE low time THCLK-1 THCLK+1 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 2 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2.5 ns tw(NADV) FSMC_NADV low time THCLK– 1.5 THCLK ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 2 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+ 3 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 126/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx tw(NE) FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_AD[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE) Address t v(NADV_NE) tw(NADV) th(A_NWE) Address th(BL_NWE) NBL t v(Data_NADV) Data th(AD_NADV) t h(NE_NWE) th(Data_NWE) FSMC_NADV ai14891B Table 73. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low tim e FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD(adress) valid hold time after FSMC_NADV high) 4THCLK-1 THCLK- 1 2THCLK THCLK- 1 1 THCLK– 2 THCLK 4THCLK+1 ns THCLK ns 2THCLK+1 ns - ns 0 ns 2 ns THCLK+ 2 ns - ns th(A_NWE) th(BL_NWE) tv(BL_NE) tv(Data_NADV) th(Data_NWE) Address hold time after FSMC_NWE high FSMC_BL hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_NADV high to Data valid Data hold time after FSMC_NWE high THCLK– 0.5 - ns THCLK- 1 - ns - 0.5 ns - THCLK+2 ns THCLK– 0.5 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 15818 Rev 9 127/177 Electrical characteristics STM32F20xxx Synchronous waveforms and timings Figure 58 through Figure 61 represent synchronous waveforms and Table 75 through Table 77 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ● CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual) ● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. Figure 58. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) BUSTURN = 0 FSMC_CLK FSMC_NEx td(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] Data latency = 0 td(CLKL-NExL) td(CLKL-NADVH) td(CLKL-AV) t d(CLKL-NExH) td(CLKL-AIV) td(CLKH-NOEL) td(CLKL-NOEH) FSMC_NOE td(CLKL-ADV) FSMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH) AD[15:0] tsu(NWAITV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) D1 D2 th(CLKH-ADV) th(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893h 128/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 74. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max tw(CLK) FSMC_CLK period 2THCLK - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.5 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3 td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 5 - th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Doc ID 15818 Rev 9 129/177 Electrical characteristics STM32F20xxx Figure 59. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) FSMC_CLK FSMC_NEx td(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] FSMC_NWE td(CLKL-ADV) FSMC_AD[15:0] Data latency = 0 td(CLKL-NExL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-NWEL) td(CLKL-ADIV) td(CLKL-Data) AD[15:0] td(CLKL-Data) D1 BUSTURN = 0 td(CLKL-NExH) td(CLKL-AIV) td(CLKL-NWEH) D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) FSMC_NBL th(CLKH-NWAITV) td(CLKL-NBLH) Table 75. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 2THCLK- 1 2 3 7 0 0 - 0.5 ai14992g Max Unit - ns 0 ns - ns 2 ns - ns 0 ns - ns 1 ns - ns - ns 2 ns - ns 130/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) BUSTURN = 0 FSMC_CLK td(CLKL-NExL) FSMC_NEx Data latency = 0 td(CLKL-NExH) td(CLKL-NADVL) FSMC_NADV td(CLKL-NADVH) FSMC_A[25:0] td(CLKL-AV) td(CLKL-AIV) FSMC_NOE FSMC_D[15:0] td(CLKH-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) tsu(NWAITV-CLKH) th(CLKH-DV) tsu(DV-CLKH) D1 D2 th(CLKH-DV) th(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894g Table 76. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 2THCLK - ns - 0 ns 1 - ns - 2.5 ns 4 - ns - 0 ns 3 - ns - 1 ns 1.5 - ns 8 - ns 3.5 - ns Doc ID 15818 Rev 9 131/177 Electrical characteristics STM32F20xxx Figure 61. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0 FSMC_CLK td(CLKL-NExL) FSMC_NEx Data latency = 0 td(CLKL-NExH) td(CLKL-NADVL) FSMC_NADV td(CLKL-NADVH) FSMC_A[25:0] td(CLKL-AV) td(CLKL-AIV) FSMC_NWE td(CLKL-NWEL) td(CLKL-NWEH) FSMC_D[15:0] td(CLKL-Data) td(CLKL-Data) D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) FSMC_NBL td(CLKL-NBLH) th(CLKH-NWAITV) Table 77. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL- NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 2THCLK- 1 1 - 6 8 1 2 ai14993g Max Unit - ns 1 ns - ns 5 ns - ns 0 ns - ns 1 ns - ns 2 ns - ns 132/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 62 through Figure 67 represent synchronous waveforms together with Table 78 and Table 79 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.FSMC_WaitSetupTime = 0x07; ● ATT.FSMC_HoldSetupTime = 0x04; ● ATT.FSMC_HiZSetupTime = 0x00; ● IO.FSMC_SetupTime = 0x04; ● IO.FSMC_WaitSetupTime = 0x07; ● IO.FSMC_HoldSetupTime = 0x04; ● IO.FSMC_HiZSetupTime = 0x00; ● TCLRSetupTime = 0; ● TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. Figure 62. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD tv(NCEx-A) td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-AI) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) FSMC_NWE td(NCE4_1-NOE) FSMC_NOE FSMC_D[15:0] tw(NOE) tsu(D-NOE) 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. th(NOE-D) ai14895b Doc ID 15818 Rev 9 133/177 Electrical characteristics STM32F20xxx Figure 63. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High FSMC_A[10:0] tv(NCE4_1-A) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) FSMC_NWE td(NREG-NCE4_1) td(NIORD-NCE4_1) tw(NWE) th(NCE4_1-AI) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NWE-NCE4_1) FSMC_NOE FSMC_D[15:0] MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) ai14896b 134/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NWE td(NCE4_1-NOE) FSMC_NOE FSMC_D[15:0](1) tw(NOE) tsu(D-NOE) 1. Only data bits 0...7 are read (bits 8...15 are disregarded). td(NOE-NCE4_1) th(NOE-D) ai14897b Doc ID 15818 Rev 9 135/177 Electrical characteristics STM32F20xxx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High FSMC_A[10:0] tv(NCE4_1-A) th(NCE4_1-AI) FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) tw(NWE) td(NWE-NCE4_1) tv(NWE-D) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE tv(NCEx-A) th(NCE4_1-AI) FSMC_NIOWR td(NIORD-NCE4_1) FSMC_NIORD FSMC_D[15:0] tsu(D-NIORD) tw(NIORD) td(NIORD-D) ai14899B 136/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] tv(NCEx-A) th(NCE4_1-AI) FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) FSMC_NIOWR ATTxHIZ =1 FSMC_D[15:0] tw(NIOWR) tv(NIOWR-D) th(NIOWR-D) ai14900c Table 78. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low tw(NOE) FSMC_NOE low width td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high th (N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low tv (NWE-D) FSMC_NWE low to FSMC_D[15:0] valid th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 4 THCLK+ 4 8THCLK– 0.5 5THCLK+ 2.5 4 2 8THCLK- 1 5THCLK+ 1.5 8 THCLK 13THCLK 0 3.5 5THCLK+ 1 5THCLK 8THCLK+ 1 8THCLK+ 4 5HCLK+ 1 0 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Doc ID 15818 Rev 9 137/177 Electrical characteristics STM32F20xxx Table 79. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter Min Max Unit tw(NIOWR) FSMC_NIOWR low width 8THCLK - 0.5 - ns tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid - 5THCLK- 1 ns th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 1 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 0.5 - ns tw(NIORD) FSMC_NIORD low width 8THCLK+ 1 - ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9.5 ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 68 through Figure 71 represent synchronous waveforms, together with Table 80 and Table 81 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x01; ● COM.FSMC_WaitSetupTime = 0x03; ● COM.FSMC_HoldSetupTime = 0x02; ● COM.FSMC_HiZSetupTime = 0x01; ● ATT.FSMC_SetupTime = 0x01; ● ATT.FSMC_WaitSetupTime = 0x03; ● ATT.FSMC_HoldSetupTime = 0x02; ● ATT.FSMC_HiZSetupTime = 0x01; ● Bank = FSMC_Bank_NAND; ● MemoryDataWidth = FSMC_MemoryDataWidth_16b; ● ECC = FSMC_ECC_Enable; ● ECCPageSize = FSMC_ECCPageSize_512Bytes; ● TCLRSetupTime = 0; ● TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. 138/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 68. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] td(ALE-NOE) th(NOE-ALE) tsu(D-NOE) th(NOE-D) Figure 69. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NWE) th(NWE-ALE) ai14901c FSMC_NOE (NRE) FSMC_D[15:0] tv(NWE-D) th(NWE-D) ai14902c Doc ID 15818 Rev 9 139/177 Electrical characteristics STM32F20xxx Figure 70. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] td(ALE-NOE) th(NOE-ALE) tw(NOE) tsu(D-NOE) th(NOE-D) ai14912c Figure 71. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) FSMC_NWE tw(NWE) th(NOE-ALE) FSMC_NOE FSMC_D[15:0] td(D-NWE) tv(NWE-D) th(NWE-D) ai14913c Table 80. Switching characteristics for NAND Flash read cycles(1)(2) Symbol Parameter Min Max tw(N0E) tsu(D-NOE) FSMC_NOE low width FSMC_D[15-0] valid data before FSMC_NOE high 4THCLK- 1 9 th(NOE-D) td(ALE-NOE) th(NOE-ALE) FSMC_D[15-0] valid data after FSMC_NOE high FSMC_ALE valid before FSMC_NOE low FSMC_NWE high to FSMC_ALE invalid 3 3THCLK+ 2 1. CL = 30 pF. 2. Based on characterization, not tested in production. 4THCLK+ 2 - 3THCLK - Unit ns ns ns ns ns 140/177 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5.3.26 Table 81. Switching characteristics for NAND Flash write cycles(1)(2) Symbol Parameter Min Max tw(NWE) FSMC_NWE low width tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 2. Based on characterization, not tested in production. 4THCLK- 1 - 3THCLK 5THCLK 3THCLK- 2 4THCLK+ 3 0 - 3THCLK+ 2 - Unit ns ns ns ns ns ns Camera interface (DCMI) timing specifications Table 82. DCMI characteristics Symbol Parameter Frequency ratio DCMI_PIXCLK/fHCLK Conditions Min Max DCMI_PIXCLK= 48 MHz 0.4 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 83 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 72. SDIO high-speed mode tf tr tW(CKH) CK D, CMD (output) D, CMD (input) tC tOV tW(CKL) tOH tISU tIH Doc ID 15818 Rev 9 ai14887 141/177 Electrical characteristics Figure 73. SD default mode STM32F20xxx CK D, CMD (output) tOVD tOHD 5.3.28 ai14888 Table 83. SD / MMC characteristics Symbol Parameter Conditions Min fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 - SDIO_CK/fPCLK2 frequency ratio - - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 tr Clock rise time CL ≤ 30 pF tf Clock fall time CL ≤ 30 pF CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF 2 tIH Input hold time CL ≤ 30 pF 0 CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF tOH Output hold time CL ≤ 30 pF 0.3 CMD, D outputs (referenced to CK) in SD default mode(1) tOVD Output valid default time CL ≤ 30 pF tOHD Output hold default time CL ≤ 30 pF 0.5 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. Max Unit 48 MHz 8/3 - ns 3.5 5 ns 6 ns 7 ns RTC characteristics Table 84. RTC characteristics Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - 142/177 Doc ID 15818 Rev 9 STM32F20xxx 6 Package characteristics Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 15818 Rev 9 143/177 Package characteristics STM32F20xxx Figure 74. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline A A2 A1 E E1 b e D1 c D L1 1. Drawing is not to scale. L ai14398b Table 85. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data Symbol millimeters Min Typ Max inches(1) Min Typ Max A 1.600 A1 0.050 0.150 0.0020 A2 1.350 1.400 1.450 0.0531 b 0.170 0.220 0.270 0.0067 c 0.090 0.200 0.0035 D 12.000 D1 10.000 E 12.000 E1 10.000 e 0.500 θ 0° 3.5° 7° 0° L 0.450 0.600 0.750 0.0177 L1 1.000 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 0.0551 0.0087 0.4724 0.3937 0.4724 0.3937 0.0197 3.5° 0.0236 0.0394 0.0630 0.0059 0.0571 0.0106 0.0079 7° 0.0295 144/177 Doc ID 15818 Rev 9 STM32F20xxx Figure 75. Recommended footprint 48 49 12.7 10.3 64 1 1. Drawing is not to scale. 2. Dimensions are in millimeters. Package characteristics 33 0.3 0.5 32 10.3 16 7.8 12.7 17 1.2 ai14909 Doc ID 15818 Rev 9 145/177 Package characteristics STM32F20xxx Figure 76. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline A1 ball location D e1 e Detail A E Wafer back side A2 A Side view Detail A rotated by 90 °C eee e e1 G F Bump side A1 b Seating plane A0FX_ME 1. Drawing is not to scale. Table 86. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data Symbol millimeters inches Min Typ Max Min Typ Max A 0.520 0.570 0.600 0.0205 0.0224 0.0236 A1 0.170 0.190 0.210 0.0067 0.0075 0.0083 A2 0.350 0.380 0.410 0.0138 0.0150 0.0161 b 0.245 0.270 0.295 0.0096 0.0106 0.0116 D 3.619 3.639 3.659 0.1425 0.1433 0.1441 E 3.951 3.971 3.991 0.1556 0.1563 0.1571 e 0.400 0.0157 e1 3.218 0.1267 F 0.220 0.0087 G 0.386 0.0152 eee 0.050 0.0020 146/177 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics Figure 77. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 0.25 mm 0.10 inch GAGE PLANE 75 76 D D1 D3 51 50 k L L1 C b E3 E1 E 100 Pin 1 1 identification 1. Drawing is not to scale. 26 25 e SEATING PLANE C ccc C A1 A2 A 1L_ME Table 87. Symbol LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 12.000 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15818 Rev 9 147/177 Package characteristics Figure 78. Recommended footprint 75 76 16.7 14.3 51 50 0.5 0.3 STM32F20xxx 100 1 1. Drawing is not to scale. 2. Dimensions are in millimeters. 26 1.2 25 12.3 16.7 ai14906 148/177 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics Figure 79. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline Seating plane C A A2 A1 b ccc C D D1 D3 108 109 c 73 72 0.25 mm gage plane k A1 L L1 E1 E E3 144 Pin 1 1 identification 37 36 e ME_1A 1. Drawing is not to scale. Table 88. Symbol LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 17.500 0.689 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 17.500 0.6890 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15818 Rev 9 149/177 Package characteristics Figure 80. Recommended footprint 108 109 0.35 0.5 73 1.35 72 STM32F20xxx 17.85 19.9 22.6 144 1 1. Drawing is not to scale. 2. Dimensions are in millimeters. 19.9 22.6 37 36 ai14905c 150/177 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics Figure 81. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline C Seating plane A A2 0.25 mm gauge plane A1 ccc C HD D ZD 132 133 b c A1 ZE 89 88 k L L1 E HE 1. Drawing is not to scale. 176 Pin 1 1 identification 45 44 e 1T_ME Table 89. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data Symbol millimeters Min Typ Max inches(1) Min Typ Max A 1.600 A1 0.050 0.150 0.0020 A2 1.350 1.450 0.0531 b 0.170 0.270 0.0067 c 0.090 0.200 0.0035 D 23.900 24.100 0.9409 E 23.900 24.100 0.9409 e 0.500 HD 25.900 26.100 1.0197 HE 25.900 L(2) 0.450 26.100 0.750 1.0197 0.0177 L1 1.000 ZD 1.250 ZE 1.250 k 0° 7° 0° ccc 0.080 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. 0.0197 0.0394 0.0492 0.0492 0.0630 0.0059 0.0571 0.0106 0.0079 0.9488 0.9488 1.0276 1.0276 0.0295 7° 0.0031 Doc ID 15818 Rev 9 151/177 Package characteristics Figure 82. LQFP176 recommended footprint 176 1 STM32F20xxx 1.2 0.5 133 132 0.3 26.7 21.8 44 45 1. Dimensions are expressed in millimeters. 21.8 26.7 89 88 1.2 1T_FP_V1 152/177 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline C Seating plane A2 A4 A3 e A ddd C A1 A F Ball A1 D Ball A1 F E e R 15 1 BOTTOM VIEW 1. Drawing is not to scale. TOP VIEW A0E7_ME_V2 Table 90. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Symbol millimeters Min Typ Max inches(1) Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.130 0.0051 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3740 0.3937 0.3957 E 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15818 Rev 9 153/177 Package characteristics STM32F20xxx 6.2 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: ● TA max is the maximum ambient temperature in °C, ● ΘJA is the package junction-to-ambient thermal resistance, in °C/W, ● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), ● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 91. Package thermal characteristics Symbol Parameter Thermal resistance junction-ambient LQFP 64 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient WLCSP64+2 - 0.400 mm pitch Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch ΘJA Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.5 mm pitch Value 45 51 46 40 38 39 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 154/177 Doc ID 15818 Rev 9 STM32F20xxx Part numbering 7 Part numbering Table 92. Ordering information scheme Example: STM32 F 205 R E T 6 V xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity, 207= STM32F20x, connectivity, camera interface, Ethernet Pin count R = 64 pins or 66 pins(1) V = 100 pins Z = 144 pins I = 176 pins Flash memory size B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory E = 512 Kbytes of Flash memory F = 768 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Software option Internal code or Blank Options xxx = programmed parts TR = tape and reel 1. The 66 pins is available on WLCSP package only. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 15818 Rev 9 155/177 Application block diagrams Appendix A Application block diagrams STM32F20xxx A.1 Main applications versus package Table 93 gives examples of configurations for each package. Table 93. Main applications versus package for STM32F2xxx microcontrollers 64 pins(1) 100 pins 144 pins 176 pins USB OTG FS OTG FS FS USB OTG HS HS ULPI OTG FS FS Ethernet MII (2) RMII SPI/I2S2 SPI/I2S3 Config Config Config Config Config Config Config Config Config Config Config Config Config 1 2 3 1 2 3 4 1 2 3 4 1 2 - - - X X X - X - X - X - - - - X X X X X X X X X - X - X X - - - X X - - X X X X X X - - - X X - - X X X X X X X X X X X X X X X - - - - - X X - - X X X X - - - - X X X X X X X X X - X - - X X X X X X X X X SDIO SDIO X X - X X X X X 8-bit Data - 10-bit Data - - - SDIO or DCMI SDIO or DCMI SDIO or DCMI X X SDIO or DCMI X X SDIO or DCMI X X X X X X DCMI(2) 12-bit Data - - - X X X X X 14-bit Data - - - - - - - - X - X X X NOR/ RAM - - - X X X X X X X X X X Muxed FSMC NOR/ RAM - - - X X X X X X NAND - - - X X X X X X X X X X CF - - - - - - - X X X X X X CAN - X X - X X X - - X X - X 1. Not available on STM32F2x7xx. 2. Not available on STM32F2x5xx. 156/177 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams A.2 Application example with regulator OFF Figure 84. Regulator OFF/internal reset ON Power-down reset risen after VCAP_1/VCAP_2 stabilization Application reset signal (optional) Power-down reset risen before VCAP_1/VCAP_2 stabilization VCAP_1/2 monitoring Application reset Ext. reset controller active signal (optional) when VCAP_1/2 < 1.08 V VDD (1.8 to 3.6 V) PA0 VDD NRST VDD (1.8 to 3.6 V) PA0 VDD NRST 1.2 V REGOFF VCAP_1 VCAP_2 1.2 V REGOFF VCAP_1 IRROFF VCAP_2 ai18476 1. This mode is available only on UFBGA176 and WLCSP64+2 packages. 2. In regulator bypass mode, PA0 is used as power-on reset. The connection between PA0 and NRST can consequently prevent debug connection. If the debug connection under reset or pre-reset is required, the user must manage the reset and the power-on reset separately. Figure 85. Regulator OFF/ internal reset OFF VDD 1.2 V 1.2 V VDD/VCAP_1/2 monitoring Ext. reset controller active when VDD < 1.65 V and VCAP_1/2 < 1.08 V NRST REGOFF IRROFF VDD VCAP_1 VCAP_2 1. This mode is available only on WLCSP64+2 package. VDD (1.65 to 3.6 V) VDD ai18477 Doc ID 15818 Rev 9 157/177 Application block diagrams A.3 USB OTG full speed (FS) interface solutions Figure 86. USB OTG FS (full speed) device-only connection VDD 5V to VDD Volatge regulator (1) STM32F20xxx USB Std-B connector STM32F20xxx OSC_IN OSC_OUT PA9 PA11 PA12 VBUS DM DP VSS ai17295 1. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 87. USB OTG FS (full speed) host-only connection GPIO GPIO+IRQ STM32F20xx OSC_IN OSC_OUT PA9 PA11 PA12 VDD EN Overcurrent Current limiter power switch(1) 5 V Pwr VBUS DM DP VSS USB Std-A connector ai17296c 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. 158/177 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams Figure 88. OTG FS (full speed) connection dual-role with internal PHY VDD 5 V to VDD voltage regulator (1) GPIO GPIO+IRQ EN Overcurrent VDD Current limiter 5 V Pwr power switch(2) USBmicro-AB connector STM32F20xxx OSC_IN OSC_OUT PA9 PA11 PA12 PA10 VBUS DM DP ID(3) VSS ai17294c 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Doc ID 15818 Rev 9 159/177 Application block diagrams STM32F20xxx A.4 USB OTG high speed (HS) interface solutions Figure 89. OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY STM32F20xxx USB HS OTG Ctrl FS PHY DP not connected DM ULPI ULPI_CLK ULPI_D[7:0] ULPI_DIR ULPI_STP ULPI_NXT XT1 PLL 24 or 26 MHz XT(1) High speed OTG PHY MCO1 or MCO2 XI DP DM ID(2) VBUS VSS USB connector ai16036c 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F20x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. 160/177 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 90 and Figure 91. Figure 90 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 90. Complete audio player solution 1 XTAL 25 MHz or 14.7456 MHz USB Mass-storage device MMC/ SDCard Cortex-M3 core up to 120 MHz Program memory OTG (host mode) + PHY SPI/ FSMC File System Audio CODEC User application SPI GPIO I2S LCD touch screen Control buttons DAC + Audio ampli Figure 91 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. ai16039c Figure 91. Complete audio player solution 2 XTAL 25 MHz or 14.7456 MHz USB Mass-storage device SOF MMC/ SDCard Cortex-M3 core up to 120 MHz SPI/ FSMC OTG + PHY Program memory File System GPIO I2S SPI/ FSMC User application SOF synchronization of input/output audio streaming 1. SOF = start of frame. LCD touch screen Control buttons Audio PLL +DAC Audio ampli ai16040c Doc ID 15818 Rev 9 161/177 Application block diagrams Figure 92. Audio player solution using PLL, PLLI2S, USB and 1 crystal XTAL 25 MHz or 14.7456 MHz OSC Div by M PLL x N1 up to Div 120 MHz by P Div by Q PLLI2S Div x N2 by R Cortex-M3 core up to 120 MHz OTG 48 MHz PHY STM32F20xxx MCO1/ MCO2 MCLK in MCO1PRE MCO2PRE I2S <0.04% accuracy) MCLK out SCLK DAC + Audio ampli ai18412b Figure 93. Audio PLL (PLLI2S) providing accurate I2S clock CLKIN PLLI2S Phase lock detector /M M=1,2,3,..,64 1 MHz PhaseC 192 to 432 MHz VCO /N I2S_MCK = 256 × FSAUDIO 11.2896 MHz for 44.1 kHz 12.2880 MHz for 48.0 kHz N=192,194,..,432 I2SCOM_CK /R R=2,3,4,5,6,7 I2S CTL I2S_MCK I2SD=2,3,4.. 129 ai16041b 162/177 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams Figure 94. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD I2S controller 2,3,4,..,129 /8 /(2 x 16) for 16-bit stereo FSAUDIO I2S_MCK = 256 × FSAUDIO = 11.2896 MHz for FSAUDIO = 44.1 kHz = 12.2880 MHz for FSAUDIO = 48.0 kHz I2S_SCK(1) = I2S_MCK/8 for 16-bit stereo = I2S_MCK/4 for 32-bit stereo /4 /(2 x 32) for 32-bit stereo FSAUDIO 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 95. Master clock (MCK) not used to drive the external audio DAC ai16042 I2S controller I2SCOM_CK /I2SD /(2 x 16) for 16-bit stereo /(2 x 32) for 32-bit stereo FSAUDIO FSAUDIO I2S_SCK(1) ai16042 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Doc ID 15818 Rev 9 163/177 Application block diagrams STM32F20xxx A.6 Ethernet interface solutions Figure 96. MII mode using a 25 MHz crystal XTAL 25 MHz MCU STM32 Ethernet MAC 10/100 HCLK(1) IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MDIO MDC PPS_OUT(2) Ethernet PHY 10/100 MII = 15 pins MII + MDC = 17 pins OSC PLL HCLK MCO1/MCO2 PHY_CLK 25 MHz XT1 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 97. RMII with a 50 MHz oscillator STM32 MCU HCLK(1) Ethernet MAC 10/100 IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC MS19968V1 Ethernet PHY 10/100 RMII = 7 pins RMII + MDC = 9 pins XTAL /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC PLL HCLK OSC 50 MHz 1. fHCLK must be greater than 25 MHz. 50MHz XT1 50 MHz MS19971V1 164/177 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams Figure 98. RMII with a 25 MHz crystal and PHY with PLL MCU HCLK(1) STM32F Ethernet MAC 10/100 IEEE1588 PTP Timer input TIM2 trigger Timestamp comparator RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK MDIO MDC Ethernet PHY 10/100 RMII = 7 pins REF_CLK RMII + MDC = 9 pins XTAL 25 MHz /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC PLL HCLK PLL MCO1/MC02 PHY_CLK 25 MHz XT1 MS19970V1 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. Doc ID 15818 Rev 9 165/177 Revision history 8 Revision history STM32F20xxx Table 94. Document revision history Date Revision Changes 05-Jun-2009 1 Initial release. 09-Oct-2009 Document status promoted from Target specification to Preliminary data. In Table 6: STM32F20x pin and ball definitions: – Note 4 updated 2 – VDD_SA and VDD_3 pins inverted (Figure 10: STM32F20x LQFP100 pinout, Figure 11: STM32F20x LQFP144 pinout and Figure 12: STM32F20x LQFP176 pinout corrected accordingly). Section 6.1: Package mechanical data changed to LQFP with no exposed pad. 01-Feb-2010 LFBGA144 package removed. STM32F203xx part numbers removed. Part numbers with 128 and 256 Kbyte Flash densities added. 3 Encryption features removed. PC13-TAMPER-RTC renamed to PC13-RTC_AF1 and PI8-TAMPERRTC renamed to PI8-RTC_AF2. 13-Jul-2010 Renamed high-speed SRAM, system SRAM. Removed combination: 128 KBytes Flash memory in LQFP144. Added UFBGA176 package. Added note 1 related to LQFP176 package in Table 2, Figure 12, and Table 92. Added information on ART accelerator and audio PLL (PLLI2S). Added Table 5: USART feature comparison. Several updates on Table 6: STM32F20x pin and ball definitions and Table 8: Alternate function mapping. ADC, DAC, oscillator, RTC_AF, WKUP and VBUS signals removed from alternate functions and moved to the “other functions” column in Table 6: STM32F20x pin and ball definitions. TRACESWO added in Figure 4: STM32F20x block diagram, Table 6: STM32F20x pin and ball definitions, and Table 8: Alternate function 4 mapping. XTAL oscillator frequency updated on cover page, in Figure 4: STM32F20x block diagram and in Section 2.2.11: External interrupt/event controller (EXTI). Updated list of peripherals used for boot mode in Section 2.2.13: Boot modes. Added Regulator bypass mode in Section 2.2.16: Voltage regulator, and Section 5.3.4: Operating conditions at power-up / power-down (regulator OFF). Updated Section 2.2.17: Real-time clock (RTC), backup SRAM and backup registers. Added Note Note: in Section 2.2.18: Low-power modes. Added SPI TI protocol in Section 2.2.23: Serial peripheral interface (SPI). 166/177 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94. Document revision history (continued) Date Revision Changes 13-Jul-2010 Added USB OTG_FS features in Section 2.2.28: Universal serial bus on-the-go full-speed (OTG_FS). Updated VCAP_1 and VCAP_2 capacitor value to 2.2 µF in Figure 17: Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for 1.8 to 2.1 V range in Table 13: Limitations depending on the operating power supply range. Added VBORL, VBORM, VBORH and IRUSH in Table 17: Embedded reset and power control block characteristics. Removed table Typical current consumption in Sleep mode with Flash memory in Deep power down mode. Merged typical and maximum current consumption sections and added Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table 19: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, Table 20: Typical and maximum current consumption in Sleep mode, Table 21: Typical and maximum current consumptions in Stop mode, Table 22: Typical and maximum current consumptions in Standby mode, and Table 23: Typical and maximum current consumptions in VBAT mode. Update Table 32: Main PLL characteristics and added Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Added Note 8 for CIO in Table 44: I/O static characteristics. 4 Updated Section 5.3.18: TIM timer characteristics. (continued) Added TNRST_OUT in Table 47: NRST pin characteristics. Updated Table 50: I2C characteristics. Removed 8-bit data in and data out waveforms from Figure 45: ULPI timing diagram. Removed note related to ADC calibration in Table 65. Section 5.3.20: 12-bit ADC characteristics: ADC characteristics tables merged into one single table; tables ADC conversion time and ADC accuracy removed. Updated Table 66: DAC characteristics. Updated Section 5.3.22: Temperature sensor characteristics and Section 5.3.23: VBAT monitoring characteristics. Update Section 5.3.26: Camera interface (DCMI) timing specifications. Added Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics, and Section 5.3.28: RTC characteristics. Added Section 6.2: Thermal characteristics. Updated Table 89: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data and Figure 81: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline. Changed tape and reel code to TX in Table 92: Ordering information scheme. Added Table 93: Main applications versus package for STM32F2xxx microcontrollers. Updated figures in Appendix A.3: USB OTG full speed (FS) interface solutions and A.4: USB OTG high speed (HS) interface solutions. Updated Figure 92: Audio player solution using PLL, PLLI2S, USB and 1 crystal and Figure 93: Audio PLL (PLLI2S) providing accurate I2S clock. Doc ID 15818 Rev 9 167/177 Revision history STM32F20xxx Table 94. Document revision history (continued) Date Revision Changes 25-Nov-2010 Update I/Os in Section : Features. Added WLCSP66(64+2) package. Added note 1 related to LQFP176 on cover page. Added trademark for ART accelerator. Updated Section 2.2.2: Adaptive real-time memory accelerator (ART Accelerator™). Updated Figure 5: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 2.2.15: Power supply supervisor. Reworked Section 2.2.16: Voltage regulator to clarify regulator off modes. Renamed PDROFF, IRROFF in the whole document. Added Section 2.2.19: VBAT operation. Updated LIN and IrDA features for UART4/5 in Table 5: USART feature comparison. Table 6: STM32F20x pin and ball definitions: Modified VDD_3 pin, and added note related to the FSMC_NL pin; renamed BYPASS-REG REGOFF, and add IRROFF pin; renamed USART4/5 UART4/5. USART4 pins renamed UART4. Changed VSS_SA to VSS, and VDD_SA pin reserved for future use. Updated maximum HSE crystal frequency to 26 MHz. Section 5.2: Absolute maximum ratings: Updated VIN minimum and maximum values and note related to five-volt tolerant inputs in Table 9: Voltage characteristics. Updated IINJ(PIN) maximum values and related notes in Table 10: Current characteristics. 5 Updated VDDA minimum value in Table 12: General operating conditions. Added Note 2 and updated Maximum CPU frequency in Table 13: Limitations depending on the operating power supply range, and added Figure 19: Number of wait states versus fCPU and VDD range. Added brownout level 1, 2, and 3 thresholds in Table 17: Embedded reset and power control block characteristics. Changed fOSC_IN maximum value in Table 28: HSE 4-26 MHz oscillator characteristics. Changed fPLL_IN maximum value in Table 32: Main PLL characteristics, and updated jitter parameters in Table 33: PLLI2S (audio PLL) characteristics. Section 5.3.16: I/O port characteristics: updated VIH and VIL in Table 44: I/O static characteristics. Added Note 1 below Table 45: Output voltage characteristics. Updated RPD and RPU parameter description in Table 55: USB OTG FS DC electrical characteristics. Updated VREF+ minimum value in Table 64: ADC characteristics. Updated Table 69: Embedded internal reference voltage. Removed Ethernet and USB2 for 64-pin devices in Table 93: Main applications versus package for STM32F2xxx microcontrollers. Added A.2: Application example with regulator OFF, removed “OTG FS connection with external PHY” figure, updated Figure 87, Figure 88, and Figure 90 to add STULPI01B. 168/177 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94. Document revision history (continued) Date Revision Changes 22-Apr-2011 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability of WLCSP64+2 package limited to 512 Kbyte and 1 Mbyte devices. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package and Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. Added camera interface for STM32F207Vx devices in Table 2: STM32F205xx features and peripheral counts. Removed 16 MHz internal RC oscillator accuracy in Section 2.2.12: Clocks and startup. Updated Section 2.2.16: Voltage regulator. Modified I2S sampling frequency range in Section 2.2.12: Clocks and startup, Section 2.2.24: Inter-integrated sound (I2S), and Section 2.2.30: Audio PLL (PLLI2S). Updated Section 2.2.17: Real-time clock (RTC), backup SRAM and backup registers and description of TIM2 and TIM5 in Section : General-purpose timers (TIMx). Modified maximum baud rate (oversampling by 16) for USART1 in Table 5: USART feature comparison. Updated note related to RFU pin below Figure 10: STM32F20x LQFP100 pinout, Figure 11: STM32F20x LQFP144 pinout, Figure 12: STM32F20x LQFP176 pinout, Figure 13: STM32F20x UFBGA176 6 ballout, and Table 6: STM32F20x pin and ball definitions. In Table 6: STM32F20x pin and ball definitions,:changed I2S2_CK and I2S3_CK to I2S2_SCK and I2S3_SCK, respectively; added PA15 and TT (3.6 V tolerant I/O). Added RTC_50Hz as PB15 alternate function in Table 6: STM32F20x pin and ball definitions and Table 8: Alternate function mapping. Removed ETH _RMII_TX_CLK for PC3/AF11 in Table 8: Alternate function mapping. Updated Table 9: Voltage characteristics and Table 10: Current characteristics. TSTG updated to –65 to +150 in Table 11: Thermal characteristics. Added CEXT, ESL, and ESR in Table 12: General operating conditions as well as Section 5.3.2: VCAP1/VCAP2 external capacitor. Modified Note 4 in Table 13: Limitations depending on the operating power supply range. Updated Table 15: Operating conditions at power-up / power-down (regulator ON), and Table 16: Operating conditions at power-up / power-down (regulator OFF). Added OSC_OUT pin in Figure 15: Pin loading conditions. and Figure 16: Pin input voltage. Updated Figure 17: Power supply scheme to add IRROFF and REGOFF pins and modified notes. Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and IRUSH, added ERUSH and Note 3 in Table 17: Embedded reset and power control block characteristics. Doc ID 15818 Rev 9 169/177 Revision history STM32F20xxx Table 94. Document revision history (continued) Date Revision Changes 22-Apr-2011 Updated Typical and maximum current consumption conditions, as well as Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 19: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure 21, Figure 22, Figure 23, and Figure 24. Updated Table 20: Typical and maximum current consumption in Sleep mode, and added Figure 25 and Figure 26. Updated Table 21: Typical and maximum current consumptions in Stop mode. Added Figure 27: Typical current consumption vs temperature in Stop mode. Updated Table 22: Typical and maximum current consumptions in Standby mode and Table 23: Typical and maximum current consumptions in VBAT mode. Updated On-chip peripheral current consumption conditions and Table 24: Peripheral current consumption. Updated tWUSTDBY and tWUSTOP, and added Note 3 in Table 25: Lowpower mode wakeup timings. Maximum fHSE_ext and minimum tw(HSE) values updated in Table 26: High-speed external user clock characteristics. Updated C and gm in Table 28: HSE 4-26 MHz oscillator characteristics. Updated RF, I2, gm, and tsu(LSE) in Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz). 6 Added Note 1 and updated ACCHSI, IDD(HSI, and tsu(HSI) in Table 30: (continued) HSI oscillator characteristics. Added Figure 32: ACCHSI versus temperature. Updated fLSI, tsu(LSI) and IDD(LSI) in Table 31: LSI oscillator characteristics. Added Figure 33: ACCLSI versus temperature Table 32: Main PLL characteristics: removed note 1, updated tLOCK, jitter, IDD(PLL) and IDDA(PLL), added Note 2 for fPLL_IN minimum and maximum values. Table 33: PLLI2S (audio PLL) characteristics: removed note 1, updated tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S), added Note 2 for fPLLI2S_IN minimum and maximum values. Added Note 1 in Table 34: SSCG parameters constraint. Updated Table 35: Flash memory characteristics. Modified Table 36: Flash memory programming and added Note 2 for tprog. Updated tprog and added Note 1 in Table 37: Flash memory programming with VPP. Modified Figure 37: Recommended NRST pin protection. Updated Table 40: EMI characteristics and EMI monitoring conditions in Section : Electromagnetic Interference (EMI). Added Note 2 related to VESD(HBM)in Table 41: ESD absolute maximum ratings. Updated Table 44: I/O static characteristics. Added Section 5.3.15: I/O current injection characteristics. Modified maximum frequency values and conditions in Table 46: I/O AC characteristics. Updated tres(TIM) in Table 48: Characteristics of TIMx connected to the APB1 domain. Modified tres(TIM) and fEXT Table 49: Characteristics of TIMx connected to the APB2 domain. 170/177 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94. Document revision history (continued) Date Revision Changes 22-Apr-2011 Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 50: I2C characteristics and in Figure 38: I2C bus AC waveforms and measurement circuit. Added Table 55: USB OTG FS DC electrical characteristics and updated Table 56: USB OTG FS electrical characteristics. Updated VDD minimum value in Table 60: Ethernet DC electrical characteristics. Updated Table 64: ADC characteristics and RAIN equation. Updated RAIN equation. Updated Table 66: DAC characteristics. Updated tSTART in Table 67: TS characteristics. Updated R typical value in Table 68: VBAT monitoring characteristics. Updated Table 69: Embedded internal reference voltage. Modified FSMC_NOE waveform in Figure 54: Asynchronous non- multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL- AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL- 6 NWEH), and updated data latency from 1 to 0 in Figure 58: Synchronous multiplexed NOR/PSRAM read timings, Figure 59: (continued) Synchronous multiplexed PSRAM write timings, Figure 60: Synchronous non-multiplexed NOR/PSRAM read timings, and Figure 61: Synchronous non-multiplexed PSRAM write timings, Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV), td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and modified tw(CLK) minimum value in Table 74, Table 75, Table 76, and Table 77. Updated note 2 in Table 70, Table 71, Table 72, Table 73, Table 74, Table 75, Table 76, and Table 77. Modified th(NIOWR-D) in Figure 67: PC Card/CompactFlash controller waveforms for I/O space write access. Modified FSMC_NCEx signal in Figure 68: NAND controller waveforms for read access, Figure 69: NAND controller waveforms for write access, Figure 70: NAND controller waveforms for common memory read access, and Figure 71: NAND controller waveforms for common memory write access Specified Full speed (FS) mode for Figure 89: USB OTG HS peripheral-only connection in FS mode and Figure 90: USB OTG HS host-only connection in FS mode. Doc ID 15818 Rev 9 171/177 Revision history STM32F20xxx Table 94. Document revision history (continued) Date Revision Changes 14-Jun-2011 20-Dec-2011 Added SDIO in Table 2: STM32F205xx features and peripheral counts. Updated VIN for 5V tolerant pins in Table 9: Voltage characteristics. Updated jitter parameters description in Table 32: Main PLL characteristics. Remove jitter values for system clock in Table 33: PLLI2S (audio PLL) characteristics. Updated Table 40: EMI characteristics. Update Note 2 in Table 50: I2C characteristics. Updated Avg_Slope typical value and TS_temp minimum value in 7 Table 67: TS characteristics. Updated TS_vbat minimum value in Table 68: VBAT monitoring characteristics. Updated TS_vrefint mimimum value in Table 69: Embedded internal reference voltage. Added Software option in Section 7: Part numbering. In Table 93: Main applications versus package for STM32F2xxx microcontrollers, renamed USB1 and USB2, USB OTG FS and USB OTG HS, respectively; and removed USB OTG FS and camera interface for 64-pin package; added USB OTG HS on 64-pin package; added Note 1 and Note 2. Updated SDIO register addresses in Figure 14: Memory map. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package, Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package, Figure 1: Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package, and added Figure 4: Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Section 2.2.3: Memory protection unit. Updated Section 2.2.6: Embedded SRAM. Updated Section 2.2.28: Universal serial bus on-the-go full-speed (OTG_FS) to remove external FS OTG PHY support. 8 In Table 6: STM32F20x pin and ball definitions: changed SPI2_MCK and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added ETH _RMII_TX_EN atlternate function to PG11. Added EVENTOUT in the list of alternate functions for I/O pin/balls. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. In Table 8: Alternate function mapping: changed I2S3_SCK to I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. Changed I2S3_SCK into I2S3_MCK for PC7/AF6. Updated peripherals corresponding to AF12. Removed CEXT and ESR from Table 12: General operating conditions. 172/177 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94. Document revision history (continued) Date Revision Changes 20-Dec-2011 Added maximum power consumption at TA=25 °C in Table 21: Typical and maximum current consumptions in Stop mode. Updated md minimum value in Table 34: SSCG parameters constraint. Added examples in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 52: SPI characteristics and Table 53: I2S characteristics. Updated Figure 45: ULPI timing diagram and Table 59: ULPI timing. Updated Table 61: Dynamics characteristics: Ethernet MAC signals for SMI, Table 62: Dynamics characteristics: Ethernet MAC signals for RMII, and Table 63: Dynamics characteristics: Ethernet MAC signals for MII. Section 5.3.25: FSMC characteristics: updated Table 70 toTable 81, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 59: Synchronous multiplexed PSRAM write timings. 8 (continued) UpdatedTable 82: DCMI characteristics. Updated Table 90: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. Updated Table 92: Ordering information scheme. Appendix A.3: USB OTG full speed (FS) interface solutions: updated Figure 87: USB OTG FS (full speed) host-only connection and added Note 2 , updated Figure 88: OTG FS (full speed) connection dual-role with internal PHY and added Note 3 and Note 4, modified Figure 89: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY and added Note 2. Appendix A.4: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode,updated Figure 89: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY. Added Appendix A.6: Ethernet interface solutions. Updated disclaimer on last page. 24-Apr-2012 Updated VDD minimum value in Section 2: Description. Updated number of USB OTG HS and FS, modified packages for STM32F207Ix part numbers, added Note 1 related to FSMC and Note 2 related to SPI/I2S, and updated Note 3 in Table 2: STM32F205xx features and peripheral counts and Table 3: STM32F207xx features and peripheral counts. Added Note 2 and update TIM5 in Figure 4: STM32F20x block 9 diagram. Updated maximum number of maskable interrupts in Section 2.2.10: Nested vectored interrupt controller (NVIC). Updated VDD minimum value in Section 2.2.14: Power supply schemes. Updated Note a in Section : Regulator ON. Removed STM32F205xx in Section 2.2.28: Universal serial bus onthe-go full-speed (OTG_FS). Doc ID 15818 Rev 9 173/177 Revision history STM32F20xxx Table 94. Document revision history (continued) Date Revision Changes 24-Apr-2012 Removed support of I2C for OTG PHY in Section 2.2.29: Universal serial bus on-the-go high-speed (OTG_HS). Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 6: STM32F20x pin and ball definitions and Table 8: Alternate function mapping. Renamed PH10 alternate function into TIM5_CH1 in Table 8: Alternate function mapping. Added Table 7: FSMC pin definition. Updated Note 1 in Table 12: General operating conditions, Note 2 in Table 13: Limitations depending on the operating power supply range, and Note 1 below Figure 19: Number of wait states versus fCPU and VDD range. Updated VPOR/PDR in Table 17: Embedded reset and power control block characteristics. Updated typical values in Table 22: Typical and maximum current consumptions in Standby mode and Table 23: Typical and maximum current consumptions in VBAT mode. Updated Table 28: HSE 4-26 MHz oscillator characteristics and Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz). 9 Updated Table 35: Flash memory characteristics, Table 36: Flash (continued) memory programming, and Table 37: Flash memory programming with VPP. Updated Section : Output driving current. Updated Note 3 and removed note related to minimum hold time value in Table 50: I2C characteristics. Updated Table 62: Dynamics characteristics: Ethernet MAC signals for RMII. Updated Note 1, CADC, IVREF+, and IVDDA in Table 64: ADC characteristics. Updated Note 3 and note concerning ADC accuracy vs. negative injection current in Table 65: ADC accuracy. Updated Note 1 in Table 66: DAC characteristics. Updated Section Figure 83.: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. Appendix A.1: Main applications versus package: removed number of address lines for FSMC/NAND in Table 93: Main applications versus package for STM32F2xxx microcontrollers. Appendix A.5: Complete audio player solutions: updated Figure 90: Complete audio player solution 1 and Figure 91: Complete audio player solution 2. 174/177 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94. Document revision history (continued) Date Revision Changes 29-Oct-2012 Changed minimum supply voltage from 1.65 to 1.8 V. Updated number of AHB buses in Section 2: Description and Section 2.2.12: Clocks and startup. Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Note 2 below Figure 4: STM32F20x block diagram. Changed System memory to System memory + OTP in Figure 14: Memory map. Added Note 1 below Table 14: VCAP1/VCAP2 operating conditions. Updated VDDA and VREF+ decouping capacitor in Figure 17: Power supply scheme and updated Note 3. Changed simplex mode into half-duplex mode in Section 2.2.24: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and PA5 in Table 8: Alternate function mapping. Updated note applying to IDD (external clock and all peripheral disabled) in Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled). Updated Note 3 below Table 20: Typical and maximum current consumption in Sleep mode. 10 Removed fHSE_ext typical value in Table 26: High-speed external user clock characteristics. Updated master I2S clock jitter conditions and vlaues in Table 33: PLLI2S (audio PLL) characteristics. Updated equations in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Swapped TTL and CMOS port conditions for VOL and VOH in Table 45: Output voltage characteristics. Updated VIL(NRST) and VIH(NRST) in Table 47: NRST pin characteristics. Updated Table 52: SPI characteristics and Table 53: I2S characteristics. Removed note 1 related to measurement points below Figure 40: SPI timing diagram - slave mode and CPHA = 1, Figure 41: SPI timing diagram - master mode, and Figure 42: I2S slave timing diagram (Philips protocol)(1). Updated tHC in Table 59: ULPI timing. Updated Figure 46: Ethernet SMI timing diagram, Table 61: Dynamics characteristics: Ethernet MAC signals for SMI and Table 63: Dynamics characteristics: Ethernet MAC signals for MII. Update fTRIG in Table 64: ADC characteristics. Updated IDDA description in Table 66: DAC characteristics. Updated note below Figure 51: Power supply and reference decoupling (VREF+ not connected to VDDA) and Figure 52: Power supply and reference decoupling (VREF+ connected to VDDA). Doc ID 15818 Rev 9 175/177 Revision history STM32F20xxx Table 94. Document revision history (continued) Date Revision Changes 29-Oct-2012 Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 74: Synchronous multiplexed NOR/PSRAM read timings, Table 76: Synchronous non- multiplexed NOR/PSRAM read timings, Figure 58: Synchronous multiplexed NOR/PSRAM read timings and Figure 60: Synchronous 10 non-multiplexed NOR/PSRAM read timings. (continued) Added Figure 82: LQFP176 recommended footprint. Added Note 2 below Figure 84: Regulator OFF/internal reset ON. Updated device subfamily in Table 92: Ordering information scheme. Remove reference to note 2 for USB IOTG FS in Table 93: Main applications versus package for STM32F2xxx microcontrollers. 176/177 Doc ID 15818 Rev 9 STM32F20xxx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15818 Rev 9 177/177

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