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pcie_3.0_总线规范

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  • 日期: 2018-01-15
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标签: pcie3.0

详细介绍pcie3.0的协议(中文)

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PCI Express Base Specification Revision 30 November 10 2010 Revision 10 10a 11 20 21 DATE 07222002 04152003 03282005 12202006 03042009 Revision History Initial release Incorporated Errata C1C66 and E1E417 Incorporated approved Errata and ECNs Added 50 GTs data rate and incorporated approved Errata and ECNs Incorporated Errata for the PCI Express Base Specification Rev 20 February 27 2009 and added the following ECNs Internal Error Reportin......

PCI Express® Base Specification Revision 3.0 November 10, 2010 Revision 1.0 1.0a 1.1 2.0 2.1 DATE 07/22/2002 04/15/2003 03/28/2005 12/20/2006 03/04/2009 • • • • Revision History Initial release. Incorporated Errata C1-C66 and E1-E4.17. Incorporated approved Errata and ECNs. Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. Incorporated Errata for the PCI Express Base Specification, Rev. 2.0 (February 27, 2009), and added the following ECNs: Internal Error Reporting ECN (April 24, 2008) Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) Dynamic Power Allocation ECN (May 24, 2008) ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) Extended Tag Enable Default ECN (September 5, 2008) TLP Processing Hints ECN (September 11, 2008) TLP Prefix ECN (December 15, 2008) • • • • • • • 3.0 Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: 11/10/2010 • • • Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010) PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: Phone: Fax: Technical Support techsupp@pcisig.com administration@pcisig.com 503-619-0569 503-644-6708 DISCLAIMER This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright © 2002-2010 PCI-SIG 2 PCI EXPRESS BASE SPECIFICATION, REV. 3.0 Contents OBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. 1.4. 1.5. 1.5.1. 1.5.2. 1.5.3. 1.5.4. 1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.3.5. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 PCI EXPRESS LINK......................................................................................................... 39 1.2. 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 Root Complex........................................................................................................ 41 Endpoints .............................................................................................................. 42 Switch.................................................................................................................... 45 Root Complex Event Collector.............................................................................. 46 PCI Express to PCI/PCI-X Bridge........................................................................ 46 PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 46 PCI EXPRESS LAYERING OVERVIEW.............................................................................. 47 Transaction Layer................................................................................................. 48 Data Link Layer .................................................................................................... 48 Physical Layer ...................................................................................................... 49 Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 TRANSACTION LAYER OVERVIEW.................................................................................. 53 Address Spaces, Transaction Types, and Usage................................................... 54 Packet Format Overview ...................................................................................... 56 TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 58 Common Packet Header Fields ............................................................................ 58 2.2.1. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.2. TLP Digest Rules .................................................................................................. 65 2.2.3. Routing and Addressing Rules.............................................................................. 65 2.2.4. First/Last DW Byte Enables Rules........................................................................ 69 2.2.5. 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules......................................................................................... 83 2.2.9. Completion Rules.................................................................................................. 97 2.2.10. TLP Prefix Rules................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 104 2.1. 2.2. 2.1.1. 2.1.2. 3 PCI EXPRESS BASE SPECIFICATION, REV. 3.0 2.4. 2.9.1. 2.9.2. 3.3. 3.2.1. 3.3.1. 3.4.1. 2.3.1. 2.3.2. 2.6.1. 2.7.1. 2.7.2. 2.5.1. 2.5.2. 2.5.3. 2.4.1. 2.4.2. 2.4.3. Request Handling Rules...................................................................................... 107 Completion Handling Rules................................................................................ 120 TRANSACTION ORDERING............................................................................................ 122 Transaction Ordering Rules ............................................................................... 122 Update Ordering and Granularity Observed by a Read Transaction................ 126 Update Ordering and Granularity Provided by a Write Transaction ................ 127 2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 128 Virtual Channel Identification (VC ID) .............................................................. 130 TC to VC Mapping.............................................................................................. 131 VC and TC Rules................................................................................................. 132 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 133 Flow Control Rules............................................................................................. 134 2.7. DATA INTEGRITY ......................................................................................................... 145 ECRC Rules ........................................................................................................ 145 Error Forwarding ............................................................................................... 149 2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 151 LINK STATUS DEPENDENCIES ...................................................................................... 151 2.9. Transaction Layer Behavior in DL_Down Status............................................... 151 Transaction Layer Behavior in DL_Up Status ................................................... 153 3. DATA LINK LAYER SPECIFICATION.......................................................................... 155 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 155 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 157 Data Link Control and Management State Machine Rules ................................ 158 FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 160 Flow Control Initialization State Machine Rules ............................................... 160 3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 164 Data Link Layer Packet Rules ............................................................................ 164 3.5. DATA INTEGRITY ......................................................................................................... 169 Introduction......................................................................................................... 169 LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 169 LCRC and Sequence Number (TLP Receiver).................................................... 182 4. PHYSICAL LAYER SPECIFICATION ............................................................................ 191 INTRODUCTION ............................................................................................................ 191 LOGICAL SUB-BLOCK................................................................................................... 191 Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 192 4.2.1. Encoding for 8.0 GT/s and Higher Data Rates................................................... 200 4.2.2. Link Equalization Procedure for 8.0 GT/s Data Rate ........................................ 218 4.2.3. Link Initialization and Training.......................................................................... 226 4.2.4. Link Training and Status State Machine (LTSSM) Descriptions........................ 244 4.2.5. Link Training and Status State Rules.................................................................. 247 4.2.6. Clock Tolerance Compensation.......................................................................... 314 4.2.7. 4.2.8. Compliance Pattern in 8b/10b Encoding............................................................ 317 4.2.9. Modified Compliance Pattern in 8b/10b Encoding ............................................ 318 4.2.10. Compliance Pattern in 128b/130b Encoding...................................................... 320 4.2.11. Modified Compliance Pattern in 128b/130b Encoding ...................................... 322 3.5.1. 3.5.2. 3.5.3. 4.1. 4.2. 4 PCI EXPRESS BASE SPECIFICATION, REV. 3.0 4.3. 5.6. 6.1. 6.2. 5.1.1. 5.3.1. 5.3.2. 5.3.3. 5.4.1. 5.5.1. 5.2. 5.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.7. 4.3.8. ELECTRICAL SUB-BLOCK ............................................................................................. 323 Electrical Specification Organization................................................................. 323 Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices .............................. 323 Transmitter Specification.................................................................................... 325 Receiver Specifications ....................................................................................... 359 Low Frequency and Miscellaneous Signaling Requirements ............................. 382 Channel Specification ......................................................................................... 387 Refclk Specifications ........................................................................................... 400 Refclk Specifications for 8.0 GT/s....................................................................... 408 5. POWER MANAGEMENT................................................................................................. 413 5.1. OVERVIEW ................................................................................................................... 413 Statement of Requirements.................................................................................. 414 LINK STATE POWER MANAGEMENT............................................................................. 414 PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 419 Device Power Management States (D-States) of a Function.............................. 419 PM Software Control of the Link Power Management State.............................. 424 Power Management Event Mechanisms ............................................................. 429 5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 436 Active State Power Management (ASPM) .......................................................... 436 5.5. AUXILIARY POWER SUPPORT....................................................................................... 455 Auxiliary Power Enabling................................................................................... 455 POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 456 6. SYSTEM ARCHITECTURE ............................................................................................. 459 INTERRUPT AND PME SUPPORT................................................................................... 459 Rationale for PCI Express Interrupt Model........................................................ 459 6.1.1. PCI Compatible INTx Emulation........................................................................ 460 6.1.2. 6.1.3. INTx Emulation Software Model ........................................................................ 460 6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 460 PME Support....................................................................................................... 462 6.1.5. Native PME Software Model .............................................................................. 462 6.1.6. Legacy PME Software Model ............................................................................. 463 6.1.7. 6.1.8. Operating System Power Management Notification........................................... 463 PME Routing Between PCI Express and PCI Hierarchies ................................ 463 6.1.9. ERROR SIGNALING AND LOGGING................................................................................ 464 Scope................................................................................................................... 464 Error Classification ............................................................................................ 464 Error Signaling ................................................................................................... 466 Error Logging ..................................................................................................... 474 Sequence of Device Error Signaling and Logging Operations .......................... 478 Error Message Controls ..................................................................................... 480 Error Listing and Rules ...................................................................................... 481 Virtual PCI Bridge Error Handling.................................................................... 486 Internal Errors.................................................................................................... 488 6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 489 Introduction and Scope....................................................................................... 489 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. 6.2.6. 6.2.7. 6.2.8. 6.2.9. 6.3.1. 5
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