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ASUS_U35(U30)JC 华硕笔记本电路图

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  • 日期: 2018-07-24
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标签: 电路图

华硕笔记本电路图。

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5 4 3 2 1 SYSTEM PAGE REF PAGE Content U35JC SCHEMATIC Revision 10 Power VCORE System VTTPCH DDR VTT 18VS NVDD Page 80 Page 81 D Page 82 Page 83 Page 84 Page 85 VGFXCORE Page 86 Charger Page 88 C Load Switch Page 91 RJ45 Page 34 NEC UPD720200F1 USB30 Page 68 4 6 CMOS Camera B Page 62 MiniCard TV Tuner 12 Bluetooth 11 Page 64 Page 61 CPU CLARKFIELDAUBURNDALE DCQC Page 36 FDI x8 FDI x8 FDI x8 FDI x8 PCH Ibex PeakM DDR3 SODIMM Page 1618 IOBD MiniCard WLAN Shirley Peak Echo Peak P......

5 4 3 2 1 SYSTEM PAGE REF. PAGE Content U35JC SCHEMATIC Revision 1.0 Power VCORE System VTT_PCH DDR & VTT +1.8VS +NVDD Page 80 Page 81 D Page 82 Page 83 Page 84 Page 85 +VGFX_CORE Page 86 Charger Page 88 C Load Switch Page 91 RJ45 Page 34 NEC UPD720200F1 USB3.0 Page 68 4 6 CMOS Camera B Page 62 MiniCard TV Tuner 12 Bluetooth 1.1 Page 64 Page 61 CPU CLARKFIELD/AUBURNDALE (DC&QC) Page 3~6 FDI x8 FDI x8 FDI x8 FDI x8 PCH Ibex Peak-M DDR3 SO-DIMM Page 16~18 IO_BD. MiniCard WLAN Shirley Peak/ Echo Peak Page 53 Page 64 Page 33 MiniCard TV Tuner GigaLAN AR8131 ExpressCard Page 43 USB Port(1) Page 52 USB Port(2) IO_BD. Page 56 9 2 DDR3 800/1066MHz DDR3 800/1066MHz DDR3 800/1066MHz DDR3 800/1066MHz PCIE x1 PCIE x1 PCIE x1 PCIE x1 USBUSBUSBUSB Page 51 5 0 1 1 5 6 3 Page 20~28 ODD HDD(1) Page 51 eSATA Page 39 DMI x4 DMI x4 DMI x4 DMI x4 SATA SATA1 SATASATA 0 5 D C B A 1 2 3 4 5 6 7 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 35 44 45 46 48 50 51 52 57 58 60 61 62 63 65 70 Block Diagram System Setting CPU(1)_DMI,PEG,FDI,CLK,MISC CPU(2)_DDR3 CPU(3)_CFG,RSVD,GND CPU(4)_PWR CPU(5)_XDP DDR3 SO-DIMM_0 DDR3 SO-DIMM_1 DDR3 CA_DQ VOLTAGE PCH_IBEX(1)SATA,IHDA,RTC,LPC PCH_IBEX(2)_PCIE,CLK,SMB,PEG PCH_IBEX(3)_FDI,DMI,SYS PWR PCH_IBEX(4)_DP,LVDS,CRT PCH_IBEX(5)_PCI,NVRAM,USB PCH_IBEX(6)CPU,GPIO,MISC PCH_IBEX(7)_POWER,GND PCH_IBEX(8)_POWER,GND PCH_SPI ROM,OTH CLK_ICS9LRS3197 EC_IT8570(1/2) EC_IT8570(2/2)KB, TP RST_Reset Circuit Hybrid Switch BUG_Debug CRT_LCD Panel CRT_D-Sub TV_HDMI FAN_Fan & Sensor XDD_HDD & ODD USB_USB Port *1 DSG_Discharge PW_PROTECT DC & BAT Conn. BT_Bluetooth CMO CMOS CAMERA B TO B Conn ME_Conn & Skew Hole VGA_Madison 80 81 82 83 84 85 86 88 91 93 94 PW_VCORE PW_SYSTEM PW_I/O_VTT_PCH PW_I/O_DDR& VTT PW_I/O_+1.8VS PW_I/O_+NVDD PW_+VGFX_CORE PW_CHARGER PW_LOAD SWITCH PW_SIGNAL PW_FLOWCHART BLOCK DIAGRAM HDMI Page 48 CRT Page 46 LCD Panel Page 45 CRTCRTCRTCRTHDMI HDMI HDMIHDMI Touchpad Page 31 Keyboard Page 31 N11M-GE2 128Mx8 VRAM Page 70 LVDSCRTCRTCRTCRT LVDS LVDSLVDS LVDS LVDS LVDSLVDS EC ITE IT8570 Page 30 SPI ROM Debug Conn. Page 44 Page 28 INT. MIC Page 62 IO_BD. Audio Amp Page 36 Jack Page 65 Cardreader Page 40 Azalia Codec Realtek ALC269 Page 36 CardReader AU6344 Page 40 Clock Generator ICS ICS9LRS3162 Page 29 PCIE x16 PCIE x16 PCIE x16 PCIE x16 LPCLPCLPCLPC Azalia Azalia Azalia Azalia USBUSBUSBUSB 5 4 3 2 Discharge Circuit DC & BATT. Conn. Page 57 Page 60 Reset Circuit Skew Holes Page 50 Page 32 Page 65 PWM Fan A Rev Rev Rev 1.0 1.0 1.0 ASUSTeK COMPUTER INC. NB4 ASUSTeK COMPUTER INC. NB4 ASUSTeK COMPUTER INC. NB4 Size Size Size Project Name Project Name Project Name Title : Title : Title : Engineer: Engineer: Engineer: Block Diagram Block Diagram Block Diagram Leon Leon Leon C C C U35JC U35JC U35JC Date: Date: Date: Tuesday, March 02, 2010 Tuesday, March 02, 2010 Tuesday, March 02, 2010 Sheet Sheet Sheet 1 1 1 of of of 99 99 99 1 5 4 3 PCH_IBEX GPIO PCH_IBEX GPIO GPIO 00 GPIO 01 GPIO [2:5] D C B A GPIO 06 GPIO 07 GPIO 08 GPIO 09 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 44 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 72 GPIO 73 GPIO 74 GPIO 75 Use As Signal Name Native Native Native GPI GPI GPI Native Native GPI Native Native Native GPO GPO GPI Native Native Native Native GPO Native GPO Native GPI Native GPO Native GPO GPI GPI GPI Native Native GPO GPI GPI GPI Native Native Native Native Native Native Native Native Native GPO Native Native GPO Native Native Native Native GPO GPI Native Native Native Native Native Native Native GPO GPO Native Native Native GPI GPIO0 GPIO1 PCI_INT[E:H]# DGPU_HPD_INTR#_R USB3_SMI# EXT_SMI# - - EXT_SCI# - HDA_DOCK_RST# - BT_LED DGPU_HOLD_RST# DGPU_PWROK CLK_REQ1_TV# SATA1GP CLKREQ2#_WLAN SATA0GP WLAN_LED LPC_DRQ#1 USB20_SEL CLKREQ3_NEWCARD# CLKREQ4_USB VRM_EN WLAN_ON# ME_PM_SLP_LAN#_PCH ME_SusPwrDnAck ME_AC_PRESENT_PCH PM_CLKRUN# HDA_DOCK_EN# GPIO34 SATA_CLK_REQ# dGPU_PWR_EN#_GPIO36 DGPU_PRSNT# PCB_ID0 PCB_ID1 - - - - CLK_REQ5# CLK_REQ6# CLK_REQ7# CLKREQ_PEG#_R GPIO48 PCH_TEMP_ALERT# PCI_REQ1# PCI_GNT1# dGPU_SELECT#_GPIO52 - PCI_REQ3# PCI_GNT3# CLKREQ_GLAN# BT_ON SML1_CLK - SML0ALERT# PM_SUS_STAT# SUS_CLK SLP_S5# CLK_OUT0 CLK_OUT1 CLK_OUT2 CLK_OUT3 PW_BATLOW# CLK_REQ0# SML1ALERT# SML1_DAT Internal & External Pull-up/down EXT PU INT PU, EXT PU EXT PU INT PU, EXT PU INT PU, EXT PU EXT PU & INT PU EXT PU EXT PU EXT PU - INT PD - INT PD - EXT PD & INT PU EXT PU EXT PU EXT PD EXT PU - INT PU - EXT PU EXT PD INT PU INT PU - EXT PU EXT PU EXT PU EXT PD, INT PU EXT PU EXT PD - - EXT PD EXT PD EXT PU EXT PU EXT PU EXT PU EXT PU EXT PD, INT PU EXT PU EXT PU/PD EXT PU EXT PU EXT PU INT PU - INT PU EXT PU EXT PU, INT PU EXT PD - EXT PU EXT PU (Not used) EXT PU - - - INT PD INT PD INT PD - Power +3VS +3VS +3VS +3VS +3VS +3VSUS +3VSUS +3VSUS +3VSUS_ORG - - +3VSUS - - GND +3VS +3VS GND +3VS - - - +3VSUS_ORG GND - - - +3VSUS_ORG +3VSUS_ORG +3VS GND - - - - - - +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VS +3VS +3VS - +3VS - +3VS +3VS GND - +3VSUS_ORG +3VSUS +3VSUS_ORG - - - - - - - EXT PU, INT PU INT PU EXT PU EXT PU +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG EC GPIO Use As Signal Name GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPG0 GPG1 GPG2 GPG6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 GPJ5 O O O O O O O IO IO O O O O IO IO O I O I I I I I O O O I I I I I O O O O I IO O I I I IO O O O O O O I I I I I I I I O O O O O O PWR_LED# CHG_LED# CHG_FULL_LED# - LCD_BL_PWM FAN_PWM - - BATSEL_0 BATSEL_1 ME_AC_PRESENT_EC SMB0_CLK SMB0_DAT A20GATE RCIN# PM_RSMRST# Clock_select_uc SMB1_CLK SMB1_DAT PM_PWRBTN# AC_IN_OC# OP_SD# BAT1_IN_OC# RFON_SW# PWRLIMIT# PM_SUSC# BUF_PLT_RST# EXT_SCI# EXT_SMI# LCD_BACKOFF# FAN0_TACH HDMI_HP_EC - - - - PWR_SW# - LID_SW# MARATHON# - VSUS_ON VCCP_DV0 VCCP_DV1 TP_CLK TP_DAT THRO_CPU PCH_SPI_OV ME_SusPwrDnAck_EC PM_SUSB# - - PM_CLKRUN# GFX_VR_ON CHG_EN SUSC_EC# SUSB_EC# NUM_LED# CAP_LED# VGA_ALERT# SUS_PWRGD ALL_SYSTEM_PWRGD VRM_PWRGD PCH_TEMP_ALERT# CPU_ISENSE GPU_ISENSE VCORE_CMSET CPU_VRON PM_PWROK VSET_EC ISET_EC CPU_DV0 CPU_DV1 2 EC IT8570 1 PCIE 1 USB 0 USB Port (1) PCIE 2 Minicard WLAN USB 1 Card Reader(2.0) PCIE 3 PCIE 4 USB 3.0 PCIE 5 PCIE 6 GLAN PCIE 7 PCIE 8 SATA 0 SATA HDD (1) SATA1 SATA4 SATA5 USB 2 USB Port (3) USB 3 USB 4 USB 5 USB 6 USB 7 USB 8 WiFi/WiMax USB 9 Camera USB 10 USB 11 USB 12 Bluetooth USB 13 SM_BUS ADDRESS : PCH Master SM-Bus Device Clock Generator( ICS9LVS3162BKLFT) SO-DIMM 0 SO-DIMM 1 WiFi/WiMax EC Master (SMB1) SM-Bus Device INA219AIDCNR(CPU) INA219AIDCNR(VGA) Device Identification SM-Bus Address 1101001x ( D2 ) 1010000x ( A0 ) 1010001x ( A2 ) N/A SM-Bus Address x1000000 ( 40 ) x1000001 ( 41 ) CPU Thermal Sensor P/N: component name 1st 06G073050010 Current/Power Monitor S S S Clock Gen P/N: component name 1st 06G011604010 ICS9LRS3197 S S D C B A 5 4 3 2 ASUSTeK COMPUTER INC. NB4 ASUSTeK COMPUTER INC. NB4 ASUSTeK COMPUTER INC. NB4 Size Size Size Project Name Project Name Project Name Title : Title : Title : Engineer: Engineer: Engineer: System Setting System Setting System Setting Leon Leon Leon C C C U35JC U35JC U35JC Date: Date: Date: Wednesday, March 10, 2010 Wednesday, March 10, 2010 Wednesday, March 10, 2010 Sheet Sheet Sheet 2 2 2 of of of 99 99 99 1 Rev Rev Rev 1.0 1.0 1.0 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 D 22 FDI_TXN[7:0] 22 FDI_TXP[7:0] 5 F7 J8 K8 J4 F9 J6 K9 J2 H17 K15 J13 F10 G17 M15 G13 J11 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 L2 N7 M4 P1 N10 R7 U7 W8 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 K1 N5 N2 R2 N9 R8 U6 W10 U0301A U0301A DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] 22 22 22 22 22 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 AC7 AC9 AB5 AA1 AB2 FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] C For Intel GFX display D D M M I I I I n n t t e e l l ( ( R R ) ) F F D D I I S S C C I I H H P P A A R R G G - - - - S S S S E E R R P P X X E E I I C C P P PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] B12 A13 D12 B11 G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L20 4 3 2 1 PEG_IRCOMP_R R0301 R0301 EXP_RBIAS R0302 R0302 1 1 1% 1% 1% 1% 2 2 49.9Ohm 49.9Ohm 750Ohm 750Ohm PCIENB_RXN0 PCIENB_RXN1 PCIENB_RXN2 PCIENB_RXN3 PCIENB_RXN4 PCIENB_RXN5 PCIENB_RXN6 PCIENB_RXN7 PCIENB_RXP0 PCIENB_RXP1 PCIENB_RXP2 PCIENB_RXP3 PCIENB_RXP4 PCIENB_RXP5 PCIENB_RXP6 PCIENB_RXP7 PCIENB_RXN[7:0] 70 Main Board CLKDREF CLKDREF# R330 R330 R331 R331 1 1 N/A N/A N/A N/A 2 2 0Ohm 0Ohm 0Ohm 0Ohm R0370,R0371,R0372 near U0301 SKTOCC#:pulled to ground on processor. may use to determine if CPU is present PCIENB_RXP[7:0] 70 20Ohm 20Ohm 20Ohm 20Ohm 49.9Ohm 49.9Ohm 49.9Ohm 49.9Ohm 2 2 2 2 1% 1% 1% 1% 1% 1% 1% 1% 1 1 1 1 R0303 R0303 H_COMP3 AD71 R0304 R0304 H_COMP2 AC70 R0305 R0305 H_COMP1 AD69 R0306 R0306 H_COMP0 AE66 U0301B U0301B COMP3 COMP2 COMP1 COMP0 For EC request, to read PECI via EC. Connection: R0317.2-->Q0301.1-->U3001.118 49.9Ohm 49.9Ohm 2 H_CATERR# 1% 1% 1 R0307 R0307 N61 CATERR# +VTT_CPU T0301 T0301 TP_SKTOCC# 1 M71 PROC_DETECT M M i i s s c c s s k k c c o o l l C C BCLK BCLK# BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# AK7 AK8 K71 J70 L21 J21 Y2 W4 CLK_CPU_BCLK CLK_CPU_BCLK# CLK_ITP_BCLK_R CLK_ITP_BCLK#_R CLK_EXP_P CLK_EXP_N CLKDREF CLKDREF# CLK selection 2 2 SL0333 SL0333 SL0334 SL0334 0402 0402 0402 0402 1 1 CLK_ITP_BCLK 7 CLK_ITP_BCLK# 7 R0329 R0329 R0330 R0330 1 1 @ @ @ @ 2 2 0Ohm 0Ohm 0Ohm 0Ohm CLK_DREF CLK_DREF# 21 21 120MHz from PCH. PCIENB_TXN0 PCIENB_TXN1 PCIENB_TXN2 PCIENB_TXN3 PCIENB_TXN4 PCIENB_TXN5 PCIENB_TXN6 PCIENB_TXN7 C0301 C0301 C0302 C0302 C0303 C0303 C0304 C0304 C0305 C0305 C0306 C0306 C0307 C0307 C0308 C0308 PCIENB_TXP0 PCIENB_TXP1 PCIENB_TXP2 PCIENB_TXP3 PCIENB_TXP4 PCIENB_TXP5 PCIENB_TXP6 PCIENB_TXP7 C0317 C0317 C0318 C0318 C0319 C0319 C0320 C0320 C0321 C0321 C0322 C0322 C0323 C0323 C0324 C0324 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V PCIEG_RXN0 PCIEG_RXN1 PCIEG_RXN2 PCIEG_RXN3 PCIEG_RXN4 PCIEG_RXN5 PCIEG_RXN6 PCIEG_RXN7 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V PCIEG_RXP0 PCIEG_RXP1 PCIEG_RXP2 PCIEG_RXP3 PCIEG_RXP4 PCIEG_RXP5 PCIEG_RXP6 PCIEG_RXP7 R0310 don't remove +VTT_CPU 25 H_PECI 80 H_PROCHOT_S# 2 SL0312 SL0312 0402 0402 PCIEG_RXN[7:0] 70 25 H_THRMTRIP# SL0311 SL0311 THRO_CPU SL0308 SL0308 R0322 R0322 2 0Ohm 0Ohm 2 @ R0317 R0317 @ 2 0402 0402 1 1 H_PECI_ISO N19 PECI 1 68OHM 68OHM H_PROCHOT_S#_R N67 PROCHOT# 1 H_THRMTRIP#_R N17 0402 0402 THERMTRIP# 1 2 7 H_CPURST# 22 PM_SYNC# 2 SL0329 SL0329 0402 0402 1 PM_SYNC#_R N70 M17 RESET_OBS# PM_SYNC PCIEG_RXP[7:0] 70 7,25 H_CPUPWRGD 2 SL0330 SL0330 0402 0402 VCCPWRGOOD_1_R 1 AM7 T0306 T0306 1 VCCPWRGOOD_1 2 SL0331 SL0331 0402 0402 VCCPWRGOOD_0_R 1 Y67 T0305 T0305 1 VCCPWRGOOD_0 22 H_DRAM_PWRGD 2 SL0332 SL0332 0402 0402 VDDPWRGOOD_R 1 AM5 SM_DRAMPWROK 58 H_VTTPWRGD 7 H_PWRGD_XDP 7,24,30,32,63,70 BUF_PLT_RST# T0304 T0304 1 H15 Y70 VTTPWRGOOD TAPPWRGOOD R0318 R0318 1 2 PLT_RST#_R 1 G3 T0307 T0307 RSTIN# 1.5KOhm 1.5KOhm 1% 1% 1 R0319 R0319 750Ohm 750Ohm 1% 1% 2 +VTT_CPU H_CPURST# R0313 R0313 XDP_TMS R0345 R0345 XDP_TDI_R R0346 R0346 XDP_PREQ# R0347 R0347 XDP_TCLK R0348 R0348 2 1 1 1 1 @ @ @ @ @ @ @ @ @ @ 1 2 2 2 2 68OHM 68OHM 51Ohm 51Ohm 51Ohm 51Ohm 51Ohm 51Ohm 51Ohm 51Ohm T T h h e e r r m m a a l l P P o o w w e e r r M M a a n n a a g g e e m m e e n n t t 3 3 R R D D D D c c s s i i M M P P B B M M & & G G A A T T J J SM_DRAMRST# BJ12 M_DRAMRST# 16,17 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] BV33 BP39 BV40 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 R0331 R0331 R0332 R0332 R0333 R0333 1 1 1 1% 1% 1% 1% 1% 1% 2 2 2 100Ohm 100Ohm 24.9Ohm 24.9Ohm 130Ohm 130Ohm PM_EXT_TS#[0] PM_EXT_TS#[1] AV66 AV64 PM_EXTTS#1 +VTT_CPU PM_EXTTS#0 16,17 RN0301A RN0301A RN0301B RN0301B 2 4 10KOHM 10KOHM 10KOHM 10KOHM 1 3 1 T0309 T0309 XDP_PRDY# XDP_PREQ# 7 7 XDP_TCLK 7 1 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M T0308 T0308 XDP_TRST# 7 1 T0310 T0310 XDP_TMS 7 1 1 1 1 T0311 T0311 T0312 T0312 T0313 T0313 T0314 T0314 U71 U69 T67 N65 P69 T69 T71 P71 T70 W71 H_DBR#_R 1 0402 0402 2 SL0350 SL0350 J69 J67 J62 K65 K62 J64 K69 M69 XDP_DBRESET# 7,22 XDP_OBS[7:0] 7 XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 PRDY# PREQ# TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] DRAMPWROK: (DGU R1.52) VDDPWRGOOD_R +1.5V 2 1 1 2 R0320 R0320 1.1KOhm 1.1KOhm 1% 1% R0321 R0321 3.01KOHM 3.01KOHM 1% 1% D C B A CN80617003981 CN80617003981 25 BCLK_CPU_P_PCH 25 BCLK_CPU_N_PCH 21 CLK_DMI_PCH 21 CLK_DMI#_PCH 2 SL0323 SL0323 2 SL0324 SL0324 0402 0402 0402 0402 2 SL0325 SL0325 2 SL0326 SL0326 0402 0402 0402 0402 1 1 1 1 CLK_CPU_BCLK CLK_CPU_BCLK# CLK_EXP_P CLK_EXP_N B A FDI disable: (For discrete graphic) 1. NC: FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7] VCC_AXGSENSE,VSS_AXGSENSE 2. Pull-down to GND via 1KΩ ± 5% resistor: FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON ~15mW power saving.(DG R0.8 P.70) 3. Connected to GND: VCCAXG, 4. Can be connected to GND directly: DPLL_REF_CLK,DPLL_REF_CLK# 5. Connect to +V1.05S rail: VCCFDIPLL FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 FDI_INT DG R1.1 P.83: 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1 1 1 1 1 @ @ @ @ @ @ @ @ @ @ 2 R0364 R0364 2 R0361 R0361 2 R0365 R0365 2 R0362 R0362 2 R0363 R0363 *FDI_FSYNC[0],FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1] can be ganged together with one resistor. *On the other hand,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PCH side can be left as no connect without any power or functional impact. JTAG MAPPING XDP_TDI_R XDP_TDO_M 2 SL0328 SL0328 R0350 R0350 1 0402 0402 @ @ 1 2 SL0351 2 SL0351 0 0 4 4 0 0 2 XDP_TDI_M R0352 R0352 1 @ @ XDP_TDO_R 2 SL0327 SL0327 0402 0402 1 2 2 1 0Ohm 0Ohm 0Ohm 0Ohm XDP_TDI 7 XDP_TDO 7 XDP_TRST# 1 2 R0354 R0354 51Ohm 51Ohm 30,88 PWRLIMIT# H_PROCHOT_S# @ @ 2 D0301 D0301 1 RB751V-40 RB751V-40 R1.1,item L10. 3 3 D D 1 1 G G S S 2 2 Q0301 Q0301 2N7002 2N7002 THRO_CPU 30 Add test point for factory ICT boundary scan . CPU: (page3) Ball# Signal Test Point PCH: (page 20,21,22) Ball# Signal Test Point BCLK T0303 VTTPWRGOOD T0304 VCCPWRGOOD_0 T0305 VCCPWRGOOD_1 T0306 RSTIN# T0307 TRST# T0308 TCK T0309 TMS T0310 TDI T0311 TDO T0312 TDI_M T0313 TDO_M T0314 JTAG_TCK T2013 JTAG_TMS T2014 JTAG_TDI T2015 JTAG_TDO T2016 JTAG_RST# T2017 RSMRST# T2209 RTCRST# T2018 PWROK T2210 MEPWROK T2211 LAN_RST# T2212 CLKIN_PCILOOPBACK T2113 INTVRMEN T2019 SYS_PWROK T2213 SRTCRST# T2020 5 4 3 2 C C C U35JC U35JC U35JC Date: Date: Date: Friday, April 09, 2010 Friday, April 09, 2010 Friday, April 09, 2010 Sheet Sheet Sheet 3 3 3 of of of 99 99 99 1 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 Size Size Size Project Name Project Name Project Name Title : Title : Title : Engineer: Engineer: Engineer: CPU(1)_DMI,PEG,FDI,CLK,MISC CPU(1)_DMI,PEG,FDI,CLK,MISC CPU(1)_DMI,PEG,FDI,CLK,MISC Leon Leon Leon Rev Rev Rev 1.0 1.0 1.0 5 4 3 2 1 Main Board U0301C U0301C SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AT8 AT6 BB5 BB9 AV7 AV6 BE6 BE8 BF11 BE11 BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 BK15 BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66 BJ66 BF65 AY64 BC70 16 16 16 16 16 16 M_A_BS0 M_A_BS1 M_A_BS2 M_A_CAS# M_A_RAS# M_A_WE# BT38 BH38 BF21 SA_BS[0] SA_BS[1] SA_BS[2] BK43 BL38 BF38 SA_CAS# SA_RAS# SA_WE# CN80617003981 CN80617003981 D 16 M_A_DQ[63:0] C B A SA_CK[0] SA_CK#[0] SA_CKE[0] BM34 BP35 BF20 SA_CK[1] SA_CK#[1] SA_CKE[1] BK36 BH36 BK24 SA_CS#[0] SA_CS#[1] BH40 BJ47 SA_ODT[0] SA_ODT[1] BF43 BL47 M_CLK_DDR0 M_CLK_DDR#0 M_CKE0 16 16 16 M_CLK_DDR1 M_CLK_DDR#1 M_CKE1 16 16 16 M_CS#0 M_CS#1 M_ODT0 M_ODT1 16 16 16 16 17 M_B_DQ[63:0] M_A_DM[7:0] 16 M_A_DQS#[7:0] 16 M_A_DQS[7:0] 16 M_A_A[15:0] 16 A A Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59 AY5 BJ7 BN13 BL21 BH44 BK51 BP58 BE62 AY7 BJ5 BL13 BN21 BK44 BH51 BM60 BE64 BT36 BP33 BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28 BH34 BH30 BJ28 BF40 BN28 BN25 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 U0301D U0301D SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# BA2 AW2 BD1 BE4 AY1 BC2 BF2 BH2 BG4 BG1 BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60 BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BK70 BK67 BD71 BD69 BV43 BV41 BV24 BU46 BT40 BT41 CN80617003981 CN80617003981 B B - - Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D 17 17 17 17 17 17 M_B_BS0 M_B_BS1 M_B_BS2 M_B_CAS# M_B_RAS# M_B_WE# M_CLK_DDR2 M_CLK_DDR#2 17 M_CKE2 17 17 M_CLK_DDR3 M_CLK_DDR#3 M_CKE3 17 17 17 M_CS#2 M_CS#3 M_ODT2 M_ODT3 17 17 17 17 M_B_DM[7:0] 17 M_B_DQS#[7:0] 17 M_B_DQS[7:0] 17 M_B_A[15:0] 17 SB_CK[0] SB_CK#[0] SB_CKE[0] SB_CK[1] SB_CK#[1] SB_CKE[1] BU33 BV34 BT26 BV38 BU39 BT24 SB_CS#[0] SB_CS#[1] BP46 BT43 SB_ODT[0] SB_ODT[1] BV45 BU49 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] BE2 BM3 BU12 BT19 BT52 BV55 BU63 BG69 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] BD4 BN4 BV13 BT17 BT50 BU56 BV62 BJ69 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] BT34 BP30 BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27 BU42 BU26 BT29 BT45 BV26 BU23 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 D C B A 5 4 3 2 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 Size Size Size Project Name Project Name Project Name Title : Title : Title : Engineer: Engineer: Engineer: CPU(2)_DDR3 CPU(2)_DDR3 CPU(2)_DDR3 Leon Leon Leon C C C U35JC U35JC U35JC Date: Date: Date: Friday, April 09, 2010 Friday, April 09, 2010 Friday, April 09, 2010 Sheet Sheet Sheet 4 4 4 of of of 99 99 99 1 Rev Rev Rev 1.0 1.0 1.0 5 4 3 2 1 CFG strapping information: CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only) - 11 = 1 x 16 PEG (Default) - 10 = 2 x 8 PEG CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only) - 1:Normal Operation (Default) - 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, ... CFG[4]: Embedded DisplayPort Detection.(Auburndale Only) - 1:Disabled - No Physical Display Port attached to Embedded DisplayPort - 0:Enabled - An external Display Port device is connected to the Embedded Display Port D CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfield) Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistor For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality. Unmount if Intel has fixed this issue. Note: (Auburndale)Hardware Straps are sampled on the asserting edge of VCCPWRGOOD_0 and VCCPWRGOOD_1 and latched inside the processor. Note: (Clarksfield)Hardware Straps are sampled after RSTIN# de-assertion. Intel sighting #: 402607(3393727) To drive a value of zero on CFG[0] pin use a 250 Ohm pull down resistor to Vss. CFG0 R0535 R0535 CFG3 R0536 R0536 CFG4 R0537 R0537 C CFG7 R0538 R0538 1 3.01KOHM 3.01KOHM 1 3.01KOHM 3.01KOHM 1 3.01KOHM 3.01KOHM 1 3.01KOHM 3.01KOHM 2 2 2 2 @ @ 1% 1% @ @ 1% 1% @ @ 1% 1% @ @ 1% 1% R1.1,item B1 1 1 1 1 1 1 1 1 T0504 T0504 T0501 T0501 T0503 T0503 T0507 T0507 T0505 T0505 T0513 T0513 T0508 T0508 T0509 T0509 R0540 R0540 R0541 R0541 1 1 2 2 0Ohm @ 0Ohm @ 0Ohm @ 0Ohm @ H_TP_DC_TEST_BV71_BV69 H_TP_DC_TEST_BV3_BT3 H_TP_DC_TEST_BV1_BT1 H_TP_DC_TEST_BT71_BT69 H_TP_DC_TEST_C71_A71 H_TP_DC_TEST_C69_A69 VCAP0_SENSE VCAP0_VSS_SENSE RSVD34 RSVD_TP[2] RSVD_TP[1] RSVD37 RSVD38 RSVD39 RSVD_NCTF[3] RSVD_TP[6] RSVD_NCTF[2] RSVD_NCTF[1] RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 RSVD_TP[4] RSVD_TP[3] RSVD62 RSVD63 RSVD64 RSVD65 DC_TEST_BV71 DC_TEST_BV69 DC_TEST_BV68 DC_TEST_BV5 DC_TEST_BV3 DC_TEST_BV1 DC_TEST_BT71 DC_TEST_BT69 DC_TEST_BT3 DC_TEST_BT1 DC_TEST_BR71 DC_TEST_BR1 DC_TEST_E71 DC_TEST_E1 DC_TEST_C71 DC_TEST_C69 DC_TEST_C3 DC_TEST_A71 DC_TEST_A69 DC_TEST_A68 DC_TEST_A5 W66 W64 AC69 AC71 AA71 AA69 R66 R64 BT5 BR5 BV6 BV8 AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67 AP2 AN7 AV4 AU2 BE69 BE71 BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1 E71 E1 C71 C69 C3 A71 A69 A68 A5 D D E E V V R R E E S S E E R R eDP=3.3K PD U0301E U0301E AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] AU1 RSVD_TP[5] T0578 T0578 T0567 T0567 T0566 T0566 T0565 T0565 T0569 T0569 T0568 T0568 T0571 T0571 T0572 T0572 T0574 T0574 T0570 T0570 T0575 T0575 T0573 T0573 T0576 T0576 T0577 T0577 T0592 T0592 T0581 T0581 T0580 T0580 T0579 T0579 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 R0542 R0542 R0543 R0543 1 1 2 2 0Ohm @ 0Ohm @ 0Ohm @ 0Ohm @ T4 T2 U1 V2 AV71 AW70 AY69 BB69 D8 B7 A10 B9 C5 A6 E3 F1 T0511 T0511 T0512 T0512 T0514 T0514 T0515 T0515 1 1 1 1 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD26 RSVD27 RSVD_NCTF[7] RSVD_NCTF[8] RSVD_NCTF[6] RSVD_NCTF[5] CN80617003981 CN80617003981 B A U0301I U0301I U0301J U0301J VSS VSS BU62 BU58 BU55 BU51 BU48 BU44 BU37 BU32 BU25 BU21 BU18 BU14 BU11 BU7 BP42 BN64 BN6 BM70 BM51 BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20 BK63 BK60 BK53 BK34 BK10 BJ64 BJ21 BJ9 BJ1 BH70 BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30 BF13 BF8 BE70 BE65 BE9 BE1 BD57 BD53 BD50 BD46 BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42 BB39 BB7 BB1 BA70 AY71 AY66 AY62 AY59 AY55 AY51 AY48 AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23 AR21 AR19 AR17 AR15 AR14 AR4 AR1 AP70 AP64 AN62 AN55 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 CN80617003981 CN80617003981 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4 AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9 AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35 AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17 AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46 AN51 AN48 AN44 AN41 AN37 AN5 AN4 AM64 AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33 AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 BV66 BV64 BT68 BR69 BR68 BR3 BN71 BN1 BL71 BL1 R14 H71 F71 E69 E68 A66 A64 E5 C68 VSS VSS AH53 AH51 AH50 AH48 AH46 AH44 AH42 AH41 AH39 AH37 AH35 AH33 AH32 AH30 AH28 AH26 AH24 AH23 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30 AA28 AA26 AA24 AA23 AA21 AA19 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B40 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS374 VSS375 VSS376 VSS377 VSS378 VSS379 VSS380 VSS381 VSS382 VSS383 VSS384 VSS385 VSS386 VSS387 VSS388 VSS389 VSS390 VSS391 VSS392 VSS415 CN80617003981 CN80617003981 VSS404 VSS405 VSS406 VSS407 VSS408 VSS409 VSS410 VSS411 VSS412 VSS413 VSS393 VSS394 VSS395 VSS396 VSS397 VSS398 VSS399 VSS400 VSS401 VSS402 VSS403 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360 VSS361 VSS362 VSS363 VSS364 VSS365 VSS366 VSS367 VSS368 VSS369 VSS370 VSS371 VSS372 VSS373 A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 AA17 AA15 AA14 AA4 W69 W62 W57 W53 W50 W46 W42 W6 W1 V70 U64 U62 U57 U53 U50 U46 U42 U39 U9 U4 T1 R70 R62 R57 R53 R50 R46 R42 R5 P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36 M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11 K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 ASUSTeK COMPUTER INC. NB1 Size Size Size Project Name Project Name Project Name Main Board D C B A Title : Title : Title : Engineer: Engineer: Engineer: CPU(3)_CFG,RSVD,GND CPU(3)_CFG,RSVD,GND CPU(3)_CFG,RSVD,GND Leon Leon Leon Rev Rev Rev 1.0 1.0 1.0 5 4 3 2 1 C C C U35JC U35JC U35JC Date: Date: Date: Friday, March 12, 2010 Friday, March 12, 2010 Friday, March 12, 2010 Sheet Sheet Sheet 5 5 5 of of of 99 99 99
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