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LPC176x/5x User manual

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标签: LPC176xUsermanual

LPC176x User  manual  原版手册。

UM10360 LPC176x/5x User manual Rev. 3.1 — 2 April 2014 User manual Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC176x/5x user manual NXP Semiconductors UM10360 LPC17xx user manual Revision history Rev Date 3.1 20140402 3 20131220 Description LPC176x/5x user manual Modifications: • Added LPC1768UK. • Table 73 “Pin description (LPC175x)” and Table 74 “Pin description (LPC176x)”: Changed RX_MCLK and TX_MCLK type from INPUT to OUTPUT. LPC176x/5x user manual Modifications: • Part ID for part LPC1763 added. • Changed title to “LPC176x/5x User manual”. • Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See Section 16.13 “ID look-up table RAM” and Section 16.15 “Configuration and search algorithm”. • Updated Serial Wire Output description (Table 610). • Clarified burst mode information for ADGINTEN (Table 532 and Table 534). • Condition CCLK > 18 MHz for USB operation is not applicable for this USB peripheral and was removed (see Section 4.7.1, Section 11.13, and Section 13.11). • Description of CAN interrupt request updated. One common CAN interrupt is triggered. See Section 16.8.3. • Condition on minimum frequency of CAP input clock added in Section 21.5.1. • Description of RIMASK register corrected. See Table 434. • Condition for maximum allowable STCLK frequency added. See Section 23.4. • Delete statement “All PWM related Match registers are configured for toggle on match.” in Figure 121. • Description of INXCNT register updated. See Section 26.6.3.6. • Reset value of the RTC_AUX register corrected. See Table 508. • DAC power-down mode removed in Section 30.2. • Added: The DAC output is disabled in deep-sleep, power-down, or deep power-down modes. See Table 538. • Boot loader SRAM use explained. See Section 33.5. • SYSRESETREQ supported. See Table 660. • Figure 19 “Ethernet packet fields” corrected. • Bit description in the SPI test control register corrected. Bit 0 indicates test mode. All other bits are reserved. See Section 17.7.5 “SPI Test Control Register (SPTCR - 0x4002 0010)”. • Figure 118 “RI timer block diagram” updated. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 2 of 849 NXP Semiconductors UM10360 LPC17xx user manual Revision history …continued Rev Date Description 2 20100819 LPC176x/5x user manual revision. Modifications: • UART0/1/2/3: FIFOLVL register removed. • ADC: reset value of the ADCTRM register changed to 0xF00 (Table 500). • Timer0/1/2/3: Description of DMA operation updated. • USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read) (Table 184). • Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46). • Part LPC1763 added. • Update register bit description of USBIntStat register in Host and Device mode (Table 155 and Table 221). • Motor control PWM: update description of match and limit registers. • GPIO: update register bit description of the FIOPIN register (Table 73). • Numerous editorial updates throughout the user manual. 1 20100104 LPC176x/5x user manual revision. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 3 of 849 UM10360 Chapter 1: LPC176x/5x Introductory information Rev. 3.1 — 2 April 2014 User manual 1.1 Introduction The LPC176x/5x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration. High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The peripheral complement of the LPC176x/5x includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 4 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information 1.2 Features Refer to Section 1.4.1 for details of features on specific part numbers. • ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included. • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). • Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash. • Up to 64 kB on-chip SRAM includes: – Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. – Up to two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose instruction and data storage. • Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers. • Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. • Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy. • Serial interfaces: – Ethernet MAC with RMII interface and dedicated DMA controller. – USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation with an on-chip PHY for device and Host functions and a dedicated DMA controller. – Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support. – Two-channel CAN controller. – Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. – SPI controller with synchronous, serial, full duplex communication and programmable data length. SPI is included as a legacy peripheral and can be used instead of SSP0. – Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 5 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information UM10360 User manual – I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. • Other peripherals: – 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. – 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. – 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. – Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. – One motor control PWM with support for three-phase motor control. – Quadrature encoder interface that can monitor one external quadrature encoder. – One standard PWM/timer block with external count input. – Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V Lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. – Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. – Cortex-M3 system tick timer, including an external clock input option. – Repetitive interrupt timer provides programmable and repeating timed interrupts. • Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace Port options. • Emulation trace module supports real-time trace. • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. • Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C. • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. • Non-maskable Interrupt (NMI) input. • Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, or the USB clock. • The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 6 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI). • Each peripheral has its own clock divider for further power savings. • Brownout detect with separate threshold for interrupt and forced reset. • On-chip Power-On Reset (POR). • On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz. • 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock. • An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. • A second, dedicated PLL may be used for the USB interface in order to allow added flexibility for the Main PLL settings. • Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. • Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7 mm), WLCSP100 (5.074  5.074  0.6 mm) package, and 80-pin LQFP (12 x 12 x 1.4 mm) packages 1.3 Applications • eMetering • Lighting • Industrial networking • Alarm systems • White goods • Motor control 1. LPC1768/65 only. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 7 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information 1.4 Ordering information Table 1. Ordering information Type number Package Name Description LPC1769FBD100 LPC1768FBD100 LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1763FBD100 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074  5.074  0.6 mm LPC1759FBD80 LPC1758FBD80 LPC1756FBD80 LQFP80 plastic low profile quad flat package; 80 leads; body 12  12 1.4 mm LPC1754FBD80 LPC1752FBD80 LPC1751FBD80 Version SOT407-1 SOT926-1 SOT315-1 1.4.1 Part options summary Table 2. Ordering options for LPC176x/5x parts Type number Max. CPU Flash speed Total Ethernet USB SRAM CAN I2S LPC1769FBD100 120 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes LPC1768FBD100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes LPC1768FET100 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes LPC1768UK 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes LPC1767FBD100 100 MHz 512 kB 64 kB yes no no yes LPC1766FBD100 100 MHz 256 kB 64 kB yes Device/Host/OTG 2 yes LPC1765FBD100 100 MHz 256 kB 64 kB no Device/Host/OTG 2 yes LPC1764FBD100 100 MHz 128 kB 32 kB yes Device 2 no LPC1763FBD100 100 MHz 256 kB 64 kB no no no yes LPC1759FBD80 120 MHz 512 kB 64 kB no Device/Host/OTG 2 yes LPC1758FBD80 100 MHz 512 kB 64 kB yes Device/Host/OTG 2 yes LPC1756FBD80 100 MHz 256 kB 32 kB no Device/Host/OTG 2 yes LPC1754FBD80 100 MHz 128 kB 32 kB no Device/Host/OTG 1 no LPC1752FBD80 100 MHz 64 kB 16 kB no Device 1 no LPC1751FBD80 100 MHz 32 kB 8 kB no Device 1 no DAC Package yes 100 pin yes 100 pin yes 100 pin yes 100 pin yes 100 pin yes 100 pin yes 100 pin no 100 pin yes 100 pin yes 80 pin yes 80 pin yes 80 pin yes 80 pin no 80 pin no 80 pin UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 8 of 849 NXP Semiconductors 1.5 Simplified block diagram UM10360 Chapter 1: LPC176x/5x Introductory information Trace Module Xtalin Xtalout RST Trace Port JTAG interface Ethernet PHY interface USB interface Test/Debug Interface ARM Cortex-M3 DMA controller Ethernet 10/100 MAC USB device, host, OTG Clocks and Controls Clock Generation, Power Control, Brownout Detect, and other system functions System bus D-code bus I-code bus High Speed GPIO APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/Compare Timers 0 & 1 Watchdog Timer PWM1 12-bit ADC Pin Connect Block GPIO Interrupt Ctl 32 kHz oscillator Real Time Clock 20 bytes of backup registers RTC Power Domain Multilayer AHB Matrix AHB to APB bridge AHB to APB bridge Flash Accelerator SRAM 64 kB ROM 8 kB Flash 512 kB APB slave group 1 SSP0 UARTs 2 & 3 I2S I2C2 Repetitive Interrupt Timer Capture/Compare Timers 2 & 3 External Interrupts DAC System Control Motor Control PWM Quadrature Encoder Note: shaded peripheral blocks support General Purpose DMA Fig 1. LPC1768 simplified block diagram UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 9 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information 1.6 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC176x/5x uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. Details of the multilayer matrix connections are shown in Figure 2. APB peripherals are connected to the CPU via two APB busses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller. The APB bus bridges are configured to buffer writes so that the CPU or DMA controller can write to APB devices without always waiting for APB write completion. 1.7 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with Wake-up Interrupt Controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is appended to this manual. 1.7.1 Cortex-M3 Configuration Options The LPC176x/5x uses the r2p0 version of the Cortex-M3 CPU, which includes a number of configurable options, as noted below. System options: • The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the SYSTICK timer. • The Wake-up Interrupt Controller (WIC) is included. The WIC allows more powerful options for waking up the CPU from reduced power modes. • A Memory Protection Unit (MPU) is included. • A ROM Table in included. The ROM Table provides addresses of debug components to external debug systems. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 10 of 849 NXP Semiconductors UM10360 Chapter 1: LPC176x/5x Introductory information Debug related options: • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire. • The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction trace capabilities. • The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data address or data value matches to be trace information or trigger other events. The DWT includes 4 comparators and counters for certain internal events. • An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in order to send messages to the trace port. • The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides trace information to the outside world. This can be on the Serial Wire Viewer pin or the 4-bit parallel trace port. • A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware breakpoints and remap specific addresses in code space to SRAM as a temporary method of altering non-volatile code. The FPB include 2 literal comparators and 6 instruction comparators. 1.8 On-chip flash memory system The LPC176x/5x contains up to 512 kB of on-chip flash memory. A flash memory accelerator maximizes performance for use with the two fast AHB-Lite buses. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. 1.9 On-chip Static RAM The LPC176x/5x contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus. Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each situated on separate slave ports on the AHB multilayer matrix. This architecture allows the possibility for CPU and DMA accesses to be separated in such a way that there are few or no delays for the bus masters. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 11 of 849 NXP Semiconductors 1.10 Block diagram UM10360 Chapter 1: LPC176x/5x Introductory information EMULATION TRACE MODULE X32Kin X32Kout Xtalin Xtalout RST JTAG interface Debug Port Ethernet PHY USB interface interface TEST/DEBUG INTERFACE ARM Cortex-M3 I-code D-code System bus bus bus DMA controller Ethernet 10/100 MAC Multilayer AHB Matrix APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/compare timers 0 & 1 Watchdog timer PWM1 12-bit ADC Pin connect block GPIO interrupt control 32 kHz oscillator Real Time Clock Vbat ultra-low power regulator Backup registers (20 bytes) RTC Power Domain AHB to APB bridge AHB to APB bridge USB device, host, OTG clocks and controls internal power clock generation, CLK power control, OUT and other system functions voltage regulator Vdd Flash Accelerator Flash 512 kB SRAM 32 kB SRAM 16 kB ROM 8 kB SRAM 16 kB HS GPIO DMAC USB Ethernet regs regs regs APB slave group 1 SSP0 UARTs 2 & 3 I2S I2C2 Capture/compare timers 2 & 3 Repetitive interrupt timer External interrupts DAC System control Motor control PWM Quadrature encoder Note: shaded peripheral blocks support General Purpose DMA Fig 2. LPC1768 block diagram, CPU and buses UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 12 of 849 UM10360 Chapter 2: LPC176x/5x Memory map Rev. 3.1 — 2 April 2014 User manual 2.1 Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the LPC176x/5x. Table 3. LPC176x/5x memory usage and details Address range General Use Address range details and description 0x0000 0000 to On-chip non-volatile 0x0000 0000 - 0x0007 FFFF 0x1FFF FFFF memory 0x0000 0000 - 0x0003 FFFF For devices with 512 kB of flash memory. For devices with 256 kB of flash memory. 0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory. 0x0000 0000 - 0x0000 7FFF For devices with 32 kB of flash memory. On-chip SRAM 0x1000 0000 - 0x1000 7FFF For devices with 32 kB of local SRAM. 0x1000 0000 - 0x1000 3FFF For devices with 16 kB of local SRAM. 0x1000 0000 - 0x1000 1FFF For devices with 8 kB of local SRAM. Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services. 0x2000 0000 to 0x3FFF FFFF On-chip SRAM (typically used for peripheral data) 0x2007 C000 - 0x2007 FFFF 0x2008 0000 - 0x2008 3FFF AHB SRAM - bank 0 (16 kB), present on devices with 32 kB or 64 kB of total SRAM. AHB SRAM - bank 1 (16 kB), present on devices with 64 kB of total SRAM. GPIO 0x2009 C000 - 0x2009 FFFF GPIO. 0x4000 0000 to APB Peripherals 0x5FFF FFFF 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks, 16 kB each. 0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks, 16 kB each. AHB peripherals 0x5000 0000 - 0x501F FFFF DMA Controller, Ethernet interface, and USB interface. 0xE000 0000 to Cortex-M3 Private 0xE00F FFFF Peripheral Bus 0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC and System Tick Timer. 2.2 Memory maps The LPC176x/5x incorporates several distinct memory regions, shown in the following figures. Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 13 of 849 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 0x4010 0000 0x400F C000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 APB1 peripherals 31 system control 30 - 16 reserved 15 QEI 14 motor control PWM 13 reserved 12 repetitive interrupt timer 11 reserved 10 I2S 9 reserved 8 I2C2 7 UART3 6 UART2 5 Timer 3 4 Timer 2 3 DAC 2 SSP0 1 - 0 reserved 4 GB LPC1768 memory space 0xFFFF FFFF reserved private peripheral bus 0xE010 0000 0xE000 0000 reserved 0x5020 0000 1 GB 0.5 GB I-code/D-code memory space AHB periherals 0x5000 0000 reserved 0x4400 0000 peripheral bit band alias addressing 0x4200 0000 reserved APB1 peripherals APB0 peripherals 0x4010 0000 0x4008 0000 0x4000 0000 reserved 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserved 0x200A 0000 GPIO 0x2009 C000 reserved 0x2008 4000 AHB SRAM (2 blocks of 16 kB) 0x2007 C000 reserved 8 kB boot ROM 0x1FFF 2000 0x1FFF 0000 reserved 32 kB local static RAM 0x1000 8000 0x1000 0000 reserved 0x0000 0400 + 256 words 0x0000 0000 active interrupt vectors 0 GB 512 kB on-chip flash 0x0008 0000 0x0000 0000 Fig 3. LPC176x/5x system memory map AHB peripherals 127- 4 reserved 0x5020 0000 3 USB controller 0x5000 C000 2 reserved 0x5000 8000 1 GPDMA controller 0x5000 4000 0 Ethernet controller 0x5000 0000 APB0 peripherals 31 - 24 reserved 0x4008 0000 0x4006 0000 23 I2C1 0x4005 C000 22 - 19 reserved 0x4004 C000 18 CAN2 0x4004 8000 17 CAN1 0x4004 4000 16 CAN common 0x4004 0000 15 CAN AF registers 0x4003 C000 14 CAN AF RAM 0x4003 8000 13 ADC 0x4003 4000 12 SSP1 0x4003 0000 11 pin connect 0x4002 C000 10 GPIO interrupts 0x4002 8000 9 RTC + backup registers 0x4002 4000 8 SPI 0x4002 0000 7 I2C0 0x4001 C000 6 PWM1 0x4001 8000 5 reserved 0x4001 4000 4 UART1 0x4001 0000 3 UART0 0x4000 C000 2 TIMER1 0x4000 8000 1 TIMER0 0x4000 4000 0 WDT 0x4000 0000 UM10360 Chapter 2: LPC176x/5x Memory map © NXP B.V. 2014. All rights reserved. 14 of 849 NXP Semiconductors UM10360 Chapter 2: LPC176x/5x Memory map Figure 3 and Table 4 show different views of the peripheral address space. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately. 2.3 APB peripheral addresses The following table shows the APB0/1 address maps. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range. Table 4. APB0 peripherals and base addresses APB0 peripheral Base address 0 0x4000 0000 1 0x4000 4000 2 0x4000 8000 3 0x4000 C000 4 0x4001 0000 5 0x4001 4000 6 0x4001 8000 7 0x4001 C000 8 0x4002 0000 9 0x4002 4000 10 0x4002 8000 11 0x4002 C000 12 0x4003 0000 13 0x4003 4000 14 0x4003 8000 15 0x4003 C000 16 0x4004 0000 17 0x4004 4000 18 0x4004 8000 19 to 22 0x4004 C000 to 0x4005 8000 23 0x4005 C000 24 to 31 0x4006 0000 to 0x4007 C000 Peripheral name Watchdog Timer Timer 0 Timer 1 UART0 UART1 reserved PWM1 I2C0 SPI RTC GPIO interrupts Pin Connect Block SSP1 ADC CAN Acceptance Filter RAM CAN Acceptance Filter Registers CAN Common Registers CAN Controller 1 CAN Controller 2 reserved I2C1 reserved UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 15 of 849 NXP Semiconductors UM10360 Chapter 2: LPC176x/5x Memory map Table 5. APB1 peripherals and base addresses APB1 peripheral Base address 0 0x4008 0000 1 0x4008 4000 2 0x4008 8000 3 0x4008 C000 4 0x4009 0000 5 0x4009 4000 6 0x4009 8000 7 0x4009 C000 8 0x400A 0000 9 0x400A 4000 10 0x400A 8000 11 0x400A C000 12 0x400B 0000 13 0x400B 4000 14 0x400B 8000 15 0x400B C000 16 to 30 0x400C 0000 to 0x400F 8000 31 0x400F C000 Peripheral name reserved reserved SSP0 DAC Timer 2 Timer 3 UART2 UART3 I2C2 reserved I2S reserved Repetitive interrupt timer reserved Motor control PWM Quadrature Encoder Interface reserved System control 2.4 Memory re-mapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the Cortex-M3. Refer to Section 6.4 and Section 34.4.3.5 of the Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature. Boot ROM re-mapping Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is normally transparent to the user. However, if execution is halted immediately after reset by a debugger, it should correct the mapping for the user. See Section 33.6. 2.5 AHB arbitration The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3 D-code bus has the highest priority, followed by the I-Code bus. All other masters share a lower priority. 2.6 Bus fault exceptions UM10360 User manual The LPC176x/5x generates Bus Fault exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are areas of the memory map that are not implemented for a specific derivative. These include all spaces marked “reserved” in Figure 3. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 16 of 849 NXP Semiconductors UM10360 Chapter 2: LPC176x/5x Memory map For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address. Within the address space of an existing APB peripheral, an exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0x4000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0x4000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC176x/5x documentation and are not a supported feature. If software executes a write directly to the flash memory, the flash accelerator will generate a Bus Fault exception. Flash programming must be accomplished by using the specified flash programming interface provided by the Boot Code. Note that the Cortex-M3 core stores the exception flag along with the associated instruction in the pipeline and processes the exception only if an attempt is made to execute the instruction fetched from the disallowed address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 17 of 849 UM10360 Chapter 3: LPC176x/5x System control Rev. 3.1 — 2 April 2014 User manual 3.1 Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: • Reset • Brown-Out Detection • External Interrupt Inputs • Miscellaneous System Controls and Status Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses 3.2 Pin description Table 6 shows pins that are associated with System Control block functions. Table 6. Pin summary Pin name Pin Pin description direction EINT0 Input External Interrupt Input 0 - An active low/high level or falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Sleep, Deep-sleep, or Power-down modes. EINT1 Input External Interrupt Input 1 - See the EINT0 description above. EINT2 Input External Interrupt Input 2 - See the EINT0 description above. EINT3 Input External Interrupt Input 3 - See the EINT0 description above. RESET Input External Reset input - A LOW on this pin resets the chip, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 18 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.3 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 7. Summary of system control registers Name Description External Interrupts EXTINT External Interrupt Flag Register EXTMODE External Interrupt Mode register EXTPOLAR External Interrupt Polarity Register Reset RSID Reset Source Identification Register Syscon Miscellaneous Registers SCS System Control and Status Access Reset value R/W 0 R/W 0 R/W 0 R/W see Table 8 R/W 0 Address 0x400F C140 0x400F C148 0x400F C14C 0x400F C180 0x400F C1A0 3.4 Reset Reset has 4 sources on the LPC176x/5x: the RESET pin, Watchdog Reset, Power On Reset (POR), and Brown Out Detect (BOD). The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in Section 4.9 “Wake-up timer” in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. The reset logic is shown in the following block diagram (see Figure 4). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 19 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control external reset watchdog reset POR BOD power-down EINT0 wake-up EINT1 wake-up EINT2 wake-up EINT3 wake-up RTC wake-up BOD wake-up Ethernet MAC wake-up USB need_clk wake-up CAN wake-up GPIO0 port wake-up GPIO2 port wake-up C Q S Reset to the on-chip circuitry Reset to PCON.PD internal RC oscillator WAKE-UP TIMER START COUNT 2 n write “1” from APB reset C Q S APB read of PDBIT in PCON FOSC to other blocks Fig 4. Reset block diagram including the wake-up timer On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 s on power-up) and after the IRC provides a stable clock output, the reset signal is latched and synchronized on the IRC clock. Then the following two sequences start simultaneously: 1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times out. The boot code performs the boot tasks and may jump to the flash. If the flash is not ready to access, the Flash Accelerator will insert wait cycles until the flash is ready. 2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. The flash wake-up timer generates the 100 s flash start-up time. Once it times out, the flash initialization sequence is started, which takes about 250 cycles. When it’s done, the Flash Accelerator will be granted access to the flash. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Figure 5 shows an example of the relationship between the RESET, the IRC, and the processor status when the LPC176x/5x starts up after reset. See Section 4.3.2 “Main oscillator” for start-up of the main oscillator if selected by the user code. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 20 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control IRC status IRC starts IRC stable RESET VDD(REG)(3V3) valid threshold GND supply ramp-up time processor status 60 μs Fig 5. Example of start-up after reset 1 μs; IRC stability count boot time 7 μs 181 μs 224 μs user code flash read starts flash read finishes boot code execution finishes; user code starts UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 21 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below. Table 8. Reset Source Identification register (RSID - address 0x400F C180) bit description Bit Symbol Description Reset value 0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in See this register. But if another Reset signal (e.g., External Reset) remains text asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. 1 EXTR Assertion of the RESET signal sets this bit. This bit is cleared only by See software or POR. text 2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit See in the Watchdog Mode Register is 1. This bit is cleared only by software or text POR. 3 BODR This bit is set when the VDD(REG)(3V3) voltage reaches a level below the See BOD reset trip level (typically 1.85 V under nominal room temperature text conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. 31:4 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 22 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.5 Brown-out detection The LPC176x/5x includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the Raw Interrupt Status Register. The second stage of low-voltage detection asserts Reset to inactivate the LPC176x/5x when the voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the Power-On Reset circuitry maintains the overall Reset. Both the BOD reset interrupt level and the BOD reset trip level thresholds include some hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level detection to reliably interrupt, or a regularly-executed event loop to sense the condition. But when Brown-Out Detection is enabled to bring the LPC176x/5x out of Power-down mode (which is itself not a guaranteed operation -- see Section 4.8.7 “Power Mode Control register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before the wake-up timer has completed its delay. In this case, the net result of the transient BOD is that the part wakes up and continues operation after the instructions that set Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being 0. Since all other wake-up conditions have latching flags (see Section 3.6.2 “External Interrupt flag register (EXTINT - 0x400F C140)” and Section 27.6.2), a wake-up of this type, without any apparent cause, can be assumed to be a Brown-Out that has gone away. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 23 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.6 External interrupt inputs TheLPC176x/5x includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in Figure 6. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section 4.8.8 “Wake-up from Reduced Power Modes” for details. EINTi pin EXTPOLARi GLITCH FILTER EINTi interrupt enable S 1D Q EXTMODEi internal reset write to EXTINTi Fig 6. External interrupt logic EINTi to wakeup timer Interrupt flag (one bit of EXTINT) S Q R PCLK S Q R PCLK to interrupt controller APB read of EXTINTi 100621 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 24 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.6.1 Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters. Table 9. External Interrupt registers Name Description Access EXTINT The External Interrupt Flag Register contains R/W interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table 10. EXTMODE The External Interrupt Mode Register controls R/W whether each pin is edge- or level-sensitive. See Table 11. EXTPOLAR The External Interrupt Polarity Register controls R/W which level or edge on each pin will cause an interrupt. See Table 12. Reset Address value[1] 0x00 0x400F C140 0x00 0x400F C148 0x00 0x400F C14C [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 3.6.2 External Interrupt flag register (EXTINT - 0x400F C140) When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the NVIC, which will cause an interrupt if interrupts from the pin are enabled. Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive state. Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future. Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section 3.6.3 “External Interrupt Mode register (EXTMODE - 0x400F C148)” and Section 3.6.4 “External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”. For example, if a system wakes up from Power-down using low level on external interrupt 0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke Power-down mode will fail. The same goes for external interrupt handling. More details on Power-down mode will be discussed in the following chapters. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 25 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description Bit Symbol Description Reset value 0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for 0 its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for 0 its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for 0 its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for 0 its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 31:4 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. [1] Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 3.6.3 External Interrupt Mode register (EXTMODE - 0x400F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see Section 8.5) and enabled in the appropriate NVIC register) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the mode and not having the EXTINT cleared. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 26 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit description Bit Symbol Value Description 0 EXTMODE0 0 1 1 EXTMODE1 0 1 2 EXTMODE2 0 1 3 EXTMODE3 0 1 31:4 - - Level-sensitivity is selected for EINT0. EINT0 is edge sensitive. Level-sensitivity is selected for EINT1. EINT1 is edge sensitive. Level-sensitivity is selected for EINT2. EINT2 is edge sensitive. Level-sensitivity is selected for EINT3. EINT3 is edge sensitive. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 0 0 NA 3.6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C) In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are selected for the EINT function (see Section 8.5) and enabled in the appropriate NVIC register) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the polarity and not having the EXTINT cleared. Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Bit Symbol Value Description Reset value 0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on 0 EXTMODE0). 1 EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). 1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on 0 EXTMODE1). 1 EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). 2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on 0 EXTMODE2). 1 EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 27 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Bit Symbol Value Description Reset value 3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on 0 EXTMODE3). 1 EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). 31:4 - - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 28 of 849 NXP Semiconductors UM10360 Chapter 3: LPC176x/5x System control 3.7 Other system controls and status flags Some aspects of controlling LPC176x/5x operation that do not fit into peripheral or other registers are grouped here. 3.7.1 System Controls and Status register (SCS - 0x400F C1A0) The SCS register contains several control/status bits related to the main oscillator. Since chip operation always begins using the Internal RC Oscillator, and the main oscillator may not be used at all in some applications, it will only be started by software request. This is accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that software can determine when the oscillator is running and stable. At that point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. Table 13. System Controls and Status register (SCS - address 0x400F C1A0) bit description Bit Symbol Value Description Access Reset value 3:0 - - Reserved. User software should not write ones to - NA reserved bits. The value read from a reserved bit is not defined. 4 OSCRANGE Main oscillator range select. R/W 0 0 The frequency range of the main oscillator is 1 MHz to 20 MHz. 1 The frequency range of the main oscillator is 15 MHz to 25 MHz. 5 OSCEN Main oscillator enable. R/W 0 0 The main oscillator is disabled. 1 The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. 6 OSCSTAT Main oscillator status. RO 0 0 The main oscillator is not ready to be used as a clock source. 1 The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. 31:7 - - Reserved. User software should not write ones to - NA reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 29 of 849 UM10360 Chapter 4: LPC176x/5x Clocking and power control Rev. 3.1 — 2 April 2014 User manual 4.1 Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC176x/5x and options of clock source selection, as well as power control and wake-up from reduced power modes. Functions described in the following subsections include: • Oscillators • Clock source selection • PLLs • Clock dividers • APB dividers • Power control • Wake-up timer • External clock output osc_clk rtc_clk irc_osc PCLK_WDT USB PLL settings (PLL1...) USB PLL (PLL1) main PLL settings (PLL0...) CPU PLL select (PLL0CON) sysclk Main PLL (PLL0) ` system clock select CLKSRCSEL[1:0] watchdog clock select WDCLKSEL[1:0] USB PLL select (PLL1CON) USB Clock Divider usb_clk USB clock divider setting USBCLKCFG[3:0] pllclk CPU Clock cclk Divider CPU clock divider setting CCLKCFG[7:0] Peripheral Clock Divider pclk1 pclk2 pclk4 pclk8 wd_clk Fig 7. Clock generation for the LPC176x/5x UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 30 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.2 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 14. Summary of system control registers Name Description Clock source selection CLKSRCSEL Clock Source Select Register Phase Locked Loop (PLL0, Main PLL) PLL0CON PLL0 Control Register PLL0CFG PLL0 Configuration Register PLL0STAT PLL0 Status Register PLL0FEED PLL0 Feed Register Phase Locked Loop (PLL1, USB PLL) PLL1CON PLL1 Control Register PLL1CFG PLL1 Configuration Register PLL1STAT PLL1 Status Register PLL1FEED PLL1 Feed Register Clock dividers CCLKCFG CPU Clock Configuration Register USBCLKCFG USB Clock Configuration Register PCLKSEL0 Peripheral Clock Selection register 0. PCLKSEL1 Peripheral Clock Selection register 1. Power control PCON Power Control Register PCONP Power Control for Peripherals Register Utility CLKOUTCFG Clock Output Configuration Register Access Reset value Address R/W 0 0x400F C10C R/W 0 R/W 0 RO 0 WO NA 0x400F C080 0x400F C084 0x400F C088 0x400F C08C R/W 0 R/W 0 RO 0 WO NA 0x400F C0A0 0x400F C0A4 0x400F C0A8 0x400F C0AC R/W 0 R/W 0 R/W 0 R/W 0 0x400F C104 0x400F C108 0x400F C1A8 0x400F C1AC R/W 0 0x400F C0C0 R/W 0x03BE 0x400F C0C4 R/W 0 0x400F C1C8 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 31 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.3 Oscillators The LPC176x/5x includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in Figure 7. Following Reset, the LPC176x/5x will operate from the Internal RC Oscillator until switched by software. This allows systems to operate without any external crystal, and allows the boot loader code to operate at a known frequency. 4.3.1 Internal RC oscillator The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer, and/or as the clock that drives PLL0 and subsequently the CPU. The precision of the IRC does not allow for use of the USB interface, which requires a much more precise time base in order to comply with the USB specification. Also, the IRC should not be used with the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The nominal IRC frequency is 4 MHz. Upon power-up or any chip reset, the LPC176x/5x uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 4.3.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer to Section 4.5 “PLL0 (Phase Locked Loop 0)” for details. The on-board oscillator in the LPC176x/5x can operate in one of two modes: slave mode and oscillation mode. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (CC in Figure 8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms. This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 8, drawings b and c, and in Table 15 and Table 16. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 8, drawing c, represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 32 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control LPC17xx XTAL1 XTAL2 CC Clock LPC17xx XTAL1 XTAL2 Xtal CX1 CX2 <=> L CL CP RS a) b) c) Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for CX1/X2 evaluation Table 15. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode (OSCRANGE = 0, see Table 13) Fundamental oscillation frequency FOSC 1 MHz to 5 MHz Crystal load capacitance CL 10 pF Maximum crystal series resistance RS < 300  External load capacitors CX1, CX2 18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 16. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) high frequency mode (OSCRANGE = 1, see Table 13) Fundamental oscillation frequency FOSC 15 MHz to 20 MHz Crystal load capacitance CL 10 pF Maximum crystal series resistance RS < 180  External load capacitors CX1, CX2 18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF Since chip operation always begins using the Internal RC Oscillator, and the main oscillator may not be used at all in some applications, it will only be started by software request. This is accomplished by setting the OSCEN bit in the SCS register, as described in Table 13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that software can determine when the oscillator is running and stable. At that UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 33 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. 4.3.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be used as the clock source for PLL0 and CPU and/or the watchdog timer. Remark: The RTC oscillator must not be used as a clock source when the PLL0 output is selected to drive the USB controller. In this case select the main oscillator as clock source for PLL0 (see also Table 17). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 34 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.4 Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator. The clock source selection can only be changed safely when PLL0 is not connected. For a detailed description of how to change the clock source in a system using PLL0 see Section 4.5.13 “PLL0 setup sequence”. Note the following restrictions regarding the choice of clock sources: • Only the main oscillator must be used (via PLL0) as the clock source for the USB subsystem. The IRC or RTC oscillators do not provide the proper tolerances for this use. • The IRC oscillator should not be used (via PLL0) as the clock source for the CAN controllers if the CAN baud rate is higher than 100 kbit/s. 4.4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C) The CLKSRCSEL register contains the bits that select the clock source for PLL0. Table 17. Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit description Bit Symbol Value Description Reset value 1:0 CLKSRC Selects the clock source for PLL0 as follows: 0 00 Selects the Internal RC oscillator as the PLL0 clock source (default). 01 Selects the main oscillator as the PLL0 clock source. Remark: Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s. 10 Selects the RTC oscillator as the PLL0 clock source. 11 Reserved, do not use this setting. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. 31:2 - 0 Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 35 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.5 PLL0 (Phase Locked Loop 0) PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock source is selected in the CLKSRCSEL register (see Section 4.4). The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem has its own dedicated PLL (see Section 4.6). PLL0 can produce a clock up to the maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and LPC1759), and 100 MHz on other versions. 4.5.1 PLL0 operation The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value "N", which may be in the range of 1 to 256. This input division provides a greater number of possibilities in providing a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the range of 6 through 512, plus additional values listed in Table 21. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. There are additional dividers at the output of PLL0 to bring the frequency down to what is needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output dividers are described in the Clock Dividers section following the PLL0 description. A block diagram of PLL0 is shown in Figure 9 PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values are controlled by the PLL0CFG register. These two registers are protected in order to prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, could be dependent on PLL0 if so configured (for example when it is providing the chip clock), accidental changes to the PLL0 setup values could result in unexpected or fatal behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLL0FEED register. PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 must be configured, enabled, and connected to the system by software. It is important that the setup procedure described in Section 4.5.13 “PLL0 setup sequence” is followed or PLL0 might not operate at all! 4.5.1.1 PLL0 and startup/boot code interaction When there is no valid user code (determined by the checksum word) in the user flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is disabled when the user opens a debug session to debug the application code. The user startup code must follow the steps described in this chapter to disconnect the PLL. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 36 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.5.2 PLL0 register description PLL0 is controlled by the registers shown in Table 18. More detailed descriptions follow. Warning: Improper setting of PLL0 values may result in incorrect operation of the device! Table 18. PLL0 registers Name Description Access Reset Address value[1] PLL0CON PLL0 Control Register. Holding register for R/W 0 updating PLL0 control bits. Values written to this register do not take effect until a valid PLL0 feed sequence has taken place. 0x400F C080 PLL0CFG PLL0 Configuration Register. Holding register for R/W 0 updating PLL0 configuration values. Values written to this register do not take effect until a valid PLL0 feed sequence has taken place. 0x400F C084 PLL0STAT PLL0 Status Register. Read-back register for RO 0 PLL0 control and configuration information. If PLL0CON or PLL0CFG have been written to, but a PLL0 feed sequence has not yet occurred, they will not reflect the current PLL0 state. Reading this register provides the actual values controlling the PLL0, as well as the PLL0 status. 0x400F C088 PLL0FEED PLL0 Feed Register. This register enables WO NA loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG registers into the shadow registers that actually affect PLL0 operation. 0x400F C08C [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. PLLC PLLE pd pllclkin NSEL [7:0] MSEL [14:0] N-DIVIDER PLOCK refclk PHASEFREQUENCY DETECTOR FILTER CCO M-DIVIDER /2 pllclk Fig 9. PLL0 block diagram 4.5.3 PLL0 Control register (PLL0CON - 0x400F C080) The PLL0CON register contains the bits that enable and connect PLL0. Enabling PLL0 allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting PLL0 causes the processor and most chip functions to run from the PLL0 output clock. Changes to the PLL0CON register do not take effect until a correct PLL0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 37 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description Bit Symbol Description Reset value 0 PLLE0 PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate 0 PLL0 and allow it to lock to the requested frequency. See PLL0STAT register, Table 22. 1 PLLC0 PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and 0 locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register, Table 22. 31:2 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. PLL0 must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL0 output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardware does not insure that PLL0 is locked before it is connected or automatically disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is likely that the oscillator clock has become unstable and disconnecting PLL0 will not remedy the situation. 4.5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084) The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the PLL0CFG register do not take effect until a correct PLL feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Calculations for the PLL frequency, and multiplier and divider values are found in the Section 4.5.10 “PLL0 frequency calculation”. Table 20. PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description Bit Symbol Description Reset value 14:0 MSEL0 PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency 0 calculations. The value stored here is M - 1. Supported values for M are 6 through 512 and those listed in Table 21. Note: Not all values of M are needed, and therefore some are not supported by hardware. For details on selecting values for MSEL0 see Section 4.5.10 “PLL0 frequency calculation”. 15 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. 23:16 NSEL0 PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency 0 calculations. The value stored here is N - 1. Supported values for N are 1 through 32. Note: For details on selecting the right value for NSEL0 see Section 4.5.10 “PLL0 frequency calculation”. 31:24 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 38 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 21. Multiplier values for PLL0 with a 32 kHz input Multiplier Pre-divide FCCO (M) (N) Multiplier (M) 4272 1 279.9698 12085 4395 1 288.0307 12207 4578 1 300.0238 12817 4725 1 309.6576 12817 4807 1 315.0316 13184 5127 1 336.0031 13184 5188 1 340.0008 13672 5400 1 353.8944 13733 5493 1 359.9892 13733 5859 1 383.9754 13916 6042 1 395.9685 14099 6075 1 398.1312 14420 6104 1 400.0317 14648 6409 1 420.0202 15381 6592 1 432.0133 15381 6750 1 442.3680 15564 6836 1 448.0041 15625 6866 1 449.9702 15869 6958 1 455.9995 16113 7050 1 462.0288 16479 7324 1 479.9857 17578 7425 1 486.6048 18127 7690 1 503.9718 18311 7813 1 512.0328 19226 7935 1 520.0282 19775 8057 1 528.0236 20508 8100 1 530.8416 20599 8545 2 280.0026 20874 8789 2 287.9980 21149 9155 2 299.9910 21973 9613 2 314.9988 23071 10254 2 336.0031 23438 10376 2 340.0008 23804 10986 2 359.9892 24170 11719 2 384.0082 Pre-divide FCCO (N) 2 396.0013 2 399.9990 2 419.9875 3 279.9916 2 432.0133 3 288.0089 2 448.0041 2 450.0029 3 300.0020 2 455.9995 2 461.9960 3 315.0097 2 479.9857 2 504.0046 3 336.0031 3 340.0008 2 512.0000 2 519.9954 2 527.9908 3 359.9892 3 383.9973 3 395.9904 3 400.0099 3 419.9984 3 431.9915 3 448.0041 3 449.9920 3 455.9995 3 462.0070 3 480.0075 3 503.9937 3 512.0109 3 520.0063 3 528.0017 4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088) The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in PLL0CON and PLL0CFG because changes to those registers do not take effect until a UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 39 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control proper PLL0 feed has occurred (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 22. PLL Status register (PLL0STAT - address 0x400F C088) bit description Bit Symbol Description Reset value 14:0 MSEL0 Read-back for the PLL0 Multiplier value. This is the value currently 0 used by PLL0, and is one less than the actual multiplier. 15 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 23:16 NSEL0 Read-back for the PLL0 Pre-Divider value. This is the value 0 currently used by PLL0, and is one less than the actual divider. 24 PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the 0 PLEC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. 25 PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of 0 the PLLC0 bit in PLL0CON (see Table 19) after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. 26 PLOCK0 Reflects the PLL0 Lock status. When zero, PLL0 is not locked. 0 When one, PLL0 is locked onto the requested frequency. See text for details. 31:27 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 4.5.6 PLL0 Interrupt: PLOCK0 The PLOCK0 bit in the PLL0STAT register reflects the lock status of PLL0. When PLL0 is enabled, or parameters are changed, PLL0 requires some time to establish lock under the new conditions. PLOCK0 can be monitored to determine when PLL0 may be connected for use. The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 s when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0 and continue with other functions without having to wait for PLL0 to achieve lock. When the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0 appears as interrupt 32 in Table 50. Note that PLOCK0 remains asserted whenever PLL0 is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK0 interrupt prior to exiting. 4.5.7 PLL0 Modes The combinations of PLLE0 and PLLC0 are shown in Table 23. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 40 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 23. PLL control bit combinations PLLC0 PLLE0 PLL Function 0 0 PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. 0 1 PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is asserted. 1 0 Same as 00 combination. This prevents the possibility of PLL0 being connected without also being enabled. 1 1 PLL0 is active and has been connected as the system clock source. 4.5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C) A correct feed sequence must be written to the PLL0FEED register in order for changes to the PLL0CON and PLL0CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL0FEED. 2. Write the value 0x55 to PLL0FEED. The two writes must be in the correct sequence, and there must be no other register access in the same address space (0x400F C000 to 0x400F FFFF) between them. Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed operation, if there is a possibility that an interrupt service routine could write to another register in that space. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will not become effective. Table 24. PLL Feed register (PLL0FEED - address 0x400F C08C) bit description Bit Symbol Description 7:0 PLL0FEED The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x00 NA 4.5.9 PLL0 and Power-down mode Power-down mode automatically turns off and disconnects PLL0. Wake-up from Power-down mode does not automatically restore PLL0 settings, this must be done in software. Typically, a routine to activate PLL0, wait for lock, and then connect PLL0 can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart PLL0 by simply feeding it when execution resumes after a wake-up from Power-down mode. This would enable and connect PLL0 at the same time, before PLL lock is established. 4.5.10 PLL0 frequency calculation PLL0 equations use the following parameters: UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 41 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 25. PLL frequency parameter Parameter Description FIN FCCO N the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator) PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer from 1 through 32. M PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG MSEL0 field + 1). Not all potential values are supported. See below. FREF PLL internal reference frequency, FIN divided by N. The PLL0 output frequency (when PLL0 is both active and connected) is given by: FCCO = (2  M  FIN) / N PLL inputs and settings must meet the following: • FIN is in the range of 32 kHz to 50 MHz. • FCCO is in the range of 275 MHz to 550 MHz. The equation can be solved for other PLL parameters: M = (FCCO  N) / (2  FIN) N = (2  M  FIN) / FCCO FIN = (FCCO  N) / (2  M) Allowed values for M: At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are allowed. This supports the entire useful range of both the main oscillator and the IRC. For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65 additional M values have been selected for supporting baud rate generation, CAN operation, and obtaining integer MHz frequencies. These values are shown in Table 26. Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input Low Frequency PLL Multipliers 4272 4395 4578 4725 4807 5127 5188 5400 5493 5859 6042 6075 6104 6409 6592 6750 6836 6866 6958 7050 7324 7425 7690 7813 7935 8057 8100 8545 8789 9155 9613 10254 10376 10986 11719 12085 12207 12817 13184 13672 13733 13916 14099 14420 14648 15381 15564 15625 15869 16113 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 42 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input Low Frequency PLL Multipliers 16479 17578 18127 18311 19226 19775 20508 20599 20874 21149 21973 23071 23438 23804 24170 4.5.11 Procedure for determining PLL0 settings PLL0 parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL0 parameters by hand, the following general procedure may be used: 1. Determine if the application requires use of the USB interface, and whether it will be clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very small tolerance, which means that FCCO must be an even integer multiple of 48 MHz (i.e. an integer multiple of 96 MHz), within a very small tolerance. 2. Choose the desired processor operating frequency (CCLK). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc. Bear in mind that peripheral devices may be running from a lower clock frequency than that of the processor (see Section 4.7 “Clock dividers” on page 55 and Section 4.8 “Power control” on page 59). Find a value for FCCO that is close to a multiple of the desired CCLK frequency, bearing in mind the requirement for USB support in [1] above, and that lower values of FCCO result in lower power dissipation. 3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support, the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used to clock the USB subsystem, this affects the choice of the main oscillator frequency. 4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value -1 will be written to the NSEL0 field in PLL0CFG. In general, it is better to use a smaller value for N, to reduce the level of multiplication that must be accomplished by the CCO. Due to the difficulty in finding the best values in some cases, it is recommended to use a spreadsheet or similar method to show many possibilities at once, from which an overall best choice may be selected. A spreadsheet is available from NXP for this purpose. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 43 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.5.12 Examples of PLL0 settings The following table gives a summary of examples that illustrate selecting PLL0 values based on different system requirements. Table 27. Summary of PLL0 examples Example Description 1 • The PLL0 clock source is 10 MHz. • PLL0 is not used as the USB clock source, or the USB interface is not used. • The desired CPU clock is 100 MHz. 2 • The PLL0 clock source is 4 MHz. • PLL0 is used as the USB clock source. • The desired CPU clock is 60 MHz. 3 • The PLL0 clock source is the 32.768 kHz RTC clock. • PLL0 is not used as the USB clock source, or the USB interface is not used. • The desired CPU clock is 72 MHz. UM10360 User manual Example 1 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 100 MHz. • An external 10 MHz crystal or clock source will be used as the system clock source. Calculations: M = (FCCO  N) / (2  FIN) A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M), both result in better PLL operational stability and lower output jitter. Lower values of FCCO also save power. So, the process of determining PLL setup parameters involves looking for the smallest N and M values giving the lowest FCCO value that will support the required CPU and/or USB clocks. It is usually easier to work backward from the desired output clock rate and determine a target FCCO rate, then find a way to obtain that FCCO rate from the available input clock. Potential precise values of FCCO are integer multiples of the desired CPU clock. In this example, it is clear that the smallest frequency for FCCO that can produce the desired CPU clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz (3 ´ 100 MHz). Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives M = ((300 ´ 106 ´ 1) / (2  10 ´ 106) = 300 / 20 = 15. Since the result is an integer, there is no need to look any further for a good set of PLL0 configuration values. The value written to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4.7.1. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 44 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Example 2 Assumptions: • The USB interface will be used in the application and will be clocked from PLL0. • The desired CPU rate is 60 MHz. • An external 4 MHz crystal or clock source will be used as the system clock source. This clock source could be the Internal RC oscillator (IRC). Calculations: M = (FCCO  N) / (2  FIN) Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that need must be addressed first. Potential precise values of FCCO are integer multiples of the 2 ´ the 48 MHz USB clock. The 2 ´ insures that the clock has a 50% duty cycle, which would not be the case for a division of the PLL output by an odd number. The possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. The smallest frequency for FCCO that can produce a valid USB clock rate and is within the PLL0 operating range is 288 MHz (3 ´ 2 ´ 48 MHz). Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So, M = ((288 ´ 106) ´ 1) / (2  (4 ´ 106)) = 288 / 8 = 36. The result is an integer, which is necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23). The potential CPU clock rate can be determined by dividing FCCO by the desired CPU frequency: 288 ´ 106 / 60 ´ 106 = 4.8. The nearest integer value for the CPU Clock Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate. If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0 settings for 480 MHz are N = 1 and M = 60. The PLL output must be further divided in order to produce both the CPU clock and the USB clock. This is accomplished using separate dividers that are described later in this chapter. See Section 4.7.1 and Section 4.7.2. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 45 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control UM10360 User manual Example 3 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 72 MHz • The 32.768 kHz RTC clock source will be used as the system clock source Calculations: M = (FCCO  N) / (2  FIN) The smallest integer multiple of the desired CPU clock rate that is within the PLL0 operating range is 288 MHz (4 ´ 72 MHz). Using the equation above and assuming that N = 1, M = ((288 ´ 106) ´ 1) / (2  32,768) = 4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with this setting. Since this example is less obvious, it may be useful to make a table of possibilities for different values of N (see below). Table 28. Potential values for PLL example NM M Rounded FREF in Hz (FIN / N) 1 4394.53125 4395 32768 2 8789.0625 8789 16384 3 13183.59375 13184 10922.67 4 17578.125 17578 8192 5 21972.65625 21973 6553.6 FCCO in CCLK in MHz  Error MHz (FREF x (FCCO / 4) (CCLK-72) / 72 M) 288.0307 72.0077 0.0107 287.9980 71.9995 -0.0007 288.0089 72.0022 0.0031 287.9980 71.9995 -0.0007 288.0045 72.0011 0.0016 Beyond N = 5, the value of M is out of range or not supported, so the table stops at that point. In the third column of the table, the calculated M value is rounded to the nearest integer. If this results in CCLK being above the maximum operating frequency, it is allowed if it is not more than 1/2  above the maximum frequency. In general, larger values of FREF result in a more stable PLL when the input clock is a low frequency. Even the first table entry shows a very small error of just over 1 hundredth of a percent, or 107 parts per million (ppm). If that is not accurate enough in the application, the second case gives a much smaller error of 7 ppm. There are no allowed combinations that give a smaller error than that. Remember that when a frequency below about 1 MHz is used as the PLL0 clock source, not all multiplier values are available. As it turns out, all of the rounded M values found in Table 28 of this example are supported, which may be confirmed in Table 26. If PLL0 calculations suggest use of unsupported multiplier values, those values must be disregarded and other values examined to find the best fit. The value written to PLL0CFG for the second table entry would be 0x12254 (N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4.7.1. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 46 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.5.13 PLL0 setup sequence The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected. 2. Disable PLL0 with one feed sequence. 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired. 4. Write to the Clock Source Selection Control register to change the clock source if needed. 5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG can only be updated when PLL0 is disabled. 6. Enable PLL0 with one feed sequence. 7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do this before connecting PLL0. 8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register, or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz. 9. Connect PLL0 with one feed sequence. It is very important not to merge any steps above. For example, do not update the PLL0CFG and enable PLL0 simultaneously with the same feed sequence. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 47 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.6 PLL1 (Phase Locked Loop 1) PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0. PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is enabled and connected via the PLL1CON register (see Section 4.6.2), it is automatically selected to drive the USB subsystem (see Figure 7). PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values are controlled by the PLL1CFG register. These two registers are protected in order to prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLL1FEED register. PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up to the range of 48 MHz for the USB clock using a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB, the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while PLL1 is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A block diagram of PLL1 is shown in Figure 10. 4.6.1 PLL1 register description PLL1 is controlled by the registers shown in Table 29. More detailed descriptions follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Warning: Improper setting of PLL1 values may result in incorrect operation of the USB subsystem! Table 29. PLL1 registers Name Description Access Reset Address value[1] PLL1CON PLL1 Control Register. Holding register for R/W 0 updating PLL1 control bits. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place. 0x400F C0A0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 48 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 29. PLL1 registers Name Description Access Reset Address value[1] PLL1CFG PLL1 Configuration Register. Holding register R/W 0 for updating PLL1 configuration values. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place. 0x400F C0A4 PLL1STAT PLL1 Status Register. Read-back register for RO 0 PLL1 control and configuration information. If PLL1CON or PLL1CFG have been written to, but a PLL1 feed sequence has not yet occurred, they will not reflect the current PLL1 state. Reading this register provides the actual values controlling PLL1, as well as PLL1 status. 0x400F C0A8 PLL1FEED PLL1 Feed Register. This register enables WO NA loading of PLL1 control and configuration information from the PLL1CON and PLL1CFG registers into the shadow registers that actually affect PLL1 operation. 0x400F C0AC [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. PLL input clock PLOCK PLLSTAT[10] Phase Detector Divide by M CurrentControlled Oscillator Fcco Divide by 2P PSEL PLLSTAT[6:5] PLL output clock MSEL PLLSTAT[4:0] Fig 10. PLL1 block diagram 100416 4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0) The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1 allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes to the PLL1CON register do not take effect until a correct PLL feed sequence has been given (see Section 4.6.6 and Section 4.6.3). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 49 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description Bit Symbol Description 0 PLLE1 1 PLLC1 31:2 - PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. See PLL1STAT register, Table 32. PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register, Table 32. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 NA PLL1 must be set up, enabled, and lock established before it may be used as a clock source for the USB subsystem. The hardware does not insure that the PLL is locked before it is connected nor does it automatically disconnect the PLL if lock is lost during operation. 4.6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4) The PLL1CFG register contains the PLL1 multiplier and divider values. Changes to the PLL1CFG register do not take effect until a correct PLL1 feed sequence has been given (see Section 4.6.6). Calculations for the PLL1 frequency, and multiplier and divider values are found in Section 4.6.9. Table 31. PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description Bit Symbol Description Reset value 4:0 MSEL1 PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency 0 calculations. Note: For details on selecting the right value for MSEL1 see Section 4.6.8. 6:5 PSEL1 PLL1 Divider value. Supplies the value "P" in the PLL1 frequency 0 calculations. Note: For details on selecting the right value for PSEL1 see Section 4.6.8. 31:7 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. 4.6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8) The read-only PLL1STAT register provides the actual PLL1 parameters that are in effect at the time it is read, as well as the PLL1 status. PLL1STAT may disagree with values found in PLL1CON and PLL1CFG because changes to those registers do not take effect until a proper PLL1 feed has occurred (see Section 4.6.6 “PLL1 Feed register (PLL1FEED - 0x400F C0AC)”). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 50 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description Bit Symbol Description Reset value 4:0 MSEL1 Read-back for the PLL1 Multiplier value. This is the value currently 0 used by PLL1. 6:5 PSEL1 Read-back for the PLL1 Divider value. This is the value currently 0 used by PLL1. 7 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 8 PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently 0 activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. 9 PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are 0 both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. 10 PLOCK1 Reflects the PLL1 Lock status. When zero, PLL1 is not locked. 0 When one, PLL1 is locked onto the requested frequency. 31:11 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 4.6.4.1 PLL1 modes The combinations of PLLE1 and PLLC1 are shown in Table 33. Table 33. PLL1 control bit combinations PLLC1 PLLE1 PLL1 Function 0 0 PLL1 is turned off and disconnected. 0 1 PLL1 is active, but not yet connected. PLL1 can be connected after PLOCK1 is asserted. 1 0 Same as 00 combination. This prevents the possibility of PLL1 being connected without also being enabled. 1 1 PLL1 is active and has been connected. The clock for the USB subsystem is sourced from PLL1. 4.6.5 PLL1 Interrupt: PLOCK1 The PLOCK1 bit in the PLL1STAT register reflects the lock status of PLL1. When PLL1 is enabled, or parameters are changed, the PLL requires some time to establish lock under the new conditions. PLOCK1 can be monitored to determine when the PLL may be connected for use. PLOCK1 is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs, the PLL may be connected, and the interrupt disabled. PLOCK1 appears as interrupt 48 in Table 50. Note that PLOCK1 remains asserted whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK1 interrupt prior to exiting. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 51 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL1FEED. 2. Write the value 0x55 to PLL1FEED. The two writes must be in the correct sequence, and there must be no other register access in the same address space (0x400F C000 to 0x400F FFFF) between them. Because of this, it may be necessary to disable interrupts for the duration of the PLL feed operation, if there is a possibility that an interrupt service routine could write to another register in that space. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will not become effective. Table 34. PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description Bit Symbol Description 7:0 PLL1FEED The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x00 NA 4.6.7 PLL1 and Power-down mode Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up from Power-down mode does not automatically restore PLL settings, this must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart a PLL by simply feeding it when execution resumes after a wake-up from Power-down mode. This would enable and connect the PLL at the same time, before PLL lock is established. If activity on the USB data lines is not selected to wake the microcontroller from Power-down mode (see Section 4.8.8 for details of wake up from reduced modes), both the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and disconnected when Power-down mode is invoked, as described above. However, if the USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 192 for a description of USB_NEED_CLK), it is not possible to go into Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the current state. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 52 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.6.8 PLL1 frequency calculation The PLL1 equations use the following parameters: Table 35. Element FOSC FCCO USBCLK M P Elements determining PLL frequency Description the frequency from the crystal oscillator the frequency of the PLL1 current controlled oscillator the PLL1 output frequency (48 MHz for USB) PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register PLL1 Divider value from the PSEL1 bits in the PLL1CFG register The PLL1 output frequency (when the PLL is both active and connected) is given by: USBCLK = M  FOSC or USBCLK = FCCO / (2  P) The CCO frequency can be computed as: FCCO = USBCLK  2  P or FCCO = FOSC ´ M  2  P The PLL1 inputs and settings must meet the following criteria: • FOSC is in the range of 10 MHz to 25 MHz. • USBCLK is 48 MHz. • FCCO is in the range of 156 MHz to 320 MHz. 4.6.9 Procedure for determining PLL1 settings The PLL1 configuration for USB may be determined as follows: 1. The desired PLL1 output frequency is USBCLK = 48 MHz. 2. Choose an oscillator frequency (FOSC). USBCLK must be the whole (non-fractional) multiple of FOSC meaning that the possible values for FOSC are 12 MHz, 16 MHz, and 24 MHz. 3. Calculate the value of M to configure the MSEL1 bits. M = USBCLK / FOSC. In this case, the possible values for M = 2, 3, or 4 (FOSC = 24 MHz, 16 MHz, or 12 MHz). The value written to the MSEL1 bits in PLL1CFG is M - 1 (see Table 37). 4. Find a value for P to configure the PSEL1 bits, such that FCCO is within its defined frequency limits of 156 MHz to 320 MHz. FCCO is calculated using FCCO = USBCLK  2  P. It follows that P = 2 is the only P value to yield FCCO in the allowed range. The value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see Table 36). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 53 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 36. PLL1 Divider values Values allowed for using PLL1 with USB are highlighted. PSEL1 Bits (PLL1CFG bits [6:5]) 00 01 10 11 Table 37. PLL1 Multiplier values Values allowed for using PLL1 with USB are highlighted. MSEL1 Bits (PLL1CFG bits [4:0]) 00000 00001 00010 00011 ... 11110 11111 Value of P 1 2 4 8 Value of M 1 2 3 4 ... 31 32 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 54 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.7 Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4.6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation. USB PLL settings (PLL1...) osc_clk USB PLL (PLL1) main PLL settings (PLL0...) CPU PLL select (PLL0CON) sysclk Main PLL (PLL0) pllclk USB PLL select (PLL1CON) USB Clock Divider USB clock divider setting USBCLKCFG[3:0] CPU Clock Divider usb_clk cclk CPU clock divider setting CCLKCFG[7:0] Fig 11. PLLs and clock dividers 4.7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104) The CCLKCFG register controls the division of the PLL0 output before it is used by the CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the output must be divided in order to bring the CPU clock frequency (CCLK) within operating limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low rate for temporary power savings without turning off PLL0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 55 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit description Bit Symbol Value Description Reset value 7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) 0x00 from the PLL0 output. 0 pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 pllclk is divided by 3 to produce the CPU clock. 3 pllclk is divided by 4 to produce the CPU clock. 4 pllclk is divided by 5 to produce the CPU clock. : : 255 pllclk is divided by 256 to produce the CPU clock. 31:8 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having CCLKSEL = 2 results in CCLK being one third of the PLL0 output, CCLKSEL = 3 results in CCLK being one quarter of the PLL0 output, etc. 4.7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108) This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the USB clock divider. The USBCLKCFG register controls the division of the PLL0 output before it is used by the USB subsystem.The PLL0 output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range. Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is using PLL0 as a clock source because a more precise clock is needed for USB specification compliance (see Table 17). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 56 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit description Bit Symbol Value Description Reset value 3:0 USBSEL Selects the divide value for creating the USB clock from the 0 PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 PLL0 output is divided by 10. PLL0 output must be 480 MHz. 31:4 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. 4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 0x400F C1A8 and PCLKSEL1 - 0x400F C1AC) A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal that will be supplied to the corresponding peripheral as specified in Table 40, Table 41 and Table 42. Remark: The peripheral clock for the RTC block is fixed at CCLK/8. Table 40. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit description Bit Symbol Description Reset value 1:0 PCLK_WDT Peripheral clock selection for WDT. 00 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00 11:10 - Reserved. NA 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00 15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00 17:16 PCLK_SPI Peripheral clock selection for SPI. 00 19:18 - Reserved. NA 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00 23:22 PCLK_DAC Peripheral clock selection for DAC. 00 25:24 PCLK_ADC Peripheral clock selection for ADC. 00 27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00 29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering.[1] 00 [1] PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 57 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 41. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit description Bit Symbol Description Reset value 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder 00 Interface. 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00 9:8 - Reserved. NA 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00 21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00 23:22 PCLK_I2S Peripheral clock selection for I2S. 00 25:24 - Reserved. NA 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM. 00 Table 42. Peripheral Clock Selection register bit values PCLKSEL0 and PCLKSEL1 Function individual peripheral’s clock select options Reset value 00 PCLK_peripheral = CCLK/4 00 01 PCLK_peripheral = CCLK 10 PCLK_peripheral = CCLK/2 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 58 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.8 Power control The LPC176x/5x supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Entry to any reduced power mode begins with the execution of either a WFI (Wait For Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3 internally supports two reduced power modes: Sleep and Deep Sleep. These are selected by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep Power-down modes are selected by bits in the PCON register. See Table 44. The same register contains flags that indicate whether entry into each reduced power mode actually occurred. The LPC176x/5x also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the Real Time Clock. Reduced power modes have some limitation during debug, see Section 33.5 for more information. 4.8.1 Sleep mode Note: Sleep mode on the LPC176x/5x corresponds to the Idle mode on LPC2xxx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC176x/5x documentation uses the Cortex-M3 terminology where applicable. When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in PCON is set, see Table 44.Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The GPDMA may operate in Sleep mode to access AHB SRAMs and peripherals with GPDMA support, but the GPDMA cannot access the flash memory or the main SRAM, which are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. UM10360 User manual 4.8.2 Deep Sleep mode Note: Deep Sleep mode on the LPC176x/5x corresponds to the Sleep mode on LPC23xx and LPC24xx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC176x/5x documentation uses the Cortex-M3 terminology where applicable. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 59 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 44. The IRC remains running and can be configured to drive the Watchdog Timer, allowing the Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC interrupts may be used as a wake-up source. The flash is left in the standby mode allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep Sleep mode and the logic levels of chip pins remain static. The Deep Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power consumption to a very low value. On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities will resume after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main oscillator timer starts counting and the code execution will resume when the timer expires (4096 cycles). The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a Watchdog Timer time out, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. 4.8.3 Power-down mode Power-down mode does everything that Deep Sleep mode does, but also turns off the flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see Table 44. This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. Upon wake-up from Power-down mode, if the IRC was used before entering Power-down mode, after IRC-start-up time (about 60 s), the 2-bit IRC timer starts counting and expiring in 4 cycles. Code execution can then be resumed immediately following the expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash wake-up timer measures flash start-up time of about 100 s. When it times out, access to the flash is enabled. The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 60 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.8.4 Deep Power-down mode In Deep Power-down mode, power is shut off to the entire chip with the exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 44. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins after entering Deep Power-down mode.Power to the on-chip regulator must be restored before device operation can be restarted. Wake-up from Deep Power-down mode will occur when an external reset signal is applied, or the RTC interrupt is enabled and an RTC interrupt is generated. 4.8.5 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. This is detailed in the description of the PCONP register. 4.8.6 Register description The Power Control function uses registers shown in Table 43. More detailed descriptions follow. Table 43. Power Control registers Name Description PCON PCONP Power Control Register. This register contains control bits that enable some reduced power operating modes of the LPC176x/5x. See Table 44. Power Control for Peripherals Register. This register contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed. Access Reset value[1] R/W 0x00 R/W Address 0x400F C0C0 0x400F C0C4 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 61 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table 44. Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description Bit Symbol Description Reset value 0 PM0 Power mode control bit 0. This bit controls entry to the Power-down 0 mode. See Section 4.8.7.1 below for details. 1 PM1 Power mode control bit 1. This bit controls entry to the Deep 0 Power-down mode. See Section 4.8.7.1 below for details. 2 BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the 0 Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. 3 BOGD[1] Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect 0 circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit. 4 BORD Brown-Out Reset Disable. When BORD is 1, the BOD will not reset 0 the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.5 for details of Brown-Out detection. 7:3 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. 8 SMFLAG Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. 0 [2][3] 9 DSFLAG Deep Sleep entry flag. Set when the Deep Sleep mode is successfully 0 [2][3] entered. Cleared by software writing a one to this bit. 10 PDFLAG Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. 0 [2][3] 11 DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode 0 [2][4] is successfully entered. Cleared by software writing a one to this bit. 31:12 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. [1] BOD reset (BORD- bit 4 in PCON register) and BOD interrupt needs to be disabled before a user disables or enables the power to BOD (BOGD - bit 3 in PCON register). [2] Only one of these flags will be valid at a specific time. [3] Hardware reset only for a power-up of core power or by a brownout detect event. [4] Hardware reset only for a power-up event on Vbat. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 62 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes. Table 45 below shows the encoding for the three reduced power modes supported by the LPC176x/5x. Table 45. Encoding of reduced power modes PM1, PM0 Description 00 Execution of WFI or WFE enters either Sleep or Deep Sleep mode as defined by the SLEEPDEEP bit in the Cortex-M3 System Control Register. 01 Execution of WFI or WFE enters Power-down mode if the SLEEPDEEP bit in the Cortex-M3 System Control Register is 1. 10 Reserved, this setting should not be used. 11 Execution of WFI or WFE enters Deep Power-down mode if the SLEEPDEEP bit in the Cortex-M3 System Control Register is 1. 4.8.8 Wake-up from Reduced Power Modes Any enabled interrupt can wake up the CPU from Sleep mode. Certain interrupts can wake up the processor if it is in either Deep Sleep mode or Power-down mode. Interrupts that can occur during Deep Sleep or Power-down mode will wake up the CPU if the interrupt is enabled. After wake-up, execution will continue to the appropriate interrupt service routine. These interrupts are NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN Activity Interrupt, and USB Activity Interrupt. In addition, the watchdog timer can wake up the part from Deep Sleep mode if the watchdog timer is being clocked by the IRC oscillator. For the wake-up process to take place the corresponding interrupt must be enabled in the NVIC. For pin-related peripheral functions, the related functions must also be mapped to pins. The CAN Activity Interrupt is generated by activity on the CAN bus pins, and the USB Activity Interrupt is generated by activity on the USB bus pins. These interrupts are only useful to wake up the CPU when it is on Deep Sleep or Power-down mode, when the peripheral functions are powered up, but not active. Typically, if these interrupts are used, their flags should be polled just before enabling the interrupt and entering the desired reduced power mode. This can save time and power by avoiding an immediate wake-up. Upon wake-up, the interrupt service can turn off the related activity interrupt, do any application specific setup, and exit to await a normal peripheral interrupt. In Deep Power-down mode, internal power to most of the device is removed, which limits the possibilities for waking up from this mode. Wake-up from Deep Power-down mode will occur when an external reset signal is applied, or the RTC interrupt is enabled and an RTC interrupt is generated. 4.8.9 Power Control for Peripherals register (PCONP - 0x400F C0C4) The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer, the Pin Connect block, and the System Control block). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 63 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control UM10360 User manual Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. Each bit in PCONP controls one peripheral as shown in Table 46. If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled. Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Bit Symbol Description Reset value 0- Reserved. NA 1 PCTIM0 Timer/Counter 0 power/clock control bit. 1 2 PCTIM1 Timer/Counter 1 power/clock control bit. 1 3 PCUART0 UART0 power/clock control bit. 1 4 PCUART1 UART1 power/clock control bit. 1 5- Reserved. NA 6 PCPWM1 PWM1 power/clock control bit. 1 7 PCI2C0 The I2C0 interface power/clock control bit. 1 8 PCSPI The SPI interface power/clock control bit. 1 9 PCRTC The RTC power/clock control bit. 1 10 PCSSP1 The SSP 1 interface power/clock control bit. 1 11 - Reserved. NA 12 PCADC A/D converter (ADC) power/clock control bit. 0 Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. 13 PCCAN1 CAN Controller 1 power/clock control bit. 0 14 PCCAN2 CAN Controller 2 power/clock control bit. 0 15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1 16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0 17 PCMCPWM Motor Control PWM 0 18 PCQEI Quadrature Encoder Interface power/clock control bit. 0 19 PCI2C1 The I2C1 interface power/clock control bit. 1 20 - Reserved. NA 21 PCSSP0 The SSP0 interface power/clock control bit. 1 22 PCTIM2 Timer 2 power/clock control bit. 0 23 PCTIM3 Timer 3 power/clock control bit. 0 24 PCUART2 UART 2 power/clock control bit. 0 25 PCUART3 UART 3 power/clock control bit. 0 26 PCI2C2 I2C interface 2 power/clock control bit. 1 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 64 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Bit Symbol Description Reset value 27 PCI2S I2S interface power/clock control bit. 0 28 - Reserved. NA 29 PCGPDMA GPDMA function power/clock control bit. 0 30 PCENET Ethernet block power/clock control bit. 0 31 PCUSB USB interface power/clock control bit. 0 Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register. See Section 8.5.2 “Pin Function Select Register 1 (PINSEL1 0x4002 C004)”. 4.8.10 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application might have to access the PCONP in order to start using some of the on-board peripherals. Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0. 4.8.11 Power domains The LPC176x/5x provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the Real Time Clock. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. Whenever the device core power is present, that power is used to operate the RTC, causing no power drain from a battery when main power is available. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 65 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.9 Wake-up timer The LPC176x/5x begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If the main oscillator or one or both PLLs are needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power-on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(REG)(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096), then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator is ready for use. Software can then switch to the main oscillator and start any required PLLs. Refer to the Main Oscillator description in this chapter for details. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 66 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control 4.10 External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 12. Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator (osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock (rtc_clk). CLKOUTCFG[3:0] cclk 000 osc_clk 001 irc_osc 010 usb_clk 011 rtc_clk 100 CLKOUTCFG[7:4] CLKOUT Divider CLKOUTCFG[8] Clock Enable CLKOUT Syncronizer CLKOUTCFG[9] Fig 12. CLKOUT selection 4.10.1 Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) The CLKOUTCFG register controls the selection of the internal clock that appears on the CLKOUT pin and allows dividing the clock by an integer value up to 16. The divider can be used to produce a system clock that is related to one of the on-chip clocks. For most clock sources, the division may be by 1. When the CPU clock is selected and is higher than approximately 50 MHz, the output must be divided in order to bring the frequency within the ability of the pin to switch with reasonable logic levels. Note: The CLKOUT multiplexer is designed to switch cleanly, without glitches, between the possible clock sources. The divider is also designed to allow changing the divide value without glitches. Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Bit Symbol Value Description Reset value 3:0 CLKOUTSEL Selects the clock source for the CLKOUT function. 0 0000 Selects the CPU clock as the CLKOUT source. 0001 Selects the main oscillator as the CLKOUT source. 0010 Selects the Internal RC oscillator as the CLKOUT source. 0011 Selects the USB clock as the CLKOUT source. 0100 Selects the RTC oscillator as the CLKOUT source. others Reserved, do not use these settings. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 67 of 849 NXP Semiconductors UM10360 Chapter 4: LPC176x/5x Clocking and power control Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Bit Symbol Value Description Reset value 7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0 0000 Clock is divided by 1. 0001 Clock is divided by 2. 0010 Clock is divided by 3. ... ... 1111 Clock is divided by 16. 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT 0 source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. 9 CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is 0 enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. 31:10 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 68 of 849 UM10360 Chapter 5: LPC176x/5x Flash accelerator Rev. 3.1 — 2 April 2014 User manual 5.1 Introduction The flash accelerator block in the LPC176x/5x allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power. The flash accelerator also provides speed and power improvements for data accesses to the flash memory. 5.2 Flash accelerator blocks The flash accelerator is divided into several functional blocks: • AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as well as by the General Purpose DMA Controller • An array of eight 128-bit buffers • Flash accelerator control logic, including address compare and flash control • A flash memory interface Figure 13 shows a simplified diagram of the flash accelerator blocks and data paths. Cortex-M3 CPU DCode bus ICode bus Bus Matrix Combined AHB Flash Accelerator AHB-Lite bus interface Buffer Array Flash Interface Flash Memory General Purpose DMA Controller DMA Master Port Flash Accelerator Control Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections In the following descriptions, the term “fetch” applies to an explicit flash read request from the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current processor fetch address. 5.2.1 Flash memory bank There is one bank of flash memory controlled by the LPC176x/5x flash accelerator. Flash programming operations are not controlled by the flash accelerator, but are handled as a separate function. A Boot ROM contains flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow programming of the flash memory. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 69 of 849 NXP Semiconductors UM10360 Chapter 5: LPC176x/5x Flash accelerator 5.2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation. Under some conditions, this delay could result in a Watchdog time-out. The user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the flash memory. In order to preclude the possibility of stale data being read from the flash memory, the LPC176x/5x flash accelerator buffers are automatically invalidated at the beginning of any flash programming or erase operation. Any subsequent read from a flash address will cause a new fetch to be initiated after the flash operation has completed. 5.3 Register description The flash accelerator is controlled by the register shown in Table 48. More detailed descriptions follow. Table 48. Summary of flash accelerator registers Name Description FLASHCFG Flash Accelerator Configuration Register. Controls flash access timing. See Table 49. Access Reset Address value[1] R/W 0x303A 0x400F C000 [1] Reset Value reflects the data stored in defined bits only. It does not include reserved bits content. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 70 of 849 NXP Semiconductors UM10360 Chapter 5: LPC176x/5x Flash accelerator 5.4 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000) Configuration bits select the flash access time, as shown in Table 49. The lower bits of FLASHCFG control internal flash accelerator functions and should not be altered. Following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks. Changing the FLASHCFG register value causes the flash accelerator to invalidate all of the holding latches, resulting in new reads of flash information as required. This guarantees synchronization of the flash accelerator to CPU operation. Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description Bit Symbol Value Description Reset value 11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used 0x3 for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. 0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. 0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. 0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices. 31:16 - Reserved. The value read from a reserved bit is not defined. NA 5.5 Operation Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will be needed in its latches in time to prevent CPU fetch stalls. The LPC176x/5x uses one bank of flash memory. The flash accelerator includes an array of eight 128-bit buffers to store both instructions and data in a configurable manner. Each 128-bit buffer in the array can include four 32-bit instructions, eight 16-bit instructions or some combination of the two. During sequential code execution, a buffer typically contains the current instruction and the entire flash line that contains that instruction, or one flash line of data containing a previously requested address. Buffers are marked according to how they are used (as instruction or data buffers), and when they have been accessed. This information is used to carry out the buffer replacement strategy. The Cortex-M3 provides a separate bus for instruction access (I-code) and data access (D-code) in the code memory space. These buses, plus the General Purpose DMA Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the flash memory’s address space is presented to the flash accelerator. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 71 of 849 NXP Semiconductors UM10360 Chapter 5: LPC176x/5x Flash accelerator If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not. When the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated. Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. Buffer replacement strategy in the flash accelerator attempts to maximize the chances that potentially reusable information is retained until it is needed again. If an attempt is made to write directly to the flash memory without using the normal flash programming interface (via Boot ROM function calls), the flash accelerator generates an error condition. The CPU treats this error as a data abort. The GPDMA handles error conditions as described in Section 31.4.1.6.3. When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the CPU is stalled for a shorter time since the required flash access is already in progress. Typically, a flash prefetch is begun whenever an access is made to a just prefetched address, or to a buffer whose immediate successor is not already in another buffer. A prefetch in progress may be aborted by a data access, in order to minimize CPU stalls. A prefetched flash line is latched within the flash memory, but the flash accelerator does not capture the line in a buffer until the CPU presents an address that is contained within the prefetched flash line. If the core presents an instruction address that is not already buffered and is not contained in the prefetched flash line, the prefetched line will be discarded. Some special cases include the possibility that the CPU will request a data access to an address already contained in an instruction buffer. In this case, the data will be read from the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction address that can be satisfied from an existing data buffer, causes the instruction to be supplied from the data buffer, and the buffer to be changed into an instruction buffer. This causes the buffer to be handled differently when the flash accelerator is determining which buffer is to be overwritten next. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 72 of 849 UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Rev. 3.1 — 2 April 2014 User manual 6.1 Features • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 • Tightly coupled interrupt controller provides low interrupt latency • Controls system exceptions and peripheral interrupts • In the LPC176x/5x, the NVIC supports 35 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt • Software interrupt generation 6.2 Description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. Refer to the Cortex-M3 User Guide Section 34.4.2 for details of NVIC operation. 6.3 Interrupt sources Table 50 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted. Exception numbers relate to where entries are stored in the exception vector table. Interrupt numbers are used in some other contexts, such as software interrupts. In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to operate from an external signal, the NMI function must be connected to the related device pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User Manual. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 73 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function ID Number Offset Flag(s) 0 16 0x40 WDT Watchdog Interrupt (WDINT) 1 17 0x44 Timer 0 Match 0 - 1 (MR0, MR1) Capture 0 - 1 (CR0, CR1) 2 18 0x48 Timer 1 Match 0 - 2 (MR0, MR1, MR2) Capture 0 - 1 (CR0, CR1) 3 19 0x4C Timer 2 Match 0-3 Capture 0-1 4 20 0x50 Timer 3 Match 0-3 Capture 0-1 5 21 0x54 UART0 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 6 22 0x58 UART1 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Control Change End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 7 23 0x5C UART 2 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 8 24 0x60 UART 3 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 9 25 0x64 PWM1 Match 0 - 6 of PWM1 Capture 0-1 of PWM1 10 26 0x68 I2C0 SI (state change) 11 27 0x6C I2C1 SI (state change) 12 28 0x70 I2C2 SI (state change) 13 29 0x74 SPI SPI Interrupt Flag (SPIF) Mode Fault (MODF) UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 74 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function ID Number Offset Flag(s) 14 30 0x78 SSP0 Tx FIFO half empty of SSP0 Rx FIFO half full of SSP0 Rx Timeout of SSP0 Rx Overrun of SSP0 15 31 0x7C SSP 1 Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun 16 32 0x80 PLL0 (Main PLL) PLL0 Lock (PLOCK0) 17 33 0x84 RTC Counter Increment (RTCCIF) Alarm (RTCALF) 18 34 0x88 External Interrupt External Interrupt 0 (EINT0) 19 35 0x8C External Interrupt External Interrupt 1 (EINT1) 20 36 0x90 External Interrupt External Interrupt 2 (EINT2) 21 37 0x94 External Interrupt External Interrupt 3 (EINT3). Note: EINT3 channel is shared with GPIO interrupts 22 38 0x98 ADC A/D Converter end of conversion 23 39 0x9C BOD Brown Out detect 24 40 0xA0 USB USB_INT_REQ_LP, USB_INT_REQ_HP, USB_INT_REQ_DMA 25 41 0xA4 CAN CAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx, CAN 1 Rx 26 42 0xA8 GPDMA IntStatus of DMA channel 0, IntStatus of DMA channel 1 27 43 0xAC I2S irq, dmareq1, dmareq2 28 44 0xB0 Ethernet WakeupInt, SoftInt, TxDoneInt, TxFinishedInt, TxErrorInt, TxUnderrunInt, RxDoneInt, RxFinishedInt, RxErrorInt, RxOverrunInt. 29 45 0xB4 Repetitive Interrupt Timer RITINT 30 46 0xB8 Motor Control PWM IPER[2:0], IPW[2:0], ICAP[2:0], FES 31 47 0xBC Quadrature Encoder INX_Int, TIM_Int, VELC_Int, DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int, POS2_Int, REV_Int, POS0REV_Int, POS1REV_Int, POS2REV_Int 32 48 0xC0 PLL1 (USB PLL) PLL1 Lock (PLOCK1) 33 49 0xC4 USB Activity Interrupt USB_NEED_CLK 34 50 0xC8 CAN Activity Interrupt CAN1WAKE, CAN2WAKE UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 75 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.4 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table should be located on a 256 word (1024 byte) boundary to insure alignment on LPC176x/5x family devices. Refer to Section 34.4.3.5 of the Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature. ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code or SRAM. For simplicity, this bit can be thought as simply part of the address offset since the split between the “code” space and the “SRAM” space occurs at the location corresponding to bit 29 in a memory address. Examples: To place the vector table at the beginning of the “local” static RAM, starting at address 0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address 0x1000 0000 in the code space, since bit 29 of the VTOR equals 0. To place the vector table at the beginning of the AHB static RAM, starting at address 0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address 0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 76 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5 Register description The following table summarizes the registers in the NVIC as implemented in the LPC176x/5x. The Cortex-M3 User Guide Section 34.4.2 provides a functional description of the NVIC. Table 51. NVIC register map Name Description Access Reset value ISER0 to Interrupt Set-Enable Registers. These 2 registers allow enabling RW 0 ISER1 interrupts and reading back the interrupt enables for specific peripheral functions. ICER0 to Interrupt Clear-Enable Registers. These 2 registers allow disabling RW 0 ICER1 interrupts and reading back the interrupt enables for specific peripheral functions. ISPR0 to Interrupt Set-Pending Registers. These 2 registers allow changing RW 0 ISPR1 the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. ICPR0 to Interrupt Clear-Pending Registers. These 2 registers allow RW 0 ICPR1 changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. IABR0 to Interrupt Active Bit Registers. These 2 registers allow reading the RO 0 IABR1 current interrupt active state for specific peripheral functions. IPR0 to Interrupt Priority Registers. These 9 registers allow assigning a RW 0 IPR8 priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. STIR Software Trigger Interrupt Register. This register allows software to WO 0 generate an interrupt. Address ISER0 - 0xE000 E100 ISER1 - 0xE000 E104 ICER0 - 0xE000 E180 ICER1 - 0xE000 E184 ISPR0 - 0xE000 E200 ISPR1 - 0xE000 E204 ICPR0 - 0xE000 E280 ICPR1 - 0xE000 E284 IABR0 - 0xE000 E300 IABR1 - 0xE000 E304 IPR0 - 0xE000 E400 IPR1 - 0xE000 E404 IPR2 - 0xE000 E408 IPR3 - 0xE000 E40C IPR4 - 0xE000 E410 IPR5 - 0xE000 E414 IPR6 - 0xE000 E418 IPR7 - 0xE000 E41C IPR8 - 0xE000 E420 STIR - 0xE000 EF00 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 77 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1 register (Section 6.5.2). Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6.5.3 and Section 6.5.4). Table 52. Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) Bit Name Function 0 ISE_WDT Watchdog Timer Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ISE_TIMER0 Timer 0 Interrupt Enable. See functional description for bit 0. 2 ISE_TIMER1 Timer 1. Interrupt Enable. See functional description for bit 0. 3 ISE_TIMER2 Timer 2 Interrupt Enable. See functional description for bit 0. 4 ISE_TIMER3 Timer 3 Interrupt Enable. See functional description for bit 0. 5 ISE_UART0 UART0 Interrupt Enable. See functional description for bit 0. 6 ISE_UART1 UART1 Interrupt Enable. See functional description for bit 0. 7 ISE_UART2 UART2 Interrupt Enable. See functional description for bit 0. 8 ISE_UART3 UART3 Interrupt Enable. See functional description for bit 0. 9 ISE_PWM PWM1 Interrupt Enable. See functional description for bit 0. 10 ISE_I2C0 I2C0 Interrupt Enable. See functional description for bit 0. 11 ISE_I2C1 I2C1 Interrupt Enable. See functional description for bit 0. 12 ISE_I2C2 I2C2 Interrupt Enable. See functional description for bit 0. 13 ISE_SPI SPI Interrupt Enable. See functional description for bit 0. 14 ISE_SSP0 SSP0 Interrupt Enable. See functional description for bit 0. 15 ISE_SSP1 SSP1 Interrupt Enable. See functional description for bit 0. 16 ISE_PLL0 PLL0 (Main PLL) Interrupt Enable. See functional description for bit 0. 17 ISE_RTC Real Time Clock (RTC) Interrupt Enable. See functional description for bit 0. 18 ISE_EINT0 External Interrupt 0 Interrupt Enable. See functional description for bit 0. 19 ISE_EINT1 External Interrupt 1 Interrupt Enable. See functional description for bit 0. 20 ISE_EINT2 External Interrupt 2 Interrupt Enable. See functional description for bit 0. 21 ISE_EINT3 External Interrupt 3 Interrupt Enable. See functional description for bit 0. 22 ISE_ADC ADC Interrupt Enable. See functional description for bit 0. 23 ISE_BOD BOD Interrupt Enable. See functional description for bit 0. 24 ISE_USB USB Interrupt Enable. See functional description for bit 0. 25 ISE_CAN CAN Interrupt Enable. See functional description for bit 0. 26 ISE_DMA GPDMA Interrupt Enable. See functional description for bit 0. 27 ISE_I2S I2S Interrupt Enable. See functional description for bit 0. 28 ISE_ENET Ethernet Interrupt Enable. See functional description for bit 0. 29 ISE_RIT Repetitive Interrupt Timer Interrupt Enable. See functional description for bit 0. 30 ISE_MCPWM Motor Control PWM Interrupt Enable. See functional description for bit 0. 31 ISE_QEI Quadrature Encoder Interface Interrupt Enable. See functional description for bit 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 78 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6.5.3 and Section 6.5.4). Table 53. Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) Bit Name Function 0 ISE_PLL1 PLL1 (USB PLL) Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ISE_USBACT USB Activity Interrupt Enable. See functional description for bit 0. 2 ISE_CANACT CAN Activity Interrupt Enable. See functional description for bit 0. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 79 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section 6.5.4). Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6.5.1 and Section 6.5.2). Table 54. Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) Bit Name Function 0 ICE_WDT Watchdog Timer Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ICE_TIMER0 Timer 0 Interrupt Disable. See functional description for bit 0. 2 ICE_TIMER1 Timer 1. Interrupt Disable. See functional description for bit 0. 3 ICE_TIMER2 Timer 2 Interrupt Disable. See functional description for bit 0. 4 ICE_TIMER3 Timer 3 Interrupt Disable. See functional description for bit 0. 5 ICE_UART0 UART0 Interrupt Disable. See functional description for bit 0. 6 ICE_UART1 UART1 Interrupt Disable. See functional description for bit 0. 7 ICE_UART2 UART2 Interrupt Disable. See functional description for bit 0. 8 ICE_UART3 UART3 Interrupt Disable. See functional description for bit 0. 9 ICE_PWM PWM1 Interrupt Disable. See functional description for bit 0. 10 ICE_I2C0 I2C0 Interrupt Disable. See functional description for bit 0. 11 ICE_I2C1 I2C1 Interrupt Disable. See functional description for bit 0. 12 ICE_I2C2 I2C2 Interrupt Disable. See functional description for bit 0. 13 ICE_SPI SPI Interrupt Disable. See functional description for bit 0. 14 ICE_SSP0 SSP0 Interrupt Disable. See functional description for bit 0. 15 ICE_SSP1 SSP1 Interrupt Disable. See functional description for bit 0. 16 ICE_PLL0 PLL0 (Main PLL) Interrupt Disable. See functional description for bit 0. 17 ICE_RTC Real Time Clock (RTC) Interrupt Disable. See functional description for bit 0. 18 ICE_EINT0 External Interrupt 0 Interrupt Disable. See functional description for bit 0. 19 ICE_EINT1 External Interrupt 1 Interrupt Disable. See functional description for bit 0. 20 ICE_EINT2 External Interrupt 2 Interrupt Disable. See functional description for bit 0. 21 ICE_EINT3 External Interrupt 3 Interrupt Disable. See functional description for bit 0. 22 ICE_ADC ADC Interrupt Disable. See functional description for bit 0. 23 ICE_BOD BOD Interrupt Disable. See functional description for bit 0. 24 ICE_USB USB Interrupt Disable. See functional description for bit 0. 25 ICE_CAN CAN Interrupt Disable. See functional description for bit 0. 26 ICE_DMA GPDMA Interrupt Disable. See functional description for bit 0. 27 ICE_I2S I2S Interrupt Disable. See functional description for bit 0. 28 ICE_ENET Ethernet Interrupt Disable. See functional description for bit 0. 29 ICE_RIT Repetitive Interrupt Timer Interrupt Disable. See functional description for bit 0. 30 ICE_MCPWM Motor Control PWM Interrupt Disable. See functional description for bit 0. 31 ICE_QEI Quadrature Encoder Interface Interrupt Disable. See functional description for bit 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 80 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6.5.1 and Section 6.5.2). Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) Bit Name Function 0 ICE_PLL1 PLL1 (USB PLL) Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ICE_USBACT USB Activity Interrupt Disable. See functional description for bit 0. 2 ICE_CANACT CAN Activity Interrupt Disable. See functional description for bit 0. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 81 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register (Section 6.5.6). Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.7 and Section 6.5.8). Table 56. Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) Bit Name Function 0 ISP_WDT Watchdog Timer Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ISP_TIMER0 Timer 0 Interrupt Pending set. See functional description for bit 0. 2 ISP_TIMER1 Timer 1. Interrupt Pending set. See functional description for bit 0. 3 ISP_TIMER2 Timer 2 Interrupt Pending set. See functional description for bit 0. 4 ISP_TIMER3 Timer 3 Interrupt Pending set. See functional description for bit 0. 5 ISP_UART0 UART0 Interrupt Pending set. See functional description for bit 0. 6 ISP_UART1 UART1 Interrupt Pending set. See functional description for bit 0. 7 ISP_UART2 UART2 Interrupt Pending set. See functional description for bit 0. 8 ISP_UART3 UART3 Interrupt Pending set. See functional description for bit 0. 9 ISP_PWM PWM1 Interrupt Pending set. See functional description for bit 0. 10 ISP_I2C0 I2C0 Interrupt Pending set. See functional description for bit 0. 11 ISP_I2C1 I2C1 Interrupt Pending set. See functional description for bit 0. 12 ISP_I2C2 I2C2 Interrupt Pending set. See functional description for bit 0. 13 ISP_SPI SPI Interrupt Pending set. See functional description for bit 0. 14 ISP_SSP0 SSP0 Interrupt Pending set. See functional description for bit 0. 15 ISP_SSP1 SSP1 Interrupt Pending set. See functional description for bit 0. 16 ISP_PLL0 PLL0 (Main PLL) Interrupt Pending set. See functional description for bit 0. 17 ISP_RTC Real Time Clock (RTC) Interrupt Pending set. See functional description for bit 0. 18 ISP_EINT0 External Interrupt 0 Interrupt Pending set. See functional description for bit 0. 19 ISP_EINT1 External Interrupt 1 Interrupt Pending set. See functional description for bit 0. 20 ISP_EINT2 External Interrupt 2 Interrupt Pending set. See functional description for bit 0. 21 ISP_EINT3 External Interrupt 3 Interrupt Pending set. See functional description for bit 0. 22 ISP_ADC ADC Interrupt Pending set. See functional description for bit 0. 23 ISP_BOD BOD Interrupt Pending set. See functional description for bit 0. 24 ISP_USB USB Interrupt Pending set. See functional description for bit 0. 25 ISP_CAN CAN Interrupt Pending set. See functional description for bit 0. 26 ISP_DMA GPDMA Interrupt Pending set. See functional description for bit 0. 27 ISP_I2S I2S Interrupt Pending set. See functional description for bit 0. 28 ISP_ENET Ethernet Interrupt Pending set. See functional description for bit 0. 29 ISP_RIT Repetitive Interrupt Timer Interrupt Pending set. See functional description for bit 0. 30 ISP_MCPWM Motor Control PWM Interrupt Pending set. See functional description for bit 0. 31 ISP_QEI Quadrature Encoder Interface Interrupt Pending set. See functional description for bit 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 82 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.7 and Section 6.5.8). Table 57. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) Bit Name Function 0 ISP_PLL1 PLL1 (USB PLL) Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ISP_USBACT USB Activity Interrupt Pending set. See functional description for bit 0. 2 ISP_CANACT CAN Activity Interrupt Pending set. See functional description for bit 0. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 83 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register (Section 6.5.8). Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.5 and Section 6.5.6). Table 58. Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) Bit Name Function 0 ICP_WDT Watchdog Timer Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ICP_TIMER0 Timer 0 Interrupt Pending clear. See functional description for bit 0. 2 ICP_TIMER1 Timer 1. Interrupt Pending clear. See functional description for bit 0. 3 ICP_TIMER2 Timer 2 Interrupt Pending clear. See functional description for bit 0. 4 ICP_TIMER3 Timer 3 Interrupt Pending clear. See functional description for bit 0. 5 ICP_UART0 UART0 Interrupt Pending clear. See functional description for bit 0. 6 ICP_UART1 UART1 Interrupt Pending clear. See functional description for bit 0. 7 ICP_UART2 UART2 Interrupt Pending clear. See functional description for bit 0. 8 ICP_UART3 UART3 Interrupt Pending clear. See functional description for bit 0. 9 ICP_PWM PWM1 Interrupt Pending clear. See functional description for bit 0. 10 ICP_I2C0 I2C0 Interrupt Pending clear. See functional description for bit 0. 11 ICP_I2C1 I2C1 Interrupt Pending clear. See functional description for bit 0. 12 ICP_I2C2 I2C2 Interrupt Pending clear. See functional description for bit 0. 13 ICP_SPI SPI Interrupt Pending clear. See functional description for bit 0. 14 ICP_SSP0 SSP0 Interrupt Pending clear. See functional description for bit 0. 15 ICP_SSP1 SSP1 Interrupt Pending clear. See functional description for bit 0. 16 ICP_PLL0 PLL0 (Main PLL) Interrupt Pending clear. See functional description for bit 0. 17 ICP_RTC Real Time Clock (RTC) Interrupt Pending clear. See functional description for bit 0. 18 ICP_EINT0 External Interrupt 0 Interrupt Pending clear. See functional description for bit 0. 19 ICP_EINT1 External Interrupt 1 Interrupt Pending clear. See functional description for bit 0. 20 ICP_EINT2 External Interrupt 2 Interrupt Pending clear. See functional description for bit 0. 21 ICP_EINT3 External Interrupt 3 Interrupt Pending clear. See functional description for bit 0. 22 ICP_ADC ADC Interrupt Pending clear. See functional description for bit 0. 23 ICP_BOD BOD Interrupt Pending clear. See functional description for bit 0. 24 ICP_USB USB Interrupt Pending clear. See functional description for bit 0. 25 ICP_CAN CAN Interrupt Pending clear. See functional description for bit 0. 26 ICP_DMA GPDMA Interrupt Pending clear. See functional description for bit 0. 27 ICP_I2S I2S Interrupt Pending clear. See functional description for bit 0. 28 ICP_ENET Ethernet Interrupt Pending clear. See functional description for bit 0. 29 ICP_RIT Repetitive Interrupt Timer Interrupt Pending clear. See functional description for bit 0. 30 ICP_MCPWM Motor Control PWM Interrupt Pending clear. See functional description for bit 0. 31 ICP_QEI Quadrature Encoder Interface Interrupt Pending clear. See functional description for bit 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 84 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.5 and Section 6.5.6). Table 59. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) Bit Name Function 0 ICP_PLL1 PLL1 (USB PLL) Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ICP_USBACT USB Activity Interrupt Pending clear. See functional description for bit 0. 2 ICP_CANACT CAN Activity Interrupt Pending clear. See functional description for bit 0. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 85 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if they are enabled. The remaining interrupts can have their active state read via the IABR1 register (Section 6.5.10). Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) Bit Name Function 0 IAB_WDT Watchdog Timer Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 IAB_TIMER0 Timer 0 Interrupt Active. See functional description for bit 0. 2 IAB_TIMER1 Timer 1. Interrupt Active. See functional description for bit 0. 3 IAB_TIMER2 Timer 2 Interrupt Active. See functional description for bit 0. 4 IAB_TIMER3 Timer 3 Interrupt Active. See functional description for bit 0. 5 IAB_UART0 UART0 Interrupt Active. See functional description for bit 0. 6 IAB_UART1 UART1 Interrupt Active. See functional description for bit 0. 7 IAB_UART2 UART2 Interrupt Active. See functional description for bit 0. 8 IAB_UART3 UART3 Interrupt Active. See functional description for bit 0. 9 IAB_PWM PWM1 Interrupt Active. See functional description for bit 0. 10 IAB_I2C0 I2C0 Interrupt Active. See functional description for bit 0. 11 IAB_I2C1 I2C1 Interrupt Active. See functional description for bit 0. 12 IAB_I2C2 I2C2 Interrupt Active. See functional description for bit 0. 13 IAB_SPI SPI Interrupt Active. See functional description for bit 0. 14 IAB_SSP0 SSP0 Interrupt Active. See functional description for bit 0. 15 IAB_SSP1 SSP1 Interrupt Active. See functional description for bit 0. 16 IAB_PLL0 PLL0 (Main PLL) Interrupt Active. See functional description for bit 0. 17 IAB_RTC Real Time Clock (RTC) Interrupt Active. See functional description for bit 0. 18 IAB_EINT0 External Interrupt 0 Interrupt Active. See functional description for bit 0. 19 IAB_EINT1 External Interrupt 1 Interrupt Active. See functional description for bit 0. 20 IAB_EINT2 External Interrupt 2 Interrupt Active. See functional description for bit 0. 21 IAB_EINT3 External Interrupt 3 Interrupt Active. See functional description for bit 0. 22 IAB_ADC ADC Interrupt Active. See functional description for bit 0. 23 IAB_BOD BOD Interrupt Active. See functional description for bit 0. 24 IAB_USB USB Interrupt Active. See functional description for bit 0. 25 IAB_CAN CAN Interrupt Active. See functional description for bit 0. 26 IAB_DMA GPDMA Interrupt Active. See functional description for bit 0. 27 IAB_I2S I2S Interrupt Active. See functional description for bit 0. 28 IAB_ENET Ethernet Interrupt Active. See functional description for bit 0. 29 IAB_RIT Repetitive Interrupt Timer Interrupt Active. See functional description for bit 0. 30 IAB_MCPWM Motor Control PWM Interrupt Active. See functional description for bit 0. 31 IAB_QEI Quadrature Encoder Interface Interrupt Active. See functional description for bit 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 86 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if they are enabled. Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) Bit Name Function 0 IAB_PLL1 PLL1 (USB PLL) Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 IAB_USBACT USB Activity Interrupt Active. See functional description for bit 0. 2 IAB_CANACT CAN Activity Interrupt Active. See functional description for bit 0. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 87 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400) The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_WDT Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_TIMER0 Timer 0 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_TIMER1 Timer 1 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_TIMER2 Timer 2 Interrupt Priority. See functional description for bits 7-3. 6.5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404) The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000 E404) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_TIMER3 Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_UART0 UART0 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_UART1 UART1 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_UART2 UART2 Interrupt Priority. See functional description for bits 7-3. 6.5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408) The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000 E408) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_UART3 UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_PWM PWM Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_I2C0 I2C0 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_I2C1 I2C1 Interrupt Priority. See functional description for bits 7-3. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 88 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_I2C2 I2C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_SPI SPI Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_SSP0 SSP0 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_SSP1 SSP1 Interrupt Priority. See functional description for bits 7-3. 6.5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410) The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000 E410) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_PLL0 PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_RTC Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_EINT0 External Interrupt 0 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_EINT1 External Interrupt 1 Interrupt Priority. See functional description for bits 7-3. 6.5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414) The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_EINT2 External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_EINT3 External Interrupt 3 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_ADC ADC Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_BOD BOD Interrupt Priority. See functional description for bits 7-3. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 89 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418) The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_USB USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_CAN CAN Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_DMA GPDMA Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_I2S I2S Interrupt Priority. See functional description for bits 7-3. 6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_ENET Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_RIT Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_MCPWM Motor Control PWM Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_QEI Quadrature Encoder Interface Interrupt Priority. See functional description for bits 7-3. 6.5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420) The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000 E420) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_PLL1 PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_USBACT USB Activity Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_CANACT CAN Activity Interrupt Priority. See functional description for bits 7-3. 31:24 Unimplemented These bits ignore writes, and read as 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 90 of 849 NXP Semiconductors UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00) The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. By default, only privileged software can write to the STIR register. Unprivileged software can be given this ability if privileged software sets the USERSETMPEND bit in the CCR register (see Section 34.4.3.8). Table 71. Software Trigger Interrupt Register (STIR - 0xE000 EF00) Bit Name Function 8:0 INTID Writing a value to this field generates an interrupt for the specified the interrupt number (see Table 50). The range allowed for the LPC176x/5x is 0 to 111. 31:9 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 91 of 849 UM10360 Chapter 7: LPC176x/5x Pin configuration Rev. 3.1 — 2 April 2014 7.1 LPC176x/5x pin configuration User manual 76 100 1 75 25 Fig 14. LPC176x LQFP100 pin configuration 26 50 51 002aad945_1 61 80 1 60 20 Fig 15. LPC175x LQFP80 pin configuration 21 40 41 002aae158 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 92 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration ball A1 index area LPC1768FET100 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aaf723 Transparent top view Fig 16. Pin configuration TFBGA100 package bump A1 index area LPC1768UK 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K aaa-009522 Transparent top view Fig 17. Pin configuration WLCSP100 package Table 72. Pin allocation table TFBGA100 package Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] Row B 1 TMS/SWDIO 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 2 RTCK Pin Symbol 3 VDD(3V3) 7 VDD(REG)(3V3) 11 - 3 VSS Pin Symbol 4 P1[4]/ENET_TX_EN 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 12 - 4 P1[1]/ENET_TXD1 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 93 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 72. Pin allocation table TFBGA100 package …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS Row D 10 VDD(3V3) 11 - 12 - 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ 10 P2[5]/PWM1[6]/ 11 - DSR1/TRACEDATA[1] DTR1/TRACEDATA[0] 12 - Row E 1 VSSA 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 2 VDDA 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 3 VREFP 4 n.c. 7 P2[3]/PWM1[4]/ 8 P2[6]/PCAP1[0]/ DCD1/TRACEDATA[2] RI1/TRACECLK 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ 8 P0[16]/RXD1/ RXD2 SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 94 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 72. Pin allocation table TFBGA100 package …continued Pin Symbol Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 9 P2[13]/EINT3/ I2STX_SDA Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 5 P1[23]/MCI1/ PWM1[4]/MISO0 9 P0[11]/RXD2/ SCL2/MAT3[1] 6 VSS 10 P2[10]/EINT0/NMI 2 VDD(3V3) 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 10 P2[12]/EINT2/ I2STX_WS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 11 - 3 VSS 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 11 - Pin Symbol 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 8 P0[1]/TD1/RXD3/SCL1 12 - 4 P1[20]/MCI0/ PWM1[2]/SCK0 8 P0[0]/RD1/TXD3/SDA1 12 - 7.1.1 LPC176x/5x pin description I/O pins on the LPC176x/5x are 5V tolerant and have input hysteresis unless indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be A to D converter inputs, they are no longer 5V tolerant and must be limited to the voltage at the ADC positive reference pin (VREFP). Table 73. Pin description (LPC175x) Symbol Pin Type Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of Port 0 pins depends upon the pin function selected via the pin connect block. Some port pins are not available on the LQFP80 package. P0[0]/RD1/TXD3/ 37[1] SDA1 I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ 38[1] SCL1 I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 79[2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 80[2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 95 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description P0[6]/ 64[1] I2SRX_SDA/ SSEL1/MAT2[0] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1759/58/56 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/I2STX_CLK/ 63[1] SCK1/MAT2[1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1759/58/56 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/I2STX_WS/ 62[1] MISO1/MAT2[2] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1759/58/56 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/I2STX_SDA/ 61[1] MOSI1/MAT2[3] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1759/58/56 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ 39[1] SDA2/MAT3[0] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. P0[11]/RXD2/ 40[1] I/O P0[11] — General purpose digital input/output pin. SCL2/MAT3[1] I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 47[1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 48[1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 96 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description P0[17]/CTS1/ MISO0/MISO 46[1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ 45[1] I/O P0[18] — General purpose digital input/output pin. MOSI0/MOSI I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[22]/RTS1/TD1 44[1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. P0[25]/AD0[2]/ 7[2] I2SRX _SDA/ TXD3 I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1759/58/56 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ 6[3] AOUT/RXD3 I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output. (LPC1759/58/56/54 only). I RXD3 — Receiver input for UART3. P0[29]/USB_D+ 22[4] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. P0[30]/USB_D 23[4] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Some port pins are not available on the LQFP80 package. P1[0]/ ENET_TXD0 76[1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1758 only). P1[1]/ ENET_TXD1 75[1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1758 only). P1[4]/ 74[1] I/O P1[4] — General purpose digital input/output pin. ENET_TX_EN O ENET_TX_EN — Ethernet transmit data enable. (LPC1758 only). P1[8]/ ENET_CRS 73[1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1758 only). P1[9]/ ENET_RXD0 72[1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1758 only). P1[10]/ ENET_RXD1 71[1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1758 only). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 97 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description P1[14]/ ENET_RX_ER 70[1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1758 only). P1[15]/ 69[1] ENET_REF_CLK I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1758 only). P1[18]/ 25[1] USB_UP_LED/ PWM1[1]/ CAP1[0] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ 26[1] USB_PPWR CAP1[1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1759/58/56/54 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ 27[1] PWM1[2]/SCK0 I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[22]/MCOB0/ 28[1] USB_PWRD/ MAT1[0] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch). (LPC1759/58/56/54 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ 29[1] PWM1[4]/MISO0 I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ 30[1] PWM1[5]/MOSI0 I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. P1[25]/MCOA1/ 31[1] MAT1[1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 98 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description P1[26]/MCOB1/ 32[1] PWM1[6]/CAP0[0] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[28]/MCOA2/ 35[1] PCAP1[0]/ MAT0[0] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ 36[1] PCAP1[1]/ MAT0[1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 18[2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 17[2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Some port pins are not available on the LQFP80 package. P2[0]/PWM1[1]/ TXD1 60[1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 59[1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. P2[2]/PWM1[3]/ 58[1] CTS1/ TRACEDATA[3] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ 55[1] DCD1/ TRACEDATA[2] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ 54[1] DSR1/ TRACEDATA[1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 99 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description P2[5]/PWM1[6]/ 53[1] DTR1/ TRACEDATA[0] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ 52[1] RI1/TRACECLK I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 51[1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1759/58/56 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 50[1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1759/58/56 only). O TXD2 — Transmitter output for UART2. P2[9]/ 49[1] USB_CONNECT/ RXD2 I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 41[5] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Some port pins are not available on the LQFP80 package. P4[28]/RX_MCLK/ 65[1] MAT2[0]/TXD3 I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I2S receive master clock. (LPC1759/58/56 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ 68[1] MAT2[1]/RXD3 I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I2S transmit master clock. (LPC1759/58/56 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. TDO/SWO 1[6] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2[7] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3[7] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4[7] I TRST — Test Reset for JTAG interface. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 100 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description (LPC175x) …continued Symbol Pin Type Description TCK/SWDCLK 5[6] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RSTOUT 11 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates UM10360 being in Reset state. RESET 14[8] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 19[9][10] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 20[9][10] O Output from the oscillator amplifier. RTCX1 13[9][11] I Input to the RTC oscillator circuit. RTCX2 15[9] O Output from the RTC oscillator circuit. VSS 24, 33, I ground: 0 V reference. 43, 57, 66, 78 VSSA 9 I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 21, 42, I 56, 77 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 34, 67 I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 8 I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 10 I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFN 12 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 16[11] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [5] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [6] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [7] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [8] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [9] Pad provides special analog functionality. 32 kHz crystal oscillator must be used with the RTC. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 101 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration [10] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [11] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. Table 74. Pin description (LPC176x) Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. SDA1 I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. SCL1 O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 102 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[6]/ 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I2SRX_SDA/ SSEL1/MAT2[0] I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I2STX_WS/ MISO1/MAT2[2] I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I2STX_SDA/ MOSI1/MAT2[3] I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 103 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 104 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 105 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. ENET_REF_CLK I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). P1[18]/ 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. USB_UP_LED/ PWM1[1]/ CAP1[0] O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. USB_PPWR/ CAP1[1] O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 106 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P1[20]/MCI0/ 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. PWM1[2]/SCK0 I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. PWM1[3]/ SSEL0 O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. USB_PWRD/ MAT1[0] O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. PWM1[4]/MISO0 I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. PWM1[5]/MOSI0 I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. P1[25]/MCOA1/ 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. MAT1[1] O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. PWM1[6]/CAP0[0] O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. /USB_OVRCR/ CAP0[1] O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 107 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P1[28]/MCOA2/ 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. PCAP1[0]/ MAT0[0] O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. PCAP1[1]/ MAT0[1] O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. TXD1 O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. RXD1 O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. P2[2]/PWM1[3]/ 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. CTS1/ TRACEDATA[3] O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. DCD1/ TRACEDATA[2] O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. DSR1/ TRACEDATA[1] O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 108 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P2[5]/PWM1[6]/ 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. DTR1/ TRACEDATA[0] O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. RI1/TRACECLK I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. USB_CONNECT/ RXD2 O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 109 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P3[0] to P3[31] I/O P3[25]/MAT0[0]/ 27 H3 D8 [1] I/O PWM1[2] O O P3[26]/STCLK/ 26 K1 A10 [1] I/O MAT0[1]/PWM1[3] I O O P4[0] to P4[31] I/O P4[28]/RX_MCLK/ 82 C7 G1 [1] I/O MAT2[0]/TXD3 O O O P4[29]/TX_MCLK/ 85 E6 F1 [1] I/O MAT2[1]/RXD3 O TDO/SWO TDI TMS/SWDIO TRST TCK/SWDCLK RTCK RSTOUT O I 1 A1 A1 [1][7] O O 2 C3 C4 [1][8] I 3 B1 B3 [1][8] I I/O 4 C2 A2 [1][8] I 5 C1 D4 [1][7] I I 100 B2 B2 [1][7] O 14 - - - O RESET 17 F3 C6 [9] I Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25] — General purpose digital input/output pin. MAT0[0] — Match output for Timer 0, channel 0. PWM1[2] — Pulse Width Modulator 1, output 2. P3[26] — General purpose digital input/output pin. STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. MAT0[1] — Match output for Timer 0, channel 1. PWM1[3] — Pulse Width Modulator 1, output 3. Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28] — General purpose digital input/output pin. RX_MCLK — I2S receive master clock. (LPC1769/68/67/66/65 only). MAT2[0] — Match output for Timer 2, channel 0. TXD3 — Transmitter output for UART3. P4[29] — General purpose digital input/output pin. TX_MCLK — I2S transmit master clock. (LPC1769/68/67/66/65 only). MAT2[1] — Match output for Timer 2, channel 1. RXD3 — Receiver input for UART3. TDO — Test Data out for JTAG interface. SWO — Serial wire trace output. TDI — Test Data in for JTAG interface. TMS — Test Mode Select for JTAG interface. SWDIO — Serial wire debug data input/output. TRST — Test Reset for JTAG interface. TCK — Test Clock for JTAG interface. SWDCLK — Serial wire clock. RTCK — JTAG interface control signal. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 110 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration Table 74. Pin description (LPC176x) …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 XTAL1 XTAL2 RTCX1 RTCX2 VSS VSSA VDD(3V3) VDD(REG)(3V3) VDDA VREFP VREFN VBAT n.c. 22 H2 D7 23 G3 A9 16 F2 A7 18 G1 B7 31, B3, E5, 41, B7, F5, 55, C9, F6, 72, G7, G5, 83, J6, G6, 97 K3 G7 11 E1 B5 [10][11] I [10][11] O [10][11] I [10] O [10] I [10] I 28, K2, E4, [10] I 54, H9, E6, 71, C10 F7, 96 , A3 G4 42, H6, F4, [10] I 84 A7 F0 10 E2 A4 [10] I 12 E3 A5 [10] I 15 F1 A6 I 19 G2 A8 [10] I 13 D4, B6, - E4 D6 Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. ground: 0 V reference. analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 3.3 V supply voltage: This is the power supply voltage for the I/O ports. 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. not connected. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 111 of 849 NXP Semiconductors UM10360 Chapter 7: LPC176x/5x Pin configuration [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 112 of 849 UM10360 Chapter 8: LPC176x/5x Pin connect block Rev. 3.1 — 2 April 2014 User manual 8.1 How to read this chapter Table 75 shows the functions of the PINSEL registers in the LPC176x/5x. Table 75. Summary of PINSEL registers Register Controls PINSEL0 P0[15:0] PINSEL1 P0 [31:16] PINSEL2 P1 [15:0] (Ethernet) PINSEL3 P1 [31:16] PINSEL4 P2 [15:0] PINSEL5 P2 [31:16] PINSEL6 P3 [15:0] PINSEL7 P3 [31:16] PINSEL8 P4 [15:0] PINSEL9 P4 [31:16] PINSEL10 Trace port enable Table Table 80 Table 81 Table 82 Table 83 Table 84 not used not used Table 85 not used Table 86 Table 87 8.2 Description The pin connect block allows most pins of the microcontroller to have more than one potential function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Selection of a single function on a port pin excludes other peripheral functions available on the same pin. However, the GPIO input stays connected and may be read by software or used to contribute to the GPIO interrupt feature. 8.3 Pin function select register values UM10360 User manual The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins. Table 76. Pin function select register bits PINSEL0 to Function PINSEL9 Values 00 Primary (default) function, typically GPIO port 01 First alternate function 10 Second alternate function 11 Third alternate function Value after Reset 00 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 113 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet. Multiple connections Since a particular peripheral function may be allowed on more than one pin, it is in principle possible to configure more than one pin to perform the same function. If a peripheral output function is configured to appear on more than one pin, it will in fact be routed to those pins. If a peripheral input function is configured to appear on more than one pin for some reason, the peripheral will receive its input from the lowest port number. For instance, any pin of port 0 will take precedence over any pin of a higher numbered port, and pin 0 of any port will take precedence over a higher numbered pin of the same port. 8.4 Pin mode select register values UM10360 User manual The PINMODE registers control the input mode of all ports. This includes the use of the on-chip pull-up/pull-down resistor feature and a special open drain operating mode. The on-chip pull-up/pull-down resistor can be selected for every port pin regardless of the function on this pin with the exception of the I2C pins for the I2C0 interface and the USB pins (see Section 8.5.10). Three bits are used to control the mode of a port pin, two in a PINMODE register, and an additional one in a PINMODE_OD register. Bits are reserved for unused pins as in the PINSEL registers. Table 77. Pin Mode Select register Bits PINMODE0 to Function PINMODE9 Values 00 Pin has an on-chip pull-up resistor enabled. 01 Repeater mode (see text below). 10 Pin has neither pull-up nor pull-down resistor enabled. 11 Pin has an on-chip pull-down resistor enabled. Value after Reset 00 Repeater mode enables the pull-up resistor if the pin is at a logic high and enables the pull-down resistor if the pin is at a logic low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep Power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven. The PINMODE_OD registers control the open drain mode for ports. The open drain mode causes the pin to be pulled low normally if it is configured as an output and the data value is 0. If the data value is 1, the output drive of the pin is turned off, equivalent to changing the pin direction. This combination simulates an open drain output. Table 78. Open Drain Pin Mode Select register Bits PINMODE_OD0 to Function PINMODE_OD4 Values 0 Pin is in the normal (not open drain) mode. 1 Pin is in the open drain mode. Value after Reset 00 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 114 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Function of PINMODE in open drain mode Normally the value of PINMODE applies to a pin only when it is in the input mode. When a pin is in the open drain mode, caused by a 1 in the corresponding bit of one of the PINMODE_OD registers, the input mode still does not apply when the pin is outputting a 0. However, when the pin value is 1, PINMODE applies since this state turns off the pin’s output driver. For example, this allows for the possibility of configuring a pin to be open drain with an on-chip pullup. A pullup in this case which is only on when the pin is not being pulled low by the pin’s own output. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 115 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block 8.5 Register description The Pin Control Module contains 11 registers as shown in Table 79 below. Table 79. Pin Connect Block Register Map Name Description PINSEL0 PINSEL1 PINSEL2 PINSEL3 PINSEL4 PINSEL7 PINSEL8 PINSEL9 PINSEL10 PINMODE0 PINMODE1 PINMODE2 PINMODE3 PINMODE4 PINMODE5 PINMODE6 PINMODE7 PINMODE9 PINMODE_OD0 PINMODE_OD1 PINMODE_OD2 PINMODE_OD3 PINMODE_OD4 I2CPADCFG Pin function select register 0. Pin function select register 1. Pin function select register 2. Pin function select register 3. Pin function select register 4 Pin function select register 7 Pin function select register 8 Pin function select register 9 Pin function select register 10 Pin mode select register 0 Pin mode select register 1 Pin mode select register 2 Pin mode select register 3. Pin mode select register 4 Pin mode select register 5 Pin mode select register 6 Pin mode select register 7 Pin mode select register 9 Open drain mode control register 0 Open drain mode control register 1 Open drain mode control register 2 Open drain mode control register 3 Open drain mode control register 4 I2C Pin Configuration register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x4002 C000 0x4002 C004 0x4002 C008 0x4002 C00C 0x4002 C010 0x4002 C01C 0x4002 C020 0x4002 C024 0x4002 C028 0x4002 C040 0x4002 C044 0x4002 C048 0x4002 C04C 0x4002 C050 0x4002 C054 0x4002 C058 0x4002 C05C 0x4002 C064 0x4002 C068 0x4002 C06C 0x4002 C070 0x4002 C074 0x4002 C078 0x4002 C07C [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Pin control module register reset values On external reset, watchdog reset, power-on-reset (POR), and BOD reset, all registers in this module are reset to '0'. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 116 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block 8.5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000) The PINSEL0 register controls the functions of the lower half of Port 0. The direction control bit in FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. Table 80. Pin function select register 0 (PINSEL0 - address 0x4002 C000) bit description PINSEL0 Pin Function when Function when 01 Function name 00 when 10 Function when 11 Reset value 1:0 P0.0 GPIO Port 0.0 RD1 TXD3 SDA1 00 3:2 P0.1 GPIO Port 0.1 TD1 RXD3 SCL1 00 5:4 P0.2 GPIO Port 0.2 TXD0 AD0.7 Reserved 00 7:6 P0.3 GPIO Port 0.3 RXD0 AD0.6 Reserved 00 9:8 P0.4[1] GPIO Port 0.4 I2SRX_CLK RD2 CAP2.0 00 11:10 P0.5[1] GPIO Port 0.5 I2SRX_WS TD2 CAP2.1 00 13:12 P0.6 GPIO Port 0.6 I2SRX_SDA SSEL1 MAT2.0 00 15:14 P0.7 GPIO Port 0.7 I2STX_CLK SCK1 MAT2.1 00 17:16 P0.8 GPIO Port 0.8 I2STX_WS MISO1 MAT2.2 00 19:18 P0.9 GPIO Port 0.9 I2STX_SDA MOSI1 MAT2.3 00 21:20 P0.10 GPIO Port 0.10 TXD2 SDA2 MAT3.0 00 23:22 P0.11 GPIO Port 0.11 RXD2 SCL2 MAT3.1 00 29:24 - Reserved Reserved Reserved Reserved 0 31:30 P0.15 GPIO Port 0.15 TXD1 SCK0 SCK 00 [1] Not available on 80-pin package. 8.5.2 Pin Function Select Register 1 (PINSEL1 - 0x4002 C004) The PINSEL1 register controls the functions of the upper half of Port 0. The direction control bit in the FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions the direction is controlled automatically. Table 81. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description PINSEL1 Pin name Function when Function 00 when 01 Function when 10 Function when 11 1:0 P0.16 GPIO Port 0.16 RXD1 SSEL0 SSEL 3:2 P0.17 GPIO Port 0.17 CTS1 MISO0 MISO 5:4 P0.18 GPIO Port 0.18 DCD1 MOSI0 MOSI 7:6 P0.19[1] GPIO Port 0.19 DSR1 Reserved SDA1 9:8 P0.20[1] GPIO Port 0.20 DTR1 Reserved SCL1 11:10 P0.21[1] GPIO Port 0.21 RI1 Reserved RD1 13:12 P0.22 GPIO Port 0.22 RTS1 Reserved TD1 15:14 P0.23[1] GPIO Port 0.23 AD0.0 I2SRX_CLK CAP3.0 17:16 P0.24[1] GPIO Port 0.24 AD0.1 I2SRX_WS CAP3.1 19:18 P0.25 GPIO Port 0.25 AD0.2 I2SRX_SDA TXD3 21:20 P0.26 GPIO Port 0.26 AD0.3 AOUT RXD3 23:22 P0.27[1][2] GPIO Port 0.27 SDA0 USB_SDA Reserved Reset value 00 00 00 00 00 00 00 00 00 00 00 00 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 117 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 81. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description …continued PINSEL1 Pin name Function when Function 00 when 01 Function when 10 Function when 11 25:24 P0.28[1][2] GPIO Port 0.28 SCL0 USB_SCL Reserved 27:26 P0.29 GPIO Port 0.29 USB_D Reserved Reserved 29:28 P0.30 GPIO Port 0.30 USB_D Reserved Reserved 31:30 - Reserved Reserved Reserved Reserved [1] Not available on 80-pin package. [2] Pins P0[27] and P0[28] are open-drain for I2C-bus compliance. Reset value 00 00 00 00 8.5.3 Pin Function Select register 2 (PINSEL2 - 0x4002 C008) The PINSEL2 register controls the functions of the lower half of Port 1, which contains the Ethernet related pins. The direction control bit in the FIO1DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. Table 82. Pin function select register 2 (PINSEL2 - address 0x4002 C008) bit description PINSEL2 Pin name Function when Function when Function 00 01 when 10 Function when 11 Reset value 1:0 P1.0 GPIO Port 1.0 ENET_TXD0 Reserved Reserved 00 3:2 P1.1 GPIO Port 1.1 ENET_TXD1 Reserved Reserved 00 7:4 - Reserved Reserved Reserved Reserved 0 9:8 P1.4 GPIO Port 1.4 ENET_TX_EN Reserved Reserved 00 15:10 - Reserved Reserved Reserved Reserved 0 17:16 P1.8 GPIO Port 1.8 ENET_CRS Reserved Reserved 00 19:18 P1.9 GPIO Port 1.9 ENET_RXD0 Reserved Reserved 00 21:20 P1.10 GPIO Port 1.10 ENET_RXD1 Reserved Reserved 00 27:22 - Reserved Reserved Reserved Reserved 0 29:28 P1.14 GPIO Port 1.14 ENET_RX_ER Reserved Reserved 00 31:30 P1.15 GPIO Port 1.15 ENET_REF_CLK Reserved Reserved 00 8.5.4 Pin Function Select Register 3 (PINSEL3 - 0x4002 C00C) The PINSEL3 register controls the functions of the upper half of Port 1. The direction control bit in the FIO1DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 83. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description PINSEL3 Pin Function when Function when Function name 00 01 when 10 Function when 11 1:0 P1.16[1] GPIO Port 1.16 ENET_MDC Reserved Reserved 3:2 P1.17[1] GPIO Port 1.17 ENET_MDIO Reserved Reserved 5:4 P1.18 GPIO Port 1.18 USB_UP_LED PWM1.1 CAP1.0 7:6 P1.19 GPIO Port 1.19 MCOA0 USB_PPWR CAP1.1 9:8 P1.20 GPIO Port 1.20 MCI0 PWM1.2 SCK0 Reset value 00 00 00 00 00 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 118 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 83. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description …continued PINSEL3 Pin Function when Function when Function name 00 01 when 10 Function when 11 11:10 P1.21[1] GPIO Port 1.21 MCABORT PWM1.3 SSEL0 13:12 P1.22 GPIO Port 1.22 MCOB0 USB_PWRD MAT1.0 15:14 P1.23 GPIO Port 1.23 MCI1 PWM1.4 MISO0 17:16 P1.24 GPIO Port 1.24 MCI2 PWM1.5 MOSI0 19:18 P1.25 GPIO Port 1.25 MCOA1 Reserved MAT1.1 21:20 P1.26 GPIO Port 1.26 MCOB1 PWM1.6 CAP0.0 23:22 P1.27[1] GPIO Port 1.27 CLKOUT USB_OVRCR CAP0.1 25:24 P1.28 GPIO Port 1.28 MCOA2 PCAP1.0 MAT0.0 27:26 P1.29 GPIO Port 1.29 MCOB2 PCAP1.1 MAT0.1 29:28 31:30 P1.30 P1.31 GPIO Port 1.30 Reserved GPIO Port 1.31 Reserved VBUS SCK1 AD0.4 AD0.5 [1] Not available on 80-pin package. Reset value 00 00 00 00 00 00 00 00 00 00 00 8.5.5 Pin Function Select Register 4 (PINSEL4 - 0x4002 C010) The PINSEL4 register controls the functions of the lower half of Port 2. The direction control bit in the FIO2DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 84. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description PINSEL4 Pin Function when Function when 01 Function Function when Reset name 00 when 10 11 value 1:0 P2.0 GPIO Port 2.0 PWM1.1 TXD1 Reserved 00 3:2 P2.1 GPIO Port 2.1 PWM1.2 RXD1 Reserved 00 5:4 P2.2 GPIO Port 2.2 PWM1.3 CTS1 Reserved [2] 00 7:6 P2.3 GPIO Port 2.3 PWM1.4 DCD1 Reserved [2] 00 9:8 P2.4 GPIO Port 2.4 PWM1.5 DSR1 Reserved [2] 00 11:10 P2.5 GPIO Port 2.5 PWM1.6 DTR1 Reserved [2] 00 13:12 P2.6 GPIO Port 2.6 PCAP1.0 RI1 Reserved [2] 00 15:14 P2.7 GPIO Port 2.7 RD2 RTS1 Reserved 00 17:16 P2.8 GPIO Port 2.8 TD2 TXD2 ENET_MDC 00 19:18 P2.9 GPIO Port 2.9 USB_CONNECT RXD2 ENET_MDIO 00 21:20 P2.10 GPIO Port 2.10 EINT0 NMI Reserved 00 23:22 P2.11[1] GPIO Port 2.11 EINT1 Reserved I2STX_CLK 00 25:24 P2.12[1] GPIO Port 2.12 EINT2 Reserved I2STX_WS 00 27:26 P2.13[1] GPIO Port 2.13 EINT3 Reserved I2STX_SDA 00 31:28 - Reserved Reserved Reserved Reserved 0 [1] Not available on 80-pin package. [2] These pins support a debug trace function when selected via a development tool or by writing to the PINSEL10 register. See Section 8.5.8 “Pin Function Select Register 10 (PINSEL10 - 0x4002 C028)” for details. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 119 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block 8.5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C) The PINSEL7 register controls the functions of the upper half of Port 3. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 85. Pin function select register 7 (PINSEL7 - address 0x4002 C01C) bit description PINSEL7 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 17:0 - Reserved Reserved Reserved Reserved 0 19:18 P3.25[1] GPIO Port 3.25 Reserved MAT0.0 PWM1.2 00 21:20 P3.26[1] GPIO Port 3.26 STCLK MAT0.1 PWM1.3 00 31:22 - Reserved Reserved Reserved Reserved 0 [1] Not available on 80-pin package. 8.5.7 Pin Function Select Register 9 (PINSEL9 - 0x4002 C024) The PINSEL9 register controls the functions of the upper half of Port 4. The direction control bit in the FIO4DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 86. Pin function select register 9 (PINSEL9 - address 0x4002 C024) bit description PINSEL9 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 23:0 - Reserved Reserved Reserved Reserved 00 25:24 P4.28 GPIO Port 4.28 RX_MCLK MAT2.0 TXD3 00 27:26 P4.29 GPIO Port 4.29 TX_MCLK MAT2.1 RXD3 00 31:28 - Reserved Reserved Reserved Reserved 00 8.5.8 Pin Function Select Register 10 (PINSEL10 - 0x4002 C028) Only bit 3 of this register is used to control the Trace function on pins P2.2 through P2.6. Table 87. Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description Bit Symbol Value Description Reset value 2:0 - - Reserved. Software should not write 1 to these bits. NA 3 GPIO/TRACE TPIU interface pins control. 0 0 TPIU interface is disabled. 1 TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content. 31:4 - - Reserved. Software should not write 1 to these bits. NA UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 120 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block 8.5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040) This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. Table 88. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description PINMODE0 Symbol Value Description Reset value 1:0 P0.00MODE Port 0 pin 0 on-chip pull-up/down resistor control. 00 00 P0.0 pin has a pull-up resistor enabled. 01 P0.0 pin has repeater mode enabled. 10 P0.0 pin has neither pull-up nor pull-down. 11 P0.0 has a pull-down resistor enabled. 3:2 P0.01MODE Port 0 pin 1 control, see P0.00MODE. 00 5:4 P0.02MODE Port 0 pin 2 control, see P0.00MODE. 00 7:6 P0.03MODE Port 0 pin 3 control, see P0.00MODE. 00 9:8 P0.04MODE[1] Port 0 pin 4 control, see P0.00MODE. 00 11:10 P0.05MODE[1] Port 0 pin 5 control, see P0.00MODE. 00 13:12 P0.06MODE Port 0 pin 6 control, see P0.00MODE. 00 15:14 P0.07MODE Port 0 pin 7 control, see P0.00MODE. 00 17:16 P0.08MODE Port 0 pin 8 control, see P0.00MODE. 00 19:18 P0.09MODE Port 0 pin 9control, see P0.00MODE. 00 21:20 P0.10MODE Port 0 pin 10 control, see P0.00MODE. 00 23:22 P0.11MODE Port 0 pin 11 control, see P0.00MODE. 00 29:24 - Reserved. NA 31:30 P0.15MODE Port 0 pin 15 control, see P0.00MODE. 00 [1] Not available on 80-pin package. 8.5.10 Pin Mode select register 1 (PINMODE1 - 0x4002 C044) This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 26. For details see Section 8.4 “Pin mode select register values”. Table 89. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description PINMODE1 Symbol Description Reset value 1:0 P0.16MODE Port 1 pin 16 control, see P0.00MODE. 00 3:2 P0.17MODE Port 1 pin 17 control, see P0.00MODE. 00 5:4 P0.18MODE Port 1 pin 18 control, see P0.00MODE. 00 7:6 P0.19MODE[1] Port 1 pin 19 control, see P0.00MODE. 00 9:8 P0.20MODE[1] Port 1 pin 20control, see P0.00MODE. 00 11:10 P0.21MODE[1] Port 1 pin 21 control, see P0.00MODE. 00 13:12 P0.22MODE Port 1 pin 22 control, see P0.00MODE. 00 15:14 P0.23MODE[1] Port 1 pin 23 control, see P0.00MODE. 00 17:16 P0.24MODE[1] Port 1 pin 24 control, see P0.00MODE. 00 19:18 P0.25MODE Port 1 pin 25 control, see P0.00MODE. 00 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 121 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 89. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description PINMODE1 Symbol Description Reset value 21:20 P0.26MODE Port 1 pin 26 control, see P0.00MODE. 00 29:22 - Reserved. [2] NA 31:30 - Reserved. NA [1] Not available on 80-pin package. [2] The pin mode cannot be selected for pins P0[27] to P0[30]. Pins P0[27] and P0[28] are dedicated I2C open-drain pins without pull-up/down. Pins P0[29] and P0[30] are USB specific pins without configurable pull-up or pull-down resistors. Pins P0[29] and P0[30] also must have the same direction since they operate as a unit for the USB function, see Section 9.5.1 “GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080)”. 8.5.11 Pin Mode select register 2 (PINMODE2 - 0x4002 C048) This register controls pull-up/pull-down resistor configuration for Port 1 pins 0 to 15. For details see Section 8.4 “Pin mode select register values”. Table 90. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description PINMODE2 Symbol Description Reset value 1:0 P1.00MODE Port 1 pin 0 control, see P0.00MODE. 00 3:2 P1.01MODE Port 1 pin 1 control, see P0.00MODE. 00 7:4 - Reserved. NA 9:8 P1.04MODE Port 1 pin 4 control, see P0.00MODE. 00 15:10 - Reserved. NA 17:16 P1.08MODE Port 1 pin 8 control, see P0.00MODE. 00 19:18 P1.09MODE Port 1 pin 9 control, see P0.00MODE. 00 21:20 P1.10MODE Port 1 pin 10 control, see P0.00MODE. 00 27:22 - Reserved. NA 29:28 P1.14MODE Port 1 pin 14 control, see P0.00MODE. 00 31:30 P1.15MODE Port 1 pin 15 control, see P0.00MODE. 00 8.5.12 Pin Mode select register 3 (PINMODE3 - 0x4002 C04C) This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 31. For details see Section 8.4 “Pin mode select register values”. Table 91. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description PINMODE3 Symbol Description Reset value 1:0 P1.16MODE[1] Port 1 pin 16 control, see P0.00MODE. 00 3:2 P1.17MODE[1] Port 1 pin 17 control, see P0.00MODE. 00 5:4 P1.18MODE Port 1 pin 18 control, see P0.00MODE. 00 7:6 P1.19MODE Port 1 pin 19 control, see P0.00MODE. 00 9:8 P1.20MODE Port 1 pin 20 control, see P0.00MODE. 00 11:10 P1.21MODE[1] Port 1 pin 21 control, see P0.00MODE. 00 13:12 P1.22MODE Port 1 pin 22 control, see P0.00MODE. 00 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 122 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 91. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description PINMODE3 Symbol Description Reset value 15:14 P1.23MODE Port 1 pin 23 control, see P0.00MODE. 00 17:16 P1.24MODE Port 1 pin 24 control, see P0.00MODE. 00 19:18 P1.25MODE Port 1 pin 25 control, see P0.00MODE. 00 21:20 P1.26MODE Port 1 pin 26 control, see P0.00MODE. 00 23:22 P1.27MODE[1] Port 1 pin 27 control, see P0.00MODE. 00 25:24 P1.28MODE Port 1 pin 28 control, see P0.00MODE. 00 27:26 P1.29MODE Port 1 pin 29 control, see P0.00MODE. 00 29:28 P1.30MODE Port 1 pin 30 control, see P0.00MODE. 00 31:30 P1.31MODE Port 1 pin 31 control, see P0.00MODE. 00 [1] Not available on 80-pin package. 8.5.13 Pin Mode select register 4 (PINMODE4 - 0x4002 C050) This register controls pull-up/pull-down resistor configuration for Port 2 pins 0 to 15. For details see Section 8.4 “Pin mode select register values”. Table 92. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description PINMODE4 Symbol Description Reset value 1:0 P2.00MODE Port 2 pin 0 control, see P0.00MODE. 00 3:2 P2.01MODE Port 2 pin 1 control, see P0.00MODE. 00 5:4 P2.02MODE Port 2 pin 2 control, see P0.00MODE. 00 7:6 P2.03MODE Port 2 pin 3 control, see P0.00MODE. 00 9:8 P2.04MODE Port 2 pin 4 control, see P0.00MODE. 00 11:10 P2.05MODE Port 2 pin 5 control, see P0.00MODE. 00 13:12 P2.06MODE Port 2 pin 6 control, see P0.00MODE. 00 15:14 P2.07MODE Port 2 pin 7 control, see P0.00MODE. 00 17:16 P2.08MODE Port 2 pin 8 control, see P0.00MODE. 00 19:18 P2.09MODE Port 2 pin 9 control, see P0.00MODE. 00 21:20 P2.10MODE Port 2 pin 10 control, see P0.00MODE. 00 23:22 P2.11MODE[1] Port 2 pin 11 control, see P0.00MODE. 00 25:24 P2.12MODE[1] Port 2 pin 12 control, see P0.00MODE. 00 27:26 P2.13MODE[1] Port 2 pin 13 control, see P0.00MODE. 00 31:28 - Reserved. NA [1] Not available on 80-pin package. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 123 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block 8.5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8.4 “Pin mode select register values”. Table 93. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description PINMODE7 Symbol Description Reset value 17:0 - Reserved NA 19:18 P3.25MODE[1] Port 3 pin 25 control, see P0.00MODE. 00 21:20 P3.26MODE[1] Port 3 pin 26 control, see P0.00MODE. 00 31:22 - Reserved. NA [1] Not available on 80-pin package. 8.5.15 Pin Mode select register 9 (PINMODE9 - 0x4002 C064) This register controls pull-up/pull-down resistor configuration for Port 4 pins 16 to 31. For details see Section 8.4 “Pin mode select register values”. Table 94. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description PINMODE9 Symbol Description Reset value 23:0 - Reserved. NA 25:24 P4.28MODE Port 4 pin 28 control, see P0.00MODE. 00 27:26 P4.29MODE Port 4 pin 29 control, see P0.00MODE. 00 31:28 - Reserved. NA 8.5.16 Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068) This register controls the open drain mode for Port 0 pins. For details see Section 8.4 “Pin mode select register values”. Table 95. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description PINMODE Symbol _OD0 Value Description Reset value 0 P0.00OD[3] Port 0 pin 0 open drain mode control. 0 0 P0.0 pin is in the normal (not open drain) mode. 1 P0.0 pin is in the open drain mode. 1 P0.01OD[3] Port 0 pin 1 open drain mode control, see P0.00OD 0 2 P0.02OD Port 0 pin 2 open drain mode control, see P0.00OD 0 3 P0.03OD Port 0 pin 3 open drain mode control, see P0.00OD 0 4 P0.04OD Port 0 pin 4 open drain mode control, see P0.00OD 0 5 P0.05OD Port 0 pin 5 open drain mode control, see P0.00OD 0 6 P0.06OD Port 0 pin 6 open drain mode control, see P0.00OD 0 7 P0.07OD Port 0 pin 7 open drain mode control, see P0.00OD 0 8 P0.08OD Port 0 pin 8 open drain mode control, see P0.00OD 0 9 P0.09OD Port 0 pin 9 open drain mode control, see P0.00OD 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 124 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 95. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description …continued PINMODE Symbol _OD0 Value Description Reset value 10 P0.10OD[3] Port 0 pin 10 open drain mode control, see P0.00OD 0 11 P0.11OD[3] Port 0 pin 11 open drain mode control, see P0.00OD 0 14:12 - Reserved. NA 15 P0.15OD Port 0 pin 15 open drain mode control, see P0.00OD 0 16 P0.16OD Port 0 pin 16 open drain mode control, see P0.00OD 0 17 P0.17OD Port 0 pin 17 open drain mode control, see P0.00OD 0 18 P0.18OD Port 0 pin 18 open drain mode control, see P0.00OD 0 19 P0.19OD[3] Port 0 pin 19 open drain mode control, see P0.00OD 0 20 P0.20OD[3] Port 0 pin 20open drain mode control, see P0.00OD 0 21 P0.21OD Port 0 pin 21 open drain mode control, see P0.00OD 0 22 P0.22OD Port 0 pin 22 open drain mode control, see P0.00OD 0 23 P0.23OD Port 0 pin 23 open drain mode control, see P0.00OD 0 24 P0.24OD Port 0 pin 24open drain mode control, see P0.00OD 0 25 P0.25OD Port 0 pin 25 open drain mode control, see P0.00OD 0 26 P0.26OD Port 0 pin 26 open drain mode control, see P0.00OD 0 28:27 - [2] Reserved. NA 29 P0.29OD Port 0 pin 29 open drain mode control, see P0.00OD 0 30 P0.30OD Port 0 pin 30 open drain mode control, see P0.00OD 0 31 - Reserved. NA [1] Not available on 80-pin package. [2] Port 0 pins 27 and 28 should be set up using the I2CPADCFG register if they are used for an I2C-bus. Bits 27 and 28 of PINMODE_OD0 do not have any affect on these pins, they are special open drain I2C-bus compatible pins. [3] Port 0 bits 1:0, 11:10, and 20:19 may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. 8.5.17 Open Drain Pin Mode select register 1 (PINMODE_OD1 0x4002 C06C) This register controls the open drain mode for Port 1 pins. For details see Section 8.4 “Pin mode select register values”. Table 96. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description PINMODE Symbol _OD1 Value Description Reset value 0 P1.00OD Port 1 pin 0 open drain mode control. 0 0 P1.0 pin is in the normal (not open drain) mode. 1 P1.0 pin is in the open drain mode. 1 P1.01OD Port 1 pin 1 open drain mode control, see P1.00OD 0 3:2 - Reserved. NA 4 P1.04OD Port 1 pin 4 open drain mode control, see P1.00OD 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 125 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 96. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description …continued PINMODE Symbol _OD1 Value Description Reset value 7:5 - Reserved. NA 8 P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD 0 9 P1.09OD Port 1 pin 9 open drain mode control, see P1.00OD 0 10 P1.10OD Port 1 pin 10 open drain mode control, see P1.00OD 0 13:11 - Reserved. NA 14 P1.14OD Port 1 pin 14 open drain mode control, see P1.00OD 0 15 P1.15OD Port 1 pin 15 open drain mode control, see P1.00OD 0 16 P1.16OD[1] Port 1 pin 16 open drain mode control, see P1.00OD 0 17 P1.17OD[1] Port 1 pin 17 open drain mode control, see P1.00OD 0 18 P1.18OD Port 1 pin 18 open drain mode control, see P1.00OD 0 19 P1.19OD Port 1 pin 19 open drain mode control, see P1.00OD 0 20 P1.20OD Port 1 pin 20open drain mode control, see P1.00OD 0 21 P1.21OD[1] Port 1 pin 21 open drain mode control, see P1.00OD 0 22 P1.22OD Port 1 pin 22 open drain mode control, see P1.00OD 0 23 P1.23OD Port 1 pin 23 open drain mode control, see P1.00OD 0 24 P1.24OD Port 1 pin 24open drain mode control, see P1.00OD 0 25 P1.25OD Port 1 pin 25 open drain mode control, see P1.00OD 0 26 P1.26OD Port 1 pin 26 open drain mode control, see P1.00OD 0 27 P1.27OD[1] Port 1 pin 27 open drain mode control, see P1.00OD 0 28 P1.28OD Port 1 pin 28 open drain mode control, see P1.00OD 0 29 P1.29OD Port 1 pin 29 open drain mode control, see P1.00OD 0 30 P1.30OD Port 1 pin 30 open drain mode control, see P1.00OD 0 31 P1.31OD Port 1 pin 31 open drain mode control. 0 [1] Not available on 80-pin package. 8.5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070) This register controls the open drain mode for Port 2 pins. For details see Section 8.4 “Pin mode select register values”. Table 97. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description PINMODE Symbol _OD2 Value Description Reset value 0 P2.00OD Port 2 pin 0 open drain mode control. 0 0 P2.0 pin is in the normal (not open drain) mode. 1 P2.0 pin is in the open drain mode. 1 P2.01OD Port 2 pin 1 open drain mode control, see P2.00OD 0 2 P2.02OD Port 2 pin 2 open drain mode control, see P2.00OD 0 3 P2.03OD Port 2 pin 3 open drain mode control, see P2.00OD 0 4 P2.04OD Port 2 pin 4 open drain mode control, see P2.00OD 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 126 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 97. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description …continued PINMODE Symbol _OD2 Value Description Reset value 5 P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD 0 6 P2.06OD Port 2 pin 6 open drain mode control, see P2.00OD 0 7 P2.07OD Port 2 pin 7 open drain mode control, see P2.00OD 0 8 P2.08OD Port 2 pin 8 open drain mode control, see P2.00OD 0 9 P2.09OD Port 2 pin 9 open drain mode control, see P2.00OD 0 10 P2.10OD Port 2 pin 10 open drain mode control, see P2.00OD 0 11 P2.11OD[1] Port 2 pin 11 open drain mode control, see P2.00OD 0 12 P2.12OD[1] Port 2 pin 12 open drain mode control, see P2.00OD 0 13 P2.13OD[1] Port 2 pin 13 open drain mode control, see P2.00OD 0 31:14 - Reserved. NA [1] Not available on 80-pin package. 8.5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074) This register controls the open drain mode for Port 3 pins. For details see Section 8.4 “Pin mode select register values”. Table 98. Open Drain Pin Mode select register 3 (PINMODE_OD3 - address 0x4002 C074) bit description PINMODE Symbol _OD3 Value Description Reset value 24:0 - Reserved. NA 25 P3.25OD[1] Port 3 pin 25 open drain mode control. 0 0 P3.25 pin is in the normal (not open drain) mode. 1 P3.25 pin is in the open drain mode. 26 P3.26OD[1] Port 3 pin 26 open drain mode control, see P3.25OD 0 31:27 - Reserved. NA [1] Not available on 80-pin package. 8.5.20 Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078) This register controls the open drain mode for Port 4 pins. For details see Section 8.4 “Pin mode select register values”. Table 99. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description PINMODE Symbol _OD4 Value Description Reset value 27:0 - Reserved. NA UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 127 of 849 NXP Semiconductors UM10360 Chapter 8: LPC176x/5x Pin connect block Table 99. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description …continued PINMODE Symbol _OD4 Value Description Reset value 28 P4.28OD Port 4 pin 28 open drain mode control. 0 0 P4.28 pin is in the normal (not open drain) mode. 1 P4.28 pin is in the open drain mode. 29 P4.28OD Port 4 pin 29 open drain mode control, see P4.28OD 0 31:30 - Reserved. NA 8.5.21 I2C Pin Configuration register (I2CPADCFG - 0x4002 C07C) The I2CPADCFG register allows configuration of the I2C pins for the I2C0 interface only, in order to support various I2C-bus operating modes. For use in standard or Fast Mode I2C, the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I2C use of these pins, it may be desirable to turn off I2C filtering and slew rate control by setting SDAI2C0 and SCLI2C0 to 1. See Table 100 below. Table 100. I2C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit description I2CPADCFG Symbol Value Description 0 SDADRV0 Drive mode control for the SDA0 pin, P0.27. 0 The SDA0 pin is in the standard drive mode. 1 The SDA0 pin is in Fast Mode Plus drive mode. 1 SDAI2C0 I2C mode control for the SDA0 pin, P0.27. 0 The SDA0 pin has I2C glitch filtering and slew rate control enabled. 1 The SDA0 pin has I2C glitch filtering and slew rate control disabled. 2 SCLDRV0 Drive mode control for the SCL0 pin, P0.28. 0 The SCL0 pin is in the standard drive mode. 1 The SCL0 pin is in Fast Mode Plus drive mode. 3 SCLI2C0 I2C mode control for the SCL0 pin, P0.28. 0 The SCL0 pin has I2C glitch filtering and slew rate control enabled. 1 The SCL0 pin has I2C glitch filtering and slew rate control disabled. 31:4 - Reserved. Reset value 0 0 0 0 NA UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 128 of 849 UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Rev. 3.1 — 2 April 2014 User manual 9.1 Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8.3 for GPIO pins and their modes. 3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see (Section 4.8.8). 4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (Table 115) or IO0/2IntEnF (Table 117). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 9.2 Features 9.2.1 Digital I/O ports • Accelerated GPIO functions: – GPIO registers are located on a peripheral AHB bus for fast I/O timing. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte, half-word, and word addressable. – Entire port value can be written in one instruction. – GPIO registers are accessible by the GPDMA. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • All GPIO registers support Cortex-M3 bit-banding. • GPIO registers are accessible by the GPDMA controller to allow DMA of data to or from GPIOs, synchronized to any DMA request. • Direction control of individual port bits. • All I/Os default to input with pullup after reset. 9.2.2 Interrupt generating digital ports • Port 0 and Port 2 can provide a single interrupt for any combination of port pins. • Each port pin can be programmed to generate an interrupt on a rising edge, a falling edge, or both. • Edge detection is asynchronous, so it may operate when clocks are not present, such as during Power-down mode. With this feature, level triggered interrupts are not needed. • Each enabled interrupt contributes to a wake-up signal that can be used to bring the part out of Power-down mode. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 129 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3. 9.3 Applications • General purpose I/O • Driving LEDs or other indicators • Controlling off-chip devices • Sensing digital inputs, detecting edges • Bringing the part out of Power-down mode 9.4 Pin description Table 101. GPIO pin description Pin Name Type Description P0[30:0][1]; P1[31:0][2]; P2[13:0]; P3[26:25]; P4[29:28] Input/ Output General purpose input/output. These are typically shared with other peripherals functions and will therefore not all be available in an application. Packaging options may affect the number of GPIOs available in a particular device. Some pins may be limited by requirements of the alternate functions of the pin. For example, the pins containing the I2C0 functions are open-drain for any function selected on that pin. Details may be found in Section 7.1.1. [1] P0[14:12] are not available. [2] P1[2], P1[3], P1[7:5], P1[13:11] are not available. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 130 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5 Register description Due to compatibility requirements with the LPC2300 series ARM7-based products, the LPC176x/5x implements portions of five 32-bit General Purpose I/O ports. Details on a specific GPIO port usage can be found in Section 8.3. The registers in Table 102 represent the enhanced GPIO features available on all of the GPIO ports. These registers are located on an AHB bus for fast read and write timing. They can all be accessed in byte, half-word, and word sizes. A mask register allows access to a group of bits in a single GPIO port independently from other bits in the same port. Table 102. GPIO register map (local bus accessible registers - enhanced GPIO features) Generic Description Name Access Reset PORTn Register value[1] Name & Address FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin. R/W 0 FIO0DIR - 0x2009 C000 FIO1DIR - 0x2009 C020 FIO2DIR - 0x2009 C040 FIO3DIR - 0x2009 C060 FIO4DIR - 0x2009 C080 FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to R/W 0 port (done via writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN) alter or return only the bits enabled by zeros in this register. FIO0MASK - 0x2009 C010 FIO1MASK - 0x2009 C030 FIO2MASK - 0x2009 C050 FIO3MASK - 0x2009 C070 FIO4MASK - 0x2009 C090 FIOPIN Fast Port Pin value register using FIOMASK. The current state R/W 0 of digital port pins can be read from this register, regardless of pin direction or alternate function selection (as long as pins are not configured as an input to ADC). The value read is masked by ANDing with inverted FIOMASK. Writing to this register places corresponding values in all bits enabled by zeros in FIOMASK. FIO0PIN - 0x2009 C014 FIO1PIN - 0x2009 C034 FIO2PIN - 0x2009 C054 FIO3PIN - 0x2009 C074 FIO4PIN - 0x2009 C094 Important: if an FIOPIN register is read, its bit(s) masked with 1 in the FIOMASK register will be read as 0 regardless of the physical pin state. FIOSET Fast Port Output Set register using FIOMASK. This register R/W 0 controls the state of output pins. Writing 1s produces highs at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by 0 in FIOMASK can be altered. FIO0SET - 0x2009 C018 FIO1SET - 0x2009 C038 FIO2SET - 0x2009 C058 FIO3SET - 0x2009 C078 FIO4SET - 0x2009 C098 FIOCLR Fast Port Output Clear register using FIOMASK. This register WO 0 controls the state of output pins. Writing 1s produces lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by 0 in FIOMASK can be altered. FIO0CLR - 0x2009 C01C FIO1CLR - 0x2009 C03C FIO2CLR - 0x2009 C05C FIO3CLR - 0x2009 C07C FIO4CLR - 0x2009 C09C [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 131 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 103. GPIO interrupt register map Generic Name Description IntEnR GPIO Interrupt Enable for Rising edge. IntEnF GPIO Interrupt Enable for Falling edge. IntStatR GPIO Interrupt Status for Rising edge. IntStatF GPIO Interrupt Status for Falling edge. IntClr GPIO Interrupt Clear. IntStatus GPIO overall Interrupt Status. Access R/W R/W RO RO WO RO Reset value[1] 0 0 0 0 0 0 PORTn Register Name & Address IO0IntEnR - 0x4002 8090 IO2IntEnR - 0x4002 80B0 IO0IntEnR - 0x4002 8094 IO2IntEnR - 0x4002 80B4 IO0IntStatR - 0x4002 8084 IO2IntStatR - 0x4002 80A4 IO0IntStatF - 0x4002 8088 IO2IntStatF - 0x4002 80A8 IO0IntClr - 0x4002 808C IO2IntClr - 0x4002 80AC IOIntStatus - 0x4002 8080 [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. 9.5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080) This word accessible register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality. Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and P0.30 will be outputs. Table 104. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to 0x2009 C080) bit description Bit Symbol Value Description Reset value 31:0 FIO0DIR Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR 0x0 FIO1DIR controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31. FIO2DIR 0 FIO3DIR FIO4DIR 1 Controlled pin is input. Controlled pin is output. Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 105, too. Next to providing the same functions as the FIODIR register, these additional registers allow easier and faster access to the physical port pins. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 132 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 105. Fast GPIO port Direction control byte and half-word accessible register description Generic Register name Description Register Reset length (bits) value & access PORTn Register Address & Name FIOxDIR0 Fast GPIO Port x Direction 8 (byte) control register 0. Bit 0 in R/W FIOxDIR0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 0x00 FIO0DIR0 - 0x2009 C000 FIO1DIR0 - 0x2009 C020 FIO2DIR0 - 0x2009 C040 FIO3DIR0 - 0x2009 C060 FIO4DIR0 - 0x2009 C080 FIOxDIR1 Fast GPIO Port x Direction 8 (byte) control register 1. Bit 0 in R/W FIOxDIR1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 0x00 FIO0DIR1 - 0x2009 C001 FIO1DIR1 - 0x2009 C021 FIO2DIR1 - 0x2009 C041 FIO3DIR1 - 0x2009 C061 FIO4DIR1 - 0x2009 C081 FIOxDIR2 Fast GPIO Port x Direction 8 (byte) control register 2. Bit 0 in R/W FIOxDIR2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 0x00 FIO0DIR2 - 0x2009 C002 FIO1DIR2 - 0x2009 C022 FIO2DIR2 - 0x2009 C042 FIO3DIR2 - 0x2009 C062 FIO4DIR2 - 0x2009 C082 FIOxDIR3 Fast GPIO Port x Direction 8 (byte) control register 3. Bit 0 in R/W FIOxDIR3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 0x00 FIO0DIR3 - 0x2009 C003 FIO1DIR3 - 0x2009 C023 FIO2DIR3 - 0x2009 C043 FIO3DIR3 - 0x2009 C063 FIO4DIR3 - 0x2009 C083 FIOxDIRL Fast GPIO Port x Direction control Lower half-word register. Bit 0 in FIOxDIRL register corresponds to pin Px.0 … bit 15 to pin Px.15. 16 (half-word) 0x0000 FIO0DIRL - 0x2009 C000 R/W FIO1DIRL - 0x2009 C020 FIO2DIRL - 0x2009 C040 FIO3DIRL - 0x2009 C060 FIO4DIRL - 0x2009 C080 FIOxDIRU Fast GPIO Port x Direction control Upper half-word register. Bit 0 in FIOxDIRU register corresponds to Px.16 … bit 15 to Px.31. 16 (half-word) 0x0000 FIO0DIRU - 0x2009 C002 R/W FIO1DIRU - 0x2009 C022 FIO2DIRU - 0x2009 C042 FIO3DIRU - 0x2009 C062 FIO4DIRU - 0x2009 C082 9.5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009 C018 to 0x2009 C098) This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the FIOxSET has no effect. Reading the FIOxSET register returns the value of this register, as determined by previous writes to FIOxSET and FIOxCLR (or FIOxPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 133 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9.5.5). Table 106. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 to 0x2009 C098) bit description Bit Symbol Value Description Reset value 31:0 FIO0SET FIO1SET FIO2SET 0 FIO3SET FIO4SET 1 Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin 0x0 Px.0, bit 31 in FIOxSET controls pin Px.31. Controlled pin output is unchanged. Controlled pin output is set to HIGH. Aside from the 32-bit long and word only accessible FIOxSET register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 107, too. Next to providing the same functions as the FIOxSET register, these additional registers allow easier and faster access to the physical port pins. Table 107. Fast GPIO port output Set byte and half-word accessible register description Generic Register name Description Register Reset length (bits) value & access PORTn Register Address & Name FIOxSET0 Fast GPIO Port x output Set register 0. Bit 0 in FIOxSET0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 8 (byte) R/W 0x00 FIO0SET0 - 0x2009 C018 FIO1SET0 - 0x2009 C038 FIO2SET0 - 0x2009 C058 FIO3SET0 - 0x2009 C078 FIO4SET0 - 0x2009 C098 FIOxSET1 Fast GPIO Port x output Set register 1. Bit 0 in FIOxSET1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) R/W 0x00 FIO0SET1 - 0x2009 C019 FIO1SET1 - 0x2009 C039 FIO2SET1 - 0x2009 C059 FIO3SET1 - 0x2009 C079 FIO4SET1 - 0x2009 C099 FIOxSET2 Fast GPIO Port x output Set register 2. Bit 0 in FIOxSET2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 8 (byte) R/W 0x00 FIO0SET2 - 0x2009 C01A FIO1SET2 - 0x2009 C03A FIO2SET2 - 0x2009 C05A FIO3SET2 - 0x2009 C07A FIO4SET2 - 0x2009 C09A FIOxSET3 Fast GPIO Port x output Set register 3. Bit 0 in FIOxSET3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 8 (byte) R/W 0x00 FIO0SET3 - 0x2009 C01B FIO1SET3 - 0x2009 C03B FIO2SET3 - 0x2009 C05B FIO3SET3 - 0x2009 C07B FIO4SET3 - 0x2009 C09B FIOxSETL Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETL - 0x2009 C018 Lower half-word register. Bit 0 R/W FIO1SETL - 0x2009 C038 in FIOxSETL register FIO2SETL - 0x2009 C058 corresponds to pin Px.0 … bit FIO3SETL - 0x2009 C078 15 to pin Px.15. FIO4SETL - 0x2009 C098 FIOxSETU Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETU - 0x2009 C01A Upper half-word register. Bit 0 R/W FIO1SETU - 0x2009 C03A in FIOxSETU register FIO2SETU - 0x2009 C05A corresponds to Px.16 … bit FIO3SETU - 0x2009 C07A 15 to Px.31. FIO4SETU - 0x2009 C09A UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 134 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the FIOxSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to FIOxCLR has no effect. Access to a port pin via the FIOxCLR register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9.5.5). Table 108. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009 C01C to 0x2009 C09C) bit description Bit Symbol Value Description Reset value 31:0 FIO0CLR FIO1CLR FIO2CLR 0 FIO3CLR FIO4CLR 1 Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin 0x0 Px.0, bit 31 controls pin Px.31. Controlled pin output is unchanged. Controlled pin output is set to LOW. Aside from the 32-bit long and word only accessible FIOxCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 109, too. Next to providing the same functions as the FIOxCLR register, these additional registers allow easier and faster access to the physical port pins. Table 109. Fast GPIO port output Clear byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxCLR0 Fast GPIO Port x output Clear register 0. Bit 0 in FIOxCLR0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 8 (byte) WO 0x00 FIO0CLR0 - 0x2009 C01C FIO1CLR0 - 0x2009 C03C FIO2CLR0 - 0x2009 C05C FIO3CLR0 - 0x2009 C07C FIO4CLR0 - 0x2009 C09C FIOxCLR1 Fast GPIO Port x output Clear register 1. Bit 0 in FIOxCLR1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) WO 0x00 FIO0CLR1 - 0x2009 C01D FIO1CLR1 - 0x2009 C03D FIO2CLR1 - 0x2009 C05D FIO3CLR1 - 0x2009 C07D FIO4CLR1 - 0x2009 C09D FIOxCLR2 Fast GPIO Port x output Clear register 2. Bit 0 in FIOxCLR2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 8 (byte) WO 0x00 FIO0CLR2 - 0x2009 C01E FIO1CLR2 - 0x2009 C03E FIO2CLR2 - 0x2009 C05E FIO3CLR2 - 0x2009 C07E FIO4CLR2 - 0x2009 C09E UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 135 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 109. Fast GPIO port output Clear byte and half-word accessible register description …continued Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxCLR3 Fast GPIO Port x output Clear register 3. Bit 0 in FIOxCLR3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 8 (byte) WO 0x00 FIO0CLR3 - 0x2009 C01F FIO1CLR3 - 0x2009 C03F FIO2CLR3 - 0x2009 C05F FIO3CLR3 - 0x2009 C07F FIO4CLR3 - 0x2009 C09F FIOxCLRL Fast GPIO Port x output Clear Lower half-word register. Bit 0 in FIOxCLRL register corresponds to pin Px.0 … bit 15 to pin Px.15. 16 (half-word) WO 0x0000 FIO0CLRL - 0x2009 C01C FIO1CLRL - 0x2009 C03C FIO2CLRL - 0x2009 C05C FIO3CLRL - 0x2009 C07C FIO4CLRL - 0x2009 C09C FIOxCLRU Fast GPIO Port x output Clear Upper half-word register. Bit 0 in FIOxCLRU register corresponds to pin Px.16 … bit 15 to Px.31. 16 (half-word) WO 0x0000 FIO0CLRU - 0x2009 C01E FIO1CLRU - 0x2009 C03E FIO2CLRU - 0x2009 C05E FIO3CLRU - 0x2009 C07E FIO4CLRU - 0x2009 C09E 9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 C014 to 0x2009 C094) This register provides the value of port pins that are configured to perform only digital functions. The register will give the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the corresponding FIOxPIN register. If a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital features of the pin. In that case, the pin value read in the FIOxPIN register is not valid. Writing to the FIOxPIN register stores the value in the port output register, bypassing the need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9.5.5). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 136 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Only pins masked with zeros in the Mask register (see Section 9.5.5) will be correlated to the current content of the Fast GPIO port pin value register. Table 110. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to 0x2009 C094) bit description Bit Symbol Value Description Reset value 31:0 FIO0VAL FIO1VAL FIO2VAL FIO3VAL FIO4VAL 0 Fast GPIO output value bits. Bit 0 corresponds to pin Px.0, bit 31 0x0 corresponds to pin Px.31. Only bits also set to 0 in the FIOxMASK register are affected by a write or show the pin’s actual logic state. Reading a 0 indicates that the port pin’s current state is LOW. Writing a 0 sets the output register value to LOW. 1 Reading a 1 indicates that the port pin’s current state is HIGH. Writing a 1 sets the output register value to HIGH. Aside from the 32-bit long and word only accessible FIOxPIN register, every fast GPIO port can also be controlled via several byte and half-word accessible register listed in Table 111, too. Next to providing the same functions as the FIOxPIN register, these additional registers allow easier and faster access to the physical port pins. Table 111. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name Description Register Reset length (bits) value & access PORTn Register Address & Name FIOxPIN0 Fast GPIO Port x Pin value register 0. Bit 0 in FIOxPIN0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 8 (byte) R/W 0x00 FIO0PIN0 - 0x2009 C014 FIO1PIN0 - 0x2009 C034 FIO2PIN0 - 0x2009 C054 FIO3PIN0 - 0x2009 C074 FIO4PIN0 - 0x2009 C094 FIOxPIN1 Fast GPIO Port x Pin value register 1. Bit 0 in FIOxPIN1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) R/W 0x00 FIO0PIN1 - 0x2009 C015 FIO1PIN1 - 0x2009 C035 FIO2PIN1 - 0x2009 C055 FIO3PIN1 - 0x2009 C075 FIO4PIN1 - 0x2009 C095 FIOxPIN2 Fast GPIO Port x Pin value register 2. Bit 0 in FIOxPIN2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 8 (byte) R/W 0x00 FIO0PIN2 - 0x2009 C016 FIO1PIN2 - 0x2009 C036 FIO2PIN2 - 0x2009 C056 FIO3PIN2 - 0x2009 C076 FIO4PIN2 - 0x2009 C096 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 137 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 111. Fast GPIO port Pin value byte and half-word accessible register description …continued Generic Register name Description Register Reset length (bits) value & access PORTn Register Address & Name FIOxPIN3 Fast GPIO Port x Pin value register 3. Bit 0 in FIOxPIN3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 8 (byte) R/W 0x00 FIO0PIN3 - 0x2009 C017 FIO1PIN3 - 0x2009 C037 FIO2PIN3 - 0x2009 C057 FIO3PIN3 - 0x2009 C077 FIO4PIN3 - 0x2009 C097 FIOxPINL Fast GPIO Port x Pin value Lower half-word register. Bit 0 in FIOxPINL register corresponds to pin Px.0 … bit 15 to pin Px.15. 16 (half-word) 0x0000 FIO0PINL - 0x2009 C014 R/W FIO1PINL - 0x2009 C034 FIO2PINL - 0x2009 C054 FIO3PINL - 0x2009 C074 FIO4PINL - 0x2009 C094 FIOxPINU Fast GPIO Port x Pin value Upper half-word register. Bit 0 in FIOxPINU register corresponds to pin Px.16 … bit 15 to Px.31. 16 (half-word) 0x0000 FIO0PINU - 0x2009 C016 R/W FIO1PINU - 0x2009 C036 FIO2PINU - 0x2009 C056 FIO3PINU - 0x2009 C076 FIO4PINU - 0x2009 C096 9.5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK 0x2009 C010 to 0x2009 C090) This register is used to select port pins that will and will not be affected by write accesses to the FIOxPIN, FIOxSET or FIOxCLR register. Mask register also filters out port’s content when the FIOxPIN register is read. A zero in this register’s bit enables an access to the corresponding physical pin via a read or write access. If a bit in this register is one, corresponding pin will not be changed with write access and if read, will not be reflected in the updated FIOxPIN register. For software examples, see Section 9.6. Table 112. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010 to 0x2009 C090) bit description Bit Symbol Value Description Reset value 31:0 FIO0MASK FIO1MASK 0 FIO2MASK FIO3MASK FIO4MASK 1 Fast GPIO physical pin access control. 0x0 Controlled pin is affected by writes to the port’s FIOxSET, FIOxCLR, and FIOxPIN register(s). Current state of the pin can be read from the FIOxPIN register. Controlled pin is not affected by writes into the port’s FIOxSET, FIOxCLR and FIOxPIN register(s). When the FIOxPIN register is read, this bit will not be updated with the state of the physical pin. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 138 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 113, too. Next to providing the same functions as the FIOxMASK register, these additional registers allow easier and faster access to the physical port pins. Table 113. Fast GPIO port Mask byte and half-word accessible register description Generic Register name Description Register Reset PORTn Register length (bits) value Address & Name & access FIOxMASK0 Fast GPIO Port x Mask register 0. Bit 0 in FIOxMASK0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 8 (byte) R/W 0x0 FIO0MASK0 - 0x2009 C010 FIO1MASK0 - 0x2009 C030 FIO2MASK0 - 0x2009 C050 FIO3MASK0 - 0x2009 C070 FIO4MASK0 - 0x2009 C090 FIOxMASK1 Fast GPIO Port x Mask register 1. Bit 0 in FIOxMASK1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) R/W 0x0 FIO0MASK1 - 0x2009 C011 FIO1MASK1 - 0x2009 C031 FIO2MASK1 - 0x2009 C051 FIO3MASK1 - 0x2009 C071 FIO4MASK1 - 0x2009 C091 FIOxMASK2 Fast GPIO Port x Mask 8 (byte) register 2. Bit 0 in R/W FIOxMASK2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 0x0 FIO0MASK2 - 0x2009 C012 FIO1MASK2 - 0x2009 C032 FIO2MASK2 - 0x2009 C052 FIO3MASK2 - 0x2009 C072 FIO4MASK2 - 0x2009 C092 FIOxMASK3 Fast GPIO Port x Mask 8 (byte) register 3. Bit 0 in R/W FIOxMASK3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 0x0 FIO0MASK3 - 0x2009 C013 FIO1MASK3 - 0x2009 C033 FIO2MASK3 - 0x2009 C053 FIO3MASK3 - 0x2009 C073 FIO4MASK3 - 0x2009 C093 FIOxMASKL Fast GPIO Port x Mask 16 0x0 FIO0MASKL - 0x2009 C010 Lower half-word register. (half-word) FIO1MASKL - 0x2009 C030 Bit 0 in FIOxMASKL R/W FIO2MASKL - 0x2009 C050 register corresponds to pin FIO3MASKL - 0x2009 C070 Px.0 … bit 15 to pin Px.15. FIO4MASKL - 0x2009 C090 FIOxMASKU Fast GPIO Port x Mask 16 0x0 FIO0MASKU - 0x2009 C012 Upper half-word register. (half-word) FIO1MASKU - 0x2009 C032 Bit 0 in FIOxMASKU R/W FIO2MASKU - 0x2009 C052 register corresponds to pin FIO3MASKU - 0x2009 C072 Px.16 … bit 15 to Px.31. FIO4MASKU - 0x2009 C092 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 139 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only status one bit per port is required. Table 114. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit description Bit Symbol Value Description Reset value 0 P0Int Port 0 GPIO interrupt pending. 0 0 There are no pending interrupts on Port 0. 1 There is at least one pending interrupt on Port 0. 1- - Reserved. The value read from a reserved bit is not defined. NA 2 P2Int Port 2 GPIO interrupt pending. 0 0 There are no pending interrupts on Port 2. 1 There is at least one pending interrupt on Port 2. 31:2 - - Reserved. The value read from a reserved bit is not defined. NA 9.5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 0 pin. Table 115. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description Bit Symbol Value Description Reset value 0 P0.0ER Enable rising edge interrupt for P0.0. 0 0 Rising edge interrupt is disabled on P0.0. 1 Rising edge interrupt is enabled on P0.0. 1 P0.1ER Enable rising edge interrupt for P0.1. 0 2 P0.2ER Enable rising edge interrupt for P0.2. 0 3 P0.3ER Enable rising edge interrupt for P0.3. 0 4 P0.4ER[1] Enable rising edge interrupt for P0.4. 0 5 P0.5ER[1] Enable rising edge interrupt for P0.5. 0 6 P0.6ER Enable rising edge interrupt for P0.6. 0 7 P0.7ER Enable rising edge interrupt for P0.7. 0 8 P0.8ER Enable rising edge interrupt for P0.8. 0 9 P0.9ER Enable rising edge interrupt for P0.9. 0 10 P0.10ER Enable rising edge interrupt for P0.10. 0 11 P0.11ER Enable rising edge interrupt for P0.11. 0 14:12 - Reserved NA 15 P0.15ER Enable rising edge interrupt for P0.15. 0 16 P0.16ER Enable rising edge interrupt for P0.16. 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 140 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 115. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description …continued Bit Symbol Value Description Reset value 17 P0.17ER Enable rising edge interrupt for P0.17. 0 18 P0.18ER Enable rising edge interrupt for P0.18. 0 19 P0.19ER[1] Enable rising edge interrupt for P0.19. 0 20 P0.20ER[1] Enable rising edge interrupt for P0.20. 0 21 P0.21ER[1] Enable rising edge interrupt for P0.21. 0 22 P0.22ER Enable rising edge interrupt for P0.22. 0 23 P0.23ER[1] Enable rising edge interrupt for P0.23. 0 24 P0.24ER[1] Enable rising edge interrupt for P0.24. 0 25 P0.25ER Enable rising edge interrupt for P0.25. 0 26 P0.26ER Enable rising edge interrupt for P0.26. 0 27 P0.27ER[1] Enable rising edge interrupt for P0.27. 0 28 P0.28ER[1] Enable rising edge interrupt for P0.28. 0 29 P0.29ER Enable rising edge interrupt for P0.29. 0 30 P0.30ER Enable rising edge interrupt for P0.30. 0 31 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin. Table 116. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description Bit Symbol Value Description Reset value 0 P2.0ER Enable rising edge interrupt for P2.0. 0 0 Rising edge interrupt is disabled on P2.0. 1 Rising edge interrupt is enabled on P2.0. 1 P2.1ER Enable rising edge interrupt for P2.1. 0 2 P2.2ER Enable rising edge interrupt for P2.2. 0 3 P2.3ER Enable rising edge interrupt for P2.3. 0 4 P2.4ER Enable rising edge interrupt for P2.4. 0 5 P2.5ER Enable rising edge interrupt for P2.5. 0 6 P2.6ER Enable rising edge interrupt for P2.6. 0 7 P2.7ER Enable rising edge interrupt for P2.7. 0 8 P2.8ER Enable rising edge interrupt for P2.8. 0 9 P2.9ER Enable rising edge interrupt for P2.9. 0 10 P2.10ER Enable rising edge interrupt for P2.10. 0 11 P2.11ER[1] Enable rising edge interrupt for P2.11. 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 141 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 116. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description …continued Bit Symbol Value Description Reset value 12 P2.12ER[1] Enable rising edge interrupt for P2.12. 0 13 P2.13ER[1] Enable rising edge interrupt for P2.13. 0 31:14 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 0 pin. UM10360 User manual Table 117. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description Bit Symbol Value Description Reset value 0 P0.0EF Enable falling edge interrupt for P0.0 0 0 Falling edge interrupt is disabled on P0.0. 1 Falling edge interrupt is enabled on P0.0. 1 P0.1EF Enable falling edge interrupt for P0.1. 0 2 P0.2EF Enable falling edge interrupt for P0.2. 0 3 P0.3EF Enable falling edge interrupt for P0.3. 0 4 P0.4EF[1] Enable falling edge interrupt for P0.4. 0 5 P0.5EF[1] Enable falling edge interrupt for P0.5. 0 6 P0.6EF Enable falling edge interrupt for P0.6. 0 7 P0.7EF Enable falling edge interrupt for P0.7. 0 8 P0.8EF Enable falling edge interrupt for P0.8. 0 9 P0.9EF Enable falling edge interrupt for P0.9. 0 10 P0.10EF Enable falling edge interrupt for P0.10. 0 11 P0.11EF Enable falling edge interrupt for P0.11. 0 14:12 - Reserved. NA 15 P0.15EF Enable falling edge interrupt for P0.15. 0 16 P0.16EF Enable falling edge interrupt for P0.16. 0 17 P0.17EF Enable falling edge interrupt for P0.17. 0 18 P0.18EF Enable falling edge interrupt for P0.18. 0 19 P0.19EF[1] Enable falling edge interrupt for P0.19. 0 20 P0.20EF[1] Enable falling edge interrupt for P0.20. 0 21 P0.21EF[1] Enable falling edge interrupt for P0.21. 0 22 P0.22EF Enable falling edge interrupt for P0.22. 0 23 P0.23EF[1] Enable falling edge interrupt for P0.23. 0 24 P0.24EF[1] Enable falling edge interrupt for P0.24. 0 25 P0.25EF Enable falling edge interrupt for P0.25. 0 26 P0.26EF Enable falling edge interrupt for P0.26. 0 27 P0.27EF[1] Enable falling edge interrupt for P0.27. 0 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 142 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 117. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description …continued Bit Symbol Value Description Reset value 28 P0.28EF[1] Enable falling edge interrupt for P0.28. 0 29 P0.29EF Enable falling edge interrupt for P0.29. 0 30 P0.30EF Enable falling edge interrupt for P0.30. 0 31 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 2 pin. Table 118. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit description Bit Symbol Value Description Reset value 0 P2.0EF Enable falling edge interrupt for P2.0 0 0 Falling edge interrupt is disabled on P2.0. 1 Falling edge interrupt is enabled on P2.0. 1 P2.1EF Enable falling edge interrupt for P2.1. 0 2 P2.2EF Enable falling edge interrupt for P2.2. 0 3 P2.3EF Enable falling edge interrupt for P2.3. 0 4 P2.4EF Enable falling edge interrupt for P2.4. 0 5 P2.5EF Enable falling edge interrupt for P2.5. 0 6 P2.6EF Enable falling edge interrupt for P2.6. 0 7 P2.7EF Enable falling edge interrupt for P2.7. 0 8 P2.8EF Enable falling edge interrupt for P2.8. 0 9 P2.9EF Enable falling edge interrupt for P2.9. 0 10 P2.10EF Enable falling edge interrupt for P2.10. 0 11 P2.11EF[1] Enable falling edge interrupt for P2.11. 0 12 P2.12EF[1] Enable falling edge interrupt for P2.12. 0 13 P2.13EF[1] Enable falling edge interrupt for P2.13. 0 31:14 - Reserved. NA [1] Not available on 80-pin package. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 143 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR 0x4002 8084) Each bit in these read-only registers indicates the rising edge interrupt status for port 0. Table 119. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) bit description Bit Symbol Value Description Reset value 0 P0.0REI Status of Rising Edge Interrupt for P0.0 0 0 A rising edge has not been detected on P0.0. 1 Interrupt has been generated due to a rising edge on P0.0. 1 P0.1REI Status of Rising Edge Interrupt for P0.1. 0 2 P0.2REI Status of Rising Edge Interrupt for P0.2. 0 3 P0.3REI Status of Rising Edge Interrupt for P0.3. 0 4 P0.4REI[1] Status of Rising Edge Interrupt for P0.4. 0 5 P0.5REI[1] Status of Rising Edge Interrupt for P0.5. 0 6 P0.6REI Status of Rising Edge Interrupt for P0.6. 0 7 P0.7REI Status of Rising Edge Interrupt for P0.7. 0 8 P0.8REI Status of Rising Edge Interrupt for P0.8. 0 9 P0.9REI Status of Rising Edge Interrupt for P0.9. 0 10 P0.10REI Status of Rising Edge Interrupt for P0.10. 0 11 P0.11REI Status of Rising Edge Interrupt for P0.11. 0 14:12 - Reserved. NA 15 P0.15REI Status of Rising Edge Interrupt for P0.15. 0 16 P0.16REI Status of Rising Edge Interrupt for P0.16. 0 17 P0.17REI Status of Rising Edge Interrupt for P0.17. 0 18 P0.18REI Status of Rising Edge Interrupt for P0.18. 0 19 P0.19REI[1] Status of Rising Edge Interrupt for P0.19. 0 20 P0.20REI[1] Status of Rising Edge Interrupt for P0.20. 0 21 P0.21REI[1] Status of Rising Edge Interrupt for P0.21. 0 22 P0.22REI Status of Rising Edge Interrupt for P0.22. 0 23 P0.23REI[1] Status of Rising Edge Interrupt for P0.23. 0 24 P0.24REI[1] Status of Rising Edge Interrupt for P0.24. 0 25 P0.25REI Status of Rising Edge Interrupt for P0.25. 0 26 P0.26REI Status of Rising Edge Interrupt for P0.26. 0 27 P0.27REI[1] Status of Rising Edge Interrupt for P0.27. 0 28 P0.28REI[1] Status of Rising Edge Interrupt for P0.28. 0 29 P0.29REI Status of Rising Edge Interrupt for P0.29. 0 30 P0.30REI Status of Rising Edge Interrupt for P0.30. 0 31 - Reserved. NA [1] Not available on 80-pin package. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 144 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR 0x4002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for port 2. Table 120. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) bit description Bit Symbol Value Description Reset value 0 P2.0REI Status of Rising Edge Interrupt for P2.0 0 0 A rising edge has not been detected on P2.0. 1 Interrupt has been generated due to a rising edge on P2.0. 1 P2.1REI Status of Rising Edge Interrupt for P2.1. 0 2 P2.2REI Status of Rising Edge Interrupt for P2.2. 0 3 P2.3REI Status of Rising Edge Interrupt for P2.3. 0 4 P2.4REI Status of Rising Edge Interrupt for P2.4. 0 5 P2.5REI Status of Rising Edge Interrupt for P2.5. 0 6 P2.6REI Status of Rising Edge Interrupt for P2.6. 0 7 P2.7REI Status of Rising Edge Interrupt for P2.7. 0 8 P2.8REI Status of Rising Edge Interrupt for P2.8. 0 9 P2.9REI Status of Rising Edge Interrupt for P2.9. 0 10 P2.10REI Status of Rising Edge Interrupt for P2.10. 0 11 P2.11REI[1] Status of Rising Edge Interrupt for P2.11. 0 12 P2.12REI[1] Status of Rising Edge Interrupt for P2.12. 0 13 P2.13REI[1] Status of Rising Edge Interrupt for P2.13. 0 31:14 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF 0x4002 8088) Each bit in these read-only registers indicates the falling edge interrupt status for port 0. Table 121. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description Bit Symbol Value Description Reset value 0 P0.0FEI Status of Falling Edge Interrupt for P0.0 0 0 A falling edge has not been detected on P0.0. 1 Interrupt has been generated due to a falling edge on P0.0. 1 P0.1FEI Status of Falling Edge Interrupt for P0.1. 0 2 P0.2FEI Status of Falling Edge Interrupt for P0.2. 0 3 P0.3FEI Status of Falling Edge Interrupt for P0.3. 0 4 P0.4FEI[1] Status of Falling Edge Interrupt for P0.4. 0 5 P0.5FEI[1] Status of Falling Edge Interrupt for P0.5. 0 6 P0.6FEI Status of Falling Edge Interrupt for P0.6. 0 7 P0.7FEI Status of Falling Edge Interrupt for P0.7. 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 145 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 121. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description …continued Bit Symbol Value Description Reset value 8 P0.8FEI Status of Falling Edge Interrupt for P0.8. 0 9 P0.9FEI Status of Falling Edge Interrupt for P0.9. 0 10 P0.10FEI Status of Falling Edge Interrupt for P0.10. 0 11 P0.11FEI Status of Falling Edge Interrupt for P0.11. 0 14:12 - Reserved. NA 15 P0.15FEI Status of Falling Edge Interrupt for P0.15. 0 16 P0.16FEI Status of Falling Edge Interrupt for P0.16. 0 17 P0.17FEI Status of Falling Edge Interrupt for P0.17. 0 18 P0.18FEI Status of Falling Edge Interrupt for P0.18. 0 19 P0.19FEI[1] Status of Falling Edge Interrupt for P0.19. 0 20 P0.20FEI[1] Status of Falling Edge Interrupt for P0.20. 0 21 P0.21FEI[1] Status of Falling Edge Interrupt for P0.21. 0 22 P0.22FEI Status of Falling Edge Interrupt for P0.22. 0 23 P0.23FEI[1] Status of Falling Edge Interrupt for P0.23. 0 24 P0.24FEI[1] Status of Falling Edge Interrupt for P0.24. 0 25 P0.25FEI Status of Falling Edge Interrupt for P0.25. 0 26 P0.26FEI Status of Falling Edge Interrupt for P0.26. 0 27 P0.27FEI[1] Status of Falling Edge Interrupt for P0.27. 0 28 P0.28FEI[1] Status of Falling Edge Interrupt for P0.28. 0 29 P0.29FEI Status of Falling Edge Interrupt for P0.29. 0 30 P0.30FEI Status of Falling Edge Interrupt for P0.30. 0 31 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF 0x4002 80A8) Each bit in these read-only registers indicates the falling edge interrupt status for port 2. UM10360 User manual Table 122. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description Bit Symbol Value Description Reset value 0 P2.0FEI Status of Falling Edge Interrupt for P2.0 0 0 A falling edge has not been detected on P2.0. 1 Interrupt has been generated due to a falling edge on P2.0. 1 P2.1FEI Status of Falling Edge Interrupt for P2.1. 0 2 P2.2FEI Status of Falling Edge Interrupt for P2.2. 0 3 P2.3FEI Status of Falling Edge Interrupt for P2.3. 0 4 P2.4FEI Status of Falling Edge Interrupt for P2.4. 0 5 P2.5FEI Status of Falling Edge Interrupt for P2.5. 0 6 P2.6FEI Status of Falling Edge Interrupt for P2.6. 0 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 146 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 122. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description …continued Bit Symbol Value Description Reset value 7 P2.7FEI Status of Falling Edge Interrupt for P2.7. 0 8 P2.8FEI Status of Falling Edge Interrupt for P2.8. 0 9 P2.9FEI Status of Falling Edge Interrupt for P2.9. 0 10 P2.10FEI Status of Falling Edge Interrupt for P2.10. 0 11 P2.11FEI[1] Status of Falling Edge Interrupt for P2.11. 0 12 P2.12FEI[1] Status of Falling Edge Interrupt for P2.12. 0 13 P2.13FEI[1] Status of Falling Edge Interrupt for P2.13. 0 31:14 - Reserved. NA [1] Not available on 80-pin package. 9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 0 pin. Table 123. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Bit Symbol Value Description Reset value 0 P0.0CI Clear GPIO port Interrupts for P0.0 0 0 Corresponding bits in IOxIntStatR and IOxIntStatF are unchanged. 1 Corresponding bits in IOxIntStatR and IOxStatF are cleared. 1 P0.1CI Clear GPIO port Interrupts for P0.1. 0 2 P0.2CI Clear GPIO port Interrupts for P0.2. 0 3 P0.3CI Clear GPIO port Interrupts for P0.3. 0 4 P0.4CI[1] Clear GPIO port Interrupts for P0.4. 0 5 P0.5CI[1] Clear GPIO port Interrupts for P0.5. 0 6 P0.6CI Clear GPIO port Interrupts for P0.6. 0 7 P0.7CI Clear GPIO port Interrupts for P0.7. 0 8 P0.8CI Clear GPIO port Interrupts for P0.8. 0 9 P0.9CI Clear GPIO port Interrupts for P0.9. 0 10 P0.10CI Clear GPIO port Interrupts for P0.10. 0 11 P0.11CI Clear GPIO port Interrupts for P0.11. 0 14:12 - Reserved. NA 15 P0.15CI Clear GPIO port Interrupts for P0.15. 0 16 P0.16CI Clear GPIO port Interrupts for P0.16. 0 17 P0.17CI Clear GPIO port Interrupts for P0.17. 0 18 P0.18CI Clear GPIO port Interrupts for P0.18. 0 19 P0.19CI[1] Clear GPIO port Interrupts for P0.19. 0 20 P0.20CI[1] Clear GPIO port Interrupts for P0.20. 0 21 P0.21CI[1] Clear GPIO port Interrupts for P0.21. 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 147 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 123. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description …continued Bit Symbol Value Description 22 P0.22CI 23 P0.23CI[1] 24 P0.24CI[1] 25 P0.25CI 26 P0.26CI 27 P0.27CI[1] 28 P0.28CI[1] 29 P0.29CI 30 P0.30CI 31 - Clear GPIO port Interrupts for P0.22. Clear GPIO port Interrupts for P0.23. Clear GPIO port Interrupts for P0.24. Clear GPIO port Interrupts for P0.25. Clear GPIO port Interrupts for P0.26. Clear GPIO port Interrupts for P0.27. Clear GPIO port Interrupts for P0.28. Clear GPIO port Interrupts for P0.29. Clear GPIO port Interrupts for P0.30. Reserved. Reset value 0 0 0 0 0 0 0 0 0 NA [1] Not available on 80-pin package. 9.5.6.11 GPIO Interrupt Clear register for port 2 (IO2IntClr - 0x4002 80AC) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 2 pin. Table 124. GPIO Interrupt Clear register for port 2 (IO2IntClr - 0x4002 80AC) bit description Bit Symbol Value Description Reset value 0 P2.0CI Clear GPIO port Interrupts for P2.0 0 0 Corresponding bits in IOxIntStatR and IOxIntStatF are unchanged. 1 Corresponding bits in IOxIntStatR and IOxStatF are cleared. 1 P2.1CI Clear GPIO port Interrupts for P2.1. 0 2 P2.2CI Clear GPIO port Interrupts for P2.2. 0 3 P2.3CI Clear GPIO port Interrupts for P2.3. 0 4 P2.4CI Clear GPIO port Interrupts for P2.4. 0 5 P2.5CI Clear GPIO port Interrupts for P2.5. 0 6 P2.6CI Clear GPIO port Interrupts for P2.6. 0 7 P2.7CI Clear GPIO port Interrupts for P2.7. 0 8 P2.8CI Clear GPIO port Interrupts for P2.8. 0 9 P2.9CI Clear GPIO port Interrupts for P2.9. 0 10 P2.10CI Clear GPIO port Interrupts for P2.10. 0 11 P2.11CI[1] Clear GPIO port Interrupts for P2.11. 0 12 P2.12CI[1] Clear GPIO port Interrupts for P2.12. 0 13 P2.13CI[1] Clear GPIO port Interrupts for P2.13. 0 31:14 - Reserved. NA [1] Not available on 80-pin package. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 148 of 849 NXP Semiconductors UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.6 GPIO usage notes 9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ; FIO0PIN = 0x0000A500; Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; 9.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used, only pin/bit(s) written with 1 will be changed, while those written as 0 will remain unaffected. Writing to the FIOPIN register enables instantaneous output of a desired value on the parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs on that port: zeroes in the value will produce low level pin outputs and ones in the value will produce high level pin outputs. A subset of a port’s pins may be changed by using the FIOMASK register to define which pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that will be changed, and ones for all others. Solution 2 from Section 9.6.1 above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 149 of 849 UM10360 Chapter 10: LPC176x/5x Ethernet Rev. 3.1 — 2 April 2014 User manual 10.1 Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2. Clock: see Table 38. 3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes through the PINMODE registers, see Section 8.5. 4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from Power-down mode, see Section 4.8.8. 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 10.17.2. 10.2 Introduction UM10360 User manual The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU. The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix, it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum bandwidth to the Ethernet function. The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced Media Independent Interface) protocol and the on-chip MIIM (Media Independent Interface Management) serial bus, also referred to as MDIO (Management Data Input/Output). Table 125. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Definition AHB Advanced High-performance bus CRC Cyclic Redundancy Check DMA Direct Memory Access Double-word 64-bit entity FCS Frame Check Sequence (CRC) Fragment A (part of an) Ethernet frame; one or multiple fragments can add up to a single Ethernet frame. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 150 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 125. Ethernet acronyms, abbreviations, and definitions …continued Acronym or Abbreviation Definition Frame An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. Half-word 16-bit entity LAN Local Area Network MAC Media Access Control sublayer MII Media Independent Interface MIIM MII management Octet An 8-bit data entity, used in lieu of "byte" by IEEE 802.3 Packet A frame that is transported across Ethernet; a packet consists of a preamble, a start of frame delimiter and an Ethernet frame. PHY Ethernet Physical Layer RMII Reduced MII Rx Receive TCP/IP Transmission Control Protocol / Internet Protocol. The most common high-level protocol used with Ethernet. Tx Transmit VLAN Virtual LAN WoL Wake-up on LAN Word 32-bit entity 10.3 Features • Ethernet standards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – VLAN frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and prefetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic FCS insertion (CRC) for transmit. – Selectable automatic transmit frame padding. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 151 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through a standard Reduced MII (RMII) interface. – PHY register access is available via the Media Independent Interface Management (MIIM) interface. 10.4 Architecture and operation Figure 18 shows the internal architecture of the Ethernet block. BUS IN TER F ACE ETH ER N ET MAC R MII A DAP TER ET HE RN ET PHY register interface (AHB slave) HOST REGISTERS TRANSMIT FLOW CONTROL TRANSMIT DMA TRANSMIT RETRY RMII BUS IN T ERF AC E AHB BUS DMA interface (AHB master) ETHERNET BLOCK RECEIVE DMA RECEIVE BUFFER RECEIVE FILTER MIIM Fig 18. Ethernet block diagram The block diagram for the Ethernet block consists of: • The host registers module containing the registers in the software view and handling AHB accesses to the Ethernet block. The host registers connect to the transmit and receive data path as well as the MAC. • The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access on-chip SRAM for reading of descriptors, writing of status, and reading and writing data buffers. • The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface. • The transmit data path, including: UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 152 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames. • The receive data path, including: – The receive DMA manager which reads descriptors from memory and writes data and status to memory. – The Ethernet MAC which detects frame types by parsing part of the frame header. – The receive filter which can filter out certain Ethernet frames by applying different filtering schemes. – The receive buffer implementing a delay for receive frames to allow the filter to filter out certain frames before storing them to memory. 10.5 DMA engine functions The Ethernet block is designed to provide optimized performance via DMA hardware acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load many data transfers from the CPU. Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received. Descriptors are stored in arrays in memory, which are located by pointer registers in the Ethernet block. Other registers determine the size of the arrays, point to the next descriptor in each array that will be used by the DMA engine, and point to the next descriptor in each array that will be used by the Ethernet device driver. 10.6 Overview of DMA operation The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array in memory. All or part of an Ethernet frame may be contained in a memory buffer associated with a descriptor. When transmitting, the transmit DMA engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. When receiving, the receive DMA engine also uses as many descriptors as needed (one or more) to find places to store (scatter) all of the data in the received frame. The base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor array input/output pointers are contained in the Ethernet block. The descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the Ethernet block. The descriptor entries tell where related frame data is stored in memory, certain aspects of how the data is handled, and the result status of each Ethernet transaction. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 153 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. The two pointers create a circular queue in the descriptor array and allow both the DMA hardware and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. Similarly, driver software must set up pointers to data that will be transmitted by the Ethernet MAC, giving instructions for each fragment of data, and advancing the software transmit pointer for outgoing data. Hardware in the DMA engine reads this information and sends the data to the Ethernet MAC interface when possible, updating the status and advancing the hardware transmit pointer. 10.7 Ethernet Packet Figure 19 illustrates the different fields in an Ethernet packet. PREAMBLE 7 bytes start-of-frame delimiter 1 byte ethernet packet ETHERNET FRAME DESTINATION SOURCE OPTIONAL LEN ADDRESS ADDRESS VLAN TYPE PAYLOAD FCS DesA DesA 1st 2nd octet octet DesA 3rd octet DesA 4th octet DesA 5th octet DesA 6th octet SrcA 1st octet SrcA 2nd octet SrcA 3rd octet SrcA 4th octet SrcA 5th octet SrcA 6th octet LSB MSB bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 time Fig 19. Ethernet packet fields A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 154 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. 10.8 Overview 10.8.1 Partitioning The Ethernet block and associated device driver software offer the functionality of the Media Access Control (MAC) sublayer of the data link layer in the OSI reference model (see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving frames to the next higher protocol level, the MAC client layer, typically the Logical Link Control sublayer. The device driver software implements the interface to the MAC client layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to frames in memory and receives results back from the Ethernet block through interrupts. When a frame is transmitted, the software partially sets up the Ethernet frames by providing pointers to the destination address field, source address field, the length/type field, the MAC client data field and optionally the CRC in the frame check sequence field. Preferably concatenation of frame fields should be done by using the scatter/gather functionality of the Ethernet core to avoid unnecessary copying of data. The hardware adds the preamble and start frame delimiter fields and can optionally add the CRC, if requested by software. When a packet is received the hardware strips the preamble and start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device driver, including destination address, source address, length/type field, MAC client data and frame check sequence (FCS). Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that control receive and transmit data streams between the MAC and the AHB interface. Frames are passed via descriptor arrays located in host memory, so that the hardware can process many frames without software/CPU support. Frames can consist of multiple fragments that are accessed with scatter/gather DMA. The DMA managers optimize memory bandwidth using prefetching and buffering. A receive filter block is used to identify received frames that are not addressed to this Ethernet station, so that they can be discarded. The Rx filters include a perfect address filter and a hash filter. Wake-on-LAN power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the LAN. Wake-up frames are recognized by the receive filtering modules or by a Magic Frame detection technology. System wake-up occurs by triggering an interrupt. An interrupt logic block raises and masks interrupts and keeps track of the cause of interrupts. The interrupt block sends an interrupt request signal to the host system. Interrupts can be enabled, cleared and set by software. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 155 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded. The Ethernet block has a standard Reduced Media Independent Interface (RMII) to connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the AHB interface through the serial management connection of the MIIM bus, typically operating at 2.5 MHz. 10.8.2 Example PHY Devices Some examples of compatible PHY devices are shown in Table 126. Table 126. Example PHY Devices Manufacturer Broadcom ICS Intel LSI Logic Micrel National SMSC Part Number(s) BCM5221 ICS1893 LXT971A L80223, L80225, L80227 KS8721 DP83847, DP83846, DP83843 LAN83C185 10.9 Pin description Table 127 shows the signals used for connecting the Reduced Media Independent Interface (RMII) to the external PHY. Table 127. Ethernet RMII pin descriptions Pin Name Type Pin Description ENET_TX_EN Output Transmit data enable ENET_TXD[1:0] Output Transmit data, 2 bits ENET_RXD[1:0] Input Receive data, 2 bits. ENET_RX_ER Input Receive error. ENET_CRS Input Carrier sense/data valid. ENET_REF_CLK/ Input ENET_RX_CLK Reference clock Table 128 shows the signals used for Media Independent Interface Management (MIIM) of the external PHY. Table 128. Ethernet MIIM pin descriptions Pin Name Type Pin Description ENET_MDC Output MIIM clock. ENET_MDIO Input/Output MI data input and output UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 156 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.10 Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections. 10.10.1 Register map Table 129 lists the registers, register addresses and other basic information. The total AHB address space required is 4 kilobytes. After a hard reset or a soft reset via the RegReset bit of the Command register all bits in all registers are reset to 0 unless stated otherwise in the following register descriptions. Some registers will have unused bits which will return a 0 on a read via the AHB interface. Writing to unused register bits of an otherwise writable register will not have side effects. The register map consists of registers in the Ethernet MAC and registers around the core for controlling DMA transfers, flow control and filtering. Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to reserved addresses or reserved bits has no effect. Reading of write-only registers will return a read error on the AHB interface. Writing of read-only registers will return a write error on the AHB interface. Table 129. Ethernet register definitions Name Description MAC registers MAC1 MAC configuration register 1. MAC2 MAC configuration register 2. IPGT Back-to-Back Inter-Packet-Gap register. IPGR Non Back-to-Back Inter-Packet-Gap register. CLRT Collision window / Retry register. MAXF Maximum Frame register. SUPP PHY Support register. TEST Test register. MCFG MII Mgmt Configuration register. MCMD MII Mgmt Command register. MADR MII Mgmt Address register. MWTD MII Mgmt Write Data register. MRDD MII Mgmt Read Data register. MIND MII Mgmt Indicators register. SA0 Station Address 0 register. SA1 Station Address 1 register. SA2 Station Address 2 register. Control registers Command Command register. Access Reset Value Address R/W 0x8000 R/W 0 R/W 0 R/W 0 R/W 0x370F R/W 0x0600 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 0x5000 0000 0x5000 0004 0x5000 0008 0x5000 000C 0x5000 0010 0x5000 0014 0x5000 0018 0x5000 001C 0x5000 0020 0x5000 0024 0x5000 0028 0x5000 002C 0x5000 0030 0x5000 0034 0x5000 0040 0x5000 0044 0x5000 0048 R/W 0 0x5000 0100 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 157 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 129. Ethernet register definitions …continued Name Description Status Status register. RxDescriptor Receive descriptor base address register. RxStatus Receive status base address register. RxDescriptorNumber Receive number of descriptors register. RxProduceIndex Receive produce index register. RxConsumeIndex Receive consume index register. TxDescriptor Transmit descriptor base address register. TxStatus Transmit status base address register. TxDescriptorNumber Transmit number of descriptors register. TxProduceIndex Transmit produce index register. TxConsumeIndex Transmit consume index register. TSV0 Transmit status vector 0 register. TSV1 Transmit status vector 1 register. RSV Receive status vector register. FlowControlCounter Flow control counter register. FlowControlStatus Flow control status register. Rx filter registers RxFliterCtrl Receive filter control register. RxFilterWoLStatus Receive filter WoL status register. RxFilterWoLClear Receive filter WoL clear register. HashFilterL Hash filter table LSBs register. HashFilterH Hash filter table MSBs register. Module control registers IntStatus Interrupt status register. IntEnable Interrupt enable register. IntClear Interrupt clear register. IntSet Interrupt set register. PowerDown Power-down register. Access Reset Value RO 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 Address 0x5000 0104 0x5000 0108 0x5000 010C 0x5000 0110 0x5000 0114 0x5000 0118 0x5000 011C 0x5000 0120 0x5000 0124 0x5000 0128 0x5000 012C 0x5000 0158 0x5000 015C 0x5000 0160 0x5000 0170 0x5000 0174 0 0x5000 0200 0 0x5000 0204 0 0x5000 0208 0 0x5000 0210 0 0x5000 0214 RO 0 R/W 0 WO 0 WO 0 R/W 0 0x5000 0FE0 0x5000 0FE4 0x5000 0FE8 0x5000 0FEC 0x5000 0FF4 The third column in the table lists the accessibility of the register: read-only, write-only, read/write. All AHB register write transactions except for accesses to the interrupt registers are posted i.e. the AHB transaction will complete before write data is actually committed to the register. Accesses to the interrupt registers will only be completed by accepting the write data when the data has been committed to the register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 158 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.11 Ethernet MAC register definitions This section defines the bits in the individual registers of the Ethernet block register map. 10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000) The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit definition is shown in Table 130. Table 130. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description Bit Symbol Function Reset value 0 RECEIVE ENABLE Set this to allow receive frames to be received. Internally the MAC synchronizes 0 this control bit to the incoming receive stream. 1 PASS ALL RECEIVE When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal 0 FRAMES vs. Control). When disabled, the MAC does not pass valid Control frames. 2 RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control 0 frames. When disabled, received PAUSE Flow Control frames are ignored. 3 TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be 0 transmitted. When disabled, Flow Control frames are blocked. 4 LOOPBACK Setting this bit will cause the MAC Transmit interface to be looped back to the MAC 0 Receive interface. Clearing this bit results in normal operation. 7:5 - Unused 0x0 8 RESET TX Setting this bit will put the Transmit Function logic in reset. 0 9 RESET MCS / TX Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic 0 implements flow control. 10 RESET RX Setting this bit will put the Ethernet receive logic in reset. 0 11 RESET MCS / RX Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic 0x0 implements flow control. 13:12 - Reserved. User software should not write ones to reserved bits. The value read 0x0 from a reserved bit is not defined. 14 SIMULATION RESET Setting this bit will cause a reset to the random number generator within the 0 Transmit Function. 15 SOFT RESET Setting this bit will put all modules within the MAC in reset except the Host 1 Interface. 31:16 - Reserved. User software should not write ones to reserved bits. The value read 0x0 from a reserved bit is not defined. 10.11.2 MAC Configuration Register 2 (MAC2 - 0x5000 0004) The MAC configuration register 2 (MAC2) has an address of 0x5000 0004. Its bit definition is shown in Table 131. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 159 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 131. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Bit Symbol Function Reset value 0 FULL-DUPLEX When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, 0 the MAC operates in Half-Duplex mode. 1 FRAME LENGTH When enabled (set to ’1’), both transmit and receive frame lengths are compared to 0 CHECKING the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. 2 HUGE FRAME When enabled (set to ’1’), frames of any length are transmitted and received. 0 ENABLE 3 DELAYED CRC This bit determines the number of bytes, if any, of proprietary header information 0 that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. 4 CRC ENABLE Set this bit to append a CRC to every frame whether padding was required or not. 0 Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. 5 PAD / CRC ENABLE Set this bit to have the MAC pad all short frames. Clear this bit if frames presented 0 to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 133 - Pad Operation for details on the pad function. 6 VLAN PAD ENABLE Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid 0 CRC. Consult Table 133 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. 7 AUTO DETECT PAD Set this bit to cause the MAC to automatically detect the type of frame, either tagged 0 ENABLE or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 133 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. 8 PURE PREAMBLE When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure 0 ENFORCEMENT it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. 9 LONG PREAMBLE When enabled (set to ’1’), the MAC only allows receive packets which contain 0 ENFORCEMENT preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. 11:10 - Reserved. User software should not write ones to reserved bits. The value read 0x0 from a reserved bit is not defined. 12 NO BACKOFF When enabled (set to ’1’), the MAC will immediately retransmit following a collision 0 rather than using the Binary Exponential Backoff algorithm as specified in the Standard. 13 BACK PRESSURE / When enabled (set to ’1’), after the MAC incidentally causes a collision during back 0 NO BACKOFF pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. 14 EXCESS DEFER When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the 0 Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. 31:15 - Reserved. User software should not write ones to reserved bits. The value read 0x0 from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 160 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 132. Pad operation Type Auto detect VLAN pad pad enable enable MAC2 [7] MAC2 [6] Any x x Any 0 0 Any x 1 Any 1 0 Pad/CRC enable MAC2 [5] 0 1 1 1 Action No pad or CRC check Pad to 60 bytes, append CRC Pad to 64 bytes, append CRC If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to 64 bytes and append CRC. 10.11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008) The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0x5000 0008. Its bit definition is shown in Table 133. Table 133. Back-to-back Inter-packet-gap register (IPGT - address 0x5000 0008) bit description Bit Symbol Function Reset value 6:0 BACK-TO-BACK This is a programmable field representing the nibble time offset of the minimum 0x0 INTER-PACKET-GAP possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). 31:7 - Reserved. User software should not write ones to reserved bits. The value read 0x0 from a reserved bit is not defined. 10.11.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C) The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of 0x5000 000C. Its bit definition is shown in Table 134. Table 134. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description Bit Symbol Function Reset value 6:0 NON-BACK-TO-BACK This is a programmable field representing the Non-Back-to-Back 0x0 INTER-PACKET-GAP PART2 Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). 7 - Reserved. User software should not write ones to reserved bits. The value 0x0 read from a reserved bit is not defined. 14:8 NON-BACK-TO-BACK INTER-PACKET-GAP PART1 This is a programmable field representing the optional carrierSense 0x0 window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) 31:15 - Reserved. User software should not write ones to reserved bits. The value 0x0 read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 161 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010) The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit definition is shown in Table 135. Table 135. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description Bit Symbol Function Reset value 3:0 RETRANSMISSION This is a programmable field specifying the number of retransmission attempts 0xF MAXIMUM following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. 7:4 - Reserved. User software should not write ones to reserved bits. The value read from 0x0 a reserved bit is not defined. 13:8 COLLISION WINDOW This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. 0x37 31:14 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 10.11.6 Maximum Frame Register (MAXF - 0x5000 0014) The Maximum Frame register (MAXF) has an address of 0x5000 0014. Its bit definition is shown in Table 136. Table 136. Maximum Frame register (MAXF - address 0x5000 0014) bit description Bit Symbol Function Reset value 15:0 MAXIMUM FRAME This field resets to the value 0x0600, which represents a maximum receive frame of 0x0600 LENGTH 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. 31:16 - Unused 0x0 10.11.7 PHY Support Register (SUPP - 0x5000 0018) The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register provides additional control over the RMII interface. The bit definition of this register is shown in Table 137. Table 137. PHY Support register (SUPP - address 0x5000 0018) bit description Bit Symbol Function Reset value 7:0 - Unused 0x0 8 SPEED This bit configures the Reduced MII logic for the current operating speed. When set, 0 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. 31:9 - Unused 0x0 Unused bits in the PHY support register should be left as zeroes. 10.11.8 Test Register (TEST - 0x5000 001C) The Test register (TEST) has an address of 0x5000 001C. The bit definition of this register is shown in Table 138. These bits are used for testing purposes only. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 162 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 138. Test register (TEST - address 0x5000 ) bit description Bit Symbol Function Reset value 0 SHORTCUT PAUSE This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. 0 QUANTA 1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a 0 PAUSE Receive Control frame with a nonzero pause time parameter was received. 2 TEST Setting this bit will cause the MAC to assert backpressure on the link. Backpressure 0 BACKPRESSURE causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. 31:3 - Unused 0x0 10.11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020) The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit definition of this register is shown in Table 139. Table 139. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description Bit Symbol Function Reset value 0 SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a 0 range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. 1 SUPPRESS PREAMBLE Set this bit to cause the MII Management hardware to perform read/write cycles 0 without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. 5:2 CLOCK SELECT This field is used by the clock divide logic in creating the MII Management Clock 0 (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 140 below for the definition of values for this field. 14:6 - Unused 0x0 15 RESET MII MGMT This bit resets the MII Management hardware. 0 31:16 - Unused 0x0 UM10360 User manual Table 140. Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Host Clock divided by 4 Host Clock divided by 6 Host Clock divided by 8 Host Clock divided by 10 Host Clock divided by 14 Host Clock divided by 20 Host Clock divided by 28 Host Clock divided by 36 Host Clock divided by 40 Host Clock divided by 44 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 Bit 2 x 0 1 0 1 0 1 0 1 0 Maximum AHB clock supported 10 15 20 25 35 50 70 80[1] 90[1] 100[1] © NXP B.V. 2014. All rights reserved. 163 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 140. Clock select encoding Clock Select Bit 5 Host Clock divided by 48 1 Host Clock divided by 52 1 Host Clock divided by 56 1 Host Clock divided by 60 1 Host Clock divided by 64 1 Bit 4 0 1 1 1 1 Bit 3 1 0 0 1 1 Bit 2 1 0 1 0 1 Maximum AHB clock supported 120[1] 130[1] 140[1] 150[1] 160[1] [1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device. 10.11.10 MII Mgmt Command Register (MCMD - 0x5000 0024) The MII Mgmt Command register (MCMD) has an address of 0x5000 0024. The bit definition of this register is shown in Table 141. Table 141. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description Bit Symbol Function Reset value 0 READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is 0 returned in Register MRDD (MII Mgmt Read Data). 1 SCAN This bit causes the MII Management hardware to perform Read cycles continuously. This is 0 useful for monitoring Link Fail for example. 31:2 - Unused 0x0 10.11.11 MII Mgmt Address Register (MADR - 0x5000 0028) The MII Mgmt Address register (MADR) has an address of 0x5000 0028. The bit definition of this register is shown in Table 142. Table 142. MII Mgmt Address register (MADR - address 0x5000 0028) bit description Bit Symbol Function Reset value 4:0 REGISTER ADDRESS This field represents the 5-bit Register Address field of Mgmt 0x0 cycles. Up to 32 registers can be accessed. 7:5 - Unused 0x0 12:8 PHY ADDRESS This field represents the 5-bit PHY Address field of Mgmt 0x0 cycles. Up to 31 PHYs can be addressed (0 is reserved). 31:13 - Unused 0x0 10.11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C) The MII Mgmt Write Data register (MWTD) is a write-only register with an address of 0x5000 002C. The bit definition of this register is shown in Table 143. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 164 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 143. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description Bit Symbol Function Reset value 15:0 WRITE DATA When written, an MII Mgmt write cycle is performed using the 16-bit 0x0 data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). 31:16 - Unused 0x0 10.11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030) The MII Mgmt Read Data register (MRDD) is a read-only register with an address of 0x5000 0030. The bit definition of this register is shown in Table 144. Table 144. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description Bit Symbol Function Reset value 15:0 READ DATA Following an MII Mgmt Read Cycle, the 16-bit data can be read from 0x0 this location. 31:16 - Unused 0x0 10.11.14 MII Mgmt Indicators Register (MIND - 0x5000 0034) The MII Mgmt Indicators register (MIND) is a read-only register with an address of 0x5000 0034. The bit definition of this register is shown in Table 145. Table 145. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description Bit Symbol Function Reset value 0 BUSY When ’1’ is returned - indicates MII Mgmt is currently performing an 0 MII Mgmt Read or Write cycle. 1 SCANNING When ’1’ is returned - indicates a scan operation (continuous MII 0 Mgmt Read cycles) is in progress. 2 NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not 0 completed and the Read Data is not yet valid. 3 MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has 0 occurred. 31:4 - Unused 0x0 Here are two examples to access PHY via the MII Management Controller. For PHY Write if scan is not used: 1. Write 0 to MCMD 2. Write PHY address and register address to MADR 3. Write data to MWTD 4. Wait for busy bit to be cleared in MIND For PHY Read if scan is not used: 1. Write 1 to MCMD 2. Write PHY address and register address to MADR UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 165 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 3. Wait for busy bit to be cleared in MIND 4. Write 0 to MCMD 5. Read data from MRDD 10.11.15 Station Address 0 Register (SA0 - 0x5000 0040) The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of this register is shown in Table 146. Table 146. Station Address register (SA0 - address 0x5000 0040) bit description Bit Symbol Function 7:0 STATION ADDRESS, This field holds the second octet of the station address. 2nd octet 15:8 STATION ADDRESS, This field holds the first octet of the station address. 1st octet 31:16 - Unused Reset value 0x0 0x0 0x0 The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 19. 10.11.16 Station Address 1 Register (SA1 - 0x5000 0044) The Station Address 1 register (SA1) has an address of 0x5000 0044. The bit definition of this register is shown in Table 147. Table 147. Station Address register (SA1 - address 0x5000 0044) bit description Bit Symbol Function 7:0 STATION ADDRESS, This field holds the fourth octet of the station address. 4th octet 15:8 STATION ADDRESS, This field holds the third octet of the station address. 3rd octet 31:16 - Unused Reset value 0x0 0x0 0x0 The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 19. 10.11.17 Station Address 2 Register (SA2 - 0x5000 0048) The Station Address 2 register (SA2) has an address of 0x5000 0048. The bit definition of this register is shown in Table 148. Table 148. Station Address register (SA2 - address 0x5000 0048) bit description Bit Symbol Function 7:0 STATION ADDRESS, This field holds the sixth octet of the station address. 6th octet 15:8 STATION ADDRESS, This field holds the fifth octet of the station address. 5th octet 31:16 - Unused Reset value 0x0 0x0 0x0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 166 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 19. 10.12 Control register definitions 10.12.1 Command Register (Command - 0x5000 0100) The Command register (Command) register has an address of 0x5000 0100. Its bit definition is shown in Table 149. Table 149. Command register (Command - address 0x5000 0100) bit description Bit Symbol Function Reset value 0 RxEnable Enable receive. 0 1 TxEnable Enable transmit. 0 2 - Unused 0x0 3 RegReset When a ’1’ is written, all datapaths and the host registers are 0 reset. The MAC needs to be reset separately. 4 TxReset When a ’1’ is written, the transmit datapath is reset. 0 5 RxReset When a ’1’ is written, the receive datapath is reset. 0 6 PassRuntFrame When set to ’1’, passes runt frames smaller than 64 bytes to 0 memory unless they have a CRC error. If ’0’ runt frames are filtered out. 7 PassRxFilter When set to ’1’, disables receive filtering i.e. all frames 0 received are written to memory. 8 TxFlowControl Enable IEEE 802.3 / clause 31 flow control sending pause 0 frames in full duplex and continuous preamble in half duplex. 9 RMII When set to “1”, RMII mode is selected. This bit must be set to 0 one during Ethernet initialization. See Section 10.17.2. 10 FullDuplex When set to “1”, indicates full duplex operation. 0 31:11 - Unused 0x0 All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0. 10.12.2 Status Register (Status - 0x5000 0104) The Status register (Status) is a read-only register with an address of 0x5000 0104. Its bit definition is shown in Table 150. Table 150. Status register (Status - address 0x5000 0104) bit description Bit Symbol Function Reset value 0 RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive. 0 1 TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0 31:2 - Unused 0x0 The values represent the status of the two channels/data paths. When the status is 1, the channel is active, meaning: UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 167 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet • It is enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame. • Also, for the transmit channel, the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex. • Also, for the receive channel, the receive queue is not full i.e. ProduceIndex != ConsumeIndex - 1. The status transitions from active to inactive if the channel is disabled by a software reset of the Rx/TxEnable bit in the Command register and the channel has committed the status and data of the current frame to memory. The status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory. 10.12.3 Receive Descriptor Base Address Register (RxDescriptor 0x5000 0108) The Receive Descriptor base address register (RxDescriptor) has an address of 0x5000 0108. Its bit definition is shown in Table 151. Table 151. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108) bit description Bit Symbol Function Reset value 1:0 - Fixed to ’00’ - 31:2 RxDescriptor MSBs of receive descriptor base address. 0x0 The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. 10.12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C) The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. Table 152. receive Status Base Address register (RxStatus - address 0x5000 010C) bit description Bit Symbol Function Reset value 2:0 - Fixed to ’000’ - 31:3 RxStatus MSBs of receive status base address. 0x0 The receive status base address is a byte address aligned to a double word boundary i.e. LSB 2:0 are fixed to “000”. 10.12.5 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110) The Receive Number of Descriptors register (RxDescriptorNumber) has an address of 0x5000 0110. Its bit definition is shown in Table 153. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 168 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 153. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit description Bit Symbol Function Reset value 15:0 RxDescriptorNumber Number of descriptors in the descriptor array for which 0x0 RxDescriptor is the base address. The number of descriptors is minus one encoded. 31:16 - Unused 0x0 The receive number of descriptors register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.12.6 Receive Produce Index Register (RxProduceIndex - 0x5000 0114) The Receive Produce Index register (RxProduceIndex) is a read-only register with an address of 0x5000 0114. Its bit definition is shown in Table 154. Table 154. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit description Bit Symbol Function Reset value 15:0 RxProduceIndex Index of the descriptor that is going to be filled next by the 0x0 receive datapath. 31:16 - Unused 0x0 The receive produce index register defines the descriptor that is going to be filled next by the hardware receive process. After a frame has been received, hardware increments the index. The value is wrapped to 0 once the value of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.12.7 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118) The Receive consume index register (RxConsumeIndex) has an address of 0x5000 0118. Its bit definition is shown in Table 155. Table 155. Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit description Bit Symbol Function Reset value 15:0 RxConsumeIndex Index of the descriptor that is going to be processed next by the receive 31:16 - Unused 0x0 The receive consume register defines the descriptor that is going to be processed next by the software receive driver. The receive array is empty as long as RxProduceIndex equals RxConsumeIndex. As soon as the array is not empty, software can process the frame pointed to by RxConsumeIndex. After a frame has been processed by software, software should increment the RxConsumeIndex. The value must be wrapped to 0 once the value UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 169 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor 0x5000 011C) The Transmit Descriptor base address register (TxDescriptor) has an address of 0x5000 011C. Its bit definition is shown in Table 156. Table 156. Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C) bit description Bit Symbol Function Reset value 1:0 - Fixed to ’00’ - 31:2 TxDescriptor MSBs of transmit descriptor base address. 0x0 The transmit descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. 10.12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120) The Transmit Status base address register (TxStatus) has an address of 0x5000 0120. Its bit definition is shown in Table 157. Table 157. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit description Bit Symbol Function Reset value 1:0 - Fixed to ’00’ - 31:2 TxStatus MSBs of transmit status base address. 0x0 The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of statuses. 10.12.10 Transmit Number of Descriptors Register (TxDescriptorNumber 0x5000 0124) The Transmit Number of Descriptors register (TxDescriptorNumber) has an address of 0x5000 0124. Its bit definition is shown in Table 158. Table 158. Transmit Number of Descriptors register (TxDescriptorNumber - address 0x5000 0124) bit description Bit Symbol Function Reset value 15:0 TxDescriptorNumber Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. 31:16 - Unused 0x0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 170 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.12.11 Transmit Produce Index Register (TxProduceIndex - 0x5000 0128) The Transmit Produce Index register (TxProduceIndex) has an address of 0x5000 0128. Its bit definition is shown in Table 159. Table 159. Transmit Produce Index register (TxProduceIndex - address 0x5000 0128) bit description Bit Symbol Function Reset value 15:0 TxProduceIndex Index of the descriptor that is going to be filled next by the 0x0 transmit software driver. 31:16 - Unused 0x0 The transmit produce index register defines the descriptor that is going to be filled next by the software transmit driver. The transmit descriptor array is empty as long as TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start transmitting frames as soon as the descriptor array is not empty. After a frame has been processed by software, it should increment the TxProduceIndex. The value must be wrapped to 0 once the value of TxDescriptorNumber has been reached. If the TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software should stop producing new descriptors until hardware has transmitted some frames and updated the TxConsumeIndex. 10.12.12 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C) The Transmit Consume Index register (TxConsumeIndex) is a read-only register with an address of 0x5000 012C. Its bit definition is shown in Table 160. Table 160. Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit description Bit Symbol Function Reset value 15:0 TxConsumeIndex Index of the descriptor that is going to be transmitted next by 0x0 the transmit datapath. 31:16 - Unused 0x0 The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. 10.12.13 Transmit Status Vector 0 Register (TSV0 - 0x5000 0158) The Transmit Status Vector 0 register (TSV0) is a read-only register with an address of 0x5000 0158. The transmit status vector registers store the most recent transmit status returned by the MAC. Since the status vector consists of more than 4 bytes, status is UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 171 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet distributed over two registers TSV0 and TSV1. These registers are provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Table 161 lists the bit definitions of the TSV0 register. Table 161. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description Bit Symbol Function Reset value 0 CRC error The attached CRC in the packet did not match the 0 internally generated CRC. 1 Length check error Indicates the frame length field does not match the actual 0 number of data items and is not a type field. 2 Length out of range[1] Indicates that frame type/length field was larger than 0 1500 bytes. 3 Done Transmission of packet was completed. 0 4 Multicast Packet’s destination was a multicast address. 0 5 Broadcast Packet’s destination was a broadcast address. 0 6 Packet Defer Packet was deferred for at least one attempt, but less than 0 an excessive defer. 7 Excessive Defer Packet was deferred in excess of 6071 nibble times in 0 100 Mbps or 24287 bit times in 10 Mbps mode. 8 Excessive Collision Packet was aborted due to exceeding of maximum allowed 0 number of collisions. 9 Late Collision Collision occurred beyond collision window, 512 bit times. 0 10 Giant Byte count in frame was greater than can be represented 0 in the transmit byte count field in TSV1. 11 Underrun Host side caused buffer underrun. 0 27:12 Total bytes The total number of bytes transferred including collided 0x0 attempts. 28 Control frame The frame was a control frame. 0 29 Pause The frame was a control frame with a valid PAUSE 0 opcode. 30 Backpressure Carrier-sense method backpressure was previously 0 applied. 31 VLAN Frame’s length/type field contained 0x8100 which is the 0 VLAN protocol identifier. [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 10.12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C) The Transmit Status Vector 1 register (TSV1) is a read-only register with an address of 0x5000 015C. The transmit status vector registers store the most recent transmit status returned by the MAC. Since the status vector consists of more than 4 bytes, status is distributed over two registers TSV0 and TSV1. These registers are provided for debug UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 172 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.Table 162 lists the bit definitions of the TSV1 register. Table 162. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description Bit Symbol Function Reset value 15:0 Transmit byte count The total number of bytes in the frame, not counting the 0x0 collided bytes. 19:16 Transmit collision count Number of collisions the current packet incurred during 0x0 transmission attempts. The maximum number of collisions (16) cannot be represented. 31:20 - Unused 0x0 10.12.15 Receive Status Vector Register (RSV - 0x5000 0160) The Receive status vector register (RSV) is a read-only register with an address of 0x5000 0160. The receive status vector register stores the most recent receive status returned by the MAC. This register is provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Table 163 lists the bit definitions of the RSV register. Table 163. Receive Status Vector register (RSV - address 0x5000 0160) bit description Bit Symbol Function Reset value 15:0 Received byte count Indicates length of received frame. 0x0 16 Packet previously Indicates that a packet was dropped. 0 ignored 17 RXDV event previously seen Indicates that the last receive event seen was not long 0 enough to be a valid packet. 18 Carrier event previously seen Indicates that at some time since the last receive statistics, 0 a carrier event was detected. 19 Receive code violation Indicates that received PHY data does not represent a 0 valid receive code. 20 CRC error The attached CRC in the packet did not match the 0 internally generated CRC. 21 Length check error Indicates the frame length field does not match the actual 0 number of data items and is not a type field. 22 Length out of range[1] Indicates that frame type/length field was larger than 0 1518 bytes. 23 Receive OK The packet had valid CRC and no symbol errors. 0 24 Multicast The packet destination was a multicast address. 0 25 Broadcast The packet destination was a broadcast address. 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 173 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 163. Receive Status Vector register (RSV - address 0x5000 0160) bit description …continued Bit Symbol Function Reset value 26 Dribble Nibble Indicates that after the end of packet another 1-7 bits were 0 received. A single nibble, called dribble nibble, is formed but not sent out. 27 Control frame The frame was a control frame. 0 28 PAUSE The frame was a control frame with a valid PAUSE 0 opcode. 29 Unsupported Opcode The current frame was recognized as a Control Frame but 0 contains an unknown opcode. 30 VLAN Frame’s length/type field contained 0x8100 which is the 0 VLAN protocol identifier. 31 - Unused 0x0 [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 10.12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170) The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170. Table 164 lists the bit definitions of the register. Table 164. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit description Bit Symbol Function Reset value 15:0 MirrorCounter In full duplex mode the MirrorCounter specifies the number 0x0 of cycles before re-issuing the Pause control frame. 31:16 PauseTimer In full-duplex mode the PauseTimer specifies the value 0x0 that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. 10.12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174) The Flow Control Status register (FlowControlStatus) is a read-only register with an address of 0x5000 0174. Table 165 lists the bit definitions of the register. Table 165. Flow Control Status register (FlowControlStatus - address 0x5000 0174) bit description Bit Symbol Function Reset value 15:0 MirrorCounterCurrent In full duplex mode this register represents the current 0x0 value of the datapath’s mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. 31:16 - Unused 0x0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 174 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.13 Receive filter register definitions 10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200) The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 166 lists the definition of the individual bits in the register. Table 166. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description Bit Symbol Function Reset value 0 AcceptUnicastEn When set to ’1’, all unicast frames are accepted. 0 1 AcceptBroadcastEn When set to ’1’, all broadcast frames are accepted. 0 2 AcceptMulticastEn When set to ’1’, all multicast frames are accepted. 0 3 AcceptUnicastHashEn When set to ’1’, unicast frames that pass the imperfect 0 hash filter are accepted. 4 AcceptMulticastHashEn When set to ’1’, multicast frames that pass the 0 imperfect hash filter are accepted. 5 AcceptPerfectEn When set to ’1’, the frames with a destination address 0 identical to the station address are accepted. 11:6 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 12 MagicPacketEnWoL When set to ’1’, the result of the magic packet filter will 0 generate a WoL interrupt when there is a match. 13 RxFilterEnWoL When set to ’1’, the result of the perfect address 0 matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. 31:14 - Unused 0x0 10.13.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204) The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only register with an address of 0x5000 0204. Table 167 lists the definition of the individual bits in the register. Table 167. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description Bit Symbol Function Reset value 0 AcceptUnicastWoL When the value is ’1’, a unicast frames caused WoL. 0 1 AcceptBroadcastWoL When the value is ’1’, a broadcast frame caused WoL. 0 2 AcceptMulticastWoL When the value is ’1’, a multicast frame caused WoL. 0 3 AcceptUnicastHashWoL When the value is ’1’, a unicast frame that passes the 0 imperfect hash filter caused WoL. 4 AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the 0 imperfect hash filter caused WoL. 5 AcceptPerfectWoL When the value is ’1’, the perfect address matching filter 0 caused WoL. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 175 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 167. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description …continued Bit Symbol Function Reset value 6- Unused 0x0 7 RxFilterWoL When the value is ’1’, the receive filter caused WoL. 0 8 MagicPacketWoL When the value is ’1’, the magic packet filter caused 0 WoL. 31:9 - Unused 0x0 The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be cleared by writing the RxFilterWoLClear register. 10.13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208) The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only register with an address of 0x5000 0208. Table 168 lists the definition of the individual bits in the register. Table 168. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit description Bit Symbol Function Reset value 0 AcceptUnicastWoLClr 1 AcceptBroadcastWoLClr 2 AcceptMulticastWoLClr When a ’1’ is written to one of these bits (0 to 5), the 0 corresponding status bit in the RxFilterWoLStatus 0 register is cleared. 0 3 AcceptUnicastHashWoLClr 0 4 AcceptMulticastHashWoLClr 0 5 AcceptPerfectWoLClr 0 6- Unused 0x0 7 RxFilterWoLClr 8 MagicPacketWoLClr When a ’1’ is written to one of these bits (7 and/or 8), 0 the corresponding status bit in the RxFilterWoLStatus 0 register is cleared. 31:9 - Unused 0x0 The bits in this register are write-only; writing resets the corresponding bits in the RxFilterWoLStatus register. 10.13.4 Hash Filter Table LSBs Register (HashFilterL - 0x5000 0210) The Hash Filter table LSBs register (HashFilterL) has an address of 0x5000 0210. Table 169 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10.17.10 “Receive filtering” on page 207. Table 169. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit description Bit Symbol Function 31:0 HashFilterL Bits 31:0 of the imperfect filter hash table for receive filtering. Reset value 0x0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 176 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214) The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. Table 170 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10.17.10 “Receive filtering” on page 207. Table 170. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description Bit Symbol Function Reset value 31:0 HashFilterH Bits 63:32 of the imperfect filter hash table for receive 0x0 filtering. 10.14 Module control register definitions 10.14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0) The Interrupt Status register (IntStatus) is a read-only register with an address of 0x5000 0FE0. The interrupt status register bit definition is shown in Table 171. Note that all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if there are wake-up events while clocks are disabled. Table 171. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description Bit Symbol Function Reset value 0 RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The 0 fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. 1 RxErrorInt Interrupt trigger on receive errors: AlignmentError, RangeError, 0 LengthError, SymbolError, CRCError or NoDescriptor or Overrun. 2 RxFinishedInt Interrupt triggered when all receive descriptors have been 0 processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. 3 RxDoneInt Interrupt triggered when a receive descriptor has been processed 0 while the Interrupt bit in the Control field of the descriptor was set. 4 TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The 0 fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. 5 TxErrorInt Interrupt trigger on transmit errors: LateCollision, 0 ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. 6 TxFinishedInt Interrupt triggered when all transmit descriptors have been 0 processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. 7 TxDoneInt Interrupt triggered when a descriptor has been transmitted while 0 the Interrupt bit in the Control field of the descriptor was set. 11:8 - Unused 0x0 12 SoftInt Interrupt triggered by software writing a 1 to the SoftintSet bit in 0 the IntSet register. 13 WakeupInt Interrupt triggered by a Wake-up event detected by the receive 0 filter. 31:14 - Unused 0x0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 177 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. 10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4) The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt enable register bit definition is shown in Table 172. Table 172. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description Bit Symbol Function Reset value 0 RxOverrunIntEn Enable for interrupt trigger on receive buffer overrun or 0 descriptor underrun situations. 1 RxErrorIntEn Enable for interrupt trigger on receive errors. 0 2 RxFinishedIntEn Enable for interrupt triggered when all receive descriptors have 0 been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. 3 RxDoneIntEn Enable for interrupt triggered when a receive descriptor has 0 been processed while the Interrupt bit in the Control field of the descriptor was set. 4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor 0 underrun situations. 5 TxErrorIntEn Enable for interrupt trigger on transmit errors. 0 6 TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors 0 have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. 7 TxDoneIntEn Enable for interrupt triggered when a descriptor has been 0 transmitted while the Interrupt bit in the Control field of the descriptor was set. 11:8 - Unused 0x0 12 SoftIntEn Enable for interrupt triggered by the SoftInt bit in the IntStatus 0 register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. 13 WakeupIntEn Enable for interrupt triggered by a Wake-up event detected by 0 the receive filter. 31:14 - Unused 0x0 10.14.3 Interrupt Clear Register (IntClear - 0x5000 0FE8) The Interrupt Clear register (IntClear) is a write-only register with an address of 0x5000 0FE8. The interrupt clear register bit definition is shown in Table 173. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 178 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 173. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Bit Symbol Function Reset value 0 RxOverrunIntClr Writing a ’1’ to one of these bits clears (0 to 7) the 0 1 RxErrorIntClr corresponding status bit in interrupt status register 0 IntStatus. 2 RxFinishedIntClr 0 3 RxDoneIntClr 0 4 TxUnderrunIntClr 0 5 TxErrorIntClr 0 6 TxFinishedIntClr 0 7 TxDoneIntClr 0 11:8 - Unused 0x0 12 SoftIntClr 13 WakeupIntClr Writing a ’1’ to one of these bits (12 and/or 13) clears the 0 corresponding status bit in interrupt status register 0 IntStatus. 31:14 - Unused 0x0 The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears the corresponding bit in the status register. Writing a 0 will not affect the interrupt status. 10.14.4 Interrupt Set Register (IntSet - 0x5000 0FEC) The Interrupt Set register (IntSet) is a write-only register with an address of 0x5000 0FEC. The interrupt set register bit definition is shown in Table 174. Table 174. Interrupt Set register (IntSet - address 0x5000 0FEC) bit description Bit Symbol Function 0 RxOverrunIntSet 1 RxErrorIntSet 2 RxFinishedIntSet 3 RxDoneIntSet 4 TxUnderrunIntSet 5 TxErrorIntSet 6 TxFinishedIntSet 7 TxDoneIntSet 11:8 - 12 SoftIntSet 13 WakeupIntSet 31:14 - Writing a ’1’ to one of these bits (0 to 7) sets the corresponding status bit in interrupt status register IntStatus. Unused Writing a ’1’ to one of these bits (12 and/or 13) sets the corresponding status bit in interrupt status register IntStatus. Unused Reset value 0 0 0 0 0 0 0 0 0x0 0 0 0x0 The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the corresponding bit in the status register. Writing a 0 will not affect the interrupt status. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 179 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.14.5 Power-Down Register (PowerDown - 0x5000 0FF4) The Power-Down register (PowerDown) is used to block all AHB accesses except accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The bit definition of the register is listed in Table 175. Table 175. Power-Down register (PowerDown - address 0x5000 0FF4) bit description Bit Symbol Function Reset value 30:0 - Unused 0x0 31 PowerDownMACAHB If true, all AHB accesses will return a read/write error, 0 except accesses to the Power-Down register. Setting the bit will return an error on all read and write accesses on the MACAHB interface except for accesses to the Power-Down register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 180 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.15 Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame. 10.15.1 Receive descriptors and statuses Figure 20 depicts the layout of the receive descriptors in memory. RxDescriptor 1 PACKET CONTROL 2 PACKET CONTROL 3 PACKET CONTROL 4 PACKET CONTROL 5 PACKET CONTROL DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER RxStatus StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC RxDescriptorNumber PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC Fig 20. Receive descriptor memory layout UM10360 User manual Receive descriptors are stored in an array in memory. The base address of the array is stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the RxDescriptorNumber register using a minus one encoding style e.g. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the RxStatus register, and must be aligned on an 8 byte address boundary. During operation (when the receive data path is enabled) the RxDescriptor, RxStatus and RxDescriptorNumber registers should not be modified. Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both registers act as counters starting at 0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex contains the index of the descriptor that is going to be filled with the next frame being All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 181 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex == RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors. Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes two words (8 bytes) in memory. Each receive descriptor consists of a pointer to the data buffer for storing receive data (Packet) and a control word (Control). The Packet field has a zero address offset, the control field has a 4 byte address offset with respect to the descriptor address as defined in Table 176. Table 176. Receive Descriptor Fields Symbol Address Bytes Description offset Packet 0x0 4 Base address of the data buffer for storing receive data. Control 0x4 4 Control information, see Table 177. The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. The definition of the control word bits is listed in Table 177. Table 177. Receive Descriptor Control Word Bit Symbol Description 10:0 Size Size in bytes of the data buffer. This is the size of the buffer reserved by the device driver for a frame or frame fragment i.e. the byte size of the buffer pointed to by the Packet field. The size is -1 encoded e.g. if the buffer is 8 bytes the size field should be equal to 7. 30:11 - Unused 31 Interrupt If true generate an RxDone interrupt when the data in this frame or frame fragment and the associated status information has been committed to memory. Table 178 lists the fields in the receive status elements from the status array. Table 178. Receive Status Fields Symbol Address Bytes Description offset StatusInfo 0x0 4 Receive status return flags, see Table 180. StatusHashCRC 0x4 4 The concatenation of the destination address hash CRC and the source address hash CRC. Each receive status consists of two words. The StatusHashCRC word contains a concatenation of the two 9-bit hash CRCs calculated from the destination and source addresses contained in the received frame. After detecting the destination and source addresses, StatusHashCRC is calculated once, then held for every fragment of the same frame. The concatenation of the two CRCs is shown in Table 179: UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 182 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Table 179. Receive Status HashCRC Word Bit Symbol Description 8:0 SAHashCRC Hash CRC calculated from the source address. 15:9 - Unused 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - Unused The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception. Table 180 lists the bit definitions in the StatusInfo word. Table 180. Receive status information word Bit Symbol Description 10:0 RxSize The size in bytes of the actual data transferred into one fragment buffer. In other words, this is the size of the frame or fragment as actually written by the DMA manager for one descriptor. This may be different from the Size bits of the Control field in the descriptor that indicate the size of the buffer allocated by the device driver. Size is -1 encoded e.g. if the buffer has 8 bytes the RxSize value will be 7. 17:11 - Unused 18 ControlFrame Indicates this is a control frame for flow control, either a pause frame or a frame with an unsupported opcode. 19 VLAN Indicates a VLAN frame. 20 FailFilter Indicates this frame has failed the Rx filter. These frames will not normally pass to memory. But due to the limitation of the size of the buffer, part of this frame may already be passed to memory. Once the frame is found to have failed the Rx filter, the remainder of the frame will be discarded without being passed to the memory. However, if the PassRxFilter bit in the Command register is set, the whole frame will be passed to memory. 21 Multicast Set when a multicast frame is received. 22 Broadcast Set when a broadcast frame is received. 23 CRCError The received frame had a CRC error. 24 SymbolError The PHY reports a bit error over the PHY interface during reception. 25 LengthError The frame length field value in the frame specifies a valid length, but does not match the actual data length. 26 RangeError[1] The received packet exceeds the maximum packet size. 27 AlignmentError An alignment error is flagged when dribble bits are detected and also a CRC error is detected. This is in accordance with IEEE std. 802.3/clause 4.3.2. 28 Overrun Receive overrun. The adapter can not accept the data stream. 29 NoDescriptor No new Rx descriptor is available and the frame is too long for the buffer size in the current receive descriptor. 30 LastFlag When set to 1, indicates this descriptor is for the last fragment of a frame. If the frame consists of a single fragment, this bit is also set to 1. 31 Error An error occurred during reception of this frame. This is a logical OR of AlignmentError, RangeError, LengthError, SymbolError, CRCError, and Overrun. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 183 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError, SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined. The status of the last fragment in the frame will copy the value for these bits from the MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and NoDescriptor bits. 10.15.2 Transmit descriptors and statuses Figure 21 depicts the layout of the transmit descriptors in memory. TxDescriptor 1 PACKET CONTROL 2 PACKET CONTROL 3 PACKET CONTROL 4 PACKET CONTROL 5 PACKET CONTROL DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER TxStatus StatusInfo StatusInfo StatusInfo StatusInfo StatusInfo TxDescriptorNumber PACKET CONTROL DATA BUFFER StatusInfo Fig 21. Transmit descriptor memory layout UM10360 User manual Transmit descriptors are stored in an array in memory. The lowest address of the transmit descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the TxStatus register, and must be aligned on a 4 byte address boundary. During operation (when the transmit data path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should not be modified. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 184 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver. The TxConsumeIndex contains the index of the next descriptor going to be transmitted by the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty. When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the transmit buffer is full and the software driver cannot add new descriptors until the hardware has transmitted one or more frames to free up descriptors. Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a pointer to the data buffer containing transmit data (Packet) and a control word (Control). The Packet field has a zero address offset, whereas the control field has a 4 byte address offset, see Table 181. Table 181. Transmit descriptor fields Symbol Address offset Bytes Description Packet 0x0 4 Base address of the data buffer containing transmit data. Control 0x4 4 Control information, see Table 182. The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. The definition of the control word bits is listed in Table 182. Table 182. Transmit descriptor control word Bit Symbol Description 10:0 Size Size in bytes of the data buffer. This is the size of the frame or fragment as it needs to be fetched by the DMA manager. In most cases it will be equal to the byte size of the data buffer pointed to by the Packet field of the descriptor. Size is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7. 25:11 - Unused 26 Override Per frame override. If true, bits 30:27 will override the defaults from the MAC internal registers. If false, bits 30:27 will be ignored and the default values from the MAC will be used. 27 Huge If true, enables huge frame, allowing unlimited frame sizes. When false, prevents transmission of more than the maximum frame length (MAXF[15:0]). 28 Pad If true, pad short frames to 64 bytes. 29 CRC If true, append a hardware CRC to the frame. 30 Last If true, indicates that this is the descriptor for the last fragment in the transmit frame. If false, the fragment from the next descriptor should be appended. 31 Interrupt If true, a TxDone interrupt will be generated when the data in this frame or frame fragment has been sent and the associated status information has been committed to memory. Table 183 shows the one field transmit status. Table 183. Transmit status fields Symbol Address offset Bytes StatusInfo 0x0 4 Description Transmit status return flags, see Table 184. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 185 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission. Table 184 lists the bit definitions in the StatusInfo word. Table 184. Transmit status information word Bit Symbol Description 20:0 - Unused 24:21 CollisionCount The number of collisions this packet incurred, up to the Retransmission Maximum. 25 Defer This packet incurred deferral, because the medium was occupied. This is not an error unless excessive deferral occurs. 26 ExcessiveDefer This packet incurred deferral beyond the maximum deferral limit and was aborted. 27 ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was aborted. 28 LateCollision An Out of window Collision was seen, causing packet abort. 29 Underrun A Tx underrun occurred due to the adapter not producing transmit data. 30 NoDescriptor The transmit stream was interrupted because a descriptor was not available. 31 Error An error occurred during transmission. This is a logical OR of Underrun, LateCollision, ExcessiveCollision, and ExcessiveDefer. For multi-fragment frames, the value of the LateCollision, ExcessiveCollision, ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will be 0. The status of the last fragment in the frame will copy the value for these bits from the MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits. 10.16 Ethernet block functional description This section defines the functions of the DMA capable 10/100 Ethernet MAC. After introducing the DMA concepts of the Ethernet block, and a description of the basic transmit and receive functions, this section elaborates on advanced features such as flow control, receive filtering, etc. 10.16.1 Overview The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet PHY connected through the RMII interface. Typically during system start-up, the Ethernet block will be initialized. Software initialization of the Ethernet block should include initialization of the descriptor and status arrays as well as the receiver fragment buffers. Remark: When initializing the Ethernet block, it is important to first configure the PHY and ensure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 186 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt. The hardware will receive packets from the PHY and apply filtering as configured by the software driver. While receiving a packet the hardware will read a descriptor from memory to find the location of the associated receiver data buffer. Receive data is written in the data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors. 10.16.2 AHB interface The registers of the Ethernet block connect to an AHB slave interface to allow access to the registers from the CPU. The AHB interface has a 32-bit data path, which supports only word accesses and has an address aperture of 4 kB. Table 129 lists the registers of the Ethernet block. All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear and IntEnable registers. AHB write operations are executed in order. If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses will return a read or write error except for accesses to the PowerDown register. Bus Errors The Ethernet block generates errors for several conditions: • The AHB interface will return a read error when there is an AHB read access to a write-only register; likewise a write error is returned when there is an AHB write access to the read-only register. An AHB read or write error will be returned on AHB read or write accesses to reserved registers. These errors are propagated back to the CPU. Registers defined as read-only and write-only are identified in Table 129. • If the PowerDown bit is set all accesses to AHB registers will result in an error response except for accesses to the PowerDown register. 10.17 Interrupts The Ethernet block has a single interrupt request output to the CPU (via the NVIC). The interrupt service routine must read the IntStatus register to determine the origin of the interrupt. All interrupt statuses can be set by software writing to the IntSet register; statuses can be cleared by software writing to the IntClear register. The transmit and receive data paths can only set interrupt statuses, they cannot clear statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for test purposes. 10.17.1 Direct Memory Access (DMA) Descriptor arrays UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 187 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames. Using buffering for frame descriptors, the memory traffic and memory bandwidth utilization of descriptors can be kept small. Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer containing a frame or a fragment, whereas the second field is a control word related to that frame or fragment. The software driver must write the base addresses of the descriptor and status arrays in the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of descriptors/statuses in each array must be written in the TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an array corresponds to the number of statuses in the associated status array. Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be aligned on a 4 byte (32bit)address boundary, while the receive status array must be aligned on a 8 byte (64bit) address boundary. Ownership of descriptors Both device driver software and Ethernet hardware can read and write the descriptor arrays at the same time in order to produce and consume descriptors. A descriptor is "owned" either by the device driver or by the Ethernet hardware. Only the owner of a descriptor reads or writes its value. Typically, the sequence of use and ownership of descriptors and statuses is as follows: a descriptor is owned and set up by the device driver; ownership of the descriptor/status is passed by the device driver to the Ethernet block, which reads the descriptor and writes information to the status field; the Ethernet block passes ownership of the descriptor back to the device driver, which uses the status information and then recycles the descriptor to be used for another frame. Software must pre-allocate the memory used to hold the descriptor arrays. Software can hand over ownership of descriptors and statuses to the hardware by incrementing (and wrapping if on the array boundary) the TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and status to software by updating the TxConsumeIndex/ RxProduceIndex registers. After handing over a descriptor to the receive and transmit DMA hardware, device driver software should not modify the descriptor or reclaim the descriptor by decrementing the TxProduceIndex/ RxConsumeIndex registers because descriptors may have been prefetched by the hardware. In this case the device driver software will have to wait until the frame has been transmitted or the device driver has to soft-reset the transmit and/or receive data paths which will also reset the descriptor arrays. Sequential order with wrap-around When descriptors are read from and statuses are written to the arrays, this is done in sequential order with wrap-around. Sequential order means that when the Ethernet block has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 188 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full. A descriptor array is empty when all descriptors are owned by the producer. A descriptor array is partially full if both producer and consumer own part of the descriptors and both are busy processing those descriptors. A descriptor array is full when all descriptors (except one) are owned by the consumer, so that the producer has no more room to process frames. Ownership of descriptors is indicated with the use of a consume index and a produce index. The produce index is the first element of the array owned by the producer. It is also the index of the array element that is next going to be used by the producer of frames (it may already be busy using it and subsequent elements). The consume index is the first element of the array that is owned by the consumer. It is also the number of the array element next to be consumed by the consumer of frames (it and subsequent elements may already be in the process of being consumed). If the consume index and the produce index are equal, the descriptor array is empty and all array elements are owned by the producer. If the consume index equals the produce index plus one, then the array is full and all array elements (except the one at the produce index) are owned by the consumer. With a full descriptor array, still one array element is kept empty, to be able to easily distinguish the full or empty state by looking at the value of the produce index and consume index. An array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of value 0 and a consume index of value 1. The wrap around of the arrays is taken into account when determining if a descriptor array is full, so a produce index that indicates the last element in the array and a consume index that indicates the first element in the array, also means the descriptor array is full. When the produce index and the consume index are unequal and the consume index is not the produce index plus one (with wrap around taken into account), then the descriptor array is partially full and both the consumer and producer own enough descriptors to be able to operate actively on the descriptor array. Interrupt bit The descriptors have an Interrupt bit, which is programmed by software. When the Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers flexible ways of managing the descriptor arrays. For instance, the device driver could add 10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the descriptor array. This would invoke the interrupt service routine before the transmit descriptor array is completely exhausted. The device driver could add another batch of frames to the descriptor array, without interrupting continuous transmission of frames. Frame fragments For maximum flexibility in frame storage, frames can be split up into multiple frame fragments with fragments located in different places in memory. In this case one descriptor is used for each frame fragment. So, a descriptor can point to a single frame or All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 189 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas. Another use of fragments is to be able to locate a frame header and frame payload in different places and to concatenate them without copy operations in the device driver. For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor is a new Ethernet frame. 10.17.2 Initialization After reset, the Ethernet software driver needs to initialize the Ethernet block. During initialization the software needs to: • Remove the soft reset condition from the MAC • Configure the PHY via the MIIM interface of the MAC. Remark: it is important to configure the PHY and insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used. • Select RMII mode • Configure the transmit and receive DMA engines, including the descriptor arrays • Configure the host registers (MAC1,MAC2 etc.) in the MAC • Enable the receive and transmit data paths Depending on the PHY, the software needs to initialize registers in the PHY via the MII Management interface. The software can read and write PHY registers by programming the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the MWTD register; read data and status information can be read from the MRDD and MIND registers. The Ethernet block supports RMII PHYs. During initialization software must select RMII mode by programming the Command register. Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be de-asserted. The phy_ref_clk must be running and internally connected during this operation. Transmit and receive DMA engines should be initialized by the device driver by allocating the descriptor and status arrays in memory. Transmit and receive functions have their own dedicated descriptor and status arrays. The base addresses of these arrays need to be programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The number of descriptors in an array matches the number of statuses in an array. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 190 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the number of descriptors register should be 3. After setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. The Packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor. Amongst others the Control field in the receive descriptor needs to contain the size of the data buffer using -1 encoding. The receive data path has a configurable filtering function for discarding/ignoring specific Ethernet frames. The filtering function should also be configured during initialization. After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The soft reset condition must be removed before the Ethernet block can be enabled. Enabling of the receive function is located in two places. The receive DMA manager needs to be enabled and the receive data path of the MAC needs to be enabled. To prevent overflow in the receive DMA engine the receive DMA engine should be enabled by setting the RxEnable bit in the Command register before enabling the receive data path in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register. The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the Command register. Before enabling the data paths, several options can be programmed in the MAC, such as automatic flow control, transmit to receive loop-back for verification, full/half duplex modes, etc. Base addresses of descriptor arrays and descriptor array sizes cannot be modified without a (soft) reset of the receive and transmit data paths. 10.17.3 Transmit process Overview This section outlines the transmission process. Device driver sets up descriptors and data If the descriptor array is full the device driver should wait for the descriptor arrays to become not full before writing to a descriptor in the descriptor array. If the descriptor array is not full, the device driver should use the descriptor numbered TxProduceIndex of the array pointed to by TxDescriptor. The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be transmitted. The Size field in the Command field of the descriptor should be set to the number of bytes in the fragment buffer, -1 encoded. Additional control information can be indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 191 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register. When there is a multi-fragment transmission for fragments other than the last, the Last bit in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To trigger an interrupt when the frame has been transmitted and transmission status has been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have the hardware add a CRC in the frame sequence control field of this Ethernet frame, set the CRC bit in the descriptor. This should be done if the CRC has not already been added by software. To enable automatic padding of small frames to the minimum required frame size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits CRC and Pad are both set to 1. The device driver can set up interrupts using the IntEnable register to wait for a signal of completion from the hardware or can periodically inspect (poll) the progress of transmission. It can also add new frames at the end of the descriptor array, while hardware consumes descriptors at the start of the array. The device driver can stop the transmit process by resetting the TxEnable bit in the Command register to 0. The transmission will not stop immediately; frames already being transmitted will be transmitted completely and the status will be committed to memory before deactivating the data path. The status of the transmit data path can be monitored by the device driver reading the TxStatus bit in the Status register. As soon as the transmit data path is enabled and the corresponding TxConsumeIndex and TxProduceIndex are not equal i.e. the hardware still needs to process frames from the descriptor array, the TxStatus bit in the Status register will return to 1 (active). Tx DMA manager reads the Tx descriptor array When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at the address determined by TxDescriptor and TxConsumeIndex. The number of descriptors requested is determined by the total number of descriptors owned by the hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes memory loading. Read data returned from memory is buffered and consumed as needed. Tx DMA manager transmits data After reading the descriptor the transmit DMA engine reads the associated frame data from memory and transmits the frame. After transfer completion, the Tx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status field. The value of the TxConsumeIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Tx DMA manager continues to transmit frames until the descriptor array is empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled. The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments. The Tx DMA manager gathers all the fragments from the host memory, visiting a string of All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 192 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found. Update ConsumeIndex Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back. The device driver software can keep track of the progress of the DMA manager by reading the TxConsumeIndex register to see how far along the transmit process is. When the Tx descriptor array is emptied completely, the TxConsumeIndex register retains its last value. Write transmission status After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame descriptor is updated by the DMA manager. If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame transmission, error flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set in the status. The CollisionCount field is set to the number of collisions the frame incurred, up to the Retransmission Maximum programmed in the Collision window/retry register of the MAC. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame fragment other than the last fragment, the error flags are returned via the AHB interface. If the Ethernet block detects a transmission error during transmission of a (multi-fragment) frame, all remaining fragments of the frame are still read via the AHB interface. After an error, the remaining transmit data is discarded by the Ethernet block. If there are errors during transmission of a multi-fragment frame the error statuses will be repeated until the last fragment of the frame. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. These may include error information if the error is detected early enough. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Thus, the status for the last fragment will always reflect any error that occurred anywhere in the frame. The status of the last frame transmission can also be inspected by reading the TSV0 and TSV1 registers. These registers do not report statuses on a fragment basis and do not store information of previously sent frames. They are provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. The status registers are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Transmission error handling If an error occurs during the transmit process, the Tx DMA manager will report the error via the transmission StatusInfo word written in the Status array and the IntStatus interrupt status register. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 193 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus register. Underrun errors can have three causes: • The next fragment in a multi-fragment transmission is not available. This is a nonfatal error. A NoDescriptor status will be returned on the previous fragment and the TxError bit in IntStatus will be set. • The transmission fragment data is not available when the Ethernet block has already started sending the frame. This is a nonfatal error. An Underrun status will be returned on transfer and the TxError bit in IntStatus will be set. • The flow of transmission statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This is a fatal error which can only be resolved by a soft reset of the hardware. The first and second situations are nonfatal and the device driver has to re-send the frame or have upper software layers re-send the frame. In the third case the hardware is in an undefined state and needs to be soft reset by setting the TxReset bit in the Command register. After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, the transmission of the erroneous frame will be aborted, remaining transmission data and frame fragments will be discarded and transmission will continue with the next frame in the descriptor array. Device drivers should catch the transmission errors and take action. Transmit triggers interrupts The transmit data path can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the TxDoneInt bit in the IntStatus register after sending the fragment and committing the associated transmission status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame the Interrupt bit in the descriptor can be used to generate an interrupt. • If the descriptor array is empty while the Ethernet hardware is enabled the hardware will set the TxFinishedInt bit of the IntStatus register. • If the AHB interface does not consume the transmission statuses at a sufficiently high bandwidth the transmission may underrun in which case the TxUnderrun bit will be set in the IntStatus register. This is a fatal error which requires a soft reset of the transmission queue. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 194 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet • In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Transmit example Figure 22 illustrates the transmit process in an example transmitting uses a frame header of 8 bytes and a frame payload of 12 bytes. 0x2008131B 0x20081314 TxDescriptor 0x200810EC TxStatus 0x200811F8 status array 0x200810EC Packet 0x20081314 0x200810F0 0 0 COonNtrToRl OL 7 0x200810F4 Packet 0x20081411 0x200810F8 0 0 CCOonNtrToRl OL 7 0x200810FC Packet 0x20081419 descriptor 1 descriptor 0 0x20081411 PACKET 0 HEADER (8 bytes) PACKET 0 PAYLOAD (12 bytes) 0x20081419 0x2008141C status 3 status 2 status 1 status 0 0x200811F8 StatusInfo 0x200811FC StatusInfo StatusInfo 0x20081200 StatusInfo 0x20081204 descriptor array 0x2008132B 0x20081324 descriptor 2 0x20081100 1 1 CCOonNtrToRl OL 3 0x20081104 Packet 0x20081324 0x20081108 0 0 CCOonNtrToRl OL 7 descriptor array descriptor 3 PACKET 1 HEADER (8 bytes) TxProduceIndex TxConsumeIndex TxDescriptorNumber =3 fragment buffers status array Fig 22. Transmit example memory and registers UM10360 User manual After reset the values of the DMA registers will be zero. During initialization the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 195 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit data path may be enabled by setting the TxEnable bit in the Command register. If the transmit data path is enabled while there are no further frames to send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the IntEnable register. Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will add a header to the frame. The frame header need not be immediately in front of the payload data in memory. The device driver can program the Tx DMA to collect header and payload data. To do so, the device driver will program the first descriptor to point at the frame header; the Last flag in the descriptor will be set to false/0 to indicate a multi-fragment transmission. The device driver will program the next descriptor to point at the actual payload data. The maximum size of a payload buffer is 2 kB so a single descriptor suffices to describe the payload buffer. For the sake of the example though the payload is distributed across two descriptors. After the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array describes the remaining 4 bytes of the frame. In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set in the last fragment of the frame in order to trigger an interrupt after the transmission completed. The Size field in the descriptor’s Control word is set to the number of bytes in the fragment buffer, -1 encoded. Note that in real device drivers, the payload will typically only be split across multiple descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). After setting up the descriptors for the transaction the device driver increments the TxProduceIndex register by 3 since three descriptors have been programmed. If the transmit data path was not enabled during initialization the device driver needs to enable the data path now. If the transmit data path is enabled the Ethernet block will start transmitting the frame as soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero after reset. The Tx DMA will start reading the descriptors from memory. The memory system will return the descriptors and the Ethernet block will accept them one by one while reading the transmit data fragments. As soon as transmission read data is returned from memory, the Ethernet block will try to start transmission on the Ethernet connection via the RMII interface. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 196 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information. In this example the device driver cannot add new descriptors as long as the Ethernet block has not incremented the TxConsumeIndex because the descriptor array is full (even though one descriptor is not programmed yet). Only after the hardware commits the status for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager can the device driver program the next (the fourth) descriptor. The fourth descriptor can already be programmed before completely transmitting the first frame. In this example the hardware adds the CRC to the frame. If the device driver software adds the CRC, the CRC trailer can be considered another frame fragment which can be added by doing another gather DMA. Each data byte is transmitted across the RMII interface as four 2-bit values. The Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if hardware CRC is enabled. Once transmission on the RMII interface commences the transmission cannot be interrupted without generating an underrun error, which is why descriptors and data read commands are issued as soon as possible and pipelined. Using an RMII PHY, the data communication between the Ethernet block and the PHY is communicated at 50 MHz. In 10 Mbps mode data will only be transmitted once every 10 clock cycles. 10.17.4 Receive process This section outlines the receive process including the activities in the device driver software. Device driver sets up descriptors After initializing the receive descriptor and status arrays to receive frames from the Ethernet connection, the receive data path should be enabled in the MAC1 register and the Control register. During initialization, each Packet pointer in the descriptors is set to point to a data fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt bit allows generation of an interrupt after a fragment buffer has been filled and its status has been committed to memory. After the initialization and enabling of the receive data path, all descriptors are owned by the receive hardware and should not be modified by the software unless hardware hands over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been received. The device driver is allowed to modify the descriptors after a (soft) reset of the receive data path. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 197 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex. The Ethernet block will start reading descriptors even before actual receive data arrives on the RMII interface (descriptor prefetching). The block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed. RX DMA manager receives data After reading the descriptor, the receive DMA engine waits for the MAC to return receive data from the RMII interface that passes the receive filter. Receive frames that do not match the filtering criteria are not passed to memory. Once a frame passes the receive filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA does not write beyond the size of the buffer. When a frame is received that is larger than a descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment in the frame will return a status where the LastFrag bit is set to 0. Only on the last fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the last of a frame, the buffer may not be filled completely. The first receive data of the next frame will be written to the fragment buffer of the next descriptor. After receiving a fragment, the Rx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of the RxProduceIndex is only updated after the fragment data and the fragment status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Rx DMA manager continues to receive frames until the descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the receive descriptor array is full any new receive data will generate an overflow error and interrupt. Update ProduceIndex Each time the Rx DMA manager commits a data fragment and the associated status word to memory, it completes the reception of a descriptor and increments the RxProduceIndex (taking wrap around into account) in order to hand the descriptor back to the device driver software. Software can re-use the descriptor for new receptions by handing it back to hardware when the receive data has been processed. The device driver software can keep track of the progress of the DMA manager by reading the RxProduceIndex register to see how far along the receive process is. When the Rx descriptor array is emptied completely, the RxProduceIndex retains its last value. Write reception status After the frame has been received from the RMII bus, the StatusInfo and StatusHashCRC words of the frame descriptor are updated by the DMA manager. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 198 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually written to the fragment buffer, -1 encoded. For fragments not being the last in the frame the RxSize will match the size of the buffer. The hash CRCs of the destination and source addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0. The status of the last received frame can also be inspected by reading the RSV register. The register does not report statuses on a fragment basis and does not store information of previously received frames. RSV is provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. Reception error handling When an error occurs during the receive process, the Rx DMA manager will report the error via the receive StatusInfo written in the Status array and the IntStatus interrupt status register. The receive process can generate several types of errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo, AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError, LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to be soft reset by setting the RxReset bit in the Command register. Overrun errors can have three causes: • In the case of a multi-fragment reception, the next descriptor may be missing. In this case the NoDescriptor field is set in the status word of the previous descriptor and the RxError in the IntStatus register is set. This error is nonfatal. • The data flow on the receiver data interface stalls, corrupting the packet. In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set. This error is nonfatal. • The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This error will corrupt the hardware state and requires the hardware to be soft reset. The error is detected and sets the Overrun bit in the IntStatus register. The first overrun situation will result in an incomplete frame with a NoDescriptor status and the RxError bit in IntStatus set. Software should discard the partially received frame. In the second overrun situation the frame data will be corrupt which results in the Overrun status bit being set in the Status word while the IntError interrupt bit is set. In the third case All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 199 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware. Device drivers should catch the above receive errors and take action. Receive triggers interrupts The receive data path can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an interrupt. • If the descriptor array is full while the Ethernet hardware is enabled, the hardware will set the RxFinishedInt bit of the IntStatus register. • If the AHB interface does not consume receive statuses at a sufficiently high bandwidth, the receive status process may overrun, in which case the RxOverrun bit will be set in the IntStatus register. • If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or CRCError), or a multi-fragment frame where the device driver did provide descriptors for the initial fragments but did not provide the descriptors for the rest of the fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Device driver processes receive data As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the device driver can read the descriptors that have been handed over to it by the hardware (RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words in the status array to check for multi-fragment receptions and receive errors. The device driver can forward receive data and status to upper software layers. After processing of data and status, the descriptors, statuses and data buffers may be recycled and handed back to hardware by incrementing the RxConsumeIndex. Receive example Figure 23 illustrates the receive process in an example receiving a frame of 19 bytes. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 200 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 0x20081410 0x20081409 RxDescriptor 0x200810EC RxStatus 0x200811F8 status array 0x200810EC PACKET 0x20081409 0x200810F0 1 CONTROL 7 0x200810F4 PACKET 0x20081411 0x200810F8 1 CONTROL 7 0x200810FC PACKET 0x20081419 Descriptor 1 Descriptor 0 0x20081419 0x20081411 FRAGMENT 0 BUFFER(8 bytes) FRAGMENT 1 BUFFER(8 bytes) FRAGMENT 2 BUFFER(3 bytes) 0x2008141B 0x20081418 Status 3 Status 2 Status 1 Status 0 StatusInfo 7 0x200811F8 StatusHashCRC StatusInfo 7 0x20081200 StatusHashCRC StatusInfo 2 0x20081208 StatusHashCRC StatusInfo 7 0x20081210 StatusHashCRC descriptor array 0x2008132C 0x20081325 Descriptor 2 0x20081100 1 CONTROL 7 0x20081104 PACKET 0x20081325 1 CONTROL 7 0x20081108 descriptor array Descriptor 3 FRAGMENT 3 BUFFER(8 bytes) RxProduceIndex RxConsumeIndex RxDescriptorNumber= 3 fragment buffers status array Fig 23. Receive Example Memory and Registers After reset, the values of the DMA registers will be zero. During initialization, the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. Since the number of descriptors matches the number of statuses, the status array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) in the RxDescriptor register, and the base address of the status array (0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized yet. After allocating the descriptors, a fragment buffer needs to be allocated for each of the descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base address of the fragment buffer is stored in the Packet field of the descriptors. The number of bytes in the fragment buffer is stored in the Size field of the descriptor Control word. The Interrupt field in the Control word of the descriptor can be set to generate an interrupt as soon as the descriptor has been filled by the receive process. In this example the fragment buffers are 8 bytes, so the value of the Size field in the Control word of the descriptor is set to 7. Note that in this example, the fragment buffers are actually a UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 201 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. The device driver should enable the receive process by writing a 1 to the RxEnable bit of the Command register, after which the MAC needs to be enabled by writing a 1 to the ‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts can be disabled by setting the relevant bits in the IntEnable register. After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In this example the number of descriptors is 4. Initially the RxProduceIndex and RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex == RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex RxProduceIndex - 1 =) 3 descriptors; note the wrapping. After enabling the receive function in the MAC, data reception will begin starting at the next frame i.e. if the receive function is enabled while the RMII interface is halfway through receiving a frame, the frame will be discarded and reception will start at the next frame. The Ethernet block will strip the preamble and start of frame delimiter from the frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the frame to the first fragment buffer. Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA will continue filling the second fragment buffer. Since this is a multi-fragment receive, the status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second fragment the Rx DMA will continue writing the third fragment. The status of the second fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing the three bytes in the third fragment buffer, the end of the frame has been reached and the status of the third fragment is written. The third fragment’s status will have the LastFrag bit set to 1 and the RxSize equal to 2 (3, -1 encoded). The next frame received from the RMII interface will be written to the fourth fragment buffer i.e. five bytes of the third buffer will be unused. The Rx DMA manager uses an internal tag protocol in the memory interface to check that the receive data and status have been committed to memory. After the status of the fragments are committed to memory, an RxDoneInt interrupt will be triggered, which activates the device driver to inspect the status information. In this example, all descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate an interrupt after committing data and status to memory. In this example the receive function cannot read new descriptors as long as the device driver does not increment the RxConsumeIndex, because the descriptor array is full (even though one descriptor is not programmed yet). Only after the device driver has forwarded the receive data to application software, and after the device driver has updated the RxConsumeIndex by incrementing it, will the Ethernet block can continue reading descriptors and receive data. The device driver will probably increment the RxConsumeIndex by 3, since the driver will forward the complete frame consisting of three fragments to the application, and hence free up three descriptors at the same time. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 202 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability, three descriptors are buffered. The value of the RxProduceIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The software device driver will process the receive data, after which the device driver will update the RxConsumeIndex. 10.17.5 Transmission retry If a collision on the Ethernet occurs, it usually takes place during the collision window spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this data can be used during the retry. A transmission retry within the first 64 bytes in a frame is fully transparent to the application and device driver software. When a collision occurs outside of the 64 byte collision window, a LateCollision error is triggered, and the transmission is aborted. After a LateCollision error, the remaining data in the transmit frame will be discarded. The Ethernet block will set the Error and LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the IntStatus register will be propagated to the CPU (via the NVIC). The device driver software should catch the interrupt and take appropriate actions. The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure the maximum number of retries before aborting the transmission. 10.17.6 Status hash CRC calculations For each received frame, the Ethernet block is able to detect the destination address and source address and from them calculate the corresponding hash CRCs. To perform the computation, the Ethernet block features two internal blocks: one is a controller synchronized with the beginning and the end of each frame, the second block is the CRC calculator. When a new frame is detected, internal signaling notifies the controller.The controller starts counting the incoming bytes of the frame, which correspond to the destination address bytes. When the sixth (and last) byte is counted, the controller notifies the calculator to store the corresponding 32-bit CRC into a first inner register. Then the controller repeats counting the next incoming bytes, in order to get synchronized with the source address. When the last byte of the source address is encountered, the controller again notifies the CRC calculator, which freezes until the next new frame. When the calculator receives this second notification, it stores the present 32-bit CRC into a second inner register. Then the CRCs remain frozen in their own registers until new notifications arise. The destination address and source address hash CRCs being written in the StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated by the CRC calculator. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 203 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 10.17.8 IEE 802.3/Clause 31 flow control Overview For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control using pause frames. This type of flow control may be used in full-duplex point-to-point connections. Flow control allows a receiver to stall a transmitter e.g. when the receive buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the transmitting side. Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles. Receive flow control In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control frames. When a pause frame is received on the Rx side of the Ethernet block, transmission on the Tx side will be interrupted after the currently transmitting frame has completed, for an amount of time as indicated in the received pause frame. The transmit data path will stop transmitting data for the number of 512 bit slot times encoded in the pause-timer field of the received pause control frame. By default the received pause control frames are not forwarded to the device driver. To forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE FRAMES’ bit in the MAC1 configuration register. Transmit flow control If case device drivers need to stall the receive data e.g. because software buffers are full, the Ethernet block can transmit pause control frames. Transmit flow control needs to be initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by hardware, such as the DMA managers. With software flow control, the device driver can detect a situation in which the process of receiving frames needs to be interrupted by sending out Tx pause frames. Note that due to Ethernet delays, a few frames can still be received before the flow control takes effect and the receive stream stops. Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command register. When the Ethernet block operates in full duplex mode, this will result in transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is written to TxFlowControl bit of the Command register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 204 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. When flow control be in force for an extended time, a sequence of pause frames must be transmitted. This is supported with a mirror counter mechanism. To enable mirror counting, a nonzero value is written to the MirrorCounter[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is transmitted. After sending the pause frame, an internal mirror counter is initialized to zero. The internal mirror counter starts incrementing one every 512 bit-slot times. When the internal mirror counter reaches the MirrorCounter value, another pause frame is transmitted with pause-timer value equal to the PauseTimer field from the FlowControlCounter register, the internal mirror counter is reset to zero and restarts counting. The register MirrorCounter[15:0] is usually set to a smaller value than register PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send a new pause frame before the transmission on the other side can resume. By continuing to send pause frames before the transmitting side finishes counting the pause timer, the pause can be extended as long as TxFlowControl is asserted. This continues until TxFlowControl is de-asserted when a final pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. To disable the mirror counter mechanism, write the value 0 to MirrorCounter field in the FlowControlCounter register. When using the mirror counter mechanism, account for time-of-flight delays, frame transmission time, queuing delays, crystal frequency tolerances, and response time delays by programming the MirrorCounter conservatively, typically about 80% of the PauseTimer value. If the software device driver sets the MirrorCounter field of the FlowControlCounter register to zero, the Ethernet block will only send one pause control frame. After sending the pause frame an internal pause counter is initialized at zero; the internal pause counter is incremented by one every 512 bit-slot times. Once the internal pause counter reaches the value of the PauseTimer register, the TxFlowControl bit in the Command register will be reset. The software device driver can poll the TxFlowControl bit to detect when the pause completes. The value of the internal counter in the flow control module can be read out via the FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register will return the value of the internal mirror counter; if the MirrorCounter is zero the FlowControlStatus register will return the value of the internal pause counter value. The device driver is allowed to dynamically modify the MirrorCounter register value and switch between zero MirrorCounter and nonzero MirrorCounter modes. Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1 configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not transmit pause control frames, software must not initiate pause frame transmissions, and the TxFlowControl bit in the Command register should be zero. Transmit flow control example Figure 24 illustrates the transmit flow control. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 205 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet device driver PauseTimer register MirrorCounter writes TxFlowCtl RMII normal pause control frame transmit transmission transmission MirrorCounter (1/515 bit slots) RMII receive normal receive normal transimisson clear TxFlowCtl pause control frame transmission pause control frame transmission pause in effect normal receive 0 50 100 150 200 250 300 350 400 450 500 Fig 24. Transmit Flow Control In this example, a frame is received while transmitting another frame (full duplex.) The device driver detects that some buffer might overrun and enables the transmit flow control by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter register, after which it enables the transmit flow control by setting the TxFlowControl bit in the Command register. As a response to the enabling of the flow control a pause control frame will be sent after the currently transmitting frame has been transmitted. When the pause frame transmission completes the internal mirror counter will start counting bit slots; as soon as the counter reaches the value in the MirrorCounter field another pause frame is transmitted. While counting the transmit data path will continue normal transmissions. As soon as software disables transmit flow control a zero pause control frame is transmitted to resume the receive process. 10.17.9 Half-Duplex mode backpressure When in half-duplex mode, backpressure can be generated to stall receive packets by sending continuous preamble that basically jams any other transmissions on the Ethernet medium. When the Ethernet block operates in half duplex mode, asserting the TxFlowControl bit in the Command register will result in applying continuous preamble on the Ethernet wire, effectively blocking traffic from any other Ethernet station on the same segment. In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins transmitting preamble, which raises carrier sense causing all other stations to defer. In the event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the collision. The colliding station backs off and then defers to the backpressure. If during backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame sent and then the backpressure resumed. If TxFlowControl is asserted for longer than 3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending preamble for several byte times to avoid the jabber limit. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 206 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. • Hash table filter: allows imperfect filtering of packets based on the station address. • Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or broadcast packets. • Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt. The filtering functions can be logically combined to create complex filtering functions. Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a promiscuous mode allows all packets to be passed to software. Overview The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet destination address in the frame. This capability greatly reduces the load on the host system, because Ethernet frames that are addressed to other stations would otherwise need to be inspected and rejected by the device driver software, using up bandwidth, memory space, and host CPU time. Address filtering can be implemented using the perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code which can be used as an index into a 64 entry programmable hash table. Figure 25 depicts a functional view of the receive filter. At the top of the diagram the Ethernet receive frame enters the filters. Each filter is controlled by signals from control registers; each filter produces a ‘Ready’ output and a ‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering then it will assert its Ready output; if the filter finds a matching frame it will assert the Match output along with the Ready output. The results of the filters are combined by logic functions into a single RxAbort output. If the RxAbort output is asserted, the frame does not need to be received. In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and removed from the buffer and not stored to memory at all, not using up receive descriptors, etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to reception of a Magic Packet), part of the frame is already written to memory and the Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard the frame immediately. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 207 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet packet AcceptUnicastEn AcceptMulticastEn AcceptMulticastHashEn IMPERFECT HASH AcceptUnicastHashEn FILTER HashFilter StationAddress AcceptPerfectEn PERFECT ADDRESS FILTER H FMatc h HFReady PAReady PAMatch CRC OK? FMatch RxFilterWoL FReady RxFilterEnWoL RxAbort Fig 25. Receive filter block diagram Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast, respectively, to be accepted, ignoring the Ethernet destination address in the frame. To program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1. Perfect address match When a frame with a unicast destination address is received, a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1, and the address matches, the frame is accepted. Imperfect hash filtering An imperfect filter is available, based on a hash mechanism. This filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. The advantage of this type of filter is that a small table can cover any possible address. The disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 208 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access the hash table: it is used as an index in the 64-bit HashFilter register that has been programmed with accept values. If the selected accept value is 1, the frame is accepted. – The device driver can initialize the hash filter table by writing to the registers HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table and HashFilterH contains bit 32 through 63 of the table. So, hash value 0 corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to bit 31 of the HashFilterH register. • Multicast and unicast – The imperfect hash filter can be applied to multicast addresses, by setting the AcceptMulticastHashEn bit in the RxFilter register to 1. – The same imperfect hash filter that is available for multicast addresses can also be used for unicast addresses. This is useful to be able to respond to a multitude of unicast addresses without enabling all unicast addresses. The hash filter can be applied to unicast addresses by setting the AcceptUnicastHashEn bit in the RxFilter register to 1. Enabling and disabling filtering The filters as defined in the sections above can be bypassed by setting the PassRxFilter bit in the Command register. When the PassRxFilter bit is set, all receive frames will be passed to memory. In this case the device driver software has to implement all filtering functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering as defined in the next section. Runt frames A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the minimum Ethernet frame size and therefore considered erroneous; they might be collision fragments. The receive data path automatically filters and discards these runt frames without writing them to memory and using a receive descriptor. When a runt frame has a correct CRC there is a possibility that it is intended to be useful. The device driver can receive the runt frames with correct CRC by setting the PassRuntFrame bit of the Command register to 1. 10.17.11 Power management The Ethernet block supports power management by means of clock switching. All clocks in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should not be switched off. 10.17.12 Wake-up on LAN Overview UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 209 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet UM10360 User manual The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state. Wake-up of the system takes effect through an interrupt. When a wake-up event is detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This interrupt should be used by system power management logic to wake up the system. While in a power-down state the packet that generates a Wake-up on LAN event is lost. There are two ways in which Ethernet packets can trigger wake-up events: generic Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the triggering packet has a valid CRC. Figure 25 shows the generation of the wake-up signal. The RxFilterWoLStatus register can be read by the software to inspect the reason for a Wake-up event. Before going to power-down the power management software should clear the register by writing the RxFilterWolClear register. NOTE: when entering in power-down mode, a receive frame might be not entirely stored into the Rx buffer. In this situation, after turning exiting power-down mode, the next receive frame is corrupted due to the data of the previous frame being added in front of the last received frame. Software drivers have to reset the receive data path just after exiting power-down mode. The following subsections describe the two Wake-up on LAN mechanisms. Filtering for WoL The receive filter functionality can be used to generate Wake-up on LAN events. If the RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt bit of the IntStatus register if a frame is received that passes the filter. The interrupt will only be generated if the CRC of the frame is correct. Magic Packet WoL The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely intended for wake-up purposes. This packet can be received, analyzed and recognized by the Ethernet block and used to trigger a wake-up event. A Magic Packet is a packet that contains in its data portion the station address repeated 16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the data portion of the packet. The whole packet must be a well-formed Ethernet frame. The magic packet detection unit analyzes the Ethernet packets, extracts the packet address and checks the payload for the Magic Packet pattern. The address from the packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic packet only sets the wake-up interrupt status bit if the packet passes the receive filter as illustrated in Figure 25: the result of the receive filter is ANDed with the magic packet filter result to produce the result. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 210 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets is more strict. When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register, the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the bit writing a 1 to the corresponding bit of the RxFilterWoLClear register. Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55 0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet): FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 10.17.13 Enabling and disabling receive and transmit Enabling and disabling reception After reset, the receive function of the Ethernet block is disabled. The receive function can be enabled by the device driver setting the RxEnable bit in the Command register and the “RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order). The status of the receive data path can be monitored by the device driver by reading the RxStatus bit of the Status register. Figure 26 illustrates the state machine for the generation of the RxStatus bit. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 211 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet ACTIVE RxStatus = 1 RxEnable = 1 xxxxxxxxxxxxxxxxxx RxEnable = 0 and not busy receiving OR RxProduceIndex = RxConsumeIndex - 1 INACTIVE RxStatus = 0 reset Fig 26. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state. As soon as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the receive data path is busy receiving a packet while the receive data path gets disabled, the packet will be received completely, stored to memory along with its status before returning to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will return to the INACTIVE state. For the state machine in Figure 26, a soft reset is like a hardware reset assertion, i.e. after a soft reset the receive data path is inactive until the data path is re-enabled. Enabling and disabling transmission After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data path can be enabled by the device driver setting the TxEnable bit in the Command register to 1. The status of the transmit data paths can be monitored by the device driver reading the TxStatus bit of the Status register. Figure 27 illustrates the state machine for the generation of the TxStatus bit. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 212 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet ACTIVE TxStatus = 1 TxEnable = 1 AND TxProduceIndex <> TxConsumeIndex xxxxxxxxxxxxxxxxxxxxxx TxEnable = 0 and not busy transmitting OR TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 27. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the transmit data path has completed all pending transmissions, including committing the transmission status to memory, the state machine returns to the INACTIVE state. The state machine will also return to the INACTIVE state if the Produce and Consume indices are equal again i.e. all frames have been transmitted. For the state machine in Figure 27, a soft reset is like a hardware reset assertion, i.e. after a soft reset the transmit data path is inactive until the data path is re-enabled. 10.17.14 Transmission padding and CRC In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’ (ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the MAC2 configuration register, as well as the Override and Pad bits from the transmit descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and ‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and CRC bits from the transmit descriptor Control word. The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable (ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the descriptor. If padding is required and enabled, a CRC will always be appended to the padded frames. A CRC will only be appended to the non-padded frames if ECRCE is set. UM10360 User manual If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is set. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 213 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating 64 or 68 bytes padded frames. If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information. 10.17.15 Huge frames and frame length checking The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to enable transmission and reception of frames of any length. Huge frame transmission can be enabled on a per frame basis by setting the Override and Huge bits in the transmit descriptor Control word. When enabling huge frames, the Ethernet block will not check frame lengths and report frame length errors (RangeError and LengthError). If huge frames are enabled, the received byte count in the RSV register may be invalid because the frame may exceed the maximum size; the RxSize fields from the receive status arrays will be valid. Frame lengths are checked by comparing the length/type field of the frame to the actual number of bytes in the frame. A LengthError is reported by setting the corresponding bit in the receive StatusInfo word. The MAXF register allows the device driver to specify the maximum number of bytes in a frame. The Ethernet block will compare the actual receive frame to the MAXF value and report a RangeError in the receive StatusInfo word if the frame is larger. 10.17.16 Statistics counters Generally, Ethernet applications maintain many counters that track Ethernet traffic statistics. There are a number of standards specifying such counters, such as IEEE std 802.3 / clause 30. Other standards are RFC 2665 and RFC 2233. The approach taken here is that by default all counters are implemented in software. With the help of the StatusInfo field in frame statuses, many of the important statistics events listed in the standards can be counted by software. 10.17.17 MAC status vectors Transmit and receive status information as detected by the MAC are available in registers TSV0, TSV1 and RSV so that software can poll them. These registers are normally of limited use because the communication between driver software and the Ethernet block takes place primarily through frame descriptors. Statistical events can be counted by software in the device driver. However, for debug purposes the transmit and receive status vectors are made visible. They are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 214 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.17.18 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. Hard reset After a hard reset, all registers will be set to their default value. Soft reset Parts of the Ethernet block can be soft reset by setting bits in the Command register and the MAC1 configuration register.The MAC1 register has six different reset bits: • SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware reset. • SIMULATION RESET: Resets the random number generator in the Transmit Function. The value after a hardware reset assertion is 0. • RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the receive function in the MAC. The value after a hardware reset assertion is 0. • RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a hardware reset assertion is 0. • RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the transmit function in the MAC. The value after a hardware reset assertion is 0. • RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after a hardware reset assertion is 0. The above reset bits must be cleared by software. The Command register has three different reset bits: • TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the MAC portions, including all (read-only) registers in the transmit data path, as well as the TxProduceIndex register in the host registers module. A soft reset of the transmit data path will abort all AHB transactions of the transmit data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear the TxStatus bit in the Status register. • RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the MAC portions, including all (read-only) registers in the receive data path, as well as the RxConsumeIndex register in the host registers module. A soft reset of the receive data path will abort all AHB transactions of the receive data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear the RxStatus bit in the Status register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 215 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet • RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block. To do a full soft reset of the Ethernet block, device driver software must: • Set the ‘SOFT RESET’ bit in the MAC1 register to 1. • Set the RegReset bit in the Command register, this bit clears automatically. • Re-initialize the MAC registers (0x000 to 0x0FC). • Reset the ‘SOFT RESET’ bit in the MAC1 register to 0. To reset just the transmit data path, the device driver software has to: • Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1. • Disable the Tx DMA managers by setting the TxEnable bits in the Command register to 0. • Set the TxReset bit in the Command register, this bit clears automatically. • Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0. To reset just the receive data path, the device driver software has to: • Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1 configuration register and resetting of the RxEnable bit of the Command register. • Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1. • Set the RxReset bit in the Command register, this bit clears automatically. • Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0. 10.17.19 Ethernet errors The Ethernet block generates errors for the following conditions: • A reception can cause an error: AlignmentError, RangeError, LengthError, SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the receive StatusInfo and in the interrupt status register (IntStatus). • A transmission can cause an error: LateCollision, ExcessiveCollision, ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the transmission StatusInfo and in the interrupt status register (IntStatus). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 216 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.18 AHB bandwidth The Ethernet block is connected to an AHB bus which must carry all of the data and control information associated with all Ethernet traffic in addition to the CPU accesses required to operate the Ethernet block and deal with message contents. 10.18.1 DMA access Assumptions By making some assumptions, the bandwidth needed for each type of AHB transfer can be calculated and added in order to find the overall bandwidth requirement. The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes. In order to analyze bus bandwidth requirements, some assumptions must be made about these buffers. The "worst case" is not addressed since that would involve all descriptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and very little data. It can easily be shown that the AHB cannot handle the huge amount of bus traffic that would be caused by such a degenerate (and illogical) case. For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame. Continuous traffic is assumed on both the transmit and receive channels. This analysis does not reflect the flow of Ethernet traffic over time, which would include inter-packet gaps in both the transmit and receive channels that reduce the bandwidth requirements over a larger time frame. Types of DMA access and their bandwidth requirements The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz, transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps. The Ethernet block initiates DMA accesses for the following cases: • Tx descriptor read: – Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of transmitted data. – This gives 1/8th of the data rate, which = 1.5625 Mbps. • Rx descriptor read: – Receive descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of received data. – This gives 1/8th of the data rate, which = 1.5625 Mbps. • Tx status write: – Transmit status occupies 1 word (4 bytes) of memory and is written once for each use of a descriptor. – One word write happens once every 64 bytes (16 words) of transmitted data. – This gives 1/16th of the data rate, which = 0.7813 Mbps. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 217 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet • Rx status write: – Receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. – Two word write happens once every 64 bytes (16 words) of received data. – This gives 1/8 of the data rate, which = 1.5625 Mbps. • Tx data read: – Data transmitted in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. • Rx data write: – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function. 10.18.2 Types of CPU access • Accesses that mirror each of the DMA access types: – All or part of status values must be read, and all or part of descriptors need to be written after each use, transmitted data must be stored in the memory by the CPU, and eventually received data must be retrieved from the memory by the CPU. – This gives roughly the same or slightly lower rate as the combined DMA functions, which = 30.5 Mbps. • Access to registers in the Ethernet block: – The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus registers, and both read and write the RxConsumeIndex and TxProduceIndex registers. – 7 word read/writes once every 64 bytes (16 words) of transmitted and received data. – This gives 7/16 of the data rate, which = 5.4688 Mbps. This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function. 10.18.3 Overall bandwidth Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which comes to approximately 66.5 MB/s. The peak bandwidth requirement can be somewhat higher due to the use of small memory buffers, in order to hold often used addresses (e.g. the station address) for example. Driver software can determine how to build frames in an efficient manner that does not overutilize the AHB. The bandwidth available on the AHB bus depends on the system clock frequency. As an example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses related to the Ethernet will be word transfers. The raw AHB bandwidth can be approximated as 4 bytes per two system clocks, which equals 2 times the system clock rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 218 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet for Ethernet traffic during simultaneous transmit and receive operations. This shows that it is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty of bandwidth headroom. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 219 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet 10.19 CRC calculation The calculation is used for several purposes: • Generation the FCS at the end of the Ethernet frame. • Generation of the hash table index for the hash table filtering. • Generation of the destination and source address hash CRCs. The C pseudocode function below calculates the CRC on a frame taking the frame (without FCS) and the number of bytes in the frame as arguments. The function returns the CRC as a 32-bit integer. int crc_calc(char frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // CRC result int q0, q1, q2, q3; // temporary variables crc = 0xFFFFFFFF; for (i = 0; i < frame_len; i++) { byte = *frame_no_fcs++; for (j = 0; j < 2; j++) { if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) { q3 = 0x04C11DB7; } else { q3 = 0x00000000; } if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) { q2 = 0x09823B6E; } else { q2 = 0x00000000; } if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) { q1 = 0x130476DC; } else { q1 = 0x00000000; } if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) { q0 = 0x2608EDB8; } else { q0 = 0x00000000; } crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0; byte >>= 4; } } return crc; } For FCS calculation, this function is passed a pointer to the first byte of the frame and the length of the frame without the FCS. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 220 of 849 NXP Semiconductors UM10360 Chapter 10: LPC176x/5x Ethernet For hash filtering, this function is passed a pointer to the destination address part of the frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits [28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit is set the packet is passed, otherwise it is rejected by the hash filter. For obtaining the destination and source address hash CRCs, this function calculates first both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are extracted, concatenated, and written in every StatusHashCRC word of every fragment status. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 221 of 849 UM10360 Chapter 11: LPC176x/5x USB device controller Rev. 3.1 — 2 April 2014 User manual 11.1 How to read this chapter This chapter describes the USB controller which is present on all LPC176x/5x devices except the LPC1767. On some LPC176x/5x family devices, the USB controller can also be configured for Host or OTG operation. 11.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the USB clock or with the Main PLL (PLL0). See Section 4.6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8.5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode, see Section 4.8.8. 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 11.13. 11.3 Introduction The Universal Serial Bus (USB) is a four-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame (SOF) marker and transactions that transfer data to or from device endpoints. Each device can have a maximum of 16 logical or 32 physical endpoints. There are four types of transfers defined for the endpoints. Control transfers are used to configure the device. Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no error correction. For more information on the Universal Serial Bus, see the USB Implementers Forum website. The USB device controller on the LPC176x/5x enables full-speed (12 Mb/s) data exchange with a USB host controller. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 222 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 185. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description AHB Advanced High-performance bus ATLE Auto Transfer Length Extraction ATX Analog Transceiver DD DMA Descriptor DDP DMA Description Pointer DMA Direct Memory Access EOP End-Of-Packet EP Endpoint EP_RAM Endpoint RAM FS Full Speed LED Light Emitting Diode LS Low Speed MPS Maximum Packet Size NAK Negative Acknowledge PLL Phase Locked Loop RAM Random Access Memory SOF Start-Of-Frame SIE Serial Interface Engine SRAM Synchronous RAM UDCA USB Device Communication Area USB Universal Serial Bus 11.4 Features • Fully compliant with the USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • Supports DMA transfers on all non-control endpoints. • Allows dynamic switching between CPU controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 11.5 Fixed endpoint configuration Table 186 shows the supported endpoint configurations. Endpoints are realized and configured at run time using the Endpoint realization registers, documented in Section 11.10.4 “Endpoint realization registers”. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 223 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 186. Fixed endpoint configuration Logical endpoint Physical endpoint Endpoint type 0 0 Control 0 1 Control 1 2 Interrupt 1 3 Interrupt 2 4 Bulk 2 5 Bulk 3 6 Isochronous 3 7 Isochronous 4 8 Interrupt 4 9 Interrupt 5 10 Bulk 5 11 Bulk 6 12 Isochronous 6 13 Isochronous 7 14 Interrupt 7 15 Interrupt 8 16 Bulk 8 17 Bulk 9 18 Isochronous 9 19 Isochronous 10 20 Interrupt 10 21 Interrupt 11 22 Bulk 11 23 Bulk 12 24 Isochronous 12 25 Isochronous 13 26 Interrupt 13 27 Interrupt 14 28 Bulk 14 29 Bulk 15 30 Bulk 15 31 Bulk Direction Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Packet size (bytes) 8, 16, 32, 64 8, 16, 32, 64 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 8, 16, 32, 64 8, 16, 32, 64 Double buffer No No No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes 11.6 Functional description The architecture of the USB device controller is shown below in Figure 28. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 224 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller DMA interface (AHB master) BUS MASTER INTERFACE DMA ENGINE REGISTER INTERFACE EP_RAM ACCESS CONTROL SERIAL INTERFACE ENGINE VBUS USB_CONNECT USB_D+ USB_D- AHB BUS USB ATX register interface (AHB slave) USB DEVICE BLOCK EP_RAM (4K) USB_UP_LED Fig 28. USB device controller block diagram 11.6.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus. 11.6.2 Serial Interface Engine (SIE) The SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. It handles transfer of data between the endpoint buffers in EP_RAM and the USB bus. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. 11.6.3 Endpoint RAM (EP_RAM) Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the EP_RAM. The total EP_RAM space required depends on the number of realized endpoints, the maximum packet size of the endpoint, and whether the endpoint supports double buffering. 11.6.4 EP_RAM access control The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the three sources that can access it: the CPU (via the Register Interface), the SIE, and the DMA Engine. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 225 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.6.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface. 11.6.6 Register interface The Register Interface allows the CPU to control the operation of the USB Device Controller. It also provides a way to write transmit data to the controller and read receive data from the controller. 11.6.7 SoftConnect The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow software to finish its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without having to unplug the cable. To use the SoftConnect feature, the CONNECT signal should control an external switch that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the CONNECT signal by writing to the CON bit using the SIE Set Device Status command. 11.6.8 GoodLink Good USB connection indication is provided through GoodLink technology. When the device is successfully enumerated and configured, the LED indicator will be permanently ON. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device. It is a useful field diagnostics tool to isolate faulty equipment. To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED signal is controlled using the SIE Configure Device command. 11.7 Operational overview Transactions on the USB bus transfer data between device endpoints and the host. The direction of a transaction is defined with respect to the host. OUT transactions transfer data from the host to the device. IN transactions transfer data from the device to the host. All transactions are initiated by the host controller. For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and converts it into a parallel data stream. The parallel data is written to the corresponding endpoint buffer in the EP_RAM. For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM, converts it into serial data, and transmits it onto the USB bus using the USB ATX. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 226 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface. See Section 11.14 “Slave mode operation” for a detailed description of this mode. In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See Section 11.15 “DMA operation” for a detailed description of this mode. 11.8 Pin description Table 187. USB external interface Name Direction VBUS I USB_CONNECT O USB_UP_LED O USB_D+ I/O USB_D- I/O Description VBUS status input. When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally. SoftConnect control signal. GoodLink LED control signal. Positive differential data. Negative differential data. 11.9 Clocking and power management This section describes the clocking and power management features of the USB Device Controller. 11.9.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device). The following constraints should be met by a bus-powered device: 1. A device in the non-configured state should draw a maximum of 100 mA from the bus. 2. A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500 mA. 3. A suspended device can draw a maximum of 2.5 mA. 11.9.2 Clocks The USB device controller clocks are shown in Table 188 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 227 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 188. USB device controller clock sources Clock source Description AHB master clock Clock for the AHB master bus interface and DMA AHB slave clock Clock for the AHB slave interface usbclk 48 MHz clock from the dedicated USB PLL (PLL1) or the Main PLL (PLL0), used to recover the 12 MHz clock from the USB bus 11.9.3 Power management support To help conserve power, the USB device controller automatically disables the AHB master clock and usbclk when not in use. When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the usbclk input to the device controller is automatically disabled, helping to conserve power. However, if software wishes to access the device controller registers, usbclk must be active. To allow access to the device controller registers while in the suspend state, the USBClkCtrl and USBClkSt registers are provided. When software wishes to access the device controller registers, it should first ensure usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain enabled until DEV_CLK_EN is cleared by software. When a DMA transfer occurs, the device controller automatically turns on the AHB master clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the last DMA access, the AHB master clock is automatically disabled to help conserve power. If desired, software also has the capability of forcing this clock to remain enabled using the USBClkCtrl register. Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is set. When the device controller is not in use, all of the device controller clocks may be disabled by clearing PCUSB. The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK can be read from the USBIntSt register. Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 228 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.9.4 Remote wake-up The USB device controller supports software initiated remote wake-up. Remote wake-up involves resume signaling on the USB bus initiated from the device. This is done by clearing the SUS bit in the SIE Set Device Status register. Before writing into the register, all the clocks to the device controller have to be enabled using the USBClkCtrl register. 11.10 Register description Table 189 shows the USB Device Controller registers directly accessible by the CPU. The Serial Interface Engine (SIE) has other registers that are indirectly accessible via the SIE command registers. See Section 11.12 “Serial interface engine command description” for more info. Table 189. USB device register map Name Description Clock control registers USBClkCtrl USB Clock Control USBClkSt USB Clock Status Device interrupt registers USBIntSt USB Interrupt Status USBDevIntSt USB Device Interrupt Status USBDevIntEn USB Device Interrupt Enable USBDevIntClr USB Device Interrupt Clear USBDevIntSet USB Device Interrupt Set USBDevIntPri USB Device Interrupt Priority Endpoint interrupt registers USBEpIntSt USB Endpoint Interrupt Status USBEpIntEn USB Endpoint Interrupt Enable USBEpIntClr USB Endpoint Interrupt Clear USBEpIntSet USB Endpoint Interrupt Set USBEpIntPri USB Endpoint Priority Endpoint realization registers USBReEp USB Realize Endpoint USBEpIn USB Endpoint Index USBMaxPSize USB MaxPacketSize USB transfer registers USBRxData USB Receive Data USBRxPLen USB Receive Packet Length USBTxData USB Transmit Data USBTxPLen USB Transmit Packet Length USBCtrl USB Control SIE Command registers USBCmdCode USB Command Code USBCmdData USB Command Data Access Reset value[1] Address R/W 0 RO 0 0x5000 CFF4 0x5000 CFF8 R/W 0x8000 0000 0x400F C1C0 RO 0x10 0x5000 C200 R/W 0 0x5000 C204 WO 0 0x5000 C208 WO 0 0x5000 C20C WO 0 0x5000 C22C RO 0 R/W 0 WO 0 WO 0 WO[2] 0 0x5000 C230 0x5000 C234 0x5000 C238 0x5000 C23C 0x5000 C240 R/W 0x3 WO[2] 0 R/W 0x8 0x5000 C244 0x5000 C248 0x5000 C24C RO 0 RO 0 WO[2] 0 WO[2] 0 R/W 0 0x5000 C218 0x5000 C220 0x5000 C21C 0x5000 C224 0x5000 C228 WO[2] 0 RO 0 0x5000 C210 0x5000 C214 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 229 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 189. USB device register map …continued Name Description DMA registers USBDMARSt USB DMA Request Status USBDMARClr USB DMA Request Clear USBDMARSet USB DMA Request Set USBUDCAH USB UDCA Head USBEpDMASt USB Endpoint DMA Status USBEpDMAEn USB Endpoint DMA Enable USBEpDMADis USB Endpoint DMA Disable USBDMAIntSt USB DMA Interrupt Status USBDMAIntEn USB DMA Interrupt Enable USBEoTIntSt USB End of Transfer Interrupt Status USBEoTIntClr USB End of Transfer Interrupt Clear USBEoTIntSet USB End of Transfer Interrupt Set USBNDDRIntSt USB New DD Request Interrupt Status USBNDDRIntClr USB New DD Request Interrupt Clear USBNDDRIntSet USB New DD Request Interrupt Set USBSysErrIntSt USB System Error Interrupt Status USBSysErrIntClr USB System Error Interrupt Clear USBSysErrIntSet USB System Error Interrupt Set Access Reset value[1] Address RO 0 WO[2] 0 WO[2] 0 R/W 0 RO 0 WO[2] 0 WO[2] 0 RO 0 R/W 0 RO 0 WO[2] 0 WO[2] 0 RO 0 WO[2] 0 WO[2] 0 RO 0 WO[2] 0 WO[2] 0 0x5000 C250 0x5000 C254 0x5000 C258 0x5000 C280 0x5000 C284 0x5000 C288 0x5000 C28C 0x5000 C290 0x5000 C294 0x5000 C2A0 0x5000 C2A4 0x5000 C2A8 0x5000 C2AC 0x5000 C2B0 0x5000 C2B4 0x5000 C2B8 0x5000 C2BC 0x5000 C2C0 [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. [2] Reading WO register will return an invalid value. 11.10.1 Clock control registers 11.10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4) This register controls the clocking of the USB Device Controller. Whenever software wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN must be set. The software does not have to repeat this exercise for every register access, provided that the corresponding USBClkCtrl bits are already set. Note that this register is functional only when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device controller are disabled irrespective of the contents of this register. USBClkCtrl is a read/write register. Table 190. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description Bit Symbol Description 0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 DEV_CLK_EN Device clock enable. Enables the usbclk input to the device controller 2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value NA 0 NA UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 230 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 190. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description …continued Bit Symbol Description 3 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 AHB_CLK_EN AHB clock enable 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value NA 0 NA 11.10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8) This register holds the clock availability status. The bits of this register are ORed together to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with the register access. Software does not have to repeat this exercise for every access, provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register. Table 191. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description Bit Symbol Description 0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 1 DEV_CLK_ON Device clock on. The usbclk input to the device controller is active. 3:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 AHB_CLK_ON AHB clock on. 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value NA 0 NA 0 NA 11.10.2 Device interrupt registers 11.10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0) The USB Device Controller has three interrupt lines. This register allows software to determine their status with a single read operation. All three interrupt lines are ORed together to a single channel of the vectored interrupt controller. This register also contains the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write register. Table 192. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description Reset value 0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 0 1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 0 2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. 0 7:3 - These bits are reserved in a device-only configuration. User software should NA not write ones to reserved bits. The value read from a reserved bit is not defined. See Table 258 for OTG configuration. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 231 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 192. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description …continued Bit Symbol Description Reset value 8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change 1 of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.8.8 “Wake-up from Reduced Power Modes” for details). Also see Section 4.5.9 “PLL0 and Power-down mode” and Section 4.8.9 “Power Control for Peripherals register (PCONP - 0x400F C0C4)” for considerations about the PLL and invoking the Power-down mode. This bit is read-only. 30:9 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt 1 Controller does not see the ORed output of the USB interrupt lines. 11.10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200) The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and 1 indicates the presence of the interrupt. USBDevIntSt is a read-only register. Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol - - - - - - - Bit 23 22 21 20 19 18 17 Symbol - - - - - - - Bit 15 14 13 12 11 10 9 Symbol - - - - - - ERR_INT Bit 7 6 5 4 3 2 1 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST 24 16 8 EP_RLZED 0 FRAME Table 194. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description Bit Symbol Description Reset value 0 FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0 1 EP_FAST Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, 0 the corresponding endpoint interrupt will be routed to this bit. 2 EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is 0 not set, the corresponding endpoint interrupt will be routed to this bit. 3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs. 0 Refer to Section 11.12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on page 256. 4 CCEMPTY The command code register (USBCmdCode) is empty (New command can be written). 1 5 CDFULL Command data register (USBCmdData) is full (Data can be read now). 0 6 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0 7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes 0 programmed in the TxPacket length register (USBTxPLen). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 232 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 194. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description …continued Bit Symbol Description Reset value 8 EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0 register (USBMaxPSize) is updated and the corresponding operation is completed. 9 ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 11.12.9 0 “Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 258 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 11.10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204) Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to generate an interrupt on one of the interrupt lines when set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. USBDevIntEn is a read/write register. Table 195. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol - - - - - - - Bit 23 22 21 20 19 18 17 Symbol - - - - - - - Bit 15 14 13 12 11 10 9 Symbol - - - - - - ERR_INT Bit 7 6 5 4 3 2 1 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST 24 16 8 EP_RLZED 0 FRAME Table 196. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description Bit Symbol Value Description Reset value 31:0 See 0 USBDevIntEn 1 bit allocation table above No interrupt is generated. 0 An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 193) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. 11.10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208) Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a zero has no effect. Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding endpoint interrupts in USBEpIntSt should be cleared. USBDevIntClr is a write-only register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 233 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 197. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol - - - - - - - Bit 23 22 21 20 19 18 17 Symbol - - - - - - - Bit 15 14 13 12 11 10 9 Symbol - - - - - - ERR_INT Bit 7 6 5 4 3 2 1 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST 24 16 8 EP_RLZED 0 FRAME Table 198. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description Bit Symbol Value Description Reset value 31:0 See 0 No effect. 0 USBDevIntClr 1 bit allocation The corresponding bit in USBDevIntSt (Section 11.10.2.2) is cleared. table above 11.10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C) Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a zero has no effect USBDevIntSet is a write-only register. Table 199. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol - - - - - - - Bit 23 22 21 20 19 18 17 Symbol - - - - - - - Bit 15 14 13 12 11 10 9 Symbol - - - - - - ERR_INT Bit 7 6 5 4 3 2 1 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST 24 16 8 EP_RLZED 0 FRAME Table 200. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description Bit Symbol Value Description 31:0 See 0 USBDevIntSet 1 bit allocation table above No effect. The corresponding bit in USBDevIntSt (Section 11.10.2.2) is set. Reset value 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 234 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register. Table 201. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description Bit Symbol Value Description 0 FRAME 0 1 1 EP_FAST 0 1 31:2 - FRAME interrupt is routed to USB_INT_REQ_LP. FRAME interrupt is routed to USB_INT_REQ_HP. EP_FAST interrupt is routed to USB_INT_REQ_LP. EP_FAST interrupt is routed to USB_INT_REQ_HP. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 NA 11.10.3 Endpoint interrupt registers The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are used in Slave mode operation. 11.10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230) Each physical non-isochronous endpoint is represented by a bit in this register to indicate that it has generated an interrupt. All non-isochronous OUT endpoints generate an interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet is successfully transmitted, or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section 11.12.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 255). A bit set to one in this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a read-only register. Note that for Isochronous endpoints, handling of packet data is done when the FRAME interrupt occurs. Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX Bit 23 22 21 20 19 18 17 Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX Bit 15 14 13 12 11 10 9 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX Bit 7 6 5 4 3 2 1 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX 24 EP12RX 16 EP8RX 8 EP4RX 0 EP0RX UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 235 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 203. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Bit Symbol Description Reset value 0 EP0RX Endpoint 0, Data Received Interrupt bit. 0 1 EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. 0 2 EP1RX Endpoint 1, Data Received Interrupt bit. 0 3 EP1TX Endpoint 1, Data Transmitted Interrupt bit or sent a NAK. 0 4 EP2RX Endpoint 2, Data Received Interrupt bit. 0 5 EP2TX Endpoint 2, Data Transmitted Interrupt bit or sent a NAK. 0 6 EP3RX Endpoint 3, Isochronous endpoint. NA 7 EP3TX Endpoint 3, Isochronous endpoint. NA 8 EP4RX Endpoint 4, Data Received Interrupt bit. 0 9 EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. 0 10 EP5RX Endpoint 5, Data Received Interrupt bit. 0 11 EP5TX Endpoint 5, Data Transmitted Interrupt bit or sent a NAK. 0 12 EP6RX Endpoint 6, Isochronous endpoint. NA 13 EP6TX Endpoint 6, Isochronous endpoint. NA 14 EP7RX Endpoint 7, Data Received Interrupt bit. 0 15 EP7TX Endpoint 7, Data Transmitted Interrupt bit or sent a NAK. 0 16 EP8RX Endpoint 8, Data Received Interrupt bit. 0 17 EP8TX Endpoint 8, Data Transmitted Interrupt bit or sent a NAK. 0 18 EP9RX Endpoint 9, Isochronous endpoint. NA 19 EP9TX Endpoint 9, Isochronous endpoint. NA 20 EP10RX Endpoint 10, Data Received Interrupt bit. 0 21 EP10TX Endpoint 10, Data Transmitted Interrupt bit or sent a NAK. 0 22 EP11RX Endpoint 11, Data Received Interrupt bit. 0 23 EP11TX Endpoint 11, Data Transmitted Interrupt bit or sent a NAK. 0 24 EP12RX Endpoint 12, Isochronous endpoint. NA 25 EP12TX Endpoint 12, Isochronous endpoint. NA 26 EP13RX Endpoint 13, Data Received Interrupt bit. 0 27 EP13TX Endpoint 13, Data Transmitted Interrupt bit or sent a NAK. 0 28 EP14RX Endpoint 14, Data Received Interrupt bit. 0 29 EP14TX Endpoint 14, Data Transmitted Interrupt bit or sent a NAK. 0 30 EP15RX Endpoint 15, Data Received Interrupt bit. 0 31 EP15TX Endpoint 15, Data Transmitted Interrupt bit or sent a NAK. 0 11.10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234) Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated endpoint. USBEpIntEn is a read/write register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 236 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 204. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX Bit 23 22 21 20 19 18 17 Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX Bit 15 14 13 12 11 10 9 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX Bit 7 6 5 4 3 2 1 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX 24 EP12RX 16 EP8RX 8 EP4RX 0 EP0RX Table 205. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntEn bit 0 allocation table above The corresponding bit in USBDMARSt is set when an interrupt occurs 0 for this endpoint. 1 The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. 11.10.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238) Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt command to be executed (Table 249) for the corresponding physical endpoint. Writing zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the CDFULL bit is set, USBCmdData contains the status of the endpoint, and the corresponding bit in USBEpIntSt is cleared. Notes: • When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be set to ensure the corresponding interrupt has been cleared before proceeding. • While setting multiple bits in USBEpIntClr simultaneously is possible, it is not recommended; only the status of the endpoint corresponding to the least significant interrupt bit cleared will be available at the end of the operation. • Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly invoked using the SIE command registers, but using USBEpIntClr is recommended because of its ease of use. Each physical endpoint has its own reserved bit in this register. The bit field definition is the same as that of USBEpIntSt shown in Table 202. USBEpIntClr is a write-only register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 237 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 206. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX Bit 23 22 21 20 19 18 17 Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX Bit 15 14 13 12 11 10 9 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX Bit 7 6 5 4 3 2 1 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX 24 EP12RX 16 EP8RX 8 EP4RX 0 EP0RX Table 207. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntClr bit 0 allocation table above 1 No effect. 0 Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. 11.10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C) Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write-only register. Table 208. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX Bit 23 22 21 20 19 18 17 Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX Bit 15 14 13 12 11 10 9 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX Bit 7 6 5 4 3 2 1 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX 24 EP12RX 16 EP8RX 8 EP4RX 0 EP0RX Table 209. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description Bit Symbol Value Description 31:0 See USBEpIntSet bit 0 allocation table above 1 No effect. Sets the corresponding bit in USBEpIntSt. Reset value 0 11.10.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240) This register determines whether an endpoint interrupt is routed to the EP_FAST or EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST or EP_SLOW is possible. Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 238 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller USBEpIntPri is a write-only register. Table 210. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX Bit 23 22 21 20 19 18 17 Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX Bit 15 14 13 12 11 10 9 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX Bit 7 6 5 4 3 2 1 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX 24 EP12RX 16 EP8RX 8 EP4RX 0 EP0RX Table 211. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntPri bit 0 The corresponding interrupt is routed to the EP_SLOW bit of 0 allocation table above USBDevIntSt 1 The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt 11.10.4 Endpoint realization registers The registers in this group allow realization and configuration of endpoints at run time. 11.10.4.1 EP RAM requirements The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next word boundary. Also, each buffer has one word header showing the size of the packet length received. The EP_ RAM space (in words) required for the physical endpoint can be expressed as EPRAMspace =   -M-----a---x---P----a----c---k---e---t--S---i--z---e----+-----34 + 1  dbstatus (1) where dbstatus = 1 for a single-buffered endpoint and 2 for a double-buffered endpoint. Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is N TotalEPRAMspace = 32 +  EPRAMspacen (2) n=0 where N is the number of realized endpoints. Total EP_RAM space should not exceed 4096 bytes (4 kB, 1 kwords). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 239 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244) Writing one to a bit in this register causes the corresponding endpoint to be realized. Writing zeros causes it to be unrealized. This register returns to its reset state when a bus reset occurs. USBReEp is a read/write register. Table 212. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation Reset value: 0x0000 0003 Bit 31 30 29 28 27 26 Symbol EP31 EP30 EP29 EP28 EP27 EP26 Bit 23 22 21 20 19 18 Symbol EP23 EP22 EP21 EP20 EP19 EP18 Bit 15 14 13 12 11 10 Symbol EP15 EP14 EP13 EP12 EP11 EP10 Bit 7 6 5 4 3 2 Symbol EP7 EP6 EP5 EP4 EP3 EP2 25 EP25 17 EP17 9 EP9 1 EP1 24 EP24 16 EP16 8 EP8 0 EP0 Table 213. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description Bit Symbol Value Description 0 EP0 0 Control endpoint EP0 is not realized. 1 Control endpoint EP0 is realized. 1 EP1 0 Control endpoint EP1 is not realized. 1 Control endpoint EP1 is realized. 31:2 EPxx 0 Endpoint EPxx is not realized. 1 Endpoint EPxx is realized. Reset value 1 1 0 On reset, only the control endpoints are realized. Other endpoints, if required, are realized by programming the corresponding bits in USBReEp. To calculate the required EP_RAM space for the realized endpoints, see Section 11.10.4.1. Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is shown below. Clear EP_RLZED bit in USBDevIntSt; for every endpoint to be realized, { /* OR with the existing value of the Realize Endpoint register */ USBReEp |= (UInt32) ((0x1 << endpt)); /* Load Endpoint index Reg with physical endpoint no.*/ USBEpIn = (UInt32) endpointnumber; /* load the max packet size Register */ USBEpMaxPSize = MPS; UM10360 User manual /* check whether the EP_RLZED bit in the Device Interrupt Status register is set */ while (!(USBDevIntSt & EP_RLZED)) { /* wait until endpoint realization is complete */ All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 240 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller } /* Clear the EP_RLZED bit */ Clear EP_RLZED bit in USBDevIntSt; } The device will not respond to any transactions to unrealized endpoints. The SIE Configure Device command will only cause realized and enabled endpoints to respond to transactions. For details see Table 244. 11.10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 C248) Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is in fact a register array. Hence before writing, this register is addressed through the USBEpIn register. The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize will set the array element pointed to by USBEpIn. USBEpIn is a write-only register. Table 214. USB Endpoint Index register (USBEpIn - address 0x5000 C248) bit description Bit Symbol Description Reset value 4:0 PHY_EP Physical endpoint number (0-31) 0 31:5 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11.10.4.4 USB MaxPacketSize register (USBMaxPSize - 0x5000 C24C) On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At the end, the EP_RLZED bit will be set in USBDevIntSt (Table 193). USBMaxPSize array indexing is shown in Figure 29. USBMaxPSize is a read/write register. Table 215. USB MaxPacketSize register (USBMaxPSize - address 0x5000 C24C) bit description Bit Symbol Description Reset value 9:0 MPS The maximum packet size value. 0x008[1] 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. [1] Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0. ENDPOINT INDEX MPS_EP0 UM10360 User manual MPS_EP31 The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the USBMaxPSize register. Fig 29. USB MaxPacketSize register array indexing All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 241 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.5 USB transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation. See Section 11.14 “Slave mode operation”. 11.10.5.1 USB Receive Data register (USBRxData - 0x5000 C218) For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately. On reading this register, data from the selected endpoint buffer is fetched. The data is in little endian format: the first byte received from the USB bus will be available in the least significant byte of USBRxData. USBRxData is a read-only register. Table 216. USB Receive Data register (USBRxData - address 0x5000 C218) bit description Bit Symbol Description 31:0 RX_DATA Data received. Reset value 0x0000 0000 11.10.5.2 USB Receive Packet Length register (USBRxPLen - 0x5000 C220) This register contains the number of bytes remaining in the endpoint buffer for the current packet being read via the USBRxData register, and a bit indicating whether the packet is valid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately. This register is updated on each read of the USBRxData register. USBRxPLen is a read-only register. Table 217. USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description Bit Symbol Value Description Reset value 9:0 PKT_LNGTH - The remaining number of bytes to be read from the currently selected 0 endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. 10 DV Data valid. This bit is useful for isochronous endpoints. Non-isochronous 0 endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. 0 Data is invalid. 1 Data is valid. 11 PKT_RDY - The PKT_LNGTH field is valid and the packet is ready for reading. 0 31:12 - - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 11.10.5.3 USB Transmit Data register (USBTxData - 0x5000 C21C) For an IN transaction, the CPU writes the endpoint data into this register. Before writing to this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately, and the packet length should be written to the USBTxPlen register. On writing this register, the data is written to the selected endpoint buffer. The data is in little endian format: the first byte sent on the USB bus will be the least significant byte of USBTxData. USBTxData is a write-only register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 242 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 218. USB Transmit Data register (USBTxData - address 0x5000 C21C) bit description Bit Symbol Description 31:0 TX_DATA Transmit Data. Reset value 0x0000 0000 11.10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224) This register contains the number of bytes transferred from the CPU to the selected endpoint buffer. Before writing data to USBTxData, software should first write the packet length (MaxPacketSize) to this register. After each write to USBTxData, hardware decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set to select the desired endpoint buffer before starting this process. For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write-only register. Table 219. USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description Bit Symbol Value Description Reset value 9:0 PKT_LNGTH - The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. 0x000 31:10 - - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 11.10.5.5 USB Control register (USBCtrl - 0x5000 C228) This register controls the data transfer operation of the USB device. It selects the endpoint buffer that is accessed by the USBRxData and USBTxData registers, and enables reading and writing them. USBCtrl is a read/write register. Table 220. USB Control register (USBCtrl - address 0x5000 C228) bit description Bit Symbol Value Description Reset value 0 RD_EN Read mode control. Enables reading data from the OUT endpoint buffer 0 for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. 0 Read mode is disabled. 1 Read mode is enabled. 1 WR_EN Write mode control. Enables writing data to the IN endpoint buffer for the 0 endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. 0 Write mode is disabled. 1 Write mode is enabled. 5:2 LOG_ENDPOINT - Logical Endpoint number. 0x0 31:6 - - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 243 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.6 SIE command code registers The SIE command code registers are used for communicating with the Serial Interface Engine. See Section 11.12 “Serial interface engine command description” for more information. 11.10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210) This register is used for sending the command and write data to the SIE. The commands written here are propagated to the SIE and executed there. After executing the command, the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See Section 11.12 for details. USBCmdCode is a write-only register. Table 221. USB Command Code register (USBCmdCode - address 0x5000 C210) bit description Bit Symbol Value Description Reset value 7:0 - - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 15:8 CMD_PHASE The command phase: 0x00 0x01 Write 0x02 Read 0x05 Command 23:16 CMD_CODE/ CMD_WDATA This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). 0x00 31:24 - - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 11.10.6.2 USB Command Data register (USBCmdData - 0x5000 C214) This register contains the data retrieved after executing a SIE command. When the data is ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 193 for details. USBCmdData is a read-only register. Table 222. USB Command Data register (USBCmdData - address 0x5000 C214) bit description Bit Symbol Description Reset value 7:0 CMD_RDATA Command Read Data. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11.10.7 DMA registers The registers in this group are used for the DMA mode of operation (see Section 11.15 “DMA operation”) 11.10.7.1 USB DMA Request Status register (USBDMARSt - 0x5000 C250) A bit in this register associated with a non-isochronous endpoint is set by hardware when an endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when the corresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves as a UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 244 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller flag for the DMA engine to start the data transfer if the DMA is enabled for the corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for control endpoints (EP0 and EP1). USBDMARSt is a read-only register. Table 223. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit allocation Reset value: 0x0000 0000 Bit 31 30 29 28 27 26 25 Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 Bit 23 22 21 20 19 18 17 Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 Bit 15 14 13 12 11 10 9 Symbol EP15 EP14 EP13 EP12 EP11 EP10 EP9 Bit 7 6 5 4 3 2 1 Symbol EP7 EP6 EP5 EP4 EP3 EP2 EP1 24 EP24 16 EP16 8 EP8 0 EP0 Table 224. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description Bit Symbol Value Description 0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). 1 EP1 31:2 EPxx 0 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). Endpoint xx (2 xx 31) DMA request. 0 DMA not requested by endpoint xx. 1 DMA requested by endpoint xx. Reset value 0 0 0 [1] DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0. 11.10.7.2 USB DMA Request Clear register (USBDMARClr - 0x5000 C254) Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt register. Writing zero has no effect. This register is intended for initialization prior to enabling the DMA for an endpoint. When the DMA is enabled for an endpoint, hardware clears the corresponding bit in USBDMARSt on completion of a packet transfer. Therefore, software should not clear the bit using this register while the endpoint is enabled for DMA operation. USBDMARClr is a write-only register. The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 223). Table 225. USB DMA Request Clear register (USBDMARClr - address 0x5000 C254) bit description Bit Symbol Value Description Reset value 0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 0 bit must be 0). 1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit 0 must be 0). 31:2 EPxx Clear the endpoint xx (2 xx 31) DMA request. 0 0 No effect. 1 Clear the corresponding bit in USBDMARSt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 245 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258) Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register. Writing zero has no effect. This register allows software to raise a DMA request. This can be useful when switching from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is not raised by hardware. Software can then use this register to manually start the DMA transfer. Software can also use this register to initiate a DMA transfer to proactively fill an IN endpoint buffer before an IN token packet is received from the host. USBDMARSet is a write-only register. The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 223). Table 226. USB DMA Request Set register (USBDMARSet - address 0x5000 C258) bit description Bit Symbol Value Description Reset value 0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit 0 must be 0). 1 EP1 0 31:2 EPxx Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must 0 be 0). Set the endpoint xx (2 xx 31) DMA request. 0 0 No effect. 1 Set the corresponding bit in USBDMARSt. 11.10.7.4 USB UDCA Head register (USBUDCAH - 0x5000 C280) The UDCA (USB Device Communication Area) Head register maintains the address where the UDCA is located in the RAM. Refer to Section 11.15.2 “USB device communication area” and Section 11.15.4 “The DMA descriptor” for more details on the UDCA and DMA descriptors. USBUDCAH is a read/write register. Table 227. USB UDCA Head register (USBUDCAH - address 0x5000 C280) bit description Bit Symbol Description Reset value 6:0 - Reserved. Software should not write ones to reserved bits. The UDCA is aligned to 0x00 128-byte boundaries. 31:7 UDCA_ADDR Start address of the UDCA. 0 11.10.7.5 USB EP DMA Status register (USBEpDMASt - 0x5000 C284) Bits in this register indicate whether DMA operation is enabled for the corresponding endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in this register. USBEpDMASt is a read-only register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 246 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 228. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description Bit Symbol Value Description Reset value 0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0 the EP0_DMA_ENABLE bit must be 0). 1 EP1_DMA_ENABLE 0 31:2 EPxx_DMA_ENABLE Control endpoint IN (DMA cannot be enabled for this endpoint and 0 the EP1_DMA_ENABLE bit must be 0). endpoint xx (2 xx 31) DMA enabled bit. 0 0 The DMA for endpoint EPxx is disabled. 1 The DMA for endpoint EPxx is enabled. 11.10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288) Writing one to a bit to this register will enable the DMA operation for the corresponding endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints EP0 and EP1. USBEpDMAEn is a write-only register. Table 229. USB EP DMA Enable register (USBEpDMAEn - address 0x5000 C288) bit description Bit Symbol Value Description Reset value 0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0 the EP0_DMA_ENABLE bit value must be 0). 1 EP1_DMA_ENABLE 0 31:2 EPxx_DMA_ENABLE Control endpoint IN (DMA cannot be enabled for this endpoint and the 0 EP1_DMA_ENABLE bit must be 0). Endpoint xx(2 xx 31) DMA enable control bit. 0 0 No effect. 1 Enable the DMA operation for endpoint EPxx. 11.10.7.7 USB EP DMA Disable register (USBEpDMADis - 0x5000 C28C) Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register clears the internal DMA_PROCEED flag. Refer to Section 11.15.5.4 “Optimizing descriptor fetch” for more information on the DMA_PROCEED flag. If a DMA transfer is in progress for an endpoint when its corresponding bit is cleared, the transfer is completed before the DMA is disabled. When an error condition is detected during a DMA transfer, the corresponding bit is cleared by hardware. USBEpDMADis is a write-only register. Table 230. USB EP DMA Disable register (USBEpDMADis - address 0x5000 C28C) bit description Bit Symbol Value Description Reset value 0 EP0_DMA_DISABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and 0 the EP0_DMA_DISABLE bit value must be 0). 1 EP1_DMA_DISABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the 0 EP1_DMA_DISABLE bit value must be 0). 31:2 EPxx_DMA_DISABLE Endpoint xx (2 xx 31) DMA disable control bit. 0 0 No effect. 1 Disable the DMA operation for endpoint EPxx. 11.10.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290) Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt status register are set. USBDMAIntSt is a read-only register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 247 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 231. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description Bit Symbol Value Description 0 EOT End of Transfer Interrupt bit. 0 All bits in the USBEoTIntSt register are 0. 1 At least one bit in the USBEoTIntSt is set. 1 NDDR New DD Request Interrupt bit. 0 All bits in the USBNDDRIntSt register are 0. 1 At least one bit in the USBNDDRIntSt is set. 2 ERR System Error Interrupt bit. 0 All bits in the USBSysErrIntSt register are 0. 1 At least one bit in the USBSysErrIntSt is set. 31:3 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 0 0 NA 11.10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294) Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn is a read/write register. Table 232. USB DMA Interrupt Enable register (USBDMAIntEn - address 0x5000 C294) bit description Bit Symbol Value Description Reset value 0 EOT End of Transfer Interrupt enable bit. 0 0 The End of Transfer Interrupt is disabled. 1 The End of Transfer Interrupt is enabled. 1 NDDR New DD Request Interrupt enable bit. 0 0 The New DD Request Interrupt is disabled. 1 The New DD Request Interrupt is enabled. 2 ERR System Error Interrupt enable bit. 0 0 The System Error Interrupt is disabled. 1 The System Error Interrupt is enabled. 31:3 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 11.10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0) When the DMA transfer completes for the current DMA descriptor, either normally (descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in this register. The cause of the interrupt is recorded in the DD_status field of the descriptor. USBEoTIntSt is a read-only register. Table 233. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description Bit Symbol Value Description 31:0 EPxx Endpoint xx (2 xx 31) End of Transfer Interrupt request. Reset value 0 0 There is no End of Transfer interrupt request for endpoint xx. 1 There is an End of Transfer Interrupt request for endpoint xx. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 248 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4) Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntClr is a write-only register. Table 234. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description Bit Symbol Value Description Reset value 31:0 EPxx Clear endpoint xx (2 xx 31) End of Transfer Interrupt request. 0 0 No effect. 1 Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 11.10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8) Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntSet is a write-only register. Table 235. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description Bit Symbol Value Description Reset value 31:0 EPxx Set endpoint xx (2 xx 31) End of Transfer Interrupt request. 0 0 No effect. 1 Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 11.10.7.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0x5000 C2AC) A bit in this register is set when a transfer is requested from the USB device and no valid DD is detected for the corresponding endpoint. USBNDDRIntSt is a read-only register. Table 236. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description Bit Symbol Value Description 31:0 EPxx Endpoint xx (2 xx 31) new DD interrupt request. Reset value 0 0 There is no new DD interrupt request for endpoint xx. 1 There is a new DD interrupt request for endpoint xx. 11.10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000 C2B0) Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt register. Writing zero has no effect. USBNDDRIntClr is a write-only register. Table 237. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description Bit Symbol Value Description Reset value 31:0 EPxx Clear endpoint xx (2 xx 31) new DD interrupt request. 0 0 No effect. 1 Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. 11.10.7.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0x5000 C2B4) Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt register. Writing zero has no effect. USBNDDRIntSet is a write-only register UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 249 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 238. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description Bit Symbol Value Description Reset value 31:0 EPxx Set endpoint xx (2 xx 31) new DD interrupt request. 0 0 No effect. 1 Set the EPxx new DD interrupt request in the USBNDDRIntSt register. 11.10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8) If a system error (AHB bus error) occurs when transferring the data or when fetching or updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read-only register. Table 239. USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description Bit Symbol Value Description 31:0 EPxx Endpoint xx (2 xx 31) System Error Interrupt request. Reset value 0 0 There is no System Error Interrupt request for endpoint xx. 1 There is a System Error Interrupt request for endpoint xx. 11.10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC) Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt register. Writing zero has no effect. USBSysErrIntClr is a write-only register. Table 240. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description Bit Symbol Value Description 31:0 EPxx Clear endpoint xx (2 xx 31) System Error Interrupt request. Reset value 0 0 No effect. 1 Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. 11.10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0) Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt register. Writing zero has no effect. USBSysErrIntSet is a write-only register. Table 241. USB System Error Interrupt Set register (USBSysErrIntSet - address 0x5000 C2C0) bit description Bit Symbol Value Description Reset value 31:0 EPxx Set endpoint xx (2 xx 31) System Error Interrupt request. 0 0 No effect. 1 Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. 11.11 Interrupt handling UM10360 User manual This section describes how an interrupt event on any of the endpoints is routed to the Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event handling, see Figure 30. All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet has been successfully transmitted or when a NAK signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see Section 11.12.3. For isochronous endpoints, a frame interrupt is generated every 1 ms. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 250 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller The interrupt handling is different for Slave and DMA mode. Slave mode If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For non-isochronous endpoints, all endpoint interrupt events are divided into two types by the corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the EP_SLOW bit in USBDevIntSt. For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms. The USBDevIntSt register holds the status of all endpoint interrupt events as well as the status of various other interrupts (see Section 11.10.2.2). By default, all interrupts (if enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt register to request low priority interrupt handling. However, the USBDevIntPri register can route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt register. Only one of the EP_FAST and FRAME interrupt events can be routed to the USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both interrupt events are routed to USB_INT_REQ_LP. Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for low priority interrupt handling by software. The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the USBIntSt register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set. DMA mode If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer is enabled for the corresponding endpoint in the USBEpDMASt register. Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End of transfer interrupt, new DD request interrupt, and system error interrupt. These interrupt events set a bit for each endpoint in the respective registers USBEoTIntSt, USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request interrupts and system error interrupt events are routed to the NDDR and ERR bits respectively in the USBDMAStInt register. The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in USBIntSt, the interrupt is routed to the NVIC. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 251 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller interrupt event on EPn USBEpIntSt n from other Endpoints .... .... USBEpIntEn[n] .... USBEpIntPri[n] .... Slave mode USBDevIntSt FRAME EP_FAST EP_SLOW .... ERR_INT USBDevIntPri[0] .... USBDevIntPri[1] USBDMARSt n to DMA engine USBEoTIntST 0 .... 31 USBNDDRIntSt 0 .... 31 USBSysErrIntSt 0 .... 31 DMA Mode USBDMAIntSt EOT NDDR ERR For simplicity, USBDevIntEn and USBDMAIntEn are not shown. Fig 30. Interrupt event handling USBIntSt USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to NVIC UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 252 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.12 Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). The USBCmdCode (Table 221) and USBCmdData (Table 222) registers are used for these accesses. A complete access consists of two phases: 1. Command phase: the USBCmdCode register is written with the CMD_PHASE field set to the value 0x05 (Command), and the CMD_CODE field set to the desired command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is set. 2. Data phase (optional): for writes, the USBCmdCode register is written with the CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with the desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt is set. For reads, USBCmdCode register is written with the CMD_PHASE field set to the value 0x02 (Read), and the CMD_CODE field set with command code the read corresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set, indicating the data is available for reading in the USBCmdData register. In the case of multi-byte registers, the least significant byte is accessed first. An overview of the available commands is given in Table 242. Here is an example of the Read Current Frame Number command (reading 2 bytes): USBDevIntClr = 0x30; // Clear both CCEMPTY & CDFULL USBCmdCode = 0x00F50500; // CMD_CODE=0xF5, CMD_PHASE=0x05(Command) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY interrupt bit. USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read) while (!(USBDevIntSt & 0x20)); // Wait for CDFULL. USBDevIntClr = 0x20; // Clear CDFULL. CurFrameNum = USBCmdData; // Read Frame number LSB byte. USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read) while (!(USBDevIntSt & 0x20)); // Wait for CDFULL. Temp = USBCmdData; // Read Frame number MSB byte USBDevIntClr = 0x20; // Clear CDFULL interrupt bit. CurFrameNum = CurFrameNum | (Temp << 8); Here is an example of the Set Address command (writing 1 byte): USBDevIntClr = 0x10; // Clear CCEMPTY. USBCmdCode = 0x00D00500; // CMD_CODE=0xD0, CMD_PHASE=0x05(Command) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY. USBCmdCode = 0x008A0100; // CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA), // CMD_PHASE=0x01(Write) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 253 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 242. SIE command code table Command name Recipient Device commands Set Address Device Configure Device Device Set Mode Device Read Current Frame Number Device Read Test Register Device Set Device Status Device Get Device Status Device Get Error Code Device Read Error Status Device Endpoint Commands Select Endpoint Endpoint 0 Endpoint 1 Endpoint xx Select Endpoint/Clear Interrupt Endpoint 0 Endpoint 1 Endpoint xx Set Endpoint Status Endpoint 0 Endpoint 1 Endpoint xx Clear Buffer Selected Endpoint Validate Buffer Selected Endpoint Code (Hex) D0 D8 F3 F5 FD FE FE FF FB 00 01 xx 40 41 xx  40 40 41 xx  40 F2 FA Data phase Write 1 byte Write 1 byte Write 1 byte Read 1 or 2 bytes Read 2 bytes Write 1 byte Read 1 byte Read 1 byte Read 1 byte Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte Read 1 byte Read 1 byte Write 1 byte Write 1 byte Write 1 byte Read 1 byte (optional) None 11.12.1 Set Address (Command: 0xD0, Data: write 1 byte) The Set Address command is used to set the USB assigned address and enable the (embedded) function. The address set in the device will take effect after the status stage of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default endpoint). Table 243. Set Address command bit description Bit Symbol Description 6:0 DEV_ADDR Device address set by the software. After a bus reset this field is set to 0x00. 7 DEV_EN Device Enable. After a bus reset this bit is set to 1. 0: Device will not respond to any packets. 1: Device will respond to packets for function address DEV_ADDR. Reset value 0x00 0 11.12.2 Configure Device (Command: 0xD8, Data: write 1 byte) A value of 1 written to the register indicates that the device is configured and all the enabled non-control endpoints will respond. Control endpoints are always enabled and respond even if the device is not configured, in the default state. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 254 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 244. Configure Device command bit description Bit Symbol Description 0 CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0). 7:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value NA 11.12.3 Set Mode (Command: 0xF3, Data: write 1 byte) Table 245. Set Mode command bit description Bit Symbol Value Description Reset value 0 AP_CLK Always PLL Clock. 0 0 USB_NEED_CLK is functional; the 48 MHz clock can be stopped when the device enters suspend state. 1 USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be stopped when the device enters suspend state. 1 INAK_CI Interrupt on NAK for Control IN endpoint. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts. 2 INAK_CO Interrupt on NAK for Control OUT endpoint. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. 3 INAK_II Interrupt on NAK for Interrupt IN endpoint. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts. 4 INAK_IO[1] Interrupt on NAK for Interrupt OUT endpoints. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. 5 INAK_BI Interrupt on NAK for Bulk IN endpoints. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts. 6 INAK_BO[2] Interrupt on NAK for Bulk OUT endpoints. 0 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. 7 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. [1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints. [2] This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints. 11.12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 255 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller • In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. • In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 11.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes) The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk and AHB slave clock) are running. 11.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) The Set Device Status command sets bits in the Device Status Register. Table 246. Set Device Status command bit description Bit Symbol Value Description Reset value 0 CON The Connect bit indicates the current connect status of the device. It controls the 0 CONNECT output pin, used for SoftConnect. Reading the connect bit returns the current connect status. This bit is cleared by hardware when the VBUS status input is LOW for more than 3 ms. The 3 ms delay filters out temporary dips in the VBUS voltage. 0 Writing a 0 will make the CONNECT pin go HIGH. 1 Writing a 1 will make the CONNECT pin go LOW. 1 CON_CH Connect Change. 0 0 This bit is cleared when read. 1 This bit is set when the device’s pull-up resistor is disconnected because VBUS disappeared. The DEV_STAT interrupt is generated when this bit is 1. 2 SUS Suspend: The Suspend bit represents the current suspend state. 0 When the device is suspended (SUS = 1) and the CPU writes a 0 into it, the device will generate a remote wake-up. This will only happen when the device is connected (CON = 1). When the device is not connected or not suspended, writing a 0 has no effect. Writing a 1 to this bit has no effect. 0 This bit is reset to 0 on any activity. 1 This bit is set to 1 when the device hasn’t seen any activity on its upstream port for more than 3 ms. 3 SUS_CH Suspend (SUS) bit change indicator. The SUS bit can toggle because: 0 • The device goes into the suspended state. • The device is disconnected. • The device receives resume signalling on its upstream port. This bit is cleared when read. 0 SUS bit not changed. 1 SUS bit changed. At the same time a DEV_STAT interrupt is generated. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 256 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 246. Set Device Status command bit description Bit Symbol Value Description 4 RST Bus Reset bit. On a bus reset, the device will automatically go to the default state. In the default state: • Device is unconfigured. • Will respond to address 0. • Control endpoint will be in the Stalled state. • All endpoints are unrealized except control endpoints EP0 and EP1. • Data toggling is reset for all endpoints. • All buffers are cleared. • There is no change to the endpoint interrupt status. • DEV_STAT interrupt is generated. Note: Bus resets are ignored when the device is not connected (CON=0). 0 This bit is cleared when read. 1 This bit is set when the device receives a bus reset. A DEV_STAT interrupt is generated. 7:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0 NA 11.12.7 Get Device Status (Command: 0xFE, Data: read 1 byte) The Get Device Status command returns the Device Status Register. Reading the device status returns 1 byte of data. The bit field definition is same as the Set Device Status Register as shown in Table 246. Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared before executing the Get Device Status command. 11.12.8 Get Error Code (Command: 0xFF, Data: read 1 byte) Different error conditions can arise inside the SIE. The Get Error Code command returns the last error code that occurred. The 4 least significant bits form the error code. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 257 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 247. Get Error Code command bit description Bit Symbol Value Description 3:0 EC Error Code. 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification. 0100 Error in Token CRC. 0101 Error in Data CRC. 0110 Time Out Error. 0111 Babble. 1000 Error in End of Packet. 1001 Sent/Received NAK. 1010 Sent Stall. 1011 Buffer Overrun Error. 1100 Sent Empty Packet (ISO Endpoints only). 1101 Bitstuff Error. 1110 Error in Sync. 1111 Wrong Toggle Bit in Data PID, ignored data. 4 EA - The Error Active bit will be reset once this register is read. 7:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset value 0x0 NA 11.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) This command reads the 8-bit Error register from the USB device. This register records which error events have recently occurred in the SIE. If any of these bits are set, the ERR_INT bit of USBDevIntSt is set. The error bits are cleared after reading this register. Table 248. Read Error Status command bit description Bit Symbol Description 0 PID_ERR PID encoding error or Unknown PID or Token CRC. 1 UEPKT Unexpected Packet - any packet sequence violation from the specification. 2 DCRC Data CRC error. 3 TIMEOUT Time out error. 4 EOP End of packet error. 5 B_OVRN Buffer Overrun. 6 BTSTF Bit stuff error. 7 TGL_ERR Wrong toggle bit in data PID, ignored data. Reset value 0 0 0 0 0 0 0 0 11.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s). The command code of the Select Endpoint command is equal to the physical endpoint number. In the case of a single buffered endpoint the B_2_FULL bit is not valid. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 258 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 249. Select Endpoint command bit description Bit Symbol Value Description Reset value 0 FE Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s). 0 For IN endpoints, the FE bit gives the ANDed result of the B_1_FULL and B_2_FULL bits. For OUT endpoints, the FE bit gives ORed result of the B_1_FULL and B_2_FULL bits. For single buffered endpoints, this bit simply reflects the status of B_1_FULL. 0 For an IN endpoint, at least one write endpoint buffer is empty. 1 For an OUT endpoint, at least one endpoint read buffer is full. 1 ST Stalled endpoint indicator. 0 0 The selected endpoint is not stalled. 1 The selected endpoint is stalled. 2 STP SETUP bit: the value of this bit is updated after each successfully received 0 packet (i.e. an ACKed package on that particular physical endpoint). 0 The STP bit is cleared by doing a Select Endpoint/Clear Interrupt on this endpoint. 1 The last received packet for the selected endpoint was a SETUP packet. 3 PO Packet over-written bit. 0 0 The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’ command. 1 The previously received packet was over-written by a SETUP packet. 4 EPN EP NAKed bit indicates sending of a NAK. If the host sends an OUT packet to a 0 filled OUT buffer, the device returns NAK. If the host sends an IN token packet to an empty IN buffer, the device returns NAK. 0 The EPN bit is reset after the device has sent an ACK after an OUT packet or when the device has seen an ACK after sending an IN packet. 1 The EPN bit is set when a NAK is sent and the interrupt on NAK feature is enabled. 5 B_1_FULL The buffer 1 status. 0 0 Buffer 1 is empty. 1 Buffer 1 is full. 6 B_2_FULL The buffer 2 status. 0 0 Buffer 2 is empty. 1 Buffer 2 is full. 7 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 11.12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte) Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the following differences: • They clear the bit corresponding to the endpoint in the USBEpIntSt register. • In case of a control OUT endpoint, they clear the STP and PO bits in the corresponding Select Endpoint Register. • Reading one byte is obligatory. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 259 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Remark: This command may be invoked by using the USBCmdCode and USBCmdData registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the USBEpIntClr register is recommended. 11.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional)) The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical endpoint number in hex. Not all bits can be set for all types of endpoints. Table 250. Set Endpoint Status command bit description Bit Symbol Value Description Reset value 0 ST Stalled endpoint bit. A Stalled control endpoint is automatically unstalled when it 0 receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the CPU can stall it again by setting this bit. When a stalled endpoint is unstalled - either by the Set Endpoint Status command or by receiving a SETUP token - it is also re-initialized. This flushes the buffer: in case of an OUT buffer it waits for a DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID. There is no change of the interrupt status of the endpoint. When already unstalled, writing a zero to this bit initializes the endpoint. When an endpoint is stalled by the Set Endpoint Status command, it is also re-initialized. 0 The endpoint is unstalled. 1 The endpoint is stalled. 4:1 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 5 DA Disabled endpoint bit. 0 0 The endpoint is enabled. 1 The endpoint is disabled. 6 RF_MO Rate Feedback Mode. 0 0 Interrupt endpoint is in the Toggle mode. 1 Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes place without data toggle bit. 7 CND_ST Conditional Stall bit. 0 0 Unstalls both control endpoints. 1 Stall both control endpoints, unless the STP bit is set in the Select Endpoint register. It is defined only for control OUT endpoints. 11.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional)) When an OUT packet sent by the host has been received successfully, an internal hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by returning a NAK. When the device software has read the data, it should free the buffer by issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the buffer is cleared, new packets will be accepted. When bit 0 of the optional data byte is 1, the previously received packet was over-written by a SETUP packet. The Packet over-written bit is used only in control transfers. According to the USB specification, a SETUP packet should be accepted irrespective of the buffer status. The software should always check the status of the PO bit after reading UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 260 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller the SETUP data. If it is set then it should discard the previously read data, clear the PO bit by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and again check the status of the PO bit. See Section 11.14 “Slave mode operation” for a description of when this command is used. Table 251. Clear Buffer command bit description Bit Symbol Value Description Reset value 0 PO Packet over-written bit. This bit is only applicable to the control endpoint EP0. 0 0 The previously received packet is intact. 1 The previously received packet was over-written by a later SETUP packet. 7:1 - - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11.12.14 Validate Buffer (Command: 0xFA, Data: none) When the CPU has written data into an IN buffer, software should issue a Validate Buffer command. This tells hardware that the buffer is ready for sending on the USB bus. Hardware will send the contents of the buffer when the next IN token packet is received. Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty. A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP packet. For the control endpoint the validated buffer will be invalidated when a SETUP packet is received. See Section 11.14 “Slave mode operation” for a description of when this command is used. 11.13 USB device controller initialization The LPC176x/5x USB device controller initialization includes the following steps: 1. Enable the device controller by setting the PCUSB bit of PCONP. 2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk and the desired frequency for cclk. For the procedure for determining the PLL setting and configuration, see Section 4.5.11 “Procedure for determining PLL0 settings”. 3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until they are set. 4. Enable the USB pin functions by writing to the corresponding PINSEL register. 5. Disable the pull-ups and pull-downs on the VBUS pin using the corresponding PINMODE register by putting the pin in the “pin has neither pull-up nor pull-down resistor enabled” mode. See Section 8.4 “Pin mode select register values”. 6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 261 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 7. Enable endpoint interrupts (Slave mode): – Clear all endpoint interrupts using USBEpIntClr. – Clear any device interrupts using USBDevIntClr. – Enable Slave mode for the desired endpoints by setting the corresponding bits in USBEpIntEn. – Set the priority of each enabled interrupt using USBEpIntPri. – Configure the desired interrupt mode using the SIE Set Mode command. – Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW, and possibly EP_FAST). 8. Configure the DMA (DMA mode): – Disable DMA operation for all endpoints using USBEpDMADis. – Clear any pending DMA requests using USBDMARClr. – Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and USBSysErrIntClr. – Prepare the UDCA in system memory. – Write the desired address for the UDCA to USBUDCAH. – Enable the desired endpoints for DMA operation using USBEpDMAEn. – Set EOT, DDR, and ERR bits in USBDMAIntEn. 9. Install USB interrupt handler in the NVIC by writing its address to the appropriate vector table location and enabling the USB interrupt in the NVIC. 10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address command. A bus reset will also cause this to happen. 11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status command. The configuration of the endpoints varies depending on the software application. By default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional endpoints are enabled and configured by software after a SET_CONFIGURATION or SET_INTERFACE device request is received from the host. 11.14 Slave mode operation In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface. 11.14.1 Interrupt generation In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated in response to an endpoint interrupt. Endpoint interrupts are enabled using the USBEpIntEn register, and are observable in the USBEpIntSt register. All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet is successfully transmitted, or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 262 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in USBDevIntSt) occurs. 11.14.2 Data transfer for OUT endpoints When the software wants to read the data from an endpoint buffer it should set the RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register, and set the PKT_RDY bit (Table 217). Software can now start reading the data from the USBRxData register (Table 216). When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in the USBDevSt register. Software now issues a Clear Buffer (refer to Table 251) command. The endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the next packet will be received irrespective of whether the buffer has been cleared. Any data not read from the buffer before the end of the frame is lost. See Section 11.16 “Double buffered endpoint operation” for more details. If the software clears RD_EN before the entire packet is read, reading is terminated, and the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the data will be read from the beginning. 11.14.3 Data transfer for IN endpoints When writing data to an endpoint buffer, WR_EN (Section 11.10.5.5 “USB Control register (USBCtrl - 0x5000 C228)”) is set and software writes to the number of bytes it is going to send in the packet to the USBTxPLen register (Section 11.10.5.4). It can then write data continuously in the USBTxData register. When the number of bytes programmed in USBTxPLen have been written to USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register. Software issues a Validate Buffer (Section 11.12.14 “Validate Buffer (Command: 0xFA, Data: none)”) command. The endpoint is now ready to send the packet. For IN isochronous endpoints, the data in the buffer will be sent only if the buffer is validated before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the next frame. If the software clears WR_EN before the entire packet is written, writing will start again from the beginning the next time WR_EN is set for this endpoint. Both RD_EN and WR_EN can be high at the same time for the same logical endpoint. Interleaved read and write operation is possible. 11.15 DMA operation In DMA mode, the DMA transfers data between RAM and the endpoint buffer. The following sections discuss DMA mode operation. Background information is given in sections Section 11.15.2 “USB device communication area” and Section 11.15.3 “Triggering the DMA engine”. The fields of the DMA Descriptor are described in Section 11.15.4 “The DMA descriptor”. The last three sections describe DMA operation: Section 11.15.5 “Non-isochronous endpoint operation”, Section 11.15.6 “Isochronous endpoint operation”, and Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode operation”. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 263 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.1 Transfer terminology Within this section three types of transfers are mentioned: 1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers to these simply as transfers. Within this section they are referred to as USB transfers to distinguish them from DMA transfers. A USB transfer is composed of transactions. Each transaction is composed of packets. 2. DMA transfers – the transfer of data between an endpoint buffer and system memory (RAM). 3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of data between an endpoint buffer and system memory (RAM). A DMA transfer is composed of one or more packet transfers. 11.15.2 USB device communication area The CPU and DMA controller communicate through a common area of memory, called the USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs for unrealized endpoints and endpoints disabled for DMA operation are ignored and can be set to a NULL (0x0) value. The start address of the UDCA is stored in the USBUDCAH register. The UDCA can reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA controller. Figure 31 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH) register and DMA Descriptors. UDCA 0 1 2 DDP-EP2 NULL NULL Next_DD_pointer DD-EP2-a UDCA HEAD REGISTER NULL 16 DDP-EP16 Next_DD_pointer DD-EP16-a 31 DDP-EP31 Fig 31. UDCA Head register and DMA Descriptors Next_DD_pointer DD-EP2-b Next_DD_pointer DD-EP16-b Next_DD_pointer DD-EP2-c NULL NULL UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 264 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.3 Triggering the DMA engine An endpoint raises a DMA request when Slave mode is disabled by setting the corresponding bit in the USBEpIntEn register to 0 (Section 11.10.3.2) and an endpoint interrupt occurs (see Section 11.10.7.1 “USB DMA Request Status register (USBDMARSt - 0x5000 C250)”). A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for the endpoint. All endpoints share a single DMA channel to minimize hardware overhead. If more than one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint number is processed first. In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command (Section 11.12.3). 11.15.4 The DMA descriptor DMA transfers are described by a data structure called the DMA Descriptor (DD). DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at word-aligned addresses. DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints are five words long. The parameters associated with a DMA transfer are: • The start address of the DMA buffer • The length of the DMA buffer • The start address of the next DMA descriptor • Control information • Count information (number of bytes transferred) • Status information Table 252 lists the DMA descriptor fields. Table 252. DMA descriptor Word Access position (H/W) Access (S/W) 0 R R/W Bit position 31:0 Description Next_DD_pointer UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 265 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Table 252. DMA descriptor Word Access position (H/W) Access (S/W) 1 R R/W R R/W - - R R/W R R/W R/W[1] R/W 2 R/W R/W 3 R/W R/I W R/I W R/I W R/I W R/I R W - - R/W R/I 4 R/W R/W Bit position 1:0 2 3 4 15:5 31:16 31:0 0 4:1 5 6 7 13:8 15:14 31:16 31:0 Description DMA_mode (00 -Normal; 01 - ATLE) Next_DD_valid (1 - valid; 0 - invalid) Reserved Isochronous_endpoint (1 - isochronous; 0 - non-isochronous) Max_packet_size DMA_buffer_length This value is specified in bytes for non-isochronous endpoints and in number of packets for isochronous endpoints. DMA_buffer_start_addr DD_retired (To be initialized to 0) DD_status (To be initialized to 0000): 0000 - NotServiced 0001 - BeingServiced 0010 - NormalCompletion 0011 - DataUnderrun (short packet) 1000 - DataOverrun 1001 - SystemError Packet_valid (To be initialized to 0) LS_byte_extracted (ATLE mode) (To be initialized to 0) MS_byte_extracted (ATLE mode) (To be initialized to 0) Message_length_position (ATLE mode) Reserved Present_DMA_count (To be initialized to 0) Isochronous_packetsize_memory_address [1] Write-only in ATLE mode Legend: R - Read; W - Write; I - Initialize 11.15.4.1 Next_DD_pointer Pointer to the memory location from where the next DMA descriptor will be fetched. 11.15.4.2 DMA_mode Specifies the DMA mode of operation. Two modes have been defined: Normal and Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is extracted from the incoming data. See Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode operation” on page 272 for more details. 11.15.4.3 Next_DD_valid This bit indicates whether the software has prepared the next DMA descriptor. If set, the DMA engine fetches the new descriptor when it is finished with the current one. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 266 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.4.4 Isochronous_endpoint When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence 5 words have to be read when fetching it. 11.15.4.5 Max_packet_size The maximum packet size of the endpoint. This parameter is used while transferring the data for IN endpoints from the memory. It is used for OUT endpoints to detect the short packet. This is applicable to non-isochronous endpoints only. This field should be set to the same MPS value that is assigned for the endpoint using the USBMaxPSize register. 11.15.4.6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor. In Normal mode operation, software sets this value for both IN and OUT endpoints. In ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints, hardware sets this value using the extracted length of the data stream. For isochronous endpoints, DMA_buffer_length is specified in number of packets, for non-isochronous endpoints in bytes. 11.15.4.7 DMA_buffer_start_addr The address where the data is read from or written to. This field is updated each time the DMA engine finishes transferring a packet. 11.15.4.8 DD_retired This bit is set by hardware when the DMA engine finishes the current descriptor. This happens when the end of the buffer is reached, a short packet is transferred (non-isochronous endpoints), or an error condition is detected. 11.15.4.9 DD_status The status of the DMA transfer is encoded in this field. The following codes are defined: UM10360 User manual • NotServiced - No packet has been transferred yet. • BeingServiced - At least one packet is transferred. • NormalCompletion - The DD is retired because the end of the buffer is reached and there were no errors. The DD_retired bit is also set. • DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is terminated because a short packet is received. The DD_retired bit is also set. • DataOverrun - The end of the DMA buffer is reached in the middle of a packet transfer. This is an error situation. The DD_retired bit is set. The present DMA count field is equal to the value of DMA_buffer_length. The packet must be re-transmitted from the endpoint buffer in another DMA transfer. The corresponding EPxx_DMA_ENABLE bit in USBEpDMASt is cleared. • SystemError - The DMA transfer being serviced is terminated because of an error on the AHB bus. The DD_retired bit is not set in this case. The corresponding EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen while updating the DD, the DD fields in RAM may be unreliable. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 267 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.4.10 Packet_valid This bit is used for isochronous endpoints. It indicates whether the last packet transferred to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was received without errors. See Section 11.15.6 “Isochronous endpoint operation” on page 270 for isochronous endpoint operation. This bit is unnecessary for non-isochronous endpoints because a DMA request is generated only for packets without errors, and thus Packet_valid will always be set when the request is generated. 11.15.4.11 LS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16. 11.15.4.12 MS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of the transfer size has been extracted. The size extracted is reflected in the DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and MS_byte_extracted bits are set. 11.15.4.13 Present_DMA_count The number of bytes transferred by the DMA engine. The DMA engine updates this field after completing each packet transfer. For isochronous endpoints, Present_DMA_count is the number of packets transferred; for non-isochronous endpoints, Present_DMA_count is the number of bytes. 11.15.4.14 Message_length_position Used in ATLE mode. This field gives the offset of the message length position embedded in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates that the message length starts from the first byte of the first packet. 11.15.4.15 Isochronous_packetsize_memory_address The memory buffer address where the packet size information along with the frame number has to be transferred or fetched. See Figure 32. This is applicable to isochronous endpoints only. 11.15.5 Non-isochronous endpoint operation 11.15.5.1 Setting up DMA transfers Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled for DMA transfer. These DDs are present in on-chip RAM. The start address of the first DD is programmed into the DMA Description pointer (DDP) location for the corresponding endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in the USBEpDMAEn register (Section 11.10.7.6).The DMA_mode bit field in the descriptor is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in Table 252. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 268 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints). 11.15.5.2 Finding DMA Descriptor When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first determine whether a new descriptor has to the fetched or not. A new descriptor does not have to be fetched if the last packet transferred was for the same endpoint and the DD is not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this condition (see Section 11.15.5.4 “Optimizing descriptor fetch” on page 269). If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid. In this case the NDDR interrupt is raised. All other word-aligned addresses are considered valid. When the DD is fetched, the DD status word (word 3) is read first and the status of the DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the DMA engine will read the control word (word 1) of the DD. If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0) of the DD and load it to the DDP. The new DDP is written to the UDCA area. The full DD (4 words) will then be fetched from the address in the DDP. The DD will give the details of the DMA transfer to be done. The DMA engine will load its hardware resources with the information fetched from the DD (start address, DMA count etc.). If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit. 11.15.5.3 Transferring the data For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and transferred to on-chip RAM memory locations starting from DMA_buffer_start_addr. For IN endpoints, the data is fetched from on-chip RAM at DMA_buffer_start_addr and written to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are updated after each packet is transferred. 11.15.5.4 Optimizing descriptor fetch A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet transfer, hardware sets an internal flag called DMA_PROCEED. The DMA_PROCEED flag is cleared after the required number of bytes specified in the DMA_buffer_length field is transferred. It is also cleared when the software writes into the USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation for any endpoint. 11.15.5.5 Ending the packet transfer On completing a packet transfer, the DMA engine writes back the DD with updated status information to the same memory location from where it was read. The DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are updated. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 269 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller A DD can have the following types of completion: Normal completion - If the current packet is fully transferred and the Present_DMA_count field equals the DMA_buffer_length, the DD has completed normally. The DD will be written back to memory with DD_retired set and DD_status set to NormalCompletion. The EOT interrupt is raised for this endpoint. USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs. The DD will be written back to the memory with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT interrupt is raised for this endpoint. Error completion - If the current packet is partially transferred i.e. the end of the DMA buffer is reached in the middle of the packet transfer, an error situation occurs. The DD is written back with DD_retired set and DD_status set to the DataOverrun status code. The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt register is cleared. The packet will be re-sent from the endpoint buffer to memory when the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn register. 11.15.5.6 No_Packet DD For an IN transfer, if the system does not have any data to send for a while, it can respond to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt corresponding to the endpoint without transferring a packet. The DD is retired with a status code of NormalCompletion. This can be repeated as often as necessary. The device will respond to IN token packets on the USB bus with a NAK until a DD with a data packet is programmed and the DMA transfers the packet into the endpoint buffer. 11.15.6 Isochronous endpoint operation For isochronous endpoints, the packet size can vary for each packet. There is one packet per isochronous endpoint for each frame. 11.15.6.1 Setting up DMA transfers Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of the Isochronous_packetsize_memory_address field. All other fields are initialized the same as for non-isochronous endpoints. For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in frames rather than bytes. 11.15.6.2 Finding the DMA Descriptor Finding the descriptors is done in the same way as that for a non-isochronous endpoint. A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME interrupt. On processing the request, the DMA engine will fetch the descriptor and if Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address from the fifth word of the DD. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 270 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.6.3 Transferring the Data The data is transferred to or from the memory location DMA_buffer_start_addr. After the end of the packet transfer the Present_DMA_count value is incremented by 1. The isochronous packet size is stored in memory as shown in Figure 32. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size – one word for each packet to transfer. OUT endpoints At the completion of each frame, the packet size is written to the address location in Isochronous_packet_size_memory_address, and Isochronous_packet_size_memory_address is incremented by 4. IN endpoints Only the Packet_length field of the isochronous packet size word is used. For each frame, an isochronous data packet of size specified by this field is transferred from the USB device to the host, and Isochronous_packet_size_memory_address is incremented by 4 at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by the USB device. 11.15.6.4 DMA descriptor completion DDs for isochronous endpoints can only end with a status code of NormalCompletion since there is no short packet on Isochronous endpoints, and the USB transfer continues indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous endpoints. 11.15.6.5 Isochronous OUT Endpoint Operation Example Assume that an isochronous endpoint is programmed for the transfer of 10 frames and that the transfer begins when the frame number is 21. After transferring four frames with packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map appear as shown in Figure 32. The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35. The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 271 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller Next_DD_Pointer W0 NULL DMA_buffer_length W1 0x000A Max_packet_size 0x0 Isochronous_endpoint 1 Next_DD_Valid 0 DMA_mode 0 W2 Present_DMA_Count W3 0x0 DMA_buffer_start_addr 0x80000000 ATLE settings Packet_Valid NA NA DD_Status 0x0 DD_Retired 0 Isocronous_packetsize_memory_address W4 0x60000000 after 4 packets W0 0x0 W1 0x000A0010 W2 0x80000035 W3 0x4 - - 0x1 0 W4 0x60000010 frame_ number Packet_Valid Packet_Length 31 16 15 0 21 1 10 22 1 15 23 1 8 24 1 20 FULL EMPTY data memory packet size memory Fig 32. Isochronous OUT endpoint operation example 11.15.7 Auto Length Transfer Extraction (ATLE) mode operation Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are capable of concatenating small USB transfers (delta transfers) to form a single large USB transfer. For OUT USB transfers, the device hardware has to break up this concatenated transfer back into the original delta transfers and transfer them to separate DMA buffers. This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE) mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 272 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller OUT transfers in ATLE mode data to be sent by host driver 160 bytes data in packets as seen on USB 64 bytes 64 bytes data to be stored in RAM by DMA engine 160 bytes DMA_buffer_start_addr of DD1 100 bytes 32 bytes 32 bytes 64 bytes 4 bytes 100 bytes DMA_buffer_start_addr of DD2 Fig 33. Data transfer in ATLE mode Figure 33 shows a typical OUT USB transfer in ATLE mode, where the host concatenates two USB transfers of 160 bytes and 100 bytes, respectively. Given a MaxPacketSize of 64, the device hardware interprets this USB transfer as four packets of 64 bytes and a short packet of 4 bytes. The third and fourth packets are concatenated. Note that in Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32, and 64 and 36 bytes. It is now the responsibility of the DMA engine to separate these two USB transfers and put them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1 (DD1) and DMA Descriptor 2 (DD2). Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the USB transfer) specified by Message_length_position from the incoming data packets and writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the DMA_buffer_length are extracted in the event they are split between two packets, the flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the normal mode. The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again for the next DD. If DD1 is retired during the transfer of a concatenated packet (such as the third packet in Figure 33), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1 is retired with DD_status set to the DataOverrun status code. This is treated as an error condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared by hardware. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 273 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer. IN transfers in ATLE mode For IN USB transfers from the device to the host, DMA_buffer_length is set by the device software as in normal mode. In ATLE mode, the device concatenates data from multiple DDs to form a single USB transfer. If a DD is retired in the middle of a packet (packet size is less than MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s buffer. If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer length for the current DD has completed before the MaxPacketSize packet boundary, then the available bytes from current DD are sent as a short packet on USB, which marks the end of the USB transfer for the host. If the last buffer length completes on a MaxPacketSize packet boundary, the device software must program the next DD with DMA_buffer_length field 0, so that an empty packet is sent by the device to mark the end of the USB transfer for the host. 11.15.7.1 Setting up the DMA transfer For OUT endpoints, the host hardware needs to set the field Message_length_position in the DD. This indicates the start location of the message length in the incoming data packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT endpoints because this field is updated by the device hardware after the extraction of the buffer length. For IN endpoints, descriptors are set in the same way as in normal mode operation. Since a single packet can be split between two DDs, software should always keep two DDs ready, except for the last DMA transfer which ends with a short or empty packet. 11.15.7.2 Finding the DMA Descriptor DMA descriptors are found in the same way as the normal mode operation. 11.15.7.3 Transferring the Data OUT endpoints If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the hardware will extract the transfer length from the data stream and program DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and MS_byte_extracted bits will be set. IN endpoints The DMA transfer proceeds as in normal mode and continues until the number of bytes transferred equals the DMA_buffer_length. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 274 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11.15.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated. If this happens in the middle of the packet, the linked DD will get loaded and the remaining part of the packet gets transferred to or from the address pointed by the new DD. OUT endpoints If the linked DD is not valid and the packet is partially transferred to memory, the DD ends with DataOverrun status code set, and the DMA will be disabled for this endpoint. Otherwise DD_status will be updated with the NormalCompletion status code. IN endpoints If the linked DD is not valid and the packet is partially transferred to USB, the DD ends with a status code of NormalCompletion in the DD_status field. This situation corresponds to the end of the USB transfer, and the packet will be sent as a short packet. Also, when the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the end of the USB transfer. 11.16 Double buffered endpoint operation The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to increase data throughput. When a double-buffered endpoint is realized, enough space for both endpoint buffers is automatically allocated in the EP_RAM. See Section 11.10.4.1. For the following discussion, the endpoint buffer currently accessible to the CPU or DMA engine for reading or writing is said to be the active buffer. 11.16.1 Bulk endpoints For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or Validate Buffer commands. The following example illustrates how double buffering works for a Bulk OUT endpoint in Slave mode: Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is B_1. 1. The host sends a data packet to the endpoint. The device hardware puts the packet into B_1, and generates an endpoint interrupt. 2. Software clears the endpoint interrupt and begins reading the packet data from B_1. While B_1 is still being read, the host sends a second packet, which device hardware places in B_2, and generates an endpoint interrupt. 3. Software is still reading from B_1 when the host attempts to send a third packet. Since both B_1 and B_2 are full, the device hardware responds with a NAK. 4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet. B_2 becomes the active buffer. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 275 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2. 6. The host re-sends the third packet which device hardware places in B_1. An endpoint interrupt is generated. 7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer command to free B_2 to receive another packet. B_1 becomes the active buffer. Software waits for the next endpoint interrupt to occur (it already has been generated back in step 6). 8. Software responds to the endpoint interrupt by clearing it and begins reading the third packet from B_1. 9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet. B_2 becomes the active buffer. 10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0). 11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur. The active buffer is now B_2. The next data packet sent by the host will be placed in B_2. The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode: Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is B_1. The interrupt on NAK feature is enabled. 1. The host requests a data packet by sending an IN token packet. The device responds with a NAK and generates an endpoint interrupt. 2. Software clears the endpoint interrupt. The device has three packets to send. Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The active buffer is switched to B_2. 3. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the second packet. Software sends a SIE Validate Buffer command, and the active buffer is switched to B_1. 4. Software waits for the endpoint interrupt to occur. 5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint interrupt occurs. 6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and validates it using the SIE Validate Buffer command. The active buffer is switched to B_2. 7. The device successfully sends the second packet from B_2 and generates an endpoint interrupt. 8. Software has no more packets to send, so it simply clears the interrupt. 9. The device successfully sends the third packet from B_1 and generates an endpoint interrupt. 10. Software has no more packets to send, so it simply clears the interrupt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 276 of 849 NXP Semiconductors UM10360 Chapter 11: LPC176x/5x USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the USBDMARSet register. 11.16.2 Isochronous endpoints For isochronous endpoints, the active data buffer is switched by hardware when the FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do not cause the active buffer to be switched. Double buffering allows the software to make full use of the frame interval writing or reading a packet to or from the active buffer, while the packet in the other buffer is being sent or received on the bus. For an OUT isochronous endpoint, any data not read from the active buffer before the end of the frame is lost when it switches. For an IN isochronous endpoint, if the active buffer is not validated before the end of the frame, an empty packet is sent on the bus when the active buffer is switched, and its contents will be overwritten when it becomes active again. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 277 of 849 UM10360 Chapter 12: LPC176x/5x USB Host controller Rev. 3.1 — 2 April 2014 User manual 12.1 How to read this chapter The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation. 12.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the USB clock or with the Main PLL (PLL0). See Section 4.6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8.5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode, see Section 4.8.8. 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 13.11. 12.3 Introduction This section describes the host portion of the USB 2.0 OTG dual role core which integrates the host controller (OHCI compliant), device controller, and I2C interface. The I2C interface controls the external OTG ATX. The USB is a 4 wire bus that supports communication between a host and a number (127 max.) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, un-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host controller enables data exchange with various USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies to the OHCI specification. Table 253. USB (OHCI) related acronyms and abbreviations used in this chapter Acronym/abbreviation Description AHB Advanced High-Performance Bus ATX Analog Transceiver DMA Direct Memory Access FS Full Speed UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 278 of 849 NXP Semiconductors UM10360 Chapter 12: LPC176x/5x USB Host controller Table 253. USB (OHCI) related acronyms and abbreviations used in this chapter …continued Acronym/abbreviation Description LS Low Speed OHCI Open Host Controller Interface USB Universal Serial Bus 12.3.1 Features • OHCI compliant. • OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver – USBOperational: Process Lists and generate SOF Tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wake-up activity. – USBResume: Forces resume signaling on the bus. • The Host Controller has four USB states visible to the SW Driver. • HCCA register points to Interrupt and Isochronous Descriptors List. • ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List. 12.3.2 Architecture The architecture of the USB host controller is shown below in Figure 34. register interface (AHB slave) REGISTER INTERFACE DMA interface (AHB master) BUS MASTER INTERFACE HOST CONTROLLER ATX CONTROL LOGIC/ PORT MUX USB ATX USB port AHB bus USB HOST BLOCK Fig 34. USB Host controller block diagram 12.4 Interfaces The USB interface is controlled by the OTG controller. It has one USB port. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 279 of 849 NXP Semiconductors UM10360 Chapter 12: LPC176x/5x USB Host controller 12.4.1 Pin description Table 254. USB Host port pins Pin name Direction USB_D+ I/O USB_D I/O USB_UP_LED O USB_PPWR O USB_PWRD I USB_OVRCR I Description Positive differential data Negative differential data GoodLink LED control signal Port power enable Port power status Over-current status Type USB Connector USB Connector Control Host power switch Host power switch Host power switch 12.4.1.1 USB host usage note The USB block can be configured as USB host. For details on how to connect the USB port, see the USB OTG chapter, Section 13.7. The USB device/host/OTG controller is disabled after RESET and must be enabled by writing a 1 to the PCUSB bit in the PCONP register, see Table 46. 12.4.2 Software interface The software interface of the USB host block consists of a register view and the format definitions for the endpoint descriptors. For details on these two aspects see the OHCI specification. The register map is shown in the next subsection. 12.4.2.1 Register map The following registers are located in the AHB clock ‘cclk’ domain. They can be accessed directly by the processor. All registers are 32 bits wide and aligned in the word address boundaries. Table 255. USB Host register address definitions Name Address R/W[1] Function Reset value HcRevision 0x5000 C000 R BCD representation of the version of the HCI 0x10 specification that is implemented by the Host Controller. HcControl 0x5000 C004 R/W Defines the operating modes of the HC. 0x0 HcCommandStatus 0x5000 C008 R/W This register is used to receive the commands from the 0x0 Host Controller Driver (HCD). It also indicates the status of the HC. HcInterruptStatus 0x5000 C00C R/W Indicates the status on various events that cause 0x0 hardware interrupts by setting the appropriate bits. HcInterruptEnable 0x5000 C010 R/W Controls the bits in the HcInterruptStatus register and 0x0 indicates which events will generate a hardware interrupt. HcInterruptDisable 0x5000 C014 R/W The bits in this register are used to disable 0x0 corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt. HcHCCA 0x5000 C018 R/W Contains the physical address of the host controller 0x0 communication area. HcPeriodCurrentED 0x5000 C01C R Contains the physical address of the current isochronous 0x0 or interrupt endpoint descriptor. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 280 of 849 NXP Semiconductors UM10360 Chapter 12: LPC176x/5x USB Host controller Table 255. USB Host register address definitions …continued Name Address R/W[1] Function Reset value HcControlHeadED 0x5000 C020 R/W Contains the physical address of the first endpoint 0x0 descriptor of the control list. HcControlCurrentED 0x5000 C024 R/W Contains the physical address of the current endpoint 0x0 descriptor of the control list HcBulkHeadED 0x5000 C028 R/W Contains the physical address of the first endpoint 0x0 descriptor of the bulk list. HcBulkCurrentED 0x5000 C02C R/W Contains the physical address of the current endpoint 0x0 descriptor of the bulk list. HcDoneHead 0x5000 C030 R Contains the physical address of the last transfer 0x0 descriptor added to the ‘Done’ queue. HcFmInterval 0x5000 C034 R/W Defines the bit time interval in a frame and the full speed 0x2EDF maximum packet size which would not cause an overrun. HcFmRemaining 0x5000 C038 R A 14-bit counter showing the bit time remaining in the 0x0 current frame. HcFmNumber 0x5000 C03C R Contains a 16-bit counter and provides the timing 0x0 reference among events happening in the HC and the HCD. HcPeriodicStart 0x5000 C040 R/W Contains a programmable 14-bit value which determines 0x0 the earliest time HC should start processing a periodic list. HcLSThreshold 0x5000 C044 R/W Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF. 0x628h HcRhDescriptorA 0x5000 C048 R/W First of the two registers which describes the characteristics of the root hub. 0xFF000902 HcRhDescriptorB 0x5000 C04C R/W Second of the two registers which describes the characteristics of the Root Hub. 0x60000h HcRhStatus 0x5000 C050 R/W This register is divided into two parts. The lower D-word 0x0 represents the hub status field and the upper word represents the hub status change field. HcRhPortStatus[1] 0x5000 C054 R/W Controls and reports the port events on a per-port basis. 0x0 HcRhPortStatus[2] 0x5000 C058 R/W Controls and reports the port events on a per port basis. 0x0 Module_ID/Ver_Rev_ID 0x5000 C0FC R IP number, where yy (0x00) is unique version number and zz (0x00) is a unique revision number. 0x3505yyzz [1] The R/W column in Table 255 lists the accessibility of the register: a) Registers marked ‘R’ for access will return their current value when read. b) Registers marked ‘R/W’ allow both read and write. 12.4.2.2 USB Host Register Definitions Refer to the OHCI specification document on the Compaq website for register definitions. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 281 of 849 UM10360 Chapter 13: LPC176x/5x USB OTG Rev. 3.1 — 2 April 2014 User manual 13.1 How to read this chapter The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation. 13.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB clock can generated using the dedicated USB PLL (PLL1) or with the Main PLL (PLL0). See Section 4.6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8.5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode (see Section 13.10.2 and Section 4.8.8). 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 13.11. 13.3 Introduction This chapter describes the OTG and I2C portions of the USB 2.0 OTG dual role device controller which integrates the (OHCI) host controller, device controller, and I2C. The I2C interface that is part of the USB block is intended to control an external OTG transceiver, and is not the same as the I2C peripherals described in Section 19.1. USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The specification and more information on USB OTG can be found on the USB Implementers Forum web site. 13.4 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and SRP. • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 282 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 13.5 Architecture The architecture of the USB OTG controller is shown below in the block diagram. The host, device, OTG, and I2C controllers can be programmed through the register interface. The OTG controller enables dynamic switching between host and device roles through the HNP protocol. One port may be connected to an external OTG transceiver to support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I2C interface and through the external OTG transceiver interrupt signal. For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX). register interface (AHB slave) REGISTER INTERFACE DMA interface (AHB master) BUS MASTER INTERFACE USB OTG BLOCK I2C CONTROLLER OTG CONTROLLER DEVICE CONTROLLER HOST CONTROLLER OTG TRANSCEIVER ATX CONTROL LOGIC/ PORT MUX USB ATX USB port EP_RAM AHB bus Fig 35. USB OTG controller block diagram 13.6 Modes of operation The OTG controller is capable of operating in the following modes: • Host mode (see Figure 36) • Device mode (see Figure 37) • OTG mode (see Figure 38) UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 283 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 13.7 Pin configuration The OTG controller has one USB port. Table 256. USB OTG port pins Pin name Direction USB_D+ I/O USB_D I/O USB_UP_LED O USB_SCL I/O USB_SDA I/O Description Positive differential data Negative differential data GoodLink LED control signal I2C serial clock I2C serial data Pin category USB Connector USB Connector Control External OTG transceiver External OTG transceiver The following figures show different ways to realize connections to an USB device. The example described here uses an ISP1302 (ST-Ericsson) for the external OTG transceiver and the USB Host power switch LM3526-L (National Semiconductors). 13.7.1 Connecting the USB port to an external OTG transceiver For OTG functionality an external OTG transceiver must be connected to the LPC176x/5x: Use the internal USB transceiver for USB signalling and use the external OTG transceiver for OTG functionality only (see Figure 36). This option uses the internal transceiver in VP/VM mode. VDD RSTOUT VDD LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 36. USB OTG port configuration RESET_N ADR/PSW OE_N/INT_N SPEED SUSPEND SCL SDA INT_N ISP1302 VBUS ID DP DM 33 Ω 33 Ω VSSIO, VSSCORE Mini-AB connector VDD UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 284 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 13.7.2 Connecting USB as a host The USB port is connected as host using an embedded USB transceiver. There is no OTG functionality on the port. VDD USB_UP_LED LPC176x USB_D+ 33 Ω USB_D− 33 Ω 15 kΩ 15 kΩ USB_PWRD USB_OVRCR USB_PPWR ENA 5V IN LM3526-L FLAGA OUTA VSS D+ D− VDD VBUS USB-A connector Fig 37. USB host port configuration graphicID 13.7.3 Connecting USB as device The USB port is connected as device. There is no OTG functionality on the USB port. VDD USB_UP_LED VDD LPC176x USB_CONNECT USB_D+ 33 Ω USB_D− 33 Ω VBUS Fig 38. USB device port configuration VSS D+ D− VBUS USB-B connector graphicID UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 285 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 13.8 Register description The OTG and I2C registers are summarized in the following table. The Device and Host registers are explained in Table 255 and Table 189 in the USB Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide and aligned to word address boundaries. Table 257. USB OTG and I2C register address definitions Name Description Access Reset value Interrupt register USBIntSt USB Interrupt Status R/W 0x8000 0100 OTG registers OTGIntSt OTG Interrupt Status RO 0 OTGIntEn OTG Interrupt Enable R/W 0 OTGIntSet OTG Interrupt Set WO NA OTGIntClr OTG Interrupt Clear WO NA OTGStCtrl OTG Status and Control R/W 0 OTGTmr OTG Timer R/W 0xFFFF I2C registers I2C_RX I2C Receive RO NA I2C_TX I2C Transmit WO NA I2C_STS I2C Status RO 0x0A00 I2C_CTL I2C Control R/W 0 I2C_CLKHI I2C Clock High R/W 0xB9 I2C_CLKLO I2C Clock Low WO 0xB9 Clock control registers OTGClkCtrl OTG clock controller R/W 0 OTGClkSt OTG clock status RO 0 Address 0x400F C1C0 0x5000 C100 0x5000 C104 0x5000 C108 0x5000 C10C 0x5000 C110 0x5000 C114 0x5000 C300 0x5000 C300 0x5000 C304 0x5000 C308 0x5000 C30C 0x5000 C310 0x5000 CFF4 0x5000 CFF8 13.8.1 USB Interrupt Status Register (USBIntSt - 0x5000 C1C0) The USB OTG controller has seven interrupt lines. This register allows software to determine their status with a single read operation. The interrupt lines are ORed together to a single channel of the vectored interrupt controller. Remark: In a device-only configuration bits 6 to 3 of this register are reserved (see Table 192). Table 258. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description 0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. Reset Value 0 0 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 286 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 258. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description …continued Bit Symbol Description Reset Value 3 USB_HOST_INT USB host interrupt line status. This bit is read-only. 0 4 USB_ATX_INT External ATX interrupt line status. This bit is read-only. 0 5 USB_OTG_INT OTG interrupt line status. This bit is read-only. 0 6 USB_I2C_INT I2C module interrupt line status. This bit is read-only. 0 7 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 8 USB_NEED_CLK USB need clock indicator. This bit is read-only. 1 30:9 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the 1 NVIC does not see the ORed output of the USB interrupt lines. 13.8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100) Bits in this register are set by hardware when the interrupt event occurs during the HNP handoff sequence. See Section 13.9 for more information on when these bits are set. Table 259. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description Bit Symbol Description Reset Value 0 TMR Timer time-out. 0 1 REMOVE_PU Remove pull-up. 0 This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. 2 HNP_FAILURE HNP failed. 0 This bit is set by hardware to indicate that the HNP switching has failed. 3 HNP_SUCCESS HNP succeeded. 0 This bit is set by hardware to indicate that the HNP switching has succeeded. 31:4 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 13.8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104) Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT interrupt line in the USBIntSt register. The bit allocation and reset value of OTGIntEn is the same as OTGIntSt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 287 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 13.8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C) Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt. 13.8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C) Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in OTGIntSt. 13.8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110) The OTGStCtrl register allows enabling hardware tracking during the HNP hand over sequence, controlling the OTG timer, monitoring the timer count, and controlling the functions mapped to port U1 and U2. Time critical events during the switching sequence are controlled by the OTG timer. The timer can operate in two modes: 1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section 13.8.7 “OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set in OTGIntSt, and the timer will be disabled. 2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section 13.8.7 “OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set, and the timer value is reloaded into the counter. The timer is not disabled in this mode. Table 260. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description Bit Symbol Description Reset Value 1:0 PORT_FUNC Controls port function. Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 13.9. Bit 1 is reserved. 3:2 TMR_SCALE Timer scale selection. This field determines the duration 0x0 of each timer count. 00: 10 s (100 KHz) 01: 100 s (10 KHz) 10: 1000 s (1 KHz) 11: Reserved 4 TMR_MODE Timer mode selection. 0 0: monoshot 1: free running 5 TMR_EN Timer enable. When set, TMR_CNT increments. When 0 cleared, TMR_CNT is reset to 0. 6 TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0. 0 This provides a single bit control for the software to restart the timer when the timer is enabled. 7 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 288 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 260. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description …continued Bit Symbol Description Reset Value 8 B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see 0 Section 13.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. 9 A_HNP_TRACK Enable HNP tracking for A-device (host), see 0 Section 13.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. 10 PU_REMOVED When the B-device changes its role from peripheral to 0 host, software sets this bit when it removes the D+ pull-up, see Section 13.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. 15:11 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 31:16 TMR_CNT Current timer count value. 0x0 13.8.7 OTG Timer Register (OTGTmr - 0x5000 C114) Table 261. OTG Timer register (OTGTmr - address 0x5000 C114) bit description Bit Symbol Description 15:0 TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value. 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset Value 0xFFFF NA 13.8.8 OTG Clock Control Register (OTGClkCtrl - 0x5000 CFF4) This register controls the clocking of the OTG controller. Whenever software wants to access the registers, the corresponding clock control bit needs to be set. The software does not have to repeat this exercise for every register access, provided that the corresponding OTGClkCtrl bits are already set. Table 262. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit description Bit Symbol Value Description Reset Value 0 HOST_CLK_EN Host clock enable 0 0 Disable the Host clock. 1 Enable the Host clock. 1 DEV_CLK_EN Device clock enable 0 0 Disable the Device clock. 1 Enable the Device clock. 2 I2C_CLK_EN I2C clock enable 0 0 Disable the I2C clock. 1 Enable the I2C clock. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 289 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 262. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit description …continued Bit Symbol Value Description Reset Value 3 OTG_CLK_EN OTG clock enable 0 0 Disable the OTG clock. 1 Enable the OTG clock. 4 AHB_CLK_EN AHB master clock enable 0 0 Disable the AHB clock. 1 Enable the AHB clock. 31:5 - NA Reserved, user software should not write ones NA to reserved bits. The value read from a reserved bit is not defined. 13.8.9 OTG Clock Status Register (OTGClkSt - 0x5000 CFF8) This register holds the clock availability status. When enabling a clock via OTGClkCtrl, software should poll the corresponding bit in this register. If it is set, then software can go ahead with the register access. Software does not have to repeat this exercise for every access, provided that the OTGClkCtrl bits are not disturbed. Table 263. OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description Bit Symbol Value Description Reset Value 0 HOST_CLK_ON Host clock status. 0 0 Host clock is not available. 1 Host clock is available. 1 DEV_CLK_ON Device clock status. 0 0 Device clock is not available. 1 Device clock is available. 2 I2C_CLK_ON I2C clock status. 0 0 I2C clock is not available. 1 I2C clock is available. 3 OTG_CLK_ON OTG clock status. 0 0 OTG clock is not available. 1 OTG clock is available. 4 AHB_CLK_ON AHB master clock status. 0 0 AHB clock is not available. 1 AHB clock is available. 31:5 - NA Reserved, user software should not write ones NA to reserved bits. The value read from a reserved bit is not defined. 13.8.10 I2C Receive Register (I2C_RX - 0x5000 C300) This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO gives unpredictable data results. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 290 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 264. I2C Receive register (I2C_RX - address 0x5000 C300) bit description Bit Symbol Description 7:0 RX Data Receive data. Reset Value - 13.8.11 I2C Transmit Register (I2C_TX - 0x5000 C300) This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep. The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored. I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0] are ignored for master-receive operations. The master-receiver must write a dummy byte to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is set or the START bit is set to cause a RESTART condition on a byte written to the TX FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is, the last byte of a master-receive operation is not acknowledged. Table 265. I2C Transmit register (I2C_TX - address 0x5000 C300) bit description Bit Symbol Description Reset Value 7:0 TX Data Transmit data. - 8 START When 1, issue a START condition before transmitting this byte. - 9 STOP When 1, issue a STOP condition after transmitting this byte. - 31:10 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 13.8.12 I2C Status Register (I2C_STS - 0x5000 C304) The I2C_STS register provides status information on the TX and RX blocks as well as the current state of the external buses. Individual bits are enabled as interrupts by the I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt. Table 266. I2C status register (I2C_STS - address 0x5000 C304) bit description Bit Symbol Value Description Reset Value 0 TDI Transaction Done Interrupt. This flag is set if a transaction 0 completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. 0 Transaction has not completed. 1 Transaction completed. 1 AFI Arbitration Failure Interrupt. When transmitting, if the SDA is low 0 when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. 0 No arbitration failure on last transmission. 1 Arbitration failure occurred on last transmission. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 291 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 266. I2C status register (I2C_STS - address 0x5000 C304) bit description …continued Bit Symbol Value Description Reset Value 2 NAI No Acknowledge Interrupt. After every byte of data is sent, the 0 transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. 0 Last transmission received an acknowledge. 1 Last transmission did not receive an acknowledge. 3 DRMI Master Data Request Interrupt. Once a transmission is started, 0 the transmitter must have data to transmit as long as it isn’t followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. 0 Master transmitter does not need data. 1 Master transmitter needs data. 4 DRSI Slave Data Request Interrupt. Once a transmission is started, 0 the transmitter must have data to transmit as long as it isn’t followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. 0 Slave transmitter does not need data. 1 Slave transmitter needs data. 5 Active Indicates whether the bus is busy. This bit is set when a START 0 condition has been seen. It is cleared when a STOP condition is seen.. 6 SCL The current value of the SCL signal. - 7 SDA The current value of the SDA signal. - 8 RFF Receive FIFO Full (RFF). This bit is set when the RX FIFO is full 0 and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. 0 RX FIFO is not full 1 RX FIFO is full 9 RFE Receive FIFO Empty. RFE is set when the RX FIFO is empty 1 and is cleared when the RX FIFO contains valid data. 0 RX FIFO contains data. 1 RX FIFO is empty 10 TFF Transmit FIFO Full. TFF is set when the TX FIFO is full and is 0 cleared when the TX FIFO is not full. 0 TX FIFO is not full. 1 TX FIFO is full UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 292 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 266. I2C status register (I2C_STS - address 0x5000 C304) bit description …continued Bit Symbol Value Description Reset Value 11 TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty 1 and is cleared when the TX FIFO contains valid data. 0 TX FIFO contains valid data. 1 TX FIFO is empty 31:12 - NA Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 13.8.13 I2C Control Register (I2C_CTL - 0x5000 C308) The I2C_CTL register is used to enable interrupts and reset the I2C state machine. Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set. Table 267. I2C Control register (I2C_CTL - address 0x5000 C308) bit description Bit Symbol Value Description 0 TDIE Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. Reset Value 0 0 Disable the TDI interrupt. 1 Enable the TDI interrupt. 1 AFIE Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is 0 asserted during transmission when trying to set SDA high, but the bus is driven low by another device. 0 Disable the AFI. 1 Enable the AFI. 2 NAIE Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling 0 that transmitted byte was not acknowledged. 0 Disable the NAI. 1 Enable the NAI. 3 DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which 0 signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. 0 Disable the DRMI interrupt. 1 Enable the DRMI interrupt. 4 DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which 0 signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. 0 Disable the DRSI interrupt. 1 Enable the DRSI interrupt. 5 REFIE Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to 0 indicate that the receive FIFO cannot accept any more data. 0 Disable the RFFI. 1 Enable the RFFI. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 293 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Table 267. I2C Control register (I2C_CTL - address 0x5000 C308) bit description …continued Bit Symbol Value Description Reset Value 6 RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that 0 data is available in the receive FIFO (i.e. not empty). 0 Disable the DAI. 1 Enable the DAI. 7 TFFIE Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt 0 to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. 0 Disable the TFFI. 1 Enable the TFFI. 8 SRST Soft reset. This is only needed in unusual circumstances. If a device issues a start 0 condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. 0 See the text. 1 Reset the I2C to idle state. Self clearing. 31:9 - NA Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 13.8.14 I2C Clock High Register (I2C_CLKHI - 0x5000 C30C) The CLK register holds a terminal count for counting 48 MHz clock cycles to create the high period of the slower I2C serial clock, SCL. Table 268. I2C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description Bit Symbol Description 7:0 CDHI Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. Reset Value 0xB9 13.8.15 I2C Clock Low Register (I2C_CLKLO - 0x5000 C310) The CLK register holds a terminal count for counting 48 MHz clock cycles to create the low period of the slower I2C serial clock, SCL. Table 269. I2C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description Bit Symbol Description 7:0 CDLO Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. Reset Value 0xB9 13.8.16 Interrupt handling The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 294 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit. For more details on the interrupts created by device controller, see the USB device chapter. For interrupts created by the host controllers, see the OHCI specification. The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB related interrupts to the NVIC controller (see Figure 39). Remark: During the HNP switching between host and device with the OTG stack active, an action may raise several levels of interrupts. It is advised to let the OTG stack initiate any actions based on interrupts and ignore device and host level interrupts. This means that during HNP switching, the OTG stack provides the communication to the host and device controllers. USB DEVICE INTERRUPTS USB HOST INTERRUPTS OTGIntSt TMR REMOVE_PU HNP_SUCCESS HNP_FAILURE USBIntSt USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA USB_HOST_INT USB_OTG_INT USB_I2C_INT USB_NEED_CLOCK USB I2C INTERRUPTS EN_USB_INTS Fig 39. USB OTG interrupt handling to NVIC 13.9 HNP support This section describes the hardware support for the Host Negotiation Protocol (HNP) provided by the OTG controller. When two dual-role OTG devices are connected to each other, the plug inserted into the mini-AB receptacle determines the default role of each device. The device with the mini-A plug inserted becomes the default Host (A-device), and the device with the mini-B plug inserted becomes the default Peripheral (B-device). Once connected, the default Host (A-device) and the default Peripheral (B-device) can switch Host and Peripheral roles using HNP. The context of the OTG controller operation is shown in Figure 40. Each controller (Host, Device, or OTG) communicates with its software stack through a set of status and control registers and interrupts. In addition, the OTG software stack communicates with the external OTG transceiver through the I2C interface and the external transceiver interrupt signal. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 295 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections. The USB state machines, the HNP switching, and the communications between the USB controllers are described in more detail in the following documentation: • USB OHCI specification • USB OTG supplement, version 1.2 • USB 2.0 specification • ISP1302 data sheet and user manual OHCI STACK OTG STACK HOST CONTROLLER OTG CONTROLLER MUX USB BUS DEVICE STACK DEVICE CONTROLLER I2C CONTROLLER ISP1302 Fig 40. USB OTG controller with software stack 13.9.1 B-device: peripheral to host switching In this case, the default role of the OTG controller is peripheral (B-device), and it switches roles from Peripheral to Host. The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP using a state machine diagram. The OTG software stack is responsible for implementing all of the states in the Dual-Role B-Device State Diagram. The OTG controller hardware provides support for the state transitions between the states b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device switching from peripheral to host. The hardware actions after setting this bit are shown in Figure 41. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 296 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG idle B_HNP_TRACK = 0 no B_HNP_TRACK = 1 ? no bus suspended ? disconnect device controller from U1 set REMOVE_PU set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED no PU_REMOVED set? yes PU_REMOVED set? bus reset/resume detected? yes no wait 25 s for bus to settle reconnect port U1 to the device controller reconnect port U1 to the device controller yes connect from A-device detected? no yes bus reset/resume detected? no set HNP_SUCCESS set PORT_FUNC[0] drive J on internal host controller port and SE0 on U1 SE0 sent by host? no yes connect U1 to host controller clear B_HNP_TRACK clear PU_REMOVED Fig 41. Hardware support for B-device switching from peripheral state to host state Figure 42 shows the actions that the OTG software stack should take in response to the hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The relationship of the software actions to the Dual-Role B-Device states is also shown. B-device states are in bold font with a circle around them. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 297 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK no REMOVE_PU set? yes remove D+ pull-up, set PU_REMOVED go to b_wait_acon go to b_peripheral yes HNP_FAILURE set? no no HNP_SUCCESS set? add D+ pull-up yes go to b_host Fig 42. State transitions implemented in software during B-device switching from peripheral to host Note that only the subset of B-device HNP states and state transitions supported by hardware are shown. Software is responsible for implementing all of the HNP states. Figure 42 may appear to imply that the interrupt bits such as REMOVE_PU should be polled, but this is not necessary if the corresponding interrupt is enabled. Following are code examples that show how the actions in Figure 42 are accomplished. The examples assume that ISP1302 is being used as the external OTG transceiver. Remove D+ pull-up /* Remove D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address OTG_I2C_TX = 0x201; // Clear DP_PULLUP bit, send STOP condition UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 298 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; 13.9.2 A-device: host to peripheral HNP switching In this case, the role of the OTG controller is host (A-device), and the A-device switches roles from host to peripheral. The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP using a state machine diagram. The OTG software stack is responsible for implementing all of the states in the Dual-Role A-Device State Diagram. The OTG controller hardware provides support for the state transitions between a_host, a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram. Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching the A-device from the host state to the device state. The hardware actions after setting this bit are shown in Figure 43. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 299 of 849 NXP Semiconductors idle A_HNP_TRACK = 0 no A_HNP_TRACK = 1 ? disconnect host controller from U1 UM10360 Chapter 13: LPC176x/5x USB OTG set HNP_FAILURE, clear A_HNP_TRACK no bus suspended ? yes resume detected ? yes no connnect host controller back to U1 yes bus reset detected? no yes resume detected? no no OTG timer expired? (TMR =1 ) yes clear A_HNP_TRACK set HNP_SUCCESS connect device to U1 by clearing PORT_FUNC[0] Fig 43. Hardware support for A-device switching from host state to peripheral state Figure 44 shows the actions that the OTG software stack should take in response to the hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The relationship of the software actions to the Dual-Role A-Device states is also shown. A-device states are shown in bold font with a circle around them. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 300 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend no TMR set? yes clear BDIS_ACON_EN bit in external OTG transceiver discharge VBUS go to a_wait_vfall no HNP_SUCCESS set? yes stop the OTG timer go to a_peripheral no HNP_FAILURE set? yes stop OTG timer clear BDIS_ACON_EN bit in external OTG transceiver go to a_host Fig 44. State transitions implemented in software during A-device switching from host to peripheral UM10360 User manual Note that only the subset of A-device HNP states and state transitions supported by hardware are shown. Software is responsible for implementing all of the HNP states. Figure 44 may appear to imply that the interrupt bits such as TMR should be polled, but this is not necessary if the corresponding interrupt is enabled. Following are code examples that show how the actions in Figure 44 are accomplished. The examples assume that ISP1302 is being used as the external OTG transceiver. Set BDIS_ACON_EN in external OTG transceiver All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 301 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210; // Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Clear BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x005; // Send Mode Control 1 (Clear) register address OTG_I2C_TX = 0x210; // Clear BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Discharge VBUS /* Clear the VBUS_DRV bit in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address OTG_I2C_TX = 0x220; // Clear VBUS_DRV bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; /* Set the VBUS_DISCHRG bit in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x240; // Set VBUS_DISCHRG bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 302 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) */ /* and monoshot mode (TMR_MODE = 0) */ /* Load the timeout value to implement the a_aidl_bdis_tmr timer */ /* the minimum value is 200 ms */ OTG_TIMER = 200; /* Enable the timer */ OTG_STAT_CTRL |= TMR_EN; Stop OTG timer /* Disable the timer – causes TMR_CNT to be reset to 0 */ OTG_STAT_CTRL &= ~TMR_EN; /* Clear TMR interrupt */ OTG_INT_CLR = TMR; Suspend host on port 1 /* Write to PortSuspendStatus bit to suspend host port 1 – */ /* this example demonstrates the low-level action software needs to take. */ /* The host stack code where this is done will be somewhat more involved. */ HC_RH_PORT_STAT1 = PSS; 13.10 Clocking and power management The OTG controller clocking is shown in Figure 45. A clock switch controls each clock with the exception of ahb_slave_clk. When the enable of the clock switch is asserted, its clock output is turned on and its CLK_ON output is asserted. The CLK_ON signals are observable in the OTGClkSt register. To conserve power, the clocks to the Device, Host, OTG, and I2C controllers can be disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl register. When the entire USB block is not in use, all of its clocks can be disabled by clearing the PCUSB bit in the PCONP register. When software wishes to access registers in one of the controllers, it should first ensure that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set. Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software. Accessing the register of a controller when its 48 MHz clock is not enabled will result in a data abort exception. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 303 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG cclk PCUSB USB CLOCK DIVIDER usbclk (48 MHz) ahb_slave_clk CLOCK SWITCH EN ahb_master_clk AHB_CLK_ON CLOCK SWITCH EN DEV_CLK_ON REGISTER INTERFACE ahb_need_clk AHB_CLK_EN DEVICE CONTROLLER dev_dma_need_clk dev_need_clk DEV_CLK_EN CLOCK SWITCH EN HOST_CLK_ON HOST CONTROLLER host_dma_need_clk host_need_clk HOST_CLK_EN CLOCK SWITCH EN OTG_CLK_ON OTG CONTROLLER OTG_CLK_EN USB_NEED_CLK CLOCK SWITCH EN I2C_CLK_ON I2C CONTROLLER I2C_CLK_EN Fig 45. Clocking and power control 13.10.1 Device clock request signals The Device controller has two clock request signals, dev_need_clk and dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and ahb_master_clk respectively. The dev_need_clk signal is asserted while the device is not in the suspend state, or if the device is in the suspend state and activity is detected on the USB bus. The dev_need_clk signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device Status register – Section 11.10.6). This signal allows DEV_CLK_EN to be cleared during normal operation when software does not need to access the Device controller registers – the Device will continue to function normally and automatically shut off its clock when it is suspended or disconnected. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 304 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation. 13.10.1.1 Host clock request signals The Host controller has two clock request signals, host_need_clk and host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and ahb_master_clk respectively. The host_need_clk signal is asserted while the Host controller functional state is not UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared during normal operation when software does not need to access the Host controller registers – the Host will continue to function normally and automatically shut off its clock when it goes into the UsbSuspend state. The host_dma_need_clk signal is asserted on any Host controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation. 13.10.2 Power-down mode support The LPC176x/5x can be configured to wake up from Power-down mode on any USB bus activity. When the chip is in Power-down mode and the USB interrupt is enabled, the assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode. Before Power-down mode can be entered when the USB activity interrupt is enabled, USB_NEED_CLK must be de-asserted. This is accomplished by clearing all of the CLK_EN bits in OTGClkCtrl and putting the Host controller into the UsbSuspend functional state. If it is necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to determine when they have all been de-asserted. 13.11 USB OTG controller initialization UM10360 User manual The LPC176x/5x OTG device controller initialization includes the following steps: 1. Enable the device controller by setting the PCUSB bit of PCONP. 2. Configure and enable the USB PLL (PLL1) or Main PLL (PLL0) to provide 48 MHz for usbclk and the desired frequency for cclk. For the procedure for determining the PLL setting and configuration, see Section 4.5.11 “Procedure for determining PLL0 settings” or Section 4.6.9 “Procedure for determining PLL1 settings”. 3. Enable the desired controller clocks by setting their respective CLK_EN bits in the USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register until they are set. 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 305 of 849 NXP Semiconductors UM10360 Chapter 13: LPC176x/5x USB OTG 5. Follow the appropriate steps in Section 11.13 “USB device controller initialization” to initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 306 of 849 UM10360 Chapter 14: LPC176x/5x UART0/2/3 Rev. 3.1 — 2 April 2014 User manual 14.1 Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_UART0; in the PCLKSEL1 register (Table 41), select PCLK_UART2/3. 3. Baud rate: In register U0/2/3LCR (Table 280), set bit DLAB =1. This enables access to registers DLL (Table 274) and DLM (Table 275) for setting the baud rate. Also, if needed, set the fractional baud rate in the fractional divider register (Table 286). 4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR (Table 279) to enable FIFO. 5. Pins: Select UART pins through the PINSEL registers and pin modes through the PINMODE registers (Section 8.5). Remark: UART receive pins should not have pull-down resistors enabled. 6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR (Table 280). This enables access to U0/2/3IER (Table 276). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA controller (see Table 544). 14.2 Features • Data sizes of 5, 6, 7, and 8 bits. • Parity generation and checking: odd, even mark, space or none. • One or two stop bits. • 16 byte Receive and Transmit FIFOs. • Built-in baud rate generator, including a fractional rate divider for great versatility. • Supports DMA for both transmit and receive. • Auto-baud capability • Break generation and detection. • Multiprocessor addressing mode. • IrDA mode to support infrared communication. • Support for software flow control. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 307 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 14.3 Pin description Table 270: UARTn Pin description Pin Type Description RXD0, RXD2, RXD3 Input Serial Input. Serial receive data. TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data. 14.4 Register description Each UART contains registers as shown in Table 271. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 308 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 271. UART0/2/3 Register Map Generic Name Description Access Reset UARTn Register value[1] Name & Address RBR (DLAB =0) Receiver Buffer Register. Contains the next received RO NA U0RBR - 0x4000 C000 character to be read. U2RBR - 0x4009 8000 U3RBR - 0x4009 C000 THR (DLAB =0) Transmit Holding Register. The next character to be WO NA transmitted is written here. U0THR - 0x4000 C000 U2THR - 0x4009 8000 U3THR - 0x4009 C000 DLL (DLAB =1) Divisor Latch LSB. Least significant byte of the baud R/W rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. 0x01 U0DLL - 0x4000 C000 U2DLL - 0x4009 8000 U3DLL - 0x4009 C000 DLM (DLAB =1) Divisor Latch MSB. Most significant byte of the baud R/W rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. 0x00 U0DLM - 0x4000 C004 U2DLM - 0x4009 8004 U3DLM - 0x4009 C004 IER (DLAB =0) Interrupt Enable Register. Contains individual interrupt R/W enable bits for the 7 potential UART interrupts. 0x00 U0IER - 0x4000 C004 U2IER - 0x4009 8004 U3IER - 0x4009 C004 IIR Interrupt ID Register. Identifies which interrupt(s) are RO 0x01 U0IIR - 0x4000 C008 pending. U2IIR - 0x4009 8008 U3IIR - 0x4009 C008 FCR FIFO Control Register. Controls UART FIFO usage and WO modes. 0x00 U0FCR - 0x4000 C008 U2FCR - 0x4009 8008 U3FCR - 0x4009 C008 LCR Line Control Register. Contains controls for frame formatting and break generation. R/W 0x00 U0LCR - 0x4000 C00C U2LCR - 0x4009 800C U3LCR - 0x4009 C00C LSR Line Status Register. Contains flags for transmit and RO 0x60 U0LSR - 0x4000 C014 receive status, including line errors. U2LSR - 0x4009 8014 U3LSR - 0x4009 C014 SCR Scratch Pad Register. 8-bit temporary storage for software. R/W 0x00 U0SCR - 0x4000 C01C U2SCR - 0x4009 801C U3SCR - 0x4009 C01C ACR Auto-baud Control Register. Contains controls for the R/W auto-baud feature. 0x00 U0ACR - 0x4000 C020 U2ACR - 0x4009 8020 U3ACR - 0x4009 C020 ICR IrDA Control Register. Enables and configures the R/W 0x00 U0ICR - 0x4000 C024 IrDA mode. U2ICR - 0x4009 8024 U3ICR - 0x4009 C024 FDR Fractional Divider Register. Generates a clock input for R/W the baud rate divider. 0x10 U0FDR - 0x4000 C028 U2FDR - 0x4009 8028 U3FDR - 0x4009 C028 TER Transmit Enable Register. Turns off UART transmitter R/W for use with software flow control. 0x80 U0TER - 0x4000 C030 U2TER - 0x4009 8030 U3TER - 0x4009 C030 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 309 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR. The UnRBR is always read-only. Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the UnRBR. Table 272: UARTn Receiver Buffer Register (U0RBR - address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR 04009 C000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 RBR The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx Undefined FIFO. 31:8 - Reserved, the value read from a reserved bit is not defined. NA 14.4.2 UARTn Transmit Holding Register (U0THR - 0x4000 C000, U2THR 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0) The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the UnTHR. The UnTHR is always write-only. Table 273: UARTn Transmit Holding Register (U0THR - address 0x4000 C000, U2THR - 0x4009 8000, U3THR 0x4009 C000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 THR Writing to the UARTn Transmit Holding Register causes the data to be stored in the NA UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. 31:8 - Reserved, user software should not write ones to reserved bits. NA 14.4.3 UARTn Divisor Latch LSB register (U0DLL - 0x4000 C000, U2DLL 0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL 0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1) The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce the baud rate clock, which must be 16 the desired baud rate. The UnDLL and UnDLM registers together form a 16-bit divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 310 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 select the right value for UnDLL and UnDLM can be found later in this chapter, see Section 14.4.12. Table 274: UARTn Divisor Latch LSB register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL 0x4009 C000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the 0x01 baud rate of the UARTn. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. Table 275: UARTn Divisor Latch MSB register (U0DLM - address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM 0x4009 C004 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the 0x00 baud rate of the UARTn. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 14.4.4 UARTn Interrupt Enable Register (U0IER - 0x4000 C004, U2IER 0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0) The UnIER is used to enable the three UARTn interrupt sources. Table 276: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER 0x4009 C004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value 0 RBR Interrupt Enable Enables the Receive Data Available interrupt for UARTn. It also controls 0 the Character Receive Time-out interrupt. 0 Disable the RDA interrupts. 1 Enable the RDA interrupts. 1 THRE Interrupt Enable Enables the THRE interrupt for UARTn. The status of this can be read 0 from UnLSR[5]. 0 Disable the THRE interrupts. 1 Enable the THRE interrupts. 2 RX Line Status Interrupt Enable Enables the UARTn RX line status interrupts. The status of this interrupt 0 can be read from UnLSR[4:1]. 0 Disable the RX line status interrupts. 1 Enable the RX line status interrupts. 7:3 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 8 ABEOIntEn Enables the end of auto-baud interrupt. 0 0 Disable end of auto-baud Interrupt. 1 Enable end of auto-baud Interrupt. 9 ABTOIntEn Enables the auto-baud time-out interrupt. 0 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt. 31:10 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 311 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 14.4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR 0x4009 8008, U3IIR - 0x4009 C008) The UnIIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during an UnIIR access, the interrupt is recorded for the next UnIIR access. Table 277: UARTn Interrupt Identification Register (U0IIR - address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR 0x4009 C008) bit description Bit Symbol Value Description Reset Value 0 IntStatus Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be 1 determined by evaluating UnIIR[3:1]. 0 At least one interrupt is pending. 1 No interrupt is pending. 3:1 IntId Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the 0 UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). 011 1 - Receive Line Status (RLS). 010 2a - Receive Data Available (RDA). 110 2b - Character Time-out Indicator (CTI). 001 3 - THRE Interrupt 5:4 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 7:6 FIFO Enable Copies of UnFCR[0]. 0 8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and 0 interrupt is enabled. 9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is 0 enabled. 31:10 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 278. Given the status of UnIIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTn Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error condition that set the interrupt can be observed via UnLSR[4:1]. The interrupt is cleared upon an UnLSR read. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 312 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. Table 278: UARTn Interrupt Handling U0IIR[3:0] Priority Interrupt value[1] Type Interrupt Source Interrupt Reset 0001 - None None - 0110 Highest RX Line OE[2] or PE[2] or FE[2] or BI[2] Status / Error UnLSR Read[2] 0100 Second RX Data Available Rx data available or trigger level reached in FIFO (UnFCR0=1) UnRBR Read[3] or UARTn FIFO drops below trigger level 1100 Second Character Time-out indication Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). UnRBR Read[3] The exact time will be: [(word length)  7 - 2]  8 + [(trigger level - number of characters)  8 + 1] RCLKs 0010 Third THRE THRE[2] UnIIR Read (if source of interrupt) or THR write[4] [1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved. [2] For details see Section 14.4.8 “UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR 0x4009 8014, U3LSR - 0x4009 C014)” [3] For details see Section 14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)” [4] For details see Section 14.4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR 0x4009 8008, U3IIR - 0x4009 C008)” and Section 14.4.2 “UARTn Transmit Holding Register (U0THR 0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)” The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated when the UARTn THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UARTn THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 313 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 immediately if the UARTn THR FIFO has held two or more characters at one time and currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001). 14.4.6 UARTn FIFO Control Register (U0FCR - 0x4000 C008, U2FCR 0x4009 8008, U3FCR - 0x4009 C008) The write-only UnFCR controls the operation of the UARTn Rx and TX FIFOs. Table 279: UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR 0x4007 C008) bit description Bit Symbol Value Description Reset Value 0 FIFO Enable 0 UARTn FIFOs are disabled. Must not be used in the application. 0 1 Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. 1 RX FIFO 0 Reset 1 No impact on either of UARTn FIFOs. 0 Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. 2 TX FIFO 0 Reset 1 No impact on either of UARTn FIFOs. 0 Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. 3 DMA Mode Select When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA 0 mode. See Section 14.4.6.1. 5:4 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 7:6 RX Trigger Level These two bits determine how many receiver UARTn FIFO characters must be 0 written before an interrupt or DMA request is activated. 00 Trigger level 0 (1 character or 0x01) 01 Trigger level 1 (4 characters or 0x04) 10 Trigger level 2 (8 characters or 0x08) 11 Trigger level 3 (14 characters or 0x0E) 31:8 - Reserved, user software should not write ones to reserved bits. NA 14.4.6.1 DMA Operation The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register. UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character time-out occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 314 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller. 14.4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR 0x4009 800C, U3LCR - 0x4009 C00C) The UnLCR determines the format of the data character that is to be transmitted or received. Table 280: UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR 0x4009 C00C) bit description Bit Symbol Value Description Reset Value 1:0 Word Length Select 00 5-bit character length 0 01 6-bit character length 10 7-bit character length 11 8-bit character length 2 Stop Bit Select 0 1 stop bit. 0 1 2 stop bits (1.5 if UnLCR[1:0]=00). 3 Parity Enable 0 Disable parity generation and checking. 0 1 Enable parity generation and checking. 5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached 0 parity bit will be odd. 01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 10 Forced "1" stick parity. 11 Forced "0" stick parity. 6 Break Control 0 Disable break transmission. 0 1 Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. 7 Divisor Latch 0 Disable access to Divisor Latches. 0 Access Bit (DLAB) 1 Enable access to Divisor Latches. 31:8 - Reserved, user software should not write ones to reserved bits. The NA value read from a reserved bit is not defined. 14.4.8 UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR 0x4009 8014, U3LSR - 0x4009 C014) The UnLSR is a read-only register that provides status information on the UARTn TX and RX blocks. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 315 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 281: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Bit Symbol Value Description Reset Value 0 Receiver Data Ready (RDR) UnLSR0 is set when the UnRBR holds an unread character and is cleared when 0 the UARTn RBR FIFO is empty. 0 The UARTn receiver FIFO is empty. 1 The UARTn receiver FIFO is not empty. 1 Overrun Error (OE) The overrun error condition is set as soon as it occurs. An UnLSR read clears 0 UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. 0 Overrun error status is inactive. 1 Overrun error status is active. 2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error 0 occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. 0 Parity error status is inactive. 1 Parity error status is active. 3 Framing Error (FE) When the stop bit of a received character is a logic 0, a framing error occurs. An 0 UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. 0 Framing error status is inactive. 1 Framing error status is active. 4 Break Interrupt (BI) When RXDn is held in the spacing state (all zeroes) for one full character 0 transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. 0 Break interrupt status is inactive. 1 Break interrupt status is active. 5 Transmitter THRE is set immediately upon detection of an empty UARTn THR and is cleared 1 Holding Register on a UnTHR write. Empty (THRE)) 0 UnTHR contains valid data. 1 UnTHR is empty. 6 Transmitter Empty (TEMT) TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when 1 either the UnTSR or the UnTHR contain valid data. 0 UnTHR and/or the UnTSR contains valid data. 1 UnTHR and the UnTSR are empty. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 316 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 281: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description …continued Bit Symbol Value Description Reset Value 7 Error in RX FIFO (RXFE) UnLSR[7] is set when a character with a Rx error such as framing error, parity 0 error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. 0 UnRBR contains no UARTn RX errors or UnFCR[0]=0. 1 UARTn RBR contains at least one UARTn RX error. 31:8 - Reserved, the value read from a reserved bit is not defined. NA 14.4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR 0x4009 801C U3SCR - 0x4009 C01C) The UnSCR has no effect on the UARTn operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the UnSCR has occurred. Table 282: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR 0x4009 C01C) bit description Bit Symbol Description Reset Value 7:0 Pad A readable, writable byte. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 14.4.10 UARTn Auto-baud Control Register (U0ACR - 0x4000 C020, U2ACR 0x4009 8020, U3ACR - 0x4009 C020) The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. Table 283: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR 0x4009 C020) bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto-baud completion. 0 0 Auto-baud stop (auto-baud is not running). 1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 Mode Auto-baud mode select bit. 0 0 Mode 0. 1 Mode 1. 2 AutoRestart 0 No restart. 0 1 Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 0 7:3 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 317 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 283: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR 0x4009 C020) bit description …continued Bit Symbol Value Description Reset value 8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will 0 clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. 9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will 0 clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. 31:10 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 14.4.10.1 Auto-baud The UARTn auto-baud function can be used to measure the incoming baud-rate based on the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers UnDLM and UnDLL accordingly. Remark: the fractional rate divider is not connected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the UnACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UARTn Rx pin (the length of the start bit). The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UARTn Rx pin. The auto-baud function can generate two interrupts. • The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn is set and the auto-baud rate measurement counter overflows). • The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn is set and the auto-baud has completed successfully). The auto-baud interrupts have to be cleared by setting the corresponding UnACR ABTOIntClr and ABEOIntEn bits. Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UARTn Rx pin baud-rate, but the value of the UnFDR register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to UnDLM and UnDLL registers should be done before UnACR register write. The minimum and the maximum baud rates supported by UARTn are function of pclk, number of data bits, stop bits and parity bits. ratemin = 2----------P----C----L----K-16  215  U ART nb a ud ra t e  -----------------------------------------------P----C----L----K-----------------------------------------------16  2 + databits + paritybits + stopbits = ratemax(3) UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 318 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 14.4.10.2 Auto-baud modes When the software is expecting an “AT” command, it configures the UARTn with the expected character format and sets the UnACR Start bit. The initial values in the divisor latches UnDLM and UnDLM don‘t care. Because of the “A” or “a” ASCII coding (”A" = 0x41, “a” = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the UnACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On UnACR Start bit setting, the baud rate measurement counter is reset and the UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate. 2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UARTn input clock, guaranteeing the start bit is stored in the UnRSR. 4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UARTn input clock (pclk). 5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin. 6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched to normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the remaining bits of the “A/a” character. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 319 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 UARTn RX 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop start bit LSB of 'A' or 'a' UnACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) UARTn RX 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop start bit LSB of 'A' or 'a' UnACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 46. Auto-baud a) mode 0 and b) mode 1 waveform 14.4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) The IrDA Control Register enables and configures the IrDA mode on each UART. The value of UnICR should not be changed while transmitting or receiving data, or data loss or corruption may occur. Table 284: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description Bit Symbol Value Description Reset value 0 IrDAEn 0 IrDA mode on UARTn is disabled, UARTn acts as a standard UART. 0 1 IrDA mode on UARTn is enabled. 1 IrDAInv When 1, the serial input is inverted. This has no effect on the serial output. 0 When 0, the serial input is not inverted. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 320 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 284: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description …continued Bit Symbol Value Description Reset value 2 FixPulseEn When 1, enabled IrDA fixed pulse width mode. 0 5:3 PulseDiv Configures the pulse when FixPulseEn = 1. See text below for details. 0 31:6 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits should be set so that the resulting pulse width is at least 1.63 µs. Table 285 shows the possible pulse widths. Table 285: IrDA Pulse Width FixPulseEn PulseDiv 0 x 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 IrDA Transmitter Pulse width (µs) 3 / (16  baud rate) 2  TPCLK 4  TPCLK 8  TPCLK 16  TPCLK 32  TPCLK 64  TPCLK 128  TPCLK 256  TPCLK 14.4.12 UARTn Fractional Divider Register (U0FDR - 0x4000 C028, U2FDR 0x4009 8028, U3FDR - 0x4009 C028) The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be greater than 2. Table 286: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR 0x4009 C028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional 0 baud-rate generator will not impact the UARTn baudrate. 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for 1 UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. 31:8 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 321 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0/2/3 disabled making sure that UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this feature. UART0/2/3 baud rate can be calculated as (n = 0/2/3): UARTnbaudrate = ----------------------------------------------------------P----C----L----K-----------------------------------------------------------16  256  UnDLM + UnDLL  1 + D-----iM--v---A-u---ld--V--d--a-V---l-a---l (4) Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1  MULVAL  15 2. 0  DIVADDVAL  14 3. DIVADDVAL < MULVAL The value of the U0/2/3FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U0/2/3FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. 14.4.12.1 Baud rate calculation UARTn can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 322 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DLest is an integer? False FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) True DIVADDVAL = 0 MULVAL = 1 False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DLest [15:8] DLL = DLest [7:0] End Fig 47. Algorithm for setting UART dividers UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 323 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 287. Fractional Divider setting look-up table FR DivAddVal/ FR DivAddVal/ FR MulVal MulVal 1.000 0/1 1.250 1/4 1.500 1.067 1/15 1.267 4/15 1.533 1.071 1/14 1.273 3/11 1.538 1.077 1/13 1.286 2/7 1.545 1.083 1/12 1.300 3/10 1.556 1.091 1/11 1.308 4/13 1.571 1.100 1/10 1.333 1/3 1.583 1.111 1/9 1.357 5/14 1.600 1.125 1/8 1.364 4/11 1.615 1.133 2/15 1.375 3/8 1.625 1.143 1/7 1.385 5/13 1.636 1.154 2/13 1.400 2/5 1.643 1.167 1/6 1.417 5/12 1.667 1.182 2/11 1.429 3/7 1.692 1.200 1/5 1.444 4/9 1.700 1.214 3/14 1.455 5/11 1.714 1.222 2/9 1.462 6/13 1.727 1.231 3/13 1.467 7/15 1.733 DivAddVal/ MulVal 1/2 8/15 7/13 6/11 5/9 4/7 7/12 3/5 8/13 5/8 7/11 9/14 2/3 9/13 7/10 5/7 8/11 11/15 FR 1.750 1.769 1.778 1.786 1.800 1.818 1.833 1.846 1.857 1.867 1.875 1.889 1.900 1.909 1.917 1.923 1.929 1.933 DivAddVal/ MulVal 3/4 10/13 7/9 11/14 4/5 9/11 5/6 11/13 6/7 13/15 7/8 8/9 9/10 10/11 11/12 12/13 13/14 14/15 14.4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96. 14.4.12.1.2 Example 2: PCLK = 12 MHz, BR = 115200 According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table. The closest value for FRest = 1.628 in the look-up Table 287 is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8. According to Equation 4 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200. 14.4.13 UARTn Transmit Enable Register (U0TER - 0x4000 C030, U2TER 0x4009 8030, U3TER - 0x4009 C030) The UnTER register enables implementation of software flow control. When TXEn=1, UARTn transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UARTn transmission will stop. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 324 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Table 288 describes how to use TXEn bit in order to achieve software flow control. Table 288: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER 0x4009 C030) bit description Bit Symbol Description Reset Value 6:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as 1 soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. 14.5 Architecture The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART. The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input. The UARTn RX Shift Register (UnRSR) accepts valid characters via RXDn. After a valid character is assembled in the UnRSR, it is passed to the UARTn RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register (UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via the serial output pin, TXDn. The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by the UARTn TX block. The UnBRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the UnDLL and UnDLM registers. This divided down clock is the 16x oversample clock. The interrupt interface contains registers UnIER and UnIIR. The interrupt interface receives several one clock wide enables from the UnTX and UnRX blocks. Status information from the UnTX and UnRX is stored in the UnLSR. Control information for the UnTX and UnRX is stored in the UnLCR. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 325 of 849 NXP Semiconductors UM10360 Chapter 14: LPC176x/5x UART0/2/3 Transmitter Holding Register TX_DMA_REQ TX_DMA_CLR Transmitter Transmitter FIFO Transmitter DMA Interface Transmitter Shift Register Un_TXD PCLK Baud Rate Generator Fractional Rate Divider Main Divider (DLM, DLL) Interrupt UARTn interrupt Control & Status FIFO Control & Status Line Control & Status IrDA, & Autobaud Receiver Buffer Register RX_DMA_REQ RX_DMA_CLR Receiver Receiver FIFO Receiver DMA Interface Receiver Shift Register Un_OE Un_RXD Fig 48. UART0, 2 and 3 block diagram UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 326 of 849 UM10360 Chapter 15: LPC176x/5x UART1 Rev. 3.1 — 2 April 2014 User manual 15.1 Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_UART1. 3. Baud rate: In register U1LCR (Table 299), set bit DLAB =1. This enables access to registers DLL (Table 293) and DLM (Table 294) for setting the baud rate. Also, if needed, set the fractional baud rate in the fractional divider register (Table 306). 4. UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR (Table 298) to enable FIFO. 5. Pins: Select UART pins through PINSEL registers and pin modes through the PINMODE registers (Section 8.5). Remark: UART receive pins should not have pull-down resistors enabled. 6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR (Table 299). This enables access to U1IER (Table 295). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller (see Table 544). 15.2 Features • Full modem control handshaking available • Data sizes of 5, 6, 7, and 8 bits. • Parity generation and checking: odd, even mark, space or none. • One or two stop bits. • 16 byte Receive and Transmit FIFOs. • Built-in baud rate generator, including a fractional rate divider for great versatility. • Supports DMA for both transmit and receive. • Auto-baud capability • Break generation and detection. • Multiprocessor addressing mode. • RS-485 support. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 327 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 15.3 Pin description Table 289: UART1 Pin Description Pin Type Description RXD1 Input Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR) indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt is enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTS1 is also used in the auto-cts mode to control the transmitter. DCD1 Input Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). DSR1 Input Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR[0]. The DTR pin can also be used as an RS-485/EIA-485 output enable signal. RI1 Input Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). RTS1 Output Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR[1]. In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic. Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready to receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO threshold logic. The RTS pin can also be used as an RS-485/EIA-485 output enable signal. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 328 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 15.4 Register description UART1 contains registers organized as shown in Table 290. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. Table 290: UART1 register map Name Description Access Reset Address Value[1] U1RBR Receiver Buffer Register. Contains the next received character to RO NA 0x4001 0000 (when DLAB =0) be read. (when DLAB=0) U1THR Transmit Holding Register. The next character to be transmitted is WO NA (when DLAB =0) written here. 0x4001 0000 (when DLAB=0) U1DLL Divisor Latch LSB. Least significant byte of the baud rate divisor R/W 0x01 0x4001 0000 (when DLAB =1) value. The full divisor is used to generate a baud rate from the fractional rate divider. (when DLAB=1) U1DLM Divisor Latch MSB. Most significant byte of the baud rate divisor R/W 0x00 0x4001 0004 (when DLAB =1) value. The full divisor is used to generate a baud rate from the fractional rate divider. (when DLAB=1) U1IER Interrupt Enable Register. Contains individual interrupt enable bits R/W (when DLAB =0) for the 7 potential UART1 interrupts. 0x00 0x4001 0004 (when DLAB=0) U1IIR Interrupt ID Register. Identifies which interrupt(s) are pending. RO 0x01 0x4001 0008 U1FCR FIFO Control Register. Controls UART1 FIFO usage and modes. WO 0x00 0x4001 0008 U1LCR Line Control Register. Contains controls for frame formatting and R/W break generation. 0x00 0x4001 000C U1MCR Modem Control Register. Contains controls for flow control handshaking and loopback mode. R/W 0x00 0x4001 0010 U1LSR Line Status Register. Contains flags for transmit and receive status, RO including line errors. 0x60 0x4001 0014 U1MSR Modem Status Register. Contains handshake signal status flags. RO 0x00 0x4001 0018 U1SCR Scratch Pad Register. 8-bit temporary storage for software. R/W 0x00 0x4001 001C U1ACR Auto-baud Control Register. Contains controls for the auto-baud R/W 0x00 0x4001 0020 feature. U1FDR Fractional Divider Register. Generates a clock input for the baud R/W rate divider. 0x10 0x4001 0028 U1TER Transmit Enable Register. Turns off UART transmitter for use with R/W software flow control. 0x80 0x4001 0030 U1RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various R/W 0x00 0x4001 004C aspects of RS-485/EIA-485 modes. U1ADRMATCH RS-485/EIA-485 address match. Contains the address match value R/W for RS-485/EIA-485 mode. 0x00 0x4001 0050 U1RS485DLY RS-485/EIA-485 direction control delay. R/W 0x00 0x4001 0054 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 329 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 15.4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1RBR. The U1RBR is always read-only. Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U1LSR register, and then to read a byte from the U1RBR. Table 291: UART1 Receiver Buffer Register (U1RBR - address 0x4001 0000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 RBR The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX undefined FIFO. 31:8 - Reserved, the value read from a reserved bit is not defined. NA 15.4.2 UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0) The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1THR. The U1THR is write-only. Table 292: UART1 Transmitter Holding Register (U1THR - address 0x4001 0000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 THR Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 NA transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. 31:8 - Reserved, user software should not write ones to reserved bits. NA 15.4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000 and U1DLM - 0x4001 0004, when DLAB = 1) The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later in this chapter, see Section 15.4.16. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 330 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 293: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. 0x01 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. Table 294: UART1 Divisor Latch MSB Register (U1DLM - address 0x4001 0004 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.4 UART1 Interrupt Enable Register (U1IER - 0x4001 0004, when DLAB = 0) The U1IER is used to enable the four UART1 interrupt sources. Table 295: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value 0 RBR Interrupt Enable enables the Receive Data Available interrupt for UART1. It also controls the Character 0 Receive Time-out interrupt. 0 Disable the RDA interrupts. 1 Enable the RDA interrupts. 1 THRE Interrupt Enable enables the THRE interrupt for UART1. The status of this interrupt can be read from 0 U1LSR[5]. 0 Disable the THRE interrupts. 1 Enable the THRE interrupts. 2 RX Line Interrupt Enable enables the UART1 RX line status interrupts. The status of this interrupt can be read 0 from U1LSR[4:1]. 0 Disable the RX line status interrupts. 1 Enable the RX line status interrupts. 3 Modem Status Interrupt Enable enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. 0 0 Disable the modem interrupt. 1 Enable the modem interrupt. 6:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 7 CTS Interrupt Enable If auto-cts mode is enabled this bit enables/disables the modem status interrupt 0 generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER[3] and U1IER[7] bits are set. 0 Disable the CTS interrupt. 1 Enable the CTS interrupt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 331 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 295: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description …continued Bit Symbol Value Description Reset Value 8 ABEOIntEn Enables the end of auto-baud interrupt. 0 0 Disable end of auto-baud Interrupt. 1 Enable end of auto-baud Interrupt. 9 ABTOIntEn Enables the auto-baud time-out interrupt. 0 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.5 UART1 Interrupt Identification Register (U1IIR - 0x4001 0008) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access. Table 296: UART1 Interrupt Identification Register (U1IIR - address 0x4001 0008) bit description Bit Symbol Value Description Reset Value 0 IntStatus Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be 1 determined by evaluating U1IIR[3:1]. 0 At least one interrupt is pending. 1 No interrupt is pending. 3:1 IntId Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the UART1 0 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below are reserved (100,101,111). 011 1 - Receive Line Status (RLS). 010 2a - Receive Data Available (RDA). 110 2b - Character Time-out Indicator (CTI). 001 3 - THRE Interrupt. 000 4 - Modem Interrupt. 5:4 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 7:6 FIFO Enable Copies of U1FCR[0]. 0 8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is 0 enabled. 9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. 0 31:10 - Reserved, the value read from a reserved bit is not defined. NA Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 297. Given the status of U1IIR[3:0], an UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 332 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared upon an U1LSR read. The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. Table 297: UART1 Interrupt Handling U1IIR[3:0] Priority Interrupt Interrupt Source value[1] Type Interrupt Reset 0001 - None None - 0110 Highest RX Line Status / Error OE[2] or PE[2] or FE[2] or BI[2] U1LSR Read[2] 0100 Second RX Data Rx data available or trigger level reached in FIFO Available (U1FCR0=1) U1RBR Read[3] or UART1 FIFO drops below trigger level 1100 Second Character Time-out indication Minimum of one character in the RX FIFO and no character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). U1RBR Read[3] The exact time will be: [(word length)  7 - 2]  8 + [(trigger level - number of characters)  8 + 1] RCLKs 0010 Third THRE THRE[2] U1IIR Read[4] (if source of interrupt) or THR write 0000 Fourth Modem CTS or DSR or RI or DCD Status MSR Read [1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved. [2] For details see Section 15.4.10 “UART1 Line Status Register (U1LSR - 0x4001 0014)” [3] For details see Section 15.4.1 “UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)” [4] For details see Section 15.4.5 “UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)” and Section 15.4.2 “UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)” UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 333 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the U1THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U1THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001). It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 15.4.6 UART1 FIFO Control Register (U1FCR - 0x4001 0008) The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs. Table 298: UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description Bit Symbol Value Description Reset Value 0 FIFO Enable 0 UART1 FIFOs are disabled. Must not be used in the application. 0 1 Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. 1 RX FIFO 0 No impact on either of UART1 FIFOs. 0 Reset 1 Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. 2 TX FIFO 0 No impact on either of UART1 FIFOs. 0 Reset 1 Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. 3 DMA Mode Select When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA 0 mode. See Section 15.4.6.1. 5:4 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 7:6 RX Trigger Level These two bits determine how many receiver UART1 FIFO characters must be 0 written before an interrupt is activated. 00 Trigger level 0 (1 character or 0x01). 01 Trigger level 1 (4 characters or 0x04). 10 Trigger level 2 (8 characters or 0x08). 11 Trigger level 3 (14 characters or 0x0E). 31:8 - Reserved, user software should not write ones to reserved bits. NA 15.4.6.1 DMA Operation The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 334 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character time-out occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller. 15.4.7 UART1 Line Control Register (U1LCR - 0x4001 000C) The U1LCR determines the format of the data character that is to be transmitted or received. Table 299: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description Bit Symbol Value Description Reset Value 1:0 Word Length 00 5-bit character length. 0 Select 01 6-bit character length. 10 7-bit character length. 11 8-bit character length. 2 Stop Bit Select 0 1 stop bit. 0 1 2 stop bits (1.5 if U1LCR[1:0]=00). 3 Parity Enable 0 Disable parity generation and checking. 0 1 Enable parity generation and checking. 5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached 0 parity bit will be odd. 01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 10 Forced "1" stick parity. 11 Forced "0" stick parity. 6 Break Control 0 Disable break transmission. 0 1 Enable break transmission. Output pin UART1 TXD is forced to logic 0 when U1LCR[6] is active high. 7 Divisor Latch 0 Disable access to Divisor Latches. 0 Access Bit (DLAB) 1 Enable access to Divisor Latches. 31:8 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 15.4.8 UART1 Modem Control Register (U1MCR - 0x4001 0010) The U1MCR enables the modem loopback mode and controls the modem output signals. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 335 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 300: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description Bit Symbol Value Description Reset value 0 DTR Control Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode 0 is active. 1 RTS Control Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is 0 active. 3-2 - NA Reserved, user software should not write ones to reserved bits. The value read from a 0 reserved bit is not defined. 4 Loopback Mode Select The modem loopback mode provides a mechanism to perform diagnostic loopback 0 testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the U1MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR. 0 Disable modem loopback mode. 1 Enable modem loopback mode. 5 - NA Reserved, user software should not write ones to reserved bits. The value read from a 0 reserved bit is not defined. 6 RTSen 0 Disable auto-rts flow control. 0 1 Enable auto-rts flow control. 7 CTSen 0 Disable auto-cts flow control. 0 1 Enable auto-cts flow control. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.9 Auto-flow control If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1 output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted. 15.4.9.1 Auto-RTS The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control originates in the U1RBR module and is linked to the programmed receiver FIFO trigger level. If auto-RTS is enabled, the data-flow is controlled as follows: When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted (to a high value). It is possible that the sending UART sends an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it might not recognize the de-assertion of RTS1 until after it has begun sending the additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO has reached the previous trigger level. The re-assertion of RTS1 signals to the sending UART to continue transmitting data. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 336 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software. Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to 0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the receive FIFO contains 8 bytes (Table 298 on page 334). The RTS1 output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes. ~~ ~~ UART1 Rx start byte N stop start bits0..7 stop start bits0..7 stop ~~ ~~ ~~ RTS1 pin UART1 Rx FIFO read UART1 Rx N-1 N N-1 N-2 N-1 N-2 M+2 M+1 M M-1 FIFO level Fig 49. Auto-RTS Functional Timing 15.4.9.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta CTS bit in the U1MSR will be set though. Table 301 lists the conditions for generating a Modem Status interrupt. Table 301: Modem status interrupt generation Enable Modem Status CTSen CTS Interrupt Delta CTS Delta DCD or Trailing Edge RI Modem Status Interrupt (U1ER[3]) (U1MCR[7]) Enable (U1IER[7]) (U1MSR[0]) or Delta DSR (U1MSR[3] or Interrupt U1MSR[2] or U1MSR[1]) 0 x x x x No 1 0 x 0 0 No 1 0 x 1 x Yes 1 0 x x 1 Yes 1 1 0 x 0 No 1 1 0 x 1 Yes 1 1 1 0 0 No 1 1 1 1 x Yes 1 1 1 x 1 Yes The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS1 state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 337 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 data present in the transmit FIFO and a receiver overrun error can result. Figure 50 illustrates the Auto-CTS functional timing. ~~ ~~ UART1 TX start bits0..7 stop ~~ start bits0..7 stop start bits0..7 stop ~~ CTS1 pin Fig 50. Auto-CTS Functional Timing While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets de-asserted transmission resumes and a start bit is sent followed by the data bits of the next character. 15.4.10 UART1 Line Status Register (U1LSR - 0x4001 0014) The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks. Table 302: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description Bit Symbol Value Description Reset Value 0 Receiver Data Ready (RDR) U1LSR[0] is set when the U1RBR holds an unread character and is cleared when 0 the UART1 RBR FIFO is empty. 0 The UART1 receiver FIFO is empty. 1 The UART1 receiver FIFO is not empty. 1 Overrun Error (OE) The overrun error condition is set as soon as it occurs. An U1LSR read clears 0 U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. 0 Overrun error status is inactive. 1 Overrun error status is active. 2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error 0 occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is dependent on U1FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. 0 Parity error status is inactive. 1 Parity error status is active. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 338 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 302: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description …continued Bit Symbol Value Description Reset Value 3 Framing Error (FE) When the stop bit of a received character is a logic 0, a framing error occurs. An 0 U1LSR read clears U1LSR[3]. The time of the framing error detection is dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. 0 Framing error status is inactive. 1 Framing error status is active. 4 Break Interrupt (BI) When RXD1 is held in the spacing state (all zeroes) for one full character 0 transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An U1LSR read clears this status bit. The time of break detection is dependent on U1FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. 0 Break interrupt status is inactive. 1 Break interrupt status is active. 5 Transmitter THRE is set immediately upon detection of an empty UART1 THR and is cleared 1 Holding Register on a U1THR write. Empty (THRE) 0 U1THR contains valid data. 1 U1THR is empty. 6 Transmitter Empty (TEMT) TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when 1 either the U1TSR or the U1THR contain valid data. 0 U1THR and/or the U1TSR contains valid data. 1 U1THR and the U1TSR are empty. 7 Error in RX FIFO (RXFE) U1LSR[7] is set when a character with a RX error such as framing error, parity 0 error or break interrupt, is loaded into the U1RBR. This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO. 0 U1RBR contains no UART1 RX errors or U1FCR[0]=0. 1 UART1 RBR contains at least one UART1 RX error. 31:8 - Reserved, the value read from a reserved bit is not defined. NA 15.4.11 UART1 Modem Status Register (U1MSR - 0x4001 0018) The U1MSR is a read-only register that provides status information on the modem input signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct effect on UART1 operation, they facilitate software implementation of modem signal operations. Table 303: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Bit Symbol Value Description 0 Delta CTS Set upon state change of input CTS. Cleared on an U1MSR read. 0 No change detected on modem input, CTS. 1 State change detected on modem input, CTS. Reset Value 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 339 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 303: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Bit Symbol Value Description Reset Value 1 Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. 0 0 No change detected on modem input, DSR. 1 State change detected on modem input, DSR. 2 Trailing Edge RI Set upon low to high transition of input RI. Cleared on an U1MSR read. 0 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI. 3 Delta DCD Set upon state change of input DCD. Cleared on an U1MSR read. 0 0 No change detected on modem input, DCD. 1 State change detected on modem input, DCD. 4 CTS Clear To Send State. Complement of input signal CTS. This bit is 0 connected to U1MCR[1] in modem loopback mode. 5 DSR Data Set Ready State. Complement of input signal DSR. This bit is 0 connected to U1MCR[0] in modem loopback mode. 6 RI Ring Indicator State. Complement of input RI. This bit is connected to 0 U1MCR[2] in modem loopback mode. 7 DCD Data Carrier Detect State. Complement of input DCD. This bit is connected 0 to U1MCR[3] in modem loopback mode. 31:8 - Reserved, the value read from a reserved bit is not defined. NA 15.4.12 UART1 Scratch Pad Register (U1SCR - 0x4001 001C) The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred. Table 304: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description Bit Symbol Description 7:0 Pad A readable, writable byte. Reset Value 0x00 15.4.13 UART1 Auto-baud Control Register (U1ACR - 0x4001 0020) The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. Table 305: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description Bit Symbol Value Description 0 Start This bit is automatically cleared after auto-baud completion. 0 Auto-baud stop (auto-baud is not running). 1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 Mode Auto-baud mode select bit. 0 Mode 0. 1 Mode 1. Reset value 0 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 340 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 305: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description …continued Bit Symbol Value Description Reset value 2 AutoRestart 0 No restart 0 1 Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 0 7:3 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. 8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). 0 0 Writing a 0 has no impact. 1 Writing a 1 will clear the corresponding interrupt in the U1IIR. 9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). 0 0 Writing a 0 has no impact. 1 Writing a 1 will clear the corresponding interrupt in the U1IIR. 31:10 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. 15.4.14 Auto-baud The UART1 auto-baud function can be used to measure the incoming baud-rate based on the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U1DLM and U1DLL accordingly. Remark: the fractional rate divider is not connected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the U1ACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UART1 Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART1 Rx pin (the length of the start bit). The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin. The auto-baud function can generate two interrupts. • The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn is set and the auto-baud rate measurement counter overflows). • The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn is set and the auto-baud has completed successfully). The auto-baud interrupts have to be cleared by setting the corresponding U1ACR ABTOIntClr and ABEOIntEn bits. UM10360 User manual Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 341 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U1DLM and U1DLL registers should be done before U1ACR register write. The minimum and the maximum baud rates supported by UART1 are function of pclk, number of data bits, stop bits and parity bits. ratemin = 2----------P----C----L----K-16  215  U ART 1b a ud ra t e  1----6-----------2-----+-----d---a---t--a----b---i--t--s---P-+---C--p--L-a---K-r--i--t--y---b----i--t--s----+-----s--t--o----p---b---i--t--s--- = ratemax(5) 15.4.15 Auto-baud modes When the software is expecting an “AT” command, it configures the UART1 with the expected character format and sets the U1ACR Start bit. The initial values in the divisor latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding (”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the U1ACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate. 2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UART1 input clock, guaranteeing the start bit is stored in the U1RSR. 4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UART1 input clock (pclk). 5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin. 6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the “A/a” character. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 342 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 UARTn RX 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) 16 cycles 'A' (0x41) or 'a' (0x61) UARTn RX start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop start bit LSB of 'A' or 'a' U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 51. Auto-baud a) mode 0 and b) mode 1 waveform 15.4.16 UART1 Fractional Divider Register (U1FDR - 0x4001 0028) The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be greater than 2. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 343 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 306: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional 0 baud-rate generator will not impact the UARTn baudrate. 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for 1 UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. 31:8 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature. UART1 baud rate can be calculated as (n = 1): UART1baudrate = ----------------------------------------------------------P----C----L----K-----------------------------------------------------------16  256  U1DLM + U1DLL  1 + D-----iM--v---A-u---ld--V--d--a-V---l-a---l (6) Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1  MULVAL  15 2. 0  DIVADDVAL  14 3. DIVADDVAL < MULVAL The value of the U1FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U1FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. 15.4.16.1 Baud rate calculation UART1 can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 344 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DLest is an integer? False FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) True DIVADDVAL = 0 MULVAL = 1 False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DLest [15:8] DLL = DLest [7:0] End Fig 52. Algorithm for setting UART dividers UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 345 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 307. Fractional Divider setting look-up table FR DivAddVal/ FR DivAddVal/ FR MulVal MulVal 1.000 0/1 1.250 1/4 1.500 1.067 1/15 1.267 4/15 1.533 1.071 1/14 1.273 3/11 1.538 1.077 1/13 1.286 2/7 1.545 1.083 1/12 1.300 3/10 1.556 1.091 1/11 1.308 4/13 1.571 1.100 1/10 1.333 1/3 1.583 1.111 1/9 1.357 5/14 1.600 1.125 1/8 1.364 4/11 1.615 1.133 2/15 1.375 3/8 1.625 1.143 1/7 1.385 5/13 1.636 1.154 2/13 1.400 2/5 1.643 1.167 1/6 1.417 5/12 1.667 1.182 2/11 1.429 3/7 1.692 1.200 1/5 1.444 4/9 1.700 1.214 3/14 1.455 5/11 1.714 1.222 2/9 1.462 6/13 1.727 1.231 3/13 1.467 7/15 1.733 DivAddVal/ MulVal 1/2 8/15 7/13 6/11 5/9 4/7 7/12 3/5 8/13 5/8 7/11 9/14 2/3 9/13 7/10 5/7 8/11 11/15 FR 1.750 1.769 1.778 1.786 1.800 1.818 1.833 1.846 1.857 1.867 1.875 1.889 1.900 1.909 1.917 1.923 1.929 1.933 DivAddVal/ MulVal 3/4 10/13 7/9 11/14 4/5 9/11 5/6 11/13 6/7 13/15 7/8 8/9 9/10 10/11 11/12 12/13 13/14 14/15 15.4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96. 15.4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200 According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table. The closest value for FRest = 1.628 in the look-up Table 307 is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8. According to Equation 6 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200. 15.4.17 UART1 Transmit Enable Register (U1TER - 0x4001 0030) In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), U1TER enables implementation of software flow control, too. When TxEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART1 transmission will stop. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 346 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Although Table 308 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART1 transmission will stop. Table 308 describes how to use TXEn bit in order to achieve software flow control. Table 308: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description Bit Symbol Description Reset Value 6:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as 1 soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C) The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode. Table 309: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Bit Symbol Value Description Reset value 0 NMMEN 0 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. 1 RXDIS 0 The receiver is enabled. 0 1 The receiver is disabled. 2 AADEN 0 Auto Address Detect (AAD) is disabled. 0 1 Auto Address Detect (AAD) is enabled. 3 SEL 0 If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 1 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 4 DCTRL 0 Disable Auto Direction Control. 0 1 Enable Auto Direction Control. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 347 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 Table 309: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Bit Symbol Value Description Reset value 5 OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0 0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted. 1 The direction control pin will be driven to logic ‘1’ when the transmitter has data to be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted. 31:6 - - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 15.4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH 0x4001 0050) The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 310. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description Bit Symbol Description Reset value 7:0 ADRMATCH Contains the address match value. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054) The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. Table 311. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description Bit Symbol Description Reset value 7:0 DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15.4.21 RS-485/EIA-485 modes of operation The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs. RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 348 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 UM10360 User manual If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. RS-485/EIA-485 Auto Address Detection (AAD) mode When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode. In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register. If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value. When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt. While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO. RS-485/EIA-485 Auto Direction Control RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically control the state of either the RTS pin or the DTR pin as a direction control output signal. Setting RS485CTRL bit 4 = ‘1’ enables this feature. Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’. When Auto Direction Control is enabled, the selected pin will be asserted (driven low) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register. The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or DTR) with the exception of loopback mode. RS485/EIA-485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 349 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 RS485/EIA-485 output inversion The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted. 15.5 Architecture The architecture of the UART1 is shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART1. The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input. The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register (U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the serial output pin, TXD1. The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This divided down clock is the 16x oversample clock. The modem interface contains registers U1MCR and U1MSR. This interface is responsible for handshaking between a modem peripheral and the UART1. The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks. Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 350 of 849 NXP Semiconductors UM10360 Chapter 15: LPC176x/5x UART1 U1_CTS U1_RTS U1_DSR U1_DTR U1_DCD U1_RI Transmitter Holding Register TX_DMA_REQ TX_DMA_CLR Transmitter Transmitter FIFO Transmitter DMA Interface Transmitter Shift Register U1_TXD PCLK Baud Rate Generator Fractional Rate Divider Main Divider (DLM, DLL) UART1 interrupt Modem Control & Status Interrupt Control & Status U1_OE FIFO Control & Status Line Control & Status RS485, IrDA, & Auto-baud Receiver Buffer Register RX_DMA_REQ RX_DMA_CLR Receiver Receiver FIFO Receiver DMA Interface Receiver Shift Register U1_RXD Fig 53. UART1 block diagram UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 351 of 849 UM10360 Chapter 16: LPC176x/5x CAN1/2 Rev. 3.1 — 2 April 2014 User manual 16.1 Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_CAN1, PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be the same value. Remark: If CAN baud rates above 100 kbit/s (see Table 323) are needed, do not select the IRC as the clock source (see Table 17). 3. Wake-up: CAN controllers are able to wake up the microcontroller from Power-down mode, see Section 4.8.8. 4. Pins: Select CAN1/2 pins through the PINSEL registers and their pin modes through the PINMODE registers (Section 8.5). 5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers (Table 322). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. CAN controller initialization: see CANMOD register (Section 16.7.1). 16.2 CAN controllers Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The CAN Controller is designed to provide a full implementation of the CAN-Protocol according to the CAN Specification Version 2.0B. Microcontrollers with this on-chip CAN controller are used to build powerful local networks by supporting distributed real-time control with a very high level of security. The applications are automotive, industrial environments, and high speed networks as well as low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in various applications. The CAN module consists of two elements: the controller and the Acceptance Filter. All registers and the RAM are accessed as 32-bit words. 16.3 Features 16.3.1 General CAN features • Compatible with CAN specification 2.0B, ISO 11898-1. • Multi-master architecture with non destructive bit-wise arbitration. • Bus access priority determined by the message identifier (11-bit or 29-bit). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 352 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 • Guaranteed latency time for high priority messages. • Programmable transfer rate (up to 1 Mbit/s). • Multicast and broadcast message facility. • Data length from 0 up to 8 bytes. • Powerful error handling capability. • Non-return-to-zero (NRZ) encoding/decoding with bit stuffing. 16.3.2 CAN controller features • 2 CAN controllers and buses. • Supports 11-bit identifier as well as 29-bit identifier. • Double Receive Buffer and Triple Transmit Buffer. • Programmable Error Warning Limit and Error Counters with read/write access. • Arbitration Lost Capture and Error Code Capture with detailed bit position. • Single Shot Transmission (no re-transmission). • Listen Only Mode (no acknowledge, no active error flags). • Reception of "own" messages (Self Reception Request). 16.3.3 Acceptance filter features • Fast hardware implemented search algorithm supporting a large number of CAN identifiers. • Global Acceptance Filter recognizes 11-bit and 29-bit Rx Identifiers for all CAN buses. • Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. 16.4 Pin description Table 312. CAN Pin descriptions Pin Name Type RD1, RD2 Input TD1, TD2 Output Description Serial Inputs. From CAN transceivers. Serial Outputs. To CAN transceivers. 16.5 CAN controller architecture UM10360 User manual The CAN Controller is a complete serial interface with both Transmit and Receive Buffers but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a separate block (Acceptance Filter). Except for message buffering and acceptance filtering the functionality is similar to the PeliCAN concept. The CAN Controller Block includes interfaces to the following blocks: • APB Interface • Acceptance Filter All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 353 of 849 NXP Semiconductors • Nested Vectored Interrupt Controller (NVIC) • CAN Transceiver • Common Status Registers UM10360 Chapter 16: LPC176x/5x CAN1/2 APB BUS NVIC COMMON STATUS REGISTER ACCEPTANCE FILTER INTERFACE MANAGEMENT LOGIC TRANSMIT BUFFERS 1,2 AND 3 RECEIVE BUFFERS 1 AND 2 CAN CORE BLOCK ERROR MANAGEMENT LOGIC BIT TIMING LOGIC BIT STREAM PROCESSOR TX CAN RX TRANSCEIVER Fig 54. CAN controller block diagram 16.5.1 APB Interface Block (AIB) The APB Interface Block provides access to all CAN Controller registers. 16.5.2 Interface Management Logic (IML) The Interface Management Logic interprets commands from the CPU, controls internal addressing of the CAN Registers and provides interrupts and status information to the CPU. 16.5.3 Transmit Buffers (TXB) The TXB represents a Triple Transmit Buffer, which is the interface between the Interface Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is able to store a complete message which can be transmitted over the CAN network. This buffer is written by the CPU and read out by the BSP. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 354 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 31 24 23 16 15 TX Frame info unused TX DLC unused 0 ... 0 TX Data 4 TX Data 3 TX Data 2 TX Data 8 TX Data 7 TX Data 6 87 TX Priority ID.28 ... ID.18 TX Data 1 TX Data 5 0 TFS TID TDA TDB Standard Frame Format (11-bit Identifier) Descriptor Field Data Field 31 24 23 16 15 TX Frame info unused TX DLC unused 0 0 0 ID.28 ... TX Data 4 TX Data 3 TX Data 2 TX Data 8 TX Data 7 TX Data 6 87 TX Priority ID.00 TX Data 1 TX Data 5 0 TFS TID TDA TDB Descriptor Field Data Field Extended Frame Format (29-bit Identifier) Fig 55. Transmit buffer layout for standard and extended frame format configurations 16.5.4 Receive Buffer (RXB) The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is located between the CAN Controller Core Block and APB Interface Block and stores all received messages from the CAN Bus line. With the help of this Double Receive Buffer concept the CPU is able to process one message while another message is being received. The global layout of the Receive Buffer is very similar to the Transmit Buffer described earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length Code have the same meaning as described for the Transmit Buffer. In addition, the Receive Buffer includes an ID Index field (see Section 16.7.9.1 “ID index field”). The received Data Length Code represents the real transmitted Data Length Code, which may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum number of received data bytes is 8. This should be taken into account by reading a message from the Receive Buffer. If there is not enough space for a new message within the Receive Buffer, the CAN Controller generates a Data Overrun condition when this message becomes valid and the acceptance test was positive. A message that is partly written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if enabled. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 355 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 31 RX 24 23 16 15 Frame info unused RX DLC unused 10 9 8 7 ID Index unused ID.28 ... ID.18 RX Data 4 RX Data 3 RX Data 2 RX Data 1 RX Data 8 RX Data 7 RX Data 6 RX Data 5 0 RFS RID RDA RDB Descriptor Field Data Field Standard Frame Format (11-bit Identifier) BPM=bypass message 31 RX 24 23 16 15 Frame info unused RX DLC unused 10 9 8 7 ID Index unused ID.28 ... ID.00 RX Data 4 RX Data 3 RX Data 2 RX Data 1 RX Data 8 RX Data 7 RX Data 6 RX Data 5 0 RFS RID RDA RDB Descriptor Field Data Field Extended Frame Format (29-bit Identifier) Fig 56. Receive buffer layout for standard and extended frame format configurations 16.5.5 Error Management Logic (EML) The EML is responsible for the error confinement. It gets error announcements from the BSP and then informs the BSP and IML about error statistics. 16.5.6 Bit Timing Logic (BTL) The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant" Bus line transition at the beginning of a message (hard synchronization) and re-synchronizes on further transitions during the reception of a message (soft synchronization). The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time. 16.5.7 Bit Stream Processor (BSP) The Bit Stream Processor is a sequencer, controlling the data stream between the Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection, arbitration, stuffing and error handling on the CAN Bus. 16.5.8 CAN controller self-tests The CAN controller supports two different options for self-tests: • Global Self-Test (setting the self reception request bit in normal Operating Mode) • Local Self-Test (setting the self reception request bit in Self Test Mode) UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 356 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled. Global self test A Global Self-Test can for example be used to verify the chosen configuration of the CAN Controller in a given CAN system. As shown in Figure 57, at least one other CAN node, which is acknowledging each CAN message has to be connected to the CAN bus. TTXTXXBBuBufuffefferfer r CAN Bus LPC17xx Transceiver ack RX Buffer Fig 57. Global Self-Test (high-speed CAN Bus example) Initiating a Global Self-Test is similar to a normal CAN transmission. In this case the transmission of a CAN message(s) is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the CAN Controller Command register (CANCMR). Local self test The Local Self-Test perfectly fits for single node tests. In this case an acknowledge from other nodes is not needed. As shown in the Figure below, a CAN transceiver with an appropriate CAN bus termination has to be connected to the LPC176x/5x. The CAN Controller has to be put into the 'Self Test Mode' by setting the STM bit in the CAN Controller Mode register (CANMOD). Hint: Setting the Self Test Mode bit (STM) is possible only when the CAN Controller is in Reset Mode. TTXTXXBBuBufuffeffefrer r LPC17xx RX Buffer Transceiver Fig 58. Local self test (high-speed CAN Bus example) A message transmission is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer(s) (STB3, STB2, STB1). UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 357 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.6 Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 313. Memory map of the CAN block Address Range 0x4003 8000 - 0x4003 87FF 0x4003 C000 - 0x4003 C017 0x4004 0000 - 0x4004 000B 0x4004 4000 - 0x4004 405F 0x4004 8000 - 0x4004 805F 0x400F C110 - 0x400F C114 Used for Acceptance Filter RAM. Acceptance Filter Registers. Central CAN Registers. CAN Controller 1 Registers. CAN Controller 2 Registers. CAN Wake and Sleep Registers. 16.7 CAN controller registers CAN block implements the registers shown in Table 314 and Table 315. More detailed descriptions follow. Table 314. CAN acceptance filter and central CAN registers Name Description AFMR Acceptance Filter Register SFF_sa Standard Frame Individual Start Address Register SFF_GRP_sa Standard Frame Group Start Address Register EFF_sa Extended Frame Start Address Register EFF_GRP_sa Extended Frame Group Start Address Register ENDofTable End of AF Tables register LUTerrAd LUT Error Address register LUTerr LUT Error Register CANTxSR CAN Central Transmit Status Register CANRxSR CAN Central Receive Status Register CANMSR CAN Central Miscellaneous Register Access R/W R/W R/W R/W R/W R/W RO RO RO RO RO Reset Value 1 0 0 0 0 0 0 0 0x0003 0300 0 0 Address 0x4003 C000 0x4003 C004 0x4003 C008 0x4003 C00C 0x4003 C010 0x4003 C014 0x4003 C018 0x4003 C01C 0x4004 0000 0x4004 0004 0x4004 0008 Table 315. CAN1 and CAN2 controller register map Generic Description Name MOD Controls the operating mode of the CAN Controller. Access Reset value R/W 1 CMR Command bits that affect the state of the CAN Controller WO 0 GSR Global Controller Status and Error Counters RO[1] 0x3C ICR Interrupt status, Arbitration Lost Capture, Error Code Capture RO 0 IER Interrupt Enable R/W 0 CAN1 & 2 Register Name & Address CAN1MOD - 0x4004 4000 CAN2MOD - 0x4004 8000 CAN1CMR - 0x4004 4004 CAN2CMR - 0x4004 8004 CAN1GSR - 0x4004 4008 CAN2GSR - 0x4004 8008 CAN1ICR - 0x4004 400C CAN2ICR - 0x4004 800C CAN1IER - 0x4004 4010 CAN2IER - 0x4004 8010 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 358 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 315. CAN1 and CAN2 controller register map …continued Generic Description Name BTR Bus Timing EWL Error Warning Limit SR Status Register RFS Receive frame status RID Received Identifier RDA Received data bytes 1-4 RDB Received data bytes 5-8 TFI1 Transmit frame info (Tx Buffer 1) TID1 Transmit Identifier (Tx Buffer 1) TDA1 Transmit data bytes 1-4 (Tx Buffer 1) TDB1 Transmit data bytes 5-8 (Tx Buffer 1) TFI2 Transmit frame info (Tx Buffer 2) TID2 Transmit Identifier (Tx Buffer 2) TDA2 Transmit data bytes 1-4 (Tx Buffer 2) TDB2 Transmit data bytes 5-8 (Tx Buffer 2) TFI3 Transmit frame info (Tx Buffer 3) TID3 Transmit Identifier (Tx Buffer 3) TDA3 Transmit data bytes 1-4 (Tx Buffer 3) TDB3 Transmit data bytes 5-8 (Tx Buffer 3) [1] The error counters can only be written when RM in CANMOD is 1. [2] These registers can only be written when RM in CANMOD is 1. Access Reset value CAN1 & 2 Register Name & Address R/W[2] 0x1C0000 CAN1BTR - 0x4004 4014 CAN2BTR - 0x4004 8014 R/W[2] 0x60 CAN1EWL - 0x4004 4018 CAN2EWL - 0x4004 8018 RO 0x3C3C3C CAN1SR - 0x4004 401C CAN2SR - 0x4004 801C R/W[2] 0 CAN1RFS - 0x4004 4020 CAN2RFS - 0x4004 8020 R/W[2] 0 CAN1RID - 0x4004 4024 CAN2RID - 0x4004 8024 R/W[2] 0 CAN1RDA - 0x4004 4028 CAN2RDA - 0x4004 8028 R/W[2] 0 CAN1RDB - 0x4004 402C CAN2RDB - 0x4004 802C R/W 0 CAN1TFI1 - 0x4004 4030 CAN2TFI1 - 0x4004 8030 R/W 0 CAN1TID1 - 0x4004 4034 CAN2TID1 - 0x4004 8034 R/W 0 CAN1TDA1 - 0x4004 4038 CAN2TDA1 - 0x4004 8038 R/W 0 CAN1TDB1- 0x4004 403C CAN2TDB1 - 0x4004 803C R/W 0 CAN1TFI2 - 0x4004 4040 CAN2TFI2 - 0x4004 8040 R/W 0 CAN1TID2 - 0x4004 4044 CAN2TID2 - 0x4004 8044 R/W 0 CAN1TDA2 - 0x4004 4048 CAN2TDA2 - 0x4004 8048 R/W 0 CAN1TDB2 - 0x4004 404C CAN2TDB2 - 0x4004 804C R/W 0 CAN1TFI3 - 0x4004 4050 CAN2TFI3 - 0x4004 8050 R/W 0 CAN1TID3 - 0x4004 4054 CAN2TID3 - 0x4004 8054 R/W 0 CAN1TDA3 - 0x4004 4058 CAN2TDA3 - 0x4004 8058 R/W 0 CAN1TDB3 - 0x4004 405C CAN2TDB3 - 0x4004 805C UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 359 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 The internal registers of each CAN Controller appear to the CPU as on-chip memory mapped peripheral registers. Because the CAN Controller can operate in different modes (Operating/Reset, see also Section 16.7.1 “CAN Mode register (CAN1MOD 0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different internal address definitions. Note that write access to some registers is only allowed in Reset Mode. Table 316. CAN1 and CAN2 controller register summary Generic Operating Mode Name Read Write MOD Mode Mode CMR 0x00 Command GSR Global Status and Error Counters - ICR Interrupt and Capture - IER Interrupt Enable Interrupt Enable BTR Bus Timing - EWL Error Warning Limit - SR Status - RFS Rx Info and Index - RID Rx Identifier - RDA Rx Data - RDB Rx Info and Index - TFI1 Tx Info1 Tx Info TID1 Tx Identifier Tx Identifier TDA1 Tx Data Tx Data TDB1 Tx Data Tx Data Reset Mode Read Mode 0x00 Global Status and Error Counters Interrupt and Capture Interrupt Enable Bus Timing Error Warning Limit Status Rx Info and Index Rx Identifier Rx Data Rx Info and Index Tx Info Tx Identifier Tx Data Tx Data Write Mode Command Error Counters only Interrupt Enable Bus Timing Error Warning Limit Rx Info and Index Rx Identifier Rx Data Rx Info and Index Tx Info Tx Identifier Tx Data Tx Data Table 317. CAN Wake and Sleep registers Name Description Access Reset Value Address CANSLEEPCLR Allows clearing the current CAN channel sleep state as well as R/W 0 reading that state. 0x400F C110 CANWAKEFLAGS Allows reading the wake-up state of the CAN channels. R/W 0 0x400F C114 In the following register tables, the column “Reset Value” shows how a hardware reset affects each bit or field, while the column “RM Set” indicates how each bit or field is affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that while hardware reset sets RM, in this case the setting noted in the “Reset Value” column prevails over that shown in the “RM Set” column, in the few bits where they differ. In both columns, X indicates the bit or field is unchanged. 16.7.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD 0x4004 8000) The contents of the Mode Register are used to change the behavior of the CAN Controller. Bits may be set or reset by the CPU that uses the Mode Register as a read/write memory. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 360 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 318. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description Bit Symbol Value Function Reset RM Value Set 0 RM[1][6] Reset Mode. 1 1 0 (normal) The CAN Controller is in the Operating Mode, and certain registers can not be written. 1 (reset) CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. 1 LOM[3][2] Listen Only Mode. 0 x [6] 0 (normal) The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. 1 (listen only) The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in “error passive” mode. This mode is intended for software bit rate detection and “hot plugging”. 2 STM[3][6] Self Test Mode. 0 x 0 (normal) A transmitted message must be acknowledged to be considered successful. 1 (self test) The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. 3 TPM[4] Transmit Priority Mode. 0 x 0 (CAN ID) The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. 1 (local prio) The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. 4 SM[5] Sleep Mode. 0 0 0 (wake-up) Normal operation. 1 (sleep) The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 16.8.2 on page 379. 5 RPM Receive Polarity Mode. 0 x 0 (low active) RD input is active Low (dominant bit = 0). 1 (high active) RD input is active High (dominant bit = 1) -- reverse polarity. 6 - - Reserved, user software should not write ones to reserved bits. 0 0 7 TM Test Mode. 0 x 0 (disabled) Normal operation. 1 (enabled) The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. 31:8 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. [1] During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit is set '0' the CAN Controller will wait for: - one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated reset. - 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the Bus-On mode. [2] This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can be used e.g. for software driven bit rate detection and "hot plugging". UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 361 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 [3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously. [4] Transmit Priority Mode is explained in more detail in Section 16.5.3 “Transmit Buffers (TXB)”. [5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only when Bus-Free is detected again. [6] The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation. 16.7.2 CAN Command Register (CAN1CMR - 0x4004 x004, CAN2CMR 0x4004 8004) Writing to this write-only register initiates an action within the transfer layer of the CAN Controller. Reading this register yields zeroes. At least one internal clock cycle is needed for processing between two commands. Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Bit Symbol Value Function Reset RM Value Set 0[1][2] TR Transmission Request. 0 0 0 (absent) No transmission request. 1 (present) The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 16.5.3 “Transmit Buffers (TXB)”) 1[1][3] AT Abort Transmission. 0 0 0 (no action) Do not abort the transmission. 1 (present) if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. 2[4] RRB Release Receive Buffer. 0 0 0 (no action) Do not release the receive buffer. 1 (released) The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). 3[5] CDO Clear Data Overrun. 0 0 0 (no action) Do not clear the data overrun bit. 1 (clear) The Data Overrun bit in Status Register(s) is cleared. 4[1][6] SRR Self Reception Request. 0 0 0 (absent) No self reception request. 1 (present) The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 362 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Bit Symbol Value Function Reset RM Value Set 5 STB1 Select Tx Buffer 1. 0 0 0 (not selected) Tx Buffer 1 is not selected for transmission. 1 (selected) Tx Buffer 1 is selected for transmission. 6 STB2 Select Tx Buffer 2. 0 0 0 (not selected) Tx Buffer 2 is not selected for transmission. 1 (selected) Tx Buffer 2 is selected for transmission. 7 STB3 Select Tx Buffer 3. 0 0 0 (not selected) Tx Buffer 3 is not selected for transmission. 1 (selected) Tx Buffer 3 is selected for transmission. 31:8 - Reserved, user software should not write ones to reserved bits. NA [1] - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in case of an error or arbitration lost (single shot transmission). - Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature. No re-transmission will be performed in case of an error or arbitration lost. - Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically. - Setting TR and SRR simultaneously will ignore the set SRR bit. [2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission bit. [3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated. [4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'. This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated. [5] This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun Status bit is set no further Data Overrun Interrupt is generated. [6] Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16.7.1 “CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”). 16.7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR 0x4004 8008) The content of the Global Status Register reflects the status of the CAN Controller. This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not listed read as 0 and should be written as 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 363 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 320. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description Bit Symbol Value Function Reset RM Value Set 0 RBS[1] Receive Buffer Status. 0 0 0 (empty) No message is available. 1 (full) At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. 1 DOS[2] Data Overrun Status. 0 0 0 (absent) No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). 1 (overrun) A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). 2 TBS Transmit Buffer Status. 1 1 0 (locked) At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). 1 (released) All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 3 TCS[3] Transmit Complete Status. 1 x 0 (incomplete) At least one requested transmission has not been successfully completed yet. 1 (complete) All requested transmission(s) has (have) been successfully completed. 4 RS[4] Receive Status. 1 0 0 (idle) The CAN controller is idle. 1 (receive) The CAN controller is receiving a message. 5 TS[4] Transmit Status. 1 0 0 (idle) The CAN controller is idle. 1 (transmit) The CAN controller is sending a message. 6 ES[5] Error Status. 0 0 0 (ok) Both error counters are below the Error Warning Limit. 1 (error) One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. 7 BS[6] Bus Status. 0 0 0 (Bus-On) The CAN Controller is involved in bus activities 1 (Bus-Off) The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. 15:8 - - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. 23:16 RXERR - The current value of the Rx Error Counter (an 8-bit value). 0 X 31:24 TXERR - The current value of the Tx Error Counter (an 8-bit value). 0 X [1] After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 364 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 [2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. [3] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. [4] If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. [5] Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 16.7.7 “CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)”. [6] Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. UM10360 User manual RX error counter The RX Error Counter Register, which is part of the Status Register, reflects the current value of the Receive Error Counter. After hardware reset this register is initialized to 0. In Operating Mode this register appears to the CPU as a read-only memory. A write access to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no effect.The Rx Error Counter is determined as follows: RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000 Note that a CPU-forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. TX error counter The TX Error Counter Register, which is part of the Status Register, reflects the current value of the Transmit Error Counter. In Operating Mode this register appears to the CPU as a read-only memory. After hardware reset this register is initialized to 0. A write access to this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences of the Bus-Free signal). Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error counter is determined as follows: TX Error Counter = (CANxGSR AND 0xFF000000) / 0x01000000 Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a CPU-forced content change of the TX Error Counter is possible only if the Reset Mode was entered previously. An Error or Bus Status change (Status Register), an Error Warning, or an Error Passive Interrupt forced by the new register content will not occur All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 365 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX Counter content is interpreted and the Bus Off event is performed in the same way as if it was forced by a bus error event. That means, that the Reset Mode is entered again, the TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status and Interrupt Register bits are set. Clearing of Reset Mode now will perform the protocol defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal). If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus Off keeps active and TXERR is frozen. 16.7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C, CAN2ICR - 0x4004 800C) Bits in this register indicate information about events on the CAN bus. This register is read-only. The Interrupt flags of the Interrupt and Capture Register allow the identification of an interrupt source. When one or more bits are set, a CAN interrupt will be indicated to the CPU. After this register is read from the CPU all interrupt bits are reset except of the Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory. Bits 1 through 10 clear when they are read. Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur. Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value will remain the same until it is read, at which time it is released to capture a new value. The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read from CANxICR, regardless of whether part or all of the register is read. This means that software should always read CANxICR as a word, and process and deal with all bits of the register as appropriate for the application. Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 0 RI[1] 0 (reset) Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE 0 0 1 (set) bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. 1 TI1 0 (reset) Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 0 0 1 (set) 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. 2 EI 0 (reset) Error Warning Interrupt. This bit is set on every change (set or clear) of either the 0 X 1 (set) Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. 3 DOI 0 (reset) Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 0 0 1 (set) to 1 and the DOIE bit in CANxIER is 1. 4 WUI[2] 0 (reset) Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity 0 0 1 (set) is detected and the WUIE bit in CANxIER is 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 366 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Bit Symbol Value Function Reset RM Value Set 5 EPI 0 (reset) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the 0 0 1 (set) CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. 6 ALI 0 (reset) Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the 0 0 1 (set) CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. 7 BEI 0 (reset) Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN 0 X 1 (set) controller detects an error on the bus. 8 IDI 0 (reset) ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN 0 0 1 (set) Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. 9 TI2 0 (reset) Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 0 0 1 (set) 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. 10 TI3 0 (reset) Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 0 0 1 (set) 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. 15:11 - - Reserved, user software should not write ones to reserved bits. 0 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 367 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Bit Symbol Value Function Reset RM Value Set 20:16 ERRBIT 4:0[3] Error Code Capture: when the CAN controller detects a bus error, the location of 0 X the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 Start of Frame 00010 ID28 ... ID21 00110 ID20 ... ID18 00100 SRTR Bit 00101 IDE bit 00111 ID17 ... 13 01111 ID12 ... ID5 01110 ID4 ... ID0 01100 RTR Bit 01101 Reserved Bit 1 01001 Reserved Bit 0 01011 Data Length Code 01010 Data Field 01000 CRC Sequence 11000 CRC Delimiter 11001 Acknowledge Slot 11011 Acknowledge Delimiter 11010 End of Frame 10010 Intermission 10001 Active Error Flag 10110 Passive Error Flag 10011 Tolerate Dominant Bits 10111 Error Delimiter 11100 Overload flag 21 ERRDIR When the CAN controller detects a bus error, the direction of the current bit is 0 X captured in this bit. 0 Error occurred during transmitting. 1 Error occurred during receiving. 23:22 ERRC1:0 When the CAN controller detects a bus error, the type of error is captured in this 0 X field: 00 Bit error 01 Form error 10 Stuff error 11 Other error UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 368 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Bit Symbol Value Function Reset RM Value Set 31:24 ALCBIT[4] - Each time arbitration is lost while trying to send on the CAN, the bit number 0 X within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 arbitration lost in the first bit (MS) of identifier ... 11 arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 arbitration lost in IDE bit 13 arbitration lost in 12th bit of identifier (extended frame only) ... 30 arbitration lost in last bit of identifier (extended frame only) 31 arbitration lost in RTR bit (extended frame only) [1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. [2] A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. [3] Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. [4] On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. 16.7.5 CAN Interrupt Enable Register (CAN1IER - 0x4004 4010, CAN2IER 0x4004 8010) This read/write register controls whether various events on the CAN controller will result in an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt is disabled; if a bit in the CANxIER register is 1 the corresponding source is enabled to trigger an interrupt. Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description Bit Symbol Function Reset RM Value Set 0 RIE Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. 0 X 1 TIE1 Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted 0 X out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 2 EIE Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the 0 X CAN Controller requests the respective interrupt. 3 DOIE Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the 0 X CAN Controller requests the respective interrupt. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 369 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description …continued Bit Symbol Function Reset RM Value Set 4 WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt 0 X is requested. 5 EPIE Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error 0 X active to error passive or vice versa, the respective interrupt is requested. 6 ALIE Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective 0 X interrupt is requested. 7 BEIE Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the 0 X respective interrupt. 8 IDIE ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller 0 X requests the respective interrupt. 9 TIE2 Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted 0 X out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 10 TIE3 Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted 0 X out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 16.7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR 0x4004 8014) This register controls how various CAN timings are derived from the APB clock. It defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). Furthermore, it defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point. It can be read at any time but can only be written if the RM bit in CANmod is 1. Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description Bit Symbol Value Function Reset RM Value Set 9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the 0 X CAN clock. 13:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 15:14 SJW The Synchronization Jump Width is (this value plus one) CAN clocks. 0 X 19:16 TESG1 The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. 1100 X 22:20 TESG2 The delay from the sample point to the next nominal sync point is (this value plus one) 001 X CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 370 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description …continued Bit Symbol Value Function Reset RM Value Set 23 SAM Sampling 0 The bus is sampled once (recommended for high speed buses) 0 X 1 The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. Baud rate prescaler The period of the CAN system clock tSCL is programmable and determines the individual bit timing. The CAN system clock tSCL is calculated using the following equation: tSCL = tCANsuppliedCLK  BRP + 1 (7) Synchronization jump width To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width tSJW defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: tSJW = tSCL  SJW + 1 (8) Time segment 1 and time segment 2 Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point: tSYNCSEG = tSCL (9) tTSEG1 = tSCL  TSEG1 + 1 (10) tTSEG2 = tSCL  TSEG2 + 1 (11) 16.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1. Table 324. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018) bit description Bit Symbol Function Reset RM Value Set 7:0 EWL During CAN operation, this value is compared to both the Tx and Rx Error Counters. If 9610 = 0x6 X either of these counter matches this value, the Error Status (ES) bit in CANSR is set. 0 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 371 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Note that a content change of the Error Warning Limit Register is possible only if the Reset Mode was entered previously. An Error Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. 16.7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR 0x4004 801C) This read-only register contains three status bytes in which the bits not related to transmission are identical to the corresponding bits in the Global Status Register, while those relating to transmission reflect the status of each of the 3 Tx Buffers. Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Bit Symbol Value Function Reset RM Value Set 0 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0 1 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0 2 TBS1[1] Transmit Buffer Status 1. 1 1 0(locked) Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 1(released) Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 3 TCS1[2] Transmission Complete Status. 1 x 0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete. 1(complete) The previously requested transmission for Tx Buffer 1 has been successfully completed. 4 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0 5 TS1 Transmit Status 1. 1 0 0(idle) There is no transmission from Tx Buffer 1. 1(transmit) The CAN Controller is transmitting a message from Tx Buffer 1. 6 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0 7 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0 8 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0 9 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0 10 TBS2[1] Transmit Buffer Status 2. 1 1 0(locked) Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 1(released) Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 11 TCS2[2] Transmission Complete Status. 1 x 0(incomplete) The previously requested transmission for Tx Buffer 2 is not complete. 1(complete) The previously requested transmission for Tx Buffer 2 has been successfully completed. 12 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0 UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 372 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description …continued Bit Symbol Value Function Reset RM Value Set 13 TS2 Transmit Status 2. 1 0 0(idle) There is no transmission from Tx Buffer 2. 1(transmit) The CAN Controller is transmitting a message from Tx Buffer 2. 14 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0 15 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0 16 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0 17 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0 18 TBS3[1] Transmit Buffer Status 3. 1 1 0(locked) Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 1(released) Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 19 TCS3[2] Transmission Complete Status. 1 x 0(incomplete) The previously requested transmission for Tx Buffer 3 is not complete. 1(complete) The previously requested transmission for Tx Buffer 3 has been successfully completed. 20 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0 21 TS3 Transmit Status 3. 1 0 0(idle) There is no transmission from Tx Buffer 3. 1(transmit) The CAN Controller is transmitting a message from Tx Buffer 3. 22 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0 23 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0 31:24 - Reserved, the value read from a reserved bit is not defined. NA [1] If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is lost without this being signalled. [2] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully. 16.7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020, This register defines the characteristics of the current received message. It is read-only in normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 373 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 326. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020) bit description Bit Symbol Function Reset RM Value Set 9:0 ID Index If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry 0 X at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 16.17 “Examples of acceptance filter tables and ID index values” on page 402 for examples of ID Index values. 10 BP If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field 0 X (above) is meaningless. 15:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 19:16 DLC The field contains the Data Length Code (DLC) field of the current received message. When 0 X RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. 29:20 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 30 RTR This bit contains the Remote Transmission Request bit of the current received message. 0 0 X indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. 31 FF A 0 in this bit indicates that the current received message included an 11-bit Identifier, while 0 X a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. 16.7.9.1 ID index field The ID Index is a 10-bit field in the Info Register that contains the table position of the ID Look-up Table if the currently received message was accepted. The software can use this index to simplify message transfers from the Receive Buffer into the Shared Message Memory. Whenever bit 10 (BP) of the ID Index in the CANRFS register is 1, the current CAN message was received in acceptance filter bypass mode. 16.7.10 CAN Receive Identifier register (CAN1RID - 0x4004 4024, CAN2RID 0x4004 8024) This register contains the Identifier field of the current received message. It is read-only in normal operation but can be written for testing purposes if the RM bit in CANmod is 1. It has two different formats depending on the FF bit in CANRFS. See Table 314 for details on specific CAN channel register address. Table 327. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit description Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these 0 X bits are called ID10-0, while in CAN 2.0B they’re called ID29-18. 31:11 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 374 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 328. RX Identifier register when FF = 1 Bit Symbol Function Reset Value RM Set 28:0 ID The 29-bit Identifier field of the current received message. In CAN 2.0B these bits 0 X are called ID29-0. 31:29 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. 16.7.11 CAN Receive Data register A (CAN1RDA - 0x4004 4028, CAN2RDA 0x4004 8028) This register contains the first 1-4 Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 314 for details on specific CAN channel register address. Table 329. CAN Receive Data register A (CAN1RDA - address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit description Bit Symbol Function Reset Value RM Set 7:0 Data 1 If the DLC field in CANRFS ³ 0001, this contains the first Data byte of the current 0 X received message. 15:8 Data 2 If the DLC field in CANRFS ³ 0010, this contains the first Data byte of the current 0 X received message. 23:16 Data 3 If the DLC field in CANRFS ³ 0011, this contains the first Data byte of the current 0 X received message. 31:24 Data 4 If the DLC field in CANRFS ³ 0100, this contains the first Data byte of the current 0 X received message. 16.7.12 CAN Receive Data register B (CAN1RDB - 0x4004 402C, CAN2RDB 0x4004 802C) This register contains the 5th through 8th Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 314 for details on specific CAN channel register address. Table 330. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit description Bit Symbol Function Reset Value RM Set 7:0 Data 5 If the DLC field in CANRFS ³ 0101, this contains the first Data byte of the current 0 X received message. 15:8 Data 6 If the DLC field in CANRFS ³ 0110, this contains the first Data byte of the current 0 X received message. 23:16 Data 7 If the DLC field in CANRFS ³ 0111, this contains the first Data byte of the current 0 X received message. 31:24 Data 8 If the DLC field in CANRFS ³ 1000, this contains the first Data byte of the current 0 X received message. 16.7.13 CAN Transmit Frame Information register (CAN1TFI[1/2/3] 0x4004 40[30/ 40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer. Bits not listed read as 0 and should be written as 0. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 375 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison, when using the Self Reception facility (self test), otherwise they are not defined. The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4 words and is able to store one complete CAN message as shown in Figure 55. The buffer layout is subdivided into Descriptor and Data Field where the first word of the Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows the definition of a certain priority for each transmit message. Depending on the chosen Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes. Table 331. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] 0x4004 80[30/40/50]) bit description Bit Symbol Function Reset RM Value Set 7:0 PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx x Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. 15:8 - Reserved. 0 19:16 DLC Data Length Code. This value is sent in the DLC field of the next transmit message. In 0 X addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes 29:20 - Reserved. 0 30 RTR This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of 0 X data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. 31 FF If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame 0 X format), while if it’s 1, the message will be sent with a 29-bit Identifier (extended frame format). Automatic transmit priority detection To allow uninterrupted streams of transmit messages, the CAN Controller provides Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selected Transmit Priority Mode, internal prioritization is based on the CAN Identifier or a user defined "local priority". If more than one message is enabled for transmission (TR=1) the internal transmit message queue is organized such as that the transmit buffer with the lowest CAN Identifier (TID) or the lowest "local priority" (TX Priority) wins the prioritization and is sent first. The result of the internal scheduling process is taken into account short before a new CAN message is sent on the bus. This is also true after the occurrence of a transmission error and right before a re-transmission. UM10360 User manual Tx DLC The number of bytes in the Data Field of a message is coded with the Data Length Code (DLC). At the start of a Remote Frame transmission the DLC is not considered due to the RTR bit being '1 ' (remote). This forces the number of transmitted/received data bytes to be 0. Nevertheless, the DLC must be specified correctly to avoid bus errors, if two CAN All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 376 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Controllers start a Remote Frame transmission with the same identifier simultaneously. For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 is selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows: DataByteCount = DLC (12) 16.7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] 0x4004 40[34/44/54], CAN2TID[1/2/3] - 0x4004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, software can write to one of these registers to define the Identifier field of the next transmit message. Bits not listed read as 0 and should be written as 0. The register assumes two different formats depending on the FF bit in CANTFI. In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 to ID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits (ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during the arbitration process. The Identifier acts as the message's name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. Table 332. CAN Transfer Identifier register (CAN1TID[1/2/3] - address 0x4004 40[34/44/54], CAN2TID[1/2/3] - address 0x4004 80[34/44/54]) bit description Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier to be sent in the next transmit message. 0 X 31:11 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. Table 333. Transfer Identifier register when FF = 1 Bit Symbol Function 28:0 ID The 29-bit Identifier to be sent in the next transmit message. 31:29 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset Value RM Set 0 X NA 16.7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58], CAN2TDA[1/2/3] - 0x4004 80[38/48/58]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the first 1 - 4 data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. The first bit transmitted is the most significant bit of TX Data Byte 1. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 377 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 Table 334. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address 0x4004 80[38/48/58]) bit description Bit Symbol Function Reset Value RM Set 7:0 Data 1 If RTR = 0 and DLC ³ 0001 in the corresponding CANxTFI, this byte is sent as the 0 X first Data byte of the next transmit message. 15;8 Data 2 If RTR = 0 and DLC ³ 0010 in the corresponding CANxTFI, this byte is sent as the 0 X 2nd Data byte of the next transmit message. 23:16 Data 3 If RTR = 0 and DLC ³ 0011 in the corresponding CANxTFI, this byte is sent as the 0 X 3rd Data byte of the next transmit message. 31:24 Data 4 If RTR = 0 and DLC ³ 0100 in the corresponding CANxTFI, this byte is sent as the 0 X 4th Data byte of the next transmit message. 16.7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. The first bit transmitted is the most significant bit of TX Data Byte 1. Table 335. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address 0x4004 80[3C/4C/5C]) bit description Bit Symbol Function Reset Value RM Set 7:0 Data 5 If RTR = 0 and DLC ³ 0101 in the corresponding CANTFI, this byte is sent as the 0 X 5th Data byte of the next transmit message. 15;8 Data 6 If RTR = 0 and DLC ³ 0110 in the corresponding CANTFI, this byte is sent as the 0 X 6th Data byte of the next transmit message. 23:16 Data 7 If RTR = 0 and DLC ³ 0111 in the corresponding CANTFI, this byte is sent as the 0 X 7th Data byte of the next transmit message. 31:24 Data 8 If RTR = 0 and DLC ³ 1000 in the corresponding CANTFI, this byte is sent as the 0 X 8th Data byte of the next transmit message. 16.7.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110) This register provides the current sleep state of the two CAN channels and provides a means to restore the clocks to that channel following wake-up. Refer to Section 16.8.2 “Sleep mode” for more information on the CAN sleep feature. Table 336. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description Bit Symbol Function Reset Value 0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 1 CAN1SLEEP Sleep status and control for CAN channel 1. 0 Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. 2 CAN2SLEEP Sleep status and control for CAN channel 2. 0 Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 378 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114) This register provides the wake-up status for the two CAN channels and allows clearing wake-up events. Refer to Section 16.8.2 “Sleep mode” for more information on the CAN sleep feature. Table 337. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description Bit Symbol Function Reset Value 0 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 1 CAN1WAKE Wake-up status for CAN channel 1. 0 Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. 2 CAN2WAKE Wake-up status for CAN channel 2. 0 Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. 31:3 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 16.8 CAN controller operation 16.8.1 Error handling The CAN Controllers count and handle transmit and receive errors as specified in CAN Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected error and are decremented when operation is error-free. If the Transmit Error counter contains 255 and another error occurs, the CAN Controller is forced into a state called Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and sets EI in CANxSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before operation resumes. 16.8.2 Sleep mode The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 379 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller that wakes up in response to bus activity is not able to receive an initial message until after it detects Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wake-up is immediate. Upon wake-up, software needs to do the following things: 1. Write a 1 to the relevant bit(s) in the CANSLEEPCLR register. 2. Write a 0 to the SM bit in the CAN1MOD and/or CAN2MOD register. 3. Write a 1 to the relevant bit(s) in the CANWAKEFLAGS register. Failure to perform this step will prevent subsequent entry into Power-down mode. If the LPC176x/5x is in Deep Sleep or Power-down mode, CAN activity will wake up the device if the CAN activity interrupt is enabled. See Section 4.8 “Power control”. 16.8.3 Interrupts Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each interrupt request will trigger the CAN common interrupt in the NVIC.The “other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one NVIC channel. 16.8.4 Transmit priority If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have the same smallest value, the lowest-numbered buffer sends first. The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message. 16.9 Centralized CAN registers For easy and fast access, all CAN Controller Status bits from each CAN Controller Status register are bundled together. Each defined byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits. All Status registers are read-only and allow byte, half word and word access. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 380 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000) Table 338. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description Bit Symbol Description 0 TS1 When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). 1 TS2 When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) 7:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 TBS1 When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). 9 TBS2 When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). 15:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 16 TCS1 When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). 17:16 TCS2 When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). 31:18 - Reserved, the value read from a reserved bit is not defined. Reset Value 0 0 NA 1 1 NA 1 1 NA 16.9.2 Central Receive Status Register (CANRxSR - 0x4004 0004) Table 339. Central Receive Status Register (CANRxSR - address 0x4004 0004) bit description Bit Symbol Description 0 RS1 When 1, CAN1 is receiving a message (same as RS in CAN1GSR). 1 RS2 When 1, CAN2 is receiving a message (same as RS in CAN2GSR). 7:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 RB1 When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). 9 RB2 When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). 15:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 16 DOS1 When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). 17:16 DOS2 When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). 31:18 - Reserved, the value read from a reserved bit is not defined. Reset Value 0 0 NA 0 0 NA 0 0 NA UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 381 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) Table 340. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description Bit Symbol Description Reset Value 0 E1 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the 0 CAN1EWL register (same as ES in CAN1GSR) 1 E2 When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the 0 CAN2EWL register (same as ES in CAN2GSR) 7:2 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 8 BS1 When 1, the CAN1 controller is currently involved in bus activities (same as BS in 0 CAN1GSR). 9 BS2 When 1, the CAN2 controller is currently involved in bus activities (same as BS in 0 CAN2GSR). 31:10 - Reserved, the value read from a reserved bit is not defined. NA 16.10 Global acceptance filter This block provides lookup for received Identifiers (called Acceptance Filtering in CAN terminology) for all the CAN Controllers. It includes a 512  32 (2 kB) RAM in which software maintains one to five tables of Identifiers. This RAM can contain up to 1024 Standard Identifiers or 512 Extended Identifiers, or a mixture of both types. 16.11 Acceptance filter modes The Acceptance Filter can be put into different modes by setting the according AccOff, AccBP, and eFCAN bits in the Acceptance Filter Mode Register (Section 16.14.1 “Acceptance Filter Mode Register (AFMR - 0x4003 C000)”). During each mode the access to the Configuration Register and the ID Look-up table is handled differently. Table 341. Acceptance filter modes and access control Acceptance Bit Bit Acceptance filter mode AccOff AccBP filter state ID Look-up table RAM[1] Acceptanc e filter config. registers CAN controller message receive interrupt Off Mode 1 0 reset & r/w access r/w access no messages halted from CPU from CPU accepted Bypass X 1 reset & r/w access r/w access all messages Mode halted from CPU from CPU accepted Operating 0 0 running read-only access from hardware Mode and from CPU[2] Acceptance acceptance filtering FullCAN filter only Mode [1] The whole ID Look-up Table RAM is only word accessible. [2] During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable or enable Messages. A write access to all section configuration registers is only possible during the Acceptance Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 382 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.11.1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization. During this mode an unconditional access to all registers and to the Look-up Table RAM is possible. With the Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in the Receive Buffers of active CAN Controllers. 16.11.2 Acceptance filter Bypass mode The Acceptance Filter Bypass Mode can be used for example to change the acceptance filter configuration during a running system, e.g. change of identifiers in the ID-Look-up Table memory. During this re-configuration, software acceptance filtering has to be used. It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI). In this mode all CAN message are accepted and stored in the Receive Buffers of active CAN Controllers. 16.11.3 Acceptance filter Operating mode The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the Configuration Register is set and the eFCAN = 0. 16.11.4 FullCAN mode The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the Configuration Register is set and the eFCAN = 1. More details on FullCAN mode are available in Section 16.16 “FullCAN mode”. 16.12 Sections of the ID look-up table RAM Four 12-bit section configuration registers (SFF_sa, SFF_GRP_sa, EFF_sa, EFF_GRP_sa) are used to define the boundaries of the different identifier sections in the ID-Look-up Table Memory. The fifth 12-bit section configuration register, the End of Table address register (ENDofTable) is used to define the end of all identifier sections. The End of Table address is also used to assign the start address of the section where FullCAN Message Objects, if enabled are stored. Table 342. Section configuration register settings ID-Look up Table Section Register Value Section status FullCAN (Standard Frame Format) Identifier Section SFF_sa = 0x000 disabled > 0x000 enabled Explicit Standard Frame Format Identifier Section SFF_GRP_sa = SFF_sa disabled > SFF_sa enabled Group of Standard Frame Format Identifier Section EFF_sa = SFF_GRP_sa disabled > SFF_GRP_sa enabled Explicit Extended Frame Format Identifier Section EFF_GRP_sa = EFF_sa disabled > EFF_sa enabled Group of Extended Frame Format Identifier Section ENDofTable = EFF_GRP_sa disabled > EFF_GRP_sa enabled UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 383 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.13 ID look-up table RAM The Whole ID Look-up Table RAM is only word accessible. A write access is only possible during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all Acceptance Filter Modes. If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode. The next table contains individual Standard Identifiers and the third contains ranges of Standard Identifiers, for which messages are to be received via the CAN Controllers. The tables of FullCAN and individual Standard Identifiers must be arranged in ascending numerical order, one per halfword, two per word. Since each CAN bus has its own address map, each entry also contains the number of the CAN Controller (SCC = 000 (CAN1) -or SCC = 001 (CAN2)) to which it applies. 31 29 26 16 15 13 10 0 DIS NOT CONTROLLER # ABLE USED IDENTIFIER Fig 59. Entry in FullCAN and individual standard identifier tables The table of Standard Identifier Ranges contains paired upper and lower (inclusive) bounds, one pair per word. These must also be arranged in ascending numerical order. DISABLE NOT USED DISABLE NOT USED 31 29 CONTROLLER # 26 16 LOWER IDENTIFIER BOUND CONTROLLER # 10 0 UPPER IDENTIFIER BOUND Fig 60. Entry in standard identifier range table The disable bits in Standard entries provide a means to turn response, to particular CAN Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter function is enabled, only the disable bits in Acceptance Filter RAM can be changed by software. Response to a range of Standard addresses can be enabled by writing 32 zero bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in RAM. Only the disable bits are actually changed. Disabled entries must maintain the ascending sequence of Identifiers. If Extended (29-bit) Identifiers are used in the application, at least one of the other two tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers and one for ranges of Extended Identifiers. The table of individual Extended Identifiers must be arranged in ascending numerical order. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 384 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 31 29 28 CONTROLLER # 0 IDENTIFIER Fig 61. Entry in either extended identifier table The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order. The first and second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of Extended addresses, such that any received address that falls in the inclusive range is received (accepted). Software must maintain the table to consist of such word pairs. There is no facility to receive messages to Extended identifiers using the FullCAN method. Five address registers point to the boundaries between the tables in Acceptance Filter RAM: FullCAN Standard addresses, Standard Individual addresses, Standard address ranges, Extended Individual addresses, and Extended address ranges. These tables must be consecutive in memory. The start of each of the latter four tables is implicitly the end of the preceding table. The end of the Extended range table is given in an End of Tables register. If the start address of a table equals the start of the next table or the End Of Tables register, that table is empty. When the Receive side of a CAN controller has received a complete Identifier, it signals the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads the Controller number, the size of the Identifier, and the Identifier itself from the Controller. It then proceeds to search its RAM to determine whether the message should be received or ignored. If FullCAN mode is enabled and the CAN controller signals that the current message contains a Standard identifier, the Acceptance Filter first searches the table of identifiers for which reception is to be done in FullCAN mode. Otherwise, or if the AF doesn’t find a match in the FullCAN table, it searches its individual Identifier table for the size of Identifier signalled by the CAN controller. If it finds an equal match, the AF signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in the appropriate individual Identifier table, it then searches the Identifier Range table for the size of Identifier signalled by the CAN controller. If the AF finds a match to a range in the table, it similarly signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in either the individual or Range table for the size of Identifier received, it signals the CAN controller to discard/ignore the received message. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 385 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.14 Acceptance filter registers 16.14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000) The AccBP and AccOff bits of the acceptance filter mode register are used for putting the acceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register can be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages. Table 343. Acceptance Filter Mode Register (AFMR - address 0x4003 C000) bit description Bit Symbol Value Description Reset Value 0 AccOff[2] 1 if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN 1 buses are ignored. 1 AccBP[1] 1 All Rx messages are accepted on enabled CAN controllers. Software must set this 0 bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. 2 eFCAN[3] 0 Software must read all messages for all enabled IDs on all enabled CAN buses, 0 from the receiving CAN controllers. 1 The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 16.16 “FullCAN mode” on page 391. 31:3 - Reserved, user software should not write ones to reserved bits. The value read NA from a reserved bit is not defined. [1] Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register, the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state machine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, and acceptance filtering can be done by software. [2] Acceptance Filter Off mode (AccOff): After power-up or hardware reset, the Acceptance filter will be in Off mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or by software, will force the acceptance filter into Off mode. [3] FullCAN Mode Enhancements: A FullCAN mode for received CAN messages can be enabled by setting the eFCAN bit in the acceptance filter mode register. 16.14.2 Section configuration registers The 10-bit section configuration registers are used for the ID look-up table RAM to indicate the boundaries of the different sections for explicit and group of CAN identifiers for 11-bit CAN and 29-bit CAN identifiers, respectively. The 10-bit wide section configuration registers allow the use of a 512x32 (2 kB) look-up table RAM. The whole ID Look-up Table RAM is only word accessible. All five section configuration registers contain APB addresses for the acceptance filter RAM and do not include the APB base address. A write access to all section configuration registers is only possible during the Acceptance filter off and Bypass modes. Read access is allowed in all acceptance filter modes. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 386 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 16.14.3 Standard Frame Individual Start Address register (SFF_sa 0x4003 C004) Table 344. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 10:2 SFF_sa[1] The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the 0 table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.4 Standard Frame Group Start Address register (SFF_GRP_sa 0x4003 C008) Table 345. Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11:2 SFF_GRP_sa[1] The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If 0 the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. 31:12 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C) Table 346. Extended Frame Start Address register (EFF_sa - address 0x4003 C00C) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 10:2 EFF_sa[1] The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the 0 table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 387 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.6 Extended Frame Group Start Address register (EFF_GRP_sa 0x4003 C010) Table 347. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11:2 Eff_GRP_sa[1] The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If 0 the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. 31:12 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.7 End of AF Tables register (ENDofTable - 0x4003 C014) Table 348. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 11:2 EndofTable[1] The address above the last active address in the last active AF table. For compatibility 0 with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.8 Status registers The look-up table error status registers, the error addresses, and the flag register provide information if a programming error in the look-up table RAM during the ID screening was encountered. The look-up table error address and flag register have only read access. If an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides the UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 2 April 2014 © NXP B.V. 2014. All rights reserved. 388 of 849 NXP Semiconductors UM10360 Chapter 16: LPC176x/5x CAN1/2 information under which address during an ID screening an error in the look-up table was encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table interrupt. 16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018) Table 349. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description Bit Symbol Description 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10:2 LUTerrAd It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. 31:11 - Reserved, the value read from a reserved bit is not defined. Reset Value NA 0 NA 16.14.10 LUT Error register (LUTerr - 0x4003 C01C) Table 350. LUT Error register (LUTerr - address 0x4003 C01C) bit description Bit Symbol Description Reset Value 0 LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of 0 the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the “other CAN” interrupts from the CAN controllers, to produce the request that is connected to the NVIC. 31:1 - Reserved, the value read from a reserved bit is not defined. NA 16.14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020) A write access to the Global FullCAN Interrupt Enable register is only possible when the Acceptance Filter is in the off mode. Table 351. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description Bit Symbol Description 0 FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. 31:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Reset Value 0 NA 16.14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and FCANIC1 - 0x4003 C028) For detailed description on these two registers, see Section 16.16.2 “FullCAN interrupts”. Table 352. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description Bit Symbol Description Reset Value 0 IntPnd0 FullCan Interrupt Pending bit 0. 0 ... IntPndx (0