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TM4C123GH6PM手册

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TM4C123GH6PM,手册,关于寄存器的配置,有详细说明。

TEXAS INSTRUMENTS-PRODUCTION DATA Tiva™ TM4C123GH6PM Microcontroller DATA SHEET DS-TM4C123GH6PM-15842.2741 SPMS376E Copyright © 2007-2014 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/tm4c http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table of Contents Revision History ............................................................................................................................. 38 About This Document .................................................................................................................... 42 Audience .............................................................................................................................................. 42 About This Manual ................................................................................................................................ 42 Related Documents ............................................................................................................................... 42 Documentation Conventions .................................................................................................................. 43 1 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.4 1.5 1.6 Architectural Overview .......................................................................................... 45 Tiva™ C Series Overview .............................................................................................. 45 TM4C123GH6PM Microcontroller Overview .................................................................... 46 TM4C123GH6PM Microcontroller Features ..................................................................... 49 ARM Cortex-M4F Processor Core .................................................................................. 49 On-Chip Memory ........................................................................................................... 51 Serial Communications Peripherals ................................................................................ 53 System Integration ........................................................................................................ 57 Advanced Motion Control ............................................................................................... 63 Analog .......................................................................................................................... 65 JTAG and ARM Serial Wire Debug ................................................................................ 67 Packaging and Temperature .......................................................................................... 67 TM4C123GH6PM Microcontroller Hardware Details ........................................................ 68 Kits .............................................................................................................................. 68 Support Information ....................................................................................................... 68 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 The Cortex-M4F Processor ................................................................................... 69 Block Diagram .............................................................................................................. 70 Overview ...................................................................................................................... 71 System-Level Interface .................................................................................................. 71 Integrated Configurable Debug ...................................................................................... 71 Trace Port Interface Unit (TPIU) ..................................................................................... 72 Cortex-M4F System Component Details ......................................................................... 72 Programming Model ...................................................................................................... 73 Processor Mode and Privilege Levels for Software Execution ........................................... 73 Stacks .......................................................................................................................... 74 Register Map ................................................................................................................ 74 Register Descriptions .................................................................................................... 76 Exceptions and Interrupts .............................................................................................. 92 Data Types ................................................................................................................... 92 Memory Model .............................................................................................................. 92 Memory Regions, Types and Attributes ........................................................................... 95 Memory System Ordering of Memory Accesses .............................................................. 95 Behavior of Memory Accesses ....................................................................................... 95 Software Ordering of Memory Accesses ......................................................................... 96 Bit-Banding ................................................................................................................... 97 Data Storage ................................................................................................................ 99 Synchronization Primitives ........................................................................................... 100 Exception Model ......................................................................................................... 101 Exception States ......................................................................................................... 102 June 12, 2014 3 Texas Instruments-Production Data Table of Contents 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 3.4 3.5 3.6 3.7 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Exception Types .......................................................................................................... 102 Exception Handlers ..................................................................................................... 106 Vector Table ................................................................................................................ 106 Exception Priorities ...................................................................................................... 107 Interrupt Priority Grouping ............................................................................................ 108 Exception Entry and Return ......................................................................................... 108 Fault Handling ............................................................................................................. 111 Fault Types ................................................................................................................. 112 Fault Escalation and Hard Faults .................................................................................. 112 Fault Status Registers and Fault Address Registers ...................................................... 113 Lockup ....................................................................................................................... 113 Power Management .................................................................................................... 114 Entering Sleep Modes ................................................................................................. 114 Wake Up from Sleep Mode .......................................................................................... 114 Instruction Set Summary .............................................................................................. 115 Cortex-M4 Peripherals ......................................................................................... 122 Functional Description ................................................................................................. 122 System Timer (SysTick) ............................................................................................... 123 Nested Vectored Interrupt Controller (NVIC) .................................................................. 124 System Control Block (SCB) ........................................................................................ 125 Memory Protection Unit (MPU) ..................................................................................... 125 Floating-Point Unit (FPU) ............................................................................................. 130 Register Map .............................................................................................................. 134 System Timer (SysTick) Register Descriptions .............................................................. 137 NVIC Register Descriptions .......................................................................................... 141 System Control Block (SCB) Register Descriptions ........................................................ 156 Memory Protection Unit (MPU) Register Descriptions .................................................... 185 Floating-Point Unit (FPU) Register Descriptions ............................................................ 194 JTAG Interface ...................................................................................................... 200 Block Diagram ............................................................................................................ 201 Signal Description ....................................................................................................... 201 Functional Description ................................................................................................. 202 JTAG Interface Pins ..................................................................................................... 202 JTAG TAP Controller ................................................................................................... 204 Shift Registers ............................................................................................................ 204 Operational Considerations .......................................................................................... 205 Initialization and Configuration ..................................................................................... 207 Register Descriptions .................................................................................................. 208 Instruction Register (IR) ............................................................................................... 208 Data Registers ............................................................................................................ 210 System Control ..................................................................................................... 212 Signal Description ....................................................................................................... 212 Functional Description ................................................................................................. 212 Device Identification .................................................................................................... 212 Reset Control .............................................................................................................. 213 Non-Maskable Interrupt ............................................................................................... 218 Power Control ............................................................................................................. 218 Clock Control .............................................................................................................. 219 4 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.6 5.3 5.4 5.5 5.6 System Control ........................................................................................................... 227 Initialization and Configuration ..................................................................................... 231 Register Map .............................................................................................................. 231 System Control Register Descriptions ........................................................................... 237 System Control Legacy Register Descriptions ............................................................... 424 6 System Exception Module ................................................................................... 485 6.1 Functional Description ................................................................................................. 485 6.2 Register Map .............................................................................................................. 485 6.3 Register Descriptions .................................................................................................. 485 7 Hibernation Module .............................................................................................. 493 7.1 Block Diagram ............................................................................................................ 494 7.2 Signal Description ....................................................................................................... 494 7.3 Functional Description ................................................................................................. 495 7.3.1 Register Access Timing ............................................................................................... 495 7.3.2 Hibernation Clock Source ............................................................................................ 496 7.3.3 System Implementation ............................................................................................... 497 7.3.4 Battery Management ................................................................................................... 498 7.3.5 Real-Time Clock .......................................................................................................... 499 7.3.6 Battery-Backed Memory .............................................................................................. 501 7.3.7 Power Control Using HIB ............................................................................................. 501 7.3.8 Power Control Using VDD3ON Mode ........................................................................... 501 7.3.9 Initiating Hibernate ...................................................................................................... 501 7.3.10 Waking from Hibernate ................................................................................................ 501 7.3.11 Arbitrary Power Removal ............................................................................................. 502 7.3.12 Interrupts and Status ................................................................................................... 502 7.4 Initialization and Configuration ..................................................................................... 503 7.4.1 Initialization ................................................................................................................. 503 7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 504 7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 504 7.4.4 External Wake-Up from Hibernation .............................................................................. 504 7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 505 7.5 Register Map .............................................................................................................. 505 7.6 Register Descriptions .................................................................................................. 506 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.4 8.5 8.6 Internal Memory ................................................................................................... 524 Block Diagram ............................................................................................................ 524 Functional Description ................................................................................................. 525 SRAM ........................................................................................................................ 525 ROM .......................................................................................................................... 526 Flash Memory ............................................................................................................. 528 EEPROM .................................................................................................................... 534 Register Map .............................................................................................................. 540 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 541 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 559 Memory Register Descriptions (System Control Offset) .................................................. 576 9 Micro Direct Memory Access (μDMA) ................................................................ 585 9.1 Block Diagram ............................................................................................................ 586 9.2 Functional Description ................................................................................................. 586 June 12, 2014 5 Texas Instruments-Production Data Table of Contents 9.2.1 Channel Assignments .................................................................................................. 587 9.2.2 Priority ........................................................................................................................ 588 9.2.3 Arbitration Size ............................................................................................................ 588 9.2.4 Request Types ............................................................................................................ 588 9.2.5 Channel Configuration ................................................................................................. 589 9.2.6 Transfer Modes ........................................................................................................... 591 9.2.7 Transfer Size and Increment ........................................................................................ 599 9.2.8 Peripheral Interface ..................................................................................................... 599 9.2.9 Software Request ........................................................................................................ 599 9.2.10 Interrupts and Errors .................................................................................................... 600 9.3 Initialization and Configuration ..................................................................................... 600 9.3.1 Module Initialization ..................................................................................................... 600 9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 601 9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 602 9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 604 9.3.5 Configuring Channel Assignments ................................................................................ 606 9.4 Register Map .............................................................................................................. 606 9.5 μDMA Channel Control Structure ................................................................................. 608 9.6 μDMA Register Descriptions ........................................................................................ 615 10 General-Purpose Input/Outputs (GPIOs) ........................................................... 649 10.1 Signal Description ....................................................................................................... 649 10.2 Functional Description ................................................................................................. 652 10.2.1 Data Control ............................................................................................................... 653 10.2.2 Interrupt Control .......................................................................................................... 654 10.2.3 Mode Control .............................................................................................................. 655 10.2.4 Commit Control ........................................................................................................... 656 10.2.5 Pad Control ................................................................................................................. 656 10.2.6 Identification ............................................................................................................... 656 10.3 Initialization and Configuration ..................................................................................... 656 10.4 Register Map .............................................................................................................. 658 10.5 Register Descriptions .................................................................................................. 661 11 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 General-Purpose Timers ...................................................................................... 704 Block Diagram ............................................................................................................ 705 Signal Description ....................................................................................................... 706 Functional Description ................................................................................................. 707 GPTM Reset Conditions .............................................................................................. 708 Timer Modes ............................................................................................................... 709 Wait-for-Trigger Mode .................................................................................................. 718 Synchronizing GP Timer Blocks ................................................................................... 719 DMA Operation ........................................................................................................... 720 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 720 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 720 Initialization and Configuration ..................................................................................... 722 One-Shot/Periodic Timer Mode .................................................................................... 722 Real-Time Clock (RTC) Mode ...................................................................................... 723 Input Edge-Count Mode ............................................................................................... 723 Input Edge Time Mode ................................................................................................. 724 PWM Mode ................................................................................................................. 724 6 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 11.5 Register Map .............................................................................................................. 725 11.6 Register Descriptions .................................................................................................. 726 12 Watchdog Timers ................................................................................................. 774 12.1 Block Diagram ............................................................................................................ 775 12.2 Functional Description ................................................................................................. 775 12.2.1 Register Access Timing ............................................................................................... 776 12.3 Initialization and Configuration ..................................................................................... 776 12.4 Register Map .............................................................................................................. 776 12.5 Register Descriptions .................................................................................................. 777 13 Analog-to-Digital Converter (ADC) ..................................................................... 799 13.1 Block Diagram ............................................................................................................ 800 13.2 Signal Description ....................................................................................................... 801 13.3 Functional Description ................................................................................................. 802 13.3.1 Sample Sequencers .................................................................................................... 802 13.3.2 Module Control ............................................................................................................ 803 13.3.3 Hardware Sample Averaging Circuit ............................................................................. 807 13.3.4 Analog-to-Digital Converter .......................................................................................... 807 13.3.5 Differential Sampling ................................................................................................... 810 13.3.6 Internal Temperature Sensor ........................................................................................ 812 13.3.7 Digital Comparator Unit ............................................................................................... 813 13.4 Initialization and Configuration ..................................................................................... 817 13.4.1 Module Initialization ..................................................................................................... 817 13.4.2 Sample Sequencer Configuration ................................................................................. 818 13.5 Register Map .............................................................................................................. 818 13.6 Register Descriptions .................................................................................................. 820 14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 893 14.1 Block Diagram ............................................................................................................ 894 14.2 Signal Description ....................................................................................................... 894 14.3 Functional Description ................................................................................................. 895 14.3.1 Transmit/Receive Logic ............................................................................................... 895 14.3.2 Baud-Rate Generation ................................................................................................. 896 14.3.3 Data Transmission ...................................................................................................... 897 14.3.4 Serial IR (SIR) ............................................................................................................. 897 14.3.5 ISO 7816 Support ....................................................................................................... 898 14.3.6 Modem Handshake Support ......................................................................................... 899 14.3.7 9-Bit UART Mode ........................................................................................................ 900 14.3.8 FIFO Operation ........................................................................................................... 900 14.3.9 Interrupts .................................................................................................................... 900 14.3.10 Loopback Operation .................................................................................................... 901 14.3.11 DMA Operation ........................................................................................................... 902 14.4 Initialization and Configuration ..................................................................................... 902 14.5 Register Map .............................................................................................................. 903 14.6 Register Descriptions .................................................................................................. 905 15 Synchronous Serial Interface (SSI) .................................................................... 952 15.1 Block Diagram ............................................................................................................ 953 15.2 Signal Description ....................................................................................................... 953 15.3 Functional Description ................................................................................................. 954 June 12, 2014 7 Texas Instruments-Production Data Table of Contents 15.3.1 Bit Rate Generation ..................................................................................................... 954 15.3.2 FIFO Operation ........................................................................................................... 955 15.3.3 Interrupts .................................................................................................................... 955 15.3.4 Frame Formats ........................................................................................................... 956 15.3.5 DMA Operation ........................................................................................................... 964 15.4 Initialization and Configuration ..................................................................................... 965 15.5 Register Map .............................................................................................................. 967 15.6 Register Descriptions .................................................................................................. 968 16 Inter-Integrated Circuit (I2C) Interface ................................................................ 997 16.1 Block Diagram ............................................................................................................ 998 16.2 Signal Description ....................................................................................................... 998 16.3 Functional Description ................................................................................................. 999 16.3.1 I2C Bus Functional Overview ........................................................................................ 999 16.3.2 Available Speed Modes ............................................................................................. 1003 16.3.3 Interrupts .................................................................................................................. 1005 16.3.4 Loopback Operation .................................................................................................. 1006 16.3.5 Command Sequence Flow Charts .............................................................................. 1007 16.4 Initialization and Configuration .................................................................................... 1015 16.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 1015 16.4.2 Configure the I2C Master to High Speed Mode ............................................................ 1016 16.5 Register Map ............................................................................................................ 1017 16.6 Register Descriptions (I2C Master) .............................................................................. 1018 16.7 Register Descriptions (I2C Slave) ............................................................................... 1035 16.8 Register Descriptions (I2C Status and Control) ............................................................ 1045 17 Controller Area Network (CAN) Module ........................................................... 1048 17.1 Block Diagram ........................................................................................................... 1049 17.2 Signal Description ..................................................................................................... 1049 17.3 Functional Description ............................................................................................... 1050 17.3.1 Initialization ............................................................................................................... 1051 17.3.2 Operation .................................................................................................................. 1051 17.3.3 Transmitting Message Objects ................................................................................... 1052 17.3.4 Configuring a Transmit Message Object ...................................................................... 1053 17.3.5 Updating a Transmit Message Object ......................................................................... 1054 17.3.6 Accepting Received Message Objects ........................................................................ 1054 17.3.7 Receiving a Data Frame ............................................................................................ 1055 17.3.8 Receiving a Remote Frame ........................................................................................ 1055 17.3.9 Receive/Transmit Priority ........................................................................................... 1056 17.3.10 Configuring a Receive Message Object ...................................................................... 1056 17.3.11 Handling of Received Message Objects ...................................................................... 1057 17.3.12 Handling of Interrupts ................................................................................................ 1059 17.3.13 Test Mode ................................................................................................................. 1060 17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1062 17.3.15 Bit Time and Bit Rate ................................................................................................. 1062 17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1064 17.4 Register Map ............................................................................................................ 1067 17.5 CAN Register Descriptions ......................................................................................... 1068 8 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 18 Universal Serial Bus (USB) Controller ............................................................. 1099 18.1 Block Diagram ........................................................................................................... 1100 18.2 Signal Description ..................................................................................................... 1100 18.3 Functional Description ............................................................................................... 1101 18.3.1 Operation as a Device ............................................................................................... 1101 18.3.2 Operation as a Host ................................................................................................... 1107 18.3.3 OTG Mode ................................................................................................................ 1110 18.3.4 DMA Operation ......................................................................................................... 1112 18.4 Initialization and Configuration .................................................................................... 1113 18.4.1 Pin Configuration ....................................................................................................... 1113 18.4.2 Endpoint Configuration .............................................................................................. 1114 18.5 Register Map ............................................................................................................ 1114 18.6 Register Descriptions ................................................................................................. 1120 19 Analog Comparators .......................................................................................... 1215 19.1 Block Diagram ........................................................................................................... 1216 19.2 Signal Description ..................................................................................................... 1216 19.3 Functional Description ............................................................................................... 1217 19.3.1 Internal Reference Programming ................................................................................ 1218 19.4 Initialization and Configuration .................................................................................... 1220 19.5 Register Map ............................................................................................................ 1220 19.6 Register Descriptions ................................................................................................. 1221 20 Pulse Width Modulator (PWM) .......................................................................... 1230 20.1 Block Diagram ........................................................................................................... 1231 20.2 Signal Description ..................................................................................................... 1233 20.3 Functional Description ............................................................................................... 1234 20.3.1 Clock Configuration ................................................................................................... 1234 20.3.2 PWM Timer ............................................................................................................... 1234 20.3.3 PWM Comparators .................................................................................................... 1234 20.3.4 PWM Signal Generator .............................................................................................. 1235 20.3.5 Dead-Band Generator ............................................................................................... 1236 20.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 1236 20.3.7 Synchronization Methods .......................................................................................... 1237 20.3.8 Fault Conditions ........................................................................................................ 1238 20.3.9 Output Control Block .................................................................................................. 1239 20.4 Initialization and Configuration .................................................................................... 1239 20.5 Register Map ............................................................................................................ 1240 20.6 Register Descriptions ................................................................................................. 1243 21 Quadrature Encoder Interface (QEI) ................................................................. 1305 21.1 Block Diagram ........................................................................................................... 1305 21.2 Signal Description ..................................................................................................... 1307 21.3 Functional Description ............................................................................................... 1308 21.4 Initialization and Configuration .................................................................................... 1310 21.5 Register Map ............................................................................................................ 1310 21.6 Register Descriptions ................................................................................................. 1311 22 Pin Diagram ........................................................................................................ 1328 23 Signal Tables ...................................................................................................... 1329 23.1 Signals by Pin Number .............................................................................................. 1330 June 12, 2014 9 Texas Instruments-Production Data Table of Contents 23.2 Signals by Signal Name ............................................................................................. 1337 23.3 Signals by Function, Except for GPIO ......................................................................... 1344 23.4 GPIO Pins and Alternate Functions ............................................................................ 1351 23.5 Possible Pin Assignments for Alternate Functions ....................................................... 1353 23.6 Connections for Unused Signals ................................................................................. 1356 24 Electrical Characteristics .................................................................................. 1358 24.1 Maximum Ratings ...................................................................................................... 1358 24.2 Operating Characteristics ........................................................................................... 1359 24.3 Recommended Operating Conditions ......................................................................... 1360 24.4 Load Conditions ........................................................................................................ 1362 24.5 JTAG and Boundary Scan .......................................................................................... 1363 24.6 Power and Brown-Out ............................................................................................... 1365 24.6.1 VDDA Levels ............................................................................................................ 1365 24.6.2 VDD Levels ............................................................................................................... 1366 24.6.3 VDDC Levels ............................................................................................................ 1367 24.6.4 VDD Glitches ............................................................................................................ 1368 24.6.5 VDD Droop Response ............................................................................................... 1368 24.7 Reset ........................................................................................................................ 1370 24.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1373 24.9 Clocks ...................................................................................................................... 1374 24.9.1 PLL Specifications ..................................................................................................... 1374 24.9.2 PIOSC Specifications ................................................................................................ 1375 24.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1375 24.9.4 Hibernation Clock Source Specifications ..................................................................... 1375 24.9.5 Main Oscillator Specifications ..................................................................................... 1376 24.9.6 System Clock Specification with ADC Operation .......................................................... 1380 24.9.7 System Clock Specification with USB Operation .......................................................... 1380 24.10 Sleep Modes ............................................................................................................. 1381 24.11 Hibernation Module ................................................................................................... 1383 24.12 Flash Memory and EEPROM ..................................................................................... 1384 24.13 Input/Output Pin Characteristics ................................................................................. 1385 24.13.1 GPIO Module Characteristics ..................................................................................... 1385 24.13.2 Types of I/O Pins and ESD Protection ......................................................................... 1385 24.14 Analog-to-Digital Converter (ADC) .............................................................................. 1389 24.15 Synchronous Serial Interface (SSI) ............................................................................. 1392 24.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1395 24.17 Universal Serial Bus (USB) Controller ......................................................................... 1396 24.18 Analog Comparator ................................................................................................... 1397 24.19 Pulse-Width Modulator (PWM) ................................................................................... 1398 24.20 Current Consumption ................................................................................................. 1399 A Package Information .......................................................................................... 1402 A.1 Orderable Devices ..................................................................................................... 1402 A.2 Device Nomenclature ................................................................................................ 1402 A.3 Device Markings ........................................................................................................ 1403 A.4 Packaging Diagram ................................................................................................... 1404 10 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 8-1. Figure 8-2. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Tiva™ TM4C123GH6PM Microcontroller High-Level Block Diagram ........................ 48 CPU Block Diagram ............................................................................................. 71 TPIU Block Diagram ............................................................................................ 72 Cortex-M4F Register Set ...................................................................................... 75 Bit-Band Mapping ................................................................................................ 99 Data Storage ..................................................................................................... 100 Vector Table ...................................................................................................... 107 Exception Stack Frame ...................................................................................... 110 SRD Use Example ............................................................................................. 128 FPU Register Bank ............................................................................................ 131 JTAG Module Block Diagram .............................................................................. 201 Test Access Port State Machine ......................................................................... 204 IDCODE Register Format ................................................................................... 210 BYPASS Register Format ................................................................................... 210 Boundary Scan Register Format ......................................................................... 211 Basic RST Configuration .................................................................................... 215 External Circuitry to Extend Power-On Reset ....................................................... 215 Reset Circuit Controlled by Switch ...................................................................... 216 Power Architecture ............................................................................................ 219 Main Clock Tree ................................................................................................ 222 Module Clock Selection ...................................................................................... 229 Hibernation Module Block Diagram ..................................................................... 494 Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 496 Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 497 Using a Regulator for Both VDD and VBAT ............................................................ 498 Counter Behavior with a TRIM Value of 0x8002 ................................................... 500 Counter Behavior with a TRIM Value of 0x7FFC .................................................. 500 Internal Memory Block Diagram .......................................................................... 524 EEPROM Block Diagram ................................................................................... 525 μDMA Block Diagram ......................................................................................... 586 Example of Ping-Pong μDMA Transaction ........................................................... 592 Memory Scatter-Gather, Setup and Configuration ................................................ 594 Memory Scatter-Gather, μDMA Copy Sequence .................................................. 595 Peripheral Scatter-Gather, Setup and Configuration ............................................. 597 Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 598 Digital I/O Pads ................................................................................................. 652 Analog/Digital I/O Pads ...................................................................................... 653 GPIODATA Write Example ................................................................................. 654 GPIODATA Read Example ................................................................................. 654 GPTM Module Block Diagram ............................................................................ 705 Reading the RTC Value ...................................................................................... 712 Input Edge-Count Mode Example, Counting Down ............................................... 714 16-Bit Input Edge-Time Mode Example ............................................................... 715 16-Bit PWM Mode Example ................................................................................ 717 CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 717 June 12, 2014 11 Texas Instruments-Production Data Table of Contents Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 718 Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 718 Figure 11-9. Timer Daisy Chain ............................................................................................. 719 Figure 12-1. WDT Module Block Diagram .............................................................................. 775 Figure 13-1. Implementation of Two ADC Blocks .................................................................... 800 Figure 13-2. ADC Module Block Diagram ............................................................................... 801 Figure 13-3. ADC Sample Phases ......................................................................................... 804 Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 805 Figure 13-5. Skewed Sampling .............................................................................................. 806 Figure 13-6. Sample Averaging Example ............................................................................... 807 Figure 13-7. ADC Input Equivalency ...................................................................................... 808 Figure 13-8. ADC Voltage Reference ..................................................................................... 809 Figure 13-9. ADC Conversion Result ..................................................................................... 810 Figure 13-10. Differential Voltage Representation ..................................................................... 812 Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 813 Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 815 Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 816 Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 817 Figure 14-1. UART Module Block Diagram ............................................................................. 894 Figure 14-2. UART Character Frame ..................................................................................... 896 Figure 14-3. IrDA Data Modulation ......................................................................................... 898 Figure 15-1. SSI Module Block Diagram ................................................................................. 953 Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 957 Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 958 Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 959 Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 959 Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 960 Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 961 Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 961 Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 962 Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 963 Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 964 Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 964 Figure 16-1. I2C Block Diagram ............................................................................................. 998 Figure 16-2. I2C Bus Configuration ........................................................................................ 999 Figure 16-3. START and STOP Conditions ............................................................................. 999 Figure 16-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1000 Figure 16-5. R/S Bit in First Byte .......................................................................................... 1000 Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1001 Figure 16-7. High-Speed Data Format .................................................................................. 1005 Figure 16-8. Master Single TRANSMIT ................................................................................ 1008 Figure 16-9. Master Single RECEIVE ................................................................................... 1009 Figure 16-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1010 Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1011 Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1012 Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1013 Figure 16-14. Standard High Speed Mode Master Transmit ..................................................... 1014 Figure 16-15. Slave Command Sequence .............................................................................. 1015 12 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Figure 17-1. CAN Controller Block Diagram .......................................................................... 1049 Figure 17-2. CAN Data/Remote Frame ................................................................................. 1050 Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1059 Figure 17-4. CAN Bit Time ................................................................................................... 1063 Figure 18-1. USB Module Block Diagram ............................................................................. 1100 Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1216 Figure 19-2. Structure of Comparator Unit ............................................................................ 1217 Figure 19-3. Comparator Internal Reference Structure .......................................................... 1218 Figure 20-1. PWM Module Diagram ..................................................................................... 1232 Figure 20-2. PWM Generator Block Diagram ........................................................................ 1232 Figure 20-3. PWM Count-Down Mode .................................................................................. 1235 Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1235 Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1236 Figure 20-6. PWM Dead-Band Generator ............................................................................. 1236 Figure 21-1. QEI Block Diagram .......................................................................................... 1306 Figure 21-2. QEI Input Signal Logic ...................................................................................... 1307 Figure 21-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1309 Figure 22-1. 64-Pin LQFP Package Pin Diagram .................................................................. 1328 Figure 24-1. Load Conditions ............................................................................................... 1362 Figure 24-2. JTAG Test Clock Input Timing ........................................................................... 1363 Figure 24-3. JTAG Test Access Port (TAP) Timing ................................................................ 1364 Figure 24-4. Power Assertions versus VDDA Levels ............................................................. 1366 Figure 24-5. Power and Brown-Out Assertions versus VDD Levels ........................................ 1367 Figure 24-6. POK assertion vs VDDC ................................................................................... 1368 Figure 24-7. POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1368 Figure 24-8. POR-BOR0-BOR1 VDD Droop Response ......................................................... 1369 Figure 24-9. Digital Power-On Reset Timing ......................................................................... 1370 Figure 24-10. Brown-Out Reset Timing .................................................................................. 1371 Figure 24-11. External Reset Timing (RST) ............................................................................ 1371 Figure 24-12. Software Reset Timing ..................................................................................... 1371 Figure 24-13. Watchdog Reset Timing ................................................................................... 1371 Figure 24-14. MOSC Failure Reset Timing ............................................................................. 1372 Figure 24-15. Hibernation Module Timing ............................................................................... 1383 Figure 24-16. ESD Protection on Fail-Safe Pins ...................................................................... 1386 Figure 24-17. ESD Protection on Non-Fail-Safe Pins .............................................................. 1387 Figure 24-18. ADC Input Equivalency Diagram ....................................................................... 1391 Figure 24-19. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................. 1393 Figure 24-20. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1393 Figure 24-21. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1394 Figure 24-22. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1394 Figure 24-23. I2C Timing ....................................................................................................... 1395 Figure A-1. Key to Part Numbers ........................................................................................ 1402 Figure A-2. TM4C123GH6PM 64-Pin LQFP Package Diagram ............................................. 1404 June 12, 2014 13 Texas Instruments-Production Data Table of Contents List of Tables Table 1. Table 2. Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Revision History .................................................................................................. 38 Documentation Conventions ................................................................................ 43 TM4C123GH6PM Microcontroller Features ........................................................... 46 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 74 Processor Register Map ....................................................................................... 75 PSR Register Combinations ................................................................................. 81 Memory Map ....................................................................................................... 92 Memory Access Behavior ..................................................................................... 95 SRAM Memory Bit-Banding Regions .................................................................... 97 Peripheral Memory Bit-Banding Regions ............................................................... 98 Exception Types ................................................................................................ 103 Interrupts .......................................................................................................... 104 Exception Return Behavior ................................................................................. 111 Faults ............................................................................................................... 112 Fault Status and Fault Address Registers ............................................................ 113 Cortex-M4F Instruction Summary ....................................................................... 115 Core Peripheral Register Regions ....................................................................... 122 Memory Attributes Summary .............................................................................. 126 TEX, S, C, and B Bit Field Encoding ................................................................... 128 Cache Policy for Memory Attribute Encoding ....................................................... 129 AP Bit Field Encoding ........................................................................................ 129 Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 130 QNaN and SNaN Handling ................................................................................. 133 Peripherals Register Map ................................................................................... 134 Interrupt Priority Levels ...................................................................................... 164 Example SIZE Field Values ................................................................................ 192 JTAG_SWD_SWO Signals (64LQFP) ................................................................. 201 JTAG Port Pins State after Power-On Reset or RST assertion .............................. 202 JTAG Instruction Register Commands ................................................................. 208 System Control & Clocks Signals (64LQFP) ........................................................ 212 Reset Sources ................................................................................................... 213 Clock Source Options ........................................................................................ 220 Possible System Clock Frequencies Using the SYSDIV Field ............................... 223 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 223 Examples of Possible System Clock Frequencies with DIV400=1 ......................... 224 System Control Register Map ............................................................................. 232 RCC2 Fields that Override RCC Fields ............................................................... 260 System Exception Register Map ......................................................................... 485 Hibernate Signals (64LQFP) ............................................................................... 494 Hibernation Module Clock Operation ................................................................... 503 Hibernation Module Register Map ....................................................................... 505 Flash Memory Protection Policy Combinations .................................................... 529 User-Programmable Flash Memory Resident Registers ....................................... 533 Flash Register Map ............................................................................................ 540 μDMA Channel Assignments .............................................................................. 587 Request Type Support ....................................................................................... 589 14 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12. Table 9-13. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 10-5. Table 10-6. Table 10-7. Table 10-8. Table 10-9. Table 10-10. Table 10-11. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 11-6. Table 11-7. Table 11-8. Table 11-9. Table 11-10. Table 11-11. Table 11-12. Table 12-1. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 14-1. Table 14-2. Table 14-3. Table 15-1. Table 15-2. Table 16-1. Table 16-2. Table 16-3. Control Structure Memory Map ........................................................................... 590 Channel Control Structure .................................................................................. 590 μDMA Read Example: 8-Bit Peripheral ................................................................ 599 μDMA Interrupt Assignments .............................................................................. 600 Channel Control Structure Offsets for Channel 30 ................................................ 601 Channel Control Word Configuration for Memory Transfer Example ...................... 602 Channel Control Structure Offsets for Channel 7 .................................................. 603 Channel Control Word Configuration for Peripheral Transmit Example .................. 603 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 604 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 605 μDMA Register Map .......................................................................................... 607 GPIO Pins With Special Considerations .............................................................. 650 GPIO Pins and Alternate Functions (64LQFP) ..................................................... 650 GPIO Pad Configuration Examples ..................................................................... 657 GPIO Interrupt Configuration Example ................................................................ 658 GPIO Pins With Special Considerations .............................................................. 659 GPIO Register Map ........................................................................................... 660 GPIO Pins With Special Considerations .............................................................. 671 GPIO Pins With Special Considerations .............................................................. 677 GPIO Pins With Special Considerations .............................................................. 679 GPIO Pins With Special Considerations .............................................................. 682 GPIO Pins With Special Considerations .............................................................. 688 Available CCP Pins ............................................................................................ 706 General-Purpose Timers Signals (64LQFP) ......................................................... 706 General-Purpose Timer Capabilities .................................................................... 708 Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 709 16-Bit Timer With Prescaler Configurations ......................................................... 710 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 711 Counter Values When the Timer is Enabled in RTC Mode .................................... 711 Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 713 Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 714 Counter Values When the Timer is Enabled in PWM Mode ................................... 716 Timeout Actions for GPTM Modes ...................................................................... 719 Timers Register Map .......................................................................................... 726 Watchdog Timers Register Map .......................................................................... 777 ADC Signals (64LQFP) ...................................................................................... 801 Samples and FIFO Depth of Sequencers ............................................................ 802 Differential Sampling Pairs ................................................................................. 810 ADC Register Map ............................................................................................. 818 UART Signals (64LQFP) .................................................................................... 895 Flow Control Mode ............................................................................................. 899 UART Register Map ........................................................................................... 904 SSI Signals (64LQFP) ........................................................................................ 954 SSI Register Map .............................................................................................. 967 I2C Signals (64LQFP) ........................................................................................ 998 Examples of I2C Master Timer Period Versus Speed Mode ................................. 1004 Examples of I2C Master Timer Period in High-Speed Mode ................................ 1005 June 12, 2014 15 Texas Instruments-Production Data Table of Contents Table 16-4. Table 16-5. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 20-1. Table 20-2. Table 21-1. Table 21-2. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Table 24-1. Table 24-2. Table 24-3. Table 24-4. Table 24-5. Table 24-6. Table 24-7. Table 24-8. Table 24-9. Table 24-10. Table 24-11. Table 24-12. Table 24-13. Table 24-14. Table 24-15. Table 24-16. Table 24-17. Table 24-18. Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1017 Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1023 Controller Area Network Signals (64LQFP) ........................................................ 1050 Message Object Configurations ........................................................................ 1055 CAN Protocol Ranges ...................................................................................... 1063 CANBIT Register Values .................................................................................. 1063 CAN Register Map ........................................................................................... 1067 USB Signals (64LQFP) .................................................................................... 1101 Remainder (MAXLOAD/4) ................................................................................ 1112 Actual Bytes Read ........................................................................................... 1112 Packet Sizes That Clear RXRDY ...................................................................... 1113 Universal Serial Bus (USB) Controller Register Map ........................................... 1114 Analog Comparators Signals (64LQFP) ............................................................. 1216 Internal Reference Voltage and ACREFCTL Field Values ................................... 1218 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1219 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1219 Analog Comparators Register Map ................................................................... 1220 PWM Signals (64LQFP) ................................................................................... 1233 PWM Register Map .......................................................................................... 1240 QEI Signals (64LQFP) ...................................................................................... 1307 QEI Register Map ............................................................................................ 1311 GPIO Pins With Special Considerations ............................................................ 1329 Signals by Pin Number ..................................................................................... 1330 Signals by Signal Name ................................................................................... 1337 Signals by Function, Except for GPIO ............................................................... 1344 GPIO Pins and Alternate Functions ................................................................... 1351 Possible Pin Assignments for Alternate Functions .............................................. 1353 Connections for Unused Signals (64-Pin LQFP) ................................................. 1356 Absolute Maximum Ratings .............................................................................. 1358 ESD Absolute Maximum Ratings ...................................................................... 1358 Temperature Characteristics ............................................................................. 1359 Thermal Characteristics ................................................................................... 1359 Recommended DC Operating Conditions .......................................................... 1360 Recommended GPIO Pad Operating Conditions ................................................ 1360 GPIO Current Restrictions ................................................................................ 1360 GPIO Package Side Assignments ..................................................................... 1361 JTAG Characteristics ....................................................................................... 1363 Power-On and Brown-Out Levels ...................................................................... 1365 Reset Characteristics ....................................................................................... 1370 LDO Regulator Characteristics ......................................................................... 1373 Phase Locked Loop (PLL) Characteristics ......................................................... 1374 Actual PLL Frequency ...................................................................................... 1374 PIOSC Clock Characteristics ............................................................................ 1375 Low-Frequency internal Oscillator Characteristics .............................................. 1375 Hibernation Oscillator Input Characteristics ........................................................ 1375 Main Oscillator Input Characteristics ................................................................. 1376 16 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 24-19. Table 24-20. Table 24-21. Table 24-22. Table 24-23. Table 24-24. Table 24-25. Table 24-26. Table 24-27. Table 24-28. Table 24-29. Table 24-30. Table 24-31. Table 24-32. Table 24-33. Table 24-34. Table 24-35. Table 24-36. Table 24-37. Table 24-38. Table 24-39. Table 24-40. Table 24-41. Crystal Parameters .......................................................................................... 1378 Supported MOSC Crystal Frequencies .............................................................. 1379 System Clock Characteristics with ADC Operation ............................................. 1380 System Clock Characteristics with USB Operation ............................................. 1380 Sleep Modes AC Characteristics ....................................................................... 1381 Time to Wake with Respect to Low-Power Modes .............................................. 1381 Hibernation Module Battery Characteristics ....................................................... 1383 Hibernation Module AC Characteristics ............................................................. 1383 Flash Memory Characteristics ........................................................................... 1384 EEPROM Characteristics ................................................................................. 1384 GPIO Module Characteristics ............................................................................ 1385 Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1386 Fail-Safe GPIOs that Require an External Pull-up .............................................. 1387 Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1387 ADC Electrical Characteristics .......................................................................... 1389 SSI Characteristics .......................................................................................... 1392 I2C Characteristics ........................................................................................... 1395 Analog Comparator Characteristics ................................................................... 1397 Analog Comparator Voltage Reference Characteristics ...................................... 1397 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1397 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1398 PWM Timing Characteristics ............................................................................. 1398 Current Consumption ....................................................................................... 1399 June 12, 2014 17 Texas Instruments-Production Data Table of Contents List of Registers The Cortex-M4F Processor ........................................................................................................... 69 Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 77 Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 77 Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 77 Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 77 Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 77 Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 77 Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 77 Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 77 Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 77 Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 77 Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 77 Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 77 Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 77 Register 14: Stack Pointer (SP) ........................................................................................................... 78 Register 15: Link Register (LR) ............................................................................................................ 79 Register 16: Program Counter (PC) ..................................................................................................... 80 Register 17: Program Status Register (PSR) ........................................................................................ 81 Register 18: Priority Mask Register (PRIMASK) .................................................................................... 85 Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 86 Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 87 Register 21: Control Register (CONTROL) ........................................................................................... 88 Register 22: Floating-Point Status Control (FPSC) ................................................................................ 90 Cortex-M4 Peripherals ................................................................................................................. 122 Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 138 Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 140 Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 141 Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 142 Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 142 Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 142 Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 142 Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 143 Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 144 Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 144 Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 144 Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 144 Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 145 Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 146 Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 146 Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 146 Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 146 Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 147 Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 148 Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 148 Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 148 18 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 148 Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 149 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 150 Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 150 Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 150 Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 150 Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 151 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 152 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 152 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 152 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 152 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 152 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 152 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 152 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 152 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 152 Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 152 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 152 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 152 Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 152 Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 152 Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 152 Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 152 Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 154 Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 154 Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 154 Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 154 Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 154 Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 154 Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 154 Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 154 Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 154 Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 154 Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 154 Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 154 Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 154 Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 154 Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 154 Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 154 Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 154 Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 154 Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 154 Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 156 Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 157 CPU ID Base (CPUID), offset 0xD00 ............................................................................... 159 Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 160 Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 163 Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 164 June 12, 2014 19 Texas Instruments-Production Data Table of Contents Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: Register 90: Register 91: Register 92: Register 93: Register 94: System Control (SYSCTRL), offset 0xD10 ....................................................................... 166 Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 168 System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 170 System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 171 System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 172 System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 173 Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 177 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 183 Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 184 Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 185 MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 186 MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 187 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 189 MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 190 MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 190 MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 190 MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 190 MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 192 MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 192 MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 192 MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 192 Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 195 Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 196 Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 198 Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 199 System Control ............................................................................................................................ 212 Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 238 Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 240 Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 243 Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 244 Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 247 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 249 Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 252 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 254 Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 258 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 260 Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 263 Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 264 Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 266 Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 268 Register 15: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 270 Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 271 Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 272 Register 18: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 273 Register 19: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 274 Register 20: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 276 Register 21: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 278 Register 22: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 280 20 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 281 LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 283 Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 284 Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 287 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 288 General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 290 Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 293 Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 294 Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset 0x318 ........................................................................................................................... 295 Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 297 Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 299 Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 301 Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 302 Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 303 Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 304 Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 305 Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 306 EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 307 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 308 Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 310 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 312 General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 314 Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 316 Hibernation Software Reset (SRHIB), offset 0x514 ........................................................... 317 Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 318 Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 320 Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 322 Universal Serial Bus Software Reset (SRUSB), offset 0x528 ............................................ 324 Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 325 Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 327 Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 329 Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 330 Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 332 EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 334 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C .......... 335 Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 337 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset 0x604 ........................................................................................................................... 338 General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset 0x608 ........................................................................................................................... 340 Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset 0x60C ........................................................................................................................... 342 Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 343 Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), offset 0x618 .................................................................................................................. 344 Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset 0x61C ........................................................................................................................... 346 Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 348 June 12, 2014 21 Texas Instruments-Production Data Table of Contents Register 66: Register 67: Register 68: Register 69: Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: Register 90: Register 91: Register 92: Register 93: Register 94: Register 95: Register 96: Register 97: Register 98: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 ............... 350 Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 351 Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 352 Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 353 Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 354 Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset 0x644 ........................................................................................................................... 355 EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 356 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER), offset 0x65C .................................................................................................................. 357 Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 359 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset 0x704 ........................................................................................................................... 360 General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset 0x708 ........................................................................................................................... 362 Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset 0x70C ........................................................................................................................... 364 Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 365 Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART), offset 0x718 ............................................................................................ 366 Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset 0x71C ........................................................................................................................... 368 Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 370 Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 ............. 372 Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 373 Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset 0x738 ........................................................................................................................... 374 Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 375 Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 376 Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset 0x744 ........................................................................................................................... 377 EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 378 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER), offset 0x75C .................................................................................................................. 379 Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 381 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER), offset 0x804 .................................................................................................................. 382 General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset 0x808 ........................................................................................................................... 384 Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset 0x80C ........................................................................................................................... 386 Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 387 Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART), offset 0x818 ............................................................................................ 388 Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset 0x81C ........................................................................................................................... 390 Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset 0x820 ........................................................................................................................... 392 Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset 0x828 ........................................................................................................................... 394 22 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 99: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset 0x834 ........................................................................................................................... 395 Register 100: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset 0x838 ........................................................................................................................... 396 Register 101: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset 0x83C ........................................................................................................................... 397 Register 102: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset 0x840 ........................................................................................................................... 398 Register 103: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset 0x844 ........................................................................................................................... 399 Register 104: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 400 Register 105: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER), offset 0x85C ...................................................................................... 401 Register 106: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 403 Register 107: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 404 Register 108: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 406 Register 109: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 408 Register 110: Hibernation Peripheral Ready (PRHIB), offset 0xA14 ....................................................... 409 Register 111: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 0xA18 ........................................................................................................................... 410 Register 112: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 412 Register 113: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 414 Register 114: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28 ......................................... 416 Register 115: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 417 Register 116: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 418 Register 117: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 419 Register 118: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 .................................... 420 Register 119: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 ............................ 421 Register 120: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 422 Register 121: 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C ...... 423 Register 122: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 425 Register 123: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 427 Register 124: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 430 Register 125: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 433 Register 126: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 437 Register 127: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 440 Register 128: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 442 Register 129: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 443 Register 130: Device Capabilities 8 (DC8), offset 0x02C ....................................................................... 446 Register 131: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 449 Register 132: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 451 Register 133: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 454 Register 134: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 456 Register 135: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 460 Register 136: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 464 Register 137: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 466 Register 138: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 469 Register 139: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 472 Register 140: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 474 June 12, 2014 23 Texas Instruments-Production Data Table of Contents Register 141: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 477 Register 142: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 480 Register 143: Device Capabilities 9 (DC9), offset 0x190 ........................................................................ 482 Register 144: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 484 System Exception Module .......................................................................................................... 485 Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................ 486 Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ........................................... 488 Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ........................... 490 Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ........................................... 492 Hibernation Module ..................................................................................................................... 493 Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 507 Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 508 Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 509 Register 4: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 510 Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 514 Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 516 Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 518 Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 520 Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 521 Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ............................................... 522 Register 11: Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................ 523 Internal Memory ........................................................................................................................... 524 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 542 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 543 Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 544 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 546 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 549 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 551 Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 554 Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 555 Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 556 Register 10: Flash Size (FSIZE), offset 0xFC0 .................................................................................... 557 Register 11: SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 558 Register 12: ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 559 Register 13: EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 560 Register 14: EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 561 Register 15: EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 562 Register 16: EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 563 Register 17: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 564 Register 18: EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 565 Register 19: EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 567 Register 20: EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 569 Register 21: EEPROM Protection (EEPROT), offset 0x030 ................................................................. 570 Register 22: EEPROM Password (EEPASS0), offset 0x034 ................................................................. 572 Register 23: EEPROM Password (EEPASS1), offset 0x038 ................................................................. 572 Register 24: EEPROM Password (EEPASS2), offset 0x03C ................................................................ 572 Register 25: EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 573 Register 26: EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 574 24 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 575 EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 576 ROM Control (RMCTL), offset 0x0F0 .............................................................................. 577 Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 578 Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 578 Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 578 Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 578 Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 579 Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 579 Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 579 Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 579 Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 581 User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 584 User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 584 User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 584 User Register 3 (USER_REG3), offset 0x1EC ................................................................. 584 Micro Direct Memory Access (μDMA) ........................................................................................ 585 Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 609 Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 610 Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 611 Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 616 Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 618 Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 619 Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 620 Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 621 Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 622 Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 623 Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 624 Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 625 Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 626 Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 627 Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 628 Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 629 Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 630 Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 631 Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 632 Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 633 Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 634 Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 635 Register 23: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 636 Register 24: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 637 Register 25: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 638 Register 26: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 639 Register 27: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 640 Register 28: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 641 Register 29: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 642 Register 30: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 643 Register 31: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 644 June 12, 2014 25 Texas Instruments-Production Data Table of Contents Register 32: Register 33: Register 34: Register 35: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 645 DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 646 DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 647 DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 648 General-Purpose Input/Outputs (GPIOs) ................................................................................... 649 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 662 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 663 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 664 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 665 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 666 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 667 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 668 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 669 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 670 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 671 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 673 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 674 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 675 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 676 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 677 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 679 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 681 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 682 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 684 Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 685 Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 687 Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 688 Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 690 Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 691 Register 25: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 692 Register 26: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 693 Register 27: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 694 Register 28: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 695 Register 29: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 696 Register 30: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 697 Register 31: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 698 Register 32: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 699 Register 33: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 700 Register 34: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 701 Register 35: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 702 Register 36: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 703 General-Purpose Timers ............................................................................................................. 704 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 727 Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 729 Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 733 Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 737 Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 741 Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 745 26 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 748 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 751 GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 754 GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 756 GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 757 GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 758 GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 759 GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 760 GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 761 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 762 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 763 GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 764 GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 765 GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 766 GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 767 GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ........................................................ 768 GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ........................................ 769 GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ........................................ 770 GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064 .............................................. 771 GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068 .............................................. 772 GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ..................................................... 773 Watchdog Timers ......................................................................................................................... 774 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 778 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 779 Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 780 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 782 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 783 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 784 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 785 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 786 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 787 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 788 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 789 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 790 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 791 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 792 Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 793 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 794 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 795 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 796 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 797 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 798 Analog-to-Digital Converter (ADC) ............................................................................................. 799 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 821 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 823 Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 825 Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 828 Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 831 June 12, 2014 27 Texas Instruments-Production Data Table of Contents Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 833 ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 838 ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................... 839 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 841 ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 843 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 845 ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 847 ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 848 ADC Control (ADCCTL), offset 0x038 ............................................................................. 850 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 851 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 853 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 860 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 860 ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 860 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 860 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 861 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 861 ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 861 ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 861 ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 863 ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 865 ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 867 ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 867 ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 868 ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 868 ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 872 ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 872 ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 873 ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 873 ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 875 ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 876 ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 878 ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 879 ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 880 ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 885 ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 885 ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 885 ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 885 ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 885 ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 885 ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 885 ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 885 ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 888 ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 888 ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 888 ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 888 ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 888 ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 888 28 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 54: Register 55: Register 56: Register 57: Register 58: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 888 ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 888 ADC Peripheral Properties (ADCPP), offset 0xFC0 .......................................................... 889 ADC Peripheral Configuration (ADCPC), offset 0xFC4 ..................................................... 891 ADC Clock Configuration (ADCCC), offset 0xFC8 ............................................................ 892 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 893 Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 906 Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 908 Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 911 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 913 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 914 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 915 Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 916 Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 918 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 922 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 924 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 927 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 930 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 933 Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 935 Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 936 Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 937 Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 938 Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 939 Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 940 Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 941 Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 942 Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 943 Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 944 Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 945 Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 946 Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 947 Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 948 Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 949 Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 950 Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 951 Synchronous Serial Interface (SSI) ............................................................................................ 952 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 969 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 971 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 973 Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 974 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 976 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 977 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 978 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 980 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 982 Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 983 Register 11: SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................... 984 June 12, 2014 29 Texas Instruments-Production Data Table of Contents Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 985 Register 13: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 986 Register 14: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 987 Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 988 Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 989 Register 17: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 990 Register 18: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 991 Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 992 Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 993 Register 21: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 994 Register 22: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 995 Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 996 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 997 Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1019 Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1020 Register 3: I2C Master Data (I2CMDR), offset 0x008 ....................................................................... 1025 Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1026 Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1027 Register 6: Register 7: Register 8: Register 9: Register 10: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1028 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1029 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1030 I2C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1031 I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1033 Register 11: Register 12: Register 13: Register 14: Register 15: I2C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1034 I2C Master Configuration 2 (I2CMCR2), offset 0x038 ...................................................... 1035 I2C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1036 I2C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1037 I2C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1039 Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1040 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1041 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1042 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1043 I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1044 I2C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1045 I2C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1046 I2C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1047 Controller Area Network (CAN) Module ................................................................................... 1048 Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1070 Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................. 1072 Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................. 1075 Register 4: CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1076 Register 5: CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1077 Register 6: CAN Test (CANTST), offset 0x014 ................................................................................ 1078 Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1080 Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1081 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1081 Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1082 30 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1082 CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1085 CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1085 CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1086 CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1086 CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1088 CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1088 CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1089 CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1089 CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1091 CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1091 CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1094 CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1094 CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1094 CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1094 CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1094 CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1094 CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1094 CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1094 CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1095 CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1095 CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1096 CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1096 CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1097 CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1097 CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1098 CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1098 Universal Serial Bus (USB) Controller ..................................................................................... 1099 Register 1: USB Device Functional Address (USBFADDR), offset 0x000 .......................................... 1122 Register 2: USB Power (USBPOWER), offset 0x001 ....................................................................... 1123 Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................. 1126 Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................. 1128 Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006 ................................................ 1129 Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008 ................................................. 1131 Register 7: USB General Interrupt Status (USBIS), offset 0x00A ...................................................... 1132 Register 8: USB Interrupt Enable (USBIE), offset 0x00B .................................................................. 1135 Register 9: USB Frame Value (USBFRAME), offset 0x00C .............................................................. 1138 Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E ............................................................ 1139 Register 11: USB Test Mode (USBTEST), offset 0x00F ..................................................................... 1140 Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ........................................................... 1142 Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ........................................................... 1142 Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ........................................................... 1142 Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ........................................................... 1142 Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 ........................................................... 1142 Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 ........................................................... 1142 Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 ........................................................... 1142 Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ........................................................... 1142 Register 20: USB Device Control (USBDEVCTL), offset 0x060 .......................................................... 1143 June 12, 2014 31 Texas Instruments-Production Data Table of Contents Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................ 1145 USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 ................................ 1145 USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................ 1146 USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 ................................ 1146 USB Connect Timing (USBCONTIM), offset 0x07A ........................................................ 1147 USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B ............................................ 1148 USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D .... 1149 USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E .... 1150 USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ......... 1151 USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ......... 1151 USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ......... 1151 USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ......... 1151 USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ......... 1151 USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ......... 1151 USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ......... 1151 USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ......... 1151 USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ..................... 1152 USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A .................... 1152 USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ..................... 1152 USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A .................... 1152 USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 .................... 1152 USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA .................... 1152 USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 .................... 1152 USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA .................... 1152 USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ........................... 1153 USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ........................... 1153 USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ........................... 1153 USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ........................... 1153 USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ........................... 1153 USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB .......................... 1153 USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ........................... 1153 USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB .......................... 1153 USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ......... 1154 USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ......... 1154 USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ......... 1154 USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ......... 1154 USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC ......... 1154 USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ......... 1154 USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC ......... 1154 USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ..................... 1155 USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ..................... 1155 USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ..................... 1155 USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ..................... 1155 USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE .................... 1155 USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ..................... 1155 USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE .................... 1155 USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ........................... 1156 USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ........................... 1156 32 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 69: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ........................... 1156 Register 70: USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ........................... 1156 Register 71: USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ........................... 1156 Register 72: USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ........................... 1156 Register 73: USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ........................... 1156 Register 74: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 ......................... 1157 Register 75: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 ........................ 1157 Register 76: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 ........................ 1157 Register 77: USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 ........................ 1157 Register 78: USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 ........................ 1157 Register 79: USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 ........................ 1157 Register 80: USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 ........................ 1157 Register 81: USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ............................... 1158 Register 82: USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................. 1162 Register 83: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................. 1164 Register 84: USB Type Endpoint 0 (USBTYPE0), offset 0x10A .......................................................... 1165 Register 85: USB NAK Limit (USBNAKLMT), offset 0x10B ................................................................ 1166 Register 86: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............. 1167 Register 87: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............. 1167 Register 88: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............. 1167 Register 89: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............. 1167 Register 90: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............. 1167 Register 91: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............. 1167 Register 92: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............. 1167 Register 93: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 ............ 1171 Register 94: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ........... 1171 Register 95: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ........... 1171 Register 96: USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ........... 1171 Register 97: USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ........... 1171 Register 98: USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ........... 1171 Register 99: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ........... 1171 Register 100: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ......................... 1175 Register 101: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ......................... 1175 Register 102: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ......................... 1175 Register 103: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ......................... 1175 Register 104: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ......................... 1175 Register 105: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ......................... 1175 Register 106: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ......................... 1175 Register 107: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............. 1176 Register 108: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............. 1176 Register 109: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............. 1176 Register 110: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............. 1176 Register 111: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............. 1176 Register 112: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............. 1176 Register 113: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............. 1176 Register 114: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 ............ 1181 Register 115: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 ............ 1181 Register 116: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 ............ 1181 June 12, 2014 33 Texas Instruments-Production Data Table of Contents Register 117: USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 ............ 1181 Register 118: USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 ............ 1181 Register 119: USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 ............ 1181 Register 120: USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 ............ 1181 Register 121: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 ............................. 1185 Register 122: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 ............................ 1185 Register 123: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 ............................ 1185 Register 124: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 ............................ 1185 Register 125: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 ............................ 1185 Register 126: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 ............................ 1185 Register 127: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 ............................ 1185 Register 128: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................. 1186 Register 129: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................. 1186 Register 130: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................. 1186 Register 131: USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ................. 1186 Register 132: USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ................. 1186 Register 133: USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ................. 1186 Register 134: USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ................. 1186 Register 135: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ..................... 1188 Register 136: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ..................... 1188 Register 137: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ..................... 1188 Register 138: USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B ..................... 1188 Register 139: USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B ..................... 1188 Register 140: USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B ..................... 1188 Register 141: USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B ..................... 1188 Register 142: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................. 1189 Register 143: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................. 1189 Register 144: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................. 1189 Register 145: USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ................. 1189 Register 146: USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ................. 1189 Register 147: USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ................. 1189 Register 148: USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ................. 1189 Register 149: USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ........... 1191 Register 150: USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ........... 1191 Register 151: USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ........... 1191 Register 152: USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ........... 1191 Register 153: USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ........... 1191 Register 154: USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ........... 1191 Register 155: USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ........... 1191 Register 156: USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304 .......................................................................................................................... 1192 Register 157: USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308 .......................................................................................................................... 1192 Register 158: USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C ......................................................................................................................... 1192 Register 159: USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset 0x310 .......................................................................................................................... 1192 Register 160: USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset 0x314 .......................................................................................................................... 1192 34 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 161: USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset 0x318 .......................................................................................................................... 1192 Register 162: USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset 0x31C ......................................................................................................................... 1192 Register 163: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ........... 1193 Register 164: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 .......... 1194 Register 165: USB External Power Control (USBEPC), offset 0x400 .................................................... 1195 Register 166: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ............... 1198 Register 167: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 .......................... 1199 Register 168: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ....... 1200 Register 169: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 .......................... 1201 Register 170: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ..................................... 1202 Register 171: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................. 1203 Register 172: USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................. 1204 Register 173: USB VBUS Droop Control (USBVDC), offset 0x430 ....................................................... 1205 Register 174: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................. 1206 Register 175: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................. 1207 Register 176: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C .......... 1208 Register 177: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 ............................. 1209 Register 178: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ........................................ 1210 Register 179: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C .................... 1211 Register 180: USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1212 Register 181: USB Peripheral Properties (USBPP), offset 0xFC0 ........................................................ 1214 Analog Comparators ................................................................................................................. 1215 Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1222 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1223 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1224 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1225 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1226 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1226 Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1227 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1227 Register 9: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1229 Pulse Width Modulator (PWM) .................................................................................................. 1230 Register 1: PWM Master Control (PWMCTL), offset 0x000 .............................................................. 1244 Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... 1246 Register 3: PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ 1247 Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... 1249 Register 5: PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1251 Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1253 Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1255 Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1257 Register 9: PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1259 Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1260 Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1262 Register 12: PWM0 Control (PWM0CTL), offset 0x040 ...................................................................... 1266 Register 13: PWM1 Control (PWM1CTL), offset 0x080 ...................................................................... 1266 Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 ..................................................................... 1266 June 12, 2014 35 Texas Instruments-Production Data Table of Contents Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: PWM3 Control (PWM3CTL), offset 0x100 ...................................................................... 1266 PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ................................... 1271 PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ................................... 1271 PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ................................... 1271 PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ................................... 1271 PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ................................................... 1274 PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ................................................... 1274 PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................. 1274 PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ................................................... 1274 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C .......................................... 1276 PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C .......................................... 1276 PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC .......................................... 1276 PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......................................... 1276 PWM0 Load (PWM0LOAD), offset 0x050 ...................................................................... 1278 PWM1 Load (PWM1LOAD), offset 0x090 ...................................................................... 1278 PWM2 Load (PWM2LOAD), offset 0x0D0 ...................................................................... 1278 PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1278 PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1279 PWM1 Counter (PWM1COUNT), offset 0x094 ............................................................... 1279 PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1279 PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1279 PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1280 PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1280 PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................ 1280 PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1280 PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................ 1281 PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................ 1281 PWM2 Compare B (PWM2CMPB), offset 0x0DC ........................................................... 1281 PWM3 Compare B (PWM3CMPB), offset 0x11C ............................................................ 1281 PWM0 Generator A Control (PWM0GENA), offset 0x060 ............................................... 1282 PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ............................................... 1282 PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ............................................... 1282 PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1282 PWM0 Generator B Control (PWM0GENB), offset 0x064 ............................................... 1285 PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ............................................... 1285 PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ............................................... 1285 PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1285 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ............................................... 1288 PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1288 PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ............................................... 1288 PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1288 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................ 1289 PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................ 1289 PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................ 1289 PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1289 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................ 1290 PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................ 1290 PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................ 1290 36 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1290 PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1291 PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1291 PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1291 PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 .................................................. 1291 PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1293 PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1293 PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1293 PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 .................................................. 1293 PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1296 PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1296 PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1296 PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1296 PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1297 PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 .......................................... 1297 PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1298 PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1298 PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1298 PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1298 PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1300 PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ................................................... 1300 PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ................................................... 1300 PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 ................................................... 1300 PWM Peripheral Properties (PWMPP), offset 0xFC0 ...................................................... 1303 Quadrature Encoder Interface (QEI) ........................................................................................ 1305 Register 1: QEI Control (QEICTL), offset 0x000 .............................................................................. 1312 Register 2: QEI Status (QEISTAT), offset 0x004 .............................................................................. 1315 Register 3: QEI Position (QEIPOS), offset 0x008 ............................................................................ 1316 Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ..................................................... 1317 Register 5: QEI Timer Load (QEILOAD), offset 0x010 ..................................................................... 1318 Register 6: QEI Timer (QEITIME), offset 0x014 ............................................................................... 1319 Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... 1320 Register 8: QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1321 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1322 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1324 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1326 June 12, 2014 37 Texas Instruments-Production Data Revision History Revision History The revision history table notes changes made between the indicated revisions of the TM4C123GH6PM data sheet. Table 1. Revision History Date June 2014 Revision Description 15842.2741 ■ In System Control Chapter, corrected description for MINSYSDIV bitfield in Device Capabilities 1 (DC1) legacy register. ■ In Timers chapter, removed erroneous references to TCACT bit field. ■ In SSI chapter, corrected that during idle periods the transmit data line SSInTx is tristated. ■ In Electrical Characteristics chapter, added Data Retention parameter for extended temperature devices to Flash Memory Characteristics table. ■ In Package Information appendix: – Corrected Key to Part Numbers diagram. – Moved Orderable Part Numbers table to addendum. – Deleted Packaging Materials section and put into separate packaging document. ■ Additional minor data sheet clarifications and corrections. March 2014 15741.2722 ■ In the Internal Memory chapter, in the EEPROM section: – Added section on soft reset handling. – Added important information on EEPROM initialization and configuration. ■ In the DMA chapter, added information regarding interrupts and transfers from the UART or SSI modules. ■ In the Hibernation chapter, noted that the EXTW bit is set in the HIBRIS register regardless of the PINWEN setting in the HIBCTL register. ■ In the GPIO chapter: – Corrected table GPIO Pins with Special Considerations. – Added information on preventing false interrupts. – Corrected GPIOAMSEL register to be 8 bits. ■ In the Timer chapter: – Clarified initialization and configuration for Input-Edge Count mode. – Clarified behavior of TnMIE and TnCINTD bits in the GPTM Timer n Mode (GPTMTnMR) register. ■ In the USB chapter, added note to SUSPEND section regarding bus-powered devices. ■ In the Electrical Characteristics chapter: – In table Reset Characteristics, clarified internal reset time parameter values. – In table Hibernation Oscillator Input Characteristics, added parameter CINSE Input capacitance. – In tables Hibernation Oscillator Input Characteristics and Main Oscillator Input Characteristics, removed parameter C0 Crystal shunt capacitance. – Updated table Crystal Parameters. – In table GPIO Module Characteristics, added parameter CGPIO GPIO Digital Input Capacitance. – Added table PWM Timing Characteristics. ■ In the Package Information appendix: – Updated Orderable Devices section to reflect silicon revision 7 part numbers. – Added Tape and Reel pin 1 location. ■ Additional minor data sheet clarifications and corrections. 38 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 1. Revision History (continued) Date Revision Description November 2013 15553.2700 ■ In System Control chapter, clarified PIOSC features and accuracy. ■ In Hibernation Module chapter: – Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source" and "Using a Regulator for Both VDD and VBAT". – Replaced RTC Trim tables with two new figures "Counter Behavior with a TRIM Value of 0x8002" and "Counter Behavior with a TRIM Value of 0x7FFC". – Clarified Hibernation Data (HIBDATA) register description. ■ In Watchdog Timers chapter, clarified Watchdog Control (WDTCTL) register description. ■ In ADC chapter: – Clarified functionality when using an ADC digital comparator as a fault source. – Clarified signals used for ADC voltage reference. – Clarified ADC Trigger Source Select (ADCTSSEL) register description. – Corrected VREF bit in ADC Control (ADCCTL) register from 2-bit field [1:0] to 1-bit field [0]. ■ In UART chapter, clarified DMA operation. ■ In SSI chapter: – Corrected timing guidelines in figures "Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0" and "Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0". – Clarified SSI Initialization and Configuration. – Corrected bit 3 in SSI Control 1 (SSICR1) register from SOD (SSI Slave Mode Output Disable) to reserved. ■ In PWM chapter, added clarifications to PWM0 Control (PWM0CTL), PWM0 Interrupt Status and Clear (PWM0ISC), PWM0 Counter (PWM0COUNT), PWM0 Fault Status 0 (PWM0FLTSTAT0), and PWM0 Fault Status 1 (PWM0FLTSTAT1) registers. ■ In Signal Tables chapter: – In Unused Signals table, corrected preferred and acceptable practices for RST pin. – Clarified GNDX pin description. ■ In Electrical Characteristics chapter: – In Power-On and Brown-Out Levels table, corrected TVDDC_RISE parameter min and max values. – In PIOSC Clock Characteristics table, clarified FPIOSC parameter values by defining values for both factory calibration and recalibration. Also added PIOSC startup time parameter to table. – In Main Oscillator Specifications section, corrected minimum value for External load capacitance on OSC0, OSC1 pins. Also added two 25-MHz crystals to Crystal Parameters table. – Corrected figure "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1". – In I2C Characteristics table, clarified TDH data hold time parameter values by defining values for both slave and master. In addition, added parameter I10 TDV data valid. – Modified figure "I2C Timing" to add new parameter I10. ■ In Packaging Information appendix, added Packaging Materials figures. June 12, 2014 39 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date July 16, 2013 Revision Description 15033.2672 ■ In the Electrical Characteristics chapter: – Added maximum junction temperature to Maximum Ratings table. Also moved Unpowered storage temperature range parameter to this table. – In SSI Characteristics table, corrected values for TRXDMS, TRXDMH, and TRXDSSU. Also clarified footnotes to table. – Corrected parameter numbers in figures "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1" and "Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1". ■ Additional minor data sheet clarifications and corrections. July 2013 14995.2667 ■ Deleted erroneous references to the PWM Peripheral Configuration (PWMPC) register. ■ In the System Control chapter, corrected resets for bits [7:4] in System Properties (SYSPROP) register. ■ In the Hibernation Module chapter: – Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source" and "Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode". – Clarified when the Hibernation module can generate interrupts. ■ In the Internal Memory chapter, removed the INVPL bit from the EEPROM Done Status (EEDONE) register. ■ In the uDMA chapter, in the µDMA Channel Assignments table, corrected names of timers 6-11 to wide timers 0-5. ■ In the Timers chapter: – Clarified that the timer must be configured for one-shot or periodic time-out mode to produce an ADC trigger assertion and that the GPTM does not generate triggers for match, compare events or compare match events. – Added a step in the RTC Mode initialization and configuration: If the timer has been operating in a different mode prior to this, clear any residual set bits in the GPTM Timer n Mode (GPTMTnMR) register before reconfiguring. ■ In the Watchdog Timer chapter, added a note that locking the watchdog registers using the WDTLOCK register does not affect the WDTICR register and allows interrupts to always be serviced. ■ In the SSI chapter, clarified note in Bit Rate Generation section to indicate that the System Clock or the PIOSC can be used as the source for SSIClk. Also corrected to indicate maximum SSIClk limit in SSI slave mode as well as the fact that SYSCLK has to be at least 12 times that of SSICLk. ■ In the PWM chapter, clarified that the PWM has two clock sources, selected by the USPWMDIV bit in the Run-Mode Clock Configuration (RCC) register. ■ In the QEI chapter, noted that the INTERROR bit is only applicable when the QEI is operating in quadrature phase mode (SIGMODE=0) and should be masked when SIGMODE=1. Similarly, the INTDIR bit is only applicable when the QEI is operating in clock/direction mode (SIGMODE=1) and should be masked when SIGMODE=0. ■ In the Electrical Characteristics chapter: – Moved Maximum Ratings and ESD Absolute Maximum Ratings to the front of the chapter. – Added VBATRMP parameter to Maximum Ratings and Hibernation Module Battery Characteristics tables. 40 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 1. Revision History (continued) Date Revision Description – Added ambient and junction temperatures to Temperature Characteristics table and clarified values in Thermal Characteristics table. – Added clarifying footnote to VVDD_POK parameter in Power-On and Brown-Out Levels table. – In the Flash Memory and EEPROM Characteristics tables, added a parameter for page/mass erase times for 10k cycles and corrected existing values for all page and mass erase parameters. – Corrected DNL max value in ADC Electrical Characteristics table. – In the SSI Characteristics table, changed parameter names for S7-S14, provided a max number instead of a min for S7, and corrected values for S9-S14. – Replaced figure "SSI Timing for SPI Frame Format (FRF=00), with SPH=1" with two figures, one for Master Mode and one for Slave Mode. – Updated and added values to the table Table 24-41 on page 1399. ■ In the Package Information appendix, moved orderable devices table from addendum to appendix, clarified part markings and moved packaging diagram from addendum to appendix. ■ Additional minor data sheet clarifications and corrections. June 12, 2014 41 Texas Instruments-Production Data About This Document About This Document This data sheet provides reference information for the TM4C123GH6PM microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following related documents are available on the Tiva™ C Series web site at http://www.ti.com/tiva-c: ■ Tiva™ C Series TM4C123x Silicon Errata (literature number SPMZ849) ■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301) ■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300) ■ TivaWare™ for C Series Release Notes (literature number SPMU299) ■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298) ■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297) ■ Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367) The following related documents may also be useful: ■ ARM® Cortex™-M4 Errata (literature number SPMZ637) ■ ARM® Cortex™-M4 Technical Reference Manual ■ ARM® Debug Interface V5 Architecture Specification ■ ARM® Embedded Trace Macrocell Architecture Specification ■ Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. 42 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 43. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 92. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. RW Software can read or write this field. RWC Software can read or write this field. Writing to it with any value clears the register. RW1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. RW1S Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. June 12, 2014 43 Texas Instruments-Production Data About This Document Table 2. Documentation Conventions (continued) Notation assert a signal deassert a signal SIGNAL SIGNAL Numbers X 0x Meaning Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 44 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1 Architectural Overview Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM® Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem of software and development tools. Targeting performance and flexibility, the Tiva™ C Series architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions by integrating application-specific peripherals and providing a comprehensive library of software tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit applications. This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the TM4C123GH6PM microcontroller: ■ “Tiva™ C Series Overview” on page 45 ■ “TM4C123GH6PM Microcontroller Overview” on page 46 ■ “TM4C123GH6PM Microcontroller Features” on page 49 ■ “TM4C123GH6PM Microcontroller Hardware Details” on page 68 ■ “Kits” on page 68 ■ “Support Information” on page 68 1.1 Tiva™ C Series Overview The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced integration. The product family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: ■ Low power, hand-held smart devices ■ Gaming equipment ■ Home and commercial site monitoring and control ■ Motion control ■ Medical instrumentation ■ Test and measurement equipment ■ Factory automation ■ Fire and security ■ Smart Energy/Smart Grid solutions ■ Intelligent lighting control ■ Transportation For applications requiring extreme conservation of power, the TM4C123GH6PM microcontroller features a battery-backed Hibernation module to efficiently power down the TM4C123GH6PM to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a real-time counter (RTC), multiple wake-from-hibernate options, and dedicated battery-backed memory, the Hibernation module positions the TM4C123GH6PM microcontroller perfectly for battery applications. In addition, the TM4C123GH6PM microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, much of the TM4C123GH6PM microcontroller code is compatible to the Tiva™ C Series product line, providing flexibility across designs. June 12, 2014 45 Texas Instruments-Production Data Architectural Overview 1.2 Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. TM4C123GH6PM Microcontroller Overview The TM4C123GH6PM microcontroller combines complex integration and high performance with the features shown in Table 1-1. Table 1-1. TM4C123GH6PM Microcontroller Features Feature Performance Core Performance Flash System SRAM EEPROM Internal ROM Security Communication Interfaces Universal Asynchronous Receivers/Transmitter (UART) Synchronous Serial Interface (SSI) Inter-Integrated Circuit (I2C) Controller Area Network (CAN) Universal Serial Bus (USB) System Integration Micro Direct Memory Access (µDMA) General-Purpose Timer (GPTM) Watchdog Timer (WDT) Hibernation Module (HIB) General-Purpose Input/Output (GPIO) Advanced Motion Control Pulse Width Modulator (PWM) Quadrature Encoder Interface (QEI) Analog Support Analog-to-Digital Converter (ADC) Analog Comparator Controller Digital Comparator JTAG and Serial Wire Debug (SWD) Package Information Package Operating Range (Ambient) Description ARM Cortex-M4F processor core 80-MHz operation; 100 DMIPS performance 256 KB single-cycle Flash memory 32 KB single-cycle SRAM 2KB of EEPROM Internal ROM loaded with TivaWare™ for C Series software Eight UARTs Four SSI modules Four I2C modules with four transmission speeds including high-speed mode Two CAN 2.0 A/B controllers USB 2.0 OTG/Host/Device ARM® PrimeCell® 32-channel configurable μDMA controller Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks Two watchdog timers Low-power battery-backed Hibernation module Six physical GPIO blocks Two PWM modules, each with four PWM generator blocks and a control block, for a total of 16 PWM outputs. Two QEI modules Two 12-bit ADC modules, each with a maximum sample rate of one million samples/second Two independent integrated analog comparators 16 digital comparators One JTAG module with integrated ARM SWD 64-pin LQFP Industrial (-40°C to 85°C) temperature range Extended (-40°C to 105°C) temperature range 46 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Figure 1-1 on page 48 shows the features on the TM4C123GH6PM microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus. June 12, 2014 47 Texas Instruments-Production Data Architectural Overview Figure 1-1. Tiva™ TM4C123GH6PM Microcontroller High-Level Block Diagram JTAG/SWD System Control and Clocks (w/ Precis. Osc.) TM4C123GH6PM ARM® Cortex™-M4F (80MHz) ROM ETM NVIC FPU DCode bus MPU ICode bus System Bus Flash (256KB) Boot Loader DriverLib AES & CRC Bus Matrix SRAM (32KB) DMA EEPROM (2K) GPIOs (43) USB OTG (FS PHY) SSI (4) Analog Comparator (2) PWM (16) Advanced High-Performance Bus (AHB) Advanced Peripheral Bus (APB) SYSTEM PERIPHERALS Watchdog Timer (2) Hibernation Module GeneralPurpose Timer (12) SERIAL PERIPHERALS UART (8) I2C (4) CAN Controller (2) ANALOG PERIPHERALS 12- Bit ADC Channels (12) MOTION CONTROL PERIPHERALS QEI (2) 48 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3 1.3.1 1.3.1.1 TM4C123GH6PM Microcontroller Features The TM4C123GH6PM microcontroller component features and general function are discussed in more detail in the following section. ARM Cortex-M4F Processor Core All members of the Tiva™ C Series, including the TM4C123GH6PM microcontroller, are designed around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Processor Core (see page 69) ■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications ■ 80-MHz operation; 100 DMIPS performance ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ IEEE754-compliant single-precision Floating-Point Unit (FPU) ■ 16-bit SIMD vector processing unit ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast digital-signal-processing orientated multiply accumulate ■ Saturating arithmetic for signal processing ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing June 12, 2014 49 Texas Instruments-Production Data Architectural Overview 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 ■ Migration from the ARM7™ processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 524 for more information. ■ Ultra-low power consumption with integrated sleep modes System Timer (SysTick) (see page 123) ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine ■ A high-speed alarm timer using the system clock ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter ■ A simple counter used to measure time to completion and time used ■ An internal clock-source control based on missing/meeting durations Nested Vectored Interrupt Controller (NVIC) (see page 124) The TM4C123GH6PM controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 78 interrupts. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these values reflect no FPU stacking) ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications ■ Dynamically reprioritizable interrupts ■ Exceptional interrupt handling via hardware implementation of required register manipulations System Control Block (SCB) (see page 125) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. Memory Protection Unit (MPU) (see page 125) The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 50 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.1.6 1.3.2 1.3.2.1 1.3.2.2 Floating-Point Unit (FPU) (see page 130) The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. ■ 32-bit instructions for single-precision (C float) data-processing operations ■ Combined multiply and accumulate instructions for increased precision (Fused MAC) ■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root ■ Hardware support for denormals and all IEEE rounding modes ■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers ■ Decoupled three stage pipeline On-Chip Memory The TM4C123GH6PM microcontroller is integrated with the following set of on-chip memory and features: ■ 32 KB single-cycle SRAM ■ 256 KB Flash memory ■ 2KB EEPROM ■ Internal ROM loaded with TivaWare™ for C Series software: – TivaWare™ Peripheral Driver Library – TivaWare Boot Loader – Advanced Encryption Standard (AES) cryptography tables – Cyclic Redundancy Check (CRC) error detection functionality SRAM (see page 525) The TM4C123GH6PM microcontroller provides 32 KB of single-cycle on-chip SRAM. The internal SRAM of the device is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from SRAM by the following masters: ■ µDMA ■ USB Flash Memory (see page 528) The TM4C123GH6PM microcontroller provides 256 KB of single-cycle on-chip Flash memory. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of June 12, 2014 51 Texas Instruments-Production Data Architectural Overview 1.3.2.3 1.3.2.4 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. ROM (see page 526) The TM4C123GH6PM ROM is preprogrammed with the following software and programs: ■ TivaWare Peripheral Driver Library ■ TivaWare Boot Loader ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error-detection functionality The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as an application loader and support in-field firmware updates. The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). Modifications to the package source, however, must be open source. CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents as when previously checked. This technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes more readily. EEPROM (see page 534) The TM4C123GH6PM microcontroller includes an EEPROM with the following features: ■ 2Kbytes of memory accessible as 512 32-bit words ■ 32 blocks of 16 words (64 bytes) each ■ Built-in wear leveling ■ Access protection per block ■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes (application selectable) 52 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.3 1.3.3.1 ■ Interrupt support for write completion to avoid polling ■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion) to 15M operations (when cycling through two pages ) per each 2-page block. Serial Communications Peripherals The TM4C123GH6PM controller supports both asynchronous and synchronous serial communications with: ■ Two CAN 2.0 A/B controllers ■ USB 2.0 OTG/Host/Device ■ Eight UARTs with IrDA, 9-bit and ISO 7816 support. ■ Four I2C modules with four transmission speeds including high-speed mode ■ Four Synchronous Serial Interface modules (SSI) The following sections provide more detail on each of these communications functions. Controller Area Network (CAN) (see page 1048) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The TM4C123GH6PM microcontroller includes two CAN units with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals June 12, 2014 53 Texas Instruments-Production Data Architectural Overview 1.3.3.2 1.3.3.3 Universal Serial Bus (USB) (see page 1099) Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The TM4C123GH6PM microcontroller supports three configurations in USB 2.0 full and low speed: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems). The USB module has the following features: ■ Complies with USB-IF (Implementer's Forum) certification standards ■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY ■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 16 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 7 configurable IN endpoints and 7 configurable OUT endpoints ■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ VBUS droop and valid ID detection and interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data UART (see page 893) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The TM4C123GH6PM microcontroller includes eight fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. The eight UARTs have the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 54 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.3.4 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Modem flow control (on UART1) ■ EIA-485 9-bit support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level I2C (see page 997) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. Each device on the I2C bus can be designated as either a master or a slave. I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The TM4C123GH6PM microcontroller includes four I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave June 12, 2014 55 Texas Instruments-Production Data Architectural Overview 1.3.3.5 – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Four transmission speeds: – Standard (100 Kbps) – Fast-mode (400 Kbps) – Fast-mode plus (1 Mbps) – High-speed mode (3.33 Mbps) ■ Clock low timeout interrupt ■ Dual slave address capability ■ Glitch suppression ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode SSI (see page 952) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The TM4C123GH6PM microcontroller includes four SSI modules with the following features: 56 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.4 ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO System Integration The TM4C123GH6PM microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ Six 32-bit timers (up to twelve 16-bit) ■ Six wide 64-bit timers (up to twelve 32-bit) ■ Twelve 32/64-bit Capture Compare PWM (CCP) pins ■ Lower-power battery-backed Hibernation module ■ Real-Time Clock in Hibernation module ■ Two Watchdog Timers – One timer runs off the main oscillator – One timer runs off the precision internal oscillator ■ Up to 43 GPIOs, depending on configuration – Highly flexible pin muxing allows use as GPIO or one of several peripheral functions – Independently configurable to 2-, 4- or 8-mA drive capability – Up to 4 GPIOs can have 18-mA drive capability The following sections provide more detail on each of these functions. June 12, 2014 57 Texas Instruments-Production Data Architectural Overview 1.3.4.1 Direct Memory Access (see page 585) The TM4C123GH6PM microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ■ ARM PrimeCell® 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Flexible channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests 58 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.4.2 ■ Interrupt on transfer completion, with a separate interrupt per channel System Control and Clocks (see page 212) System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. ■ Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Multiple clock sources for microcontroller system clock. The following clock sources are provided to the TM4C123GH6PM microcontroller: – Precision Internal Oscillator (PIOSC) providing a 16-MHz frequency • 16 MHz ±3% across temperature and voltage • Can be recalibrated with 7-bit trim resolution to achieve better accuracy (16 MHz ±1%) • Software power down control for low power modes – Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. – Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving modes – Hibernate RTC oscillator (RTCOSC) clock that can be configured to be the 32.768-kHz external oscillator source from the Hibernation (HIB) module or the HIB Low Frequency clock source (HIB LFIOSC), which is located within the Hibernation Module. ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset June 12, 2014 59 Texas Instruments-Production Data Architectural Overview 1.3.4.3 – MOSC failure Programmable Timers (see page 704) Programmable timers can be used to count or time external events that drive the Timer input pins. Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that can be configured to operate independently as timersor event counters, or configured to operate as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions and DMA transfers. The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks with the following functional options: ■ 16/32-bit operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes with an 8-bit prescaler – 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal ■ 32/64-bit operating modes: – 32- or 64-bit programmable one-shot timer – 32- or 64-bit programmable periodic timer – 32-bit general-purpose timer with a 16-bit prescaler – 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 32-bit input-edge count- or time-capture modes with a16-bit prescaler – 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the PWM signal ■ Count up or down ■ Twelve 16/32-bit Capture Compare PWM pins (CCP) ■ Twelve 32/64-bit Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ Timer synchronization allows selected timers to start counting on the same clock cycle ■ ADC event trigger 60 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.4.4 1.3.4.5 ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt CCP Pins (see page 712) Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The TM4C123GH6PM microcontroller includes twelve 16/32-bit CCP pins that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer compares the current value with a stored value and generates an interrupt when a match occurs. ■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin. Hibernation Module (HIB) (see page 493) The Hibernation module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. The Hibernation module includes power-sequencing logic and has the following features: ■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds counter – 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and interrupt generation with 1/32,768 second resolution – RTC predivider trim for making fine adjustments to the clock rate ■ Two mechanisms for power control – System power control using discrete external regulator – On-chip power control using internal switches under register control ■ Dedicated pin for waking using an external signal ■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid ■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery June 12, 2014 61 Texas Instruments-Production Data Architectural Overview 1.3.4.6 1.3.4.7 ■ GPIO pin state can be retained during hibernation ■ Clock source from a 32.768-kHz external crystal or oscillator ■ Sixteen 32-bit words of battery-backed memory to save state during hibernation ■ Programmable interrupts for: – RTC match – External wake – Low battery Watchdog Timers (see page 774) A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The TM4C123GH6PM Watchdog Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The TM4C123GH6PM microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking and optional NMI function ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug Programmable GPIOs (see page 649) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The TM4C123GH6PM GPIO module is comprised of six physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-43 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1329 for the signals available to each GPIO pin). ■ Up to 43 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Ports A-G accessed through the Advanced Peripheral Bus (APB) 62 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.5 1.3.5.1 ■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence or a μDMA transfer ■ Pin state can be retained during Hibernation mode ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for 8-mA pad drive – Open drain enables – Digital input enables Advanced Motion Control The TM4C123GH6PM microcontroller provides motion control functions integrated into the device, including: ■ Two PWM modules, with a total of 16 advanced PWM outputs for motion and energy applications ■ Two fault inputs to promote low-latency shutdown ■ Two Quadrature Encoder Inputs (QEI) The following provides more detail on these motion control functions. PWM (see page 1230) The TM4C123GH6PM microcontroller contains two PWM modules, each with four PWM generator blocks and a control block, for a total of 16 PWM outputs. Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. Each TM4C123GH6PM PWM module consists of four PWM generator block and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. Each PWM June 12, 2014 63 Texas Instruments-Production Data Architectural Overview generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. Each PWM generator has the following features: ■ One fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled, for a total of two inputs ■ One 16-bit counter – Runs in Down or Up/Down mode – Output frequency controlled by a 16-bit load value – Load value updates can be synchronized – Produces output signals at zero and load value ■ Two PWM comparators – Comparator value updates can be synchronized – Produces output signals on match ■ PWM signal generator – Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals – Produces two independent PWM signals ■ Dead-band generator – Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge – Can be bypassed, leaving input PWM signals unmodified ■ Can initiate an ADC sample sequence The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options: ■ PWM output enable of each PWM signal ■ Optional output inversion of each PWM signal (polarity control) ■ Optional fault handling for each PWM signal ■ Synchronization of timers in the PWM generator blocks ■ Synchronization of timer/comparator updates across the PWM generator blocks ■ Extended PWM synchronization of timer/comparator updates across the PWM generator blocks ■ Interrupt status summary of the PWM generator blocks 64 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.5.2 1.3.6 1.3.6.1 ■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering ■ PWM generators can be operated independently or synchronized with other generators QEI (see page 1305) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can be used to reset the position counter. The TM4C123GH6PM quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The TM4C123GH6PM microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ Programmable noise filter on the inputs ■ Velocity capture using built-in timer ■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) ■ Interrupt generation on: – Index pulse – Velocity-timer expiration – Direction change – Quadrature error detection Analog The TM4C123GH6PM microcontroller provides analog functions integrated into the device, including: ■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 12 analog input channels and each with a sample rate of one million samples/second ■ Two analog comparators ■ On-chip voltage regulator The following provides more detail on these analog functions. ADC (see page 799) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The TM4C123GH6PM ADC module features 12-bit conversion resolution and supports 12 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 12 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger June 12, 2014 65 Texas Instruments-Production Data Architectural Overview 1.3.6.2 events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. The TM4C123GH6PM microcontroller provides two ADC modules, each with the following features: ■ 12 shared analog input channels ■ 12-bit precision ADC ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples ■ Eight digital comparators ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA Analog Comparators (see page 1215) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The TM4C123GH6PM microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 66 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1.3.7 1.3.8 The TM4C123GH6PM microcontroller provides two independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage JTAG and ARM Serial Wire Debug (see page 200) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Embedded Trace Macrocell (ETM) for instruction trace capture – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer Packaging and Temperature ■ 64-pin RoHS-compliant LQFP package ■ Industrial (-40°C to 85°C) ambient temperature range June 12, 2014 67 Texas Instruments-Production Data Architectural Overview ■ Extended (-40°C to 105°C) ambient temperature range 1.4 TM4C123GH6PM Microcontroller Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1328 ■ “Signal Tables” on page 1329 ■ “Electrical Characteristics” on page 1358 ■ “Package Information” on page 1402 1.5 Kits The Tiva™ C Series provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C123GH6PM microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your distributor. 1.6 Support Information For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center nearest you. 68 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2 The Cortex-M4F Processor The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ 32-bit ARM® Cortex™-M4F architecture optimized for small-footprint embedded applications ■ 80-MHz operation; 100 DMIPS performance ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ IEEE754-compliant single-precision Floating-Point Unit (FPU) ■ 16-bit SIMD vector processing unit ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast digital-signal-processing orientated multiply accumulate ■ Saturating arithmetic for signal processing ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7™ processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 524 for more information. ■ Ultra-low power consumption with integrated sleep modes June 12, 2014 69 Texas Instruments-Production Data The Cortex-M4F Processor The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing to This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A). 2.1 Block Diagram The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4F processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M4F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The TM4C123GH6PM NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 70 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep Debug FPU CM4 Core Instructions Data Memory Protection Unit ARM Cortex-M4F Embedded Trace Macrocell Serial Wire Output Trace Trace Port Port (SWO) Interface Unit Serial Wire JTAG Debug Port Flash Patch and Breakpoint Private Peripheral Bus (internal) Debug Access Port Data Instrumentation Watchpoint Trace Macrocell and Trace ROM Table Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus 2.2 2.2.1 2.2.2 Overview System-Level Interface The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. Integrated Configurable Debug The Cortex-M4F processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™ C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. June 12, 2014 71 Texas Instruments-Production Data The Cortex-M4F Processor 2.2.3 The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see the ARM® Embedded Trace Macrocell Architecture Specification. The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions for up to eight words of program code in the code memory region. This FPB enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5 Architecture Specification. Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 72. Figure 2-2. TPIU Block Diagram Debug ATB Slave Port ARM® Trace Bus (ATB) Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) APB Slave Port Advance Peripheral Bus (APB) Interface 2.2.4 Cortex-M4F System Component Details The Cortex-M4F includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 123). ■ Nested Vectored Interrupt Controller (NVIC) 72 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.3 2.3.1 An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 124). ■ System Control Block (SCB) The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” on page 125). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 125). ■ Floating-Point Unit (FPU) Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square-root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 130). Programming Model This section describes the Cortex-M4F programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. Processor Mode and Privilege Levels for Software Execution The Cortex-M4F has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M4F has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 88) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. June 12, 2014 73 Texas Instruments-Production Data The Cortex-M4F Processor 2.3.2 2.3.3 Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks: the main stack and the process stack, with a pointer for each held in independent registers (see the SP register on page 78). In Thread mode, the CONTROL register (see page 88) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 74. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Thread Applications Handler Exception handlers a. See CONTROL (page 88). Privilege Level Privileged or unprivileged a Always privileged Stack Used Main stack or process stack a Main stack Register Map Figure 2-3 on page 75 shows the Cortex-M4F register set. Table 2-2 on page 75 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. 74 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Figure 2-3. Cortex-M4F Register Set Low registers High registers Stack Pointer Link Register Program Counter R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP (R13) LR (R14) PC (R15) PSR PRIMASK FAULTMASK BASEPRI CONTROL General-purpose registers PSP‡ MSP‡ Program status register Exception mask registers CONTROL register ‡Banked version of SP Special registers Table 2-2. Processor Register Map Offset Name Type - R0 RW - R1 RW - R2 RW - R3 RW - R4 RW - R5 RW - R6 RW - R7 RW - R8 RW - R9 RW - R10 RW - R11 RW Reset - Description Cortex General-Purpose Register 0 Cortex General-Purpose Register 1 Cortex General-Purpose Register 2 Cortex General-Purpose Register 3 Cortex General-Purpose Register 4 Cortex General-Purpose Register 5 Cortex General-Purpose Register 6 Cortex General-Purpose Register 7 Cortex General-Purpose Register 8 Cortex General-Purpose Register 9 Cortex General-Purpose Register 10 Cortex General-Purpose Register 11 See page 77 77 77 77 77 77 77 77 77 77 77 77 June 12, 2014 75 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-2. Processor Register Map (continued) Offset Name Type Reset Description - R12 - SP - LR - PC - PSR - PRIMASK - FAULTMASK - BASEPRI - CONTROL - FPSC RW - Cortex General-Purpose Register 12 RW - Stack Pointer RW 0xFFFF.FFFF Link Register RW - Program Counter RW 0x0100.0000 Program Status Register RW 0x0000.0000 Priority Mask Register RW 0x0000.0000 Fault Mask Register RW 0x0000.0000 Base Priority Mask Register RW 0x0000.0000 Control Register RW - Floating-Point Status Control See page 77 78 79 80 81 85 86 87 88 90 2.3.4 Register Descriptions This section lists and describes the Cortex-M4F registers, in the order shown in Figure 2-3 on page 75. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. 76 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - Bit/Field 31:0 Name DATA Type RW Reset - Description Register data. June 12, 2014 77 Texas Instruments-Production Data The Cortex-M4F Processor Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SP Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SP Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - Bit/Field 31:0 Name SP Type RW Reset - Description This field is the address of the stack pointer. 78 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 111 for the values and description. Link Register (LR) Type RW, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LINK Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LINK Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field 31:0 Name LINK Type Reset Description RW 0xFFFF.FFFF This field is the return address. June 12, 2014 79 Texas Instruments-Production Data The Cortex-M4F Processor Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PC Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - Bit/Field 31:0 Name PC Type RW Reset - Description This field is the current program address. 80 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: ■ Application Program Status Register (APSR), bits 31:27, bits 19:16 ■ Execution Program Status Register (EPSR), bits 26:24, 15:10 ■ Interrupt Program Status Register (IPSR), bits 7:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see “Exception Entry and Return” on page 108). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 81 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register PSR Type RWa, b Combination APSR, EPSR, and IPSR IEPSR IAPSR EAPSR RO RWa RWb EPSR and IPSR APSR and IPSR APSR and EPSR a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type RW, reset 0x0100.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N Z C V Q ICI / IT THUMB reserved GE Type RW RW RW RW RW RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICI / IT reserved ISRNUM Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 June 12, 2014 81 Texas Instruments-Production Data The Cortex-M4F Processor Bit/Field 31 30 29 28 27 Name N Z C V Q Type RW RW RW RW RW Reset 0 0 0 0 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. APSR Carry or Borrow Flag Value Description 1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessing PSR or APSR. APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred when using a SIMD instruction. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. 82 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 26:25 24 23:20 19:16 Name ICI / IT THUMB reserved GE Type RO RO RO RW Reset 0x0 1 0x00 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessing PSR or EPSR. Note that these EPSR bits cannot be accessed using MRS and MSR instructions but the definitions are provided to allow the stacked (E)PSR value to be decoded within an exception handler. EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stacked xPSR value on an exception return ■ Bit 0 of the vector value on an exception entry or reset Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 113 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Greater Than or Equal Flags See the description of the SEL instruction in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessing PSR or APSR. June 12, 2014 83 Texas Instruments-Production Data The Cortex-M4F Processor Bit/Field 15:10 9:8 7:0 Name ICI / IT reserved ISRNUM Type RO RO RO Reset 0x0 0x0 0x00 Description EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessing PSR or EPSR. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x9A Interrupt Vector 138 See “Exception Types” on page 102 for more information. The value of this field is only meaningful when accessing PSR or IPSR. 84 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 102. Priority Mask Register (PRIMASK) Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved PRIMASK Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority. 0 No effect. June 12, 2014 85 Texas Instruments-Production Data The Cortex-M4F Processor Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 102. Fault Mask Register (FAULTMASK) Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FAULTMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved FAULTMASK Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. 86 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 102. Base Priority Mask Register (BASEPRI) Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BASEPRI reserved Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7:5 Name reserved BASEPRI Type RO RW Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 87 Texas Instruments-Production Data The Cortex-M4F Processor Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode. Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 111). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A), or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 111. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A). Control Register (CONTROL) Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FPCA ASP TMPL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:3 2 Name reserved FPCA Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 Floating-Point Context Active Value Description 1 Floating-point context active 0 No floating-point context active The Cortex-M4F uses this bit to determine whether to preserve floating-point state when processing an exception. Important: Two bits control when FPCA can be enabled: the ASPEN bit in the Floating-Point Context Control (FPCC) register and the DISFPCA bit in the Auxiliary Control (ACTLR) register. 88 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name ASP TMPL Type RW RW Reset 0 0 Description Active Stack Pointer Value Description 1 The PSP is the current stack pointer. 0 The MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4F updates this bit automatically on exception return. Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. June 12, 2014 89 Texas Instruments-Production Data The Cortex-M4F Processor Register 22: Floating-Point Status Control (FPSC) The FPSC register provides all necessary user-level control of the floating-point system. Floating-Point Status Control (FPSC) Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N Z C V reserved AHP DN FZ RMODE reserved Type RW RW RW RW RO RW RW RW RW RW RO RO RO RO RO RO Reset - - - - 0 - - - - - 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IDC reserved IXC UFC OFC DZC IOC Type RO RO RO RO RO RO RO RO RW RO RO RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 - 0 0 - - - - - Bit/Field 31 30 29 28 27 26 25 24 Name N Z C V reserved AHP DN FZ Type RW RW RW RW RO RW RW RW Reset 0 - - - Description Negative Condition Code Flag Floating-point comparison operations update this condition code flag. Zero Condition Code Flag Floating-point comparison operations update this condition code flag. Carry Condition Code Flag Floating-point comparison operations update this condition code flag. Overflow Condition Code Flag Floating-point comparison operations update this condition code flag. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Alternative Half-Precision When set, alternative half-precision format is selected. When clear, IEEE half-precision format is selected. The AHP bit in the FPDSC register holds the default value for this bit. Default NaN Mode When set, any operation involving one or more NaNs returns the Default NaN. When clear, NaN operands propagate through to the output of a floating-point operation. The DN bit in the FPDSC register holds the default value for this bit. Flush-to-Zero Mode When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero mode is disabled and the behavior of the floating-point system is fully compliant with the IEEE 754 standard. The FZ bit in the FPDSC register holds the default value for this bit. 90 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 23:22 21:8 7 6:5 4 3 2 1 0 Name RMODE reserved IDC reserved IXC UFC OFC DZC IOC Type RW RO RW RO RW RW RW RW RW Reset - Description Rounding Mode The specified rounding mode is used by almost all floating-point instructions. The RMODE bit in the FPDSC register holds the default value for this bit. Value Description 0x0 Round to Nearest (RN) mode 0x1 Round towards Plus Infinity (RP) mode 0x2 Round towards Minus Infinity (RM) mode 0x3 Round towards Zero (RZ) mode 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - Input Denormal Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - Inexact Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. - Underflow Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. - Overflow Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. - Division by Zero Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. - Invalid Operation Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. June 12, 2014 91 Texas Instruments-Production Data The Cortex-M4F Processor 2.3.5 2.3.6 Exceptions and Interrupts The Cortex-M4F processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 108 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 124 for more information. Data Types The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 95 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the TM4C123GH6PM controller is provided in Table 2-4 on page 92. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 97). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M4 Peripherals” on page 122). Note: Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault. Table 2-4. Memory Map Start End Memory 0x0000.0000 0x0004.0000 0x2000.0000 0x2000.8000 0x2200.0000 0x0003.FFFF 0x1FFF.FFFF 0x2000.7FFF 0x21FF.FFFF 0x220F.FFFF 0x2210.0000 Peripherals 0x4000.0000 0x4000.1000 0x4000.2000 0x4000.4000 0x4000.5000 0x3FFF.FFFF 0x4000.0FFF 0x4000.1FFF 0x4000.3FFF 0x4000.4FFF 0x4000.5FFF Description On-chip Flash Reserved Bit-banded on-chip SRAM Reserved Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 Reserved Watchdog timer 0 Watchdog timer 1 Reserved GPIO Port A GPIO Port B For details, see page ... 540 525 525 - 776 776 658 658 92 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 2-4. Memory Map (continued) Start End 0x4000.6000 0x4000.7000 0x4000.8000 0x4000.9000 0x4000.A000 0x4000.B000 0x4000.C000 0x4000.D000 0x4000.E000 0x4000.F000 0x4001.0000 0x4001.1000 0x4001.2000 0x4001.3000 0x4001.4000 Peripherals 0x4002.0000 0x4002.1000 0x4002.2000 0x4002.3000 0x4002.4000 0x4002.5000 0x4002.6000 0x4002.8000 0x4002.9000 0x4002.A000 0x4002.C000 0x4002.D000 0x4002.E000 0x4003.0000 0x4003.1000 0x4003.2000 0x4003.3000 0x4003.4000 0x4003.5000 0x4003.6000 0x4003.7000 0x4003.8000 0x4003.9000 0x4003.A000 0x4003.C000 0x4000.6FFF 0x4000.7FFF 0x4000.8FFF 0x4000.9FFF 0x4000.AFFF 0x4000.BFFF 0x4000.CFFF 0x4000.DFFF 0x4000.EFFF 0x4000.FFFF 0x4001.0FFF 0x4001.1FFF 0x4001.2FFF 0x4001.3FFF 0x4001.FFFF 0x4002.0FFF 0x4002.1FFF 0x4002.2FFF 0x4002.3FFF 0x4002.4FFF 0x4002.5FFF 0x4002.7FFF 0x4002.8FFF 0x4002.9FFF 0x4002.BFFF 0x4002.CFFF 0x4002.DFFF 0x4002.FFFF 0x4003.0FFF 0x4003.1FFF 0x4003.2FFF 0x4003.3FFF 0x4003.4FFF 0x4003.5FFF 0x4003.6FFF 0x4003.7FFF 0x4003.8FFF 0x4003.9FFF 0x4003.BFFF 0x4003.CFFF Description GPIO Port C GPIO Port D SSI0 SSI1 SSI2 SSI3 UART0 UART1 UART2 UART3 UART4 UART5 UART6 UART7 Reserved I2C 0 I2C 1 I2C 2 I2C 3 GPIO Port E GPIO Port F Reserved PWM 0 PWM 1 Reserved QEI0 QEI1 Reserved 16/32-bit Timer 0 16/32-bit Timer 1 16/32-bit Timer 2 16/32-bit Timer 3 16/32-bit Timer 4 16/32-bit Timer 5 32/64-bit Timer 0 32/64-bit Timer 1 ADC0 ADC1 Reserved Analog Comparators June 12, 2014 Texas Instruments-Production Data For details, see page ... 658 658 967 967 967 967 903 903 903 903 903 903 903 903 - 1017 1017 1017 1017 658 658 1240 1240 1310 1310 725 725 725 725 725 725 725 725 818 818 1220 93 The Cortex-M4F Processor Table 2-4. Memory Map (continued) Start End 0x4003.D000 0x4004.0000 0x4004.1000 0x4004.2000 0x4004.C000 0x4004.D000 0x4004.E000 0x4004.F000 0x4005.0000 0x4005.1000 0x4005.8000 0x4005.9000 0x4005.A000 0x4005.B000 0x4005.C000 0x4005.D000 0x4005.E000 0x400A.F000 0x400B.0000 0x400F.9000 0x400F.A000 0x400F.C000 0x400F.D000 0x400F.E000 0x400F.F000 0x4010.0000 0x4200.0000 0x4400.0000 Private Peripheral Bus 0xE000.0000 0xE000.1000 0xE000.2000 0xE000.3000 0xE000.E000 0xE000.F000 0xE004.0000 0xE004.1000 0xE004.2000 0x4003.FFFF 0x4004.0FFF 0x4004.1FFF 0x4004.BFFF 0x4004.CFFF 0x4004.DFFF 0x4004.EFFF 0x4004.FFFF 0x4005.0FFF 0x4005.7FFF 0x4005.8FFF 0x4005.9FFF 0x4005.AFFF 0x4005.BFFF 0x4005.CFFF 0x4005.DFFF 0x400A.EFFF 0x400A.FFFF 0x400F.8FFF 0x400F.9FFF 0x400F.BFFF 0x400F.CFFF 0x400F.DFFF 0x400F.EFFF 0x400F.FFFF 0x41FF.FFFF 0x43FF.FFFF 0xDFFF.FFFF 0xE000.0FFF 0xE000.1FFF 0xE000.2FFF 0xE000.DFFF 0xE000.EFFF 0xE003.FFFF 0xE004.0FFF 0xE004.1FFF 0xFFFF.FFFF Description Reserved CAN0 Controller CAN1 Controller Reserved 32/64-bit Timer 2 32/64-bit Timer 3 32/64-bit Timer 4 32/64-bit Timer 5 USB Reserved GPIO Port A (AHB aperture) GPIO Port B (AHB aperture) GPIO Port C (AHB aperture) GPIO Port D (AHB aperture) GPIO Port E (AHB aperture) GPIO Port F (AHB aperture) Reserved EEPROM and Key Locker Reserved System Exception Module Reserved Hibernation Module Flash memory control System control µDMA Reserved Bit-banded alias of 0x4000.0000 through 0x400F.FFFF Reserved For details, see page ... 1067 1067 725 725 725 725 1114 658 658 658 658 658 658 540 485 505 540 231 606 - Instrumentation Trace Macrocell (ITM) 71 Data Watchpoint and Trace (DWT) 71 Flash Patch and Breakpoint (FPB) 71 Reserved - Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 134 Reserved - Trace Port Interface Unit (TPIU) 72 Embedded Trace Macrocell (ETM) 71 Reserved - 94 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.4.1 2.4.2 2.4.3 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 96). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. Behavior of Memory Accesses Table 2-5 on page 95 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 95 for more information on memory types and the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 92 for more information). Table 2-5. Memory Access Behavior Address Range Memory Region 0x0000.0000 - 0x1FFF.FFFF Code 0x2000.0000 - 0x3FFF.FFFF SRAM 0x4000.0000 - 0x5FFF.FFFF Peripheral 0x6000.0000 - 0x9FFF.FFFF External RAM Memory Type Execute Never (XN) Normal - Normal - Device XN Normal - Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 97). This region includes bit band and bit band alias areas (see Table 2-7 on page 98). This executable region is for data. June 12, 2014 95 Texas Instruments-Production Data The Cortex-M4F Processor 2.4.4 Table 2-5. Memory Access Behavior (continued) Address Range Memory Region Memory Type Execute Never (XN) 0xA000.0000 - 0xDFFF.FFFF External device Device XN 0xE000.0000- 0xE00F.FFFF Private peripheral Strongly XN bus Ordered 0xE010.0000- 0xFFFF.FFFF Reserved - - Description This region is for external device memory. This region includes the NVIC, system timer, and system control block. - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M4F has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 125. The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 95 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. 96 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.4.5 – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A). Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 97. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 98. For the specific address range of the bit-band regions, see Table 2-4 on page 92. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table 2-6. SRAM Memory Bit-Banding Regions Address Range Start 0x2000.0000 End 0x2000.7FFF Memory Region Instruction and Data Accesses SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. June 12, 2014 97 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-6. SRAM Memory Bit-Banding Regions (continued) Address Range Start 0x2200.0000 End 0x220F.FFFF Memory Region Instruction and Data Accesses SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Start 0x4000.0000 End 0x400F.FFFF 0x4200.0000 0x43FF.FFFF Memory Region Instruction and Data Accesses Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 99 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 98 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 1-MB SRAM Bit-Band Region 76543210765432107654321076543210 0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC 76543210765432107654321076543210 0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000 2.4.5.1 2.4.5.2 2.4.6 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. Directly Accessing a Bit-Band Region “Behavior of Memory Accesses” on page 95 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 100 illustrates how data is stored. June 12, 2014 99 Texas Instruments-Production Data The Cortex-M4F Processor Figure 2-5. Data Storage Memory 7 0 Register Address A B0 lsbyte 31 24 23 16 15 8 7 0 B3 B2 B1 B0 A+1 B1 A+2 B2 A+3 B3 msbyte 2.4.7 Synchronization Primitives The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructions LDREX and STREX ■ The halfword instructions LDREXH and STREXH ■ The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 100 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes a CLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A). 2.5 Exception Model The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 103 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 78 interrupts (listed in Table 2-9 on page 104). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 124. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 124 for more information on exceptions and interrupts. June 12, 2014 101 Texas Instruments-Production Data The Cortex-M4F Processor 2.5.1 2.5.2 Exception States Each exception is in one of the following states: ■ Inactive. The exception is not active and not pending. ■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. Exception Types The exception types are: ■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution 102 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. ■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 104 lists the interrupts on the TM4C123GH6PM controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 103 shows as having configurable priority (see the SYSHNDCTRL register on page 173 and the DIS0 register on page 144). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 111. Table 2-8. Exception Types Exception Type - Vector Number 0 Reset 1 Non-Maskable Interrupt 2 (NMI) Hard Fault 3 Memory Management 4 Bus Fault 5 Usage Fault SVCall Debug Monitor - 6 7-10 11 12 13 Prioritya - -3 (highest) -2 -1 programmablec programmablec programmablec - programmablec programmablec - Vector Address or Offsetb 0x0000.0000 0x0000.0004 0x0000.0008 Activation Stack top is loaded from the first entry of the vector table on reset. Asynchronous Asynchronous 0x0000.000C 0x0000.0010 0x0000.0014 0x0000.0018 - 0x0000.002C 0x0000.0030 - Synchronous Synchronous when precise and asynchronous when imprecise Synchronous Reserved Synchronous Synchronous Reserved June 12, 2014 103 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-8. Exception Types (continued) Exception Type PendSV SysTick Interrupts Vector Number 14 15 16 and above Prioritya programmablec programmablec programmabled a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 106. c. See SYSPRI1 on page 170. d. See PRIn registers on page 152. Vector Address or Offsetb Activation 0x0000.0038 Asynchronous 0x0000.003C Asynchronous 0x0000.0040 and above Asynchronous Table 2-9. Interrupts Vector Number 0-15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Interrupt Number (Bit in Interrupt Registers) - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Vector Address or Offset 0x0000.0000 0x0000.003C 0x0000.0040 0x0000.0044 0x0000.0048 0x0000.004C 0x0000.0050 0x0000.0054 0x0000.0058 0x0000.005C 0x0000.0060 0x0000.0064 0x0000.0068 0x0000.006C 0x0000.0070 0x0000.0074 0x0000.0078 0x0000.007C 0x0000.0080 0x0000.0084 0x0000.0088 0x0000.008C 0x0000.0090 0x0000.0094 0x0000.0098 0x0000.009C 0x0000.00A0 0x0000.00A4 0x0000.00A8 0x0000.00B0 Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 I2C0 PWM0 Fault PWM0 Generator 0 PWM0 Generator 1 PWM0 Generator 2 QEI0 ADC0 Sequence 0 ADC0 Sequence 1 ADC0 Sequence 2 ADC0 Sequence 3 Watchdog Timers 0 and 1 16/32-Bit Timer 0A 16/32-Bit Timer 0B 16/32-Bit Timer 1A 16/32-Bit Timer 1B 16/32-Bit Timer 2A 16/32-Bit Timer 2B Analog Comparator 0 Analog Comparator 1 Reserved System Control 104 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 2-9. Interrupts (continued) Vector Number 45 46 47-48 49 50 51 52 53 54 55 56 57-58 59 60 61 62 63 64 65 66 67 68-72 73 74 75 76 77 78 79 80-83 84 85 86 87 88-107 108 109 110 111 112 Interrupt Number (Bit in Interrupt Registers) 29 30 31-32 33 34 35 36 37 38 39 40 41-42 43 44 45 46 47 48 49 50 51 52-56 57 58 59 60 61 62 63 64-67 68 69 70 71 72-91 92 93 94 95 96 Vector Address or Offset 0x0000.00B4 0x0000.00B8 0x0000.00C4 0x0000.00C8 0x0000.00CC 0x0000.00D0 0x0000.00D4 0x0000.00D8 0x0000.00DC 0x0000.00E0 0x0000.00EC 0x0000.00F0 0x0000.00F4 0x0000.00F8 0x0000.00FC 0x0000.0100 0x0000.0104 0x0000.0108 0x0000.010C 0x0000.0124 0x0000.0128 0x0000.012C 0x0000.0130 0x0000.0134 0x0000.0138 0x0000.013C 0x0000.0140 0x0000.014C 0x0000.0150 0x0000.0154 0x0000.0158 0x0000.015C 0x0000.0160 0x0000.01AC 0x0000.01B0 0x0000.01B4 0x0000.01B8 0x0000.01BC 0x0000.01C0 Description Flash Memory Control and EEPROM Control GPIO Port F Reserved UART2 SSI1 16/32-Bit Timer 3A 16/32-Bit Timer 3B I2C1 QEI1 CAN0 CAN1 Reserved Hibernation Module USB PWM Generator 3 µDMA Software µDMA Error ADC1 Sequence 0 ADC1 Sequence 1 ADC1 Sequence 2 ADC1 Sequence 3 Reserved SSI2 SSI3 UART3 UART4 UART5 UART6 UART7 Reserved I2C2 I2C3 16/32-Bit Timer 4A 16/32-Bit Timer 4B Reserved 16/32-Bit Timer 5A 16/32-Bit Timer 5B 32/64-Bit Timer 0A 32/64-Bit Timer 0B 32/64-Bit Timer 1A June 12, 2014 105 Texas Instruments-Production Data The Cortex-M4F Processor 2.5.3 2.5.4 Table 2-9. Interrupts (continued) Vector Number 113 114 115 116 117 118 119 120 121 122 123-149 150 151 152 153 154 Interrupt Number (Bit in Interrupt Registers) 97 98 99 100 101 102 103 104 105 106 107-133 134 135 136 137 138 Vector Address or Offset 0x0000.01C4 0x0000.01C8 0x0000.01CC 0x0000.01D0 0x0000.01D4 0x0000.01D8 0x0000.01DC 0x0000.01E0 0x0000.01E4 0x0000.01E8 0x0000.0258 0x0000.025C 0x0000.0260 0x0000.0264 0x0000.0268 Description 32/64-Bit Timer 1B 32/64-Bit Timer 2A 32/64-Bit Timer 2B 32/64-Bit Timer 3A 32/64-Bit Timer 3B 32/64-Bit Timer 4A 32/64-Bit Timer 4B 32/64-Bit Timer 5A 32/64-Bit Timer 5B System Exception (imprecise) Reserved PWM1 Generator 0 PWM1 Generator 1 PWM1 Generator 2 PWM1 Generator 3 PWM1 Fault Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 103. Figure 2-6 on page 107 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code 106 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.5.5 Figure 2-6. Vector Table Exception number IRQ number Offset Vector 154 138 IRQ131 0x0268 . . . . . . . . . 0x004C 18 2 IRQ2 0x0048 17 1 IRQ1 0x0044 16 0 IRQ0 0x0040 15 -1 Systick 0x003C 14 -2 PendSV 0x0038 13 Reserved 12 Reserved for Debug 11 -5 SVCall 0x002C 10 9 Reserved 8 7 6 -10 Usage fault 0x0018 5 -11 Bus fault 0x0014 4 -12 Memory management fault 0x0010 3 -13 Hard fault 0x000C 2 -14 NMI 0x0008 1 Reset 0x0004 Initial SP value 0x0000 On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 106). Note that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary. Exception Priorities As Table 2-8 on page 103 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 170 and page 152. Note: Configurable priority values for the Tiva™ C Series implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. June 12, 2014 107 Texas Instruments-Production Data The Cortex-M4F Processor 2.5.6 2.5.7 If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 164. Exception Entry and Return Descriptions of exception handling use the following terms: ■ Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 108 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 109 more information. ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 110 for more information. ■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 108 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.5.7.1 return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 85, FAULTMASK on page 86, and BASEPRI on page 87). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. When using floating-point routines, the Cortex-M4F processor automatically stacks the architected floating-point state on exception entry. Figure 2-7 on page 110 shows the Cortex-M4F stack frame layout when floating-point state is preserved on the stack as the result of an interrupt or an exception. Note: Where stack space for floating-point state is not allocated, the stack frame is the same as that of ARMv7-M implementations without an FPU. Figure 2-7 on page 110 shows this stack frame also. June 12, 2014 109 Texas Instruments-Production Data The Cortex-M4F Processor 2.5.7.2 Figure 2-7. Exception Stack Frame ... {aligner} Pre-IRQ top of stack FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Exception frame with floating-point storage Decreasing memory address IRQ top of stack ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Exception frame without floating-point storage Pre-IRQ top of stack IRQ top of stack Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel with the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: 110 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.6 ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. Table 2-10 on page 111 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] 0xFFFF.FFE0 0xFFFF.FFE1 0xFFFF.FFE2 - 0xFFFF.FFE8 0xFFFF.FFE9 0xFFFF.FFEA - 0xFFFF.FFEC 0xFFFF.FFED 0xFFFF.FFEE - 0xFFFF.FFF0 0xFFFF.FFF1 0xFFFF.FFF2 - 0xFFFF.FFF8 0xFFFF.FFF9 0xFFFF.FFFA - 0xFFFF.FFFC 0xFFFF.FFFD 0xFFFF.FFFE - 0xFFFF.FFFF Description Reserved Return to Handler mode. Exception return uses floating-point state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses floating-point state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses floating-point state from PSP. Execution uses PSP after return. Reserved Return to Handler mode. Exception return uses non-floating-point state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses non-floating-point state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses non-floating-point state from PSP. Execution uses PSP after return. Reserved Fault Handling Faults are a subset of the exceptions (see “Exception Model” on page 101). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. June 12, 2014 111 Texas Instruments-Production Data The Cortex-M4F Processor 2.6.1 2.6.2 ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. Fault Types Table 2-11 on page 112 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 177 for more information about the fault status registers. Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) MPU or default memory mismatch on Memory management Memory Management Fault Status instruction access fault (MFAULTSTAT) FORCED IERR a MPU or default memory mismatch on Memory management Memory Management Fault Status data access fault (MFAULTSTAT) DERR MPU or default memory mismatch on Memory management Memory Management Fault Status exception stacking fault (MFAULTSTAT) MSTKE MPU or default memory mismatch on Memory management Memory Management Fault Status exception unstacking fault (MFAULTSTAT) MUSTKE MPU or default memory mismatch during lazy floating-point state preservation Memory management Memory Management Fault Status fault (MFAULTSTAT) MLSPERR Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Bus error during lazy floating-point state Bus fault preservation Bus Fault Status (BFAULTSTAT) BLSPE Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault set state b Usage Fault Status (UFAULTSTAT) INVSTAT Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction with ICI continuation. Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 170). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 173). 112 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.6.3 2.6.4 Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 101. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 113. Table 2-12. Fault Status and Fault Address Registers Handler Status Register Name Hard fault Hard Fault Status (HFAULTSTAT) Memory management Memory Management Fault Status fault (MFAULTSTAT) Bus fault Bus Fault Status (BFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Address Register Name Register Description - page 183 Memory Management Fault page 177 Address (MMADDR) page 184 Bus Fault Address (FAULTADDR) page 177 page 185 - page 177 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. June 12, 2014 113 Texas Instruments-Production Data The Cortex-M4F Processor 2.7 2.7.1 2.7.1.1 2.7.1.2 2.7.1.3 2.7.2 Power Management The Cortex-M4F processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 166). For more information about the behavior of the sleep modes, see “System Control” on page 227. This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 115). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep mode. 114 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 2.7.2.1 2.7.2.2 2.8 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 85 and page 86. Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 166. Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 115 lists the supported instructions. Note: In Table 2-13 on page 115: ■ Angle brackets, <>, enclose alternative forms of the operand ■ Braces, {}, enclose optional operands ■ The Operands column is not exhaustive ■ Op2 is a flexible second operand that can be either a register or a constant ■ Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the ARM® Cortex™-M4 Technical Reference Manual. Table 2-13. Cortex-M4F Instruction Summary Mnemonic ADC, ADCS ADD, ADDS ADD, ADDW ADR AND, ANDS ASR, ASRS B BFC BFI BIC, BICS BKPT BL BLX BX CBNZ Operands {Rd,} Rn, Op2 {Rd,} Rn, Op2 {Rd,} Rn , #imm12 Rd, label {Rd,} Rn, Op2 Rd, Rm, label Rd, #lsb, #width Rd, Rn, #lsb, #width {Rd,} Rn, Op2 #imm label Rm Rm Rn, label Brief Description Add with carry Add Add Load PC-relative address Logical AND Arithmetic shift right Branch Bit field clear Bit field insert Bit clear Breakpoint Branch with link Branch indirect with link Branch indirect Compare and branch if non-zero Flags N,Z,C,V N,Z,C,V N,Z,C N,Z,C N,Z,C - June 12, 2014 115 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic CBZ CLREX CLZ CMN CMP CPSID CPSIE DMB DSB EOR, EORS ISB IT LDM LDMDB, LDMEA LDMFD, LDMIA LDR LDRB, LDRBT LDRD LDREX LDREXB LDREXH LDRH, LDRHT LDRSB, LDRSBT LDRSH, LDRSHT LDRT LSL, LSLS LSR, LSRS MLA MLS MOV, MOVS MOV, MOVW MOVT MRS MSR MUL, MULS MVN, MVNS NOP ORN, ORNS Operands Rn, label Rd, Rm Rn, Op2 Rn, Op2 i i {Rd,} Rn, Op2 Rn{!}, reglist Rn{!}, reglist Rn{!}, reglist Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, Rt2, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn] Rt, [Rn] Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn, #offset] Rd, Rm, Rd, Rm, Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra Rd, Op2 Rd, #imm16 Rd, #imm16 Rd, spec_reg spec_reg, Rm {Rd,} Rn, Rm Rd, Op2 {Rd,} Rn, Op2 Brief Description Flags Compare and branch if zero - Clear exclusive - Count leading zeros - Compare negative N,Z,C,V Compare N,Z,C,V Change processor state, disable - interrupts Change processor state, enable - interrupts Data memory barrier - Data synchronization barrier - Exclusive OR N,Z,C Instruction synchronization barrier - If-Then condition block - Load multiple registers, increment after - Load multiple registers, decrement - before Load multiple registers, increment after - Load register with word - Load register with byte - Load register with two bytes - Load register exclusive - Load register exclusive with byte - Load register exclusive with halfword - Load register with halfword - Load register with signed byte - Load register with signed halfword - Load register with word - Logical shift left N,Z,C Logical shift right N,Z,C Multiply with accumulate, 32-bit result - Multiply and subtract, 32-bit result - Move N,Z,C Move 16-bit constant N,Z,C Move top - Move from special register to general register Move from general register to special N,Z,C,V register Multiply, 32-bit result N,Z Move NOT N,Z,C No operation - Logical OR NOT N,Z,C 116 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic ORR, ORRS PKHTB, PKHBT POP PUSH QADD QADD16 QADD8 QASX QDADD QDSUB QSAX QSUB QSUB16 QSUB8 RBIT REV REV16 REVSH ROR, RORS RRX, RRXS RSB, RSBS SADD16 SADD8 SASX SBC, SBCS SBFX SDIV SEL SEV SHADD16 SHADD8 SHASX SHSAX SHSUB16 SHSUB8 Operands {Rd,} Rn, Op2 {Rd,} Rn, Rm, Op2 reglist reglist {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, Rn Rd, Rn Rd, Rn Rd, Rn Rd, Rm, Rd, Rm {Rd,} Rn, Op2 {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Op2 Rd, Rn, #lsb, #width {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Brief Description Flags Logical OR N,Z,C Pack halfword - Pop registers from stack - Push registers onto stack - Saturating add Q Saturating add 16 - Saturating add 8 - Saturating add and subtract with - exchange Saturating double and add Q Saturating double and subtract Q Saturating subtract and add with - exchange Saturating subtract Q Saturating subtract 16 - Saturating subtract 8 - Reverse bits - Reverse byte order in a word - Reverse byte order in each halfword - Reverse byte order in bottom halfword and sign extend Rotate right N,Z,C Rotate right with extend N,Z,C Reverse subtract N,Z,C,V Signed add 16 GE Signed add 8 GE Signed add and subtract with exchange GE Subtract with carry N,Z,C,V Signed bit field extract - Signed divide - Select bytes - Send event - Signed halving add 16 - Signed halving add 8 - Signed halving add and subtract with exchange Signed halving add and subtract with exchange Signed halving subtract 16 - Signed halving subtract 8 - June 12, 2014 117 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic SMLABB, SMLABT, SMLATB, SMLATT SMLAD, SMLADX SMLAL SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALD, SMLALDX SMLAWB,SMLAWT SMLSD SMLSDX SMLSLD SMLSLDX SMMLA SMMLS, SMMLR SMMUL, SMMULR SMUAD SMUADX SMULBB, SMULBT, SMULTB, SMULTT SMULL SMULWB, SMULWT SMUSD, SMUSDX SSAT SSAT16 SSAX SSUB16 SSUB8 STM Operands Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra RdLo, RdHi, Rn, Rm Rd, Rn, Rm, Ra Rd, Rn, Rm, Ra {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm RdLo, RdHi, Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, #n, Rm {,shift #s} Rd, #n, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rn{!}, reglist Brief Description Signed multiply accumulate long (halfwords) Flags Q Signed multiply accumulate dual Q Signed multiply with accumulate - (32x32+64), 64-bit result Signed multiply accumulate long - (halfwords) Signed multiply accumulate long dual - Signed multiply accumulate, word by Q halfword Signed multiply subtract dual Q Signed multiply subtract long dual Signed most significant word multiply accumulate Signed most significant word multiply subtract Signed most significant word multiply - Signed dual multiply add Q Signed multiply halfwords - Signed multiply (32x32), 64-bit result - Signed multiply by halfword - Signed dual multiply subtract - Signed saturate Q Signed saturate 16 Q Saturating subtract and add with GE exchange Signed subtract 16 - Signed subtract 8 - Store multiple registers, increment after - 118 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic STMDB, STMEA STMFD, STMIA STR STRB, STRBT STRD STREX STREXB STREXH STRH, STRHT STRSB, STRSBT STRSH, STRSHT STRT SUB, SUBS SUB, SUBW SVC SXTAB SXTAB16 SXTAH SXTB16 SXTB SXTH TBB TBH TEQ TST UADD16 UADD8 UASX UHADD16 UHADD8 UHASX UHSAX UHSUB16 UHSUB8 UBFX UDIV UMAAL Operands Rn{!}, reglist Rn{!}, reglist Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, Rt2, [Rn {, #offset}] Rt, Rt, [Rn {, #offset}] Rd, Rt, [Rn] Rd, Rt, [Rn] Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] Rt, [Rn {, #offset}] {Rd,} Rn, Op2 {Rd,} Rn, #imm12 #imm {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm,{,ROR #} {Rd,} Rn, Rm,{,ROR #} {Rd,} Rm {,ROR #n} {Rd,} Rm {,ROR #n} {Rd,} Rm {,ROR #n} [Rn, Rm] [Rn, Rm, LSL #1] Rn, Op2 Rn, Op2 {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm Rd, Rn, #lsb, #width {Rd,} Rn, Rm RdLo, RdHi, Rn, Rm Brief Description Flags Store multiple registers, decrement before Store multiple registers, increment after - Store register word - Store register byte - Store register two words - Store register exclusive - Store register exclusive byte - Store register exclusive halfword - Store register halfword - Store register signed byte - Store register signed halfword - Store register word - Subtract N,Z,C,V Subtract 12-bit constant N,Z,C,V Supervisor call - Extend 8 bits to 32 and add - Dual extend 8 bits to 16 and add - Extend 16 bits to 32 and add - Signed extend byte 16 - Sign extend a byte - Sign extend a halfword - Table branch byte - Table branch halfword - Test equivalence N,Z,C Test N,Z,C Unsigned add 16 GE Unsigned add 8 GE Unsigned add and subtract with GE exchange Unsigned halving add 16 - Unsigned halving add 8 - Unsigned halving add and subtract with exchange Unsigned halving subtract and add with exchange Unsigned halving subtract 16 - Unsigned halving subtract 8 - Unsigned bit field extract - Unsigned divide - Unsigned multiply accumulate - accumulate long (32x32+64), 64-bit result June 12, 2014 119 Texas Instruments-Production Data The Cortex-M4F Processor Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic UMLAL UMULL UQADD16 UQADD8 UQASX UQSAX UQSUB16 UQSUB8 USAD8 USADA8 USAT USAT16 USAX USUB16 USUB8 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH VABS.F32 VADD.F32 VCMP.F32 VCMPE.F32 Operands RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm, Ra Rd, #n, Rm {,shift #s} Rd, #n, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm, {,ROR #} {Rd,} Rn, Rm, {,ROR #} {Rd,} Rm, {,ROR #n} {Rd,} Rm, {,ROR #n} {Rd,} Rm, {,ROR #n} Sd, Sm {Sd,} Sn, Sm Sd, Sd, VCVT.S32.F32 Sd, Sm VCVT.S16.F32 Sd, Sd, #fbits VCVTR.S32.F32 Sd, Sm VCVT.F32.F16 Sd, Sm VCVTT.F32.F16 Sd, Sm VDIV.F32 VFMA.F32 {Sd,} Sn, Sm {Sd,} Sn, Sm Brief Description Flags Unsigned multiply with accumulate - (32x32+32+32), 64-bit result Unsigned multiply (32x 2), 64-bit result - Unsigned Saturating Add 16 - Unsigned Saturating Add 8 - Unsigned Saturating Add and Subtract with Exchange Unsigned Saturating Subtract and Add with Exchange Unsigned Saturating Subtract 16 - Unsigned Saturating Subtract 8 - Unsigned Sum of Absolute Differences - Unsigned Sum of Absolute Differences and Accumulate Unsigned Saturate Q Unsigned Saturate 16 Q Unsigned Subtract and add with GE Exchange Unsigned Subtract 16 GE Unsigned Subtract 8 GE Rotate, extend 8 bits to 32 and Add - Rotate, dual extend 8 bits to 16 and Add - Rotate, unsigned extend and Add - Halfword Zero extend a Byte - Unsigned Extend Byte 16 - Zero extend a Halfword - Floating-point Absolute - Floating-point Add - Compare two floating-point registers, or FPSCR one floating-point register and zero Compare two floating-point registers, or FPSCR one floating-point register and zero with Invalid Operation check Convert between floating-point and integer Convert between floating-point and fixed point Convert between floating-point and integer with rounding Converts half-precision value to - single-precision Converts single-precision register to half-precision Floating-point Divide - Floating-point Fused Multiply Accumulate - 120 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic VFNMA.F32 VFMS.F32 VFNMS.F32 VLDM.F<32|64> VLDR.F<32|64> VLMA.F32 VLMS.F32 VMOV.F32 VMOV VMOV VMOV VMOV VMOV VMRS VMSR VMUL.F32 VNEG.F32 VNMLA.F32 VNMLS.F32 VNMUL VPOP VPUSH VSQRT.F32 VSTM VSTR.F3<32|64> VSUB.F<32|64> WFE WFI Operands {Sd,} Sn, Sm {Sd,} Sn, Sm {Sd,} Sn, Sm Rn{!}, list , [Rn] {Sd,} Sn, Sm {Sd,} Sn, Sm Sd, #imm Sd, Sm Sn, Rt Sm, Sm1, Rt, Rt2 Dd[x], Rt Rt, Dn[x] Rt, FPSCR FPSCR, Rt {Sd,} Sn, Sm Sd, Sm {Sd,} Sn, Sm {Sd,} Sn, Sm {Sd,} Sn, Sm list list Sd, Sm Rn{!}, list Sd, [Rn] {Sd,} Sn, Sm - Brief Description Flags Floating-point Fused Negate Multiply Accumulate Floating-point Fused Multiply Subtract - Floating-point Fused Negate Multiply Subtract Load Multiple extension registers - Load an extension register from memory - Floating-point Multiply Accumulate - Floating-point Multiply Subtract - Floating-point Move immediate - Floating-point Move register - Copy ARM core register to single - precision Copy 2 ARM core registers to 2 single precision Copy ARM core register to scalar - Copy scalar to ARM core register - Move FPSCR to ARM core register or N,Z,C,V APSR Move to FPSCR from ARM Core register FPSCR Floating-point Multiply - Floating-point Negate - Floating-point Multiply and Add - Floating-point Multiply and Subtract - Floating-point Multiply - Pop extension registers - Push extension registers - Calculates floating-point Square Root - Floating-point register Store Multiple - Stores an extension register to memory - Floating-point Subtract - Wait for event - Wait for interrupt - June 12, 2014 121 Texas Instruments-Production Data Cortex-M4 Peripherals 3 3.1 Cortex-M4 Peripherals This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals, including: ■ SysTick (see page 123) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 124) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 125) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 125) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. ■ Floating-Point Unit (FPU) (see page 130) Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. Table 3-1 on page 122 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address 0xE000.E010-0xE000.E01F 0xE000.E100-0xE000.E4EF 0xE000.EF00-0xE000.EF03 0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F 0xE000.ED90-0xE000.EDB8 0xE000.EF30-0xE000.EF44 Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Floating Point Unit Description (see page ...) 123 124 125 125 130 Functional Description This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals: SysTick, NVIC, SCB, MPU, FPU. 122 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 3.1.1 System Timer (SysTick) Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. ■ SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC) divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick can be kept running during Deep-sleep mode by setting the CLK_SRC bit in the SysTick Control and Status Register (STCTRL) register and ensuring that the PIOSCPD bit in the Deep Sleep Clock Configuration (DSLPCLKCFG) register is clear. Ensure software uses aligned word accesses to access the SysTick registers. The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter is: 1. Program the value in the STRELOAD register. 2. Clear the STCURRENT register by writing to it with any value. 3. Configure the STCTRL register for the required operation. Note: When the processor is halted for debugging, the counter does not decrement. June 12, 2014 123 Texas Instruments-Production Data Cortex-M4 Peripherals 3.1.2 3.1.2.1 3.1.2.2 Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 78 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 124 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. Hardware and Software Control of Interrupts The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 146 or SWTRIG on page 156. A pending interrupt remains pending until one of the following: 124 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 3.1.3 3.1.4 ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 95 for more information). June 12, 2014 125 Texas Instruments-Production Data Cortex-M4 Peripherals 3.1.4.1 Table 3-2 on page 126 shows the possible MPU region attributes. See the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 130 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Strongly Ordered Device Normal Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; 0xE000ED98, MPU region number register ; Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register 126 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for prepacked information, meaning that the MPU Region Base Address (MPUBASE) register (see page 190) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: June 12, 2014 127 Texas Instruments-Production Data Cortex-M4 Peripherals 3.1.4.2 ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 192) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 128 shows. Figure 3-1. SRD Use Example Region 1 Base address of both regions Region 2, with subregions Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 128 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M4 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 130 for information on programming the MPU for TM4C123GH6PM implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX 000b 000 S C B Memory Type xa 0 0 Strongly Ordered xa 0 1 Device Shareability Shareable Shareable Other Attributes - 128 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable 001 0 0 0 Normal Not shareable 001 1 0 0 Normal Shareable 001 xa 0 1 Reserved encoding - 001 xa 1 0 Reserved encoding - 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable 010 xa 0 0 Device Not shareable 010 xa 0 1 Reserved encoding - 010 xa 1 xa Reserved encoding - 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable a. The MPU ignores the value of this bit. Other Attributes Outer and inner write-through. No write allocate. Outer and inner non-cacheable. Outer and inner write-back. Write and read allocate. Nonshared Device. Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. Table 3-4 on page 129 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB 00 01 10 11 Corresponding Cache Policy Non-cacheable Write back, write and read allocate Write through, no write allocate Write back, no write allocate Table 3-5 on page 129 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding AP Bit Field 000 001 010 Privileged Permissions No access RW RW Unprivileged Permissions No access No access RO 011 RW RW 100 Unpredictable Unpredictable 101 RO No access Description All accesses generate a permission fault. Access from privileged software only. Writes by unprivileged software generate a permission fault. Full access. Reserved. Reads by privileged software only. June 12, 2014 129 Texas Instruments-Production Data Cortex-M4 Peripherals 3.1.4.3 3.1.5 Table 3-5. AP Bit Field Encoding (continued) AP Bit Field 110 111 Privileged Permissions RO RO Unprivileged Permissions RO RO Description Read-only, by privileged or unprivileged software. Read-only, by privileged or unprivileged software. MPU Configuration for a Tiva™ C Series Microcontroller Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 130. Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers Memory Region Flash memory Internal SRAM External SRAM Peripherals TEX 000b 000b 000b 000b S C B Memory Type and Attributes 0 1 0 Normal memory, non-shareable, write-through 1 1 0 Normal memory, shareable, write-through 1 1 1 Normal memory, shareable, write-back, write-allocate 1 0 1 Device memory, shareable In current Tiva™ C Series microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 92 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 177 for more information. Floating-Point Unit (FPU) This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides: ■ 32-bit instructions for single-precision (C float) data-processing operations ■ Combined multiply and accumulate instructions for increased precision (Fused MAC) ■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root ■ Hardware support for denormals and all IEEE rounding modes ■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers ■ Decoupled three stage pipeline The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision extension registers can also be accessed as 16 doubleword registers for load, store, and move operations. 130 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 3.1.5.1 3.1.5.2 FPU Views of the Register Bank The FPU provides an extension register file containing 32 single-precision registers. These can be viewed as: ■ Sixteen 64-bit doubleword registers, D0-D15 ■ Thirty-two 32-bit single-word registers, S0-S31 ■ A combination of registers from the above views Figure 3-2. FPU Register Bank S0 D0 S1 S2 D1 S3 S4 D2 S5 S6 D3 S7 ... ... S28 D14 S29 S30 D15 S31 The mapping between the registers is as follows: ■ S<2n> maps to the least significant half of D ■ S<2n+1> maps to the most significant half of D For example, you can access the least significant half of the value in D6 by accessing S12, and the most significant half of the elements by accessing S13. Modes of Operation The FPU provides three modes of operation to accommodate a variety of applications. Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to the IEEE 754 standard in hardware. Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where the destination precision is smaller in magnitude than the minimum normal value before rounding, is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in FPSC indicates when a result flush occurs. Default NaN mode. Setting the DN bit in the FPSC register enables default NaN mode. In this mode, the result of any arithmetic data processing operation that involves an input NaN, or that generates a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS, June 12, 2014 131 Texas Instruments-Production Data Cortex-M4 Peripherals 3.1.5.3 3.1.5.4 3.1.5.5 VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits of an input NaN. Compliance with the IEEE 754 standard When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant with the IEEE 754 standard in hardware. No support code is required to achieve this compliance. Complete Implementation of the IEEE 754 standard The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE 754-2008 standard. Unsupported operations include, but are not limited to the following: ■ Remainder ■ Round floating-point number to integer-valued floating-point number ■ Binary-to-decimal conversions ■ Decimal-to-binary conversions ■ Direct comparison of single-precision and double-precision values The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with library functions. IEEE 754 standard implementation choices NaN handling All single-precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The below table shows the default NaN values. Sign 0 Fraction 0xFF Fraction bit [22] = 1, bits [21:0] are all zeros Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows: ■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data transfer operations, NaNs are transferred without raising the Invalid Operation exception. For the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change of sign if specified in the instructions, without causing the Invalid Operation exception. ■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions is the same as in full-compliance mode. 132 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 3.1.5.6 3.1.5.7 Table 3-7. QNaN and SNaN Handling Instruction Type Arithmetic CDP Default NaN Mode Off On With QNaN Operand With SNaN Operand The QNaN or one of the QNaN operands, IOCa set. The SNaN is quieted and the if there is more than one, is returned result NaN is determined by the rules according to the rules given in the ARM given in the ARM Architecture Reference Architecture Reference Manual. Manual. Default NaN returns. IOCa set. Default NaN returns. Non-arithmetic CDP Off/On NaN passes to destination with sign changed as appropriate. FCMP(Z) - Unordered compare. IOC set. Unordered compare. FCMPE(Z) - IOC set. Unordered compare. IOC set. Unordered compare. Load/store Off/On All NaNs transferred. a. IOC is the Invalid Operation exception flag, FPSCR[0]. Comparisons Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction (formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions. The flags used are chosen so that subsequent conditional execution of ARM instructions can test the predicates defined in the IEEE standard. Underflow The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions. In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode. When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If the operation does not produce a tiny result, it returns the computed result, and the UFC flag, FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set if the result was also inexact. Exceptions The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps. The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the status of one of the cumulative exception flags. For a description of these outputs, see the ARM Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM). The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the FP state, but does not save that state information to the stack. See the ARMv7-M Architecture Reference Manual (available from ARM) for more information. Enabling the FPU The FPU is disabled from reset. You must enable it before you can use any floating-point instructions. The processor must be in privileged mode to read from and write to the Coprocessor Access June 12, 2014 133 Texas Instruments-Production Data Cortex-M4 Peripherals Control (CPAC) register. The below example code sequence enables the FPU in both privileged and user modes. ; CPACR is located at address 0xE000ED88 LDR.W R0, =0xE000ED88 ; Read CPACR LDR R1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors ORR R1, R1, #(0xF << 20) ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete DSB ;reset pipeline now the FPU is enabled ISB 3.2 Register Map Table 3-8 on page 134 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-8. Peripherals Register Map Offset Name Type Reset Description System Timer (SysTick) Registers 0x010 STCTRL RW 0x0000.0004 0x014 STRELOAD RW - 0x018 STCURRENT RWC - Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 RW 0x0000.0000 0x104 EN1 RW 0x0000.0000 0x108 EN2 RW 0x0000.0000 0x10C EN3 RW 0x0000.0000 0x110 EN4 RW 0x0000.0000 0x180 DIS0 RW 0x0000.0000 0x184 DIS1 RW 0x0000.0000 0x188 DIS2 RW 0x0000.0000 0x18C DIS3 RW 0x0000.0000 0x190 DIS4 RW 0x0000.0000 0x200 PEND0 RW 0x0000.0000 0x204 PEND1 RW 0x0000.0000 SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register Interrupt 0-31 Set Enable Interrupt 32-63 Set Enable Interrupt 64-95 Set Enable Interrupt 96-127 Set Enable Interrupt 128-138 Set Enable Interrupt 0-31 Clear Enable Interrupt 32-63 Clear Enable Interrupt 64-95 Clear Enable Interrupt 96-127 Clear Enable Interrupt 128-138 Clear Enable Interrupt 0-31 Set Pending Interrupt 32-63 Set Pending See page 138 140 141 142 142 142 142 143 144 144 144 144 145 146 146 134 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 3-8. Peripherals Register Map (continued) Offset Name Type Reset Description 0x208 PEND2 0x20C PEND3 0x210 PEND4 0x280 UNPEND0 0x284 UNPEND1 0x288 UNPEND2 0x28C UNPEND3 0x290 UNPEND4 0x300 ACTIVE0 0x304 ACTIVE1 0x308 ACTIVE2 0x30C ACTIVE3 0x310 ACTIVE4 0x400 PRI0 0x404 PRI1 0x408 PRI2 0x40C PRI3 0x410 PRI4 0x414 PRI5 0x418 PRI6 0x41C PRI7 0x420 PRI8 0x424 PRI9 0x428 PRI10 0x42C PRI11 0x430 PRI12 0x434 PRI13 0x438 PRI14 0x43C PRI15 0x440 PRI16 0x444 PRI17 0x448 PRI18 RW 0x0000.0000 Interrupt 64-95 Set Pending RW 0x0000.0000 Interrupt 96-127 Set Pending RW 0x0000.0000 Interrupt 128-138 Set Pending RW 0x0000.0000 Interrupt 0-31 Clear Pending RW 0x0000.0000 Interrupt 32-63 Clear Pending RW 0x0000.0000 Interrupt 64-95 Clear Pending RW 0x0000.0000 Interrupt 96-127 Clear Pending RW 0x0000.0000 Interrupt 128-138 Clear Pending RO 0x0000.0000 Interrupt 0-31 Active Bit RO 0x0000.0000 Interrupt 32-63 Active Bit RO 0x0000.0000 Interrupt 64-95 Active Bit RO 0x0000.0000 Interrupt 96-127 Active Bit RO 0x0000.0000 Interrupt 128-138 Active Bit RW 0x0000.0000 Interrupt 0-3 Priority RW 0x0000.0000 Interrupt 4-7 Priority RW 0x0000.0000 Interrupt 8-11 Priority RW 0x0000.0000 Interrupt 12-15 Priority RW 0x0000.0000 Interrupt 16-19 Priority RW 0x0000.0000 Interrupt 20-23 Priority RW 0x0000.0000 Interrupt 24-27 Priority RW 0x0000.0000 Interrupt 28-31 Priority RW 0x0000.0000 Interrupt 32-35 Priority RW 0x0000.0000 Interrupt 36-39 Priority RW 0x0000.0000 Interrupt 40-43 Priority RW 0x0000.0000 Interrupt 44-47 Priority RW 0x0000.0000 Interrupt 48-51 Priority RW 0x0000.0000 Interrupt 52-55 Priority RW 0x0000.0000 Interrupt 56-59 Priority RW 0x0000.0000 Interrupt 60-63 Priority RW 0x0000.0000 Interrupt 64-67 Priority RW 0x0000.0000 Interrupt 68-71 Priority RW 0x0000.0000 Interrupt 72-75 Priority See page 146 146 147 148 148 148 148 149 150 150 150 150 151 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 154 154 154 June 12, 2014 135 Texas Instruments-Production Data Cortex-M4 Peripherals Table 3-8. Peripherals Register Map (continued) Offset Name Type Reset Description 0x44C PRI19 RW 0x450 PRI20 RW 0x454 PRI21 RW 0x458 PRI22 RW 0x45C PRI23 RW 0x460 PRI24 RW 0x464 PRI25 RW 0x468 PRI26 RW 0x46C PRI27 RW 0x470 PRI28 RW 0x474 PRI29 RW 0x478 PRI30 RW 0x47C PRI31 RW 0x480 PRI32 RW 0x484 PRI33 RW 0x488 PRI34 RW 0xF00 SWTRIG WO System Control Block (SCB) Registers 0x008 ACTLR RW 0xD00 CPUID RO 0xD04 INTCTRL RW 0xD08 VTABLE RW 0xD0C APINT RW 0xD10 SYSCTRL RW 0xD14 CFGCTRL RW 0xD18 SYSPRI1 RW 0xD1C SYSPRI2 RW 0xD20 SYSPRI3 RW 0xD24 SYSHNDCTRL RW 0xD28 FAULTSTAT RW1C 0xD2C HFAULTSTAT RW1C 0xD34 MMADDR RW 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Interrupt 76-79 Priority Interrupt 80-83 Priority Interrupt 84-87 Priority Interrupt 88-91 Priority Interrupt 92-95 Priority Interrupt 96-99 Priority Interrupt 100-103 Priority Interrupt 104-107 Priority Interrupt 108-111 Priority Interrupt 112-115 Priority Interrupt 116-119 Priority Interrupt 120-123 Priority Interrupt 124-127 Priority Interrupt 128-131 Priority Interrupt 132-135 Priority Interrupt 136-138 Priority Software Trigger Interrupt 0x0000.0000 0x410F.C241 0x0000.0000 0x0000.0000 0xFA05.0000 0x0000.0000 0x0000.0200 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 - Auxiliary Control CPU ID Base Interrupt Control and State Vector Table Offset Application Interrupt and Reset Control System Control Configuration and Control System Handler Priority 1 System Handler Priority 2 System Handler Priority 3 System Handler Control and State Configurable Fault Status Hard Fault Status Memory Management Fault Address See page 154 154 154 154 154 154 154 154 154 154 154 154 154 154 154 154 156 157 159 160 163 164 166 168 170 171 172 173 177 183 184 136 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 3-8. Peripherals Register Map (continued) Offset Name Type Reset Description 0xD38 FAULTADDR RW Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0xD94 MPUCTRL RW 0xD98 MPUNUMBER RW 0xD9C MPUBASE RW 0xDA0 MPUATTR RW 0xDA4 MPUBASE1 RW 0xDA8 MPUATTR1 RW 0xDAC MPUBASE2 RW 0xDB0 MPUATTR2 RW 0xDB4 MPUBASE3 RW 0xDB8 MPUATTR3 RW Floating-Point Unit (FPU) Registers 0xD88 CPAC RW 0xF34 FPCC RW 0xF38 FPCA RW 0xF3C FPDSC RW - Bus Fault Address 0x0000.0800 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 MPU Type MPU Control MPU Region Number MPU Region Base Address MPU Region Attribute and Size MPU Region Base Address Alias 1 MPU Region Attribute and Size Alias 1 MPU Region Base Address Alias 2 MPU Region Attribute and Size Alias 2 MPU Region Base Address Alias 3 MPU Region Attribute and Size Alias 3 0x0000.0000 0xC000.0000 0x0000.0000 Coprocessor Access Control Floating-Point Context Control Floating-Point Context Address Floating-Point Default Status Control See page 185 186 187 189 190 192 190 192 190 192 190 192 195 196 198 199 3.3 System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. June 12, 2014 137 Texas Instruments-Production Data Cortex-M4 Peripherals Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type RW, reset 0x0000.0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COUNT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CLK_SRC INTEN ENABLE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit/Field 31:17 16 15:3 2 Name reserved COUNT reserved CLK_SRC Type RO RO RO RW Reset 0x000 0 0x000 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Count Flag Value 0 1 Description The SysTick timer has not counted to 0 since the last time this bit was read. The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM® Debug Interface V5 Architecture Specification for more information on MasterType. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source Value Description 0 Precision internal oscillator (PIOSC) divided by 4 1 System clock 138 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name INTEN ENABLE Type RW RW Reset 0 Description Interrupt Enable Value 0 1 Description Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. An interrupt is generated to the NVIC when SysTick counts to 0. 0 Enable Value 0 1 Description The counter is disabled. Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. June 12, 2014 139 Texas Instruments-Production Data Cortex-M4 Peripherals Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. Note that in order to access this register correctly, the system clock must be faster than 8 MHz. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved RELOAD Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RELOAD Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:24 23:0 Name reserved RELOAD Type RO RW Reset Description 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. 140 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type RWC, reset - 31 30 29 28 27 26 25 reserved Type RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 15 14 13 12 11 10 9 Type RWC Reset 0 RWC 0 RWC 0 RWC 0 RWC 0 RWC 0 RWC 0 24 23 RO RWC 0 0 8 7 CURRENT RWC 0 RWC 0 22 RWC 0 6 RWC 0 21 RWC 0 5 RWC 0 20 19 CURRENT RWC 0 RWC 0 4 3 RWC 0 RWC 0 18 RWC 0 2 RWC 0 17 RWC 0 1 RWC 0 16 RWC 0 0 RWC 0 Bit/Field 31:24 23:0 Name reserved CURRENT Type RO RWC Reset Description 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00.0000 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 163. June 12, 2014 141 Texas Instruments-Production Data Cortex-M4 Peripherals Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C Note: This register can only be accessed from privileged mode. The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 (see page 143) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:0 Name INT Type Reset Description RW 0x0000.0000 Interrupt Enable Value 0 1 Description On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. 142 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 Note: This register can only be accessed from privileged mode. The EN4 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 128-138 Set Enable (EN4) Base 0xE000.E000 Offset 0x110 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:11 10:0 Name reserved INT Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0x0 Interrupt Enable Value 0 1 Description On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS4 register. June 12, 2014 143 Texas Instruments-Production Data Cortex-M4 Peripherals Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C Note: This register can only be accessed from privileged mode. The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 (see page 145) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:0 Name INT Type Reset Description RW 0x0000.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. 144 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 Note: This register can only be accessed from privileged mode. The DIS4 register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 128-138 Clear Enable (DIS4) Base 0xE000.E000 Offset 0x190 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:11 10:0 Name reserved INT Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0x0 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN4 register, disabling interrupt [n]. June 12, 2014 145 Texas Instruments-Production Data Cortex-M4 Peripherals Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C Note: This register can only be accessed from privileged mode. The PENDn registers force interrupts into the pending state and show which interrupts are pending. Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of PEND4 (see page 147) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:0 Name INT Type Reset Description RW 0x0000.0000 Interrupt Set Pending Value 0 1 Description On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. 146 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 Note: This register can only be accessed from privileged mode. The PEND4 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 128-138 Set Pending (PEND4) Base 0xE000.E000 Offset 0x210 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:11 10:0 Name reserved INT Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0x0 Interrupt Set Pending Value 0 1 Description On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND4 register. June 12, 2014 147 Texas Instruments-Production Data Cortex-M4 Peripherals Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C Note: This register can only be accessed from privileged mode. The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 (see page 149) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:0 Name INT Type Reset Description RW 0x0000.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 148 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 Note: This register can only be accessed from privileged mode. The UNPEND4 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Interrupt 128-138 Clear Pending (UNPEND4) Base 0xE000.E000 Offset 0x290 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:11 10:0 Name reserved INT Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0x0 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND4 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. June 12, 2014 149 Texas Instruments-Production Data Cortex-M4 Peripherals Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C Note: This register can only be accessed from privileged mode. The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of ACTIVE4 (see page 151) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 104 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:0 Name INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 150 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 Note: This register can only be accessed from privileged mode. The ACTIVE4 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 131. See Table 2-9 on page 104 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 128-138 Active Bit (ACTIVE4) Base 0xE000.E000 Offset 0x310 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:11 10:0 Name reserved INT Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x0 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. June 12, 2014 151 Texas Instruments-Production Data Cortex-M4 Peripherals Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430 Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434 Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438 Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C Note: This register can only be accessed from privileged mode. The PRIn registers (see also page 154) provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Bits 31:29 Bits 23:21 Bits 15:13 Bits 7:5 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n] See Table 2-9 on page 104 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 164) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. 152 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTD reserved INTC reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTB reserved INTA reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:29 28:24 23:21 20:16 15:13 12:8 7:5 4:0 Name INTD reserved INTC reserved INTB reserved INTA reserved Type RW RO RW RO RW RO RW RO Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 153 Texas Instruments-Production Data Cortex-M4 Peripherals Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440 Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444 Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448 Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450 Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454 Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458 Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460 Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468 Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470 Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474 Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478 Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480 Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484 Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488 Note: This register can only be accessed from privileged mode. The PRIn registers (see also page 152) provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Bits 31:29 Bits 23:21 Bits 15:13 Bits 7:5 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n] See Table 2-9 on page 104 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 164) indicates the position of the binary point that splits the priority and subpriority fields . These registers can only be accessed from privileged mode. 154 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Interrupt 64-67 Priority (PRI16) Base 0xE000.E000 Offset 0x440 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTD reserved INTC reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTB reserved INTA reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:29 28:24 23:21 20:16 15:13 12:8 7:5 4:0 Name INTD reserved INTC reserved INTB reserved INTA reserved Type RW RO RW RO RW RO RW RO Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 155 Texas Instruments-Production Data Cortex-M4 Peripherals Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 104 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 168) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INTID Type RO RO RO RO RO RO RO RO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7:0 Name reserved INTID Type RO WO Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. 156 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 65: Auxiliary Control (ACTLR), offset 0x008 Note: This register can only be accessed from privileged mode. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.E000 Offset 0x008 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DISOOFP DISFPCA reserved DISFOLD DISWBUF DISMCYC Type RO RO RO RO RO RO RW RW RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:10 9 8 7:3 2 Name reserved DISOOFP DISFPCA reserved DISFOLD Type RO RW RW RO RW Reset 0x00 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Disable Out-Of-Order Floating Point Disables floating-point instructions completing out of order with respect to integer instructions. Disable CONTROL.FPCA Disable automatic update of the FPCA bit in the CONTROL register. Important: Two bits control when FPCA can be enabled: the ASPEN bit in the Floating-Point Context Control (FPCC) register and the DISFPCA bit in the Auxiliary Control (ACTLR) register. 0x00 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Disable IT Folding Value Description 0 No effect. 1 Disables IT folding. In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. June 12, 2014 157 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 1 0 Name DISWBUF DISMCYC Type RW RW Reset 0 Description Disable Write Buffer Value Description 0 No effect. 1 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M4 processor. 0 Disable Interrupts of Multiple Cycle Instructions Value Description 0 No effect. 1 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. 158 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 66: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M4 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x410F.C241 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IMP VAR CON Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARTNO REV Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 Bit/Field 31:24 Name IMP Type RO Reset 0x41 Description Implementer Code Value Description 0x41 ARM 23:20 VAR RO 0x0 Variant Number Value Description 0x0 The rn value in the rnpn product revision identifier, for example, the 0 in r0p0. 19:16 CON RO 0xF Constant Value Description 0xF Always reads as 0xF. 15:4 PARTNO RO 0xC24 Part Number Value Description 0xC24 Cortex-M4 processor. 3:0 REV RO 0x1 Revision Number Value Description 0x1 The pn value in the rnpn product revision identifier, for example, the 1 in r0p1. June 12, 2014 159 Texas Instruments-Production Data Cortex-M4 Peripherals Register 67: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NMISET reserved PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved VECPEND Type RW RO RO RW WO RW WO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECPEND RETBASE reserved VECACT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31 30:29 28 Name NMISET reserved PENDSV Type RW RO RW Reset 0 0x0 0 Description NMI Set Pending Value Description 0 On a read, indicates an NMI exception is not pending. On a write, no effect. 1 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PendSV Set Pending Value Description 0 On a read, indicates a PendSV exception is not pending. On a write, no effect. 1 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 160 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 27 26 25 24 23 22 21:20 Name UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved Type WO RW WO RO RO RO RO Reset 0 0 0 0 0 0 0x0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to the PENDSTCLR bit. SysTick Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 161 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 19:12 11 10:8 7:0 Name VECPEND RETBASE reserved VECACT Type RO RO RO RO Reset 0x00 Description Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x9A Interrupt Vector 138 0 0x0 0x00 Return to Base Value Description 0 There are preempted active exceptions to execute. 1 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 81). 162 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 68: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OFFSET Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET reserved Type RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:10 9:0 Name OFFSET reserved Type RW RO Reset Description 0x000.00 Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 138 interrupts, the offset must be aligned on a 1024-byte boundary. 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 163 Texas Instruments-Production Data Cortex-M4 Peripherals Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-9 on page 164 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-9. Interrupt Priority Levels PRIGROUP Bit Field Binary Pointa Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type RW, reset 0xFA05.0000 31 30 29 28 27 26 25 Type RW RW RW RW RW RW RW Reset 1 1 1 1 1 0 1 24 23 VECTKEY RW RW 0 0 15 14 13 12 11 10 9 8 7 ENDIANESS reserved PRIGROUP Type RO RO RO RO RO RW RW RW RO Reset 0 0 0 0 0 0 0 0 0 22 21 20 RW RW RW 0 0 0 6 5 4 reserved RO RO RO 0 0 0 19 18 17 16 RW RW RW RW 0 1 0 1 3 2 1 0 SYSRESREQ VECTCLRACT VECTRESET RO WO WO WO 0 0 0 0 Bit/Field 31:16 15 14:11 Name VECTKEY ENDIANESS reserved Type RW RO RO Reset 0xFA05 0 0x0 Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. Data Endianess The Tiva™ C Series implementation uses only little-endian mode so this is cleared to 0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 164 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 10:8 7:3 2 1 0 Name PRIGROUP reserved SYSRESREQ VECTCLRACT VECTRESET Type RW RO WO WO WO Reset 0x0 0x0 0 0 0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-9 on page 164 for more information). Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Reset Request Value Description 0 No effect. 1 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. June 12, 2014 165 Texas Instruments-Production Data Cortex-M4 Peripherals Register 70: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved Type RO RO RO RO RO RO RO RO RO RO RO RW RO RW RW RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:5 4 3 2 Name reserved SEVONPEND reserved SLEEPDEEP Type RO RW RO RW Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Wake Up on Pending Value Description 0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. 166 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name SLEEPEXIT reserved Type RW RO Reset 0 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 167 Texas Instruments-Production Data Cortex-M4 Peripherals Register 71: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 156). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type RW, reset 0x0000.0200 31 30 29 28 27 Type RO RO RO RO RO Reset 0 0 0 0 0 15 14 13 12 11 reserved Type RO RO RO RO RO Reset 0 0 0 0 0 26 25 24 23 22 21 reserved RO RO RO RO RO RO 0 0 0 0 0 0 10 9 8 7 6 5 STKALIGN BFHFNMIGN reserved RO RW RW RO RO RO 0 1 0 0 0 0 20 19 18 17 16 RO RO RO RO RO 0 0 0 0 0 4 3 2 1 0 DIV0 UNALIGNED reserved MAINPEND BASETHR RW RW RO RW RW 0 0 0 0 0 Bit/Field 31:10 9 8 7:5 Name reserved STKALIGN BFHFNMIGN reserved Type RO RW RW RO Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 168 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name DIV0 UNALIGNED reserved MAINPEND BASETHR Type RW RW RO RW RW Reset 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. 0 Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. 1 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Allow Main Interrupt Trigger Value Description 0 Disables unprivileged software access to the SWTRIG register. 1 Enables unprivileged software access to the SWTRIG register (see page 156). 0 Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 110 for more information). June 12, 2014 169 Texas Instruments-Production Data Cortex-M4 Peripherals Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved USAGE reserved Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS reserved MEM reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:24 23:21 20:16 15:13 12:8 7:5 4:0 Name reserved USAGE reserved BUS reserved MEM reserved Type RO RW RO RW RO RW RO Reset 0x00 0x0 0x0 0x0 0x0 0x0 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 170 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SVC reserved Type RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:29 28:0 Name SVC reserved Type Reset Description RW 0x0 SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 171 Texas Instruments-Production Data Cortex-M4 Peripherals Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TICK reserved PENDSV reserved Type RW RW RW RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEBUG reserved Type RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:29 28:24 23:21 20:8 7:5 4:0 Name TICK reserved PENDSV reserved DEBUG reserved Type RW RO RW RO RW RO Reset Description 0x0 SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 172 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 75: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Type Reset 15 SVC RW 0 14 BUSP RW 0 13 12 11 MEMP USAGEP TICK RW RW RW 0 0 0 10 9 PNDSV reserved RW RO 0 0 8 MON RW 0 23 RO 0 7 SVCA RW 0 22 21 20 RO RO RO 0 0 0 6 5 4 reserved RO RO RO 0 0 0 19 18 17 USAGE BUS RO RW RW 0 0 0 16 MEM RW 0 3 2 1 USGA reserved BUSA RW RO RW 0 0 0 0 MEMA RW 0 Bit/Field 31:19 18 Name reserved USAGE Type RO RW Reset 0x000 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. 17 BUS RW 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. June 12, 2014 173 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 16 15 14 13 12 11 Name MEM SVC BUSP MEMP USAGEP TICK Type RW RW RW RW RW RW Reset 0 Description Memory Management Fault Enable Value Description 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. 0 SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 174 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 10 9 8 7 6:4 3 2 1 Name PNDSV reserved MON SVCA reserved USGA reserved BUSA Type RW RO RW RW RO RW RO RW Reset 0 0 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Monitor Active Value Description 0 The Debug monitor is not active. 1 The Debug monitor is active. 0 SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. June 12, 2014 175 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 0 Name MEMA Type RW Reset 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 176 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: ■ The complete FAULTSTAT register, with a word access to offset 0xD28 ■ The MFAULTSTAT, with a byte access to offset 0xD28 ■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 ■ The BFAULTSTAT, with a byte access to offset 0xD29 ■ The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type RW1C, reset 0x0000.0000 31 30 29 28 27 26 reserved Type RO RO RO RO RO RO Reset 0 0 0 0 0 0 25 24 23 DIV0 UNALIGN RW1C RW1C RO 0 0 0 22 21 reserved RO RO 0 0 20 19 18 17 16 NOCP INVPC INVSTAT UNDEF RO RW1C RW1C RW1C RW1C 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BFARV reserved BLSPERR BSTKE BUSTKE IMPRE PRECISE IBUS MMARV reserved MLSPERR MSTKE MUSTKE reserved DERR Type RW1C RO RW1C RW1C RW1C RW1C RW1C RW1C RW1C RO RW1C RW1C RW1C RO RW1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERR RW1C 0 Bit/Field 31:26 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 177 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 25 24 23:20 19 18 Name DIV0 UNALIGN reserved NOCP INVPC Type RW1C RW1C RO RW1C RW1C Reset 0 0 0x00 0 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 168). This bit is cleared by writing a 1 to it. Unaligned Access Usage Fault Value Description 0 No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 168). This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. No Coprocessor Usage Fault Value Description 0 A usage fault has not been caused by attempting to access a coprocessor. 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. Invalid PC Load Usage Fault Value Description 0 A usage fault has not been caused by attempting to load an invalid PC value. 1 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. 178 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 17 16 15 14 13 Name INVSTAT UNDEF BFARV reserved BLSPERR Type RW1C RW1C RW1C RO RW1C Reset 0 0 0 0 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. 1 The processor has attempted to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. Bus Fault Address Register Valid Value Description 0 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Fault on Floating-Point Lazy State Preservation Value Description 0 No bus fault has occurred during floating-point lazy state preservation. 1 A bus fault has occurred during floating-point lazy state preservation. This bit is cleared by writing a 1 to it. June 12, 2014 179 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 12 11 10 9 Name BSTKE BUSTKE IMPRE PRECISE Type RW1C RW1C RW1C RW1C Reset 0 0 0 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. Unstack Bus Fault Value Description 0 No bus fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. 1 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. 1 A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 180 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 8 7 6 5 4 Name IBUS MMARV reserved MLSPERR MSTKE Type RW1C RW1C RO RW1C RW1C Reset 0 0 0 0 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. Memory Management Fault Address Register Valid Value Description 0 The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Memory Management Fault on Floating-Point Lazy State Preservation Value Description 0 No memory management fault has occurred during floating-point lazy state preservation. 1 No memory management fault has occurred during floating-point lazy state preservation. This bit is cleared by writing a 1 to it. Stack Access Violation Value Description 0 No memory management fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more access violations. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. June 12, 2014 181 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 3 2 1 0 Name MUSTKE reserved DERR IERR Type RW1C RO RW1C RW1C Reset 0 0 0 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Access Violation Value Description 0 A data access violation has not occurred. 1 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. Instruction Access Violation Value Description 0 An instruction access violation has not occurred. 1 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 182 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type RW1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED reserved Type RW1C RW1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VECT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31 30 29:2 1 0 Name DBG FORCED reserved VECT reserved Type RW1C RW1C RO RW1C RO Reset 0 0 0x00 0 0 Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. Forced Hard Fault Value Description 0 No forced hard fault has occurred. 1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 183 Texas Instruments-Production Data Cortex-M4 Peripherals Register 78: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 177). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - Bit/Field 31:0 Name ADDR Type RW Reset - Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. 184 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 79: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 177). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - Bit/Field 31:0 Name ADDR Type RW Reset - Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. June 12, 2014 185 Texas Instruments-Production Data Cortex-M4 Peripherals Register 80: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved IREGION Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DREGION reserved SEPARATE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:24 23:16 15:8 Name reserved IREGION DREGION Type RO RO RO Reset 0x00 0x00 0x08 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 7:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 SEPARATE RO 0 Separate or Unified MPU Value Description 0 Indicates the MPU is unified. 186 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 81: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 92. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 95 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIVDEFEN HFNMIENA ENABLE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:3 Name reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 187 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 2 1 0 Name PRIVDEFEN HFNMIENA ENABLE Type RW RW RW Reset 0 0 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description 0 The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. 188 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 82: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 190). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NUMBER Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:3 2:0 Name reserved NUMBER Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. June 12, 2014 189 Texas Instruments-Production Data Cortex-M4 Peripherals Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR VALID reserved REGION Type RW RW RW RW RW RW RW RW RW RW RW WO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:5 Name ADDR Type Reset Description RW 0x0000.000 Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 190 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2:0 Name VALID reserved REGION Type WO RO RW Reset 0 0 0x0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. June 12, 2014 191 Texas Instruments-Production Data Cortex-M4 Peripherals Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 88: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 89: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 90: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-10 on page 192 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-10. Example SIZE Field Values SIZE Encoding Region Size Value of Na Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - 11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size region occupies the complete memory map. a. Refers to the N parameter in the MPUBASE register (see page 190). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved XN reserved AP reserved TEX S C B Type RO RO RO RW RO RW RW RW RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRD reserved SIZE ENABLE Type RW RW RW RW RW RW RW RW RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 192 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 31:29 28 27 26:24 23:22 21:19 18 17 16 15:8 7:6 5:1 Name reserved XN reserved AP reserved TEX S C B SRD reserved SIZE Type RO RW RO RW RO RW RW RW RW RW RO RW Reset 0x00 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 0 0 0x0 0x0 0 0 0 0x00 0x0 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Access Privilege For information on using this bit field, see Table 3-5 on page 129. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Type Extension Mask For information on using this bit field, see Table 3-3 on page 128. Shareable For information on using this bit, see Table 3-3 on page 128. Cacheable For information on using this bit, see Table 3-3 on page 128. Bufferable For information on using this bit, see Table 3-3 on page 128. Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called “Subregions” on page 128 for more information. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-10 on page 192 for more information. June 12, 2014 193 Texas Instruments-Production Data Cortex-M4 Peripherals Bit/Field 0 Name ENABLE Type RW Reset 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. 3.7 Floating-Point Unit (FPU) Register Descriptions This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address offset. 194 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 91: Coprocessor Access Control (CPAC), offset 0xD88 The CPAC register specifies the access privileges for coprocessors. Coprocessor Access Control (CPAC) Base 0xE000.E000 Offset 0xD88 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CP11 CP10 reserved Type RO RO RO RO RO RO RO RO RW RW RW RW RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:24 23:22 Name reserved CP11 Type RO RW Reset 0x00 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CP11 Coprocessor Access Privilege Value Description 0x0 Access Denied Any attempted access generates a NOCP Usage Fault. 0x1 Privileged Access Only An unprivileged access generates a NOCP fault. 0x2 Reserved The result of any access is unpredictable. 0x3 Full Access 21:20 CP10 RW 0x00 CP10 Coprocessor Access Privilege Value Description 0x0 Access Denied Any attempted access generates a NOCP Usage Fault. 0x1 Privileged Access Only An unprivileged access generates a NOCP fault. 0x2 Reserved The result of any access is unpredictable. 0x3 Full Access 19:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 195 Texas Instruments-Production Data Cortex-M4 Peripherals Register 92: Floating-Point Context Control (FPCC), offset 0xF34 The FPCC register sets or returns FPU control data. Floating-Point Context Control (FPCC) Base 0xE000.E000 Offset 0xF34 Type RW, reset 0xC000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ASPEN LSPEN reserved Type RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MONRDY reserved BFRDY MMRDY HFRDY THREAD reserved USER LSPACT Type RO RO RO RO RO RO RO RW RO RW RW RW RW RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31 30 29:9 8 7 6 5 Name ASPEN LSPEN reserved MONRDY reserved BFRDY MMRDY Type RW RW RO RW RO RW RW Reset 1 Description Automatic State Preservation Enable When set, enables the use of the FRACTV bit in the CONTROL register on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. Important: Two bits control when FPCA can be enabled: the ASPEN bit in the Floating-Point Context Control (FPCC) register and the DISFPCA bit in the Auxiliary Control (ACTLR) register. 1 0x00 0 0 0 0 Lazy State Preservation Enable When set, enables automatic lazy state preservation for floating-point context. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Monitor Ready When set, DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Fault Ready When set, BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. Memory Management Fault Ready When set, MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 196 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name HFRDY THREAD reserved USER LSPACT Type RW RW RO RW RW Reset 0 0 0 0 0 Description Hard Fault Ready When set, priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. Thread Mode When set, mode was Thread Mode when the floating-point stack frame was allocated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. User Privilege Level When set, privilege level was user when the floating-point stack frame was allocated. Lazy State Preservation Active When set, Lazy State preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. June 12, 2014 197 Texas Instruments-Production Data Cortex-M4 Peripherals Register 93: Floating-Point Context Address (FPCA), offset 0xF38 The FPCA register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. Floating-Point Context Address (FPCA) Base 0xE000.E000 Offset 0xF38 Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDRESS Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRESS reserved Type RW RW RW RW RW RW RW RW RW RW RW RW RW RO RO RO Reset - - - - - - - - - - - - - 0 0 0 Bit/Field 31:3 2:0 Name ADDRESS reserved Type RW RO Reset - 0x00 Description Address The location of the unpopulated floating-point register space allocated on an exception stack frame. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 198 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 94: Floating-Point Default Status Control (FPDSC), offset 0xF3C The FPDSC register holds the default values for the Floating-Point Status Control (FPSC) register. Floating-Point Default Status Control (FPDSC) Base 0xE000.E000 Offset 0xF3C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved AHP DN FZ RMODE reserved Type RO RO RO RO RO RW RW RW RW RW RO RO RO RO RO RO Reset 0 0 0 0 0 - - - - - 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:27 26 25 24 23:22 Name reserved AHP DN FZ RMODE Type RO RW RW RW RW Reset 0x00 - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. AHP Bit Default This bit holds the default value for the AHP bit in the FPSC register. DN Bit Default This bit holds the default value for the DN bit in the FPSC register. FZ Bit Default This bit holds the default value for the FZ bit in the FPSC register. RMODE Bit Default This bit holds the default value for the RMODE bit field in the FPSC register. Value Description 0x0 Round to Nearest (RN) mode 0x1 Round towards Plus Infinity (RP) mode 0x2 Round towards Minus Infinity (RM) mode 0x3 Round towards Zero (RZ) mode 21:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 199 Texas Instruments-Production Data JTAG Interface 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The TM4C123GH6PM JTAG controller works with the ARM JTAG controller built into the Cortex-M4F core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while JTAG instructions select the TDO output. The multiplexer is controlled by the JTAG controller, which has comprehensive programming for the ARM, Tiva™ C Series microcontroller, and unimplemented JTAG instructions. The TM4C123GH6PM JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Embedded Trace Macrocell (ETM) for instruction trace capture – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 200 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TDO Cortex-M4F Debug Port 4.2 Signal Description The following table lists the external signals of the JTAG/SWD controller and describes the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 656. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 671) is set to choose the JTAG/SWD function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 688) to assign the JTAG/SWD controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 649. Table 4-1. JTAG_SWD_SWO Signals (64LQFP) Pin Name SWCLK SWDIO SWO TCK TDI TDO Pin Number Pin Mux / Pin Assignment 52 PC0 (1) 51 PC1 (1) 49 PC3 (1) 52 PC0 (1) 50 PC2 (1) 49 PC3 (1) Pin Type I I/O O I I O Buffer Typea Description TTL JTAG/SWD CLK. TTL JTAG TMS and SWDIO. TTL JTAG TDO and SWO. TTL JTAG/SWD CLK. TTL JTAG TDI. TTL JTAG TDO and SWO. June 12, 2014 201 Texas Instruments-Production Data JTAG Interface Table 4-1. JTAG_SWD_SWO Signals (64LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Pin Type Buffer Typea Description Assignment TMS 51 PC1 (1) I TTL JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 201. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 208 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 1363 for JTAG timing diagrams. Note: Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST input have any effect on the JTAG module. The pin configurations are reset by both the RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset Sources” on page 213 for more information on reset. 4.3.1 JTAG Interface Pins The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their associated state after a power-on reset or reset caused by the RST input are given in Table 4-2. Detailed information on each pin follows. Note: The following pins are configured as JTAG port pins out of reset. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 649 for information on how to reprogram the configuration of these pins. Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion Pin Name TCK TMS TDI TDO Data Direction Input Input Input Output Internal Pull-Up Internal Pull-Down Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Drive Strength N/A N/A N/A 2-mA driver Drive Value N/A N/A N/A High-Z 202 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source (see page 677 and page 679). Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 204. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see page 677). Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 677). Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and June 12, 2014 203 Texas Instruments-Production Data JTAG Interface 4.3.2 pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states (see page 677 and page 679). JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 1 0 Select DR Scan 1 0 Capture DR 1 0 Shift DR 1 0 Exit 1 DR 1 0 Pause DR 1 0 Exit 2 DR 0 1 Update DR 10 Select IR Scan 1 0 Capture IR 1 0 Shift IR 1 0 Exit 1 IR 1 0 Pause IR 1 0 Exit 2 IR 0 1 Update IR 10 4.3.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller's CAPTURE states and allows this information to be shifted out on TDO during the TAP controller's SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 208. 204 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 Operational Considerations Certain operational parameters must be considered when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. GPIO Functionality When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors (PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select (GPIOAFSEL) register) on the JTAG/SWD pins. See page 671, page 677, page 679, and page 682. It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the TM4C123GH6PM microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the TM4C123GH6PM Flash Programmer "Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more information. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1329 for pin numbers). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 671), GPIO Pull Up Select (GPIOPUR) register (see page 677), GPIO Pull-Down Select (GPIOPDR) register (see page 679), and GPIO Digital Enable (GPIODEN) register (see page 682) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 684) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 685) have been set. Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. Recovering a "Locked" Microcontroller Note: Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile Register Programming” on page 532 to their factory default values. The mass erase of the Flash memory caused by the sequence below occurs prior to the non-volatile registers being restored. June 12, 2014 205 Texas Instruments-Production Data JTAG Interface 4.3.4.4 In addition, the EEPROM is erased and its wear-leveling counters are returned to factory default values when performing the sequence below. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence is: 1. Assert and hold the RST signal. 2. Apply power to the device. 3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 207. 4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 207. 5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 8. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 9. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 10. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 11. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 12. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 13. Release the RST signal. 14. Wait 400 ms. 15. Power-cycle the microcontroller. ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M4F core without having to perform, or have any knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequence of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Debug Interface V5 Architecture Specification. 206 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode before sending the switch sequence, the SWD goes into the line reset state. To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating mode, perform a SWD READID operation. The ID value can be compared against the device's known ID to verify the switch. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset state. To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The DR value can be compared against the device's known IDCODE to verify the switch. 4.4 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. To return the pins to their JTAG functions, enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. June 12, 2014 207 Texas Instruments-Production Data JTAG Interface 4.5 4.5.1 4.5.1.1 4.5.1.2 In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. Register Descriptions The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within the JTAG controller are all accessed serially through the TAP Controller. These registers include the Instruction Register and the six Data Registers. Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 4-3. JTAG Instruction Register Commands IR[3:0] 0x0 0x2 0x8 0xA 0xB 0xE 0xF All Others Instruction EXTEST SAMPLE / PRELOAD ABORT DPACC APACC IDCODE BYPASS Reserved Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. Shifts data into the ARM Debug Port Abort Register. Shifts data into and out of the ARM DP Access Register. Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. With tests that drive known values out of the controller, this instruction can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while 208 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 4.5.1.3 4.5.1.4 4.5.1.5 4.5.1.6 4.5.1.7 the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST instruction to drive data into or out of the controller. See “Boundary Scan Data Register” on page 210 for more information. ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 211 for more information. DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. See “DPACC Data Register” on page 211 for more information. APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. See “APACC Data Register” on page 211 for more information. IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 210 for more information. BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 210 for more information. June 12, 2014 209 Texas Instruments-Production Data JTAG Interface 4.5.2 4.5.2.1 Data Registers The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections. IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This definition allows auto-configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M4F during debug. Figure 4-3. IDCODE Register Format 31 28 27 TDI Version Part Number 12 11 Manufacturer ID 10 1 TDO 4.5.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This definition allows auto-configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format 0 TDI 0 TDO 4.5.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as shown in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST instruction. The EXTEST instruction forces data out of the controller. 210 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 4.5.2.4 4.5.2.5 4.5.2.6 Figure 4-5. Boundary Scan Register Format TDI I N O U T O ... I E N O U T O E I N O U T O ... E I N O U T O TDO E 1st GPIO mth GPIO (m+1)th GPIO GPIO nth APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. June 12, 2014 211 Texas Instruments-Production Data System Control 5 System Control System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes. 5.1 Signal Description The following table lists the external signals of the System Control module and describes the function of each. The NMI signal is the alternate function for two GPIO signals and functions as a GPIO after reset. The NMI pins are under commit protection and require a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 656. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 671) should be set to choose the NMI function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 688) to assign the NMI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 649. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Table 5-1. System Control & Clocks Signals (64LQFP) Pin Name Pin Number Pin Mux / Pin Pin Type Buffer Typea Description Assignment NMI 10 PD7 (8) I TTL Non-maskable interrupt. 28 PF0 (8) OSC0 40 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 41 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 38 fixed I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 5.2 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 212 ■ Local control, such as reset (see “Reset Control” on page 213), power (see “Power Control” on page 218) and clock control (see “Clock Control” on page 219) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 227 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, memory sizes, and peripherals present on the device. The Device Identification 0 (DID0) (page 238) and Device Identification 1 (DID1) (page 240) registers provide details about the device's version, package, temperature range, and so on. The Peripheral Present registers starting at System Control offset 0x300, such as the Watchdog Timer Peripheral Present (PPWD) register, provide information on how many of each type of module are included on the device. Finally, 212 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.2 5.2.2.1 information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in each peripheral's register space in the Peripheral Properties registers, such as the GPTM Peripheral Properties (GPTMPP) register. Previous devices used the Device Capabilities (DC0-DC9) registers for information about the peripherals and their capabilities. These registers are present on this device for backward software capability, but provide no information about peripherals that were not available on older devices. Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. Reset Sources The TM4C123GH6PM microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 214). 2. External reset input pin (RST) assertion (see page 215). 3. A brown-out detection that can be caused by any of the following events: (see page 216). ■ V DD under BOR0. The trigger value is the highest VDD voltage level for BOR0. ■ VDD under BOR1. The trigger value is the highest VDD voltage level for BOR1. 4. Software-initiated reset (with the software reset registers) (see page 217). 5. A watchdog timer reset condition violation (see page 217). 6. MOSC failure (see page 218). Table 5-2 provides a summary of results of the various reset operations. Table 5-2. Reset Sources Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset? Power-On Reset Yes Yes Yes RST Yes Pin Config Only Yes Brown-Out Reset Yes Pin Config Only Yes Software System Request Yes Pin Config Only Yes Reset using the SYSRESREQ bit in the APINT register. Software System Request Yes Reset using the VECTRESET bit in the APINT register. Software Peripheral Reset No Pin Config Only Pin Config Only No Yesa Watchdog Reset Yes Pin Config Only Yes MOSC Failure Reset Yes Pin Config Only Yes a. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR June 12, 2014 213 Texas Instruments-Production Data System Control 5.2.2.2 is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator. A bit in the RESC register can be cleared by writing a 0. At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot Configuration (BOOTCFG) register. At reset, the following sequence is performed: 1. The BOOTCFG register is read. If the EN bit is clear, the ROM Boot Loader is executed. 2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. f then EN bit is set or the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. Note: If the device fails the initialization phase, it toggles the TDO output pin as an indication the device is not executing. This feature is provided for debug purposes. For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01, then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the application in Flash memory is executed if the reset vector at location 0x0000.0004 is not 0xFFFF.FFFF. Otherwise, the ROM boot loader is executed. Power-On Reset (POR) Note: The JTAG controller can only be reset by the power-on reset. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VVDD_POK). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see “Power and Brown-Out” on page 1365). For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 215. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. The Power-On Reset timing is shown in “Power and Brown-Out” on page 1365. 214 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.2.3 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 215. The RST input has filtering which requires a minimum pulse width in order for the reset pulse to be recognized, see Table 24-11 on page 1370. Figure 5-1. Basic RST Configuration Tiva™ Microcontroller VDD RPU RST RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals. The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then deasserted (see “Reset” on page 1370). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 215. Figure 5-2. External Circuitry to Extend Power-On Reset Tiva™ Microcontroller VDD RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF June 12, 2014 215 Texas Instruments-Production Data System Control If the application requires the use of an external reset switch, Figure 5-3 on page 216 shows the proper circuitry to use. Figure 5-3. Reset Circuit Controlled by Switch Tiva™ Microcontroller VDD RPU RST RS C1 5.2.2.4 Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 24-11 on page 1371. Brown-Out Reset (BOR) The microcontroller provides a brown-out detection circuit that triggers if any of the following occur: ■ VDD under BOR0. The external VDD supply voltage is below the specified VDD BOR0 value. The trigger value is the highest VDD voltage level for BOR0. ■ VDD under BOR1. The external VDD supply voltage is below the specified VDD BOR1 value. The trigger value is the highest VDD voltage level for BOR1. The application can identify that a BOR event caused a reset by reading the Reset Cause (RESC) register. When a brown-out condition is detected, the default condition is to generate a reset. The BOR events can also be programmed to generate an interrupt by clearing the BOR0 bit or BOR1 bit in the Power-On and Brown-Out Reset Control (PBORCTL) register. The brown-out reset sequence is as follows: 1. When VDD drops below VBORnTH, an internal BOR condition is set. Please refer to “Power and Brown-Out” on page 1365 for VBORnTH value. 2. If the BOR condition exists, an internal reset is asserted. 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. 216 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.2.5 5.2.2.6 The internal Brown-Out Reset timing is shown in “Power and Brown-Out” on page 1365. Software Reset Software can reset a specific peripheral or generate a reset to the entire microcontroller. Peripherals can be individually reset by software via peripheral-specific reset registers available beginning at System Control offset 0x500 (for example the Watchdog Timer Software Reset (SRWD) register). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system reset sequence is as follows: 1. A software microcontroller reset is initiated by setting the SYSRESREQ bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The core only can be reset by software by setting the VECTRESET bit in the APINT register. The software-initiated core reset sequence is as follows: 1. A core reset is initiated by setting the VECTRESET bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 24-12 on page 1371. Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The TM4C123GH6PM microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module is in a different clock domain, register accesses must have a time delay between them. The watchdog timer can be configured to generate an interrupt or a non-maskable interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. June 12, 2014 217 Texas Instruments-Production Data System Control 5.2.3 5.2.3.1 5.2.3.2 5.2.4 3. The internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. For more information on the Watchdog Timer module, see “Watchdog Timers” on page 774. The watchdog reset timing is shown in Figure 24-13 on page 1371. Non-Maskable Interrupt The microcontroller has four sources of non-maskable interrupt (NMI): ■ The assertion of the NMI signal ■ A main oscillator verification error ■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M4F (see page 160). ■ The Watchdog module time-out interrupt when the INTTYPE bit in the Watchdog Control (WDTCTL) register is set (see page 780). Software must check the cause of the interrupt in order to distinguish among the sources. NMI Pin The NMI signal is an alternate function for either GPIO port pin PD7 or PF0. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 649. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see page 685. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt sequence. Main Oscillator Verification Failure The TM4C123GH6PM microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred to the NMI handler, or an interrupt is generated. The MOSCIM bit in the MOSCCTL register determines which action occurs. In either case, the system clock source is automatically switched to the PIOSC. If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described in more detail in “Main Oscillator Verification Circuit” on page 226. Power Control The TM4C123GH6PM microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. An external LDO may not be used. Note: VDDA must be supplied with a voltage that meets the specification in Table 24-5 on page 1360, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the clock circuitry. 218 June 12, 2014 Texas Instruments-Production Data Figure 5-4. Power Architecture Tiva™ TM4C123GH6PM Microcontroller VDDC VDDC +3.3V VDD VDD +3.3V VDDA VDDA Internal Logic and PLL LDO Voltage Regulator I/O Buffers Analog Circuits GND GND GND GND GNDA GNDA 5.2.5 5.2.5.1 Clock Control System control determines the control of clocks in this part. Fundamental Clock Sources There are multiple clock sources for use in the microcontroller: ■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following POR. It does not require the use of any external components and provides a 16-MHz clock with ±1% accuracy with calibration and ±3% accuracy across temperature (see “PIOSC Specifications” on page 1375). The PIOSC allows for a reduced system cost in applications that require an accurate clock source. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator, the precision internal oscillator can be trimmed by software based on a reference clock for increased accuracy. Regardless of whether or not the PIOSC is the source for the system clock, the PIOSC can be configured to be the source for the ADC clock as well as the baud clock for the UART and SSI, see “System Control” on page 227. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being June 12, 2014 219 Texas Instruments-Production Data System Control 5.2.5.2 used, the crystal value must be one of the supported frequencies between 5 MHz to 25 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 4 MHz to 25 MHz. The single-ended clock source range is as specified in Table 24-13 on page 1374. The supported crystals are listed in the XTAL bit field in the RCC register (see page 254). Note that the MOSC provides the clock source for the USB PLL and must be connected to a crystal or an oscillator. ■ Low-Frequency Internal Oscillator (LFIOSC). The low-frequency internal oscillator is intended for use during Deep-Sleep power-saving modes. The frequency can have wide variations; refer to “Low-Frequency Internal Oscillator (LFIOSC) Specifications” on page 1375 for more details. This power-savings mode benefits from reduced internal switching and also allows the MOSC to be powered down. In addition, the PIOSC can be powered down while in Deep-Sleep mode. ■ Hibernation Module Clock Source. The Hibernation module is clocked by a 32.768-kHz oscillator connected to the XOSC0 pin. The 32.768-kHz oscillator can be used for the system clock, thus eliminating the need for an additional crystal or oscillator. The Hibernation module clock source is intended to provide the system with a real-time clock source and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%). The frequency of the PLL clock reference must be in the range of 5 MHz to 25 MHz (inclusive). Table 5-3 on page 220 shows how the various clock sources can be used in a system. Table 5-3. Clock Source Options Clock Source Drive PLL? Precision Internal Oscillator Yes BYPASS = 0, OSCSRC = 0x1 Precision Internal Oscillator divide by No - 4 (4 MHz ± 1%) Main Oscillator Yes BYPASS = 0, OSCSRC = 0x0 Low-Frequency Internal Oscillator No - (LFIOSC) Hibernation Module 32.768-kHz No - Oscillator Used as SysClk? Yes BYPASS = 1, OSCSRC = 0x1 Yes BYPASS = 1, OSCSRC = 0x2 Yes BYPASS = 1, OSCSRC = 0x0 Yes BYPASS = 1, OSCSRC = 0x3 Yes BYPASS = 1, OSCSRC2 = 0x7 Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors 220 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller ■ Crystal input selection Important: Write the RCC register prior to writing the RCC2 register. When transitioning the system clock configuration to use the MOSC as the fundamental clock source, the MOSCDIS bit must be set prior to reselecting the MOSC or an undefined system clock configuration can sporadically occur. The configuration of the system clock must not be changed while an EEPROM operation is in process. Software must wait until the WORKING bit in the EEPROM Done Status (EEDONE) register is clear before making any changes to the system clock. Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The ADC clock signal can be selected from the PIOSC, the system clock if the PLL is disabled, or the PLL output divided down to 16 MHz if the PLL is enabled. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC). Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be the clock source, either with or without using the PLL, and the system clock must be at least 20 MHz. June 12, 2014 221 Texas Instruments-Production Data System Control Figure 5-5. Main Clock Tree XTALa USBPWRDNc USB PLL (480 MHz) ÷8 USEPWMDIV a MOSCDIS a Main OSC XTALa PWRDN b PLL (400 MHz) IOSCDISa Precision Internal OSC (16 MHz) Internal OSC (30 kHz) Hibernation OSC (32.768 kHz) ÷4 OSCSRC b,d PWMDW a DIV400 c ÷2 BYPASS b,d USESYSDIV a,d ÷ SYSDIVe BYPASS b,d PWRDN ÷ 25 USB Clock PWM Clock CS f UART Baud Clock System Clock CS f SSI Baud Clock CS f ADC Clock Note: a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set. f. Control provided by UARTCC, SSICC, and ADCCC register field. Communication Clock Sources In addition to the main clock tree described above, the UART, and SSI modules all have a Clock Control register in the peripheral's register map at offset 0xFC8 that can be used to select the clock source for the module's baud clock. Users can choose between the system clock, which is the default source for the baud clock, and the PIOSC. Note that there may be special considerations when using the PIOSC as the baud clock. For more information, see the Clock Control register description in the chapter describing the operation of the module. 222 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Using the SYSDIV and SYSDIV2 Fields In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-4 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-3 on page 220. Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field SYSDIV Divisor Frequency (BYPASS=0) Frequency (BYPASS=1) TivaWare™ Parametera 0x0 /1 reserved Clock source frequency/1 SYSCTL_SYSDIV_1 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-5 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-3 on page 220. Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field SYSDIV2 Divisor Frequency (BYPASS2=0) Frequency (BYPASS2=1) TivaWare Parametera 0x00 /1 reserved Clock source frequency/1 SYSCTL_SYSDIV_1 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 ... ... ... ... ... June 12, 2014 223 Texas Instruments-Production Data System Control 5.2.5.3 Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) SYSDIV2 Divisor Frequency (BYPASS2=0) Frequency (BYPASS2=1) TivaWare Parametera 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 ... ... ... ... ... 0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library. To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus one. Table 5-6 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear, SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table 5-5 on page 223. Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 SYSDIV2 SYSDIV2LSB Divisor Frequency (BYPASS2=0)a TivaWare Parameterb 0x00 reserved /2 reserved - 0 /3 reserved - 0x01 1 /4 reserved - 0 0x02 1 /5 80 MHz /6 66.67 MHz SYSCTL_SYSDIV_2_5 SYSCTL_SYSDIV_3 0 0x03 1 /7 reserved /8 50 MHz SYSCTL_SYSDIV_4 0 0x04 1 /9 44.44 MHz /10 40 MHz SYSCTL_SYSDIV_4_5 SYSCTL_SYSDIV_5 ... ... ... ... ... 0 0x3F 1 /127 3.15 MHz /128 3.125 MHz SYSCTL_SYSDIV_63_5 SYSCTL_SYSDIV_64 a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0. b. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library. Precision Internal Oscillator Operation (PIOSC) The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled as it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting the PIOSCPD bit in the DSLPCLKCFG register. The PIOSC generates a 16-MHz clock with ±1% accuracy with calibration and ±3% accuracy across temperature (see “PIOSC Specifications” on page 1375). At the factory, the PIOSC is set to 16 MHz, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of three ways: ■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator Calibration (PIOSCCAL) register. ■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As the UT value increases, the generated period increases. To commit a new UT value, first set the 224 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.5.4 5.2.5.5 5.2.5.6 5.2.5.7 UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within a few clock periods and is glitch free. ■ Automatic calibration using the Hibernation module with a functioning 32.768-kHz clock source: Set the CAL bit in the PIOSCCAL register; the results of the calibration are shown in the RESULT field in the Precision Internal Oscillator Statistic (PIOSCSTAT) register. After calibration is complete, the PIOSC is trimmed using the trimmed value returned in the CT field. Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals from 4 to 25 MHz. The XTAL bit in the RCC register (see page 254) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor, unless the DIV400 bit in the RCC2 register is set. To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x1. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers (see page 271). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 24-14 on page 1374 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 254) describes the available crystal choices and default programming of the PLLFREQn registers. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. USB PLL Frequency Configuration The USB PLL is disabled by default during power-on reset and is enabled later by software. The USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2 register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices. The main oscillator must be connected to one of the following crystal values in order to correctly generate the USB clock: 5, 6, 8, 10, 12, 16, 18, 20, 24, or 25 MHz. Only these crystals provide the necessary USB PLL VCO frequency to conform with the USB timing specifications. PLL Modes Both PLLs have two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 254 and page 260). June 12, 2014 225 Texas Instruments-Production Data System Control 5.2.5.8 5.2.5.9 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 24-13 on page 1374). During the relock time, the affected PLL is not usable as a clock reference. Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL has locked. Either PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter clocked by the system clock is used to measure the TREADY requirement. The down counter is set to 0x200 if the PLL is powering up. If the M or N values in the PLLFREQn registers are changed, the counter is set to 0xC0. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. The USB PLL is not protected during the lock time (TREADY), and software should ensure that the USB PLL has locked before using the interface. Software can use many methods to ensure the TREADY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the USB PLL Lock interrupt. Main Oscillator Verification Circuit The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register. If this circuit is enabled and detects an error, and if the MOSCIM bit in the MOSCCTL register is clear, then the following sequence is performed by the hardware: 1. The MOSCFAIL bit in the Reset Cause (RESC) register is set. 2. The system clock is switched from the main oscillator to the PIOSC. 3. An internal power-on reset is initiated. 4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence. if the MOSCIM bit in the MOSCCTL register is set, then the following sequence is performed by the hardware: 1. The system clock is switched from the main oscillator to the PIOSC. 226 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.6 2. The MOFRIS bit in the RIS register is set to indicate a MOSC failure. System Control For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for example, RCGCWD) control the clock gating logic for that peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks after a peripheral module clock is enabled in the RCGC register before any module registers are accessed. Important: To support legacy software, the RCGCn, SCGCn, and DCGCn registers are available at offsets 0x100 - 0x128. A write to any of these legacy registers also writes the corresponding bit in the peripheral-specific RCGCx, SCGCx, and DCGCx registers. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. It is recommended that new software use the new registers and not rely on legacy operation. If software uses a peripheral-specific register to write a legacy peripheral (such as TIMER0), the write causes proper operation, but the value of that bit is not reflected in the legacy register. Any bits that are changed by writing to a legacy register can be read back correctly with a read of the legacy register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. There are four levels of operation for the microcontroller defined as: ■ Run mode ■ Sleep mode ■ Deep-Sleep mode ■ Hibernate mode The following sections describe the different modes in detail. Caution – If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their Run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. June 12, 2014 227 Texas Instruments-Production Data System Control 5.2.6.1 5.2.6.2 5.2.6.3 Run Mode In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the peripheral-specific RCGC registers. The system clock can be any of the available clock sources including the PLL. Sleep Mode In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 114 for more details. Peripherals are clocked that are enabled in the peripheral-specific SCGC registers when auto-clock gating is enabled (see the RCC register) or the peripheral-specific RCGC registers when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. Additional sleep modes are available that lower the power consumption of the SRAM and Flash memory. However, the lower power consumption modes have slower sleep and wake-up times, see “Dynamic Power Management” on page 229 for more information. Important: Before executing the WFI instruction, software must confirm that the EEPROM is not busy by checking to see that the WORKING bit in the EEPROM Done Status (EEDONE) register is clear. Deep-Sleep Mode In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Deep-Sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System Control (SYSCTRL) register (see page 166) and then executing a WFI instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 114 for more details. The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode. Peripherals are clocked that are enabled in the peripheral-specific DCGC registers when auto-clock gating is enabled (see the RCC register) or the peripheral-specific RCGC registers when auto-clock gating is disabled. The system clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. USB PLL is not powered down by execution of WFI instruction. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 264. Important: Before executing the WFI instruction, software must confirm that the EEPROM is not busy by checking to see that the WORKING bit in the EEPROM Done Status (EEDONE) register is clear. 228 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the communications modules have a Clock Control register at offset 0xFC8 in the module register space. The CS field in the Clock Control register allows the user to select the PIOSC as the clock source for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSC becomes the source for the module clock as well, which allows the transmit and receive FIFOs to continue operation while the part is in Deep-Sleep. Figure 5-6 on page 229 shows how the clocks are selected. Figure 5-6. Module Clock Selection Clock Control Register PIOSC 1 0 Baud Clock System Clock Deep Sleep 1 0 Module Clock 5.2.6.4 Additional deep-sleep modes are available that lower the power consumption of the SRAM and Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up times, see “Dynamic Power Management” on page 229 for more information. Dynamic Power Management In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there are several additional power mode options that allow the LDO, Flash memory, and SRAM into different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may not be available on all devices; the System Properties (SYSPROP) register provides information on whether a mode is supported on a given MCU. The following registers provides these capabilities: ■ LDO Sleep Power Control (LDOSPCTL): controls the LDO value in Sleep mode ■ LDO Deep-Sleep Power Control (LDODPCTL): controls the LDO value in Deep-Sleep mode ■ LDO Sleep Power Calibration (LDOSPCAL): provides factory recommendations for the LDO value in Sleep mode ■ LDO Deep-Sleep Power Calibration (LDODPCAL): provides factory recommendations for the LDO value in Deep-Sleep mode ■ Sleep Power Configuration (SLPPWRCFG): controls the power saving modes for Flash memory and SRAM in Sleep mode ■ Deep-Sleep Power Configuration (DSLPPWRCFG): controls the power saving modes for Flash memory and SRAM in Deep-Sleep mode June 12, 2014 229 Texas Instruments-Production Data System Control ■ Deep-Sleep Clock Configuration (DSLPCLKCFG): controls the clocking in Deep-Sleep mode ■ Sleep / Deep-Sleep Power Mode Status (SDPMST): provides status information on the various power saving events LDO Sleep/Deep-Sleep Power Control Note: While the device is connected through JTAG, the LDO control settings for Sleep or Deep-Sleep are not available and will not be applied. The user can dynamically request to raise or lower the LDO voltage level to trade-off power/performance using either the LDOSPCTL register (see page 278) or the LDODPCTL register (see page 281). When lowering the LDO level, software must configure the system clock for the lower LDO value in RCC/RCC2 for Sleep mode and in DSLPCLKCFG for Deep-Sleep mode before requesting the LDO to lower. The LDO Power Calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for the LDO in the various modes. If software requests an LDO value that is too low or too high, the value is not accepted and an error is reported in the SDPMST register. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. Operating Voltage (LDO) 1.2 0.9 Maximum System Clock Frequency 80 MHz 20 MHz PIOSC 16 MHz 16 MHz Flash Memory and SRAM Power Control During Sleep or Deep-Sleep mode, Flash memory can be in either the default active mode or the low power mode; SRAM can be in the default active mode, standby mode, or low power mode. The active mode in each case provides the fastest times to sleep and wake up, but consumes more power. Low power mode provides the lowest power consumption, but takes longer to sleep and wake up. The SRAM can be programmed to prohibit any power management by configuring the SRAMSM bit in the System Properties (SYSPROP) register. This configuration operates in the same way that legacy Stellaris® devices operate and provides the fastest sleep and wake-up times, but consumes the most power while in Sleep and Deep-Sleep mode. Other power options are retention mode, and retention mode with lower SRAM voltage. The SRAM retention mode with lower SRAM voltage provides the lowest power consumption, but has the longest sleep and wake-up times. These modes can be independently configured for Flash memory and SRAM using the SLPPWRCFG and DSLPPWRCFG registers. The following power saving options are available in Sleep and Deep-Sleep modes: ■ The clocks can be gated according to the settings in the the peripheral-specific SCGC or DCGC registers. ■ In Deep-Sleep mode, the clock source can be changed and the PIOSC can be powered off (if no active peripheral requires it) using the DSLPCLKCFG register. These options are not available for Sleep mode. ■ The LDO voltage can be changed using the LDOSPCTL or LDODPCTL register. 230 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller 5.2.6.5 5.3 5.4 ■ The Flash memory can be put into low power mode. Refer to Table 24-24 on page 1381 for wake times from Sleep and Deep-Sleep. ■ The SRAM can be put into standby or low power mode. Refer to Table 24-24 on page 1381 for wake times from Sleep and Deep-Sleep. The SDPMST register provides results on the Dynamic Power Management command issued. It also has some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information to help tune software for power management. The status register gets written at the beginning of every Dynamic Power Management event request that provides error checking. There is no mechanism to clear the bits; they are overwritten on the next event. The real time data is real time and there is no event to register that information. Hibernate Mode In this mode, the power supplies are turned off to the main part of the microcontroller and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the microcontroller back to Run mode. The Cortex-M4F processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. Software can determine if the microcontroller has been restarted from Hibernate mode by inspecting the Hibernation module registers. For more information on the operation of Hibernate mode, see “Hibernation Module” on page 493. Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source and allowing for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. Register Map Table 5-7 on page 232 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. June 12, 2014 231 Texas Instruments-Production Data System Control Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 524. Table 5-7. System Control Register Map Offset Name Type Reset Description System Control Registers 0x000 DID0 0x004 DID1 0x030 PBORCTL 0x050 RIS 0x054 IMC 0x058 MISC 0x05C RESC 0x060 RCC 0x06C GPIOHBCTL 0x070 RCC2 0x07C MOSCCTL 0x144 DSLPCLKCFG 0x14C SYSPROP 0x150 PIOSCCAL 0x154 PIOSCSTAT 0x160 PLLFREQ0 0x164 PLLFREQ1 0x168 PLLSTAT 0x188 SLPPWRCFG 0x18C DSLPPWRCFG 0x1B4 LDOSPCTL 0x1B8 LDOSPCAL 0x1BC LDODPCTL 0x1C0 LDODPCAL 0x1CC SDPMST 0x300 PPWD 0x304 PPTIMER 0x308 PPGPIO 0x30C PPDMA RO RO RW RO RW RW1C RW RW RW RW RW RW RO RW RO RO RO RO RW RW RW RO RW RO RO RO RO RO RO 0x10A1.606E 0x0000.7FFF 0x0000.0000 0x0000.0000 0x0000.0000 0x078E.3AD1 0x0000.7E00 0x07C0.6810 0x0000.0000 0x0780.0000 0x0000.1D31 0x0000.0000 0x0000.0040 0x0000.0032 0x0000.0001 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0018 0x0000.1818 0x0000.0012 0x0000.1212 0x0000.0000 0x0000.0003 0x0000.003F 0x0000.003F 0x0000.0001 Device Identification 0 Device Identification 1 Brown-Out Reset Control Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause Run-Mode Clock Configuration GPIO High-Performance Bus Control Run-Mode Clock Configuration 2 Main Oscillator Control Deep Sleep Clock Configuration System Properties Precision Internal Oscillator Calibration Precision Internal Oscillator Statistics PLL Frequency 0 PLL Frequency 1 PLL Status Sleep Power Configuration Deep-Sleep Power Configuration LDO Sleep Power Control LDO Sleep Power Calibration LDO Deep-Sleep Power Control LDO Deep-Sleep Power Calibration Sleep / Deep-Sleep Power Mode Status Watchdog Timer Peripheral Present 16/32-Bit General-Purpose Timer Peripheral Present General-Purpose Input/Output Peripheral Present Micro Direct Memory Access Peripheral Present See page 238 240 243 244 247 249 252 254 258 260 263 264 266 268 270 271 272 273 274 276 278 280 281 283 284 287 288 290 293 232 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 5-7. System Control Register Map (continued) Offset Name Type Reset Description See page 0x314 PPHIB RO 0x0000.0001 Hibernation Peripheral Present 294 0x318 PPUART RO 0x0000.00FF Universal Asynchronous Receiver/Transmitter Peripheral Present 295 0x31C PPSSI RO 0x0000.000F Synchronous Serial Interface Peripheral Present 297 0x320 PPI2C RO 0x0000.000F Inter-Integrated Circuit Peripheral Present 299 0x328 PPUSB RO 0x0000.0001 Universal Serial Bus Peripheral Present 301 0x334 PPCAN RO 0x0000.0003 Controller Area Network Peripheral Present 302 0x338 PPADC RO 0x0000.0003 Analog-to-Digital Converter Peripheral Present 303 0x33C PPACMP RO 0x0000.0001 Analog Comparator Peripheral Present 304 0x340 PPPWM RO 0x0000.0003 Pulse Width Modulator Peripheral Present 305 0x344 PPQEI RO 0x0000.0003 Quadrature Encoder Interface Peripheral Present 306 0x358 PPEEPROM RO 0x0000.0001 EEPROM Peripheral Present 307 0x35C PPWTIMER RO 0x0000.003F 32/64-Bit Wide General-Purpose Timer Peripheral Present 308 0x500 SRWD RW 0x0000.0000 Watchdog Timer Software Reset 310 0x504 SRTIMER RW 0x0000.0000 16/32-Bit General-Purpose Timer Software Reset 312 0x508 SRGPIO RW 0x0000.0000 General-Purpose Input/Output Software Reset 314 0x50C SRDMA RW 0x0000.0000 Micro Direct Memory Access Software Reset 316 0x514 SRHIB RW 0x0000.0000 Hibernation Software Reset 317 0x518 SRUART RW 0x0000.0000 Universal Asynchronous Receiver/Transmitter Software Reset 318 0x51C SRSSI RW 0x0000.0000 Synchronous Serial Interface Software Reset 320 0x520 SRI2C RW 0x0000.0000 Inter-Integrated Circuit Software Reset 322 0x528 SRUSB RW 0x0000.0000 Universal Serial Bus Software Reset 324 0x534 SRCAN RW 0x0000.0000 Controller Area Network Software Reset 325 0x538 SRADC RW 0x0000.0000 Analog-to-Digital Converter Software Reset 327 0x53C SRACMP RW 0x0000.0000 Analog Comparator Software Reset 329 0x540 SRPWM RW 0x0000.0000 Pulse Width Modulator Software Reset 330 0x544 SRQEI RW 0x0000.0000 Quadrature Encoder Interface Software Reset 332 0x558 SREEPROM RW 0x0000.0000 EEPROM Software Reset 334 0x55C SRWTIMER RW 0x0000.0000 32/64-Bit Wide General-Purpose Timer Software Reset 335 0x600 RCGCWD RW 0x0000.0000 Watchdog Timer Run Mode Clock Gating Control 337 0x604 RCGCTIMER RW 0x0000.0000 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control 338 June 12, 2014 233 Texas Instruments-Production Data System Control Table 5-7. System Control Register Map (continued) Offset Name Type Reset Description See page 0x608 RCGCGPIO RW 0x0000.0000 General-Purpose Input/Output Run Mode Clock Gating Control 340 0x60C RCGCDMA RW 0x0000.0000 Micro Direct Memory Access Run Mode Clock Gating Control 342 0x614 RCGCHIB RW 0x0000.0001 Hibernation Run Mode Clock Gating Control 343 0x618 RCGCUART RW 0x0000.0000 Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control 344 0x61C RCGCSSI RW 0x0000.0000 Synchronous Serial Interface Run Mode Clock Gating Control 346 0x620 RCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Run Mode Clock Gating Control 348 0x628 RCGCUSB RW 0x0000.0000 Universal Serial Bus Run Mode Clock Gating Control 350 0x634 RCGCCAN RW 0x0000.0000 Controller Area Network Run Mode Clock Gating Control 351 0x638 RCGCADC RW 0x0000.0000 Analog-to-Digital Converter Run Mode Clock Gating Control 352 0x63C RCGCACMP RW 0x0000.0000 Analog Comparator Run Mode Clock Gating Control 353 0x640 RCGCPWM RW 0x0000.0000 Pulse Width Modulator Run Mode Clock Gating Control 354 0x644 RCGCQEI RW 0x0000.0000 Quadrature Encoder Interface Run Mode Clock Gating Control 355 0x658 RCGCEEPROM RW 0x0000.0000 EEPROM Run Mode Clock Gating Control 356 0x65C RCGCWTIMER RW 0x0000.0000 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control 357 0x700 SCGCWD RW 0x0000.0000 Watchdog Timer Sleep Mode Clock Gating Control 359 0x704 SCGCTIMER RW 0x0000.0000 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control 360 0x708 SCGCGPIO RW 0x0000.0000 General-Purpose Input/Output Sleep Mode Clock Gating Control 362 0x70C SCGCDMA RW 0x0000.0000 Micro Direct Memory Access Sleep Mode Clock Gating Control 364 0x714 SCGCHIB RW 0x0000.0001 Hibernation Sleep Mode Clock Gating Control 365 0x718 SCGCUART RW 0x0000.0000 Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control 366 0x71C SCGCSSI RW 0x0000.0000 Synchronous Serial Interface Sleep Mode Clock Gating Control 368 0x720 SCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Sleep Mode Clock Gating Control 370 0x728 SCGCUSB RW 0x0000.0000 Universal Serial Bus Sleep Mode Clock Gating Control 372 0x734 SCGCCAN RW 0x0000.0000 Controller Area Network Sleep Mode Clock Gating Control 373 234 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 5-7. System Control Register Map (continued) Offset Name Type Reset Description See page 0x738 SCGCADC RW 0x0000.0000 Analog-to-Digital Converter Sleep Mode Clock Gating Control 374 0x73C SCGCACMP RW 0x0000.0000 Analog Comparator Sleep Mode Clock Gating Control 375 0x740 SCGCPWM RW 0x0000.0000 Pulse Width Modulator Sleep Mode Clock Gating Control 376 0x744 SCGCQEI RW 0x0000.0000 Quadrature Encoder Interface Sleep Mode Clock Gating Control 377 0x758 SCGCEEPROM RW 0x0000.0000 EEPROM Sleep Mode Clock Gating Control 378 0x75C SCGCWTIMER RW 0x0000.0000 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control 379 0x800 DCGCWD RW 0x0000.0000 Watchdog Timer Deep-Sleep Mode Clock Gating Control 381 0x804 DCGCTIMER RW 0x0000.0000 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control 382 0x808 DCGCGPIO RW 0x0000.0000 General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control 384 0x80C DCGCDMA RW 0x0000.0000 Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control 386 0x814 DCGCHIB RW 0x0000.0001 Hibernation Deep-Sleep Mode Clock Gating Control 387 0x818 DCGCUART RW 0x0000.0000 Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control 388 0x81C DCGCSSI RW 0x0000.0000 Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control 390 0x820 DCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control 392 0x828 DCGCUSB RW 0x0000.0000 Universal Serial Bus Deep-Sleep Mode Clock Gating Control 394 0x834 DCGCCAN RW 0x0000.0000 Controller Area Network Deep-Sleep Mode Clock Gating Control 395 0x838 DCGCADC RW 0x0000.0000 Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control 396 0x83C DCGCACMP RW 0x0000.0000 Analog Comparator Deep-Sleep Mode Clock Gating Control 397 0x840 DCGCPWM RW 0x0000.0000 Pulse Width Modulator Deep-Sleep Mode Clock Gating Control 398 0x844 DCGCQEI RW 0x0000.0000 Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control 399 0x858 DCGCEEPROM RW 0x0000.0000 EEPROM Deep-Sleep Mode Clock Gating Control 400 0x85C DCGCWTIMER RW 0x0000.0000 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control 401 0xA00 PRWD RO 0x0000.0000 Watchdog Timer Peripheral Ready 403 June 12, 2014 235 Texas Instruments-Production Data System Control Table 5-7. System Control Register Map (continued) Offset Name Type Reset Description See page 0xA04 PRTIMER RO 0x0000.0000 16/32-Bit General-Purpose Timer Peripheral Ready 404 0xA08 PRGPIO RO 0x0000.0000 General-Purpose Input/Output Peripheral Ready 406 0xA0C PRDMA RO 0x0000.0000 Micro Direct Memory Access Peripheral Ready 408 0xA14 PRHIB RO 0x0000.0001 Hibernation Peripheral Ready 409 0xA18 PRUART RO 0x0000.0000 Universal Asynchronous Receiver/Transmitter Peripheral Ready 410 0xA1C PRSSI RO 0x0000.0000 Synchronous Serial Interface Peripheral Ready 412 0xA20 PRI2C RO 0x0000.0000 Inter-Integrated Circuit Peripheral Ready 414 0xA28 PRUSB RO 0x0000.0000 Universal Serial Bus Peripheral Ready 416 0xA34 PRCAN RO 0x0000.0000 Controller Area Network Peripheral Ready 417 0xA38 PRADC RO 0x0000.0000 Analog-to-Digital Converter Peripheral Ready 418 0xA3C PRACMP RO 0x0000.0000 Analog Comparator Peripheral Ready 419 0xA40 PRPWM RO 0x0000.0000 Pulse Width Modulator Peripheral Ready 420 0xA44 PRQEI RO 0x0000.0000 Quadrature Encoder Interface Peripheral Ready 421 0xA58 PREEPROM RO 0x0000.0000 EEPROM Peripheral Ready 422 0xA5C PRWTIMER RO 0x0000.0000 32/64-Bit Wide General-Purpose Timer Peripheral Ready 423 System Control Legacy Registers 0x008 DC0 RO 0x007F.007F Device Capabilities 0 425 0x010 DC1 RO 0x1333.2FFF Device Capabilities 1 427 0x014 DC2 RO 0x030F.F337 Device Capabilities 2 430 0x018 DC3 RO 0xBFFF.8FFF Device Capabilities 3 433 0x01C DC4 RO 0x0004.F03F Device Capabilities 4 437 0x020 DC5 RO 0x0130.00FF Device Capabilities 5 440 0x024 DC6 RO 0x0000.0013 Device Capabilities 6 442 0x028 DC7 RO 0xFFFF.FFFF Device Capabilities 7 443 0x02C DC8 RO 0x0FFF.0FFF Device Capabilities 8 446 0x040 SRCR0 RO 0x0000.0000 Software Reset Control 0 449 0x044 SRCR1 RO 0x0000.0000 Software Reset Control 1 451 0x048 SRCR2 RO 0x0000.0000 Software Reset Control 2 454 0x100 RCGC0 RO 0x0000.0040 Run Mode Clock Gating Control Register 0 456 0x104 RCGC1 RO 0x0000.0000 Run Mode Clock Gating Control Register 1 460 0x108 RCGC2 RO 0x0000.0000 Run Mode Clock Gating Control Register 2 464 236 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Table 5-7. System Control Register Map (continued) Offset Name Type Reset Description 0x110 0x114 0x118 0x120 0x124 0x128 0x190 0x1A0 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 DC9 NVMSTAT RO 0x0000.0040 Sleep Mode Clock Gating Control Register 0 RO 0x0000.0000 Sleep Mode Clock Gating Control Register 1 RO 0x0000.0000 Sleep Mode Clock Gating Control Register 2 RO 0x0000.0040 Deep Sleep Mode Clock Gating Control Register 0 RO 0x0000.0000 Deep-Sleep Mode Clock Gating Control Register 1 RO 0x0000.0000 Deep Sleep Mode Clock Gating Control Register 2 RO 0x00FF.00FF Device Capabilities 9 RO 0x0000.0001 Non-Volatile Memory Information See page 466 469 472 474 477 480 482 484 5.5 System Control Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. Registers provided for legacy software support only are listed in “System Control Legacy Register Descriptions” on page 424. June 12, 2014 237 Texas Instruments-Production Data System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. The MAJOR and MINOR bit fields indicate the die revision number. Combined, the MAJOR and MINOR bit fields indicate the part revision number. MAJOR Bitfield Value 0x0 0x0 0x0 0x0 0x1 0x1 0x1 MINOR Bitfield Value 0x0 0x1 0x2 0x3 0x0 0x1 0x2 Die Revision A0 A1 A2 A3 B0 B1 B2 Part Revision 1 2 3 4 5 6 7 Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved VER reserved CLASS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field 31 30:28 Name reserved VER Type RO RO Reset 0 0x01 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 238 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 23:16 15:8 7:0 Name CLASS MAJOR MINOR Type RO Reset 0x05 Description Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior microcontrollers. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x05 Tiva™ TM4C123x microcontrollers RO - Major Die Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. RO - Minor Die Revision This field specifies the minor revision number of the microcontroller. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. June 12, 2014 239 Texas Instruments-Production Data System Control Register 2: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 0x10A1.606E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER FAM PARTNO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINCOUNT reserved TEMP PKG ROHS QUAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 0 0 0 0 0 0 1 1 0 1 1 1 0 Bit/Field 31:28 Name VER Type RO Reset 0x1 Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x0 Initial DID1 register format definition, indicating a Stellaris LM3Snnn device. 0x1 Second version of the DID1 register format. 27:24 FAM RO 0x0 Family This field provides the family identification of the device within the product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Tiva™ C Series microcontrollers and legacy Stellaris microcontrollers, that is, all devices with external part numbers starting with TM4C, LM4F or LM3S. 23:16 PARTNO RO 0xA1 Part Number This field provides the part number of the device within the family. The reset value shown indicates the TM4C123GH6PM microcontroller. 240 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 15:13 12:8 7:5 4:3 2 Name PINCOUNT reserved TEMP PKG ROHS Type RO RO RO RO RO Reset 0x3 Description Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 reserved 0x1 reserved 0x2 100-pin package 0x3 64-pin package 0x4 144-pin package 0x5 157-pin package 0x6 168-pin package 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Reserved 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) 0x3 Available in both industrial temperature range (-40°C to 85°C) and extended temperature range (-40°C to 105°C) devices. See “Package Information” on page 1402 for specific order numbers. 0x1 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Reserved 0x1 LQFP package 0x2 BGA package 0x1 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. June 12, 2014 241 Texas Instruments-Production Data System Control Bit/Field 1:0 Name QUAL Type RO Reset 0x2 Description Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 242 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Note: The BOR voltage values and center points are based on simulation only. These values are yet to be characterized and are subject to change. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type RW, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BOR0 BOR1 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Bit/Field 31:3 2 Name reserved BOR0 Type RO RW Reset 0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VDD under BOR0 Event Action The VDD BOR0 trip value is 3.02V +/- 90mv. Value Description 0 A BOR0 event causes an interrupt to be generated in the interrupt controller. 1 A BOR0 event causes a reset of the microcontroller. 1 BOR1 RW 1 VDD under BOR1 Event Action The VDD BOR1 trip value is 2.88V +/- 90mv. Value Description 0 A BOR1 event causes an interrupt to be generated to the interrupt controller. 1 A BOR1 event causes a reset of the microcontroller. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 243 Texas Instruments-Production Data System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 reserved Type RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 15 Type RO Reset 0 14 13 reserved RO RO 0 0 12 11 10 9 8 7 6 BOR0RIS VDDARIS reserved MOSCPUPRIS USBPLLLRIS PLLLRIS RO RO RO RO RO RO RO 0 0 0 0 0 0 0 21 20 RO RO 0 0 5 4 reserved RO RO 0 0 19 18 17 16 RO RO RO RO 0 0 0 0 3 2 1 0 MOFRIS reserved BOR1RIS reserved RO RO RO RO 0 0 0 0 Bit/Field 31:12 11 10 9 Name reserved BOR0RIS VDDARIS reserved Type RO RO RO RO Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 VDD under BOR0 Raw Interrupt Status Value Description 0 A VDD BOR0 condition is not currently active. 1 A VDD BOR0 condition is currently active. Note the BOR0 bit in the PBORCTL register must be cleared to cause an interrupt due to a BOR0 Event. This bit is cleared by writing a 1 to the BOR0MIS bit in the MISC register. 0 VDDA Power OK Event Raw Interrupt Status Value Description 0 VDDA power is not at its appropriate functional voltage. 1 VDDA is at an appropriate functional voltage. This bit is cleared by writing a 1 to the VDDAMIS bit in the MISC register. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 244 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 8 7 6 5:4 3 2 Name MOSCPUPRIS USBPLLLRIS PLLLRIS reserved MOFRIS reserved Type RO RO RO RO RO RO Reset 0 0 0 0x0 0 0 Description MOSC Power Up Raw Interrupt Status Value Description 0 Sufficient time has not passed for the MOSC to reach the expected frequency. 1 Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_START. This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC register. USB PLL Lock Raw Interrupt Status Value Description 0 The USB PLL timer has not reached TREADY. 1 The USB PLL timer has reached TREADY indicating that sufficient time has passed for the USB PLL to lock. This bit is cleared by writing a 1 to the USBPLLLMIS bit in the MISC register. PLL Lock Raw Interrupt Status Value Description 0 The PLL timer has not reached TREADY. 1 The PLL timer has reached TREADY indicating that sufficient time has passed for the PLL to lock. This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Main Oscillator Failure Raw Interrupt Status Value Description 0 The main oscillator has not failed. 1 The MOSCIM bit in the MOSCCTL register is set and the main oscillator has failed. This bit is cleared by writing a 1 to the MOFMIS bit in the MISC register. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 245 Texas Instruments-Production Data System Control Bit/Field 1 0 Name BOR1RIS reserved Type RO RO Reset 0 0 Description VDD under BOR1 Raw Interrupt Status Value Description 0 A VDDS BOR1 condition is not currently active. 1 A VDDS BOR1 condition is currently active. Note the BOR1 bit in the PBORCTL register must be cleared to cause an interrupt due to a BOR1 Event. This bit is cleared by writing a 1 to the BOR1MIS bit in the MISC register. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 246 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type RW, reset 0x0000.0000 31 30 29 28 Type RO RO RO RO Reset 0 0 0 0 15 14 13 12 reserved Type RO RO RO RO Reset 0 0 0 0 27 26 25 24 23 22 reserved RO RO RO RO RO RO 0 0 0 0 0 0 11 10 9 8 7 6 BOR0IM VDDAIM reserved MOSCPUPIM USBPLLLIM PLLLIM RW RW RO RW RW RW 0 0 0 0 0 0 21 20 RO RO 0 0 5 4 reserved RO RO 0 0 19 18 17 16 RO RO RO RO 0 0 0 0 3 2 1 0 MOFIM reserved BOR1IM reserved RW RO RW RO 0 0 0 0 Bit/Field 31:12 11 Name reserved BOR0IM Type RO RW Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 VDD under BOR0 Interrupt Mask Value Description 0 The BOR0RIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the BOR0RIS bit in the RIS register is set. 10 VDDAIM RW 0 VDDA Power OK Interrupt Mask Value Description 0 The VDDARIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the VDDARIS bit in the RIS register is set. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MOSCPUPIM RW 0 MOSC Power Up Interrupt Mask Value Description 0 The MOSCPUPRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the MOSCPUPRIS bit in the RIS register is set. June 12, 2014 247 Texas Instruments-Production Data System Control Bit/Field 7 6 5:4 3 2 1 0 Name USBPLLLIM PLLLIM reserved MOFIM reserved BOR1IM reserved Type RW Reset 0 Description USB PLL Lock Interrupt Mask Value Description 0 The USBPLLLRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the USBPLLLRIS bit in the RIS register is set. RW 0 PLL Lock Interrupt Mask Value Description 0 The PLLLRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the PLLLRIS bit in the RIS register is set. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 Main Oscillator Failure Interrupt Mask Value Description 0 The MOFRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the MOFRIS bit in the RIS register is set. RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 VDD under BOR1 Interrupt Mask Value Description 0 The BOR1RIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the BOR1RIS bit in the RIS register is set. RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 248 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see page 244). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type RW1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 reserved Type RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 15 Type RO Reset 0 14 13 reserved RO RO 0 0 12 11 10 9 8 7 6 BOR0MIS VDDAMIS reserved MOSCPUPMIS USBPLLLMIS PLLLMIS RO RW1C RW1C RO RW1C RW1C RW1C 0 0 0 0 0 0 0 21 20 RO RO 0 0 5 4 reserved RO RO 0 0 19 18 17 16 RO RO RO RO 0 0 0 0 3 2 1 0 MOFMIS reserved BOR1MIS reserved RO RO RW1C RO 0 0 0 0 Bit/Field 31:12 11 Name reserved BOR0MIS Type Reset Description RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW1C 0 VDD under BOR0 Masked Interrupt Status Value Description 0 When read, a 0 indicates that a BOR0 condition has not occurred. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because of a BOR0 condition. Writing a 1 to this bit clears it and also the BOR0RIS bit in the RIS register. 10 VDDAMIS RW1C 0 VDDA Power OK Masked Interrupt Status Value Description 0 When read, a 0 indicates that VDDA power is good. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because VDDA was below the proper functioning voltage. Writing a 1 to this bit clears it and also the VDDARIS bit in the RIS register. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 249 Texas Instruments-Production Data System Control Bit/Field 8 7 6 5:4 3 Name MOSCPUPMIS Type RW1C Reset 0 Description MOSC Power Up Masked Interrupt Status Value Description 0 When read, a 0 indicates that sufficient time has not passed for the MOSC PLL to lock. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in the RIS register. USBPLLLMIS RW1C 0 USB PLL Lock Masked Interrupt Status Value Description 0 When read, a 0 indicates that sufficient time has not passed for the USB PLL to lock. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the USB PLL to lock. Writing a 1 to this bit clears it and also the USBPLLLRIS bit in the RIS register. PLLLMIS RW1C 0 PLL Lock Masked Interrupt Status Value Description 0 When read, a 0 indicates that sufficient time has not passed for the PLL to lock. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing a 1 to this bit clears it and also the PLLLRIS bit in the RIS register. reserved MOFMIS RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0 Main Oscillator Failure Masked Interrupt Status Value Description 0 When read, a 0 indicates that the main oscillator has not failed. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because the main oscillator failed. Writing a 1 to this bit clears it and also the MOFRIS bit in the RIS register. 250 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name reserved BOR1MIS reserved Type RO RW1C Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VDD under BOR1 Masked Interrupt Status Value Description 0 When read, a 0 indicates that a BOR1 condition has not occurred. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because of a BOR1 condition. Writing a 1 to this bit clears it and also the BOR1RIS bit in the RIS register. RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 251 Texas Instruments-Production Data System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type RW, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved MOSCFAIL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDT1 SW WDT0 BOR POR EXT Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 - - - - - - Bit/Field 31:17 16 Name reserved MOSCFAIL Type RO RW Reset 0x000 - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Failure Reset Value Description 0 When read, this bit indicates that a MOSC failure has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that the MOSC circuit was enabled for clock validation and failed while the MOSCIM bit in the MOSCCTL register is clear, generating a reset event. 15:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 WDT1 RW - Watchdog Timer 1 Reset Value Description 0 When read, this bit indicates that Watchdog Timer 1 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that Watchdog Timer 1 timed out and generated a reset. 252 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name SW WDT0 BOR POR EXT Type RW RW RW RW RW Reset - Description Software Reset Value Description 0 When read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that a software reset has caused a reset event. - Watchdog Timer 0 Reset Value Description 0 When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. - Brown-Out Reset Value Description 0 When read, this bit indicates that a brown-out (BOR0 or BOR1) reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that a brown-out (BOR0 or BOR1) reset has caused a reset event. - Power-On Reset Value Description 0 When read, this bit indicates that a power-on reset has not generated a reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that a power-on reset has caused a reset event. - External Reset Value Description 0 When read, this bit indicates that an external reset (RST assertion) has not caused a reset event since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that an external reset (RST assertion) has caused a reset event. June 12, 2014 253 Texas Instruments-Production Data System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 The bits in this register configure the system clock and oscillators. Important: Write the RCC register prior to writing the RCC2 register. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type RW, reset 0x078E.3AD1 31 30 29 28 27 26 reserved ACG Type RO RO RO RO RW RW Reset 0 0 0 0 0 1 Type Reset 15 14 reserved RO RO 0 0 13 12 11 10 PWRDN reserved BYPASS RW RO RW RW 1 1 1 0 25 24 SYSDIV RW RW 1 1 9 8 XTAL RW RW 1 0 23 22 21 20 19 18 17 16 USESYSDIV reserved USEPWMDIV PWMDIV reserved RW RW RO RW RW RW RW RO 1 0 0 0 1 1 1 0 7 6 5 4 3 2 1 0 OSCSRC reserved MOSCDIS RW RW RW RW RO RO RO RW 1 1 0 1 0 0 0 1 Bit/Field 31:28 27 26:23 Name reserved ACG SYSDIV Type RO RW RW Reset 0x0 0 0xF Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the microcontroller enters a Sleep or Deep-Sleep mode (respectively). Value Description 0 The Run-Mode Clock Gating Control (RCGCn) registers are used when the microcontroller enters a sleep mode. 1 The SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. The SCGCn and DCGCn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-4 on page 223 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 427), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. 254 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 22 21 20 19:17 16:14 13 Name USESYSDIV reserved USEPWMDIV PWMDIV reserved PWRDN Type RW RO RW RW RO RW Reset 0 Description Enable System Clock Divider Value Description 0 The system clock is used undivided. 1 The system clock divider is the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Enable PWM Clock Divisor Value Description 0 The system clock is the source for the PWM clock. 1 The PWM clock divider is the source for the PWM clock. Note that when the PWM divisor is used, it is applied to the clock for both PWM modules. 0x7 PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. The rising edge of this clock is synchronous with the system clock. Value Divisor 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 PLL Power Down Value Description 0 The PLL is operating normally. 1 The PLL is powered down. Care must be taken to ensure that another clock source is functioning and that the BYPASS bit is set before setting this bit. June 12, 2014 255 Texas Instruments-Production Data System Control Bit/Field 12 11 10:6 Name reserved BYPASS XTAL Type RO RW RW Reset 1 1 0x0B Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Bypass Value Description 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV. 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV. See Table 5-4 on page 223 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Frequencies that may be used with the USB interface are indicated in the table. To function within the clocking requirements of the USB specification, a crystal of 5, 6, 8, 10, 12, or 16 MHz must be used. Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using the PLL Using the PLL 0x00-0x5 reserved 0x06 4 MHz reserved 0x07 4.096 MHz reserved 0x08 4.9152 MHz reserved 0x09 5 MHz (USB) 0x0A 5.12 MHz 0x0B 6 MHz (USB) 0x0C 6.144 MHz 0x0D 7.3728 MHz 0x0E 8 MHz (USB) 0x0F 8.192 MHz 0x10 10.0 MHz (USB) 0x11 12.0 MHz (USB) 0x12 12.288 MHz 0x13 13.56 MHz 0x14 14.31818 MHz 0x15 16.0 MHz (USB) 0x16 16.384 MHz 0x17 18.0 MHz (USB) 0x18 20.0 MHz (USB) 0x19 24.0 MHz (USB) 0x1A 25.0 MHz (USB) 256 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 5:4 3:1 0 Name OSCSRC reserved MOSCDIS Type RW RO RW Reset 0x1 0x0 1 Description Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator (default) 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 LFIOSC Low-frequency internal oscillator For additional oscillator sources, see the RCC2 register. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Main Oscillator Disable Value Description 0 The main oscillator is enabled. 1 The main oscillator is disabled (default). June 12, 2014 257 Texas Instruments-Production Data System Control Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 10-6 on page 660). Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any of these ports is in use, read-modify-write operations should be used to change the value of this register so that these ports remain enabled. GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type RW, reset 0x0000.7E00 31 30 29 28 27 26 25 Type RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 15 14 13 12 11 10 9 reserved Type RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 24 23 reserved RO RO 0 0 8 7 RO RO 0 0 22 21 20 19 18 17 16 RO RO RO RO RO RO RO 0 0 0 0 0 0 0 6 5 4 3 2 1 0 PORTF PORTE PORTD PORTC PORTB PORTA RO RW RW RW RW RW RW 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved PORTF Type RO RW Reset Description 0x0000.0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Port F Advanced High-Performance Bus This bit defines the memory aperture for Port F. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) 4 PORTE RW 0 Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) 258 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name PORTD PORTC PORTB PORTA Type RW RW RW RW Reset 0 Description Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) 0 Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) 0 Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) 0 Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. Value Description 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 1 Advanced High-Performance Bus (AHB) June 12, 2014 259 Texas Instruments-Production Data System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-8. RCC2 Fields that Override RCC Fields RCC2 Field... SYSDIV2, bits[28:23] PWRDN2, bit[13] BYPASS2, bit[11] OSCSRC2, bits[6:4] Overrides RCC Field SYSDIV, bits[26:23] PWRDN, bit[13] BYPASS, bit[11] OSCSRC, bits[5:4] Important: Write the RCC register prior to writing the RCC2 register. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type RW, reset 0x07C0.6810 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USERCC2 DIV400 reserved SYSDIV2 SYSDIV2LSB reserved Type RW RW RO RW RW RW RW RW RW RW RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USBPWRDN PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved Type RO RW RW RO RW RO RO RO RO RW RW RW RO RO RO RO Reset 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 Bit/Field 31 Name USERCC2 Type RW Reset 0 Description Use RCC2 Value Description 0 The RCC register fields are used, and the fields in RCC2 are ignored. 1 The RCC2 register fields override the RCC register fields. 30 DIV400 RW 0 Divide PLL as 400 MHz versus 200 MHz This bit, along with the SYSDIV2LSB bit, allows additional frequency choices. Value Description 0 Use SYSDIV2 as is and apply to 200 MHz predivided PLL output. See Table 5-5 on page 223 for programming guidelines. 1 Append the SYSDIV2LSB bit to the SYSDIV2 field to create a 7 bit divisor using the 400 MHz PLL output, see Table 5-6 on page 224. 260 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 29 28:23 22 21:15 14 13 12 11 10:7 Name reserved SYSDIV2 SYSDIV2LSB reserved USBPWRDN PWRDN2 reserved BYPASS2 reserved Type RO RW RW RO RW RW RO RW RO Reset 0x0 0x0F 1 0x0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor 2 Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-5 on page 223 for programming guidelines. Additional LSB for SYSDIV2 When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400 is clear, this bit is not used. See Table 5-5 on page 223 for programming guidelines. This bit can only be set or cleared when DIV400 is set. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down USB PLL Value Description 0 The USB PLL operates normally. 1 The USB PLL is powered down. 1 Power-Down PLL 2 Value Description 0 The PLL operates normally. 1 The PLL is powered down. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 PLL Bypass 2 Value Description 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV2. 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV2. See Table 5-5 on page 223 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 261 Texas Instruments-Production Data System Control Bit/Field 6:4 3:0 Name OSCSRC2 reserved Type RW RO Reset 0x1 Description Oscillator Source 2 Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 LFIOSC Low-frequency internal oscillator 0x4-0x6 Reserved 0x7 32.768 kHz 32.768-kHz external oscillator 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 262 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NOXTAL MOSCIM CVAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:3 2 Name reserved NOXTAL Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 No Crystal Connected Value Description 0 This bit should be cleared when a crystal or oscillator is connected to the OSC0 and OSC1 inputs, regardless of whether or not the MOSC is used or powered down. 1 This bit should be set when a crystal or external oscillator is not connected to the OSC0 and OSC1 inputs to reduce power consumption. 1 MOSCIM RW 0 MOSC Failure Action Value Description 0 If the MOSC fails, a MOSC failure reset is generated and reboots to the NMI handler. 1 If the MOSC fails, an interrupt is generated as indicated by the MOFRIS bit in the RIS register.. Regardless of the action taken, if the MOSC fails, the oscillator source is switched to the PIOSC automatically. 0 CVAL RW 0 Clock Validation for MOSC Value Description 0 The MOSC monitor circuit is disabled. 1 The MOSC monitor circuit is enabled. June 12, 2014 263 Texas Instruments-Production Data System Control Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type RW, reset 0x0780.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DSDIVORIDE reserved Type RO RO RO RW RW RW RW RW RW RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DSOSCSRC reserved PIOSCPD reserved Type RO RO RO RO RO RO RO RO RO RW RW RW RO RO RW RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:29 28:23 Name reserved DSDIVORIDE Type RO RW Reset 0x0 0x0F Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override If Deep-Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field contains a system divider field that overrides the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2 register during Deep Sleep. This divider is applied to the source selected by the DSOSCSRC field. Value Description 0x0 /1 0x1 /2 0x2 /3 0x3 /4 ... ... 0x3F /64 22:7 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 264 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 6:4 3:2 1 0 Name DSOSCSRC reserved PIOSCPD reserved Type RW RO RW RO Reset 0x0 Description Clock Source Specifies the clock source during Deep-Sleep mode. Value 0x0 Description MOSC Use the main oscillator as the source. To use the MOSC as the Deep-Sleep mode clock source, the MOSC must also be configured as the Run mode clock source in the Run-Mode Clock Configuration (RCC) register. Note: If the PIOSC is being used as the clock reference for the PLL, the PIOSC is the clock source instead of MOSC in Deep-Sleep mode. 0x1 PIOSC Use the precision internal 16-MHz oscillator as the source. 0x2 Reserved 0x3 LFIOSC Use the low-frequency internal oscillator as the source. 0x4-0x6 Reserved 0x7 32.768 kHz Use the Hibernation module 32.768-kHz external oscillator as the source. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 PIOSC Power Down Request Allows software to request the PIOSC to be powered-down in Deep-Sleep mode. If the PIOSC is needed by an enabled peripheral during Deep-Sleep, the PIOSC is powered down, but a warning is generated using the PPDW bit in the SDPMST register. If it is not possible to power down the PIOSC, an error is reported using the PPDERR bit in the SDPMST register. This bit can only be used to power down the PIOSC when the PIOSCPDE bit in the SYSPROP register is set. Value Description 0 No action. 1 Software requests that the PIOSC is powered down during Deep-Sleep mode. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 265 Texas Instruments-Production Data System Control Register 13: System Properties (SYSPROP), offset 0x14C This register provides information on whether certain System Control properties are present on the microcontroller. System Properties (SYSPROP) Base 0x400F.E000 Offset 0x14C Type RO, reset 0x0000.1D31 31 30 29 28 27 26 25 24 23 22 reserved Type RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 reserved PIOSCPDE SRAMSM SRAMLPM reserved FLASHLPM reserved Type RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 1 1 0 1 0 0 21 20 RO RO 0 0 5 4 reserved RO RO 1 1 19 18 17 16 RO RO RO 0 0 0 3 2 1 reserved RO RO RO 0 0 0 RO 0 0 FPU RO 1 Bit/Field 31:13 12 Name reserved PIOSCPDE Type RO RO Reset 0x0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PIOSC Power Down Present This bit determines whether the PIOSCPD bit in the DSLPCLKCFG register can be set to power down the PIOSC in Deep-Sleep mode. Value Description 0 The status of the PIOSCPD bit is ignored. 1 The PIOSCPD bit can be set to power down the PIOSC in Deep-Sleep mode. 11 SRAMSM RO 0x1 SRAM Sleep/Deep-Sleep Standby Mode Present This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode. Value Description 0 A value of 0x1 in the SRAMPM fields is ignored. 1 The SRAMPM fields can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode. 10 SRAMLPM RO 0x1 SRAM Sleep/Deep-Sleep Low Power Mode Present This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into Low Power mode while in Sleep or Deep-Sleep mode. Value Description 0 A value of 0x3 in the SRAMPM fields is ignored. 1 The SRAMPM fields can be configured to put the SRAM into Low Power mode while in Sleep or Deep-Sleep mode. 266 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 9 8 7:6 5:4 3:1 0 Name reserved FLASHLPM reserved reserved reserved FPU Type RO RO RO RO RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Flash Memory Sleep/Deep-Sleep Low Power Mode Present This bit determines whether the FLASHPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the Flash memory into Low Power mode while in Sleep or Deep-Sleep mode. Value Description 0 A value of 0x2 in the FLASHPM fields is ignored. 1 The FLASHPM fields can be configured to put the Flash memory into Low Power mode while in Sleep or Deep-Sleep mode. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x1 FPU Present This bit indicates if the FPU is present in the Cortex-M4 core. Value Description 0 FPU is not present. 1 FPU is present. June 12, 2014 267 Texas Instruments-Production Data System Control Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UTEN reserved Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CAL UPDATE reserved UT Type RO RO RO RO RO RO RW RW RO RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31 Name UTEN Type RW Reset 0 Description Use User Trim Value Value Description 0 The factory calibration value is used for an update trim operation. 1 The trim value in bits[6:0] of this register are used for any update trim operation. 30:10 9 8 7 reserved CAL UPDATE reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RW 0 Start Calibration Value Description 0 No action. 1 Starts a new calibration of the PIOSC. Results are in the PIOSCSTAT register. The resulting trim value from the operation is active in the PIOSC after the calibration completes. The result overrides any previous update trim operation whether the calibration passes or fails. This bit is auto-cleared after it is set. RW 0 Update Trim Value Description 0 No action. 1 Updates the PIOSC trim value with the UT bit or the DT bit in the PIOSCSTAT register. Used with UTEN. This bit is auto-cleared after the update. RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 268 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 6:0 Name UT Type RW Reset 0x0 Description User Trim Value User trim value that can be loaded into the PIOSC. Refer to “Precision Internal Oscillator Operation (PIOSC)” on page 224 for more information on calibrating the PIOSC. June 12, 2014 269 Texas Instruments-Production Data System Control Register 15: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Statistics (PIOSCSTAT) Base 0x400F.E000 Offset 0x154 Type RO, reset 0x0000.0040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RESULT reserved CT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Bit/Field 31:23 22:16 15:10 9:8 Name reserved DT reserved RESULT Type RO RO RO RO Reset 0x00 - 0x0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Default Trim Value This field contains the default trim value. This value is loaded into the PIOSC after every full power-up. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Calibration Result Value Description 0x0 Calibration has not been attempted. 0x1 The last calibration operation completed to meet 1% accuracy. 0x2 The last calibration operation failed to meet 1% accuracy. 0x3 Reserved 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 CT RO 0x40 Calibration Trim Value This field contains the trim value from the last calibration operation. After factory calibration CT and DT are the same. 270 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160 This register always contains the current M value presented to the system PLL. The PLL frequency can be calculated using the following equation: PLL frequency = (XTAL frequency * MDIV) / ((Q + 1) * (N + 1)) where MDIV = MINT + (MFRAC / 1024) The Q and N values are shown in the PLLFREQ1 register. Table 24-14 on page 1374 shows the M, Q, and N values as well as the resulting PLL frequency for the various XTAL configurations. PLL Frequency 0 (PLLFREQ0) Base 0x400F.E000 Offset 0x160 Type RO, reset 0x0000.0032 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved MFRAC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFRAC MINT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:20 19:10 9:0 Name reserved MFRAC MINT Type RO RO RO Reset 0x000 0x32 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL M Fractional Value This field contains the integer value of the PLL M value. PLL M Integer Value This field contains the integer value of the PLL M value. June 12, 2014 271 Texas Instruments-Production Data System Control Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164 This register always contains the current Q and N values presented to the system PLL. The M value is shown in the PLLFREQ0 register. Table 24-14 on page 1374 shows the M, Q, and N values as well as the resulting PLL frequency for the various XTAL configurations. PLL Frequency 1 (PLLFREQ1) Base 0x400F.E000 Offset 0x164 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Q reserved N Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:13 12:8 7:5 4:0 Name reserved Q reserved N Type RO RO RO RO Reset Description 0x0000.0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 PLL Q Value This field contains the PLL Q value. 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x1 PLL N Value This field contains the PLL N value. 272 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 18: PLL Status (PLLSTAT), offset 0x168 This register shows the direct status of the PLL lock. PLL Status (PLLSTAT) Base 0x400F.E000 Offset 0x168 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LOCK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved LOCK Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x0 PLL Lock Value Description 0 The PLL is unpowered or is not yet locked. 1 The PLL is powered and locked. June 12, 2014 273 Texas Instruments-Production Data System Control Register 19: Sleep Power Configuration (SLPPWRCFG), offset 0x188 This register provides configuration information for the power control of the SRAM and Flash memory while in Sleep mode. Sleep Power Configuration (SLPPWRCFG) Base 0x400F.E000 Offset 0x188 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FLASHPM reserved SRAMPM Type RO RO RO RO RO RO RO RO RO RO RW RW RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5:4 Name reserved FLASHPM Type RO RW Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 Flash Power Modes Value Description 0x0 Active Mode Flash memory is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode. 0x1 Reserved 0x2 Low Power Mode Flash memory is placed in low power mode. This mode provides the lowers power consumption but requires more time to come out of Sleep mode. 0x3 Reserved 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 274 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1:0 Name SRAMPM Type RW Reset 0x0 Description SRAM Power Modes This field controls the low power modes of the on-chip SRAM , including the USB SRAM while the microcontroller is in Deep-Sleep mode. Value Description 0x0 Active Mode SRAM is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode. 0x1 Standby Mode SRAM is place in standby mode while in Sleep mode. 0x2 Reserved 0x3 Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Sleep mode. June 12, 2014 275 Texas Instruments-Production Data System Control Register 20: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C This register provides configuration information for the power control of the SRAM and Flash memory while in Deep-Sleep mode. Deep-Sleep Power Configuration (DSLPPWRCFG) Base 0x400F.E000 Offset 0x18C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FLASHPM reserved SRAMPM Type RO RO RO RO RO RO RO RO RO RO RW RW RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5:4 Name reserved FLASHPM Type RO RW Reset Description 0x0000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 Flash Power Modes Value Description 0x0 Active Mode Flash memory is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Deep-Sleep mode. 0x1 Reserved 0x2 Low Power Mode Flash memory is placed in low power mode. This mode provides the lowers power consumption but requires more time to come out of Deep-Sleep mode. 0x3 Reserved 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 276 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1:0 Name SRAMPM Type RW Reset 0x0 Description SRAM Power Modes This field controls the low power modes of the on-chip SRAM , including the USB SRAM while the microcontroller is in Deep-Sleep mode. Value Description 0x0 Active Mode SRAM is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Deep-Sleep mode. 0x1 Standby Mode SRAM is place in standby mode while in Deep-Sleep mode. 0x2 Reserved 0x3 Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Deep-Sleep mode. June 12, 2014 277 Texas Instruments-Production Data System Control Register 21: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 This register specifies the LDO output voltage while in Sleep mode. Writes to the VLDO bit field have no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO output voltage is fixed at the recommended factory reset value. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. Operating Voltage (LDO) 1.2 0.9 Maximum System Clock Frequency 80 MHz 20 MHz PIOSC 16 MHz 16 MHz Note: ■ The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been connected since the last power-on reset. ■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-Sleep mode. LDO Sleep Power Control (LDOSPCTL) Base 0x400F.E000 Offset 0x1B4 Type RW, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VADJEN reserved Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VLDO Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field 31 Name VADJEN Type RW Reset 0 Description Voltage Adjust Enable This bit enables the value of the VLDO field to be used to specify the output voltage of the LDO in Sleep mode. Value Description 0 The LDO output voltage is set to the factory default value in Sleep mode. The value of the VLDO field does not affect the LDO operation. 1 The LDO output value in Sleep mode is configured by the value in the VLDO field. 30:8 reserved RO 0x000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 278 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 7:0 Name VLDO Type RW Reset 0x18 Description LDO Output Voltage This field provides program control of the LDO output voltage in Run mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set. For lowest power in Sleep mode, it is recommended to configure an LDO output voltage that is equal to or lower than the default value of 1.2 V. Value Description 0x12 0.90 V 0x13 0.95 V 0x14 1.00 V 0x15 1.05 V 0x16 1.10 V 0x17 1.15 V 0x18 1.20 V 0x19 - 0xFF reserved June 12, 2014 279 Texas Instruments-Production Data System Control Register 22: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 This register provides factory determined values that are recommended for the VLDO field in the LDOSPCTL register while in Sleep mode. LDO Sleep Power Calibration (LDOSPCAL) Base 0x400F.E000 Offset 0x1B8 Type RO, reset 0x0000.1818 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WITHPLL NOPLL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 Bit/Field 31:16 15:8 7:0 Name reserved WITHPLL NOPLL Type RO RO RO Reset 0x0 0x18 0x18 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sleep with PLL The value in this field is the suggested value for the VLDO field in the LDOSPCTL register when using the PLL. This value provides the lowest recommended LDO output voltage for use with the PLL at the maximum specified value. Sleep without PLL The value in this field is the suggested value for the VLDO field in the LDOSPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use without the PLL. 280 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 23: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC This register specifies the LDO output voltage while in Deep-Sleep mode. This register must be configured in Run mode before entering Deep-Sleep. Writes to the VLDO bit field have no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO output voltage is fixed at the recommended factory reset value. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. Operating Voltage (LDO) 1.2 0.9 Maximum System Clock Frequency 80 MHz 20 MHz PIOSC 16 MHz 16 MHz Note: ■ The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been connected since the last power-on reset. ■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-Sleep mode. LDO Deep-Sleep Power Control (LDODPCTL) Base 0x400F.E000 Offset 0x1BC Type RW, reset 0x0000.0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VADJEN reserved Type RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VLDO Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Bit/Field 31 Name VADJEN Type RW Reset 0 Description Voltage Adjust Enable This bit enables the value of the VLDO field to be used to specify the output voltage of the LDO in Deep-Sleep mode. Value Description 0 The LDO output voltage is set to the factory default value in Deep-Sleep mode. The value of the VLDO field does not affect the LDO operation. 1 The LDO output value in Deep-Sleep mode is configured by the value in the VLDO field. 30:8 reserved RO 0x000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 281 Texas Instruments-Production Data System Control Bit/Field 7:0 Name VLDO Type RW Reset 0x12 Description LDO Output Voltage This field provides program control of the LDO output voltage in Run mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set. For lowest power in Deep-Sleep mode, it is recommended to configure the LDO output voltage to the default value of 0.90 V. Value Description 0x12 0.90 V 0x13 0.95 V 0x14 1.00 V 0x15 1.05 V 0x16 1.10 V 0x17 1.15 V 0x18 1.20 V 0x19 - 0xFF reserved 282 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 24: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 This register provides factory determined values that are recommended for the VLDO field in the LDODPCTL register while in Deep-Sleep mode. LDO Deep-Sleep Power Calibration (LDODPCAL) Base 0x400F.E000 Offset 0x1C0 Type RO, reset 0x0000.1212 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOPLL 30KHZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 Bit/Field 31:16 15:8 7:0 Name reserved NOPLL 30KHZ Type RO RO RO Reset 0x0 0x12 0x12 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Deep-Sleep without PLL The value in this field is the suggested value for the VLDO field in the LDODPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the system clock. Deep-Sleep with IOSC The value in this field is the suggested value for the VLDO field in the LDODPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the low-frequency internal oscillator. June 12, 2014 283 Texas Instruments-Production Data System Control Register 25: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC This register provides status information on the Sleep and Deep-Sleep power modes as well as some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information that can help tune software for power management. The status register gets written at the beginning of every Dynamic Power Management event request with the results of any error checking. There is no mechanism to clear the bits; they are overwritten on the next event. The LDOUA, FLASHLP, LOWPWR, PRACT bits provide real time data and there are no events to register that information. Sleep / Deep-Sleep Power Mode Status (SDPMST) Base 0x400F.E000 Offset 0x1CC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 reserved Type RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 15 14 13 12 11 10 9 reserved Type RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 24 23 22 21 20 19 18 17 16 LDOUA FLASHLP LOWPWR PRACT RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 PPDW LMAXERR reserved LSMINERR LDMINERR PPDERR FPDERR SPDERR RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 Bit/Field 31:20 19 Name reserved LDOUA Type RO RO Reset 0x000 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Update Active Value Description 0 The LDO voltage level is not changing. 1 The LDO voltage level is changing. 18 FLASHLP RO 0 Flash Memory in Low Power State Value Description 0 The Flash memory is currently in the active state. 1 The Flash memory is currently in the low power state as programmed in the SLPPWRCFG or DSLPPWRCFG register. 17 LOWPWR RO 0 Sleep or Deep-Sleep Mode Value Description 0 The microcontroller is currently in Run mode. 1 The microcontroller is currently in Sleep or Deep-Sleep mode and is waiting for an interrupt or is in the process of powering up. The status of this bit is not affected by the power state of the Flash memory or SRAM. 284 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 16 15:8 7 6 5 4 Name PRACT reserved PPDW LMAXERR reserved LSMINERR Type RO RO RO RO RO RO Reset 0 Description Sleep or Deep-Sleep Power Request Active Value Description 0 A power request is not active. 1 The microcontroller is currently in Deep-Sleep mode or is in Sleep mode and a request to put the SRAM and/or Flash memory into a lower power mode is currently active as configured by the SLPPWRCFG register. 0x00 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PIOSC Power Down Request Warning Value Description 0 No error. 1 A warning has occurred because software has requested that the PIOSC be powered down during Deep-Sleep using the PIOSCPD bit in the DSLPCLKCFG register and a peripheral requires that it be active in Deep-Sleep. The PIOSC is powered down regardless of the warning. 0 VLDO Value Above Maximum Error Value Description 0 No error. 1 An error has occurred because software has requested that the LDO voltage be above the maximum value allowed using the VLDO bit in the LDOSPCTL or LDODPCTL register. In this situation, the LDO is set to the factory default value. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 VLDO Value Below Minimum Error in Sleep Mode Value Description 0 No error. 1 An error has occurred because software has requested that the LDO voltage be below the minimum value allowed using the VLDO bit in the LDOSPCTL register. In this situation, the LDO voltage is not changed when entering Sleep mode. June 12, 2014 285 Texas Instruments-Production Data System Control Bit/Field 3 2 1 0 Name LDMINERR PPDERR FPDERR SPDERR Type RO RO RO RO Reset 0 Description VLDO Value Below Minimum Error in Deep-Sleep Mode Value Description 0 No error. 1 An error has occurred because software has requested that the LDO voltage be below the minimum value allowed using the VLDO bit in the LDODPCTL register. In this situation, the LDO voltage is not changed when entering Deep-Sleep mode. 0 PIOSC Power Down Request Error Value Description 0 No error. 1 An error has occurred because software has requested that the PIOSC be powered down during Deep-Sleep and it is not possible to power down the PIOSC. In this situation, the PIOSC is not powered down when entering Deep-Sleep mode. 0 Flash Memory Power Down Request Error Value Description 0 No error. 1 An error has occurred because software has requested a Flash memory power down mode that is not available using the FLASHPM field in the SLPPWRCFG or the DSLPPWRCFG register. 0 SRAM Power Down Request Error Value Description 0 No error. 1 An error has occurred because software has requested an SRAM power down mode that is not available using the SRAMPM field in the SLPPWRCFG or the DSLPPWRCFG register. 286 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 26: Watchdog Timer Peripheral Present (PPWD), offset 0x300 The PPWD register provides software information regarding the watchdog modules. Important: This register should be used to determine which watchdog timers are implemented on this microcontroller. However, to support legacy software, the DC1 register is available. A read of the DC1 register correctly identifies if a legacy module is present. Watchdog Timer Peripheral Present (PPWD) Base 0x400F.E000 Offset 0x300 Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field 31:2 1 Name reserved P1 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Present Value Description 0 Watchdog module 1 is not present. 1 Watchdog module 1 is present. 0 P0 RO 0x1 Watchdog Timer 0 Present Value Description 0 Watchdog module 0 is not present. 1 Watchdog module 0 is present. June 12, 2014 287 Texas Instruments-Production Data System Control Register 27: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 The PPTIMER register provides software information regarding the 16/32-bit general-purpose timer modules. Important: This register should be used to determine which timers are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy module is present. Software must use this register to determine if a module that is not supported by the DC2 register is present. 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER) Base 0x400F.E000 Offset 0x304 Type RO, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P5 P4 P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit/Field 31:6 5 Name reserved P5 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Present Value Description 0 16/32-bit general-purpose timer module 6 is not present. 1 16/32-bit general-purpose timer module 5 is present. 4 P4 RO 0x1 16/32-Bit General-Purpose Timer 4 Present Value Description 0 16/32-bit general-purpose timer module 4 is not present. 1 16/32-bit general-purpose timer module 4 is present. 3 P3 RO 0x1 16/32-Bit General-Purpose Timer 3 Present Value Description 0 16/32-bit general-purpose timer module 3 is not present. 1 16/32-bit general-purpose timer module 3 is present. 288 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name P2 P1 P0 Type RO RO RO Reset 0x1 Description 16/32-Bit General-Purpose Timer 2 Present Value Description 0 16/32-bit general-purpose timer module 2 is not present. 1 16/32-bit general-purpose timer module 2 is present. 0x1 16/32-Bit General-Purpose Timer 1 Present Value Description 0 16/32-bit general-purpose timer module 1 is not present. 1 16/32-bit general-purpose timer module 1 is present. 0x1 16/32-Bit General-Purpose Timer 0 Present Value Description 0 16/32-bit general-purpose timer module 0 is not present. 1 16/32-bit general-purpose timer module 0 is present. June 12, 2014 289 Texas Instruments-Production Data System Control Register 28: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 The PPGPIO register provides software information regarding the general-purpose input/output modules. Important: This register should be used to determine which GPIO ports are implemented on this microcontroller. However, to support legacy software, the DC4 register is available. A read of the DC4 register correctly identifies if a legacy module is present. Software must use this register to determine if a module that is not supported by the DC4 register is present. General-Purpose Input/Output Peripheral Present (PPGPIO) Base 0x400F.E000 Offset 0x308 Type RO, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit/Field 31:15 14 Name reserved P14 Type RO RO Reset 0 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port Q Present Value Description 0 GPIO Port Q is not present. 1 GPIO Port Q is present. 13 P13 RO 0x0 GPIO Port P Present Value Description 0 GPIO Port P is not present. 1 GPIO Port P is present. 12 P12 RO 0x0 GPIO Port N Present Value Description 0 GPIO Port N is not present. 1 GPIO Port N is present. 290 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 11 10 9 8 7 6 5 Name P11 P10 P9 P8 P7 P6 P5 Type RO RO RO RO RO RO RO Reset 0x0 Description GPIO Port M Present Value Description 0 GPIO Port M is not present. 1 GPIO Port M is present. 0x0 GPIO Port L Present Value Description 0 GPIO Port L is not present. 1 GPIO Port L is present. 0x0 GPIO Port K Present Value Description 0 GPIO Port K is not present. 1 GPIO Port K is present. 0x0 GPIO Port J Present Value Description 0 GPIO Port J is not present. 1 GPIO Port J is present. 0x0 GPIO Port H Present Value Description 0 GPIO Port H is not present. 1 GPIO Port H is present. 0x0 GPIO Port G Present Value Description 0 GPIO Port G is not present. 1 GPIO Port G is present. 0x1 GPIO Port F Present Value Description 0 GPIO Port F is not present. 1 GPIO Port F is present. June 12, 2014 291 Texas Instruments-Production Data System Control Bit/Field 4 3 2 1 0 Name P4 P3 P2 P1 P0 Type RO RO RO RO RO Reset 0x1 Description GPIO Port E Present Value Description 0 GPIO Port E is not present. 1 GPIO Port E is present. 0x1 GPIO Port D Present Value Description 0 GPIO Port D is not present. 1 GPIO Port D is present. 0x1 GPIO Port C Present Value Description 0 GPIO Port C is not present. 1 GPIO Port C is present. 0x1 GPIO Port B Present Value Description 0 GPIO Port B is not present. 1 GPIO Port B is present. 0x1 GPIO Port A Present Value Description 0 GPIO Port A is not present. 1 GPIO Port A is present. 292 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 29: Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C The PPDMA register provides software information regarding the μDMA module. Important: This register should be used to determine if the μDMA module is implemented on this microcontroller. However, to support legacy software, the DC7 register is available. A read of the DC7 register correctly identifies if the μDMA module is present. Micro Direct Memory Access Peripheral Present (PPDMA) Base 0x400F.E000 Offset 0x30C Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved P0 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Present Value Description 0 μDMA module is not present. 1 μDMA module is present. June 12, 2014 293 Texas Instruments-Production Data System Control Register 30: Hibernation Peripheral Present (PPHIB), offset 0x314 The PPHIB register provides software information regarding the Hibernation module. Important: This register should be used to determine if the Hibernation module is implemented on this microcontroller. However, to support legacy software, the DC1 register is available. A read of the DC1 register correctly identifies if the Hibernation module is present. Hibernation Peripheral Present (PPHIB) Base 0x400F.E000 Offset 0x314 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved P0 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Present Value Description 0 Hibernation module is not present. 1 Hibernation module is present. 294 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 31: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset 0x318 The PPUART register provides software information regarding the UART modules. Important: This register should be used to determine which UART modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy UART module is present. Software must use this register to determine if a module that is not supported by the DC2 register is present. Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART) Base 0x400F.E000 Offset 0x318 Type RO, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P7 P6 P5 P4 P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field 31:8 7 Name reserved P7 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Present Value Description 0 UART module 7 is not present. 1 UART module 7 is present. 6 P6 RO 0x1 UART Module 6 Present Value Description 0 UART module 6 is not present. 1 UART module 6 is present. 5 P5 RO 0x1 UART Module 5 Present Value Description 0 UART module 5 is not present. 1 UART module 5 is present. June 12, 2014 295 Texas Instruments-Production Data System Control Bit/Field 4 3 2 1 0 Name P4 P3 P2 P1 P0 Type RO RO RO RO RO Reset 0x1 Description UART Module 4 Present Value Description 0 UART module 4 is not present. 1 UART module 4 is present. 0x1 UART Module 3 Present Value Description 0 UART module 3 is not present. 1 UART module 3 is present. 0x1 UART Module 2 Present Value Description 0 UART module 2 is not present. 1 UART module 2 is present. 0x1 UART Module 1 Present Value Description 0 UART module 1 is not present. 1 UART module 1 is present. 0x1 UART Module 0 Present Value Description 0 UART module 0 is not present. 1 UART module 0 is present. 296 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 32: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C The PPSSI register provides software information regarding the SSI modules. Important: This register should be used to determine which SSI modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy SSI module is present. Software must use this register to determine if a module that is not supported by the DC2 register is present. Synchronous Serial Interface Peripheral Present (PPSSI) Base 0x400F.E000 Offset 0x31C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit/Field 31:4 3 Name reserved P3 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Present Value Description 0 SSI module 3 is not present. 1 SSI module 3 is present. 2 P2 RO 0x1 SSI Module 2 Present Value Description 0 SSI module 2 is not present. 1 SSI module 2 is present. 1 P1 RO 0x1 SSI Module 1 Present Value Description 0 SSI module 1 is not present. 1 SSI module 1 is present. June 12, 2014 297 Texas Instruments-Production Data System Control Bit/Field 0 Name P0 Type RO Reset 0x1 Description SSI Module 0 Present Value Description 0 SSI module 0 is not present. 1 SSI module 0 is present. 298 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 33: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 The PPI2C register provides software information regarding the I2C modules. Important: This register should be used to determine which I2C modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy I2C module is present. Software must use this register to determine if a module that is not supported by the DC2 register is present. Inter-Integrated Circuit Peripheral Present (PPI2C) Base 0x400F.E000 Offset 0x320 Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P5 P4 P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit/Field 31:6 5 Name reserved P5 Type RO RO Reset 0 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 5 Present Value Description 0 I2C module 5 is not present. 1 I2C module 5 is present. 4 P4 RO 0x0 I2C Module 4 Present Value Description 0 I2C module 4 is not present. 1 I2C module 4 is present. 3 P3 RO 0x1 I2C Module 3 Present Value Description 0 I2C module 3 is not present. 1 I2C module 3 is present. June 12, 2014 299 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name P2 P1 P0 Type RO RO RO Reset 0x1 Description I2C Module 2 Present Value Description 0 I2C module 2 is not present. 1 I2C module 2 is present. 0x1 I2C Module 1 Present Value Description 0 I2C module 1 is not present. 1 I2C module 1 is present. 0x1 I2C Module 0 Present Value Description 0 I2C module 0 is not present. 1 I2C module 0 is present. 300 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 34: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 The PPUSB register provides software information regarding the USB module. Important: This register should be used to determine if the USB module is implemented on this microcontroller. However, to support legacy software, the DC6 register is available. A read of the DC6 register correctly identifies if the USB module is present. Universal Serial Bus Peripheral Present (PPUSB) Base 0x400F.E000 Offset 0x328 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved P0 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Present Value Description 0 USB module is not present. 1 USB module is present. June 12, 2014 301 Texas Instruments-Production Data System Control Register 35: Controller Area Network Peripheral Present (PPCAN), offset 0x334 The PPCAN register provides software information regarding the CAN modules. Important: This register should be used to determine which CAN modules are implemented on this microcontroller. However, to support legacy software, the DC1 register is available. A read of the DC1 register correctly identifies if a legacy CAN module is present. Controller Area Network Peripheral Present (PPCAN) Base 0x400F.E000 Offset 0x334 Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field 31:2 1 Name reserved P1 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Present Value Description 0 CAN module 1 is not present. 1 CAN module 1 is present. 0 P0 RO 0x1 CAN Module 0 Present Value Description 0 CAN module 0 is not present. 1 CAN module 0 is present. 302 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 36: Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 The PPADC register provides software information regarding the ADC modules. Important: This register should be used to determine which ADC modules are implemented on this microcontroller. However, to support legacy software, the DC1 register is available. A read of the DC1 register correctly identifies if a legacy ADC module is present. Analog-to-Digital Converter Peripheral Present (PPADC) Base 0x400F.E000 Offset 0x338 Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field 31:2 1 Name reserved P1 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Present Value Description 0 ADC module 1 is not present. 1 ADC module 1 is present. 0 P0 RO 0x1 ADC Module 0 Present Value Description 0 ADC module 0 is not present. 1 ADC module 0 is present. June 12, 2014 303 Texas Instruments-Production Data System Control Register 37: Analog Comparator Peripheral Present (PPACMP), offset 0x33C The PPACMP register provides software information regarding the analog comparator module. Important: This register should be used to determine if the analog comparator module is implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if the analog comparator module is present. Note that the Analog Comparator Peripheral Properties (ACMPPP) register indicates how many analog comparator blocks are included in the module. Analog Comparator Peripheral Present (PPACMP) Base 0x400F.E000 Offset 0x33C Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved P0 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module Present Value Description 0 Analog comparator module is not present. 1 Analog comparator module is present. 304 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 38: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 The PPPWM register provides software information regarding the PWM modules. Important: This register should be used to determine which PWM modules are implemented on this microcontroller. However, to support legacy software, the DC1 register is available. A read of the DC1 register correctly identifies if the legacy PWM module is present. Software must use this register to determine if a module that is not supported by the DC1 register is present. Pulse Width Modulator Peripheral Present (PPPWM) Base 0x400F.E000 Offset 0x340 Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field 31:2 1 Name reserved P1 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Present Value Description 0 PWM module 1 is not present. 1 PWM module 1 is present. 0 P0 RO 0x1 PWM Module 0 Present Value Description 0 PWM module 0 is not present. 1 PWM module 0 is present. June 12, 2014 305 Texas Instruments-Production Data System Control Register 39: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 The PPQEI register provides software information regarding the QEI modules. Important: This register should be used to determine which QEI modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy QEI module is present. Quadrature Encoder Interface Peripheral Present (PPQEI) Base 0x400F.E000 Offset 0x344 Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field 31:2 1 Name reserved P1 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Present Value Description 0 QEI module 1 is not present. 1 QEI module 1 is present. 0 P0 RO 0x1 QEI Module 0 Present Value Description 0 QEI module 0 is not present. 1 QEI module 0 is present. 306 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 40: EEPROM Peripheral Present (PPEEPROM), offset 0x358 The PPEEPROM register provides software information regarding the EEPROM module. EEPROM Peripheral Present (PPEEPROM) Base 0x400F.E000 Offset 0x358 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved P0 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Present Value Description 0 EEPROM module is not present. 1 EEPROM module is present. June 12, 2014 307 Texas Instruments-Production Data System Control Register 41: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C The PPWTIMER register provides software information regarding the 32/64-bit wide general-purpose timer modules. 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER) Base 0x400F.E000 Offset 0x35C Type RO, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved P5 P4 P3 P2 P1 P0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit/Field 31:6 5 Name reserved P5 Type RO RO Reset 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Present Value Description 0 32/64-bit wide general-purpose timer module 5 is not present. 1 32/64-bit wide general-purpose timer module 5 is present. 4 P4 RO 0x1 32/64-Bit Wide General-Purpose Timer 4 Present Value Description 0 32/64-bit wide general-purpose timer module 4 is not present. 1 32/64-bit wide general-purpose timer module 4 is present. 3 P3 RO 0x1 32/64-Bit Wide General-Purpose Timer 3 Present Value Description 0 32/64-bit wide general-purpose timer module 3 is not present. 1 32/64-bit wide general-purpose timer module 3 is present. 2 P2 RO 0x1 32/64-Bit Wide General-Purpose Timer 2 Present Value Description 0 32/64-bit wide general-purpose timer module 2 is not present. 1 32/64-bit wide general-purpose timer module 2 is present. 308 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name P1 P0 Type RO RO Reset 0x1 Description 32/64-Bit Wide General-Purpose Timer 1 Present Value Description 0 32/64-bit wide general-purpose timer module 1 is not present. 1 32/64-bit wide general-purpose timer module 1 is present. 0x1 32/64-Bit Wide General-Purpose Timer 0 Present Value Description 0 32/64-bit wide general-purpose timer module 0 is not present. 1 32/64-bit wide general-purpose timer module 0 is present. June 12, 2014 309 Texas Instruments-Production Data System Control Register 42: Watchdog Timer Software Reset (SRWD), offset 0x500 The SRWD register provides software the capability to reset the available watchdog modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRWD bit. There may be latency from the clearing of the SRWD bit to when the peripheral is ready for use. Software can check the corresponding PRWD bit to be sure. Important: This register should be used to reset the watchdog modules. To support legacy software, the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the corresponding module. Any bits that are changed by writing to the SRCR0 register can be read back correctly when reading the SRCR0 register. If software uses this register to reset a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Software Reset (SRWD) Base 0x400F.E000 Offset 0x500 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Software Reset Value Description 0 Watchdog module 1 is not reset. 1 Watchdog module 1 is reset. 310 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name R0 Type RW Reset 0 Description Watchdog Timer 0 Software Reset Value Description 0 Watchdog module 0 is not reset. 1 Watchdog module 0 is reset. June 12, 2014 311 Texas Instruments-Production Data System Control Register 43: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 The SRTIMER register provides software the capability to reset the available 16/32-bit timer modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the timer modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRTIMER bit. There may be latency from the clearing of the SRTIMER bit to when the peripheral is ready for use. Software can check the corresponding PRTIMER bit to be sure. Important: This register should be used to reset the timer modules. To support legacy software, the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the corresponding module. Any bits that are changed by writing to the SRCR1 register can be read back correctly when reading the SRCR1 register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as Timer 1), the write causes proper operation, but the value of that bit is not reflected in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Software Reset (SRTIMER) Base 0x400F.E000 Offset 0x504 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Software Reset Value Description 0 16/32-bit general-purpose timer module 5 is not reset. 1 16/32-bit general-purpose timer module 5 is reset. 312 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name R4 R3 R2 R1 R0 Type RW RW RW RW RW Reset 0 Description 16/32-Bit General-Purpose Timer 4 Software Reset Value Description 0 16/32-bit general-purpose timer module 4 is not reset. 1 16/32-bit general-purpose timer module 4 is reset. 0 16/32-Bit General-Purpose Timer 3 Software Reset Value Description 0 16/32-bit general-purpose timer module 3 is not reset. 1 16/32-bit general-purpose timer module 3 is reset. 0 16/32-Bit General-Purpose Timer 2 Software Reset Value Description 0 16/32-bit general-purpose timer module 2 is not reset. 1 16/32-bit general-purpose timer module 2 is reset. 0 16/32-Bit General-Purpose Timer 1 Software Reset Value Description 0 16/32-bit general-purpose timer module 1 is not reset. 1 16/32-bit general-purpose timer module 1 is reset. 0 16/32-Bit General-Purpose Timer 0 Software Reset Value Description 0 16/32-bit general-purpose timer module 0 is not reset. 1 16/32-bit general-purpose timer module 0 is reset. June 12, 2014 313 Texas Instruments-Production Data System Control Register 44: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 The SRGPIO register provides software the capability to reset the available GPIO modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the GPIO modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRGPIO bit. There may be latency from the clearing of the SRGPIO bit to when the peripheral is ready for use. Software can check the corresponding PRGPIO bit to be sure. Important: This register should be used to reset the GPIO modules. To support legacy software, the SRCR2 register is available. Setting a bit in the SRCR2 register also resets the corresponding module. Any bits that are changed by writing to the SRCR2 register can be read back correctly when reading the SRCR2 register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in the SRCR2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Software Reset (SRGPIO) Base 0x400F.E000 Offset 0x508 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port F Software Reset Value Description 0 GPIO Port F is not reset. 1 GPIO Port F is reset. 314 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name R4 R3 R2 R1 R0 Type RW RW RW RW RW Reset 0 Description GPIO Port E Software Reset Value Description 0 GPIO Port E is not reset. 1 GPIO Port E is reset. 0 GPIO Port D Software Reset Value Description 0 GPIO Port D is not reset. 1 GPIO Port D is reset. 0 GPIO Port C Software Reset Value Description 0 GPIO Port C is not reset. 1 GPIO Port C is reset. 0 GPIO Port B Software Reset Value Description 0 GPIO Port B is not reset. 1 GPIO Port B is reset. 0 GPIO Port A Software Reset Value Description 0 GPIO Port A is not reset. 1 GPIO Port A is reset. June 12, 2014 315 Texas Instruments-Production Data System Control Register 45: Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C The SRDMA register provides software the capability to reset the available μDMA module. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the μDMA module and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRDMA register. While the SRDMA bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRDMA bit. There may be latency from the clearing of the SRDMA bit to when the peripheral is ready for use. Software can check the corresponding PRDMA bit to be sure. Important: This register should be used to reset the μDMA module. To support legacy software, the SRCR2 register is available. Setting the UDMA bit in the SRCR2 register also resets the μDMA module. If the UDMA bit is set by writing to the SRCR2 register, it can be read back correctly when reading the SRCR2 register. If software uses this register to reset the μDMA module, the write causes proper operation, but the value of the UDMA bit is not reflected in the SRCR2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Software Reset (SRDMA) Base 0x400F.E000 Offset 0x50C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Software Reset Value Description 0 μDMA module is not reset. 1 μDMA module is reset. 316 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 46: Hibernation Software Reset (SRHIB), offset 0x514 The SRHIB register provides software the capability to reset the available Hibernation module. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the Hibernation module and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRHIB register. While the SRHIB bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRHIB bit. There may be latency from the clearing of the SRHIB bit to when the peripheral is ready for use. Software can check the corresponding PRHIB bit to be sure. Important: This register should be used to reset the Hibernation module. To support legacy software, the SRCR0 register is available. Setting the HIB bit in the SRCR0 register also resets the Hibernation module. If the HIB bit is set by writing to the SRCR0 register, it can be read back correctly when reading the SRCR0 register. If software uses this register to reset the Hibernation module, the write causes proper operation, but the value of the HIB bit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Software Reset (SRHIB) Base 0x400F.E000 Offset 0x514 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Software Reset Value Description 0 Hibernation module is not reset. 1 Hibernation module is reset. June 12, 2014 317 Texas Instruments-Production Data System Control Register 47: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 The SRUART register provides software the capability to reset the available UART modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the UART modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRUART bit. There may be latency from the clearing of the SRUART bit to when the peripheral is ready for use. Software can check the corresponding PRUART bit to be sure. Important: This register should be used to reset the UART modules. To support legacy software, the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the corresponding module. Any bits that are changed by writing to the SRCR1 register can be read back correctly when reading the SRCR1 register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Software Reset (SRUART) Base 0x400F.E000 Offset 0x518 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R7 R6 R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7 Name reserved R7 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Software Reset Value Description 0 UART module 7 is not reset. 1 UART module 7 is reset. 318 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 6 5 4 3 2 1 0 Name R6 R5 R4 R3 R2 R1 R0 Type RW RW RW RW RW RW RW Reset 0 Description UART Module 6 Software Reset Value Description 0 UART module 6 is not reset. 1 UART module 6 is reset. 0 UART Module 5 Software Reset Value Description 0 UART module 5 is not reset. 1 UART module 5 is reset. 0 UART Module 4 Software Reset Value Description 0 UART module 4 is not reset. 1 UART module 4 is reset. 0 UART Module 3 Software Reset Value Description 0 UART module 3 is not reset. 1 UART module 3 is reset. 0 UART Module 2 Software Reset Value Description 0 UART module 2 is not reset. 1 UART module 2 is reset. 0 UART Module 1 Software Reset Value Description 0 UART module 1 is not reset. 1 UART module 1 is reset. 0 UART Module 0 Software Reset Value Description 0 UART module 0 is not reset. 1 UART module 0 is reset. June 12, 2014 319 Texas Instruments-Production Data System Control Register 48: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C The SRSSI register provides software the capability to reset the available SSI modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the SSI modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRSSI bit. There may be latency from the clearing of the SRSSI bit to when the peripheral is ready for use. Software can check the corresponding PRSSI bit to be sure. Important: This register should be used to reset the SSI modules. To support legacy software, the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the corresponding module. Any bits that are changed by writing to the SRCR1 register can be read back correctly when reading the SRCR1 register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Software Reset (SRSSI) Base 0x400F.E000 Offset 0x51C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Software Reset Value Description 0 SSI module 3 is not reset. 1 SSI module 3 is reset. 320 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name R2 R1 R0 Type RW RW RW Reset 0 Description SSI Module 2 Software Reset Value Description 0 SSI module 2 is not reset. 1 SSI module 2 is reset. 0 SSI Module 1 Software Reset Value Description 0 SSI module 1 is not reset. 1 SSI module 1 is reset. 0 SSI Module 0 Software Reset Value Description 0 SSI module 0 is not reset. 1 SSI module 0 is reset. June 12, 2014 321 Texas Instruments-Production Data System Control Register 49: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 The SRI2C register provides software the capability to reset the available I2C modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the I2C modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRI2C bit. There may be latency from the clearing of the SRI2C bit to when the peripheral is ready for use. Software can check the corresponding PRI2C bit to be sure. Important: This register should be used to reset the I2C modules. To support legacy software, the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the corresponding module. Any bits that are changed by writing to the SRCR1 register can be read back correctly when reading the SRCR1 register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Software Reset (SRI2C) Base 0x400F.E000 Offset 0x520 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 3 Software Reset Value Description 0 I2C module 3 is not reset. 1 I2C module 3 is reset. 322 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name R2 R1 R0 Type RW RW RW Reset 0 Description I2C Module 2 Software Reset Value Description 0 I2C module 2 is not reset. 1 I2C module 2 is reset. 0 I2C Module 1 Software Reset Value Description 0 I2C module 1 is not reset. 1 I2C module 1 is reset. 0 I2C Module 0 Software Reset Value Description 0 I2C module 0 is not reset. 1 I2C module 0 is reset. June 12, 2014 323 Texas Instruments-Production Data System Control Register 50: Universal Serial Bus Software Reset (SRUSB), offset 0x528 The SRUSB register provides software the capability to reset the available USB module. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the USB module and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUSB register. While the SRUSB bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRUSB bit. There may be latency from the clearing of the SRUSB bit to when the peripheral is ready for use. Software can check the corresponding PRUSB bit to be sure. Important: This register should be used to reset the USB module. To support legacy software, the SRCR2 register is available. Setting the USB0 bit in the SRCR2 register also resets the USB module. If the USB0 bit is set by writing to the SRCR2 register, it can be read back correctly when reading the SRCR2 register. If software uses this register to reset the USB module, the write causes proper operation, but the value of the USB0 bit is not reflected in the SRCR2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Software Reset (SRUSB) Base 0x400F.E000 Offset 0x528 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Software Reset Value Description 0 USB module is not reset. 1 USB module is reset. 324 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 51: Controller Area Network Software Reset (SRCAN), offset 0x534 The SRCAN register provides software the capability to reset the available CAN modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the CAN modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRCAN bit. There may be latency from the clearing of the SRCAN bit to when the peripheral is ready for use. Software can check the corresponding PRCAN bit to be sure. Important: This register should be used to reset the CAN modules. To support legacy software, the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the corresponding module. Any bits that are changed by writing to the SRCR0 register can be read back correctly when reading the SRCR0 register. If software uses this register to reset a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Software Reset (SRCAN) Base 0x400F.E000 Offset 0x534 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Software Reset Value Description 0 CAN module 1 is not reset. 1 CAN module 1 is reset. June 12, 2014 325 Texas Instruments-Production Data System Control Bit/Field 0 Name R0 Type RW Reset 0 Description CAN Module 0 Software Reset Value Description 0 CAN module 0 is not reset. 1 CAN module 0 is reset. 326 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 52: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 The SRADC register provides software the capability to reset the available ADC modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the ADC modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRADC bit. There may be latency from the clearing of the SRADC bit to when the peripheral is ready for use. Software can check the corresponding PRADC bit to be sure. Important: This register should be used to reset the ADC modules. To support legacy software, the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the corresponding module. Any bits that are changed by writing to the SRCR0 register can be read back correctly when reading the SRCR0 register. If software uses this register to reset a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Software Reset (SRADC) Base 0x400F.E000 Offset 0x538 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Software Reset Value Description 0 ADC module 1 is not reset. 1 ADC module 1 is reset. June 12, 2014 327 Texas Instruments-Production Data System Control Bit/Field 0 Name R0 Type RW Reset 0 Description ADC Module 0 Software Reset Value Description 0 ADC module 0 is not reset. 1 ADC module 0 is reset. 328 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 53: Analog Comparator Software Reset (SRACMP), offset 0x53C The SRACMP register provides software the capability to reset the available analog comparator module. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the analog comparator module and has the same bit polarity as the corresponding SRCRn bits. A block is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module is held in reset. 2. Software completes the reset process by clearing the SRACMP bit. There may be latency from the clearing of the SRACMP bit to when the module is ready for use. Software can check the corresponding PRACMP bit to be sure. Important: This register should be used to reset the analog comparator module. To support legacy software, the SRCR1 register is available. Setting any of the COMPn bits in the SRCR0 register also resets the analog comparator module. If any of the COMPn bits are set by writing to the SRCR1 register, it can be read back correctly when reading the SRCR0 register. If software uses this register to reset the analog comparator module, the write causes proper operation, but the value of R0 is not reflected by the COMPn bits in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Software Reset (SRACMP) Base 0x400F.E000 Offset 0x53C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module 0 Software Reset Value Description 0 Analog comparator module is not reset. 1 Analog comparator module is reset. June 12, 2014 329 Texas Instruments-Production Data System Control Register 54: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 The SRPWM register provides software the capability to reset the available PWM modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the PWM modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRPWM register. While the SRPWM bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRPWM bit. There may be latency from the clearing of the SRPWM bit to when the peripheral is ready for use. Software can check the corresponding PRPWM bit to be sure. Important: This register should be used to reset the PWM modules. To support legacy software, the SRCR0 register is available. Setting the PWM bit in the SRCR0 register also resets the PWM0 module. If the PWM bit is changed by writing to the SRCR0 register, it can be read back correctly when reading the SRCR0 register. Software must use this register to reset PWM1, which is not present in the legacy registers. If software uses this register to reset PWM0, the write causes proper operation, but the value of that bit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Pulse Width Modulator Software Reset (SRPWM) Base 0x400F.E000 Offset 0x540 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Software Reset Value Description 0 PWM module 1 is not reset. 1 PWM module 1 is reset. 330 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name R0 Type RW Reset 0 Description PWM Module 0 Software Reset Value Description 0 PWM module 0 is not reset. 1 PWM module 0 is reset. June 12, 2014 331 Texas Instruments-Production Data System Control Register 55: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 The SRQEI register provides software the capability to reset the available QEI modules. This register provides the same capability as the legacy Software Reset Control n SRCRn registers specifically for the QEI modules and has the same bit polarity as the corresponding SRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRQEI register. While the SRQEI bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRQEI bit. There may be latency from the clearing of the SRQEI bit to when the peripheral is ready for use. Software can check the corresponding PRQEI bit to be sure. Important: This register should be used to reset the QEI modules. To support legacy software, the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the corresponding module. Any bits that are changed by writing to the SRCR1 register can be read back correctly when reading the SRCR1 register. If software uses this register to reset a legacy peripheral (such as QEI0), the write causes proper operation, but the value of that bit is not reflected in the SRCR1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Quadrature Encoder Interface Software Reset (SRQEI) Base 0x400F.E000 Offset 0x544 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Software Reset Value Description 0 QEI module 1 is not reset. 1 QEI module 1 is reset. 332 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name R0 Type RW Reset 0 Description QEI Module 0 Software Reset Value Description 0 QEI module 0 is not reset. 1 QEI module 0 is reset. June 12, 2014 333 Texas Instruments-Production Data System Control Register 56: EEPROM Software Reset (SREEPROM), offset 0x558 The SREEPROM register provides software the capability to reset the available EEPROM module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREEPROM register. While the SREEPROM bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SREEPROM bit. There may be latency from the clearing of the SREEPROM bit to when the peripheral is ready for use. Software can check the corresponding PREEPROM bit to be sure. EEPROM Software Reset (SREEPROM) Base 0x400F.E000 Offset 0x558 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Software Reset Value Description 0 EEPROM module is not reset. 1 EEPROM module is reset. 334 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 57: 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C The SRWTIMER register provides software the capability to reset the available 32/64-bit wide timer modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRWTIMER register. While the SRWTIMER bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRWTIMER bit. There may be latency from the clearing of the SRWTIMER bit to when the peripheral is ready for use. Software can check the corresponding PRWTIMER bit to be sure. 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER) Base 0x400F.E000 Offset 0x55C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 5 is not reset. 1 32/64-bit wide general-purpose timer module 5 is reset. 4 R4 RW 0 32/64-Bit Wide General-Purpose Timer 4 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 4 is not reset. 1 32/64-bit wide general-purpose timer module 4 is reset. 3 R3 RW 0 32/64-Bit Wide General-Purpose Timer 3 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 3 is not reset. 1 32/64-bit wide general-purpose timer module 3 is reset. June 12, 2014 335 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name R2 R1 R0 Type RW RW RW Reset 0 Description 32/64-Bit Wide General-Purpose Timer 2 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 2 is not reset. 1 32/64-bit wide general-purpose timer module 2 is reset. 0 32/64-Bit Wide General-Purpose Timer 1 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 1 is not reset. 1 32/64-bit wide general-purpose timer module 1 is reset. 0 32/64-Bit Wide General-Purpose Timer 0 Software Reset Value Description 0 32/64-bit wide general-purpose timer module 0 is not reset. 1 32/64-bit wide general-purpose timer module 0 is reset. 336 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 58: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 The RCGCWD register provides software the capability to enable and disable watchdog modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, the RCGC0 register is available. A write to the RCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC0 register can be read back correctly with a read of the RCGC0 register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Run Mode Clock Gating Control (RCGCWD) Base 0x400F.E000 Offset 0x600 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Run Mode Clock Gating Control Value Description 0 Watchdog module 1 is disabled. 1 Enable and provide a clock to Watchdog module 1 in Run mode. 0 R0 RW 0 Watchdog Timer 0 Run Mode Clock Gating Control Value Description 0 Watchdog module 0 is disabled. 1 Enable and provide a clock to Watchdog module 0 in Run mode. June 12, 2014 337 Texas Instruments-Production Data System Control Register 59: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset 0x604 The RCGCTIMER register provides software the capability to enable and disable 16/32-bit timer modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, the RCGC1 register is available. A write to the RCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1 register can be read back correctly with a read of the RCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER) Base 0x400F.E000 Offset 0x604 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in Run mode. 338 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name R4 R3 R2 R1 R0 Type RW RW RW RW RW Reset 0 Description 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in Run mode. 0 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in Run mode. 0 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in Run mode. 0 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in Run mode. 0 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in Run mode. June 12, 2014 339 Texas Instruments-Production Data System Control Register 60: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset 0x608 The RCGCGPIO register provides software the capability to enable and disable GPIO modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, the RCGC2 register is available. A write to the RCGC2 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC2 register can be read back correctly with a read of the RCGC2 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in the RCGC2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO) Base 0x400F.E000 Offset 0x608 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port F Run Mode Clock Gating Control Value Description 0 GPIO Port F is disabled. 1 Enable and provide a clock to GPIO Port F in Run mode. 4 R4 RW 0 GPIO Port E Run Mode Clock Gating Control Value Description 0 GPIO Port E is disabled. 1 Enable and provide a clock to GPIO Port E in Run mode. 340 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name R3 R2 R1 R0 Type RW RW RW RW Reset 0 Description GPIO Port D Run Mode Clock Gating Control Value Description 0 GPIO Port D is disabled. 1 Enable and provide a clock to GPIO Port D in Run mode. 0 GPIO Port C Run Mode Clock Gating Control Value Description 0 GPIO Port C is disabled. 1 Enable and provide a clock to GPIO Port C in Run mode. 0 GPIO Port B Run Mode Clock Gating Control Value Description 0 GPIO Port B is disabled. 1 Enable and provide a clock to GPIO Port B in Run mode. 0 GPIO Port A Run Mode Clock Gating Control Value Description 0 GPIO Port A is disabled. 1 Enable and provide a clock to GPIO Port A in Run mode. June 12, 2014 341 Texas Instruments-Production Data System Control Register 61: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset 0x60C The RCGCDMA register provides software the capability to enable and disable the μDMA module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, the RCGC2 register is available. A write to the UDMA bit in the RCGC2 register also writes the R0 bit in this register. If the UDMA bit is changed by writing to the RCGC2 register, it can be read back correctly with a read of the RCGC2 register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but the UDMA bit in the RCGC2 register does not reflect the value of the R0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA) Base 0x400F.E000 Offset 0x60C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Run Mode Clock Gating Control Value Description 0 μDMA module is disabled. 1 Enable and provide a clock to the μDMA module in Run mode. 342 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 62: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 The RCGCHIB register provides software the capability to enable and disable the Hibernation module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, the RCGC0 register is available. A write to the HIB bit in the RCGC0 register also writes the R0 bit in this register. If the HIB bit is changed by writing to the RCGC0 register, it can be read back correctly with a read of the RCGC0 register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but the HIB bit in the RCGC0 register does not reflect the value of the R0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Run Mode Clock Gating Control (RCGCHIB) Base 0x400F.E000 Offset 0x614 Type RW, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Run Mode Clock Gating Control Value Description 0 Hibernation module is disabled. 1 Enable and provide a clock to the Hibernation module in Run mode. June 12, 2014 343 Texas Instruments-Production Data System Control Register 63: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), offset 0x618 The RCGCUART register provides software the capability to enable and disable the UART modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, the RCGC1 register is available. A write to the RCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1 register can be read back correctly with a read of the RCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART) Base 0x400F.E000 Offset 0x618 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R7 R6 R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7 Name reserved R7 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Run Mode Clock Gating Control Value Description 0 UART module 7 is disabled. 1 Enable and provide a clock to UART module 7 in Run mode. 6 R6 RW 0 UART Module 6 Run Mode Clock Gating Control Value Description 0 UART module 6 is disabled. 1 Enable and provide a clock to UART module 6 in Run mode. 344 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 5 4 3 2 1 0 Name R5 R4 R3 R2 R1 R0 Type RW RW RW RW RW RW Reset 0 Description UART Module 5 Run Mode Clock Gating Control Value Description 0 UART module 5 is disabled. 1 Enable and provide a clock to UART module 5 in Run mode. 0 UART Module 4 Run Mode Clock Gating Control Value Description 0 UART module 4 is disabled. 1 Enable and provide a clock to UART module 4 in Run mode. 0 UART Module 3 Run Mode Clock Gating Control Value Description 0 UART module 3 is disabled. 1 Enable and provide a clock to UART module 3 in Run mode. 0 UART Module 2 Run Mode Clock Gating Control Value Description 0 UART module 2 is disabled. 1 Enable and provide a clock to UART module 2 in Run mode. 0 UART Module 1 Run Mode Clock Gating Control Value Description 0 UART module 1 is disabled. 1 Enable and provide a clock to UART module 1 in Run mode. 0 UART Module 0 Run Mode Clock Gating Control Value Description 0 UART module 0 is disabled. 1 Enable and provide a clock to UART module 0 in Run mode. June 12, 2014 345 Texas Instruments-Production Data System Control Register 64: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset 0x61C The RCGCSSI register provides software the capability to enable and disable the SSI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, the RCGC1 register is available. A write to the RCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1 register can be read back correctly with a read of the RCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI) Base 0x400F.E000 Offset 0x61C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Run Mode Clock Gating Control Value Description 0 SSI module 3 is disabled. 1 Enable and provide a clock to SSI module 3 in Run mode. 2 R2 RW 0 SSI Module 2 Run Mode Clock Gating Control Value Description 0 SSI module 2 is disabled. 1 Enable and provide a clock to SSI module 2 in Run mode. 346 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name R1 R0 Type RW RW Reset 0 Description SSI Module 1 Run Mode Clock Gating Control Value Description 0 SSI module 1 is disabled. 1 Enable and provide a clock to SSI module 1 in Run mode. 0 SSI Module 0 Run Mode Clock Gating Control Value Description 0 SSI module 0 is disabled. 1 Enable and provide a clock to SSI module 0 in Run mode. June 12, 2014 347 Texas Instruments-Production Data System Control Register 65: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 The RCGCI2C register provides software the capability to enable and disable the I2C modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, the RCGC1 register is available. A write to the RCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1 register can be read back correctly with a read of the RCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C) Base 0x400F.E000 Offset 0x620 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 3 Run Mode Clock Gating Control Value Description 0 I2C module 3 is disabled. 1 Enable and provide a clock to I2C module 3 in Run mode. 2 R2 RW 0 I2C Module 2 Run Mode Clock Gating Control Value Description 0 I2C module 2 is disabled. 1 Enable and provide a clock to I2C module 2 in Run mode. 348 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name R1 R0 Type RW RW Reset 0 Description I2C Module 1 Run Mode Clock Gating Control Value Description 0 I2C module 1 is disabled. 1 Enable and provide a clock to I2C module 1 in Run mode. 0 I2C Module 0 Run Mode Clock Gating Control Value Description 0 I2C module 0 is disabled. 1 Enable and provide a clock to I2C module 0 in Run mode. June 12, 2014 349 Texas Instruments-Production Data System Control Register 66: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 The RCGCUSB register provides software the capability to enable and disable the USB module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the USB module. To support legacy software, the RCGC2 register is available. A write to the USB0 bit in the RCGC2 register also writes the R0 bit in this register. If the USB0 bit is changed by writing to the RCGC2 register, it can be read back correctly with a read of the RCGC2 register. If software uses this register to control the clock for the USB module, the write causes proper operation, but the USB0 bit in the RCGC2 register does not reflect the value of the R0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB) Base 0x400F.E000 Offset 0x628 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Run Mode Clock Gating Control Value Description 0 USB module is disabled. 1 Enable and provide a clock to the USB module in Run mode. 350 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 67: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 The RCGCCAN register provides software the capability to enable and disable the CAN modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, the RCGC0 register is available. A write to the RCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC0 register can be read back correctly with a read of the RCGC0 register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Run Mode Clock Gating Control (RCGCCAN) Base 0x400F.E000 Offset 0x634 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Run Mode Clock Gating Control Value Description 0 CAN module 1 is disabled. 1 Enable and provide a clock to CAN module 1 in Run mode. 0 R0 RW 0 CAN Module 0 Run Mode Clock Gating Control Value Description 0 CAN module 0 is disabled. 1 Enable and provide a clock to CAN module 0 in Run mode. June 12, 2014 351 Texas Instruments-Production Data System Control Register 68: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 The RCGCADC register provides software the capability to enable and disable the ADC modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, the RCGC0 register is available. A write to the RCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC0 register can be read back correctly with a read of the RCGC0 register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC) Base 0x400F.E000 Offset 0x638 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Run Mode Clock Gating Control Value Description 0 ADC module 1 is disabled. 1 Enable and provide a clock to ADC module 1 in Run mode. 0 R0 RW 0 ADC Module 0 Run Mode Clock Gating Control Value Description 0 ADC module 0 is disabled. 1 Enable and provide a clock to ADC module 0 in Run mode. 352 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 69: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C The RCGCACMP register provides software the capability to enable and disable the analog comparator module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, the RCGC1 register is available. Setting any of the COMPn bits in the RCGC1 register also sets the R0 bit in this register. If any of the COMPn bits are set by writing to the RCGC1 register, it can be read back correctly when reading the RCGC1 register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the value R0 is not reflected by the COMPn bits in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Run Mode Clock Gating Control (RCGCACMP) Base 0x400F.E000 Offset 0x63C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module 0 Run Mode Clock Gating Control Value Description 0 Analog comparator module is disabled. 1 Enable and provide a clock to the analog comparator module in Run mode. June 12, 2014 353 Texas Instruments-Production Data System Control Register 70: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 The RCGCPWM register provides software the capability to enable and disable the PWM modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the PWM modules. To support legacy software, the RCGC0 register is available. A write to the PWM bit in the RCGC0 register also writes the R0 bit in this register. If the PWM bit is changed by writing to the RCGC0 register, it can be read back correctly with a read of the RCGC0 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write to R0, the write causes proper operation, but the value of that bit is not reflected in the PWM bit in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM) Base 0x400F.E000 Offset 0x640 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Run Mode Clock Gating Control Value Description 0 PWM module 1 is disabled. 1 Enable and provide a clock to PWM module 1 in Run mode. 0 R0 RW 0 PWM Module 0 Run Mode Clock Gating Control Value Description 0 PWM module 0 is disabled. 1 Enable and provide a clock to PWM module 0 in Run mode. 354 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 71: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset 0x644 The RCGCQEI register provides software the capability to enable and disable the QEI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding RCGCn bits. Important: This register should be used to control the clocking for the QEI modules. To support legacy software, the RCGC1 register is available. A write to the RCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1 register can be read back correctly with a read of the RCGC1 register. If software uses this register to write a legacy peripheral (such as QEI0), the write causes proper operation, but the value of that bit is not reflected in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI) Base 0x400F.E000 Offset 0x644 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Run Mode Clock Gating Control Value Description 0 QEI module 1 is disabled. 1 Enable and provide a clock to QEI module 1 in Run mode. 0 R0 RW 0 QEI Module 0 Run Mode Clock Gating Control Value Description 0 QEI module 0 is disabled. 1 Enable and provide a clock to QEI module 0 in Run mode. June 12, 2014 355 Texas Instruments-Production Data System Control Register 72: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 The RCGCEEPROM register provides software the capability to enable and disable the EEPROM module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. EEPROM Run Mode Clock Gating Control (RCGCEEPROM) Base 0x400F.E000 Offset 0x658 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Run Mode Clock Gating Control Value Description 0 EEPROM module is disabled. 1 Enable and provide a clock to the EEPROM module in Run mode. 356 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 73: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER), offset 0x65C The RCGCWTIMER register provides software the capability to enable and disable 3264-bit timer modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacy Run Mode Clock Gating Control Register n RCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding RCGCn bits. 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER) Base 0x400F.E000 Offset 0x65C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in Run mode. 4 R4 RW 0 32/64-Bit Wide General-Purpose Timer 4 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in Run mode. 3 R3 RW 0 32/64-Bit Wide General-Purpose Timer 3 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in Run mode. June 12, 2014 357 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name R2 R1 R0 Type RW RW RW Reset 0 Description 32/64-Bit Wide General-Purpose Timer 2 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in Run mode. 0 32/64-Bit Wide General-Purpose Timer 1 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in Run mode. 0 32/64-Bit Wide General-Purpose Timer 0 Run Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in Run mode. 358 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 74: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 The SCGCWD register provides software the capability to enable and disable watchdog modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, the SCGC0 register is available. A write to the SCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC0 register can be read back correctly with a read of the SCGC0 register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in the SCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD) Base 0x400F.E000 Offset 0x700 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved S1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Sleep Mode Clock Gating Control Value Description 0 Watchdog module 1 is disabled. 1 Enable and provide a clock to Watchdog module 1 in sleep mode. 0 S0 RW 0 Watchdog Timer 0 Sleep Mode Clock Gating Control Value Description 0 Watchdog module 0 is disabled. 1 Enable and provide a clock to Watchdog module 0 in sleep mode. June 12, 2014 359 Texas Instruments-Production Data System Control Register 75: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset 0x704 The SCGCTIMER register provides software the capability to enable and disable 16/32-bit timer modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, the SCGC1 register is available. A write to the SCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1 register can be read back correctly with a read of the SCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER) Base 0x400F.E000 Offset 0x704 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S5 S4 S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved S5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in sleep mode. 4 S4 RW 0 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in sleep mode. 360 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name S3 S2 S1 S0 Type RW RW RW RW Reset 0 Description 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in sleep mode. 0 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in sleep mode. 0 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in sleep mode. 0 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in sleep mode. June 12, 2014 361 Texas Instruments-Production Data System Control Register 76: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset 0x708 The SCGCGPIO register provides software the capability to enable and disable GPIO modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, the SCGC2 register is available. A write to the SCGC2 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC2 register can be read back correctly with a read of the SCGC2 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in the SCGC2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO) Base 0x400F.E000 Offset 0x708 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S5 S4 S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved S5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port F Sleep Mode Clock Gating Control Value Description 0 GPIO Port F is disabled. 1 Enable and provide a clock to GPIO Port F in sleep mode. 4 S4 RW 0 GPIO Port E Sleep Mode Clock Gating Control Value Description 0 GPIO Port E is disabled. 1 Enable and provide a clock to GPIO Port E in sleep mode. 362 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name S3 S2 S1 S0 Type RW RW RW RW Reset 0 Description GPIO Port D Sleep Mode Clock Gating Control Value Description 0 GPIO Port D is disabled. 1 Enable and provide a clock to GPIO Port D in sleep mode. 0 GPIO Port C Sleep Mode Clock Gating Control Value Description 0 GPIO Port C is disabled. 1 Enable and provide a clock to GPIO Port C in sleep mode. 0 GPIO Port B Sleep Mode Clock Gating Control Value Description 0 GPIO Port B is disabled. 1 Enable and provide a clock to GPIO Port B in sleep mode. 0 GPIO Port A Sleep Mode Clock Gating Control Value Description 0 GPIO Port A is disabled. 1 Enable and provide a clock to GPIO Port A in sleep mode. June 12, 2014 363 Texas Instruments-Production Data System Control Register 77: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset 0x70C The SCGCDMA register provides software the capability to enable and disable the μDMA module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, the SCGC2 register is available. A write to the UDMA bit in the SCGC2 register also writes the S0 bit in this register. If the UDMA bit is changed by writing to the SCGC2 register, it can be read back correctly with a read of the SCGC2 register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but the UDMA bit in the SCGC2 register does not reflect the value of the S0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA) Base 0x400F.E000 Offset 0x70C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved S0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Sleep Mode Clock Gating Control Value Description 0 μDMA module is disabled. 1 Enable and provide a clock to the μDMA module in sleep mode. 364 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 78: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 The SCGCHIB register provides software the capability to enable and disable the Hibernation module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, the SCGC0 register is available. A write to the HIB bit in the SCGC0 register also writes the S0 bit in this register. If the HIB bit is changed by writing to the SCGC0 register, it can be read back correctly with a read of the SCGC0 register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but the HIB bit in the SCGC0 register does not reflect the value of the S0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Sleep Mode Clock Gating Control (SCGCHIB) Base 0x400F.E000 Offset 0x714 Type RW, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved S0 Type RO RW Reset 0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Sleep Mode Clock Gating Control Value Description 0 Hibernation module is disabled. 1 Enable and provide a clock to the Hibernation module in sleep mode. June 12, 2014 365 Texas Instruments-Production Data System Control Register 79: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART), offset 0x718 The SCGCUART register provides software the capability to enable and disable the UART modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, the SCGC1 register is available. A write to the SCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1 register can be read back correctly with a read of the SCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART) Base 0x400F.E000 Offset 0x718 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S7 S6 S5 S4 S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7 Name reserved S7 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Sleep Mode Clock Gating Control Value Description 0 UART module 7 is disabled. 1 Enable and provide a clock to UART module 7 in sleep mode. 6 S6 RW 0 UART Module 6 Sleep Mode Clock Gating Control Value Description 0 UART module 6 is disabled. 1 Enable and provide a clock to UART module 6 in sleep mode. 366 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 5 4 3 2 1 0 Name S5 S4 S3 S2 S1 S0 Type RW RW RW RW RW RW Reset 0 Description UART Module 5 Sleep Mode Clock Gating Control Value Description 0 UART module 5 is disabled. 1 Enable and provide a clock to UART module 5 in sleep mode. 0 UART Module 4 Sleep Mode Clock Gating Control Value Description 0 UART module 4 is disabled. 1 Enable and provide a clock to UART module 4 in sleep mode. 0 UART Module 3 Sleep Mode Clock Gating Control Value Description 0 UART module 3 is disabled. 1 Enable and provide a clock to UART module 3 in sleep mode. 0 UART Module 2 Sleep Mode Clock Gating Control Value Description 0 UART module 2 is disabled. 1 Enable and provide a clock to UART module 2 in sleep mode. 0 UART Module 1 Sleep Mode Clock Gating Control Value Description 0 UART module 1 is disabled. 1 Enable and provide a clock to UART module 1 in sleep mode. 0 UART Module 0 Sleep Mode Clock Gating Control Value Description 0 UART module 0 is disabled. 1 Enable and provide a clock to UART module 0 in sleep mode. June 12, 2014 367 Texas Instruments-Production Data System Control Register 80: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset 0x71C The SCGCSSI register provides software the capability to enable and disable the SSI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, the SCGC1 register is available. A write to the SCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1 register can be read back correctly with a read of the SCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI) Base 0x400F.E000 Offset 0x71C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved S3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Sleep Mode Clock Gating Control Value Description 0 SSI module 3 is disabled. 1 Enable and provide a clock to SSI module 3 in sleep mode. 2 S2 RW 0 SSI Module 2 Sleep Mode Clock Gating Control Value Description 0 SSI module 2 is disabled. 1 Enable and provide a clock to SSI module 2 in sleep mode. 368 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name S1 S0 Type RW RW Reset 0 Description SSI Module 1 Sleep Mode Clock Gating Control Value Description 0 SSI module 1 is disabled. 1 Enable and provide a clock to SSI module 1 in sleep mode. 0 SSI Module 0 Sleep Mode Clock Gating Control Value Description 0 SSI module 0 is disabled. 1 Enable and provide a clock to SSI module 0 in sleep mode. June 12, 2014 369 Texas Instruments-Production Data System Control Register 81: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 The SCGCI2C register provides software the capability to enable and disable the I2C modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, the SCGC1 register is available. A write to the SCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1 register can be read back correctly with a read of the SCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C) Base 0x400F.E000 Offset 0x720 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved S3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 3 Sleep Mode Clock Gating Control Value Description 0 I2C module 3 is disabled. 1 Enable and provide a clock to I2C module 3 in sleep mode. 2 S2 RW 0 I2C Module 2 Sleep Mode Clock Gating Control Value Description 0 I2C module 2 is disabled. 1 Enable and provide a clock to I2C module 2 in sleep mode. 370 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name S1 S0 Type RW RW Reset 0 Description I2C Module 1 Sleep Mode Clock Gating Control Value Description 0 I2C module 1 is disabled. 1 Enable and provide a clock to I2C module 1 in sleep mode. 0 I2C Module 0 Sleep Mode Clock Gating Control Value Description 0 I2C module 0 is disabled. 1 Enable and provide a clock to I2C module 0 in sleep mode. June 12, 2014 371 Texas Instruments-Production Data System Control Register 82: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 The SCGCUSB register provides software the capability to enable and disable the USB module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the USB module. To support legacy software, the SCGC2 register is available. A write to the USB0 bit in the SCGC2 register also writes the S0 bit in this register. If the USB0 bit is changed by writing to the SCGC2 register, it can be read back correctly with a read of the SCGC2 register. If software uses this register to control the clock for the USB module, the write causes proper operation, but the USB0 bit in the SCGC2 register does not reflect the value of the S0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB) Base 0x400F.E000 Offset 0x728 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved S0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Sleep Mode Clock Gating Control Value Description 0 USB module is disabled. 1 Enable and provide a clock to the USB module in sleep mode. 372 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 83: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 The SCGCCAN register provides software the capability to enable and disable the CAN modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, the SCGC0 register is available. A write to the SCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC0 register can be read back correctly with a read of the SCGC0 register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in the SCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN) Base 0x400F.E000 Offset 0x734 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved S1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Sleep Mode Clock Gating Control Value Description 0 CAN module 1 is disabled. 1 Enable and provide a clock to CAN module 1 in sleep mode. 0 S0 RW 0 CAN Module 0 Sleep Mode Clock Gating Control Value Description 0 CAN module 0 is disabled. 1 Enable and provide a clock to CAN module 0 in sleep mode. June 12, 2014 373 Texas Instruments-Production Data System Control Register 84: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset 0x738 The SCGCADC register provides software the capability to enable and disable the ADC modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, the SCGC0 register is available. A write to the SCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC0 register can be read back correctly with a read of the SCGC0 register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in the SCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC) Base 0x400F.E000 Offset 0x738 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved S1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Sleep Mode Clock Gating Control Value Description 0 ADC module 1 is disabled. 1 Enable and provide a clock to ADC module 1 in sleep mode. 0 S0 RW 0 ADC Module 0 Sleep Mode Clock Gating Control Value Description 0 ADC module 0 is disabled. 1 Enable and provide a clock to ADC module 0 in sleep mode. 374 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 85: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C The SCGCACMP register provides software the capability to enable and disable the analog comparator module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, the SCGC1 register is available. Setting any of the COMPn bits in the SCGC1 register also sets the S0 bit in this register. If any of the COMPn bits are set by writing to the SCGC1 register, it can be read back correctly when reading the SCGC1 register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the value S0 is not reflected by the COMPn bits in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP) Base 0x400F.E000 Offset 0x73C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved S0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module 0 Sleep Mode Clock Gating Control Value Description 0 Analog comparator module is disabled. 1 Enable and provide a clock to the analog comparator module in sleep mode. June 12, 2014 375 Texas Instruments-Production Data System Control Register 86: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 The SCGCPWM register provides software the capability to enable and disable the PWM modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the PWM modules. To support legacy software, the SCGC0 register is available. A write to the PWM bit in the SCGC0 register also writes the S0 bit in this register. If the PWM bit is changed by writing to the SCGC0 register, it can be read back correctly with a read of the SCGC0 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write to S0, the write causes proper operation, but the value of that bit is not reflected in the PWM bit in the SCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM) Base 0x400F.E000 Offset 0x740 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved S1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Sleep Mode Clock Gating Control Value Description 0 PWM module 1 is disabled. 1 Enable and provide a clock to PWM module 1 in sleep mode. 0 S0 RW 0 PWM Module 0 Sleep Mode Clock Gating Control Value Description 0 PWM module 0 is disabled. 1 Enable and provide a clock to PWM module 0 in sleep mode. 376 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 87: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset 0x744 The SCGCQEI register provides software the capability to enable and disable the QEI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding SCGCn bits. Important: This register should be used to control the clocking for the QEI modules. To support legacy software, the SCGC1 register is available. A write to the SCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1 register can be read back correctly with a read of the SCGC1 register. If software uses this register to write a legacy peripheral (such as QEI0), the write causes proper operation, but the value of that bit is not reflected in the SCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI) Base 0x400F.E000 Offset 0x744 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S1 S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved S1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Sleep Mode Clock Gating Control Value Description 0 QEI module 1 is disabled. 1 Enable and provide a clock to QEI module 1 in sleep mode. 0 S0 RW 0 QEI Module 0 Sleep Mode Clock Gating Control Value Description 0 QEI module 0 is disabled. 1 Enable and provide a clock to QEI module 0 in sleep mode. June 12, 2014 377 Texas Instruments-Production Data System Control Register 88: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 The SCGCEEPROM register provides software the capability to enable and disable the EEPROM module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM) Base 0x400F.E000 Offset 0x758 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved S0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Sleep Mode Clock Gating Control Value Description 0 EEPROM module is disabled. 1 Enable and provide a clock to the EEPROM module in sleep mode. 378 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 89: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER), offset 0x75C The SCGCWTIMER register provides software the capability to enable and disable 3264-bit timer modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating Control Register n SCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding SCGCn bits. 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER) Base 0x400F.E000 Offset 0x75C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S5 S4 S3 S2 S1 S0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved S5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in sleep mode. 4 S4 RW 0 32/64-Bit Wide General-Purpose Timer 4 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in sleep mode. 3 S3 RW 0 32/64-Bit Wide General-Purpose Timer 3 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in sleep mode. June 12, 2014 379 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name S2 S1 S0 Type RW RW RW Reset 0 Description 32/64-Bit Wide General-Purpose Timer 2 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in sleep mode. 0 32/64-Bit Wide General-Purpose Timer 1 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in sleep mode. 0 32/64-Bit Wide General-Purpose Timer 0 Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in sleep mode. 380 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 90: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 The DCGCWD register provides software the capability to enable and disable watchdog modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, the DCGC0 register is available. A write to the DCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC0 register can be read back correctly with a read of the DCGC0 register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in the DCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD) Base 0x400F.E000 Offset 0x800 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved D1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control Value Description 0 Watchdog module 1 is disabled. 1 Enable and provide a clock to Watchdog module 1 in deep-sleep mode. 0 D0 RW 0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control Value Description 0 Watchdog module 0 is disabled. 1 Enable and provide a clock to Watchdog module 0 in deep-sleep mode. June 12, 2014 381 Texas Instruments-Production Data System Control Register 91: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER), offset 0x804 The DCGCTIMER register provides software the capability to enable and disable 16/32-bit timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, the DCGC1 register is available. A write to the DCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1 register can be read back correctly with a read of the DCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER) Base 0x400F.E000 Offset 0x804 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D5 D4 D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved D5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in deep-sleep mode. 382 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name D4 D3 D2 D1 D0 Type RW RW RW RW RW Reset 0 Description 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in deep-sleep mode. 0 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in deep-sleep mode. 0 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in deep-sleep mode. 0 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in deep-sleep mode. 0 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control Value Description 0 16/32-bit general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in deep-sleep mode. June 12, 2014 383 Texas Instruments-Production Data System Control Register 92: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset 0x808 The DCGCGPIO register provides software the capability to enable and disable GPIO modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, the DCGC2 register is available. A write to the DCGC2 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC2 register can be read back correctly with a read of the DCGC2 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in the DCGC2 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO) Base 0x400F.E000 Offset 0x808 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D5 D4 D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved D5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port F Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port F is disabled. 1 Enable and provide a clock to GPIO Port F in deep-sleep mode. 4 D4 RW 0 GPIO Port E Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port E is disabled. 1 Enable and provide a clock to GPIO Port E in deep-sleep mode. 384 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name D3 D2 D1 D0 Type RW RW RW RW Reset 0 Description GPIO Port D Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port D is disabled. 1 Enable and provide a clock to GPIO Port D in deep-sleep mode. 0 GPIO Port C Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port C is disabled. 1 Enable and provide a clock to GPIO Port C in deep-sleep mode. 0 GPIO Port B Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port B is disabled. 1 Enable and provide a clock to GPIO Port B in deep-sleep mode. 0 GPIO Port A Deep-Sleep Mode Clock Gating Control Value Description 0 GPIO Port A is disabled. 1 Enable and provide a clock to GPIO Port A in deep-sleep mode. June 12, 2014 385 Texas Instruments-Production Data System Control Register 93: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset 0x80C The DCGCDMA register provides software the capability to enable and disable the μDMA module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, the DCGC2 register is available. A write to the UDMA bit in the DCGC2 register also writes the D0 bit in this register. If the UDMA bit is changed by writing to the DCGC2 register, it can be read back correctly with a read of the DCGC2 register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but the UDMA bit in the DCGC2 register does not reflect the value of the D0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA) Base 0x400F.E000 Offset 0x80C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved D0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Deep-Sleep Mode Clock Gating Control Value Description 0 μDMA module is disabled. 1 Enable and provide a clock to the μDMA module in deep-sleep mode. 386 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 94: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 The DCGCHIB register provides software the capability to enable and disable the Hibernation module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, the DCGC0 register is available. A write to the HIB bit in the DCGC0 register also writes the D0 bit in this register. If the HIB bit is changed by writing to the DCGC0 register, it can be read back correctly with a read of the DCGC0 register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but the HIB bit in the DCGC0 register does not reflect the value of the D0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB) Base 0x400F.E000 Offset 0x814 Type RW, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved D0 Type RO RW Reset 0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Deep-Sleep Mode Clock Gating Control Value Description 0 Hibernation module is disabled. 1 Enable and provide a clock to the Hibernation module in deep-sleep mode. June 12, 2014 387 Texas Instruments-Production Data System Control Register 95: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART), offset 0x818 The DCGCUART register provides software the capability to enable and disable the UART modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, the DCGC1 register is available. A write to the DCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1 register can be read back correctly with a read of the DCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART) Base 0x400F.E000 Offset 0x818 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D7 D6 D5 D4 D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7 Name reserved D7 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 7 is disabled. 1 Enable and provide a clock to UART module 7 in deep-sleep mode. 6 D6 RW 0 UART Module 6 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 6 is disabled. 1 Enable and provide a clock to UART module 6 in deep-sleep mode. 388 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 5 4 3 2 1 0 Name D5 D4 D3 D2 D1 D0 Type RW RW RW RW RW RW Reset 0 Description UART Module 5 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 5 is disabled. 1 Enable and provide a clock to UART module 5 in deep-sleep mode. 0 UART Module 4 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 4 is disabled. 1 Enable and provide a clock to UART module 4 in deep-sleep mode. 0 UART Module 3 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 3 is disabled. 1 Enable and provide a clock to UART module 3 in deep-sleep mode. 0 UART Module 2 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 2 is disabled. 1 Enable and provide a clock to UART module 2 in deep-sleep mode. 0 UART Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 1 is disabled. 1 Enable and provide a clock to UART module 1 in deep-sleep mode. 0 UART Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 UART module 0 is disabled. 1 Enable and provide a clock to UART module 0 in deep-sleep mode. June 12, 2014 389 Texas Instruments-Production Data System Control Register 96: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset 0x81C The DCGCSSI register provides software the capability to enable and disable the SSI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, the DCGC1 register is available. A write to the DCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1 register can be read back correctly with a read of the DCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI) Base 0x400F.E000 Offset 0x81C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved D3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Deep-Sleep Mode Clock Gating Control Value Description 0 SSI module 3 is disabled. 1 Enable and provide a clock to SSI module 3 in deep-sleep mode. 2 D2 RW 0 SSI Module 2 Deep-Sleep Mode Clock Gating Control Value Description 0 SSI module 2 is disabled. 1 Enable and provide a clock to SSI module 2 in deep-sleep mode. 390 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name D1 D0 Type RW RW Reset 0 Description SSI Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 SSI module 1 is disabled. 1 Enable and provide a clock to SSI module 1 in deep-sleep mode. 0 SSI Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 SSI module 0 is disabled. 1 Enable and provide a clock to SSI module 0 in deep-sleep mode. June 12, 2014 391 Texas Instruments-Production Data System Control Register 97: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset 0x820 The DCGCI2C register provides software the capability to enable and disable the I2C modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, the DCGC1 register is available. A write to the DCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1 register can be read back correctly with a read of the DCGC1 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C) Base 0x400F.E000 Offset 0x820 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved D3 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 3 Deep-Sleep Mode Clock Gating Control Value Description 0 I2C module 3 is disabled. 1 Enable and provide a clock to I2C module 3 in deep-sleep mode. 2 D2 RW 0 I2C Module 2 Deep-Sleep Mode Clock Gating Control Value Description 0 I2C module 2 is disabled. 1 Enable and provide a clock to I2C module 2 in deep-sleep mode. 392 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 1 0 Name D1 D0 Type RW RW Reset 0 Description I2C Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 I2C module 1 is disabled. 1 Enable and provide a clock to I2C module 1 in deep-sleep mode. 0 I2C Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 I2C module 0 is disabled. 1 Enable and provide a clock to I2C module 0 in deep-sleep mode. June 12, 2014 393 Texas Instruments-Production Data System Control Register 98: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset 0x828 The DCGCUSB register provides software the capability to enable and disable the USB module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the USB module. To support legacy software, the DCGC2 register is available. A write to the USB0 bit in the DCGC2 register also writes the D0 bit in this register. If the USB0 bit is changed by writing to the DCGC2 register, it can be read back correctly with a read of the DCGC2 register. If software uses this register to control the clock for the USB module, the write causes proper operation, but the USB0 bit in the DCGC2 register does not reflect the value of the D0 bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB) Base 0x400F.E000 Offset 0x828 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved D0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Deep-Sleep Mode Clock Gating Control Value Description 0 USB module is disabled. 1 Enable and provide a clock to the USB module in deep-sleep mode. 394 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 99: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset 0x834 The DCGCCAN register provides software the capability to enable and disable the CAN modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, the DCGC0 register is available. A write to the DCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC0 register can be read back correctly with a read of the DCGC0 register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in the DCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN) Base 0x400F.E000 Offset 0x834 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved D1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 CAN module 1 is disabled. 1 Enable and provide a clock to CAN module 1 in deep-sleep mode. 0 D0 RW 0 CAN Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 CAN module 0 is disabled. 1 Enable and provide a clock to CAN module 0 in deep-sleep mode. June 12, 2014 395 Texas Instruments-Production Data System Control Register 100: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset 0x838 The DCGCADC register provides software the capability to enable and disable the ADC modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, the DCGC0 register is available. A write to the DCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC0 register can be read back correctly with a read of the DCGC0 register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in the DCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC) Base 0x400F.E000 Offset 0x838 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved D1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 ADC module 1 is disabled. 1 Enable and provide a clock to ADC module 1 in deep-sleep mode. 0 D0 RW 0 ADC Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 ADC module 0 is disabled. 1 Enable and provide a clock to ADC module 0 in deep-sleep mode. 396 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 101: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset 0x83C The DCGCACMP register provides software the capability to enable and disable the analog comparator module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, the DCGC1 register is available. Setting any of the COMPn bits in the DCGC1 register also sets the D0 bit in this register. If any of the COMPn bits are set by writing to the DCGC1 register, it can be read back correctly when reading the DCGC1 register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the value D0 is not reflected by the COMPn bits in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP) Base 0x400F.E000 Offset 0x83C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved D0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 Analog comparator module is disabled. 1 Enable and provide a clock to the analog comparator module in deep-sleep mode. June 12, 2014 397 Texas Instruments-Production Data System Control Register 102: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset 0x840 The DCGCPWM register provides software the capability to enable and disable the PWM modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the PWM modules. To support legacy software, the DCGC0 register is available. A write to the PWM bit in the DCGC0 register also writes the D0 bit in this register. If the PWM bit is changed by writing to the DCGC0 register, it can be read back correctly with a read of the DCGC0 register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write to D0, the write causes proper operation, but the value of that bit is not reflected in the PWM bit in the DCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM) Base 0x400F.E000 Offset 0x840 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved D1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 PWM module 1 is disabled. 1 Enable and provide a clock to PWM module 1 in deep-sleep mode. 0 D0 RW 0 PWM Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 PWM module 0 is disabled. 1 Enable and provide a clock to PWM module 0 in deep-sleep mode. 398 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 103: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset 0x844 The DCGCQEI register provides software the capability to enable and disable the QEI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has the same bit polarity as the corresponding DCGCn bits. Important: This register should be used to control the clocking for the QEI modules. To support legacy software, the DCGC1 register is available. A write to the DCGC1 register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1 register can be read back correctly with a read of the DCGC1 register. If software uses this register to write a legacy peripheral (such as QEI0), the write causes proper operation, but the value of that bit is not reflected in the DCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI) Base 0x400F.E000 Offset 0x844 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D1 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved D1 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Deep-Sleep Mode Clock Gating Control Value Description 0 QEI module 1 is disabled. 1 Enable and provide a clock to QEI module 1 in deep-sleep mode. 0 D0 RW 0 QEI Module 0 Deep-Sleep Mode Clock Gating Control Value Description 0 QEI module 0 is disabled. 1 Enable and provide a clock to QEI module 0 in deep-sleep mode. June 12, 2014 399 Texas Instruments-Production Data System Control Register 104: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 The DCGCEEPROM register provides software the capability to enable and disable the EEPROM module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM) Base 0x400F.E000 Offset 0x858 Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved D0 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Deep-Sleep Mode Clock Gating Control Value Description 0 EEPROM module is disabled. 1 Enable and provide a clock to the EEPROM module in deep-sleep mode. 400 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 105: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER), offset 0x85C The DCGCWTIMER register provides software the capability to enable and disable 32/64-bit wide timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the timer modules and has the same bit polarity as the corresponding DCGCn bits. 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER) Base 0x400F.E000 Offset 0x85C Type RW, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved D5 D4 D3 D2 D1 D0 Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved D5 Type RO RW Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 5 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in deep-sleep mode. 4 D4 RW 0 32/64-Bit Wide General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in deep-sleep mode. 3 D3 RW 0 32/64-Bit Wide General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 3 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in deep-sleep mode. June 12, 2014 401 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name D2 D1 D0 Type RW RW RW Reset 0 Description 32/64-Bit Wide General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 2 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in deep-sleep mode. 0 32/64-Bit Wide General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 1 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in deep-sleep mode. 0 32/64-Bit Wide General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control Value Description 0 32/64-bit wide general-purpose timer module 0 is disabled. 1 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in deep-sleep mode. 402 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 106: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 The PRWD register indicates whether the watchdog modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCWD bit is changed. A reset change is initiated if the corresponding SRWD bit is changed from 0 to 1. The PRWD bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Watchdog Timer Peripheral Ready (PRWD) Base 0x400F.E000 Offset 0xA00 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Peripheral Ready Value Description 0 Watchdog module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 Watchdog module 1 is ready for access. 0 R0 RO 0 Watchdog Timer 0 Peripheral Ready Value Description 0 Watchdog module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 Watchdog module 0 is ready for access. June 12, 2014 403 Texas Instruments-Production Data System Control Register 107: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 The PRTIMER register indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCTIMER bit is changed. A reset change is initiated if the corresponding SRTIMER bit is changed from 0 to 1. The PRTIMER bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER) Base 0x400F.E000 Offset 0xA04 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16/32-Bit General-Purpose Timer 5 Peripheral Ready Value Description 0 16/32-bit timer module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 5 is ready for access. 4 R4 RO 0 16/32-Bit General-Purpose Timer 4 Peripheral Ready Value Description 0 16/32-bit timer module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 4 is ready for access. 3 R3 RO 0 16/32-Bit General-Purpose Timer 3 Peripheral Ready Value Description 0 16/32-bit timer module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 3 is ready for access. 404 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name R2 R1 R0 Type RO RO RO Reset 0 Description 16/32-Bit General-Purpose Timer 2 Peripheral Ready Value Description 0 16/32-bit timer module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 2 is ready for access. 0 16/32-Bit General-Purpose Timer 1 Peripheral Ready Value Description 0 16/32-bit timer module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 1 is ready for access. 0 16/32-Bit General-Purpose Timer 0 Peripheral Ready Value Description 0 16/32-bit timer module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 0 is ready for access. June 12, 2014 405 Texas Instruments-Production Data System Control Register 108: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCGPIO bit is changed. A reset change is initiated if the corresponding SRGPIO bit is changed from 0 to 1. The PRGPIO bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. General-Purpose Input/Output Peripheral Ready (PRGPIO) Base 0x400F.E000 Offset 0xA08 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port F Peripheral Ready Value Description 0 GPIO Port F is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port F is ready for access. 4 R4 RO 0 GPIO Port E Peripheral Ready Value Description 0 GPIO Port E is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port E is ready for access. 3 R3 RO 0 GPIO Port D Peripheral Ready Value Description 0 GPIO Port D is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port D is ready for access. 406 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 2 1 0 Name R2 R1 R0 Type RO RO RO Reset 0 Description GPIO Port C Peripheral Ready Value Description 0 GPIO Port C is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port C is ready for access. 0 GPIO Port B Peripheral Ready Value Description 0 GPIO Port B is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port B is ready for access. 0 GPIO Port A Peripheral Ready Value Description 0 GPIO Port A is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port A is ready for access. June 12, 2014 407 Texas Instruments-Production Data System Control Register 109: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C The PRDMA register indicates whether the μDMA module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCDMA bit is changed. A reset change is initiated if the corresponding SRDMA bit is changed from 0 to 1. The PRDMA bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Micro Direct Memory Access Peripheral Ready (PRDMA) Base 0x400F.E000 Offset 0xA0C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Module Peripheral Ready Value Description 0 The μDMA module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 The μDMA module is ready for access. 408 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 110: Hibernation Peripheral Ready (PRHIB), offset 0xA14 The PRHIB register indicates whether the Hibernation module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCHIB bit is changed. A reset change is initiated if the corresponding SRHIB bit is changed from 0 to 1. The PRHIB bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Hibernation Peripheral Ready (PRHIB) Base 0x400F.E000 Offset 0xA14 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field 31:1 0 Name reserved R0 Type RO RO Reset 0 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hibernation Module Peripheral Ready Value Description 0 The Hibernation module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 The Hibernation module is ready for access. June 12, 2014 409 Texas Instruments-Production Data System Control Register 111: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 0xA18 The PRUART register indicates whether the UART modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCUART bit is changed. A reset change is initiated if the corresponding SRUART bit is changed from 0 to 1. The PRUART bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART) Base 0x400F.E000 Offset 0xA18 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R7 R6 R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:8 7 Name reserved R7 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Module 7 Peripheral Ready Value Description 0 UART module 7 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 7 is ready for access. 6 R6 RO 0 UART Module 6 Peripheral Ready Value Description 0 UART module 6 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 6 is ready for access. 5 R5 RO 0 UART Module 5 Peripheral Ready Value Description 0 UART module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 5 is ready for access. 410 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 4 3 2 1 0 Name R4 R3 R2 R1 R0 Type RO RO RO RO RO Reset 0 Description UART Module 4 Peripheral Ready Value Description 0 UART module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 4 is ready for access. 0 UART Module 3 Peripheral Ready Value Description 0 UART module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 3 is ready for access. 0 UART Module 2 Peripheral Ready Value Description 0 UART module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 2 is ready for access. 0 UART Module 1 Peripheral Ready Value Description 0 UART module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 1 is ready for access. 0 UART Module 0 Peripheral Ready Value Description 0 UART module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 0 is ready for access. June 12, 2014 411 Texas Instruments-Production Data System Control Register 112: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C The PRSSI register indicates whether the SSI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCSSI bit is changed. A reset change is initiated if the corresponding SRSSI bit is changed from 0 to 1. The PRSSI bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Synchronous Serial Interface Peripheral Ready (PRSSI) Base 0x400F.E000 Offset 0xA1C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 3 Peripheral Ready Value Description 0 SSI module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 SSI module 3 is ready for access. 2 R2 RO 0 SSI Module 2 Peripheral Ready Value Description 0 SSI module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 SSI module 2 is ready for access. 1 R1 RO 0 SSI Module 1 Peripheral Ready Value Description 0 SSI module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 SSI module 1 is ready for access. 412 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name R0 Type RO Reset 0 Description SSI Module 0 Peripheral Ready Value Description 0 SSI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 SSI module 0 is ready for access. June 12, 2014 413 Texas Instruments-Production Data System Control Register 113: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 The PRI2C register indicates whether the I2C modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCI2C bit is changed. A reset change is initiated if the corresponding SRI2C bit is changed from 0 to 1. The PRI2C bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Inter-Integrated Circuit Peripheral Ready (PRI2C) Base 0x400F.E000 Offset 0xA20 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:4 3 Name reserved R3 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 3 Peripheral Ready Value Description 0 I2C module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 3 is ready for access. 2 R2 RO 0 I2C Module 2 Peripheral Ready Value Description 0 I2C module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 2 is ready for access. 1 R1 RO 0 I2C Module 1 Peripheral Ready Value Description 0 I2C module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 1 is ready for access. 414 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name R0 Type RO Reset 0 Description I2C Module 0 Peripheral Ready Value Description 0 I2C module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 0 is ready for access. June 12, 2014 415 Texas Instruments-Production Data System Control Register 114: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28 The PRUSB register indicates whether the USB module is ready to be accessed by software following a change in Run mode clocking or reset. A Run mode clocking change is initiated if the corresponding RCGCUSB bit is changed. A reset change is initiated if the corresponding SRUSB bit is changed from 0 to 1. The PRUSB bit is cleared on either of the above events and is not set again until the module is completely powered, enabled, and internally reset. Universal Serial Bus Peripheral Ready (PRUSB) Base 0x400F.E000 Offset 0xA28 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module Peripheral Ready Value Description 0 The USB module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 The USB module is ready for access. 416 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 115: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 The PRCAN register indicates whether the CAN modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCCAN bit is changed. A reset change is initiated if the corresponding SRCAN bit is changed from 0 to 1. The PRCAN bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Controller Area Network Peripheral Ready (PRCAN) Base 0x400F.E000 Offset 0xA34 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Peripheral Ready Value Description 0 CAN module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 CAN module 1 is ready for access. 0 R0 RO 0 CAN Module 0 Peripheral Ready Value Description 0 CAN module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 CAN module 0 is ready for access. June 12, 2014 417 Texas Instruments-Production Data System Control Register 116: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 The PRADC register indicates whether the ADC modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCADC bit is changed. A reset change is initiated if the corresponding SRADC bit is changed from 0 to 1. The PRADC bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Analog-to-Digital Converter Peripheral Ready (PRADC) Base 0x400F.E000 Offset 0xA38 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Peripheral Ready Value Description 0 ADC module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 ADC module 1 is ready for access. 0 R0 RO 0 ADC Module 0 Peripheral Ready Value Description 0 ADC module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 ADC module 0 is ready for access. 418 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 117: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C The PRACMP register indicates whether the analog comparator module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCACMP bit is changed. A reset change is initiated if the corresponding SRACMP bit is changed from 0 to 1. The PRACMP bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Analog Comparator Peripheral Ready (PRACMP) Base 0x400F.E000 Offset 0xA3C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator Module 0 Peripheral Ready Value Description 0 The analog comparator module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 The analog comparator module is ready for access. June 12, 2014 419 Texas Instruments-Production Data System Control Register 118: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 The PRPWM register indicates whether the PWM modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCPWM bit is changed. A reset change is initiated if the corresponding SRPWM bit is changed from 0 to 1. The PRPWM bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Pulse Width Modulator Peripheral Ready (PRPWM) Base 0x400F.E000 Offset 0xA40 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Peripheral Ready Value Description 0 PWM module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 PWM module 1 is ready for access. 0 R0 RO 0 PWM Module 0 Peripheral Ready Value Description 0 PWM module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 PWM module 0 is ready for access. 420 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 119: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 The PRQEI register indicates whether the QEI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCQEI bit is changed. A reset change is initiated if the corresponding SRQEI bit is changed from 0 to 1. The PRQEI bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Quadrature Encoder Interface Peripheral Ready (PRQEI) Base 0x400F.E000 Offset 0xA44 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:2 1 Name reserved R1 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Peripheral Ready Value Description 0 QEI module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 QEI module 1 is ready for access. 0 R0 RO 0 QEI Module 0 Peripheral Ready Value Description 0 QEI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 QEI module 0 is ready for access. June 12, 2014 421 Texas Instruments-Production Data System Control Register 120: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 The PREEPROM register indicates whether the EEPROM module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCEEPROM bit is changed. A reset change is initiated if the corresponding SREEPROM bit is changed from 0 to 1. The PREEPROM bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. EEPROM Peripheral Ready (PREEPROM) Base 0x400F.E000 Offset 0xA58 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:1 0 Name reserved R0 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EEPROM Module Peripheral Ready Value Description 0 The EEPROM module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 The EEPROM module is ready for access. 422 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 121: 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C The PRWTIMER register indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the corresponding RCGCWTIMER bit is changed. A reset change is initiated if the corresponding SRWTIMER bit is changed from 0 to 1. The PRWTIMER bit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER) Base 0x400F.E000 Offset 0xA5C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved R5 R4 R3 R2 R1 R0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field 31:6 5 Name reserved R5 Type RO RO Reset 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready Value Description 0 32/64-bit wide timer module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 5 is ready for access. 4 R4 RO 0 32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready Value Description 0 32/64-bit wide timer module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 4 is ready for access. 3 R3 RO 0 32/64-Bit Wide General-Purpose Timer 3 Peripheral Ready Value Description 0 32/64-bit wide timer module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 3 is ready for access. June 12, 2014 423 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name R2 R1 R0 Type RO RO RO Reset 0 Description 32/64-Bit Wide General-Purpose Timer 2 Peripheral Ready Value Description 0 32/64-bit wide timer module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 2 is ready for access. 0 32/64-Bit Wide General-Purpose Timer 1 Peripheral Ready Value Description 0 32/64-bit wide timer module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 1 is ready for access. 0 32/64-Bit Wide General-Purpose Timer 0 Peripheral Ready Value Description 0 32/64-bit wide timer module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 32/64-bit wide timer module 0 is ready for access. 5.6 System Control Legacy Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. Important: Register in this section are provided for legacy software support only; registers in “System Control Register Descriptions” on page 237 should be used instead. 424 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 122: Device Capabilities 0 (DC0), offset 0x008 This legacy register is predefined by the part and can be used to verify features. Important: This register is provided for legacy software support only. The Flash Size (FSIZE) and SRAM Size (SSIZE) registers should be used to determine this microcontroller's memory sizes. A read of DC0 correctly identifies legacy memory sizes but software must use FSIZE and SSIZE for memory sizes that are not listed below. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x007F.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field 31:16 Name SRAMSZ Type RO Reset 0x7F Description SRAM Size Indicates the size of the on-chip SRAM. Value Description 0x7 2 KB of SRAM 0xF 4 KB of SRAM 0x17 6 KB of SRAM 0x1F 8 KB of SRAM 0x2F 12 KB of SRAM 0x3F 16 KB of SRAM 0x4F 20 KB of SRAM 0x5F 24 KB of SRAM 0x7F 32 KB of SRAM June 12, 2014 425 Texas Instruments-Production Data System Control Bit/Field 15:0 Name FLASHSZ Type RO Reset 0x7F Description Flash Size Indicates the size of the on-chip Flash memory. Value Description 0x3 8 KB of Flash 0x7 16 KB of Flash 0xF 32 KB of Flash 0x1F 64 KB of Flash 0x2F 96 KB of Flash 0x3F 128 KB of Flash 0x5F 192 KB of Flash 0x7F 256 KB of Flash 426 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 123: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, DCGC0, and the peripheral-specific RCGC, SCGC, and DCGC registers cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read of DC1 correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by the DCn registers. Likewise, the ADC Peripheral Properties (ADCPP) register should be used to determine the maximum ADC sample rate and whether the temperature sensor is present. However, to support legacy software, the MAXADCnSPD fields and the TEMPSNS bit are available. A read of DC1 correctly identifies the maximum ADC sample rate for legacy rates and whether the temperature sensor is present. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x1333.2FFF 31 30 29 28 reserved WDT1 Type RO RO RO RO Reset 0 0 0 1 15 14 13 12 MINSYSDIV Type RO RO RO RO Reset 0 0 1 0 27 26 reserved RO RO 0 0 11 10 MAXADC1SPD RO RO 1 1 25 CAN1 RO 1 24 CAN0 RO 1 9 8 MAXADC0SPD RO RO 1 1 23 22 reserved RO RO 0 0 21 PWM1 RO 1 20 PWM0 RO 1 19 18 reserved RO RO 0 0 7 MPU RO 1 6 5 4 HIB TEMPSNS PLL RO RO RO 1 1 1 3 WDT0 RO 1 2 SWO RO 1 17 ADC1 RO 1 1 SWD RO 1 16 ADC0 RO 1 0 JTAG RO 1 Bit/Field 31:29 28 27:26 25 24 23:22 21 Name reserved WDT1 reserved CAN1 CAN0 reserved PWM1 Type RO RO RO RO RO RO RO Reset 0 0x1 0 0x1 0x1 0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer1 Present When set, indicates that watchdog timer 1 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 1 Present When set, indicates that CAN unit 1 is present. CAN Module 0 Present When set, indicates that CAN unit 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module 1 Present When set, indicates that the PWM module is present. June 12, 2014 427 Texas Instruments-Production Data System Control Bit/Field 20 19:18 17 16 15:12 11:10 9:8 7 Name PWM0 reserved ADC1 ADC0 MINSYSDIV MAXADC1SPD MAXADC0SPD MPU Type RO RO RO RO RO RO RO RO Reset 0x1 0 0x1 0x1 0x2 Description PWM Module 0 Present When set, indicates that the PWM module is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module 1 Present When set, indicates that ADC module 1 is present. ADC Module 0 Present When set, indicates that ADC module 0 is present System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x1 Reserved 0x2 Specifies an 80-MHz CPU clock with a PLL divider of 2.5. 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 0x4 Specifies a 40-MHz CPU clock with a PLL divider of 5. 0x7 Specifies a 25-MHz clock with a PLL divider of 8. 0x9 Specifies a 20-MHz clock with a PLL divider of 10. 0x3 Max ADC1 Speed This field indicates the maximum rate at which the ADC samples data. Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 0x3 Max ADC0 Speed This field indicates the maximum rate at which the ADC samples data. Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 0x1 MPU Present When set, indicates that the Cortex-M4F Memory Protection Unit (MPU) module is present. See the "Cortex-M4F Peripherals" chapter for details on the MPU. 428 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 6 5 4 3 2 1 0 Name HIB TEMPSNS PLL WDT0 SWO SWD JTAG Type RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description Hibernation Module Present When set, indicates that the Hibernation module is present. Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. Watchdog Timer 0 Present When set, indicates that watchdog timer 0 is present. SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. JTAG Present When set, indicates that the JTAG debugger interface is present. June 12, 2014 429 Texas Instruments-Production Data System Control Register 124: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC1, SCGC1, DCGC1, and the peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read of DC2 correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by the DCn registers. Note that the Analog Comparator Peripheral Present (PPACMP) register identifies whether the analog comparator module is present. The Analog Comparator Peripheral Properties (ACMPPP) register indicates how many analog comparator blocks are present in the module. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x030F.F337 31 30 29 28 reserved EPI0 reserved I2S0 Type RO RO RO RO Reset 0 0 0 0 27 26 25 24 reserved COMP2 COMP1 COMP0 RO RO RO RO 0 0 1 1 15 I2C1HS Type RO Reset 1 14 I2C1 RO 1 13 I2C0HS RO 1 12 I2C0 RO 1 11 10 reserved RO RO 0 0 9 QEI1 RO 1 8 QEI0 RO 1 23 22 21 reserved RO RO RO 0 0 0 7 6 reserved RO RO 0 0 5 SSI1 RO 1 20 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 RO RO RO RO RO 0 1 1 1 1 4 SSI0 RO 1 3 2 1 0 reserved UART2 UART1 UART0 RO RO RO RO 0 1 1 1 Bit/Field 31 30 29 28 27 26 25 Name reserved EPI0 reserved I2S0 reserved COMP2 COMP1 Type RO RO RO RO RO RO RO Reset 0 0x0 0 0x0 0 0x0 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. EPI Module 0 Present When set, indicates that EPI module 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2S Module 0 Present When set, indicates that I2S module 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 430 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 24 23:20 19 18 17 16 15 14 13 12 11:10 9 8 7:6 5 4 3 Name COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 I2C1HS I2C1 I2C0HS I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x1 0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0 0x1 0x1 0 0x1 0x1 0 Description Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer Module 3 Present When set, indicates that General-Purpose Timer module 3 is present. Timer Module 2 Present When set, indicates that General-Purpose Timer module 2 is present. Timer Module 1 Present When set, indicates that General-Purpose Timer module 1 is present. Timer Module 0 Present When set, indicates that General-Purpose Timer module 0 is present. I2C Module 1 Speed When set, indicates that I2C module 1 can operate in high-speed mode. I2C Module 1 Present When set, indicates that I2C module 1 is present. I2C Module 0 Speed When set, indicates that I2C module 0 can operate in high-speed mode. I2C Module 0 Present When set, indicates that I2C module 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI Module 1 Present When set, indicates that QEI module 1 is present. QEI Module 0 Present When set, indicates that QEI module 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Module 1 Present When set, indicates that SSI module 1 is present. SSI Module 0 Present When set, indicates that SSI module 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. June 12, 2014 431 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name UART2 UART1 UART0 Type RO RO RO Reset 0x1 0x1 0x1 Description UART Module 2 Present When set, indicates that UART module 2 is present. UART Module 1 Present When set, indicates that UART module 1 is present. UART Module 0 Present When set, indicates that UART module 0 is present. 432 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 125: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the feature is not present. Important: This register is provided for legacy software support only. For some modules, the peripheral-resident Peripheral Properties registers should be used to determine which pins are available on this microcontroller. A read of DC3 correctly identifies if a legacy pin is present but software must use the Peripheral Properties registers to determine if a pin is present that is not supported by the DCn registers. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBFFF.8FFF 31 30 29 28 32KHZ reserved CCP5 CCP4 Type RO RO RO RO Reset 1 0 1 1 27 CCP3 RO 1 26 CCP2 RO 1 25 CCP1 RO 1 24 23 22 21 20 19 18 17 16 CCP0 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 RO RO RO RO RO RO RO RO RO 1 1 1 1 1 1 1 1 1 15 14 PWMFAULT C2O Type RO RO Reset 1 0 13 12 11 C2PLUS C2MINUS C1O RO RO RO 0 0 1 10 9 8 C1PLUS C1MINUS C0O RO RO RO 1 1 1 7 6 5 C0PLUS C0MINUS PWM5 RO RO RO 1 1 1 4 PWM4 RO 1 3 PWM3 RO 1 2 PWM2 RO 1 1 PWM1 RO 1 0 PWM0 RO 1 Bit/Field 31 30 29 28 27 26 Name 32KHZ reserved CCP5 CCP4 CCP3 CCP2 Type RO RO RO RO RO RO Reset 0x1 0 0x1 0x1 0x1 0x1 Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. Note: The GPTMPP register does not provide this information. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. T2CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin T2CCP1 is present. Note: The GPTMPP register does not provide this information. T2CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin T2CCP0 is present. Note: The GPTMPP register does not provide this information. T1CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin T1CCP1 is present. Note: The GPTMPP register does not provide this information. T1CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin T1CCP0 is present. Note: The GPTMPP register does not provide this information. June 12, 2014 433 Texas Instruments-Production Data System Control Bit/Field 25 24 23 22 21 20 19 18 17 16 15 14 Name CCP1 CCP0 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 PWMFAULT C2O Type RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 Description T0CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin T0CCP1 is present. Note: The GPTMPP register does not provide this information. T0CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin T0CCP0 is present. Note: The GPTMPP register does not provide this information. ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. Note: The CH field in the ADCPP register provides this information. ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. Note: The CH field in the ADCPP register provides this information. PWM Fault Pin Present When set, indicates that a PWM Fault pin is present. See DC5 for specific Fault pins on this device. Note: The FCNT field in the PWMPP register provides this information. C2o Pin Present When set, indicates that the analog comparator 2 output pin is present. Note: The C2O bit in the ACMPPP register provides this information. 434 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 13 12 11 10 9 8 7 6 5 4 3 Name C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 Type RO RO RO RO RO RO RO RO RO RO RO Reset 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. Note: This pin is present when analog comparator 2 is present. C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. Note: This pin is present when analog comparator 2 is present. C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. Note: The C1O bit in the ACMPPP register provides this information. C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. Note: This pin is present when analog comparator 1 is present. C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. Note: This pin is present when analog comparator 1 is present. C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. Note: The C0O bit in the ACMPPP register provides this information. C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. Note: This pin is present when analog comparator 0 is present. C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. Note: This pin is present when analog comparator 0 is present. PWM5 Pin Present When set, indicates that the PWM pin 5 is present. Note: The GCNT field in the PWMPP register provides this information. PWM4 Pin Present When set, indicates that the PWM pin 4 is present. Note: The GCNT field in the PWMPP register provides this information. PWM3 Pin Present When set, indicates that the PWM pin 3 is present. Note: The GCNT field in the PWMPP register provides this information. June 12, 2014 435 Texas Instruments-Production Data System Control Bit/Field 2 1 0 Name PWM2 PWM1 PWM0 Type RO RO RO Reset 0x1 0x1 0x1 Description PWM2 Pin Present When set, indicates that the PWM pin 2 is present. Note: The GCNT field in the PWMPP register provides this information. PWM1 Pin Present When set, indicates that the PWM pin 1 is present. Note: The GCNT field in the PWMPP register provides this information. PWM0 Pin Present When set, indicates that the PWM pin 0 is present. Note: The GCNT field in the PWMPP register provides this information. 436 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 126: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC2, SCGC2, DCGC2, and the peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read of DC4 correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by the DCn registers. The peripheral-resident Peripheral Properties registers should be used to determine which pins and features are available on this microcontroller. A read of DC4 correctly identifies if a legacy pin or feature is present. Software must use the Peripheral Properties registers to determine if a pin or feature is present that is not supported by the DCn registers. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0004.F03F 31 30 29 28 reserved EPHY0 reserved EMAC0 Type RO RO RO RO Reset 0 0 0 0 15 CCP7 Type RO Reset 1 14 CCP6 RO 1 13 UDMA RO 1 12 ROM RO 1 27 26 25 reserved RO RO RO 0 0 0 11 10 9 reserved RO RO RO 0 0 0 24 23 E1588 RO RO 0 0 22 21 20 reserved RO RO RO 0 0 0 19 18 17 16 PICAL reserved RO RO RO RO 0 1 0 0 8 GPIOJ RO 0 7 GPIOH RO 0 6 GPIOG RO 0 5 GPIOF RO 1 4 GPIOE RO 1 3 GPIOD RO 1 2 GPIOC RO 1 1 GPIOB RO 1 0 GPIOA RO 1 Bit/Field 31 30 29 28 27:25 24 Name reserved EPHY0 reserved EMAC0 reserved E1588 Type RO RO RO RO RO RO Reset 0 0x0 0 0x0 0 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ethernet PHY Layer 0 Present When set, indicates that Ethernet PHY layer 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ethernet MAC Layer 0 Present When set, indicates that Ethernet MAC layer 0 is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1588 Capable When set, indicates that Ethernet MAC layer 0 is 1588 capable. June 12, 2014 437 Texas Instruments-Production Data System Control Bit/Field 23:19 18 17:16 15 14 13 12 11:9 8 7 6 5 4 3 2 1 Name reserved PICAL reserved CCP7 CCP6 UDMA ROM reserved GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0x1 0 0x1 0x1 0x1 0x1 0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PIOSC Calibrate When set, indicates that the PIOSC can be calibrated by software. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. T3CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin T3CCP1 is present. Note: The GPTMPP register does not provide this information. T3CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin T3CCP0 is present. Note: The GPTMPP register does not provide this information. Micro-DMA Module Present When set, indicates that the micro-DMA module present. Internal Code ROM Present When set, indicates that internal code ROM is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port J Present When set, indicates that GPIO Port J is present. GPIO Port H Present When set, indicates that GPIO Port H is present. GPIO Port G Present When set, indicates that GPIO Port G is present. GPIO Port F Present When set, indicates that GPIO Port F is present. GPIO Port E Present When set, indicates that GPIO Port E is present. GPIO Port D Present When set, indicates that GPIO Port D is present. GPIO Port C Present When set, indicates that GPIO Port C is present. GPIO Port B Present When set, indicates that GPIO Port B is present. 438 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 0 Name GPIOA Type RO Reset 0x1 Description GPIO Port A Present When set, indicates that GPIO Port A is present. June 12, 2014 439 Texas Instruments-Production Data System Control Register 127: Device Capabilities 5 (DC5), offset 0x020 This register is predefined by the part and can be used to verify PWM features. If any bit is clear in this register, the module is not present. Important: This register is provided for legacy software support only. The PWM Peripheral Properties (PWMPP) register should be used to determine what pins and features are available on PWM modules. A read of this register correctly identifies if a legacy pin or feature is present. Software must use the PWMPP register to determine if a pin or feature that is not supported by the DCn registers is present. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0130.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0 reserved PWMEFLT PWMESYNC reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field 31:28 27 26 25 24 23:22 21 20 19:8 Name reserved PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0 reserved PWMEFLT PWMESYNC reserved Type RO RO RO RO RO RO RO RO RO Reset 0 0x0 0x0 0x0 0x1 0 0x1 0x1 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Fault 3 Pin Present When set, indicates that the PWM Fault 3 pin is present. PWM Fault 2 Pin Present When set, indicates that the PWM Fault 2 pin is present. PWM Fault 1 Pin Present When set, indicates that the PWM Fault 1 pin is present. PWM Fault 0 Pin Present When set, indicates that the PWM Fault 0 pin is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Extended Fault Active When set, indicates that the PWM Extended Fault feature is active. PWM Extended SYNC Active When set, indicates that the PWM Extended SYNC feature is active. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 440 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 7 6 5 4 3 2 1 0 Name PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Type RO RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description PWM7 Pin Present When set, indicates that the PWM pin 7 is present. PWM6 Pin Present When set, indicates that the PWM pin 6 is present. PWM5 Pin Present When set, indicates that the PWM pin 5 is present. PWM4 Pin Present When set, indicates that the PWM pin 4 is present. PWM3 Pin Present When set, indicates that the PWM pin 3 is present. PWM2 Pin Present When set, indicates that the PWM pin 2 is present. PWM1 Pin Present When set, indicates that the PWM pin 1 is present. PWM0 Pin Present When set, indicates that the PWM pin 0 is present. June 12, 2014 441 Texas Instruments-Production Data System Control Register 128: Device Capabilities 6 (DC6), offset 0x024 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Important: This register is provided for legacy software support only. The USB Peripheral Properties (USBPP) register should be used to determine what features are available on the USB module. A read of this register correctly identifies if a legacy feature is present. Software must use the USBPP register to determine if a pin or feature that is not supported by the DCn registers is present. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0013 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USB0PHY reserved USB0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 Bit/Field 31:5 4 3:2 1:0 Name reserved USB0PHY reserved USB0 Type RO RO RO RO Reset 0 0x1 0 0x3 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module 0 PHY Present When set, indicates that the USB module 0 PHY is present. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module 0 Present This field indicates that USB module 0 is present and specifies its capability. sysValue Description 0x0 NA USB0 is not present. 0x1 DEVICE USB0 is Device Only. 0x2 HOST USB0 is Device or Host. 0x3 OTG USB0 is OTG. 442 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Register 129: Device Capabilities 7 (DC7), offset 0x028 This register is predefined by the part and can be used to verify μDMA channel features. A 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. Channels can have multiple assignments, see “Channel Assignments” on page 587 for more information. Important: This register is provided for legacy software support only. The DMACHANS bit field in the DMA Status (DMASTAT) register indicates the number of DMA channels. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field 31 30 29 28 27 26 25 24 23 22 Name reserved DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 Type RO RO RO RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description DMA Channel 31 When set, indicates μDMA channel 31 is available. DMA Channel 30 When set, indicates μDMA channel 30 is available. DMA Channel 29 When set, indicates μDMA channel 29 is available. DMA Channel 28 When set, indicates μDMA channel 28 is available. DMA Channel 27 When set, indicates μDMA channel 27 is available. DMA Channel 26 When set, indicates μDMA channel 26 is available. DMA Channel 25 When set, indicates μDMA channel 25 is available. DMA Channel 24 When set, indicates μDMA channel 24 is available. DMA Channel 23 When set, indicates μDMA channel 23 is available. DMA Channel 22 When set, indicates μDMA channel 22 is available. June 12, 2014 443 Texas Instruments-Production Data System Control Bit/Field 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Name DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description DMA Channel 21 When set, indicates μDMA channel 21 is available. DMA Channel 20 When set, indicates μDMA channel 20 is available. DMA Channel 19 When set, indicates μDMA channel 19 is available. DMA Channel 18 When set, indicates μDMA channel 18 is available. DMA Channel 17 When set, indicates μDMA channel 17 is available. DMA Channel 16 When set, indicates μDMA channel 16 is available. DMA Channel 15 When set, indicates μDMA channel 15 is available. DMA Channel 14 When set, indicates μDMA channel 14 is available. DMA Channel 13 When set, indicates μDMA channel 13 is available. DMA Channel 12 When set, indicates μDMA channel 12 is available. DMA Channel 11 When set, indicates μDMA channel 11 is available. DMA Channel 10 When set, indicates μDMA channel 10 is available. DMA Channel 9 When set, indicates μDMA channel 9 is available. DMA Channel 8 When set, indicates μDMA channel 8 is available. DMA Channel 7 When set, indicates μDMA channel 7 is available. DMA Channel 6 When set, indicates μDMA channel 6 is available. DMA Channel 5 When set, indicates μDMA channel 5 is available. DMA Channel 4 When set, indicates μDMA channel 4 is available. 444 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 3 2 1 0 Name DMACH3 DMACH2 DMACH1 DMACH0 Type RO RO RO RO Reset 0x1 0x1 0x1 0x1 Description DMA Channel 3 When set, indicates μDMA channel 3 is available. DMA Channel 2 When set, indicates μDMA channel 2 is available. DMA Channel 1 When set, indicates μDMA channel 1 is available. DMA Channel 0 When set, indicates μDMA channel 0 is available. June 12, 2014 445 Texas Instruments-Production Data System Control Register 130: Device Capabilities 8 (DC8), offset 0x02C This register is predefined by the part and can be used to verify features. Important: This register is provided for legacy software support only. The ADC Peripheral Properties (ADCPP) register should be used to determine how many input channels are available on the ADC module. A read of this register correctly identifies if legacy channels are present but software must use the ADCPP register to determine if a channel is present that is not supported by the DCn registers. Device Capabilities 8 (DC8) Base 0x400F.E000 Offset 0x02C Type RO, reset 0x0FFF.0FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field 31 30 29 28 27 26 25 24 23 22 Name ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 Type RO RO RO RO RO RO RO RO RO RO Reset 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 Description ADC Module 1 AIN15 Pin Present When set, indicates that ADC module 1 input pin 15 is present. ADC Module 1 AIN14 Pin Present When set, indicates that ADC module 1 input pin 14 is present. ADC Module 1 AIN13 Pin Present When set, indicates that ADC module 1 input pin 13 is present. ADC Module 1 AIN12 Pin Present When set, indicates that ADC module 1 input pin 12 is present. ADC Module 1 AIN11 Pin Present When set, indicates that ADC module 1 input pin 11 is present. ADC Module 1 AIN10 Pin Present When set, indicates that ADC module 1 input pin 10 is present. ADC Module 1 AIN9 Pin Present When set, indicates that ADC module 1 input pin 9 is present. ADC Module 1 AIN8 Pin Present When set, indicates that ADC module 1 input pin 8 is present. ADC Module 1 AIN7 Pin Present When set, indicates that ADC module 1 input pin 7 is present. ADC Module 1 AIN6 Pin Present When set, indicates that ADC module 1 input pin 6 is present. 446 June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C123GH6PM Microcontroller Bit/Field 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Name ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0 ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Description ADC Module 1 AIN5 Pin Present When set, indicates that ADC module 1 input pin 5 is present. ADC Module 1 AIN4 Pin Present When set, indicates that ADC module 1 input pin 4 is present. ADC Module 1 AIN3 Pin Present When set, indicates that ADC module 1 input pin 3 is present. ADC Module 1 AIN2 Pin Present When set, indicates that ADC module 1 input pin 2 is present. ADC Module 1 AIN1 Pin Present When set, indicates that ADC module 1 input pin 1 is present. ADC Module 1 AIN0 Pin Present When set, indicates that ADC module 1 input pin 0 is present. ADC Module 0 AIN15 Pin Present When set, indicates that ADC module 0 input pin 15 is present. ADC Module 0 AIN14 Pin Present When set, indicates that ADC module 0 input pin 14 is present. ADC Module 0 AIN13 Pin Present When set, indicates that ADC module 0 input pin 13 is present. ADC Module 0 AIN12 Pin Present When set, indicates that ADC module 0 input pin 12 is present. ADC Module 0 AIN11 Pin Present When set, indicates