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    FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 1 of 54 FOR gaoMyEaDnIg PABUS@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Overview The MT7620 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz radio and FEM, a 580 MHz MIPS® 24K™ CPU core, a 5-port 10/100 switch and two RGMII. The MT7620 includes everything needed to build an AP router from a single chip. The embedded high performance CPU can process advanced applications effortlessly, such as routing, security and VoIP. The MT7620 also includes a selection of interfaces to support a variety of applications, such as a USB port for accessing external storage. Applications:  Routers  NAS devices  iNICs  Dual band concurrent routers Features  Embedded MIPS24KEc (580 MHz) with 64 KB ICache and 32 KB D-Cache  2T2R 2.4 GHz with 300 Mbps PHY data rate  Legacy 802.11b/g and HT 802.11n modes  20/40 MHz channel bandwidth  Legacy 802.11b/g and HT 802.11n modes  Reverse Data Grant (RDG)  Maximal Ratio Combining (MRC)  Space Time Block Coding (STBC)  16-bit SDRAM up to 64 Mbytes  16-bit DDR1/2 up to 128/256 Mbytes  SPI, NAND Flash/SD-HC  1x USB 2.0, 1x PCIe host/device  5-port 10/100 SW and two RGMII  An optimized PMU  Green AP  Intelligent Clock Scaling (exclusive)  DDRII: ODT off, Self-refresh mode  SDRAM: Pre-charge power down  I2C, I2S, SPI, PCM, UART, JTAG, MDC, MDIO, GPIO  Hardware NAT with IPv6 and 2 Gbps wired speed  16 Multiple BSSID  WEP64/128, TKIP, AES, WPA, WPA2, WAPI  QoS: WMM, WMM-PS  WPS: PBC, PIN  Voice Enterprise: 802.11k+r  AP Firmware: Linux 2.6 SDK, eCOS with IPv6  RGMII iNIC Driver: Linux 2.4/2.6 Functional Block Diagram EJTAG 16-Bit SDR/DDR1/DDR2 MIPS 24KEc 64 KB I-Cache 32 KB D-Cache OCP_IF (580 MHz) OCP Bridge DRAM Controller Arbiter SDHC SD Single Port USB 2.0 PHY Host/Device RBUS (SYS_CLK) PBUS PCIe 1.1 PHY WLAN 11n 2x2 PCIe x1 2.4 GHz Switch (4FE + 2GE) GDMA 5-Port EPHY RGMII RJ45 x5 TMII/MII x2 To CPU interrupts INTC Timer SPI NFC UART GPIO I2C I2S PCM x4 SPI NAND UART GPIO /LED I2C I2S PCM Ordering Information Ralink Technology Corp. (USA) Suite 200 20833 Stevens Creek Blvd. Cupertino CA95014, U.S.A Tel: 408-725-8070 Fax: 408-725-8069 Ralink Technology Corp. (Taiwan) 5F, 5 Taiyuan 1st St Jhubei City, Hsinchu Taiwan, R.O.C Tel: 886-3-560-0868 Fax: 886-3-560 Part Package Number (Green/RoHS Compliant) MT7620A TFBGA 265 ball (11 mm x 11 mm) MT7620N DR-QFN 148 pin (12 mm x 12 mm) www.ralinktech.com DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 2 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table of Contents 1. MAIN FEATURES 2. PINS 2.1 TFBGA (11 MM X 11 MM) 265 BALL PACKAGE DIAGRAM 2.1.1 DDR1 BALL MAP 2.1.2 DDR2 BALL MAP 2.2 DR-QFN (12 MM X 12 MM) 148-PIN PACKAGE DIAGRAM 2.2.1 LEFT SIDE VIEW 2.2.2 RIGHT SIDE VIEW 2.3 PIN DESCRIPTIONS (TFBGA) 2.4 PIN DESCRIPTIONS (DRQFN) 2.5 PIN SHARING SCHEMES 2.5.1 GPIO PIN SHARE SCHEME 2.5.2 UARTF PIN SHARE SCHEME 2.5.3 RGMII PIN SHARE SCHEMES 2.5.4 WDT_RST_MODE PIN SHARE SCHEME 2.5.5 PERST_N PIN SHARE SCHEME 2.5.6 MDC/MDIO PIN SHARE SCHEME: 2.5.7 EPHY_LED PIN SHARE SCHEME 2.5.8 SPI PIN SHARE SCHEME 2.5.9 ND/SD PIN SHARE SCHEME 2.5.10 XMII PHY/MAC PIN MAPPING 2.6 BOOTSTRAPPING PINS DESCRIPTION 3. MAXIMUM RATINGS AND OPERATING CONDITIONS 3.3 ABSOLUTE MAXIMUM RATINGS 3.4 MAXIMUM TEMPERATURES 3.5 OPERATING CONDITIONS 3.6 THERMAL CHARACTERISTICS 3.7 STORAGE CONDITIONS 3.8 EXTERNAL XTAL SPECFICATION 3.9 DC ELECTRICAL CHARACTERISTICS 3.10 AC ELECTRICAL CHARACTERISTICS 3.10.1 SDRAM INTERFACE 3.10.2 DDR2 SDRAM INTERFACE 3.10.3 RGMII INTERFACE 3.10.4 MII INTERFACE (25 MHZ) 3.10.5 RVMII INTERFACE (PHY MODE MII TIMING) (25 MHZ) 3.10.6 SPI INTERFACE 3.10.7 I2S INTERFACE 3.10.8 PCM INTERFACE 3.10.9 POWER ON SEQUENCE 3.11 PACKAGE PHYSICAL DIMENSIONS 3.11.1 TFBGA (11 MM X 11 MM) 265 BALLS 3.11.2 DR-QFN (12 MM X 12 MM) 148LD 3.11.3 REFLOW PROFILE GUIDELINE 4. ABBREVIATIONS 5. REVISION HISTORY DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT 6 7 7 7 8 10 10 11 12 18 23 23 25 26 26 26 26 27 27 28 30 31 32 32 32 32 32 33 33 33 34 34 35 37 38 39 40 41 42 43 44 44 46 49 50 53 Page 3 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Table of Figures FIGURE 2-1 DR-QFN PIN DIAGRAM (LEFT VIEW) ............................................................................................................ 10 FIGURE 2-2 DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................................... 11 FIGURE 2-3 MII  MII PHY ..................................................................................................................................... 30 FIGURE 2-4 RVMII  MII MAC ................................................................................................................................ 30 FIGURE 2-5 RGMII  RGMII PHY............................................................................................................................. 30 FIGURE 2-6 RGMII RGMII MAC ........................................................................................................................... 30 FIGURE 3-1 SDRAM INTERFACE .................................................................................................................................. 34 FIGURE 3-2 DDR2 SDRAM COMMAND ....................................................................................................................... 35 FIGURE 3-3 DDR2 SDRAM WRITE DATA...................................................................................................................... 35 FIGURE 3-4 DDR2 SDRAM READ DATA ....................................................................................................................... 35 FIGURE 3-5 RGMII INTERFACE .................................................................................................................................... 37 FIGURE 3-6 MII INTERFACE......................................................................................................................................... 38 FIGURE 3-7 RVMII INTERFACE ..................................................................................................................................... 39 FIGURE 3-8 SPI INTERFACE ......................................................................................................................................... 40 FIGURE 3-9 I2S INTERFACE ......................................................................................................................................... 41 FIGURE 3-10 PCM INTERFACE..................................................................................................................................... 42 FIGURE 3-11 POWER ON SEQUENCE ............................................................................................................................ 43 FIGURE 3-12 TFBGA TOP VIEW .................................................................................................................................. 44 FIGURE 3-13 TFBGA SIDE VIEW.................................................................................................................................. 44 FIGURE 3-14 TFBGA “A” EXPANDED ........................................................................................................................... 44 FIGURE 3-15 TFBGA BOTTOM VIEW............................................................................................................................ 45 FIGURE 3-16 TFBGA “B” EXPANDED ........................................................................................................................... 45 FIGURE 3-17 DR-QFN TOP VIEW ................................................................................................................................ 46 FIGURE 3-18 DR-QFN SIDE VIEW ............................................................................................................................... 46 FIGURE 3-19 DR-QFN “B” EXPANDED ......................................................................................................................... 46 FIGURE 3-20 DR-QFN BOTTOM VIEW ......................................................................................................................... 47 FIGURE 3-21 DR-QFN “A” EXPANDED......................................................................................................................... 47 FIGURE 3-22 REFLOW PROFILE FOR MT7620 ................................................................................................................ 49 List of Tables TABLE 1-1 MAIN FEATURES........................................................................................................................................... 6 TABLE 2-1 DDR1 BALL MAP ......................................................................................................................................... 8 TABLE 2-2 DDR2 BALL MAP ......................................................................................................................................... 9 TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 32 TABLE 3-2 MAXIMUM TEMPERATURES.......................................................................................................................... 32 TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 32 TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 32 TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS.................................................................................................................... 33 TABLE 3-6 DC ELECTRICAL CHARACTERISTICS.................................................................................................................. 33 TABLE 3-7 SDRAM INTERFACE DIAGRAM KEY................................................................................................................ 34 TABLE 3-8 DDR2 SDRAM INTERFACE DIAGRAM KEY ...................................................................................................... 36 TABLE 3-9 RGMII INTERFACE DIAGRAM KEY.................................................................................................................. 37 TABLE 3-10 MII INTERFACE DIAGRAM KEY .................................................................................................................... 38 TABLE 3-11 RVMII INTERFACE DIAGRAM KEY ................................................................................................................ 39 TABLE 3-12 SPI INTERFACE DIAGRAM KEY ..................................................................................................................... 40 TABLE 3-13 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 41 TABLE 3-14 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 42 DSMT7620_V.1.3_091212 Page 4 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip TABLE 3-15 POWER ON SEQUENCE DIAGRAM KEY.......................................................................................................... 43 DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 5 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1. Main Features The following table covers the main features offered by the MT7620N and MT7620A. Overall, the MT7620N supports the requirements of an entry-level AP/router, while the more advanced MT7620A supports a number of interfaces together with a large maximum RAM capacity. Features CPU Total DMIPs I-Cache, D-Cache L2 Cache HNAT/HQoS Memory DRAM Controller SDRAM DDR1 DDR2 NAND SPI Flash SD RF PCIe USB 2.0 Switch I2S PCM I2C UART JTAG Package MT7620N MIPS24KEc (580 MHz) 580 x 1.6 DMIPs 64 KB, 32 KB n/a HNAT 16 b 512 Mb, 120 MHz 512 Mb, 193 MHz n/a n/a 3B addr mode (max 128Mbit) 4B addr mode (max 512Mbit) n/a 2T2R 802.11n 2.4 GHz n/a 1 5p FE SW n/a n/a 1 1 (Lite) 1 DRQFN148- 12 mm x 12 mm Table 1-1 Main Features MT7620A MIPS24KEc (580 MHz) 580 x 1.6 DMIPs 64 KB, 32 KB n/a HNAT 2 Gbps forwarding 16 b 512 Mb, 120 MHz 1 Gb, 193 MHz 2 Gb, 193 MHz Small page 512Byte (max 512M bit) Large page 2Kbyte (max 8G bit) 3B addr mode (max 128Mbit) 4B addr mode (max 512Mbit) SD-HC class 10 (32GB) 2T2R 802.11n 2.4 GHz 1 1 5p FE SW + RGMII(1) 4p FE SW + RGMII(2) 1 1 1 2 (Lite/Full) 1 TFBGA265- 11 mm x 11 mm DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 6 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2. Pins 2.1 TFBGA (11 mm x 11 mm) 265 Ball Package Diagram 2.1.1 DDR1 Ball Map 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 RF0 RF0 A _OUT _PA2 RF0_IN P _V33N BG XTAL_ _EXTR XI XTAL _XO BBPLL _V12 A SPI _MOSI PCIE_R XP PCIE _TXN APCK _RFCK OP FB DCDC _V33D UGAT E VFB _DDR VFB_DI G A RF0 B _PA1 _V33 RF0 _OUTN RF0_VX _LDO PLL_VC _CAP XTAL _V12A A SPI_ WP SP I PCIE_R _HOLD XN PCIE _TXP APCK _RFCK ON EXT DCDC EXT LGATE _LDO _V33 _LDO_ B _DDR A DIG C RF1_I N GND GND ADC_V X _LDO PORST _N SP I _CS0 SPI_MIS O SPI_CS 1 PCIE _REXT PCIE _RFCK P UPH Y0 _V12 D UPHY UPHY COMP 0 _VRE 0 _PAD UPHY0 _PADP C SM RF1 D _OUT GND P RF1_VX _LDO BG _V33A ANT _TRN WDT _RST_ N GPIO 0 SPI_CLK SOC_I O _V33D _0 PERST _N PCIE _RFCK N APC K _V12 A GE2 _RXCL K GE2 _RXD V GE1 _RXD V GE1 _RXCLK D RF1 E _OUT N RF1 _PA2 _V33 N RF1_P A1 _V33A SOC_ SOC_C ANT PA_PE PA_PE CO O APCK PCIE _TRNB _G0 _G1 _V12 _V12D _V12A _V33A D _1 _0 UPHY0 _V33A GE2 _RXD3 GE2 _RXD 1 GE1 _RXD 1 GE1 _RXD0 E F GND GND GND GND GND GND GND GND GE_IO _V33D GE2 _RXD2 GE2 _RXD 0 GE1 _RXD 3 GE1 _RXD2 F G SOC_I WLED_ O N _V33D GND GND GND _1 GND GND GND GND GE_IO _V33D GE2 _TXEN GE2 _TXC LK GE1 _TXE N GE1 _TXCLK G EPHY _LED H 3 _N _JTCL K EPHY _LED2 _N _JTMS EPHY _LED1 _N _JTDI EPHY _LED0 _N _JTDO DDR_I O _V25D GND GND GND GND GND GND GND GE2 _TXD2 GE2 _TXD 3 GE1 _TXD 1 GE1 _TXD0 H EPHY J MD1 5 MD14 MODT _LED4_ DDR_I N O GND _JTRST _V25D GND GND _N GND GND GND GND GE2 _TXD1 GE2 GE1 _TXD _TXD 03 GE1 _TXD2 J K MD1 3 MD12 MA5 DDR_I GND O GND GND GND _V25D SOC_C GND GND GND GND O _V12D MDC MDIO _3 K L MD1 1 MD10 MA4 DDR_I MA7 O GND GND GND _VREF GND GND GND GND SOC_C O _V12D _3 EPHY _V12A EPHY _V12 A L M MD9 MD8 MA6 DDR_I MA8 OC GND GND _V12D GND SOC_C SOC_I OO _V12D _V33D _2 _2 GND GND EPHY_ PLL _V12A MD I_RN_ P3 MDI _RP_ P3 MDI _TP_ P4 MDI _TN_P4 M DSMT7620_V.1.3_091212 Page 7 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 1 2 N MDQ S1 MDQM 1 P MCK _N MCK_P R MD0 MD1 T MD2 MD4 U MD3 MD5 1 2 3 MA9 MA11 MCKE MD6 MD7 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DDR_IO DDR_I C MA13 O _V12D _V25D SOC_C SOC_I OO _V12D _V33D _2 _2 GND EPH Y _V33 A EPHY _V33A MDI _TN_P 3 MDI_ TP _P3 MDI _RP_ P4 MDI _RN_P N 4 MA12 MA2 ND_CL DDR_I E/ ND_W MA1 O _V25 ND_CS_ N SD_CA RD P/ SD_W DSR_N RXD D _DETE P CT TXD2 MDI MDI MDI MDI _TP_P _TN_ _RP_ _RN_P P 2 P2 P2 2 MA3 MA0 MA10 MBA2 ND_RB _N/ SD_CLK ND_AL ND_RE E/ _N SD_C MD ND_W E _N TXD RTS_N RXD2 EPHY _RES _ VBG MDI _RP_ P1 MDI _RN_P 1 R MDQS0 MBA1 MCS_ N MCAS _N ND_D6/ BT_WA CT ND_D4 / BT_ST AT ND_D 2/ SD_D2 ND_D0 / SD_D0 DCD _N RIN I2C_S D MDI _RN_ P0 MDI _TP_ P1 MDI _TN_P1 T MDQM 0 MBA0 MRAS _N MWE _N ND_D7/ BT_ANT ND_D5 / BT_AU X ND_D 3/ SD_D3 ND_D1 / SD_D1 DTR _N CTS_N I2C_SC LK MDI _RP_ P0 MDI _TP_ P0 MDI _TN_P0 U 4 5 67 8 9 10 11 12 13 14 15 16 17 Table 2-1 DDR1 Ball Map 2.1.2 DDR2 Ball Map 26 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A RF0 RF0 _OUT _PA2 P _V33N RF0_I N BG_ EXTR XTAL_ XTAL BBPLL SPI XI _XO _V12A _MOSI PCIE _RXP PCIE _TXN APCK _RFCK OP FB DCDC _V33 D UGAT E VFB _DDR VFB _DIG A B RF0 _PA1 _V33 A RF0 _OUT N RF0_V X _LDO PLL _VC _CAP XTAL _V12A SPI_W SP I P _HOLD PCIE _RXN PCIE _TXP APCK _RFCK ON LGAT E EXT _LDO _DDR DCDC _V33 A EXT _LDO B _DIG C RF1_I N GND GND ADC_ VX_LD O PORS SPI_CS T _N 0 SPI _MISO SPI _CS1 UPH PCIE PCIE Y0 _REXT _RFCKP _V12 D UPHY COMP 0 _VRES UPHY 0 _PAD M UPHY 0 _PAD P C RF1 D _OUT P GND RF1_V X _LDO BG_ V33A AN T_TRN WDT _RST_ N GPIO0 SPI_CLK SOC_I O _V33D _0 PERST _N PCIE APCK _RFCK _V12 NA GE2 GE2 GE1 GE1 _RXCL _RXD _RXD _RXCL D KVVK E RF1 RF1 RF1 _OUT _PA2 _PA1 N _V33N _V33A ANT_ TRNB PA_PE _G0 PA_P E _G1 SOC_C O _V12D _1 SOC_CO _V12D_ 0 APCK _V12A PCIE _V33A UPHY0 _V33A GE2 _RXD 3 GE2 _RXD 1 GE1 _RXD 1 GE1 _RXD 0 E F GND GND GND GND GND GND GND GND GE_IO _V33D GE2 _RXD 2 GE2 _RXD 0 GE1 _RXD 3 GE1 _RXD 2 F G SOC_I WLED _N O _V33D GND GND _1 GND GND GND GND GND GE_IO _V33D GE2 _TXE N GE2 _TXCL K GE1 _TXE N GE1 _TXCL G K DSMT7620_V.1.3_091212 Page 8 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 26 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 H EPHY _LED 3 _N _JTCL K EPHY _LED2 _N _JTMS EPHY _LED1 _N_JT DI EPHY _LED0 _N _JTDO DDR_I O _V18D GND GND GND GND GND GND GND GE2 _TXD 2 GE2 GE1 _TXD3 _TXD1 GE1 _TXD 0 H EPHY _LED4 DDR_I J MD14 MD9 MODT _N O GND GND GND GND GND GND GND _JTRST _V18D _N GE2 _TXD 1 GE2 GE1 _TXD0 _TXD3 GE1 _TXD 2 J K MD12 MD11 MCS_ N GND DDR_I O GND _V18D GND GND GND GND SOC_C GND GND O _V12D MDC MDIO _3 K L MD10 MD13 MRAS _N MA0 DDR_I O GND _VREF GND GND GND GND GND SOC_C GND O _V12D _3 EPHY _V12 A EPHY _V12 A L M MD8 MD15 MCAS _N MA2 DDR _IOC GND _V12D GND GND SOC_C SOC O _IO _V12D _V33D GND _2 _2 EPHY MDI MDI_ MDI MDI GND _PLL _RN_ RP _TP_P _TN_ M _V12A P3 _P3 4 P4 N MDQ S1 MDQ M1 MA4 DDR _IOC _V12D DDR_I MA13 O _V18 D SOC_C SOC O _IO _V12D _V33D _2 _2 GND EPHY _V33 A EPHY _V33A MDI _TN_ P3 MDI _TP_P 3 MDI_ RP _P4 MDI _RN_ P4 N P MCK_ P MCK_ N MA6 ND_CL MA8 MA12 MA7 DDR _IO _V18D ND_CS_ N E/ SD _CARD _DETE ND_W P/ SD _WP DSR _N RXD MDI_ MDI MDI_ MDI TXD2 TP _TN_ RP _RN_ P _P2 P2 _P2 P2 CT R MD5 MD2 MA11 MA9 MA5 MA3 MBA2 ND_RB_ N/ SD_CLK ND_AL ND_RE E/ _N SD_CM D ND _WE _N EPHY MDI_ MDI TXD RTS_N RXD2 _RES RP _RN_ R _VBG _P1 P1 T MD0 MD6 MD4 MDQS0 MA1 MBA1 MWE _N ND_D6/ BT _WACT ND_D4 / BT_ST AT ND_D2 / SD_D2 ND _D0/ SD _D0 DCD _N RIN I2C_S D MDI _RN_ P0 MDI_ TP _P1 MDI _TN_ P1 T U MD7 MD1 MD3 MDQM 0 MA10 MBA0 MCKE ND_D7/ BT_ANT ND_D5 / BT_AU X ND_D3 / SD_D3 ND _D1/ SD _D1 DTR _N CTS_N I2C _SCLK MDI_ RP _P0 MDI _TP_P 0 MDI _TN_ P0 U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Table 2-2 DDR2 Ball Map DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 9 of 54 RF0_VXTS_LDOIEAOLNLY BG_EXTR BG_V33A PLL_VC_CAP PLL_VX_LD O XTAL_V12A XTAL_XI XTAL_X O ADC_VX _LDO NC BBPLL_V12A ANT_TRNB ANT_TR N PA_PE_G 1 PA_PE_G 0 WDT_RST_N SOC_CO_V12D_0 PORST_N GPIO0 DDRyE _MA6aDnIgA@TsEynKneCx.OcNoFmI.tDwENU DDR _MA7 VDD25 DDR _MA8 DDR _MA9 DDR _MA11 DDR _MA12 DDR_CKE DDR_ODT DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_IOC_V12D DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.2 DR-QFN (12 mm x 12 mm) 148-Pin Package Diagram 2.2.1 Left side view NC NC 74 73 72 71 70 69 68 67 66 NC 148 147 146 145 144 143 142 141 140 139 NC PLL S oC RF0_OUTP 75 RF0_PA2_V33N 1 RF0_OUTN 76 RF0_PA1_V33A 2 GND 77 RF RF1_VX_LDO 3 NC 78 RF1_OUTP 4 RF1_PA2_V33N 79 RF1_OUTN 5 RF1_PA1_V33A 80 SOC_IO_V33D_1 6 WLED_N 81 EPHY_LED3_N_JTCLK 7 EPHY_LED0_N_JTDO 82 EPHY_LED1_N_JTDI 8 LED EPHY_LED2_N_JTMS 83 EPHY_LED4_N_JTRST_N 9 SOC_CO_V12D_1 84 VDD18 VDD25 10 DDR_DQ14 DDR_DQ15 85 DDR_DQ9 DDR_DQ14 11 DDR_DQ12 DDR_DQ13 86 DDR_DQ11 DDR_DQ12 12 DDR_DQ10 DDR_DQ11 87 DDR_DQ13 DDR_DQ10 13 DRAM DDR_DQ8 DDR_DQ9 88 DDR_DQ15 DDR_DQ8 14 DDR_DQS1 DDR_DQS1 89 DDR_DQM1 DDR_DQM1 15 MCK_P MCK_N 90 MCK_N MCK_P 16 DDR_VREF DDR_VREF 91 DDR_ODT DDR_MA4 17 DDR_RAS_N DDR_MA5 92 DDR_IOC_V12D DDR_IOC_V12D 18 VDD18 VDD25 93 NC DRAM NC 94 95 96 97 98 99 100 101 102 NC NC 19 20 21 22 23 24 25 26 27 DDR_CS_N FOR gaoM DDR_ CAS_N VDD18 DDR_MA0 DDR_MA2 DDR_MA4 DDR_MA6 DDR_MA8 DDR_MA11 DDR_DQ5 DDR_DQ2 DDR_DQ0 DDR_DQ7 DDR_IOC_V12D DDR_DQ6 DDR_DQ1 DDR_DQ4 DDR_DQ3 DSMT7620_V.1.3_091212 Figure 2-1 DR-QFN Pin Diagram (left view) loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 10 of 54 SPI_WP wENUTSIEAOLNLY SPI_HOLD SPI_CS0 SPI_MISO SPI_MOSI SPI_CLK SPI_CS1 APCK_V12A APCK_V33A SOC_IO_V33D_0 DCDC_V33D LGATE UGATE COMP FB EXT_LDO_DDR VFB_DDR DCDC_V33A US B MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.2.2 Right side view 65 64 63 62 61 60 59 58 57 56 NC NC 138 137 136 135 134 133 132 131 NC SoC PCIE PMU 55 VFB_DIG 54 EXT_LDO_DIG 130 UPHY0_VRES 53 UPHY0_PADM 129 UPHY0_V33A EPHYeCx.OcNoFmI.tD 52 UPHY0_PADP 128 UPHY0_V12D 51 SOC_CO_V12D_3 127 MDI_TN_P4 50 MDI_TP_P4 126 MDI_RN_P4 49 MDI_RP_P4 125 MDI_RN_P3 48 MDI_RP_P3 124 MDI_TN_P3 47 MDI_TP_P3 123 EPHY_V12A 46 MDI_TN_P2 122 EPHY_V33A 45 MDI_TP_P2 121 MDI_RN_P2 44 MDI_RP_P2 120 EPHY_PLL_V12A 43 EPHY_RES_VBG 119 EPHY_V33A 42 MDI_RN_P1 118 MDI_RP_P1 41 MDI_TN_P1 117 EPHY_V33A 40 MDI_TP_P1 116 MDI_TN_P0 39 MDI_TP_P0 115 MDI_RN_P0 38 MDI_RP_P0 114 EPHY_V12A 37 RXD2 113 TXD2 DRAM NC 103 104 105 106 107 108 109 110 111 112 NC 28 29 30 31 32 33 34 35 36 NC NC DDR_DQS0yEaDnIgA@TsEynKn DDR_DQM0 DDR_MA3 VDD25 DDR_MA2 DDR_MA1 DDR_MA0 DDR_MA10 DDR_BA1 DDR_BA0 DDR_CS_N DDR_RAS_N DDR_CAS_N DDR_WE_N DDR_VREF SOC_CO_V12D I2C_SCLK I2C_SD SOC_IO_V33D_ 1 DDR_DQS0 FOR gaoM DDR_DQM0 DDR_MA9 VDD18 DDR_MA12 DDR_MA7 DDR_MA5 DDR_MA3 DDR_MA1 DDR_MA10 DDR_BA1 DDR_BA0 DDR_WE_N DDR_CKE DDR_VREF Figure 2-2 DR-QFN Pin Diagram (right side view) DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 11 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.3 Pin Descriptions (TFBGA) Pin Name WLAN LED G4 WLED_N UART Lite R14 RXD2 P13 TXD2 UART Full * P12 RXD T13 RIN U13 CTS_N P11 DSR_N T12 DCD_N R12 TXD U12 DTR_N R13 RTS_N SPI C8 SPI_MISO A8 SPI_MOSI B7 SPI_WP B8 SPI_HOLD D8 SPI_CLK C7 SPI_CS0 C9 SPI_CS1 I2C U14 I2C_SCLK T14 I2C_SD RGMII/MII (3.3 V)* D17 GE1_RXCLK D16 GE1_RXDV E17 GE1_RXD0 E16 GE1_RXD1 F17 GE1_RXD2 F16 GE1_RXD3 G17 GE1_TXCLK G16 GE1_TXEN H17 GE1_TXD0 H16 GE1_TXD1 J17 GE1_TXD2 J16 GE1_TXD3 D14 GE2_RXCLK D15 GE2_RXDV Type Driv. Description O, IPU 4 mA WLAN Activity LED I, IPU O, IPU 4 mA UART Lite RXD 4 mA UART Lite TXD I, IPD I, IPD I, IPD I, IPD I, IPD O, IPD O, IPD O, IPD 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA UART RXD. UART RIN. UART CTS_N. UART DSR_N. UART DCD_N. UART TXD. UART DTR. UART RTS. I/O, IPD I/O, IPD I/O, IPD I/O, IPD O, IPD O, IPU O, IPU 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA Master output/Slave input Master input/Slave output GOP function GOP function SPI clock SPI chip select0 SPI chip select1 I/O, IPU 4 mA I2C Clock O, IPU 4 mA I2C Data I/O 8 mA RGMII1 /GMII Rx Clock I 8 mA RGMII1 /GMII Rx Data Valid I 8 mA RGMII1 Rx Data bit #0/GMII Rx Data bit #0 I 8 mA RGMII1 Rx Data bit #1/GMII Rx Data bit #1 I 8 mA RGMII1 Rx Data bit #2/GMII Rx Data bit #2 I 8 mA RGMII1 Rx Data bit #3/GMII Rx Data bit #3 I/O 8 mA RGMII1 /GMII Tx Clock O 8 mA RGMII1 /GMII Tx Data Valid O 8 mA RGMII1 Tx Data bit #0/GMII Tx Data bit #0 O 8 mA RGMII1 Tx Data bit #1/GMII Tx Data bit #1 O 8 mA RGMII1 Tx Data bit #2/GMII Tx Data bit #2 O 8 mA RGMII1 Tx Data bit #3/GMII Tx Data bit #3 I/O 8 mA RGMII2 /GMII Rx Clock I 8 mA RGMII2 /GMII Rx Data Valid DSMT7620_V.1.3_091212 Page 12 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pin Name F15 GE2_RXD0 E15 GE2_RXD1 F14 GE2_RXD2 E14 GE2_RXD3 G15 GE2_TXCLK G14 GE2_TXEN J15 GE2_TXD0 J14 GE2_TXD1 H14 GE2_TXD2 H15 GE2_TXD3 PHY Management ( 3.3 V) K14 MDC K15 MDIO GPIO D7 GPIO0 5-Port PHY H4 EPHY_LED0 _N_JTDO H3 EPHY_LED1 _N_JTDI H2 EPHY_LED2 _N_JTMS H1 EPHY_LED3 _N_JTCLK J4 EPHY_LED4 _N_JTRST_N R15 EPHY_RES _VBG T15 MDI_RN_P0 U15 MDI_RP_P0 U17 MDI_TN_P0 U16 MDI_TP_P0 R17 MDI_RN_P1 R16 MDI_RP_P1 T17 MDI_TN_P1 T16 MDI_TP_P1 P17 MDI_RN_P2 P16 MDI_RP_P2 P15 MDI_TN_P2 P14 MDI_TP_P2 M14 MDI_RN_P3 M15 MDI_RP_P3 N14 MDI_TN_P3 Type I I I I I/O O O O O O Driv. 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA O 8 mA I/O 8 mA I/O, IPD 8 mA O, IPD 4 mA I/O, IPD 4 mA I/O, IPD 4 mA I/O, IPD 4 mA I/O, IPU 4 mA A I I O O I I O O I I O O I I O Description RGMII2 Rx Data bit #0/GMII Rx Data bit #0 RGMII2 Rx Data bit #1/GMII Rx Data bit #1 RGMII2 Rx Data bit #2/GMII Rx Data bit #2 RGMII2 Rx Data bit #3/GMII Rx Data bit #3 RGMII2 /GMII Tx Clock RGMII2 /GMII Tx Data Valid RGMII2 Tx Data bit #0/GMII Tx Data bit #0 RGMII2 Tx Data bit #1/GMII Tx Data bit #1 RGMII2 Tx Data bit #2/GMII Tx Data bit #2 RGMII2 Tx Data bit #3/GMII Tx Data bit #3 PHY Management Clock. Shared with GPIO23 PHY Management Data. Shared with GPIO22 GPO0 (output only) 10/100 PHY Port #0 activity LED, JTAG_TDO 10/100 PHY Port #1 activity LED, JTAG_TDI 10/100 PHY Port #2 activity LED, JTAG_TMS 10/100 PHY Port #3 activity LED, JTAG_CLK 10/100 PHY Port #4 activity LED, JTAG_TRST_N Connect to an external resistor to provide accurate bias current 10/100 PHY Port #0 RXN 10/100 PHY Port #0 RXP 10/100 PHY Port #0 TXN 10/100 PHY Port #0 TXP 10/100 PHY Port #1 RXN 10/100 PHY Port #1 RXP 10/100 PHY Port #1 TXN 10/100 PHY Port #1 TXP 10/100 PHY Port #2 RXN 10/100 PHY Port #2 RXP 10/100 PHY Port #2 TXN 10/100 PHY Port #2 TXP 10/100 PHY Port #3 RXN 10/100 PHY Port #3 RXP 10/100 PHY Port #3 TXN DSMT7620_V.1.3_091212 Page 13 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pin N15 N17 N16 M17 M16 NAND Flash* P8 R9 R11 P10 P9 R10 T11 U11 T10 U10 T9 U9 T8 U8 R8 Misc. C6 E5 Name MDI_TP_P3 MDI_RN_P4 MDI_RP_P4 MDI_TN_P4 MDI_TP_P4 ND_CS_N ND_RE_N ND_WE_N ND_WP ND_CLE ND_ALE ND_D0 ND_D1 ND_D2 ND_D3 ND_D4 ND_D5 ND_D6 ND_D7 ND_RB_N PORST_N PA_PE_G0 E6 PA_PE_G1 D5 E4 D6 USB PHY E13 C12 C15 ANT_TRN ANT_TRNB WDT_RST_N UPHY0_V33A UPHY0_V12D UPHY0_VRES C16 C17 DDR2 M2 J1 L2 K1 K2 UPHY0_PADM UPHY0_PADP MD15 MD14 MD13 MD12 MD11 Type O I I O O Driv. Description 10/100 PHY Port #3 TXP 10/100 PHY Port #4 RXN 10/100 PHY Port #4 RXP 10/100 PHY Port #4 TXN 10/100 PHY Port #4 TXP O, IPD O, IPD O, IPD O, IPD O, IPD O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPD I, IPD 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA NAND Flash Chip Select NAND Flash Read Enable NAND Flash Write Enable NAND Flash Write Protect NAND Flash Command Latch Enable NAND Flash ALE Latch Enable NAND Flash Data0 NAND Flash Data1 NAND Flash Data2 NAND Flash Data3 NAND Flash Data4 NAND Flash Data5 NAND Flash Data6 NAND Flash Data7 NAND Flash Ready/Busy I, IPU O, I PD O, IPD O, IPD O, IPD O, IPU 4 mA 16 mA 16 mA 8 mA 8 mA 4 mA Power on reset 0 V to 3.3 V control for external PA0 0 V to 3.3 V control for external PA1 Positive signal for antenna T/R switch Negative signal for antenna T/R switch Watchdog Reset P 3.3 V USB PHY analog power supply P 1.2 V USB PHY digital power supply I/O Connect to an external 8.2 kΩ resistor for band-gap reference circuit I/O USB Port0 data pin Data- I/O USB Port0 data pin Data+ I/O 8 mA DDR2 Data bit #15 I/O 8 mA DDR2 Data bit #14 I/O 8 mA DDR2 Data bit #13 I/O 8 mA DDR2 Data bit #12 I/O 8 mA DDR2 Data bit #11 DSMT7620_V.1.3_091212 Page 14 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pin L1 J2 M1 U1 T2 R1 T3 U3 R2 U2 T1 N5 P5 R3 U5 R4 P4 P6 P3 R5 N3 R6 M4 T5 L4 R7 T6 U6 L3 M3 T7 P1 P2 N2 U4 K3 N1 T4 U7 J3 PMU Name MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MBA2 MBA1 MBA0 MRAS_N MCAS_N MWE_N MCK_P MCK_N MDQM1 MDQM0 MCS_N MDQS1 MDQS0 MCKE ODT Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O O, IPD O Driv. 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Description DDR2 Data bit #10 DDR2 Data bit #9 DDR2 Data bit #8 DDR2 Data bit #7 DDR2 Data bit #6 DDR2 Data bit #5 DDR2 Data bit #4 DDR2 Data bit #3 DDR2 Data bit #2 DDR2 Data bit #1 DDR2 Data bit #0 DDR2 Address bit #13 DDR2 Address bit #12 DDR2 Address bit #11 DDR2 Address bit #10 DDR2 Address bit #9 DDR2 Address bit #8 DDR2 Address bit #7 DDR2 Address bit #6 DDR2 Address bit #5 DDR2 Address bit #4 DDR2 Address bit #3 DDR2 Address bit #2 DDR2 Address bit #1 DDR2 Address bit #0 DDR2 MBA #2 DDR2 MBA #1 DDR2 MBA #0 DDR2 MRAS_N DDR2 MCAS_N DDR2 MWE_N DDR2 MCK_P DDR2 MCK_N DDR2 MDM#1 DDR2 MDM#0 DDR2 MCS_N DDR2 MDQS#1 DDR2 MDQS#0 DDR2 MCKE DDR2 ODT DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 15 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pin A13 Name FB C14 COMP A15 UGATE B14 LGATE A14 DCDC_V33D B16 B17 A17 B15 A16 PCIe* D10 A10 B10 B9 A9 C10 DCDC_V33A EXT_LDO_DIG VFB_DIG EXT_LDO_DDR VFB_DDR PERST_N PCIE_TXN PCIE_TXP PCIE_RXN PCIE_RXP PCIE_REXT PCIe Reference Clock Generator A11 APCK_RFCKOP B11 APCK_RFCKON E10 PCIE_V33A C11 PCIE_RFCKP D11 PCIE_RFCKN PLL E9, D12 APCK_V12A A7 BBPLL_V12A B6 Power D9, G5, SOC_IO_V33D M10, N10 E7, E8, L13, SOC_CO_V12D M9, N9, K13 L5 DDR_IO_VREF Type Driv. A A A A P P A A A A I/O, IPU A A A A A 4 mA A A P A A P P P P P Description This pin is part of the error amplifier and provides the reference voltage which the sampled output voltage is compared to. A difference between these two voltages indicates an error in the output voltage. This pin provides the error amplifier output which compensates for errors in the output voltage identified using the FB pin. Gate drive for external upper MOSFET (Ipeak<200 mA; Iavg<20 mA) Gate drive for external lower MOSFET (Ipeak<200 mA; Iavg<20 mA) 3.3 V power supply only for gate driver of SW (Ipeak<200 mA; Iavg<20 mA) 3.3 V analog power (Ipeak<200 mA; Iavg<10 mA) Connect to Base terminal of external BJT (Iavg<20 mA) 1.2 V output feedback Connect to Base terminal of external BJT (Iavg<20 mA) DDR output feedback PICe reset. PCIe0 differential transmit TX PCIe0 differential transmit TX+ PCIe0 differential receive RX PCIe0 differential receive RX + PCIe0 Reference resistor connection (191 Ohm +/- 1 %) External reference clock output (positive) External reference clock output (negative) PCIe 3.3 V analog power Device reference clock input (positive) Device reference clock input (negative) 1.2 V analog power supply for CPLL/PPLL 1.2 V analog power supply to BB PLL NC 3.3 V digital I/O power supply 1.2 V digital core power supply 0.9 V/1.25 V/GND reference voltage power supply for DDR2/DDR1/SDR DSMT7620_V.1.3_091212 Page 16 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pin Name Type Driv. Description H5, N6, J5, DDR_IO_V18D/ P K5, P7 DDR_IO_V25D 1.8 V/2.5 V/3.3 V level shifter power supply for DDR2/DDR1/SDR M5, N4 DDR_IOC_V12D P 1.2 V I/O core power supply for DDR and SDR N12, N13 EPHY_V33A P 3.3 V power supply for EPHY L14, L15 EPHY_V12A P 1.2 V power supply for EPHY F13, G13 GE_IO_V33D P 3.3 V power supply for RGMII M13 EPHY_PLL_V12A P 1.2 V power supply for EPHY PLL RF A1 RF0_OUTP O 2.4 GHz TX0 PA output (positive) B2 RF0_OUTN O 2.4 GHz TX0 PA output (negative) B1 RF0_PA1 _V33A P 3.3 V Supply for RF channel0 A2 RF0_PA2 _V33N P 3.3 V Supply for RF channel0 A3 RF0_IN I 2.4 GHz RX0 input B3 RF0_VX_LDO P 1.2 V to 3.3 V supply for RF0 D1 RF1_OUTP O 2.4 GHz TX1 PA output (positive) E1 RF1_OUTN O 2.4 GHz TX1 PA output (negative) E3 RF1_PA1 _V33A P 3.3 V Supply for RF channel1 E2 RF1_PA2 _V33N P 3.3 V Supply for RF channel1 C1 RF1_IN I 2.4 GHz RX1 input D3 RF1_VX_LDO P 1.2 V to 3.3 V supply for RF1 D4 BG_V33A P 3.3 V supply for band gap reference A4 BG_EXTR I/O External reference resistor (24 kΩ) B4 PLL_VC_CAP I/O PLL external loop filter C4 GND G Ground ball C5 ADC_VX_LDO P 1.2 V to 3.3 V Supply for ADC A5 XTAL_XI I Crystal oscillator input A6 XTAL_XO O Crystal oscillator output B5 XTAL_V12A O Crystal LDO output Ground C2, D2, F2, K4, GND G F6 to F12, G6 to G12, H6 to H12, J6 to J12, K6 to K12, L6 to L12, M6 to M8, M11, M12, N11 Ground ball Total: 265 balls NOTE: 1. Pin types marked with an * indicate that they are available only in the TFBGA package. 2. Ball mapping for these pins is shown in the DDR2 Ball Map table in section 2.3.1. For information on DDR1 ball mapping, see section 2.3.2. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 17 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.4 Pin Descriptions (DRQFN) Pins Name WLAN LED 81 WLED_N UART Lite 37 RXD2 113 TXD2 SPI 137 SPI_MISO 63 SPI_MOSI 65 SPI_WP 138 SPI_HOLD 136 SPI_CLK 64 SPI_CS0 62 SPI_CS1 I2C 111 I2C_SCLK 36 I2C_SD GPIO 139 GPIO0 5-Port PHY 82 EPHY_LED0 _N_JTDO 8 EPHY_LED1 _N_JTDI 83 EPHY_LED2 _N_JTMS 7 EPHY_LED3 _N_JTCLK 9 EPHY_LED4 _N_JTRST_N 43 EPHY_RES _VBG Type O, IPU I, IPU O, IPU I/O, IPD I/O, IPD I/O, IPD I/O, IPD O, IPD O, IPU O, IPU I/O, IPU O, IPU I/O, IPD O, IPD I/O, IPD I/O, IPD I/O, IPD I/O, IPU A Driv. 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 115 MDI_RN_P0 I 38 MDI_RP_P0 I 116 MDI_TN_P0 O 39 MDI_TP_P0 O 42 MDI_RN_P1 I 118 MDI_RP_P1 I 41 MDI_TN_P1 O Description WLAN Activity LED UART Lite RXD UART Lite TXD Master output/Slave input Master input/Slave output GPO function GPO function SPI clock SPI chip select0 SPI chip select1 I2C Clock I2C Data GPO0 (output only) 10/100 PHY Port #0 activity LED, JTAG_TDO 10/100 PHY Port #1 activity LED, JTAG_TDI 10/100 PHY Port #2 activity LED, JTAG_TMS 10/100 PHY Port #3 activity LED, JTAG_CLK 10/100 PHY Port #4 activity LED, JTAG_TRST_N Connect to an external resistor to provide accurate bias current 10/100 PHY Port #0 RXN 10/100 PHY Port #0 RXP 10/100 PHY Port #0 TXN 10/100 PHY Port #0 TXP 10/100 PHY Port #1 RXN 10/100 PHY Port #1 RXP 10/100 PHY Port #1 TXN DSMT7620_V.1.3_091212 Page 18 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pins Name 40 MDI_TP_P1 121 MDI_RN_P2 44 MDI_RP_P2 46 MDI_TN_P2 45 MDI_TP_P2 125 MDI_RN_P3 48 MDI_RP_P3 124 MDI_TN_P3 47 MDI_TP_P3 126 MDI_RN_P4 49 MDI_RP_P4 127 MDI_TN_P4 50 MDI_TP_P4 Misc. 66 PORST_N 141 PA_PE_G0 68 PA_PE_G1 142 ANT_TRN 69 ANT_TRNB 67 WDT_RST_N USB PHY 129 UPHY0 _V33A 128 UPHY0 _V12D 130 UPHY0 _VRES Type O I I O O I I O O I I O O I, IPU O, IPD O, IPD O, IPD O, IPD O, IPU P P I/O 53 UPHY0 _PADM I/O 52 UPHY0 _PADP I/O DDR1/SDR 85 MD15 I/O 11 MD14 I/O 86 MD13 I/O 12 MD12 I/O 87 MD11 I/O 13 MD10 I/O 88 MD9 I/O 14 MD8 I/O 27 MD7 I/O 102 MD6 I/O 26 MD5 I/O Driv. Description 10/100 PHY Port #1 TXP 10/100 PHY Port #2 RXN 10/100 PHY Port #2 RXP 10/100 PHY Port #2 TXN 10/100 PHY Port #2 TXP 10/100 PHY Port #3 RXN 10/100 PHY Port #3 RXP 10/100 PHY Port #3 TXN 10/100 PHY Port #3 TXP 10/100 PHY Port #4 RXN 10/100 PHY Port #4 RXP 10/100 PHY Port #4 TXN 10/100 PHY Port #4 TXP 4 mA 16 mA 16 mA 8 mA 8 mA 4 mA Power on reset 0 V to 3.3 V control for external PA0 0 V to 3.3 V control for external PA1 Positive signal for antenna T/R switch Negative signal for antenna T/R switch Watchdog Reset 3.3 V USB PHY analog power supply 1.2 V USB PHY digital power supply Connect to an external 8.2 kΩ resistor for band-gap reference circuit USB Port0 data pin DataUSB Port0 data pin Data+ 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA SDRAM/DDR Data bit #15 SDRAM/DDR Data bit #14 SDRAM/DDR Data bit #13 SDRAM/DDR Data bit #12 SDRAM/DDR Data bit #11 SDRAM/DDR Data bit #10 SDRAM/DDR Data bit #9 SDRAM/DDR Data bit #8 SDRAM/DDR Data bit #7 SDRAM/DDR Data bit #6 SDRAM/DDR Data bit #5 DSMT7620_V.1.3_091212 Page 19 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pins 101 100 24 99 23 97 21 31 96 20 19 94 92 17 104 105 30 106 107 32 33 109 34 16 90 15 28 108 89 103 22 98 PMU 58 Name MD4 MD3 MD2 MD1 MD0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MBA1 MBA0 MRAS_N MCAS_N MWE_N MCK_P MCK_N MDQM1 MDQM0 MCS_N MDQS1 MDQS0 MCKE ODT FB 132 COMP Type I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O O, IPD O Driv. 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Description SDRAM/DDR Data bit #4 SDRAM/DDR Data bit #3 SDRAM/DDR Data bit #2 SDRAM/DDR Data bit #1 SDRAM/DDR Data bit #0 SDRAM/DDR Address bit #12 SDRAM/DDR Address bit #11 SDRAM/DDR Address bit #10 SDRAM/DDR Address bit #9 SDRAM/DDR Address bit #8 SDRAM/DDR Address bit #7 SDRAM/DDR Address bit #6 SDRAM/DDR Address bit #5 SDRAM/DDR Address bit #4 SDRAM/DDR Address bit #3 SDRAM/DDR Address bit #2 SDRAM/DDR Address bit #1 SDRAM/DDR Address bit #0 SDRAM/DDR MBA #1 SDRAM/DDR MBA #0 SDRAM/DDR MRAS_N SDRAM/DDR MCAS_N SDRAM/DDR MWE_N SDRAM MCK/DDR MCK_P DDR MCK_N SDRAM MDQM#1/DDR MDM#1 SDRAM MDQM#0/DDR MDM#0 SDRAM/DDR MCS_N DDR MDQS#1 DDR MDQS#0 DDR MCKE DDR2 ODT A This pin is part of the error amplifier and provides the reference voltage which the sampled output voltage is compared to. A difference between these two voltages indicates an error in the output voltage. A This pin provides the error amplifier output which compensates for errors in the output voltage identified using the FB pin. DSMT7620_V.1.3_091212 Page 20 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pins Name Type 59 UGATE A 133 LGATE A 60 DCDC _V33D P 56 DCDC _V33A P 54 EXT_LDO _DIG A 55 VFB_DIG A 131 EXT_LDO _DDR A 57 VFB_DDR A PLL 61 APCK_V33A P 135 APCK_V12A P 143 BBPLL_V12A P 70 Power 134, 6, SOC_IO _V33D P 112 84, 35, SOC_CO _V12D P 140, 51 91, 110 DDR_VREF P 10, 93, VDD18/ VDD25 P 95, 29 18, 25 DDR_IOC P _V12D 122, EPHY_V33A P 119, 117 123, EPHY_V12A P 114 RF 75 RF0_OUTP I/O 76 RF0_OUTN I/O 2 RF0_PA1 _V33A P 1 RF0_PA2 _V33N P 148 RF0_VX_LDO P Driv. Description Gate drive for external upper MOSFET (Ipeak<200 mA; Iavg<20 mA) Gate drive for external lower MOSFET (Ipeak<200mA; Iavg<20mA) 3.3 V power supply only for gate driver of SW (Ipeak<200 mA; Iavg<20 mA) 3.3 V analog power (Ipeak<200 mA; Iavg<10 mA) Connects to the base terminal of external BJT (Iavg<20 mA) 1.2 V output feedback Connect to Base terminal of external BJT (Iavg<20 mA) DDR output feedback 3.3 V analog power supply for CPLL/PPLL 1.2 V analog power supply for CPLL/PPLL 1.2 V analog power supply to BB PLL NC 3.3 V digital I/O power supply 1.2 V digital core power supply 0.9 V/1.25 V/GND reference voltage power supply for DDR2/DDR1/SDR 1.8 V/2.5 V/3.3 V level shifter power supply for DDR2/DDR1/SDR 1.2 V I/O core power supply for DDR and SDR 3.3 V power supply for EPHY 1.2 V power supply for EPHY 2.4 GHz TX0 PA output 2.4 GHz RX0 LNA input (positive) 2.4 GHz TX0 PA output 2.4 GHz RX0 LNA input (negative) 3.3 V Supply for RF channel0 3.3 V Supply for RF channel0 1.2 V to 3.3 V Supply for RF0 DSMT7620_V.1.3_091212 Page 21 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Pins Name Type 4 RF1_OUTP I/O 5 RF1_OUTN I/O 80 RF1_PA1 _V33A P 79 RF1_PA2 _V33N P 3 RF1_VX_LDO P 147 BG_V33A P 74 BG_EXTR I/O 73 PLL_VC_CAP I/O 146 PLL_VX_LDO P 144 ADC_VX_LDO P 145 XTAL_XI I 71 XTAL_XO O 72 XTAL_V12A O 77, 78 NC Ground EPAD GND G Total: 148 pins NOTE: IPD : Internal pull-down IPU : Internal pull-up I : Input O : Output IO : Bi-directional P : Power G : Ground NC : Not connected Driv. Description 2.4 GHz TX1 PA output 2.4 GHz RX1 LNA input (positive) 2.4 GHz TX1 PA output 2.4 GHz RX1 LNA input (negative) 3.3 V Supply for RF channel1 3.3 V Supply for RF channel1 1.2 V to 3.3 V Supply for RF1 3.3 V supply for band gap reference External reference resistor (24 kΩ) PLL external loop filter 1.2 V to 3.3 V Supply for PLL 1.2 V to 3.3 V Supply for ADC Crystal oscillator input Crystal oscillator output Crystal LDO output NC Ground pin DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 22 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5 Pin Sharing Schemes Some pins are shared with GPIO to provide maximum flexibility for system designers. The MT7620 provides up to 73 GPIO pins. Users can configure SYSCFG and GPIOMODE registers in the System Control block to specify the pin function, or they can use the registers specified below. For more information, see the Programmer’s Guide. Unless specified explicitly, all the GPIO pins are in input mode after reset. 2.5.1 GPIO pin share scheme I/O Pad Group WLED_N RGMII2 NAND SW_PHY_LED/JTAG Normal Mode WLAN_LED_N GE2_RXCLK GE2_RXDV GE2_RXD3 GE2_RXD2 GE2_RXD1 GE2_RXD0 GE2_TXCLK GE2_TXEN GE2_TXD3 GE2_TXD2 GE2_TXD1 GE2_TXD0 ND_D7 ND_D6 ND_D5 ND_D4 ND_D3 ND_D2 ND_D1 ND_D0 ND_ALE ND_CLE ND_RB_N ND_WP ND_RE_N ND_WE_N ND_CS_N EPHY_LED4_N_JTRST_N EPHY_LED3_N_JTCLK EPHY_LED2_N_JTMS EPHY_LED1_N_JTDI GPIO Mode GPO#72 GPIO#71 GPIO#70 GPIO#69 GPIO#68 GPIO#67 GPIO#66 GPIO#65 GPIO#64 GPIO#63 GPIO#62 GPIO#61 GPIO#60 GPIO#59 GPIO#58 GPIO#57 GPIO#56 GPIO#55 GPIO#54 GPIO#53 GPIO#52 GPIO#51 GPIO#50 GPIO#49 GPIO#48 GPIO#47 GPIO#46 GPIO#45 GPIO#44 GPIO#43 GPIO#42 GPIO#41 DSMT7620_V.1.3_091212 Page 23 of 54 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip I/O Pad Group SPI PERST_N RGMII1 MDIO PA_PE WDT_RST UARTL UARTF SPI I2C/SUTIF DSMT7620_V.1.3_091212 Normal Mode EPHY_LED0_N_JTDO SPI_WP SPI_HOLD SPI_CS1 PERST_N GE1_RXCLK GE1_RXDV GE1_RXD3 GE1_RXD2 GE1_RXD1 GE1_RXD0 GE1_TXCLK GE1_TXEN GE1_TXD3 GE1_TXD2 GE1_TXD1 GE1_TXD0 MDC MDIO PA_PE_G1 PA_PE_G0 ANT_TRN ANT_TRNB WDT_RST_N RXD2 TXD2 RIN DSR_N DCD_N DTR_N RXD CTS_N TXD RTS_N SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 I2C_SCLK loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT GPIO Mode GPIO#40 GPO#39 GPO#38 GPIO#37 GPIO#36 GPIO#35 GPIO#34 GPIO#33 GPIO#32 GPIO#31 GPIO#30 GPIO#29 GPIO#28 GPIO#27 GPIO#26 GPIO#25 GPIO#24 GPIO#23 GPIO#22 GPIO#21 GPIO#20 GPO#19 GPO#18 GPIO#17 GPIO#16 GPO#15 GPIO#14 GPIO#13 GPIO#12 GPIO#11 GPIO#10 GPIO#9 GPIO#8 GPIO#7 GPIO#6 GPO#5 GPO#4 GPIO#3 GPIO#2 Page 24 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip I/O Pad Group GPIO Normal Mode I2C_SD GPO0 GPIO Mode GPIO#1 GPO#0 2.5.2 UARTF pin share scheme Controlled by the UARTF_SHARE_MODE register. Pin Name 3’b000 UARTF 3’b001 PCM, UARTF 3’b010 PCM, I2S 3’b011 I2S UARTF RIN RIN PCMDTX PCMDTX RXD DSR_N DSR_N PCMDRX PCMDRX CTS_N DCD_N DCD_N PCMCLK PCMCLK TXD DTR_N DTR_N PCMFS PCMFS RTS_N RXD RXD RXD I2SSDI I2SSDI CTS_N CTS_N CTS_N I2SSDO I2SSDO TXD TXD TXD I2SWS I2SWS RTS_N RTS_N RTS_N I2SCLK I2SCLK 3’b100 PCM, GPIO PCMDTX PCMDRX PCMCLK PCMFS GPIO#10 GPIO#9 GPIO#8 GPIO#7 3’b101 GPIO, UARTF GPIO#14 GPIO#13 GPIO#12 GPIO#11 RXD CTS_N TXD RTS_N 3’b110 GPIO I2S GPIO#14 GPIO#13 GPIO#12 GPIO#11 I2SSDI I2SSDO I2SWS I2SCLK 3’b111 GPIO GPIO#14 GPIO#13 GPIO#12 GPIO#11 GPIO#10 GPIO#9 GPIO#8 GPIO#7 NOTE: This scheme applies only to the TFBGA package. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 25 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.3 RGMII pin share schemes Controlled by the RGMII1_GPIO_MODE register. Pin Name 1’b0 RGMII1 1’b1 GPIO GE1_RXCLK GE1_RXCLK GPIO#35 GE1_RXDV GE1_RXDV GPIO#34 GE1_RXD 0 to 3 GE1_RXD 0 to 3 GPIO#33 to 30 GE1_TXCLK GE1_TXCLK GPIO#29 GE1_TXDV GE1_TXDV GPIO#28 GE1_TXD0 to 3 GE1_TXD0 to 3 GPIO#27 to 24 NOTE: This scheme applies only to the TFBGA package. Controlled by the RGMII2_GPIO_MODE register. Pin Name 1’b0 RGMII2 1’b1 GPIO GE2_RXCLK GE2_RXCLK GPIO#71 GE2_RXDV GE2_RXDV GPIO#70 GE2_RXD0 to 3 GE2_RXD0 to 3 GPIO#69 to 66 GE2_TXCLK GE2_TXCLK GPIO#65 GE2_TXDV GE2_TXDV GPIO#64 GE2_TXD0 to 3 GE2_TXD0 to 3 GPIO#63 to 60 NOTE: This scheme applies only to the TFBGA package. 2.5.4 WDT_RST_MODE pin share scheme Controlled by the WDT_RST _MODE register. Pin Name 2’b00 WDT_RST_N WDT_RST_N 2.5.5 PERST_N pin share scheme Controlled by the PERST_GPIO_MODE register. Pin Name 2’b00 PERST_N PERST_N NOTE: This scheme applies only to the TFBGA package. 2.5.6 MDC/MDIO pin share scheme: Controlled by the the MDIO_GPIO_MODE register. Pin Name 2’b00 MDC MDC MDIO MDIO 2’b01 REFCLK0_OUT 2’b01 REFCLK0_OUT 2’b01 REFCLK0_OUT REFCLK1_OUT 2’b1x GPIO#17 2’b1x GPIO#36 2’b1x GPIO #23 GPIO #24 DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 26 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.7 EPHY_LED pin share scheme Controlled by the EPHY_BT_GPIO_MODE register. Pin Name EPHY_LED_GPIO_MODE =1’b0 EPHY_LED BS (dbg_jtag_mode=0) JTAG BS (dbg_jtag_mode=1) EPHY_LED4_N_JTRST_N EPHY_LED4_N JTAG_RST_N EPHY_LED3_N_JTCLK EPHY_LED3_N JTAG_CLK EPHY_LED2_N_JTMS EPHY_LED2_N JTAG_TMS EPHY_LED1_N_JTDI EPHY_LED1_N JTAG_TDI EPHY_LED0_N_JTDO EPHY_LED0_N JTAG_TDO EPHY_LED_GPIO_MODE=1’b1 GPIO#44 GPIO#43 GPIO#42 GPIO#41 GPIO#40 2.5.8 SPI pin share scheme Controlled by SPI_GPIO_MODE & SPI_REFCLK_MODE registers. Pin Name SPI_GPIO_MODE=0 SPI_GPIO_MODE=1 SPI_REFCLK_MODE=0 SPI_REFCLK_MODE=1 SPI_WP GPO#39 GPO#39 GPO#39 SPI_HOLD GPO#38 GPO#38 GPO#38 SPI_CS1 SPI_CS1 REFCLK0_OUT /GPI#37 GPIO#37 SPI_MISO SPI_MISO SPI_MISO GPIO#6 SPI_MOSI SPI_MOSI SPI_MOSI GPO#5 SPI_CLK SPI_CLK SPI_CLK GPO#4 SPI_CS0 SPI_CS0 SPI_CS0 GPIO#3 NOTE: I/O direction for REFCLK0_OUT at boot-up is input. Users can set GPI#37 to change to output mode. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 27 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.9 ND/SD pin share scheme Controlled by the ND_SD_GPIO_MODE register. Pin Name 2’b00 NAND ND_D7 ND_D7 ND_D6 ND_D6 ND_D5 ND_D5 ND_D4 ND_D4 ND_D3 ND_D3 ND_D2 ND_D2 ND_D1 ND_D1 ND_D0 ND_D0 ND_ALE ND_ALE ND_CLE ND_CLE ND_RB_N ND_RB_N ND_WP ND_WP ND_RE_N ND_RE_N ND_WE_N ND_WE_N ND_CS_N ND_CS_N NOTE : 1. All given GPIO are 4 mA drive capable. 2’b01 SDHC + BT + GPIO BT_ANT BT_WACT BT_AUX BT_STAT SD_D3 SD_D2 SD_D1 SD_D0 SD_CMD SD_CARD_DETECT SD_CLK SD_WP BT_ACT GPIO#46 GPIO#45 2’b1x GPIO*15 GPIO#59 GPIO#58 GPIO#57 GPIO#56 GPIO#55 GPIO#54 GPIO#53 GPIO#52 GPIO#51 GPIO#50 GPIO#49 GPIO#48 GPIO#47 GPIO#46 GPIO#45 DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 28 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.9.1 Pin share function description Pin Share Name I/O Pin Share Function description PCMDTX O PCM Data Transmit DATA signal sent from the PCM host to the external codec. PCMDRX I PCM Data Receive DATA signal sent from the external codec to the PCM host. PCMCLK I/O PCM Clock The clock signal can be generated by the PCM host (Output direction), or provided by an external clock (input direction). The clock frequency should match the slot configuration of the PCM host. e.g. 4 slots, PCM clock out/in should be 256 kHz. 8 slots, PCM clock out/in should be 512 kHz. 16 slots, PCM clock out/in should be 1.024 MHz. 32 slots, PCM clock out/in should be 2.048 MHz. 64 slots, PCM clock out/in should be 4.096 MHz. 128 slots, PCM clock out/in should be 8.192 MHz. PCMFS I2SSDI I2SSDO I2SWS I2SCLK I/O PCM SYNC signal. In our design, the direction of this signal is independent of the direction of PCMCLK. Its direction and mode is configurable. I I2S Data input O I2S Data output I/O I2S Channel Selection (or Word selection) In master mode the pin data direction is set to output, in slave mode it is set to input. I/O I2S clock In master mode the pin data direction is set to output, in slave mode it is set to input. WDT_RST_N I/O Watchdog timeout reset ND_D7 I/O Nand flash control data bit7 ND_D6 I/O Nand flash control data bit6 ND_D5 I/O Nand flash control data bit5 ND_D4 I/O Nand flash control data bit4 ND_ALE I/O Nand flash Address Latch Enable ND_CLE I/O Nand flash Command Latch Enable DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 29 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.5.10 xMII PHY/MAC Pin Mapping MII GE0_TXCLK GE0_TXCTL GE0_TXD[3:0] GE0_RXCLK GE0_RXCTL GE0_RXD[3:0] MDC MDIO MII PHY TXCLK TXCTL/TXEN TXD[3:0] MII RXCLK RXCTL/RXDV RXD[3:0] MDC MDIO Figure 2-3 MII  MII PHY RGMII GE0_TXCLK GE0_TXCTL GE0_TXD[3:0] GE0_RXCLK GE0_RXCTL GE0_RXD[3:0] MDC MDIO RGMII RGMII PHY TXCLK TXCTL/TXEN TXD[3:0] RXCLK RXCTL/RXDV RXD[3:0] MDC MDIO Figure 2-5 RGMII  RGMII PHY RvMII GE0_TXCLK GE0_TXCTL GE0_TXD[3:0] MII MAC TXCLK TXCTL/TXEN TXD[3:0] GE0_RXCLK GE0_RXCTL GE0_RXD[3:0] MDC MDIO RvMII RXCLK RXCTL/RXDV RXD[3:0] MDC MDIO Figure 2-4 RvMII  MII MAC RGMII GE0_TXCLK GE0_TXCTL GE0_TXD[3:0] RGMII MAC RXCLK RXCTL/RXDV RXD[3:0] GE0_RXCLK GE0_RXCTL GE0_RXD[3:0] MDC MDIO RGMII TXCLK TXCTL/TXEN TXD[3:0] MDC MDIO Figure 2-6 RGMII RGMII MAC DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 30 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 2.6 Bootstrapping Pins Description Pin Name Boot Strapping Signal Name Description WLED_N DRAM_FROM _EE For non-scan mode: (Validate at iNIC mode (chip mode 2 to 9) and NAND flash (chip mode 1 and 12) 0: DRAM/PLL configuration from EEPROM 1: DRAM configuration from Auto Detect ANT_TRN DBG_JTAG_MODE 0: EPHY_LED 1: JTAG MODE ANT_TRNB XTAL_FREQ_SEL 0: 20 MHz 1: 40 MHz {SPI_WP, DRAM_TYPE SPI_HOLD} 1: DDR1 (CPU/3) TSOP Package 2: DDR2 (CPU/3) FBGA Package 3: SDRAM (CPU/5) (LVTTL 3.3 V) TSOP Package {SPI_MOSI SPI_CLK, TXD2 GPIO0} CHIP_MODE[3:0] A vector to set chip function/test/debug modes. In non-test/debug operation, 1: Normal mode (boot from ROM+NAND flash 4 cycle address/2 KB page size) 2: Normal mode (boot from SPI 3-Byte Addr) 3: Normal mode (boot from SPI 4-Byte Addr) 4: iNIC RGMII (port 5) mode(boot from ROM) 5: iNIC MII (port 5) mode(boot from ROM) 6: iNIC RVMII (port 5) mode(boot from ROM) 7: iNIC PHY (port 0) mode(boot from ROM) 8: iNIC USB mode(boot from ROM) 9: iNIC PCIe mode(boot from ROM) 10: Normal mode (boot from ROM+NAND flash 4 cycle address/512 B page size) 11: Normal mode (boot from ROM+NAND flash 5 cycle address/2 KB page size) 12: Normal mode (boot from ROM+NAND flash 3 cycle address/512 B page size) 13: Debug mode 14: Scan mode 15: Test mode(CPU will be halted in this mode) NOTE: SDR/DDR1/DDR2 DRAM cell used is defined by register. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 31 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3. Maximum Ratings and Operating Conditions 3.3 Absolute Maximum Ratings I/O Supply Voltage Input, Output, or I/O Voltage Table 3-1 Absolute Maximum Ratings 3.4 Maximum Temperatures Maximum Junction Temperature (Plastic Package) Maximum Lead Temperature (Soldering 10 s) Table 3-2 Maximum Temperatures 3.5 Operating Conditions Core Supply Voltage Ambient Temperature Range I/O Supply Voltage Table 3-3 Operating Conditions 3.6 Thermal Characteristics Thermal characteristics without an external heat sink in still air conditions. MT7620N: Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB Thermal Resistance θJC (°C /W) for JEDEC 2L system PCB Thermal Resistance θJC (°C /W) for JEDEC 4L system PCB Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB MT7620A: Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB Thermal Resistance θJC (°C /W) for JEDEC 2L system PCB Thermal Resistance θJC (°C /W) for JEDEC 4L system PCB Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB Table 3-4 Thermal Characteristics 3.6 V GND -0.3 V to Vcc +0.3 V 125 °C 260 °C 1.27 V +/- 5% -20 to 55 °C 3.3 V +/- 10% 20.14 °C/W 17.19 °C/W 7.29 °C/W 6.14 °C/W 2.02°C/W 1.84°C/W 26.67 °C/W 24.9 °C/W 9.89 °C/W 9.75 °C/W 4.31°C/W 4.19°C/W DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 32 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.7 Storage Conditions The calculated shelf life in a sealed bag is 12 months if stored between 0 °C and 40 °C at less than 90% relative humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other high temperature processes must be handled in the following manner:  Mounted within 168 hours of factory conditions, i.e. < 30 °C at 60% RH.  Storage humidity needs to maintained at < 10% RH.  Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125 °C for 8 hrs. 3.8 External Xtal Specfication Frequency Frequency offset VIH/VIL Duty cycle Table 3-5 External Xtal Specifications 20 MHz/ 40 Mhz +/-20 ppm Vcc-0.3 V/0.3 V 45% to 55% 3.9 DC Electrical Characteristics Parameters 3.3 V Supply Voltage _VX supply Voltage 1.27 V Supply Voltage DDR1 IO Supply Voltage DDR2 IO Supply Voltage 3.3 V Current Consumption 1.5 V Current Consumption 1.27 V Current Consumption DDR2 Current Sym Vcc33 Vcc15 Vcc12 Vcc25 Vcc18 Icc33 Icc15 Icc12 Icc18 Conditions Min Typ Max Unit 3.0 3.3 3.6 V 1.3 1.5 3.3 V 1.20 1.27 1.33 V 2.4 2.5 2.7 V 1.7 1.8 1.9 V 218 436 mA 147 173 mA 380 540 mA 95 253 mA Table 3-6 DC Electrical Characteristics DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 33 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10 AC Electrical Characteristics 3.10.1 SDRAM Interface SDRAM CLK SDRAM_INPUT t_IN_SU t_IN_HD SDRAM_OUTPUT t_OUT_VLD Figure 3-1 SDRAM Interface Symbol t_IN_SU t_IN_HD t_OUT_VLD Description Min Setup time for Input signals (e.g. MD*) 1.5 Hold time for input signals 1.7 SDRAM_CLK to output signals (MA*, 0.8 MD*, SDRAM_RAS_N,…) valid Max Unit - ns - ns 5 ns Table 3-7 SDRAM Interface Diagram Key Remark output load: 8 pF DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 34 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.2 DDR2 SDRAM Interface The DDR2 SDRAM interface complies with 200 MHz timing requirements for standard DDR2 SDRAM. The interface drivers are SSTL_18 drivers matching the EIA/JEDEC standard JESD8-15A. tCH tCL CLK CLK# tIS tIH MCS_N tIS tIH MRAS_N tIS tIH MCAS_N tIS tIH MWE_N tIS tIH MA0 to MA13 tIS tIH MBA0, MBA1 MDQS MD MDQM Figure 3-2 DDR2 SDRAM Command tWPRE tDQSH tDQSL tDS D1 tDH D2 tDS D3 tDH tWPST D4 MDQS MD Figure 3-3 DDR2 SDRAM Write data tRPRE tRPST D1 D2 D3 tDQSQ (max) tQH Figure 3-4 DDR2 SDRAM Read data DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 35 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Symbol tCK(avg) tAC tDQSCK tCH tCL tHP tIS tIH tDQSQ tQH tRPRE tRPST tDQSS tDQSH tDQSL tDSS tDSH tWPRE tWPST tDS tDH Description Clock cycle time DQ output access time from SDRAM CLK DQS output access time from SDRAM CLK SDRAM CLK high pulse width SDRAM CLK low pulse width SDRAM CLK half period Address and control input setup time Address and control input hold time Data skew of DQS and associated DQ DQ/DQS output hold time from DQS DQS read preamble DQS read postamble DQS rising edge to CK rising edge DQS input-high pulse width DQS input-low pulse width DQS falling edge to SDRAM CLK setup time DQS falling edge hold time from SDRAM CLK DQS write preamble DQS write postamble DQ and DQM input setup time DQ and DQM input hold time Min Max Unit Remark 5 - ns -0.6 0.6 ns -0.5 0.5 ns 0.48 0.52 tCK(avg) 0.48 0.52 tCK(avg) Min(tCH,tCL) - ns 350 - ps 475 - ps - 0.35 ns tHP-0.45 - ns 0.9 1.1 tCK 0.4 0.6 tCK -0.25 0.25 tCK 0.35 - tCK 0.35 - tCK 0.2 - tCK 0.2 - tCK 0.35 - tCK 0.4 0.6 tCK *0.15 - ns *0.275 - ns Table 3-8 DDR2 SDRAM Interface Diagram Key NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 36 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.3 RGMII Interface GE0_TXCLK GE0_TXD/TXCTL t_TX_HD t_TX_SU GE0_RXCLK GE0_RXD/RXCTL t_RX_HD t_RX_SU Figure 3-5 RGMII Interface Symbol t_TX_SU t_TX_HD t_RX_SU t_RX_HD Description Setup time for output signals (e.g. GE0_TXD*, GE0_TXEN) Hold time for output signals Setup time for input signals (e.g. GE0_RXD*, GE0_RXDV) Hold time for input signals Min Max Unit Remark 1.2 - ns output load: 5 pF 1.2 - ns output load: 5 pF 1.0 - ns 1.0 - ns Table 3-9 RGMII Interface Diagram Key DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 37 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.4 MII Interface (25 Mhz) Receive: MII RXCLK RXDV,RXD t_RXCK t_RX_SU t_RX_HD Transmit: MII TXCLK t_TXCK TXEN,TXD t_TX_delay Figure 3-6 MII Interface (For 25 Mhz TXCLK & RXCLK) Symbol Description t_TX_delay Delay to output signals (e.g. GE0_TXD*, GE0_TXEN) t_RX_SU Setup time for input signals (e.g. GE0_RXD*, GE0_RXDV) t_RX_HD Hold time for input signals Min Max Unit Remark 6 22 ns output load: 5 pF 10 - ns 5 - ns Table 3-10 MII Interface Diagram Key DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 38 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.5 RvMII Interface (PHY Mode MII Timing) (25 Mhz) Receive: MII TXCLK t_TXCK TXEN,TXD t_TX_SU t_TX_HD Transmit: MII RXCLK t_RXCK RXDV,RXD t_RX_delay Figure 3-7 RvMII Interface (For 25 Mhz TXCLK & RXCLK) Symbol Description t_RX_delay Delays to output signals (e.g. GE0_TXD*, GE0_TXEN) t_TX_SU Setup time for input signals (e.g. GE0_RXD*, GE0_RXDV) t_TX_HD Hold time for input signals Min Max Unit Remark 5 25 ns output load: 5 pF 15 - ns 6 - ns Table 3-11 RvMII Interface Diagram Key DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 39 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.6 SPI Interface Write operation (driven by clock rising edge) SPI_CLK SPI_CS SPI_MOSI t_SPI_OVLD (max) T_SPI_OVLD (min) Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge) SPI_CLK SPI_CS SPI_MISO NOTE: 1) SPI_CLK is a gated clock. 2) SPI_CS is controlled by software t_SPI_IS Figure 3-8 SPI Interface t_SPI_IH Symbol t_SPI_IS t_SPI_IH t_SPI_OVLD Description Setup time for SPI input Hold time for SPI input SPI_CLK to SPI output valid Min Max Unit 6.0 - ns -1.0 - ns -2.0 3.0 ns Table 3-12 SPI Interface Diagram Key Remark output load: 5 pF DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 40 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.7 I2S Interface Transmitter SCK WS & SD Receiver SCK t_I2S_OVLD (min) t_I2S_OVLD (max) WS & SD t_I2S_IS t_I2S_IH Figure 3-9 I2S Interface Symbol t_I2S_IS t_I2S_IH t_I2S_OVLD Description Setup time for I2S input (data & WS) Hold time for I2S input (data & WS) I2S_CLK to I2S output (data & WS) valid Min Max Unit Remark 3.5 - ns 0.5 - ns 2.5 10.0 ns output load: 5 pF Table 3-13 I2S Interface Diagram Key DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 41 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.8 PCM Interface PCMCLK DTX t_PCM_OVLD PCMCLK DRX & FSYNC t_PCM_IS t_PCM_IH Figure 3-10 PCM Interface Symbol t_PCM_IS t_PCM_IH t_PCM_OVLD Description Min Max Unit Setup time for PCM input to PCM_CLK fall 3.0 - ns Hold time for PCM input to PCM_CLK 1.0 - ns fall PCM_CLK rise to PCM output valid 10.0 35.0 ns Table 3-14 PCM Interface Diagram Key Remark output load: 5 pF DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 42 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.10.9 Power On Sequence VDD33 SW_REG LDO_DIG 2.6 V LDO_DDR PORST_N T3 T4 T1 T2 t_PORST_N ( > 50 ms) 3.3 V 1.5 V 1.27 V 1.8 V 3.3 V Symbol T1 T2 T3 T4 t_PORST_N Figure 3-11 Power ON Sequence Description Min Max POR delay 800 Soft start 850 Soft start done 1.4 LDO_DIG soft start 650 Time between I/O power on to PORST_N 50 - de-assertion Table 3-15 Power ON Sequence Diagram Key Unit Remark us us ms us ms DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 43 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11 Package Physical Dimensions 3.11.1 TFBGA (11 mm x 11 mm) 265 balls 3.11.1.1 TFBGA Top View 3.11.1.2 TFBGA Side View Figure 3-12 TFBGA Top View Figure 3-13 TFBGA Side View 3.11.1.3 TFBGA “A” Expanded DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Figure 3-14 TFBGA “A” Expanded Page 44 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11.1.4 TFBGA Bottom View Figure 3-15 TFBGA Bottom View 3.11.1.5 TFBGA “B” Expanded 3.11.1.6 Package Diagram Key Symbol Dimensions (mm) Dimensions (inches) Min. Nom. Max. Min. Nom. Max. A ---- --- 1.20 --- --- 0.047 A1 0.16 0.21 0.26 0.006 0.008 0.010 A2 0.86 0.91 0.96 0.034 0.036 0.038 c 0.22 0.26 0.30 0.009 0.010 0.012 D 10.90 11.00 11.10 0.429 0.433 0.437 E 10.90 11.00 11.10 0.429 0.433 0.437 D1 --- 10.40 --- --- 0.409 --- E1 --- 10.40 --- --- 0.409 --- e --- 0.65 --- --- 0.026 --- b 0.25 0.30 0.35 0.010 0.012 0.014 aaa 0.15 0.006 bbb 0.10 0.004 ddd 0.08 0.003 eee 0.15 0.006 fff 0.08 0.003 MD/ME 17/17 17/17 NOTE: 1. Controlling dimensions are in millimeters. 2. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to primary datum C. 4. Special characteristics C class: bbb, ddd. 5. The pattern of pin 1 fiducial is for reference only. Figure 3-16 TFBGA “B” Expanded DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 45 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11.2 DR-QFN (12 mm x 12 mm) 148LD 3.11.2.1 DR-QFN Top View Figure 3-17 DR-QFN Top View 3.11.2.2 DR-QFN Side View 3.11.2.3 DR-QFN “B” Expanded Figure 3-18 DR-QFN Side View Figure 3-19 DR-QFN “B” Expanded DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 46 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11.2.4 DR-QFN Bottom View 3.11.2.5 DR-QFN “A” Expanded Figure 3-20 DR-QFN Bottom View Figure 3-21 DR-QFN “A” Expanded DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 47 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11.2.6 Package Diagram Key Symbol Dimensions (mm) Dimensions (inches) Min. Nom. Max. Min. Nom. Max. A 0.80 0.85 0.90 0.031 0.033 0.035 A1 0.00 0.02 0.05 0.000 0.0008 0.002 A2 0.65 0.70 0.75 0.026 0.028 0.030 A3 0.15 REF 0.006 REF b 0.18 0.22 0.30 0.007 0.009 0.012 D/E 11.90 12.00 12.10 0.469 0.472 0.476 D1/E1 11.75 BSC 0.463 BSC D3/E3 5.15 BSC 0.203 BSC eT 0.50 BSC 0.020 BSC eR 0.65 BSC 0.026 BSC L 0.30 0.40 0.50 0.012 0.016 0.020 θ 5° --- 15° 5° --- 15° K 0.20 --- --- 0.008 --- --- R 0.09 --- --- 0.004 --- --- aaa 0.10 0.004 bbb 0.07 0.003 ccc 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003 fff 0.10 0.004 ggg 0.20 0.008 NOTE: 1. Controlling dimensions are in millimeters. 2. Reference document: JEDEC MO-267 Exposed Pad Size D2/E2 (mm) D2/E2 (inches) L/F Min. Nom. Max. Min. Nom. Max. 5.65 5.80 5.95 0.222 0.228 0.234 Internal Pad Size (mm) (inches) L/F Min. Nom. Max. Min. Nom. Max. 5.85 6.00 6.15 0.230 0.236 0.242 DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 48 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 3.11.3 Reflow profile guideline Figure 3-22 Reflow profile for MT7620 Notes; 1. Reflow profile guideline is designed for SnAgCulead-free solder paste. 2. Reflow temperature is defined at the solder ball of package/or the lead of package. 3. MTK would recommend customer following the solder paste vendor’s guideline to design a profile appropriate your line and products. 4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk for having solder open issues. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 49 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 4. Abbreviations Abbrev. AC ACK ACPR AD/DA ADC AES AGC AIFS AIFSN ALC A-MPDU A-MSDU AP ASIC ASME ASYNC BA BAC BAR BBP BGSEL BIST BSC BJT BSSID BW CCA CCK CCMP CCX CF-END CF-ACK Description Access Category Acknowledge/ Acknowledgement Adjacent Channel Power Ratio Analog to Digital/Digital to Analog converter Analog-to-Digital Converter Advanced Encryption Standard Auto Gain Control Arbitration Inter-Frame Space Arbitration Inter-Frame Spacing Number Asynchronous Layered Coding Aggregate MAC Protocol Data Unit Aggregation of MAC Service Data Units Access Point Application-Specific Integrated Circuit American Society of Mechanical Engineers Asynchronous Block Acknowledgement Block Acknowledgement Control Base Address Register Baseband Processor Band Gap Select Built-In Self-Test Basic Spacing between Centers Basic Service Set Identifier Bandwidth Clear Channel Assessment Complementary Code Keying Counter Mode with Cipher Block Chaining Message Authentication Code Protocol Cisco Compatible Extensions Control Frame End Control Frame Acknowledgement Abbrev. CLK CPU CRC CSR CTS CW CWmax CWmin DAC DCF DDONE DDR DFT DIFS DMA DSP DW EAP EDCA EECS EEDI EEDO EEPROM eFUSE EESK EIFS EIV EVM FDS FEM FEQ FIFO FSM GF GND GP Description Clock Central Processing Unit Cyclic Redundancy Check Control Status Register Clear to Send Contention Window Maximum Contention Window Minimum Contention Window Digital-To-Analog Converter Distributed Coordination Function DMA Done Double Data Rate Discrete Fourier Transform DCF Inter-Frame Space Direct Memory Access Digital Signal Processor DWORD Expert Antenna Processor Enhanced Distributed Channel Access EEPROM chip select EEPROM data input EEPROM data output Electrically Erasable Programmable Read-Only Memory electrical Fuse EEPROM source clock Extended Inter-Frame Space Extend Initialization Vector Error Vector Magnitude Frequency Domain Spreading Front-End Module Frequency Equalization First In First Out Finite-State Machine Green Field Ground General Purpose DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 50 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Abbrev. GPO GPIO HCCA HCF HT HTC ICV IFS iNIC IV I2C I2S I/O IPI IQ JEDEC JTAG kbps KB LDO LDODIG LED LNA LO L-SIG MAC MCU MCS MDC MDIO MEM MFB MFS MIC MIMO MLNA MM Description General Purpose Output General Purpose Input/Output HCF Controlled Channel Access Hybrid Coordination Function High Throughput High Throughput Control Integrity Check Value Inter-Frame Space Intelligent Network Interface Card Initialization Vector Inter-Integrated Circuit Integrated Inter-Chip Sound Input/Output Idle Power Indicator In phase/Quadrature phase Joint Electron Devices Engineering Council Joint Test Action Group kilo (1000) bits per second Kilo (1024) Bytes Low-Dropout Regulator LDO for DIGital part output voltage Light-Emitting Diode Low Noise Amplifier Local Oscillator Legacy Signal Field Medium Access Control Microcontroller Unit Modulation and Coding Scheme Management Data Clock Management Data Input/Output Memory MCS Feedback MFB Sequence Message Integrity Code Multiple-Input Multiple-Output Monolithic Low Noise Amplifier Mixed Mode Abbrev. MOSFET MPDU MSB NAV NAS NAT NDP NVM ODT Oen OFDM OSC PA PAPE PBC PBF PCB PCF PCM PHY PIFS PLCP PLL PME PMU PN PROM PSDU PSI PSM PTN QoS RDG RAM RF RGMII Description Metal Oxide Semiconductor Field Effect Transistor MAC Protocol Data Units Most Significant Bit Network Allocation Vector Network-Attached Server Network Address Translation Null Data Packet Non-Volatile Memory On-die Termination Output Enable Orthogonal Frequency-Division Multiplexing Open Sound Control Power Amplifier Provider Authentication Policy Extension Push Button Configuration Packet Buffer Printed Circuit Board Point Coordination Function Pulse-Code Modulation Physical Layer PCF Interframe Space Physical Layer Convergence Protocol Phase-Locked Loop Physical Medium Entities Power Management Unit Packet Number Programmable Read-Only Memory Physical layer Service Data Unit Power supply Strength Indication Power Save Mode Packet Transport Network Quality of Service Reverse Direction Grant Random Access Memory Radio Frequency Reduced Gigabit Media Independent Interface DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 51 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip Abbrev. RH RoHS ROM RSSI RTS RvMII Rx RXD RXINFO RXWI S SDHC SDIO SDRAM SEC SGI SIFS SoC SPI SRAM SSCG STBC SW TA TBTT TDLS Description Relative Humidity Restriction on Hazardous Substances Read-Only Memory Received Signal Strength Indication (Indicator) Request to Send Reverse Media Independent Interface Receive Received Data Receive Information Receive Wireless Information Stream Secure Digital High Capacity Secure Digital Input Output Synchronous Dynamic Random Access Memory Security Short Guard Interval Short Inter-Frame Space System-on-a-Chip Serial Peripheral Interface Static Random Access Memory Spread Spectrum Clock Generator Space–Time Block Code Switch Regulator Transmitter Address Target Beacon Transmission Time Tunnel Direct Link Setup Abbrev. TKIP TRSW TSF TSSI Tx TxBF TXD TXDAC TXINFO TXOP TXWI UART USB UTIF VGA VCO VIH VIL VoIP WCID WEP WI WIV WMM WPA WPDMA WS Description Temporal Key Integrity Protocol Tx/Rx Switch Timing Synchronization Function Transmit Signal Strength Indication Transmit Transmit Beamforming Transmitted Data Transmit Digital-Analog Converter Transmit Information Opportunity to Transmit Tx Wireless Information Universal Asynchronous Rx/ Tx Universal Serial Bus Universal Test Interface Variable Gain Amplifier Voltage Controlled Amplifier High Level Input Voltage Low Level Input Voltage Voice over IP Wireless Client Identification Wired Equivalent Wireless Information Wireless Information Valid Wi-Fi Multimedia Wi-Fi Protected Access Wireless Polarization Division Multiple Access Word Select DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 52 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip 5. Revision History Rev Date 1.0 2012/07/09 1.1 2012/07/18 1.2 2012/08/20 1.3 2012/09/12 Description Initial Release Update SPI_WP/SPI_HOLD GPO table Fix DRQFN internal pad size typo Add IR reflow guideline This product is not designed for use in medical and/or life support applications. Do not use this product in these types of equipment or applications. This document is subject to change without notice and Ralink assumes no responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 53 of 54 FOR gaoMyEaDnIgA@TsEynKneCx.OcNoFmI.tDwENUTSIEAOLNLY MT7620 DATASHEET Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip changes in its products to improve function, performance, reliability, and to attempt to supply the best product possible. DSMT7620_V.1.3_091212 loginid=gaoyang@synnex.com.tw,time=2012-10-07 20:12:32,ip=180.174.210.9,doctitle=MT7620_Datasheet_20120912.pdf,company=Synnex Electronics HK Limited 聯強電子_RLT Page 54 of 54

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