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T89C51CC02/AT89C51CC02英文版数据手册

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  • 日期: 2018-07-03
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标签: 89C51

89C51是一种带4K字节闪烁可编程可擦除只读存储器(FPEROM—Flash Programmable and Erasable Read Only Memory)的低电压、高性能CMOS8位微处理器,俗称单片机。单片机的可擦除只读存储器可以反复擦除100次。该器件采用ATMEL高密度非易失存储器制造技术制造,与工业标准的MCS-51指令集和输出管脚相兼容。由于将多功能8位CPU和闪烁存储器组合在单个芯片中,ATMEL的89C51是一种高效微控制器,89C2051是它的一种精简版本。89C单片机为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。

89C51数据手册(英文版),详细介绍89C51功能结构及模块原理。

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Features cid129 80C51 Core Architecture cid129 256 Bytes of Onchip RAM cid129 256 Bytes of Onchip XRAM cid129 16K Bytes of Onchip Flash Memory Data Retention 10 Years at 85C EraseWrite Cycle 100K cid129 Boot Code Section with Independent Lock Bits cid129 2K Bytes of Onchip Flash for Bootloader InSystem Programming by OnChip Boot Program CAN UART and IAP Capability cid129 2K Bytes of Onchip EEPROM EraseWrite Cycle 100K cid129 14sources 4level Interrupts cid129 Three 16bit TimersCounters cid1......

Features (cid:129) 80C51 Core Architecture (cid:129) 256 Bytes of On-chip RAM (cid:129) 256 Bytes of On-chip XRAM (cid:129) 16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K (cid:129) Boot Code Section with Independent Lock Bits (cid:129) 2K Bytes of On-chip Flash for Bootloader In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability (cid:129) 2K Bytes of On-chip EEPROM – Erase/Write Cycle: 100K (cid:129) 14-sources 4-level Interrupts (cid:129) Three 16-bit Timers/Counters (cid:129) Full Duplex UART Compatible 80C51 (cid:129) Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz) (cid:129) Three or Four Ports: 16 or 20 Digital I/O Lines (cid:129) Two-channel 16-bit PCA – PWM (8-bit) – High-speed Output – Timer and Edge Capture (cid:129) Double Data Pointer (cid:129) 21-bit Watchdog Timer (7 Programmable bits) (cid:129) A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs (cid:129) Full CAN Controller – Fully Compliant with CAN rev.# 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 4 Independent Message Objects -Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature) -Priority Management for Transmission -Message Object Overrun Interrupt – Supports -Time Triggered Communication -Autobaud and Listening Mode -Programmable Automatic Reply Mode (cid:129) 1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode (cid:129) Readable Error Counters (cid:129) Programmable Link to On-chip Timer for Time Stamping and Network Synchronization Independent Baud Rate Prescaler (cid:129) Data, Remote, Error and Overload Frame Handling (cid:129) Power-saving Modes – Idle Mode – Power-down Mode (cid:129) Power Supply: 3 Volts to 5.5 Volts (cid:129) Temperature Range: Industrial (-40° to +85°C) (cid:129) Packages: SOIC28, SOIC24, PLCC28, VQFP32 Note: 1. At BRP = 1 sampling point will be fixed. Enhanced 8-bit Microcontroller with CAN Controller and Flash T89C51CC02 AT89C51CC02 Rev. 4126L–CAN–01/08 (cid:129) (cid:129) Description Block Diagram Part of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller. In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM. Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02. D x R D x T c c V s s V I C E A C P X E 2 T 2 T C D x R C D x T UART RAM 256x8 Flash 16K x 8 Boot loader 2K x 8 EE PROM 2K x 8 XRAM 256 x 8 PCA Timer 2 CAN CONTROLLER XTAL1 XTAL2 CPU C51 CORE IB-bus Timer 0 Timer 1 INT Ctrl Parallel I/O Ports Port 1 Port 2 Port 3 Port 4 Watch Dog 10-bit ADC T E S E R 0 T 1 T 0 T N I 1 T N I ) 1 ( 1 P ) 2 ( 2 P 3 P ) 2 ( 4 P F E R A V C C V A V D N G A V Note: 1. 8 analog Inputs/8 Digital I/O. 2. 2-bit I/O Port. 2 AT/T89C51CC02 4126L–CAN–01/08 Pin Configurations AT/T89C51CC02 VAREF 1 2 VAGND VAVCC 3 P4.1/RxDC 4 P4.0/TxDC 5 6 P2.1 7 P3.7 8 P3.6 9 P3.5/T1 P3.4/T0 10 P3.3/INT1 11 12 P3.2/INT0 P3.1/TxD 13 P3.0/RxD 14 VAREF VAGND VAVCC P4.1/RxDC P4.0/TxDC P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD P3.0/RxD XTAL2 1 2 3 4 5 6 7 8 9 10 11 12 SO28 SO24 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 RESET VSS VCC XTAL1 XTAL2 24 23 22 21 20 19 18 17 16 15 14 13 P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 RESET VSS VCC XTAL1 C D x R / 1 . 4 P C C V A V D N G A V F E R A V / X E 2 T 1 N A 1 / I / C E 2 N A 2 / / 2 T 0 N A 0 / . 1 P . 1 P . 1 P 25 24 23 22 21 20 19 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 RESET P4.0/TxDC P2.1 P3.7 P3.6 P3.5/T1 P3.4/T0 P3.3/INT1 5 6 7 8 9 10 11 4 3 2 1 8 2 7 2 6 2 PLCC-28 2 1 3 1 4 1 5 1 6 1 7 1 8 1 S S V C C V 2 L A T X 1 L A T X D x T 1 / . 3 P D x R / 0 . 3 P 0 T N I / 2 . 3 P 4126L–CAN–01/08 3 I C E / 2 N A / 2 . 1 P 5 242 23 22 21 20 19 18 17 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 NC RESET P4.0/TxDC P2.1 P3.7 P3.6 P3.5/T1 P3.4/T0 NC P3.3/INT1 2 3 1 3 1 2 3 4 5 6 7 8 0 9 1 C D x R / 1 . 4 P C C V A V C N D N G A V F E R A V X E 2 T / 1 N A / 1 . 1 P 2 T / 0 N A / 0 . 1 P 0 3 9 2 8 2 7 2 6 2 QFP-32 1 1 2 1 3 1 4 1 5 1 6 1 C N 2 L A T X 1 L A T X S S V C C V 0 T N I / 2 . 3 P / D x T 1 3 P . / D x R 0 3 P . 4 AT/T89C51CC02 4126L–CAN–01/08 Pin Description Pin Name Type Description AT/T89C51CC02 GND Circuit ground Supply Voltage Reference Voltage for ADC (input) Supply Voltage for ADC Reference Ground for ADC (internaly connected with the VSS) Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, See section ’Electrical Characteristic’) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2. P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2/AN2/ECI Analog input channel 2, PCA external clock input. P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5/AN5 Analog input channel 5, P1.6/AN6 Analog input channel 6, P1.7/AN7 Analog input channel 7, It can drive CMOS inputs without external pull-ups. Port 2: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. VSS VCC VAREF VAVCC VAGND P1.0:7 I/O P2.0:1 I/O 4126L–CAN–01/08 5
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