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small page nand的读写方法。绝版珍藏

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TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Introduction Technical Note Small-Block vs. Large-Block NAND Flash Devices For detailed NAND Flash device information, see www.micron.com/products/nand/partlist.aspx. Introduction As NAND Flash densities increase, it has become necessary to organize the NAND Flash array more efficiently while simultaneously reducing cost. Increasing the block size of the NAND Flash array accomplishes both of these goals. Using fewer blocks increases READ, PROGRAM, and ERASE performance and reduces chip size by reducing peripheral circuits between blocks. Most newer NAND Flash designs use the large-block format. A general rule for determining when NAND Flash devices transition from small-block to large-block organization is: • Small-block devices ≤ 1Gb density. • Large-block devices ≥ 1Gb density. Array Organization Small-block NAND Flash devices contain blocks made up of 32 pages, where each page contains 512 data bytes + 16 spare bytes. Large-block NAND Flash devices contain blocks made up of 64 pages, each page containing 2,048 data bytes + 64 spare bytes. For a 1Gb NAND Flash device, this translates to 8,192 blocks in the small-block organization and 1,024 blocks in the large-block organization. These organizational differences are highlighted in Figures 1 and 2 on page 2 and in Table 1 on page 3. 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Array Organization Figure 1: 1Gb NAND Flash Small-Block Array Organization 528 bytes Data register: 512 bytes 16 I/O 0 I/O 7 256K pages (8,192 blocks) per device 1 block 1st half of data register (256 bytes) 2nd half of data register (256 bytes) 1 page = 528 bytes 1 block = 528 bytes x 32 pages = (16K + 512) bytes 1 device = 528 bytes x 32 pages x 8,192 blocks = 1,056 Mb 512 bytes (data) 8 bits 16-byte spare area Figure 2: 1Gb NAND Flash Large-Block Array Organization 2,112 bytes Data register 2,048 bytes 64 I/O 0 I/O 7 1,024 blocks per device 1 block 2,048 bytes (data) 1 page = (2K + 64 bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 device = (2K + 64) bytes x 64 pages x 1,024 blocks = 1,056 Mb 64-byte spare area 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Address Cycles Table 1: Small-Block/Large-Block Comparison Page # 0 1 2 … 30 31 32 … 62 63 Total bytes Small Block 512 bytes + 16 bytes 512 bytes + 16 bytes 512 bytes + 16 bytes … 512 bytes + 16 bytes 512 bytes + 16 bytes N/A … N/A N/A 16,896 Large Block 2,048 bytes + 64 bytes 2,048 bytes + 64 bytes 2,048 bytes + 64 bytes … 2,048 bytes + 64 bytes 2,048 bytes + 64 bytes 2,048 bytes + 64 bytes … 2,048 bytes + 64 bytes 2,048 bytes + 64 bytes 135,168 Address Cycles NAND Flash devices have no dedicated address pins. Addresses are loaded via a shared I/O bus that is also used for loading commands and data. Small-block and large-block NAND Flash devices use 4 address cycles to load the entire address for a 1Gb device. However, as shown in Tables 2 and 3, the address cycles are used differently by smallblock and large-block devices. The small-block devices use 1 column address cycle while the large-block devices require 2 column address cycles. Small-block devices require more row address cycles due to the increased number of blocks. Large-block 2Gb devices use 5 address cycles. Table 2: Small-Block NAND Flash Address Cycles Cycle First Second Third Fourth I/O7 A7 A16 A24 LOW I/O6 A6 A15 A23 LOW I/O5 A5 A14 A22 LOW I/O4 A4 A13 A21 LOW I/O3 A3 A12 A20 LOW I/O2 A2 A11 A19 LOW I/O1 A1 A10 A18 A26 I/O0 A0 A91 A17 A25 Table 3: Cycle First Second Third Fourth Notes: 1. There is no A8 address bit in small-block devices. Large-Block NAND Flash Address Cycles I/O7 CA7 LOW BA7 LOW I/O6 CA6 LOW BA6 LOW I/O5 CA5 LOW PA5 LOW I/O4 CA4 LOW PA4 LOW I/O3 CA3 CA11 PA3 LOW I/O2 CA2 CA10 PA2 LOW I/O1 CA1 CA9 PA1 LOW I/O0 CA0 CA8 PA0 BA16 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands Commands Some commands differ between small- and large-block NAND Flash devices. The system designer should be aware of these differences and implement accordingly. Table 4 shows the basic command set for small-block NAND Flash devices; Table 5 shows the basic command set for large-block devices. Table 4: Small-Block NAND Flash Commands Command READ 1 READ 2 READ ID RESET PAGE PROGRAM (actual) PAGE PROGRAM (dummy) COPY BACK PROGRAM (actual) COPY BACK PROGRAM (dummy) BLOCK ERASE MULTI-PLANE BLOCK ERASE READ STATUS READ MULTI-PLANE STATUS 1st Cycle 00h/01h 50h 90h FFh 80h 80h 00h 03h 60h 60h-60h 70h 71h 2nd Cycle – – – – 10h 11h 8Ah 8Ah D0h D0h – – 3rd Cycle – – – – – – 10h 11h – – – – Acceptable Command During Busy No No No Yes No No No No No No Yes Yes Table 5: Large-Block NAND Flash Commands Command PAGE READ PAGE READ CACHE MODE START PAGE READ CACHE MODE START LAST READ for INTERNAL DATA MOVE RANDOM DATA READ READ ID READ STATUS PROGRAM PAGE PROGRAM PAGE CACHE MODE PROGRAM for INTERNAL DATA MOVE RANDOM DATA INPUT for PROGRAM BLOCK ERASE RESET 1st Cycle 00h 31h 3Fh 00h 05h 90h 70h 80h 80h 85h 85h 60h FFh 2nd Cycle 30h – – 35h E0h – – 10h 15h 10h – D0h – Valid During Busy No No No No No No Yes No No No No No Yes 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands Operation Examples General operation is similar in small-block and large-block NAND Flash devices. For example, when reading a page of data, both large- and small-block NAND Flash devices must first transfer a page of data from the NAND Flash array to the data register, as shown in Figure 3. The tR parameter represents the time required to move the page of data from the NAND Flash array into the data register. When a page of data is being programmed in both large- and small-block NAND Flash devices, the data is clocked into the device serially and stored in the cache register until a PROGRAM CONFIRM command is issued; the NAND Flash array is then programmed with the data. The tPROG parameter represents the time required to program the data from the data register to the NAND Flash array. Figure 3: Small-Block/Large-Block PROGRAM and READ Operations tWC Serial data in 512 + 16-byte page Data register tRC Serial data out tPROG tR Smallblock NAND Flash array tWC Serial data in Largeblock NAND Flash array 2,048 + 64-byte page Data register tPROG tRC Serial data out tR Table 6: PROGRAM and READ Operation Parameters Symbol tPROG tR tRC tWC Parameter Definition Program time Random access time Serial READ cycle time WRITE cycle time 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands READ Operations Small-Block READ Operations There are several important differences between small-block and large-block READ operations. Small-block NAND Flash devices use an 8-bit column address cycle that can access up to 256 unique bytes in a page. The page size is 512 bytes + 16 spare bytes, so the small-block device must use three address pointer commands to access all the bytes in the page. This leads to a more complicated method for accessing the NAND Flash array. As shown in Figures 4 and 5, and in Figure 6 on page 7, the address pointer is set by the command used to read the NAND Flash array: • The 00h command sets the pointer to the A area, consisting of bytes 0–255. • The 01h command sets the pointer to the B area, consisting of bytes 256–511. • The 50h command sets the pointer to the spare C area, consisting of bytes 512–527. Figure 4: Small-Block READ 1 Operation, Command 00h CLE CE# WE# ALE RE# I/O[7:0] R/B# 00h A[7:0] A[16:9] A[24:17] A[26:25] Column address Page address tR DOUT N DOUT N+1 DOUT N+2 DOUT 255 Don‘t Care Figure 5: Small-Block READ 1 Operation, Command 01h CLE CE# WE# ALE RE# I/O[7:0] R/B# 01h A[7:0] A[16:9] A[24:17] A[26:25] Column address Page address tR DOUT N DOUT N+1 DOUT N+2 DOUT 511 Don‘t Care 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands Figure 6: Small-Block READ 2 Operation CLE CE# WE# ALE RE# I/O[7:0] R/B# 50h A[7:0] A[16:9] A[24:17] A[26:25] A[3:0] = Valid address tR A[7:4] = “Don’t Care” DOUT 512 DOUT 527 Don‘t Care Large-Block READ Operations Large-block NAND Flash devices offer a simplified approach to accessing the NAND Flash array for READ operations. A PAGE READ command consists of a single command, 00h, followed by 4 address cycles for a 1Gb device, and a READ CONFIRM command, 30h, regardless of the area accessed in the NAND Flash array (see Figure 7). Figure 7: Large-Block PAGE READ Operation CLE CE# WE# ALE RE# I/O[7:0] 00h R/B# Address (4 cycles) 30h tR Data output (Serial access) Don‘t Care 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands PROGRAM Operations Small-Block NAND Flash PROGRAM Operations Small-block NAND Flash devices also use an address pointer for programming operations. Implementing the address pointer for PROGRAM operations is similar to implementing the address pointer for READ operations: • The 00h command sets the pointer to the A area, consisting of bytes 0–255. • The 01h command sets the pointer to the B area, consisting of bytes 256–511. • The 50h command sets the pointer to the spare C area, consisting of bytes 512–527. Figure 8: Area A PROGRAM Command Input Sequence CLE CE# WE# ALE I/O[7:0] 00h 80h Address cycles D1 D2 10h 00h 80h Address cycles D3 D4 10h R/B# Issue 00h command to set pointer to area A (bytes 0–255). Area A, B, or C can be programmed, depending on the number of data bytes input. This 00h command can be skipped. Figure 9: Area B PROGRAM Command Input Sequence CLE CE# WE# ALE I/O[7:0] 01h 80h Address cycles D1 D2 10h 01h 80h Address cycles D3 D4 10h R/B# Issue 01h command to set pointer to area C (bytes 256–511). Area B or C can be programmed, depending on the number of data bytes input. Reissue 01h command prior to each successive PROGRAM command. 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands Figure 10: Area C PROGRAM Command Input Sequence CLE CE# WE# ALE I/O[7:0] 50h 80h Address cycles D1 D2 10h 50h 80h Address cycles D3 D4 10h R/B# Issue 50h command to set pointer to area C (bytes 512–527). This 50h command can be skipped. Large-Block NAND Flash PROGRAM Operations Large-block NAND Flash devices offer a simplified approach to programming the NAND Flash array. A PROGRAM PAGE command consists of an 80h command followed by 4 address cycles (for a 1Gb device), and a PROGRAM CONFIRM command, 10h, regardless of the area accessed in the NAND Flash array; no special address pointers are required. This simplifies the software interface for the NAND Flash device (see Figure 11). Figure 11: Large-Block PROGRAM Operations CLE CE# tWC WE# ALE tWB tPROG RE# I/O[7:0] 80h SERIAL DATA INPUT command Col add 1 Col add 2 Row add 1 Row add 2 DIN DIN N M 1 up to m Byte serial input 10h PROGRAM command R/B# x8 device: m = 2,112 bytes x16 device: m =1,056 bytes 70h READ STATUS command Status Don‘t Care 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands ERASE Operations NAND Flash ERASE Operations ERASE operations are similar for small-block and large-block NAND Flash devices. ERASE commands operate on one block at a time, so only row address cycles are required. In the case of a 1Gb device, the small-block NAND Flash device requires 3 address cycles; the large-block NAND Flash device requires only 2 address cycles (see Figures 12 and 13). Figure 12: Small-Block ERASE Operation CLE CE# WE# tWC ALE tWB tBERS RE# I/O[7:0] 60h A[16:9] A[24:17] A[26:25] D0h ERASE SETUP command Block address ERASE CONFIRM command R/B# Busy 70h READ STATUS command Status Don‘t Care 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Commands Figure 13: Large-Block ERASE Operation CLE CE# WE# tWC ALE# tWB tBERS RE# I/O[7:0] 60h ERASE SETUP command Row add 1 Row add 2 Block address D0h ERASE CONFIRM command R/B# Busy 70h READ STATUS command Status Don‘t Care 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Performance Comparison Performance Comparison Large-block NAND Flash devices offer increased READ, PROGRAM, and ERASE performance compared to their small-block counterparts. Tables 7, 8, and 9 provide comparisons for each operation. Table 7: READ Performance: Small Block vs. Large Block Process Command latch (00h and/or 01) Address latch Command latch (30h or 50h) R/B# LOW (tR) Data output cycles Data output cycles total time Total time to read a page Data rate Small Block Repetitions 2 4 1 1 528 Cycle Time 50 50 50 15 50 Total Time 100 200 50 15 26.4 41.75 12.65 Large Block Repetitions 1 4 1 1 2,112 Cycle Time 50 50 50 25 50 Total Time 50 200 50 25 105.6 130.9 16.13 Unit ns ns ns µs ns µs µs MB/s Table 8: PROGRAM Performance: Small Block vs. Large Block Process Command latch (80h) Address latch Command latch (10h) R/B# LOW (tPROG) Data input cycles Data input cycles total time Total time to program a page Data rate Small Block Repetitions 2 4 1 1 528 Cycle Time 50 50 50 200 50 Total Time 100 200 50 200 26.4 226.75 2.33 Large Block Repetitions 1 4 1 1 2,112 Cycle Time 50 50 50 300 50 Total Time 50 200 50 300 105.6 405.9 5.20 Unit ns ns ns µs ns µs µs MB/s Table 9: Block Small Large ERASE Performance: Small Block vs. Large Block Block Size 16K 128K ERASE Time per Block 2 2 Unit ms ms 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. Summary TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Summary Large-block NAND Flash devices offer significant performance increases over their small-block NAND Flash counterparts for READ, PROGRAM, and ERASE operations. In addition, large-block NAND Flash devices can access various parts of the NAND Flash array without address pointers. This provides greater flexibility for system designers, simplifies the software interface for the NAND Flash device, and decreases overhead for command and address operations. Most newer NAND Flash designs utilize large-block format. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-29-07: Small-Block vs. Large-Block NAND Flash Devices Revision History Revision History Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/07 • “Introduction” on page 1: Revised description. • Table 3 on page 3: Changed cycle 3 and 4 values. • “Operation Examples” on page 5: Changed “cache register” to “data register” in the second, third, and last sentences. Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/06 • Table 7 on page 12: Changed “Read data cycles” and “Read data cycles total time” to “Data output cycles” and “Data output cycles total time.” Changed “Total time to program a page” to “Total time to read a page.” Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/05 • Initial release. 09005aef81999ecb pdf/ 09005aef81999f9d source tn2907_sm_block_vs_lg_block.fm - Rev. C 5/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved.

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