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VGA程序编写

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    标    签:VGA

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    基于fpga的vga控制器部分程序,仅限参考

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    彩条信号发生器模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity color is port( clk :in std_logic; md :in std_logic; hs,vs,r,g,b :out std_logic); end color; architecture ONE of color is signal hs1,vs1 :std_logic; signal mmd :std_logic_vector(1 downto 0); signal cc,ll,hent,vent :std_logic_vector(9 downto 0); signal rgbx,rgby,rgbp,rgb :std_logic_vector(3 downto 1); begin process(md) begin if md'event and md='0'then if mmd="10" then mmd<="00"; else mmd<=mmd+1; end if; end if; end process; process(mmd) begin if mmd="00" then rgbp<=rgbx; elsif mmd="01" then rgbp<=rgby; elsif mmd="10" then rgbp<=rgbx xor rgby; else rgbp<="000"; end if; end process; process(clk) begin if(rising_edge(clk))then if(hent<800)then hent<=hent+1; else hent<=(others=>'0'); end if; end if; end process; process(clk) begin if(rising_edge(clk))then if(hent=640+8)then if(vent<525)then vent<=vent+1; else vent<=(others=>'0'); end if; end if; end if; end process; ll<=hent;cc<=vent; process(clk)begin if(rising_edge(clk))then if((hent>=640+8+8)and(hent<640+8+8+96))then hs1<='0'; else hs1<='1'; end if; end if; end process; process(vent)begin if((vent>=480+8+2)and(vent<480+8+2+2))then vs1<='0'; else vs1<='1'; end if; end process; process(ll,cc) begin if ll<80 then rgbx<="001"; elsif ll<160 then rgbx<="010"; elsif ll<240 then rgbx<="011"; elsif ll<320 then rgbx<="100"; elsif ll<400 then rgbx<="101"; elsif ll<480 then rgbx<="110"; elsif ll<560 then rgbx<="111"; else rgbx<="000"; end if; if cc<60 then rgby<="001"; elsif cc<120 then rgby<="010"; elsif cc<180 then rgby<="011"; elsif cc<240 then rgby<="100"; elsif cc<300 then rgby<="101"; elsif cc<360 then rgby<="110"; elsif cc<420 then rgby<="111"; else rgby<="000"; end if; end process; rgb(1)<=(rgbp(1)xor md) and hs1 and vs1; rgb(2)<=(rgbp(2)xor md) and hs1 and vs1; rgb(3)<=(rgbp(3)xor md) and hs1 and vs1; hs<=hs1;vs<=vs1;r<=rgb(1);g<=rgb(2);b<=rgb(3); end ONE; rom信息读取显示控制器 process(clock0)begin begin if(clock0'event and clock0='1')then clock_25mhz<=not clock_25mhz; end if; end process; process(clock_25mhz)begin if(clock_25mhz'event and clock_25mhz='1')then if count_y>240 and count_y<369 then if count_x>63 and count_x<576 then addresss(8 downto 0)<=count_x(8 downto 0)-64; addresss(15 downto 9)<=count_y(6 downto 0)-241; end if; end if; end if; end process;

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