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NT35310 datasheet

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    Draft Version NT35310 NT35310 One-chip Driver IC with internal GRAM for 262K colors 320RGB x 480 a-Si TFT LCD with CPU / RGB / MDDI / MIPI Interface Draft Version Version 0.04 2012/05/11 2012/05/11 1 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 INDEX REVERSION HISTORY.................................................................................................................................................7 1. GENERAL DESCRIPTION .......................................................................................................................................9 1.1 PURPOSE OF THIS DOCUMENT ...................................................................................................................................................9 1.2 GENERAL DESCRIPTION.............................................................................................................................................................9 2. FEATURES.................................................................................................................................................................10 3. BLOCK DIAGRAM ..................................................................................................................................................13 4. PIN DESCRIPTIONS................................................................................................................................................14 4.1 POWER INPUTS .........................................................................................................................................................................14 4.2 MCU SYSTEM INTERFACE .......................................................................................................................................................14 4.3 SPI INTERFACE......................................................................................................................................................................... 15 4.4 RGB INTERFACE ......................................................................................................................................................................15 4.5 MDDI / MIPI INTERFACE........................................................................................................................................................ 16 4.6 CABC CONTROL PINS .............................................................................................................................................................16 4.7 INTERFACE LOGIC PINS ...........................................................................................................................................................17 4.8 DISPLAY DRIVER ANALOG OUTPUTS ......................................................................................................................................18 4.9 POWER SUPPLY ........................................................................................................................................................................19 4.10 TEST PINS (TEST AND DUMMY PINS) .....................................................................................................................................19 5. FUNCTION DESCRIPTIONS..................................................................................................................................20 5.1 MPU INTERFACE...................................................................................................................................................................... 20 5.1.1 General Protocol................................................................................................................................................................21 5.1.2 80-System Interface ............................................................................................................................................................21 5.1.2.1 Write cycle sequence......................................................................................................................................................................... 22 5.1.2.2 Read Cycle Sequence........................................................................................................................................................................ 23 5.2 SPI INTERFACE......................................................................................................................................................................... 24 5.2.1 General Description for LoSSI........................................................................................................................................... 24 5.2.2 Command Write for LoSSI.................................................................................................................................................. 24 5.2.3 Read Functions for LoSSI .................................................................................................................................................. 24 5.2.4 Display Module Data Transfer Recovery for LoSSI........................................................................................................... 25 5.2.5 Display Module Data Transfer Pause for LoSSI ................................................................................................................27 5.2.6 Display Module Data Transfer Modes for LoSSI ...............................................................................................................28 5.2.6.1 Method 1........................................................................................................................................................................................... 28 5.2.6.2 Method 2........................................................................................................................................................................................... 28 5.3 DISPLAY DATA RAM (DDRAM)...............................................................................................................................................29 5.3.1 Serial Interface for DATA RAM write ................................................................................................................................30 5.3.2 8-Bits Parallel Interface for RAM Data Write....................................................................................................................31 5.3.3 9-Bits Parallel Interface (80-system) for RAM Data Write ................................................................................................33 5.3.4 16-Bits Parallel Interface for RAM Data Write.................................................................................................................. 34 5.3.5 18-Bits Parallel Interface for RAM Data Write.................................................................................................................. 36 5.3.6 Serial Interface Signals for RAM Data Read .....................................................................................................................37 5.3.7 80-8-bits Parallel Interface Signals for RAM Data Read ..................................................................................................38 5.3.8 80-9-bits Parallel Interface Signals for RAM Data Read ..................................................................................................39 5.3.9 80-16-bits Parallel Interface Signals for RAM Data Read ................................................................................................40 5.3.10 80-18-bits Parallel Interface Signals for RAM Data Read .............................................................................................. 41 5.4 RGB INTERFACE ......................................................................................................................................................................42 5.4.1 General Description...........................................................................................................................................................42 5.4.2 General Timing Diagram ...................................................................................................................................................43 5.4.3 RGB Interface Bus Width Set.............................................................................................................................................. 44 5.4.4 RGB Interface Mode Set.....................................................................................................................................................45 5.4.5 RGB Interface Mode 1 & Mode 2 Timing Chart ................................................................................................................46 5.5 FRAME TEARING EFFECT INTERFACE..................................................................................................................................... 49 5.5.1 Tearing Effect Line Modes.................................................................................................................................................. 49 5.5.2 Example 1: MPU write is faster than panel read...............................................................................................................52 5.5.3 Example 2: MPU write is slower than panel read .............................................................................................................53 5.6 MDDI INTERFACE (MOBILE DISPLAY DIGITAL INTERFACE) .................................................................................................57 2012/05/11 2 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.1 MDDI Link Protocol .......................................................................................................................................................... 58 5.6.2 MDDI Link Packet descriptions.........................................................................................................................................58 5.6.3 Writing Video Data to Memory Sequence...........................................................................................................................68 5.6.4 Writing Register Sequence.................................................................................................................................................. 68 5.6.5 Reading Video Data from Memory Sequence .....................................................................................................................69 5.6.6 Reading Register Sequence ................................................................................................................................................69 5.6.7 Hibernation Setting ............................................................................................................................................................70 5.6.8 Deep Standby Mode Setting by MDDI ...............................................................................................................................71 5.6.9 Vsync Based Link Wakeup .................................................................................................................................................. 73 5.7 MIPI INTERFACE (MOBILE INDUSTRY PROCESSING INTERFACE) .........................................................................................74 5.7.1 Display Module Pin Configuration for DSI .......................................................................................................................75 5.7.2 Display Serial Interface (DSI)............................................................................................................................................76 5.7.2.1 General Description ......................................................................................................................................................................... 76 5.7.2.2 Interface Level Communication........................................................................................................................................................ 76 5.7.2.2.1 General...................................................................................................................................................................................... 76 5.7.2.2.2 DSI-CLOCK Lane ..................................................................................................................................................................... 77 5.7.2.2.3 DSI-DATA Lanes........................................................................................................................................................................ 83 5.7.2.3 Packet Level Communication ........................................................................................................................................................... 94 5.7.2.3.1 Short Packet (SPa) and Long Packet (LPa) Structures.............................................................................................................. 94 5.7.2.3.2 Packer Transmission................................................................................................................................................................ 113 5.7.2.3.3 Communication Sequence........................................................................................................................................................ 144 5.7.2.4 Video Mode Communication........................................................................................................................................................... 156 5.7.2.4.1 Transmission Packet Sequences............................................................................................................................................... 156 5.7.2.4.2 Non-Burst Mode with Sync Pulses........................................................................................................................................... 157 5.7.2.4.3 Non-Burst Mode with Sync Events........................................................................................................................................... 158 5.7.2.4.4 Burst Mode .............................................................................................................................................................................. 159 5.7.2.4.5 Parameters .............................................................................................................................................................................. 159 5.7.2.4.6 Video mode ON/OFF sequence................................................................................................................................................ 160 5.7.3 Memory access for DSI .................................................................................................................................................... 162 5.8 DYNAMIC BACKLIGHT CONTROL FUNCTION........................................................................................................................ 170 5.8.1 Content Adaptive Backlight Control (CABC).....................................................................................................................171 5.8.2 Display Backlight Dimming Control..................................................................................................................................172 5.8.3 Brightness Control Lines for Backlight..............................................................................................................................173 5.9 WINDOW ADDRESS FUNCTION...............................................................................................................................................176 5.10 REDUCED POWER CONSUMPTION DRIVE SETTINGS...........................................................................................................177 5.11 FRAME-FREQUENCY ADJUSTMENT FUNCTION ...................................................................................................................177 5.12 GAMMA FUNCTION ............................................................................................................................................................ 178 5.13 RESET FUNCTION .................................................................................................................................................................179 5.14 BASIC OPERATION MODE .................................................................................................................................................... 181 5.15 POWER ON/OFF SEQUENCE .................................................................................................................................................182 5.16 INSTRUCTION SETTING SEQUENCE...................................................................................................................................... 183 5.16.1 Sleep SET/EXIT Sequences ............................................................................................................................................ 183 5.16.2 Deep Standby Mode ENTER/EXIT Sequences ...............................................................................................................184 5.17 MTP WRITE SEQUENCE.......................................................................................................................................................185 5.17.1 First Time MTP Programming Sequence (for all MTP).................................................................................................186 5.17.2 Second Time MTP Programming Sequence ...................................................................................................................187 5.17.3 Third Time MTP Programming Sequence (Only for VCOM, ID and WRDDB) .............................................................188 5.18 INSTRUCTION SETUP FLOW .................................................................................................................................................190 5.18.1 Initializing with the Build-in Power Supply Circuit .......................................................................................................190 5.18.2 Power Off Sequence .......................................................................................................................................................191 5.19 SLEEP OUT–COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE......................192 6. COMMAND DESCRIPTIONS...............................................................................................................................194 6.1 USER COMMAND SET (COMMAND 1)..................................................................................................................................... 196 NOP (00h): No Operation ........................................................................................................................................................ 198 SOFT_RESET (01h): Software Reset ........................................................................................................................................199 RDID (04h): Read Display ID ..................................................................................................................................................200 RDNUMED (05h): Read Number of the Errors on DSI ...........................................................................................................201 GET_POWER_MODE (0Ah): Read Display Power Mode ......................................................................................................202 GET_ADDRESS_MODE (0Bh): Get the Frame Memory to the Display Panel Read Order.................................................... 203 GET_PIXEL_MODE (0Ch): Read Input Pixel Format.............................................................................................................204 GET_DISPLAY_MODE (0Dh): Read the Current Display Mode.............................................................................................205 2012/05/11 3 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_SIGNAL_MODE (0Eh): Get Display Module Signaling Mode .......................................................................................206 RDDSDR (0Fh): Read Display Self-Diagnostic Result.............................................................................................................207 ENTER_SLEEP_MODE (10h): Enter the Sleep-In Mode......................................................................................................... 208 EXIT_SLEEP_MODE (11h): Exit the Sleep-In Mode ...............................................................................................................209 ENTER_PARTIAL_MODE (12h): Partial Display Mode On ...................................................................................................210 ENTER_NORMAL_MODE (13h): Normal Display Mode On ................................................................................................. 211 EXIT_INVERT_MODE (20h): Display Inversion Off...............................................................................................................212 ENTER_INVERT_MODE (21h): Display Inversion On...........................................................................................................213 ALLPOFF (22h): All Pixel Off..................................................................................................................................................214 ALLPON (23h): All Pixel On .................................................................................................................................................... 215 GMASET (26h): Gamma Curves Selection ...............................................................................................................................216 SET_DISPLAY_OFF (28h): Display Off ..................................................................................................................................217 SET_DISPLAY_ON (29h): Display On.....................................................................................................................................218 SET_HORIZONTAL_ADDRESS (2Ah): Set the Column Address .............................................................................................219 SET_VERTICAL_ADDRESS (2Bh): Set Page Address.............................................................................................................221 WRITE_MEMORY_START (2Ch): Memory Write Start Command ..........................................................................................223 SET_MDDI_RAM_READ_ADDRESS (2Dh): Set the RAM Horizontal and Vertical Address..................................................224 READ_MEMORY_START (2Eh): Memory Read Start Command ............................................................................................ 225 SET_PARTIAL_AREA (30h): Defines the Partial Display Area ...............................................................................................227 SCRLAR (33h): Set Scroll Area.................................................................................................................................................229 SET_TEAR_ON (35h): Tearing Effect Line ON ........................................................................................................................ 233 SET_ADDRESS_MODE (36h): Memory Data Access Control ................................................................................................ 235 VSCSAD (37h): Vertical Scroll Start Address of RAM ..............................................................................................................238 EXIT_IDLE_MODE (38h): Idle Mode Off ...............................................................................................................................240 ENTER_IDLE_MODE (39h): Idle Mode On ............................................................................................................................ 241 SET_PIXEL_FORMAT (3Ah): Set the Interface Pixel Format .................................................................................................243 RGBCTRL (3Bh): RGB Interface Signal Control......................................................................................................................244 RAMWRC (3Ch): Memory Write Continuously ........................................................................................................................ 247 RAMRDC (3Eh):RAM Read Continuously.............................................................................................................................248 SET_TEAR_SCANLINE (44h): Set Tear Line ...........................................................................................................................249 RDSCL (45h):Read Scan Line................................................................................................................................................ 251 ENTER_DSTB_MODE (4Fh): Enter the Deep Standby Mode .................................................................................................252 WRDISBV (51h): Write Display Brightness ..............................................................................................................................253 RDDISBV (52h): Read Display Brightness...............................................................................................................................254 WRCTRLD (53h): Write CTRL Display ....................................................................................................................................255 RDCTRLD (54h): Read CTRL Display .....................................................................................................................................257 WRCTRLD (55h): Write CTRL Display ....................................................................................................................................258 RDCABC (56h): Read Content Adaptive Brightness Control (CABC) Mode ...........................................................................259 RDCABCMB (5Fh): Read CABC Minimum Brightness ...........................................................................................................261 RDDSDR (68h): Read Display Self-Diagnostic Result .............................................................................................................262 SET_MDDI (8Fh) .....................................................................................................................................................................263 RDDDBS (A1h): Read DDB Start.............................................................................................................................................264 RDDDBC (A8h): Read DDB Continue .....................................................................................................................................265 RDFCS (AAh): Read First Checksum .......................................................................................................................................266 MDDI_WAKE_TOGGLE (ADh): MDDI VSYNC BASED LINK WAKE-UP ............................................................................ 267 STB EDGE POSITION (AEh) ...................................................................................................................................................268 RDCCS (AFh): Read Continue Checksum ................................................................................................................................ 270 RDID1 (DAh): Read ID1 ..........................................................................................................................................................271 RDID2 (DBh): Read ID2 ..........................................................................................................................................................272 RDID3 (DCh): Read ID3 ..........................................................................................................................................................273 IDLEMODE_BL_Control (E1h): Write IDLEMODE_BL_Control ..........................................................................................274 IDLEMODE_BL_Control (E2h): Read IDLEMODE_BL_Control........................................................................................... 276 PAGE_CTRL (EDh): Unlock CMD2 .......................................................................................................................................277 PAGE_STATUS (FFh): PAGE unlock status............................................................................................................................ 279 6.2 CMD2_P0 REGISTER LIST .....................................................................................................................................................280 RDREGEXT1 ............................................................................................................................................................................ 281 DISPLAY_CTRL (B0h)..............................................................................................................................................................282 PORCH_CTRL: Front & Back Porch Setting (B1h) .................................................................................................................284 FRAMERATE_CTRL (B2h).......................................................................................................................................................286 SPI&RGB IF SETTING (B3h): SPI&RGB INTERFACE SETTING .........................................................................................289 2012/05/11 4 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 INVCTRL (B4h): Inversion Control ..........................................................................................................................................290 PMTCTL (B5h):Partial and Idle Mode Timing Control ......................................................................................................... 291 DISPLAY_CTRL_NORM (B6h).................................................................................................................................................293 DISPLAY_CTRL2: Set the States for LED Control (B7h) ......................................................................................................... 295 MTP Selection (B8h) .................................................................................................................................................................296 PWR_CTRL1 (C0h)...................................................................................................................................................................297 PWR_CTRL2 (C1h)...................................................................................................................................................................302 PWR_CTRL3 (C2h)...................................................................................................................................................................304 PWR_CTRL4 (C3h)...................................................................................................................................................................305 PWR_ CTRL5 (C4h)..................................................................................................................................................................306 PWR_ CTRL6 (C5h)..................................................................................................................................................................308 PWR_ CTRL7 (C6h)..................................................................................................................................................................310 WID_CTRL1 (D1h): WID1 .......................................................................................................................................................312 WID_CTRL2 (D2h): WID2 .......................................................................................................................................................313 WID_CTRL3 (D3h): WID3 .......................................................................................................................................................314 READID4 (D4h): Read ID4 ......................................................................................................................................................315 DDB_CTRL (D5h):Write DDB Info .......................................................................................................................................316 RDVNT (DDh): Read NV Memory Flag Status .........................................................................................................................317 EPWRITE (DEh): NV Memory Write Command.......................................................................................................................318 MTPPWR (DFh): MTP Write function enable ..........................................................................................................................319 RDREGEXT1 (EBh):Register read command in SPI interface ..............................................................................................320 RDREGEXT2 (ECh):Register read command in SPI interface ..............................................................................................321 PAGE_LOCK (EFh):Set the Register to command1...............................................................................................................322 PAGE_LOCK (BFh):Set the Register to command2 Page 1...................................................................................................323 6.3 CMD2_P1 REGISTER LIST .....................................................................................................................................................324 3GAMMAR_CTRL _RED_P (E0h) ...........................................................................................................................................331 3GAMAR_CTRL _RED_N (E1h) ..............................................................................................................................................333 3GAMMAR_CTRL _GREEN_P (E2h) ......................................................................................................................................335 3GAMMAR_CTRL _GREEN_N (E3h)......................................................................................................................................337 3GAMMAR_CTRL _BLUE_P (E4h) ......................................................................................................................................... 339 3GAMMAR_CTRL _BLUE_N (E5h)......................................................................................................................................... 341 CABC GAMMA offset (E6h)......................................................................................................................................................343 CABC GAMMA offset (E7h)......................................................................................................................................................345 CABC GAMMA offset (E8h)......................................................................................................................................................347 PAGE_LOCK (00h): Set the Register to command2 Page 0 ...................................................................................................349 7. ELECTRICAL CHARACTERISTICS..................................................................................................................350 7.1 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................350 7.2 DC CHARACTERISTICS ...................................................................................................................................................351 7.2.1 Basic Characteristics .......................................................................................................................................................351 7.2.2 Current Consumption .......................................................................................................................................................352 7.2.3 MDDI DC Characteristics ...............................................................................................................................................352 7.2.4 MIPI DC Characteristics .................................................................................................................................................353 7.3 AC CHARACTERISTICS ...................................................................................................................................................354 7.3.1 80-System Bus Interface Timing Characteristics (16-/8-bits Transfer Mode) ..................................................................354 7.3.2 80-System Bus Interface Timing Characteristics (1 transfer per pixel) ...........................................................................355 7.3.3 80-System Bus Interface Timing Characteristics (2 or 3 transfer per pixel)....................................................................355 7.3.4 MDDI Interface Characteristics ......................................................................................................................................358 7.3.5 MIPI Interface Characteristics ........................................................................................................................................359 7.3.6 RGB Interface Characteristics ......................................................................................................................................... 363 7.3.7 Reset Timing Characteristics............................................................................................................................................ 364 7.3.15 Liquid Crystal Driver Output Characteristics ...............................................................................................................365 8.1 CONNECT EXAMPLE WITH EXTERNAL COMPONENTS............................................................................................................ 368 8.2 POWER SCHEME.....................................................................................................................................................................370 8.3 MAXIMUM SERIES RESISTANCE .............................................................................................................................................371 9. CHIP INFORMATION............................................................................................................................................372 9.1 CHIP INFORMATION.........................................................................................................................................................372 9.1.1 CHIP OVERVIEW............................................................................................................................................................ 372 2012/05/11 5 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 9.1.2 APPLICATION CIRCUIT .......................................................................................................................................................373 9.2 BUMP INFORMATION ......................................................................................................................................................375 9.2.1 Input PAD Format ............................................................................................................................................................ 375 9.2.2 Output PAD Fotmat..........................................................................................................................................................376 9.2.3 Alignment Mark Information............................................................................................................................................ 377 9.3 PAD COORDINATES ..........................................................................................................................................................378 9.3.1 For Panel Resolution: 320(RGB)*480 ............................................................................................................................ 378 9.4 SELECTION GUIDE ...........................................................................................................................................................391 2012/05/11 6 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Reversion History Version Contents 0.00 - Initial Version - Modified MTP 1time(page 10, 182 ,184 ) - Modified DCX Pad type (page16) - Modified TE1/IDLE_ON description(page 18) - Modified VGL description (page 20) - Modified MIPI command table (page 108) - Modified RTN description(page 174) - Add SRE in 55h&56h (page 255-257) - SET_MIPI_MDDI change address to 8Fh (page192, 277) - Add STB EDGE TIMING CTRL(AEh) (page 192,284) - Add IDLEMODE_BL Control(E1,E2h) (page 192,290,291) - Add WRALS(E3h)(page 194, 292) - Add RDALS(E4h)(page 194, 293) - Change switch page flow, add command2_P0,commandP1(page 294~296) - Add command2_P0 table (page297) - Modified B2h default value, min RTN=123 (page 304,305) 0.01 - Add LPM_HZ &TE1_ON of B3h (page 307) - Modified interval scan for B5h (page 309) - Add SDT & EQI of B6h (page 311) - Add VGSP & VGSN of C0h (page321-327) - Modified C2h VGL pump setting (page 329) - Change sunlight Hystersis Curve to command2_P0 of E0h (page 346) - Add command2_P0 table (page351) - Add setting gamma command (page 359-376) - Modified DC Characteristics follow nokia spec (page 378) - Remove 70~7Eh - Add CVSS - Remove B8h’s SMX,SMY - Modified 36h note description. (page 233) - Add VGH&VGL clamp command of C6h(page 320) - Modified 3Bh default value. - Add gamma default value. - Add 8-8-8 format for MIPI interface (page133,162~165) - Modified B1h default value.(page273,277) - Modified Command2_P0 register table(page273~274) - Modified Command2_P1 register table(page.319~325) - Add MDDI IF 8-8-8 format(page65,66) - Modify SPI IF SDA pin description(page14) - Modify MTP Flow(page178~182) - Modify components table(page 361~ 364) 0.02 - Modify application circuit(pag 368,369) - Modify 7.2.4MIPI DC characteristics voltage(page 348) - Add Differential input voltage in 7.1Absolute Maximum Ratings(page 345) - Add TESTM,OSC test pin in 4.10 Test Pins description (page 18) -Modify A1h parameter and description(page190, 257) -Modify A8h parameter and description(page 190,258) -Remove SRE in 55h and 56h(page251,252) -Modify D5h parameter(page274, 311) -Modify case1&case2 components table(page361,362) 0.03 -Modify Application circuit for case1 and case2 (page366~369) -Modify CRL and DSIN description (page282) Prepared Checked Approved by by by Date Connie Charley Max 2011/11/04 Connie Charley 2011/12/12 Connie Charley 2012/02/09 Connie Charley 2012/05/09 2012/05/11 7 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Version Contents -Add CABC description (page170) -Modify MDDI AC timing unit(page358) -Modify C1h’s pump mode description (page302) -Modify VGSN,VGSP range(page300) -Modify MIIPI UIINST(page 359) -Modify 3Bh note(pgae 245) -Modify NT35310H-DP&NT35310H-DP01 (page 372,378) -Add SELECTION GUIDE(page 391) 0.04 -Modify MIPI THS-EXIT(page361) -Add description on MIPI TCLK-POST (page 362) NT35310 Prepared Checked Approved by by by Date Connie Charley 2012/05/10 2012/05/11 8 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 1. General Description 1.1 Purpose of this Document This document has been created to provide complete reference specifications for the NT35310. IC design engineers should refer to these specifications when designing ICs, test engineers when testing the compliance of manufactured ICs to guarantee their performance, and application engineers when helping customers to make sure they are using this IC properly. 1.2 General Description NT35310 is a single chip low power LCD controller/driver for 262K color a-Si TFT-LCD -LCD displays of 480 gates and 320xRGB columns. It has a 345600 bytes display RAM and a full set of control functions. The NT35310 supports Mobile Display Digital Interface(MDDI), MIPI Interface, RGB interface, 8/9/16/18-bits 80 system interfaces and serial peripheral interfaces (SPI) interface. The specified window area can be updated selectively, so that moving pictures can be displayed simultaneously independent of the still picture area. The NT35310 is also able to make gamma correction settings separately for RGB dots to allow adjustments to panel characteristics, resulting in higher display qualities. The IC possesses internal GRAM that stores 320-RGB x 480-dot 262K-color images, as well as internal boosters that generate the LCD driving voltage, breeder resistance and voltage follower circuit for the LCD driver. A deep standby mode is also supported for lower power consumption. The NT35310 also supports CABC function for the backlight control. It’s able to reduce the total power consumption of display module significantly. 2012/05/11 9 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 2. Features  Single chip a-Si TFT LCD driver-TFT-LCD Controller/ driver with Display RAM.  Display Resolutions  320RGB x 480 (HVGA)  Display Data Memory: 345600 bytes.  Display Modes  Full color: 262K-colors  Reduced color: 65K-colors  Idle mode: 8-colors  Interfaces  8-bits, 9-bits, 16-bits or 18-bits interfaces with 80-series MPU  Serial Peripheral Interface (SPI)  16-bits, 18-bits RGB interface  Mobile Display Digital Interface (MDDI 1.2 Type-1)  MlPI DSI Interface (D-PHY: V1.00.00 , DSI:1.01.00 R11, DCS:1.01.00, 1 data lane)  Display Features  High-speed RAM write function  Window address functions for specifying a rectangular area on the internal RAM to write data  Individual gamma correction setting for RGB dots  Deep standby function. 2012/05/11 10 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version  On chip  DC/DC converter  VCOM voltage generator (Dot inversion)  Provide MTP (1 times) to store related Power and gamma setting related registers  Provide MTP (4 times) to store VCOM,ID1, ID2 and ID3.  Oscillator for display clock generation  On module checksums checking  Image Enhancement Technology  Content Adaptive Backlight Control (CABC) Function  Histogram analysis & data process  Moving picture auto-detect mode.  Dimming control.  Supported in full display mode.  Driving Algorithm  Support 1 dot inversion, 2 dot inversion, 4 dot inversion, column inversion driving.  Supply Voltage Range  I/O supply voltage range for VDDI to VSS: 1.65V to 3.3 V  Analog supply voltage range VCI to AVSS: 2.3V to 3.3 V NT35310 2012/05/11 11 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310  Output Voltage Level  Positive Power supply for driver circuit range(AVDD): AVDD-AVSS = 2 x VCI,3 x VCI  Negative Power supply for driver circuit range(AVEE): AVEE-AVSS = -AVDD  Positive polarity Source output high voltage level: GVDDP = 3V to 5.5V (12.5mV/step , AVDD-GVDDP>0.25V)  Negative polarity Source output high voltage level: GVDDN= -3V to -5.5V (12.5mV/step , AVEE-GVDDN<-0.25V)  Common electrode output voltage level: VCOM = 0V, -0.2V to -3V (12.5mV/step , AVEE-VCOMDC<-0.25V)  Positive gate driver output voltage level: VGH-AVSS = 11V to 18V (VCI x4, x5, x6)  Negative gate driver output voltage level: VGL-AVSS = -18V to -7.5V (-VCIx3, x4, x5, x6) 2012/05/11 12 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 3. Block Diagram Draft Version NT35310 BIAS Gamma Generator GVDDP GVDDN Backlight Control 960 Source buffer D / A Converter Level Shift Data Latch 480 Gate buffer Level Shift Shift Register CABC Display Data RAM Address Counter RAM Data Generator MTP Instruction Control Oscillator Gate Output Generator VCOM generator LDO Charge Pump 1 Charge Pump ﴾ 2 & 3﴿ Charge Pump 5 Figure 3.1 Block Diagram 2012/05/11 13 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 4. Pin Descriptions 4.1 Power Inputs Symbol VCI VDDI VLPH VSS AVSS CVSS MTP_PWR Draft Version NT35310 Pad Type Power Supply Power Supply LDO Output Power Ground Power Ground Power Ground Power input Description Power supply to the liquid crystal power supply analog circuit. Connect VCI to an external power supply (VCI = 2.3V to 3.3). Power supply to the I/O. VDDI = 1.65V to 3.3V. LDO output for MIPI TX use (LPDT). Connect a capacitor to stabilize output voltage. Leave it open if MIPI interface is not used. Ground for the digital logic. VSS = 0V Ground for the analog unit (regulator, liquid crystal power supply circuit). AVSS = 0V. In case of COG, connect AVSS to VSS on the FPC to prevent noise. Ground for Charge pump.Please connect to VSS. -Input power for NV memory programming. -Input power range: 7.5V -When not under programming, MTP_PWR pin can be floating or tied to ground. 4.2 MCU System Interface Symbol Pad Type DCX Digital Input (VDDI) WRX/ SCL Digital Input (VDDI) RDX Digital Input (VDDI) CSX Digital Input (VDDI) D0 to D17 Digital I/O (VDDI) Description Data or Command selection pin in MCU parallel Interface Low: Index register High: Control register If not used, please pull it to VDDI. -Writes strobe signal to write data when WRX is Low in CPU system bus interface operation . -Read or write operation in CPU system bus interface. -If not used, please pull it to VDDI. -Reads strobe signal to read out data when RDX is Low in 80-system bus interface operation. -Read or write operation in CPU system bus interface. -If not used, please pull it to VDDI. Chip select input pin of NT35310. Low: Selected (accessible) High: Unselected (not accessible) If not used, please pull it to VDDI. -18-bits bi-directional data bus for CPU system interface. -8-bits interface: D7-0 are used (Un-used pin should connect to VSS level.) -9-bits interface: D8-0 are used (Un-used pin should connect to VSS level.) -16-bits interface: D15-0 are used (Un-used pin should connect to VSS level.) 2012/05/11 14 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 4.3 SPI Interface Symbol CSX WRX/SCL DIN_SDA DOUT DCX Draft Version NT35310 Pad Type Digital Input (VDDI) Digital Input (VDDI) Digital I/O (VDDI) Digital Output (VDDI) Digital Input (VDDI) Description Chip select input pin of NT35310. Low: Selected (accessible) High: Unselected (not accessible) If not used, please pull it to VDDI. -WRX: Write enable in the 8080-MCU parallel interface operation. -SCL: A synchronous clock signal in serial interface operation. Serial input signal in serial I/F mode. Note 1:If not in use, please fix this pin at VSS level. Serial data output. If SDA_EN=0, DOUT is not use. If SDA_EN=1, DOUT is serial data output. Let it to open in MPU interface mode. Used in 8-bits SPI for Data / Command Selection pin If not used, please fix this pin at VDDI level. 4.4 RGB Interface Symbol DE PCLK HS VS D0~ D17 Pad Type Digital Input (VDDI) Digital Input (VDDI) Digital Input (VDDI) Digital Output (VDDI) Digital Output (VDDI) Description Data enable signal in RGB I/F mode. If not used, please fix this pin at VSS level. Pixel clock signal in RGB I/F mode If not used, please fix this pin at VSS level. Horizontal sync. signal in RGB I/F mode If not used, please fix this pin at VDDI level. Vertical sync. signal in RGB I/F mode. If not used, please fix this pin at VDDI level. 18-bits data bus for RGB I/F mode. Data bus is share with 80 -system interface. If not used, please fix this pin at VSS level. 2012/05/11 15 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 4.5 MDDI / MIPI Interface Symbol HSSI_CLK_P/N HSSI_D0_P/N Pad Type MDDI / MIPI Input MDDI / MIPI Input/Output Description -STB+/- signal line in MDDI I/F or DSI_CLK+/- in MIPI I/F. -HSSI_CLK_P/N are differential small amplitude signals. Ensure the trace length is shortest so that the COG resistance is less than 10 ohm. -Please pull it to VSS level if NOT used. -MDDI / MIPI positive and negative data signal line. -HSSI_D0_P/N are differential small amplitude signals. Ensure the trace length is shortest so that the COG resistance is less than 10 ohm. -Please pull it to VSS level if NOT used. 4.6 CABC Control Pins Symbol Pad Type LEDPWM1 LEDPWM 2 Digital Output (VDDI –VSS or Hi-Z) Description This pin is connected to the external LED driver - PWM type control signal for brightness of the LED backlight - The width of this LEDPWM signal is set from 256 values between 0% (LOW) and 100% (HIGH) - This pin can be set to Hi-impedance output by LEDPWM_OEB bits. -If not used, please open this pin 2012/05/11 16 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 4.7 Interface Logic Pins Symbol IM2-0 TE TE1/IDLE_ON RESX Pad Type Digital Input (VDDI) Digital Output (VDDI –VSS) Digital Output (VDDI –VSS) Description Selects the interface to MPU (VDDI-VSS amplitude signal). IM2 IM1 IM0 Interface Selection 0 0 0 80-system, 18-bits interface 0 0 1 80-system, 9-bits interface 0 1 0 80-system, 16-bits interface Data Pins D17-0 D8-0 D15-0 Available Colors 262k 262k 65k, 262k 0 1 1 80-system, 8-bits interface D7-0 65k, 262k 1 0 0 MDDI+ 9bits serial interface HSSI_D0_P/N 65k, 262k 101 9bits serial interface+ RGB interface DIN_SDA,DOUT 65k, 262k 110 MIPI HSSI_D0_P/N 65k, 262k 111 8bits serial interface+ RGB interface DIN_SDA, DOUT,DCX 65k, 262k -Frame head pulse signal. Utilize this signal when synchronizing RAM data write operations. - VDDI is the Power supply for FTE pin output buffer. please connect VDDI to suitable level. -If not used, please open this pin - TE1 is used for noise sensing of touch panel (Generating a pulse output per scan line from NT35310). - IDLE_ON is used for IDLE mode BL control. -Please used command LPM_HZ &TE1_ON to select the pin function. Digital Input (VDDI) -This signal will reset the device and must be applied to properly initialize the chip. Signal is active Low. -There is no internal pull high resistor for this pin. 2012/05/11 17 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 4.8 Display Driver Analog Outputs Symbol VCOM AVDD AVEE VGLO S0 to S959 G0 to G479 Pad Type Description LCD Output Power output Power output Analog Output Source Output Gate Output VCOM output voltage for DC VCOM mode. Positive Power supply to the source and VCOM drive. Negative Power supply to the source and VCOM drive. VGLO output from charge pump (please connect to VGL on panel) Liquid crystal application voltage output lines. Gate driver output pins. 2012/05/11 18 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 4.9 Power Supply Symbol VDD VGH VGL VCL C11P/C11M C12P/C12M C21P/C21M C22P/C22M C13P/C13M GVDDP GVDDN VREF Draft Version NT35310 Pad Type Description Power Supply Charge Pump Output Power supply to the internal logic regulator circuit. VDD = 1.5V (Typical). Output voltage from the step-up circuit, generated from AVDD. IC substrate input Please connect to VGLO pad. Charge Pump Output Analog Output Analog Output Analog Output LDO Output LDO Output LDO Output Output voltage from the step-up circuit, generated from VCI. VCL = - VCI1 Capacitor connection pins for the step-up circuit 1 which generate AVDD and VCL. Capacitor connection pins for the step-up 5 circuit which generate AVEE. Capacitor connection pins for the step-up 2,3 circuit which generate VGH and VGL. Positive voltage level generated from AVDD. LDO output for positive gray scale voltage generator. Negative voltage level generated from AVEE. LDO output for negative gray scale voltage generator. Reference voltage output from the internal reference voltage generating circuit. 4.10 Test Pins (Test and Dummy Pins) Symbol Pad Type Description TESTM Digital Input Test pin not accessible to user.Please connect to VSS or let it open. OSC Digital Input Test pin not accessible to user.Please connect to VSS or let it open. VSS_DUM - Please let this pin Hiz or connect to VSS. Dummy FRM - These pins are dummy (possess no function inside) Dummy pin not accessible to user; must be let it open. This pin can select the free running mode for burn-in test. The display data alternates between full black and full white independent of Digital Input input data in free running mode. (VDDI) - FRM = ’0’, Normal operation mode - FRM = ’1’, Free running mode If it is not in use, keep it at VSS level. 2012/05/11 19 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5. Function Descriptions 5.1 MPU Interface The NT35310 provides several types of MPU interfaces at high speed. However, if the interface cycle time is faster than the limit, the external MPU needs to have dummy wait(s) to meet the limit of the interface cycle time. User can read / write the registers or RAM via these MPU interfaces. Interface type can be selected by setting the IM2 / IM1 / IM0 pins. IM2 IM1 IM0 System Interface Data Pins 0 0 0 80-System 18-bits Interface D[17 : 0] 0 0 1 80-System 9-bits Interface D[8 : 0] 0 1 0 80-System 16-bits Interface D[15 : 0] 0 1 1 80-System 8-bits Interface D[7 : 0] 1 0 0 MDDI+9bits serial interface HSSI_D0_P/N for MDDI I/F 1 0 1 9bits serial interface + RGB DIN_SDA,DOUT 1 1 0 MIPI Interface HSSI_D0_P/N 1 1 1 8bits serial interface DIN_SDA,DOUT and DCX Table 5.1.1 Interfaces of NT35310 Available Colors 262k 262k 65k, 262k 65k, 262k 65k, 262k 65k, 262k 65k, 262k 65k, 262k 2012/05/11 20 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.1.1 General Protocol For programming of the LCD driver, the general supported protocol is shown in Fig. 5.1.1 NT35310 Figure 5.1.1 Programming Protocol 5.1.2 80-System Interface The MCU uses 11-wires 8-bits-data, 12-wires 9-bits-data, 19-wires 16-bits-data and 21-wires 18-bits-data parallel interface. The chip-select CSX (active low) enables and disables the parallel interface. WRX is the parallel data write, RDX is the parallel data read and D[17 : 0] is parallel data. The Graphics Controller Chip reads the data at the rising edge of WRX signal. The DCX is the data/command flag. When DCX = '1', D[17 : 0] bits are display RAM data or command parameters. When DCX = '0', D[17 : 0] bits are commands. The 8080-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. Interface bus width can be selected by setting IM2, IM1 and IM0 as following table. IM2 IM1 IM0 Interface DCX RDX WRX Function Description 0 1 ↑ Write 8-bits command (D7 to D0) 0 1 1 8-bits Parallel 1 1 ↑ Write 16/18-bits display data or 8-bits parameter (D7 to D0) 1 ↑ 1 Read 16/18-bits Display data (D7 to D0) 1 ↑ 1 Read 8-bits parameter or status (D7 to D0) 0 1 ↑ Write 8-bits command (D7 to D0) 1 0 0 1 9-bits Parallel 1 ↑ Write 18-bits display data (D8 to D0) Write 8-bits parameter (D7 to D0) 1 ↑ 1 Read 18-bits Display data (D8 to D0) 1 ↑ 1 Read 8-bits parameter or status (D7 to D0) 0 1 ↑ Write 8-bits command (D7 to D0) 1 0 1 0 16-bits Parallel 1 ↑ Write 16/18-bits display data (D15 to D0) Write 8-bits parameter (D7 to D0) 1 ↑ 1 Read 16/18-bits Display data (D15 to D0) 1 ↑ 1 Read 8-bits parameter or status (D7 to D0) 0 1 ↑ Write 8-bits command (D7 to D0) 1 0 0 0 18-bits Parallel 1 ↑ Write 18-bits display data (D17 to D0) Write 8-bits parameter (D7 to D0) 1 ↑ 1 Read 18-bits Display data (D17 to D0) 1 ↑ 1 Read 8-bits parameter or status (D7 to D0) Table 5.1.2 The Function of 80-Series System Interface 2012/05/11 21 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.1.2.1 Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control lines (DCX, RDX, WRX) and data signals (D[17 : 0]). DCX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low ( = ’0’) and vice versa it is data ( = ’1’). The data length of each command is 16-bits (2-Bytes) WRX D[ 17 : 0] The host starts to control The display writes D [ 17 : 0 ] D[ 17 : 0 ] lines when there lines when there is a rising is a falling edge of the WRX edge of the WRX Figure 5.1.2 80-Series WRX Protocol The host stops to control D [ 17 : 0 ] lines 1- Byte Command 2- Bytes Command (n-1 ) Bytes Command ( The number of parametenr -1) S CMD CMD PA 1 CMD PA 1 PA 2 PAn-2 PAn-1 P CSX DCX RDX WRX D[ 17 : 0] Host- D[ 17 : 0] (MPU to LCD Driver) LCD Driver - D[ 17 : 0] (LCD Driver to MPU) CMD CMD PA 1 CMD PA 1 PA 2 CMD CMD PA 1 CMD PA 1 PA 2 Hi-Z Hi-Z Hi-Z Hi-Z PAn-2 PA n-1 PAn-2 PA n-1 Hi-Z CMD : Write Command Code PA: Write Parameter or RAM Data Signals on D [ 17 : 0] , DCX, RDX, and WRX pins during CSX =“ H” are ignored. Figure 5.1.3 80-Series Parallel Bus Protocol for Register or RAM Write 2012/05/11 22 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.1.2.2 Read Cycle Sequence The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The display sends data (D[17 : 0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. RDX D[ 17 : 0] The display starts to control The host reads D [ 17 : 0 ] D[ 17 : 0 ] lines when there is lines when there is a rising a falling edge of the RDX edge of the RDX Figure 5.1.6 80-Series RDX Protocol The display stops to control D [ 17 : 0 ] lines Read Parameter S CMD DM PA Read Display RAM Data CMD DM PX 1 PX 2 PX n-2 PX n-1 P CSX DCX RDX WRX D[ 17 : 0] S CMD Host- D[ 17 : 0] (MPU to LCD Driver) S LCD Driver - D[ 15 : 0] (LCD Driver to MPU) CMD Hi-Z DM PA Hi-Z Hi-Z DM PA CMD DM PX1 PX2 Hi-Z CMD Hi-Z Hi-Z Hi-Z DM PX1 PX2 Hi-Z Hi-Z PXn-2 PXn-1 Hi-Z Hi-Z Hi-Z PXn-2 PXn-1 Hi-Z CMD: Write Command Code PA: Read Parameter PX: Read RAM Data DM: Dummy Read Signals on D [ 17 : 0] , DCX, RDX, and WRX pins during CSX=“ H” are ignored . Figure 5.1.7 80-Series Parallel Bus Protocol for Register or RAM Read Note: One dummy read is required in read register and display RAM data. 2012/05/11 23 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.2 SPI Interface 5.2.1 General Description for LoSSI The Module uses a 9-bits serial interface (LoSSI). The chip-select CSX (active low) enables and disables the serial interface. RESX (active low) is an external reset signal. SCL is the serial data clock and SDA is serial data. Serial data must be input to SDA in the sequence D/CX, D7 to D0. The Graphics Controller Chip reads the data at the rising edge of SCL signal. The first bit of serial data D/CX is data/command flag. When D/CX = "1", D7 to D0 bit are display RAM data or command parameters. When D/CX = "0" D7 to D0 bit are commands. SCL is not a continuous clock and it can be stopped by the host CPU when SCL is low or high after a rising edge of SCL for D0 in the writing mode. SCL and SDA can be high or low when there is a falling or rising edge of the CSX. The 8bits serial mode consists of the Data/Command selection input (D/CX), chip enable input (CSX), the serial clock input (SCL) and serial data Input/Output (SDA) for data transmission. The data bus (D [17:0]) which are not used, must be leave these unused pins to open. Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. 5.2.2 Command Write for LoSSI The host CPU drives the CSX pin low and starts by setting the D/CX-bit on SDA. The bit is read by the display on the first rising edge of SCL. On the next falling edge of SCL the MSB data bit (D7) is set on SDA by the CPU. On the next falling edge of SCL the next bit (D6) is set on SDA. This continues until all 8 Data bits have been transmitted as shown in Figure 33: Command Write. CSX SDA SCL Command Command or parameter 0 D7 D6 D5 D4 D3 D2 D1 D0 D/CX D7 D6 D5 D4 D3 D2 D1 D0 Command Write for 9bits SPI CSX SDA SCL DCX Command Command or parameter 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Command Write for 8bits SPI 5.2.3 Read Functions for LoSSI 8-bits Reading Function Without Including Dummy Clock Cycle Reading Commands 05h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh,DAh, DBh, DCh CSX Host SCL MPU SDA Driver LCD SDA Read Command ID data Hi-z 0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-z D7 D6 D5 D4 D3 D2 D1 D0 Next Command 0 D7 D6 D5 D4 D3 D2 D1 D0 MCU Data Tx Start LCD Data Tx Start MCU Data Tx Start Command Read for 9bits SPI 2012/05/11 24 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Command Read for 8bits SPI 24-bits Reading Function With Including Dummy Clock Cycle Reading Command 04h Dummy Clock Cycle CSX Read Command ID data Host SCL MPU SDA Driver LCD SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-z D23 D22 D21 Hi-z D2 D1 D0 Next Command 0 D7 D6 D5 D4 D3 D2 D1 D0 MCU Data Tx Start LCD Data Tx Start MCU Data Tx Start Command Read for 9bits SPI CSX Host SCL MPU SDA Driver LCD SDA DCX Read Command Dummy Clock Cycle ID data 0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-z 0 D23 D22 D21 Hi-z D2 D1 D0 Next Command 0 D7 D6 D5 D4 D3 D2 D1 D0 0 MCU Data Tx Start LCD Data Tx Start MCU Data Tx Start Command Read for 8bits SPI Note: ID Data length is 24bits. 5.2.4 Display Module Data Transfer Recovery for LoSSI If there is a break in data transmission while transferring command, Frame Memory Data or Multiple Parameter command Data, before a whole byte has been completed, then the Display Module will have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example: CSX Command/Parameter Break Command or parameter Host SDA D/CX D7 D6 D5 D4 D/CX D7 D6 D5 D4 D3 D2 D1 D0 SCL LoSSI and Break If a 1 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than retransmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown: 1. Middle of frame 2012/05/11 25 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Break NT35310 Command Parameter 1 Store to register Parameter 2 The old value is kept on the register Command 2. Between frames Without break Command Parameter 1 Parameter 2 Parameter 3 With break Ignored parameter Command Parameter 1 Store to register Parameter 2 The old value is kept on the register Break Command 2 LoSSI and Break During Parameter Note: Break can be e.g. another command or noise pulse. Parameter 3 The old value is kept on the register Parameter for Command 2 2012/05/11 26 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.2.5 Display Module Data Transfer Pause for LoSSI It will be possible when transferring Frame Memory Data, Command or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of Frame Memory Data, Command or Multiple Parameter Data has been completed, then the Display Module will wait and continue the Frame Memory Data, Command or Parameter Data Transmission from the point where it was paused as shown below: CSX Command/Parameter Break Command or parameter Host SDA D4 D3 D2 D1 D0 D/CX D7 D6 D5 D4 D3 D2 D1 D0 SCL LoSSI and Pause There are 4 cases where there is possible to see this kind of pause: 1) Command – Pause – Command 2) Command – Pause – Parameter 3) Parameter – Pause – Command 4) Parameter – Pause – Parameter 2012/05/11 27 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.2.6 Display Module Data Transfer Modes for LoSSI The Module has 2 kinds of color modes for transferring data to the display RAM. These are 16-bits color per pixel and 18-bits color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. 5.2.6.1 Method 1 The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. Figure: Data Transfer Method 1 5.2.6.2 Method 2 Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Figure: Data Transfer Method 2 with “Any Command” Break Figure: Data Transfer Method 2 with “Start Frame Memory Write” Break Note: (1) These apply to all Data Transfer Color modes on both Serial and Parallel interfaces. (2) The Frame Memory can contain both odd and even number of pixels for both Methods. Only complete pixel data will be stored in the Frame Memory. (3) “Any Command” can be as same as “Start Frame Memory Write” (4) “Memory Write Continuously (3Ch)” or ” Memory Read Continuously (3Eh)” commands are not stopping writing or reading to/from the frame memory. These commands can be used if there is wanted to continue the writing or reading to/from the frame memory when “Any command” has stopped the memory writing or reading. 2012/05/11 28 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3 Display Data Ram (DDRAM) The NT35310 has an integrated 320x480x18-bits graphic type static RAM. This 345600-bytes memory allows to store a 320xRGBx480 image with 18-bits resolution (262K-color) on-chip. There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. Figure 5.2.1 Display Data RAM 2012/05/11 29 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.1 Serial Interface for DATA RAM write Different display data formats are available for four colors depth supported by the LCM listed below: - 65k colors, RGB 5, 6, 5-bits pixel data input. - 262k colors, RGB 6, 6, 6-bits pixel data input. Figure 5.3.1: Write Image Data with RGB 5, 6, 5-bits Pixel Format via SPI Figure 5.3.2 : Write Image Data with RGB 6, 6, 6-bits Pixel Format via SPI 2012/05/11 30 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.2 8-Bits Parallel Interface for RAM Data Write Different display data formats are available for three colors depth supported by the NT35310 listed below. - 65k colors, RGB 5, 6, 5-bits pixel data input. - 262k colors, RGB 6, 6, 6-bits pixel data input. Register Command D[17 : 8] X D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 0 0 Register 2Ch 3Ah D[17 : 8] D7 D6 D5 D4 D3 D2 D1 D0 Color Depth x R4 R3 R2 R1 R0 G5 G4 G3 65k - Colors 05h x G2 G1 G0 B4 B3 B2 B1 B0 (1-pixels / 2-transfer) x R5 R4 R3 R2 R1 R0 x x 06h x G5 G4 G3 G2 G1 G0 x x x B5 B4 B3 B2 B1 B0 x x Note. ‘x‘ = Don't care - Can be set to '0' or '1' Table 5.3.1 The Pixel Data Format via 80-Series 8-bits Parallel Interface 262k - Colors (1-pixels / 3-transfer) 65 k Colors Depth CMDWR 1 st RAM Data Write 2 nd RAM Data Write 3 rd RAM Data Write 4 th RAM Data Write 5 th RAM Data Write 6 th RAM Data Write 7 th RAM Data Write 8 th RAM Data Write D/ CX 0 1 1 1 1 1 1 1 1 D[ 15 :8] X X X X X X X X X D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Frame RAM Write Command Code 1(2 Ch) R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] R2[4] R2[3] R2[2] R2[1] R2[0] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] B2[4] B2[3] B2[2] B2[1] B2[0] R3[4] R3[3] R3[2] R3[1] R3[0] G3[5] G3[4] G3[3] G3[2] G3[1] G3[0] B3[4] B3[3] B3[2] B3[1] B3[0] R4[4] R4[3] R4[2] R4[1] R4[0] G4[5] G4[4] G4[3] G4[2] G4[1] G4[0] B4[4] B4[3] B4[2] B4[1] B4[0] Memory Write - 1st Pixel Data Write (R1 ,G1 ,B1) - 2nd Pixel Data Write (R2 ,G2 ,B2) - 3rd Pixel Data Write(R3 ,G3 ,B3) - 4th Pixel Data Write(R4 ,G4 ,B4) 16-bits Data Format Extends to18- bits Data Format R1[4] R1[3] R1[2] R1[1] R1[0] R1[4] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] B1[4] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] ]G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] Figure 5.3.3 Write RGB 5-6-5-bits Pixel Data via 8-bits Parallel Interface (3Ah = "05h") Note: (1) 2 times transfer is used to transmit 1 pixel data with the 16-bits color depth information. (2) The most significant bits are:Rx4, Gx5 and Bx4. (3) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 31 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 262 k Colors Depth CMDWR 1 1st RAM Data Write 2nd RAM Data Write 3rd RAM Data Write 4th RAM Data Write 5th RAM Data Write 6th RAM Data Write 7th RAM Data Write 8th RAM Data Write D/ CX 0 1 1 1 1 1 1 1 1 D[ 15 : 8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] X Frame RAM Write Command Code 1(2Ch) X R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] X X X G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] X X X B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] X X X R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] X X X G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] X X X B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] X X X R3[5] R3[4] R3[3] R3[2] R3[1] R3[0] X X X G3[5] G3[4] G3[3] G3[2] G3[1] G3[0] X X Memory Write - 1 st Pixel Data Write(R1 , G1 , B1) - 2 nd Pixel Data Write(R2 , G2 , B2) - R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 18-bit Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] [ 5 : 0] Figure 5.3.4 Write RGB 6-6-6-bits Pixel Data via 8-bits Parallel Interface (3Ah = "06h") Note: (1) 3 times transfer is used to transmit 1 pixel data with the 18-bits color depth information. (2) The most significant bits are:Rx5, Gx5 and Bx5. (3) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 32 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.3 9-Bits Parallel Interface (80-system) for RAM Data Write 9-bits parallel interface only support 262k color. - 262k colors, RGB 6, 6, 6-bits pixel data input. Register Command D[17 : 9] x D8 D7 D6 D5 D4 D3 D2 D1 D0 X 0 0 1 0 1 1 0 0 Register 2Ch 3Ah D[17 : 9] D8 D7 D6 D5 D4 D3 D2 D1 D0 Color Depth 06h x R5 R4 R3 R2 R1 R0 G5 G4 G3 262k - Colors x G2 G1 G0 B5 B4 B3 B2 B1 B0 (1-pixels / 2-transfer) Note. ‘x‘ = Don't care - Can be set to '0' or '1' Table 5.3.3 The Pixel Data Format via 80-Series/68-Series 9-bits Parallel Interface Figure 5.3.5 Write RGB 6-6-6-bits Pixel Data via 9-bits Parallel Interface (3Ah = "06h") Note: (1) 2 times transfer is used to transmit 1 pixel data with the 18-bits color depth information. (2) The most significant bits are:Rx5, Gx5 and Bx5. (3) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 33 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.4 16-Bits Parallel Interface for RAM Data Write Different display data formats are available for four colors depth supported by listed below. - 65k colors, RGB 5, 6, 5-bits pixel data input. - 262k colors, RGB 6, 6, 6-bits pixel data input. Register D[17 : 16] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command x XXXXXXXX0 0 1 0 1 1 0 0 Register 2Ch 3Ah D[17 : 16] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Color Depth 05h x R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 65k - Colors x R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x 06h x B5 B4 B3 B2 B1 B0 x x R5 R4 R3 R2 R1 R0 x x 262k - Colors (2-pixels/ 3-transfer) x G5 G4 G3 G2 G1 G0 x x B5 B4 B3 B2 B1 B0 x x Note. ‘x‘ = Don't care - Can be set to '0' or '1' Table 5.3.4 The Pixel Data Format via 80-Series/68-Series 16-bits Parallel Interface 65 k Colors Depth CMDWR1 1 st RAM Data Write 2 nd RAM Data Write 3 rd RAM Data Write 4 th RAM Data Write 5 th RAM Data Write 6 th RAM Data Write 7 th RAM Data Write 8 th RAM Data Write D/ CX 0 1 1 1 1 1 1 1 1 D[ 15] D[ 14] D[ 13] D[ 12] D[ 11] D[ 10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] - Frame RAM Write Command Code 1(2Ch) R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] R2[4] R2[3] R2[2] R2[1] R2[0] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] B2[4] B2[3] B2[2] B2[1] B2[0] R3[4] R3[3] R3[2] R3[1] R3[0] G3[5] G3[4] G3[3] G3[2] G3[1] G3[0] B3[4] B3[3] B3[2] B3[1] B3[0] R4[4] R4[3] R4[2] R4[1] R4[0] G4[5] G4[4] G4[3] G4[2] G4[1] G4[0] B4[4] B4[3] B4[2] B4[1] B4[0] R5[4] R5[3] R5[2] R5[1] R5[0] G5[5] G5[4] G5[3] G5[2] G5[1] G5[0] B5[4] B5[3] B5[2] B5[1] B5[0] R6[4] R6[3] R6[2] R6[1] R6[0] G6[5] G6[4] G6[3] G6[2] G6[1] G6[0] B6[4] B6[3] B6[2] B6[1] B6[0] R7[4] R7[3] R7[2] R7[1] R7[0] G7[5] G7[4] G7[3] G7[2] G7[1] G7[0] B7[4] B7[3] B7[2] B7[1] B7[0] R8[4] R8[3] R8[2] R8[1] R8[0] G8[5] G8[4] G8[3] G8[2] G8[1] G8[0] B8[4] B8[3] B8[2] B8[1] B8[0] Memory Write - 1 st Pixel Data Write(R1 ,G1 ,B1) 2 nd Pixel Data Write(R2 ,G2 ,B2) 3 rd Pixel Data Write(R3 ,G3 ,B3) 4 th Pixel Data Write(R4 ,G4 ,B4) 5 th Pixel Data Write(R5 ,G5 ,B5) 6 th Pixel Data Write(R6 ,G6 ,B6) 7 th Pixel Data Write(R7 ,G7 ,B7) 8 th Pixel Data Write(R8 ,G8 ,B8) 16-bits Data Format Extends to18 - bits Data Format R1[4] R1[3] R1[2] R1[1] R1[0] R1[4] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] B1[4] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] ]G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] Figure 5.3.6 Write RGB 5-6-5-bits Pixel Data via 16-bits Parallel Interface (3Ah = "05h") Note: (1) In one transfer (D15 to D0), 1 pixel data is transmitted with the 16-bits color depth information. (2) The most significant bits are:Rx4, Gx5 and Bx4. (3) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 34 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 262 Colors Depth CMDWR1 1 st RAM Data Write 2 nd RAM Data Write 3 rd RAM Data Write 4 th RAM Data Write 5 th RAM Data Write 6 th RAM Data Write 7 th RAM Data Write 8 th RAM Data Write D/ CX 0 1 1 1 1 1 1 1 1 D[ 15] D[14] D[ 13] D[ 12] D[11] D[ 10] D[9] - R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] x B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] x G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] x R3[5] R3[4] R3[3] R3[2] R3[1] R3[0] x B3[5] B3[4] B3[3] B3[2] B3[1] B3[0] x G4[5] G4[4] G4[3] G4[2] G4[1] G4[0] x R5[5] R5[4] R5[3] R5[2] R5[1] R5[0] x B5[5] B5[4] B5[3] B5[2] B5[1] B5[0] x D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Memory Write Frame RAM Write Command Code 1(2Ch) - x G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] x x - x R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] x x 1 st Pixel Data Write (R1 ,G1 ,B1) x B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] x x 2nd Pixel Data Write(R2 ,G2 ,B2) x G3[5] G3[4] G3[3] G3[2] G3[1] G3[0] x x - x R4[5] R4[4] R4[3] R4[2] R4[1] R4[0] x x 3rd Pixel Data Write (R3 ,G3 ,B3) x B4[5] B4[4] B4[3] B4[2] B4[1] B4[0] x x 4 th Pixel Data Write (R4 ,G4 ,B4) x G5[5] G5[4] G5[3] G5[2] G5[1] G5[0] x x - x R6[5] R6[4] R6[3] R6[2] R6[1] R6[0] x x 5 th Pixel Data Write(R5 ,G5 ,B5) R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] Figure 5.3.7 Write RGB 6-6-6-bits Pixel Data via 16-bits Parallel Interface (3Ah = "06h") Note: (1) 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 18-bits color depth information.. (2) The most significant bits are:Rx5, Gx5 and Bx5. (3) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 35 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.5 18-Bits Parallel Interface for RAM Data Write Different display data formats are available for four colors depth supported by listed below. - 262k colors, RGB 6, 6, 6-bits pixel data input. Register D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command X X X X X X X X X X 0 0 1 0 1 1 0 0 Register 2Ch 3Ah D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 06h R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Note. ‘x‘ = Don't care - Can be set to '0' or '1' Table 5.3.5 The Pixel Data Format via 80-Series/68-Series 18-bits Parallel Interface Color Depth 262k - Colors 262 k Colors Depth CMDWR1 1 st RAM Data Write 2 nd RAM Data Write 3 rd RAM Data Write 4 th RAM Data Write 5 th RAM Data Write 6 th RAM Data Write 7 th RAM Data Write 8 th RAM Data Write D/ CX 0 1 1 1 1 1 1 1 1 D[ 17] R1[5] R2[5] R3[5] R4[5] R5[5] R6[5] R7[5] R8[5] D[16] R1[4] R2[4] R3[4] R4[4] R5[4] R6[4] R7[4] R8[4] D[15] R1[3] R2[3] R3[3] R4[3] R5[3] R6[3] R7[3] R8[3] D[14] R1[2] R2[2] R3[2] R4[2] R5[2] R6[2] R7[2] R8[2] D[13] D[12] - R1[1] R1[0] R2[1] R2[0] R3[1] R3[0] R4[1] R4[0] R5[1] R5[0] R6[1] R6[0] R7[1] R7[0] R8[1] R8[0] D[ 11] G1[5] G2[5] G3[5] G4[5] G5[5] G6[5] G7[5] G8[5] D[10] G1[4] G2[4] G3[4] G4[4] G5[4] G6[4] G7[4] G8[4] D[9] G1[3] G2[3] G3[3] G4[3] G5[3] G6[3] G7[3] G8[3] D[8] G1[2] G2[2] G3[2] G4[2] G5[2] G6[2] G7[2] G8[2] D[7] G1[1] G2[1] G3[1] G4[1] G5[1] G6[1] G7[1] G8[1] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Frame RAM Write Command Code 1(2Ch) G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] G2[0] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] G3[0] B3[5] B3[4] B3[3] B3[2] B3[1] B3[0] G4[0] B4[5] B4[4] B4[3] B4[2] B4[1] B4[0] G5[0] B5[5] B5[4] B5[3] B5[2] B5[1] B5[0] G6[0] B6[5] B6[4] B6[3] B6[2] B6[1] B6[0] G7[0] B7[5] B7[4] B7[3] B7[2] B7[1] B7[0] G8[0] B8[5] B8[4] B8[3] B8[2] B8[1] B8[0] Memory Write - 1 st Pixel Data Write (R1 ,G1 ,B1) 2 nd Pixel Data Write (R2 ,G2 ,B2) 3 rd Pixel Data Write (R3 ,G3 ,B3) 4 th Pixel Data Write (R4 ,G4 ,B4) 5 th Pixel Data Write (R5 ,G5 ,B5) 6 th Pixel Data Write (R6 ,G6 ,B6) 7 th Pixel Data Write (R7 ,G7 ,B7) 8 th Pixel Data Write (R8 ,G8 ,B8) R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] ]G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] [ 5 :0] Figure 5.3.8 Write RGB 6-6-6-bits Pixel Data via 18-bits Parallel Interface (3Ah = "06h") Note: (1) The most significant bits are:Rx5, Gx5 and Bx5. (2) The least significant bits are:Rx0, Gx0 and Bx0. 2012/05/11 36 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.3.6 Serial Interface Signals for RAM Data Read NT35310 Note: when SDA_EN=0,data output in DOUT. Figure 5.3.9 Read RAM Data via SPI 2012/05/11 37 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.7 80-8-bits Parallel Interface Signals for RAM Data Read CSX D/ CX RDX WRX D[7] 0 D[6] 0 D[5] 1 D[4] 0 D[3] 1 D[2] 1 D[1] 1 D[0] 0 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] - G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] - 1 st Pixel B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] - 18 -bit R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] - G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] - 2 nd Pixel B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] - R3[5] R3[4] R3[3] R3[2] R3[1] R3[0] - 3 rd Pixel Frame RAM R1 G1 B1 1 st Pixel R2 G2 B2 2 nd Pixel R3 G3 B3 3 rd Pixel Figure 5.3.10 Read RAM Data via 80-8 bits Parallel Interface 2012/05/11 38 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.3.8 80-9-bits Parallel Interface Signals for RAM Data Read CSX D/ CX RDX WRX D[8] - D[7] 0 D[6] 0 D[5] 1 D[4] 0 D[3] 1 D[2] 1 D[1] 1 D[0] 0 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] 1 st Pixel R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] 2 nd Pixel 18 -bit NT35310 R3[5] R3[4] R3[3] R3[2] R3[1] R3[0] G3[5] G3[4] G3[3] G3[2] G3[1] G3[0] B3[5] B3[4] B3[3] B3[2] B3[1] B3[0] 3 rd Pixel Frame RAM R1 G1 B1 1 st Pixel R2 G2 B2 2 nd Pixel R3 G3 B3 3 rd Pixel Figure 5.3.11 Read RAM Data via 80-9 bits Parallel Interface 2012/05/11 39 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.3.9 80-16-bits Parallel Interface Signals for RAM Data Read CSX D/ CX RDX WRX D[15] - Dummy R1[5] B1[5] G2[5] R3[5] D[14] - Dummy R1[4] B1[4] G2[4] R3[4] D[13] - Dummy R1[3] B1[3] G2[3] R3[3] D[12] - Dummy R1[2] B1[2] G2[2] R3[2] D[11] - Dummy R1[1] B1[1] G2[1] R3[1] D[10] - Dummy R1[0] B1[0] G2[0] R3[0] D[9] - Dummy - - - - D[8] - Dummy - - - - D[7] 0 Dummy G1[5] R2[5] B2[5] G3[5] D[6] 0 Dummy G1[4] R2[4] B2[4] G3[4] D[5] 1 Dummy G1[3] R2[3] B2[3] G3[3] D[4] 0 Dummy G1[2] R2[2] B2[2] G3[2] D[3] 1 Dummy G1[1] R2[1] B2[1] G3[1] D[2] 1 Dummy G1[0] R2[0] B2[0] G3[0] D[1] 1 Dummy - - - - D[0] 0 Dummy - - - - 1 st Pixel 2 nd Pixel 3 rd Pixel 18-bit NT35310 B3[5] B3[4] B3[3] B3[2] B3[1] B3[0] R4[5] R4[4] R4[3] R4[2] R4[1] R4[0] - G4[5] G4[4] G4[3] G4[2] G4[1] G4[0] B4[5] B4[4] B4[3] B4[2] B4[1] B4[0] - 4 th Pixel Frame RAM R1 G1 B1 R2 G2 B2 R3 G3 B3 1 st Pixel 2 nd Pixel 3 rd Pixel Figure 5.3.12 Read RAM Data with 6-6-6-bits Pixel Format via 80-16 bits Parallel Interface 2012/05/11 40 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.3.10 80-18-bits Parallel Interface Signals for RAM Data Read NT35310 CSX D/ CX RDX WRX D[17] - Dummy R1[5] R2[5] R3[5] R4[5] R5[5] D[16] - Dummy R1[4] R2[4] R3[4] R4[4] R5[4] D[15] - Dummy R1[3] R2[3] R3[3] R4[3] R5[3] D[14] - Dummy R1[2] R2[2] R3[2] R4[2] R5[2] D[13] - Dummy R1[1] R2[1] R3[1] R4[1] R5[1] D[12] - Dummy R1[0] R2[0] R3[0] R4[0] R5[0] D[11] - Dummy G1[5] G2[5] G3[5] G4[5] G5[5] D[10] - Dummy G1[4] G2[4] G3[4] G4[4] G5[4] D[9] - Dummy G1[3] G2[3] G3[3] G4[3] G5[3] D[8] - Dummy G1[2] G2[2] G3[2] G4[2] G5[2] D[7] 0 Dummy G1[1] G2[1] G3[1] G4[1] G5[1] D[6] 0 Dummy G1[0] G2[0] G3[0] G4[0] G5[0] D[5] 1 Dummy B1[5] B2[5] B3[5] B4[5] B5[5] D[4] 0 Dummy B1[4] B2[4] B3[4] B4[4] B5[4] D[3] 1 Dummy B1[3] B2[3] B3[3] B4[3] B5[3] D[2] 1 Dummy B1[2] B2[2] B3[2] B4[2] B5[2] D[1] D[0] 1 Dummy B1-[1] B2-[1] B3-[1] B4-[1] B5-[1] 0 Dummy B1-[0] B2-[0] B3-[0] B4-[0] B5-[0] 1 st Pixel 2 nd Pixel 3 rd Pixel 4 th Pixel 5 th Pixel 18-bit Frame RAM R1 G1 B1 R2 G2 B2 R3 G3 B3 1 st Pixel 2 nd Pixel 3 rd Pixel Figure 5.3.13 Read RAM Data with 6-6-6-bits Pixel Format via 80-18 bits Parallel Interface 2012/05/11 41 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.4 RGB Interface 5.4.1 General Description The module uses16- and 18- bits parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. 16-bits parallel RGB interface only support 65k color depth (R3A00h = 0050h), 18-bits parallel RGB interface only support 262k color depth (R3Ah = 60h). Beside these setting, other mode is setting inhibits. Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. sleep in mode etc. Vertical synchronization (VS) is used to show when there is received a new frame of the display. This is negative (‘0’, low) active and its state is read to the display module by a rising edge of he PCLK signal. Horizontal synchronization (HS) is used to show when there is received a new line of the frame. This is negative (‘0’, low) active and its state is read to the display module by a rising edge of the PCLK signal. Data Enable (DE) is used to show when there is received RGB information that should be transferred on the display. This is a positive ( ‘1’, high) active and its state is read to the display module by a rising edge of the PCLK signal. D[17:0] are used to show what is the information of the image that is transferred on the display (When DE= ’1’ and there is a rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a rising edge of the PCLK signal. The PCLK cycle is described in the following figure. PCLK VS, HS, DE, D[ 17 : 0] The host changes D[ 17 : 0] , VS, HS, and DE lines when there is a falling edge of the PCL.K The driver IC reads the D [ 17 : 0] , VS, HS, and DE lines when there is a rising edge of the PCL. K Figure 5.4.1 PCLK cycle Note: PCLK is an unsynchronized signal (It can be stopped). 2012/05/11 42 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.4.2 General Timing Diagram In normal operation, host processor should continuously provide complete frames of image data at a sufficient frame rate to avoid flicker or other visible artifacts. The display image, or frame, is comprised of a rectangular array of pixels. The frame is transmitted from the host processor to a display module as a sequence of pixels. With each horizontal line of the image data sent as a group of consecutive pixels. Vsync indicated the beginning of each frame of the displayed image. Hsync signals the beginning of each horizontal line of pixels. Each pixel value (16- or 18-bits data) is transferred from the host processor to the display module during one pixel period. The rising edge of PCLK is used by the display module to capture pixel data. Since PCLK runs continuously, control signal DE is required to indicate when valid pixel data is being transmitted on the pixel data signals. HBP HAdr HFP HFP – horizontal interval when no valid display data is sent from host to display HBP – horizontal interval when no valid display data is sent from host to display VBP – vertical interval when no VBP valid display data is transferred from host to display ( Vadr+ Hadr) – period when valid display data are transferred from host to display VAdr module. VFP VFP– vertical interval when no valid display data is transferred from host to display Figure 5.4.2 RGB General Timing Diagram. 2012/05/11 43 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.4.3 RGB Interface Bus Width Set Table specifies the mapping of data bit, as components of primary pixel color value R, G, and B, to signal lines at the interface. Table 5.3.1 RGB Interface Bus Width for 16-bits Interface D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3Ah x x R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 50h (16-bits data) Table 5.3.2 RGB Interface Bus Width for 18-bits Interface D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3Ah R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 60h (18-bits data) Note 1: R0 is the LSB for the red component; G0 is the LSB for the green component, etc. Note 2: For 16-bits pixels, R primary color MSB is R4, G primary color MSB is G5 and B primary color MSB is B4. Note 3. For 18-bits pixels, R primary color MSB is R5, G primary color MSB is G5 and B primary color MSB is B5. 2012/05/11 44 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.4.4 RGB Interface Mode Set RGB I/F Mode RGB Mode 1 RGB Mode 2 PCLK Used Used DE Used Not used D17-D0 Used Used VS Used Used HS Used Used Register VBP[6:0], HBP[6:0], VFP[6:0], HFP[6:0] Not used Used In RGB Mode 1, writing data to line buffer is done by PCLK and Video Data Bus (D17 to D0), when DE is high state. The external clocks (PCLK, VS and HS) are used for internal displaying clock. So, controller must always transfer PCLK, VS and HS signal to NT35310. In RGB Mode 2, back porch of Vsync is defined by VBP[6:0] of RGBPRCTR command. And back porch of Hsync is defined by HBP[6:0] of RGBPRCTR command. Front porch of Vsync is defined by VFP[6:0] of RGBPRCTR command. And front porch of Hsync is defined by HFP[6:0] of RGBPRCTR command. 2012/05/11 45 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.4.5 RGB Interface Mode 1 & Mode 2 Timing Chart Vertical Back Porch ( VBP[ 6 : 0] ) 1 Frame Time VS tVHS HS DE PCLK NT35310 Vertical Front Porch (VFP[ 6 : 0]) tVHS Horizontal Back Porch ( HBP[ 6 : 0]) HS Valid Data Interval Horizontal Front Porch ( HFP[ 6 : 0]) PCLK DE D[17:0] Invalid Interval D1 D2 D3 D4 D5 ... ... ... Dn-3 Dn-2 Dn-1 Dn Invalid Interval Latched Data Invalid Interval D1 D2 D3 D4 D5 ... ... ... Dn-3 Dn-2 Dn-1 Dn Invalid Interval RAM WEN 1 Line Time Fig. 5.4.5.1 Video Signal Data Writing Method in RGB Mode 1 Interface Constraint : V-Porch (VBP ≧TBD , VFP ≧TBD , VBP > BP) Note: tVHS≧ TBD 2012/05/11 46 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Vertical Back Porch ( VBP[ 6 : 0] ) VS tVHS HS DE PCLK Draft Version 1 Frame Time NT35310 Vertical Front Porch ( VFP[ 6 : 0]) tVHS Horizontal Back Porch ( HBP[ 6 : 0]) HS Valid Data Interval Horizontal Front Porch ( HFP[ 6 : 0]) PCLK DE D[17:0] Invalid Interval D1 D2 D3 D4 D5 ... ... ... Dn-3 Dn-2 Dn-1 Dn Invalid Interval Latched Data Invalid Interval D1 D2 D3 D4 D5 ... ... ... Dn-3 Dn-2 Dn-1 Dn Invalid Interval RAM WEN 1 Line Time Figure 5.4.5.2 Video Signal Data Writing Method in RGB Mode 2 Interface Constraint : Vporch (VBP ≧ TBD , VFP ≧ TBD , VBP > BP) Note: tVHS≧ TBD 2012/05/11 47 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 VS HS PCLK DE RGB Data bus Frame data Figure 5.4.5.3 Enter Internal Clock mode(DM=0) Timing sequence Hi/ Low Hi/ Low Hi/ Low Low STOP N+ 1 Frame N+ 2 Frame N+ 3 Frame Don' t care Don't care Update frame data by SDI Do not update frame DATA by SPI Frame data Updating by RGB /IF Internal clock mode Set( DM=1) External clock mode Figure 5.4.5.4 Exit Internal Clock mode(DM=1) Timing sequence 2012/05/11 48 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.5 Frame Tearing Effect Interface The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off and On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 5.5.1 Tearing Effect Line Modes There are mode A, B and C for tearing effect line modes. Below figures are used to give examples based on 480 Horizontal lines condition. Mode A The Tearing Effect Output signal consists of V-Blanking Information only: tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see below) Mode B The Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one Mode A TE and 480H-sync pulses per field. thdl thdh V- sync …… V- sync Invisible Line 1 st Line 2 nd Line 3 rd Line 479 th Line 480 th Line thd h= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) AC characteristics of Tearing Effect Signal Idle Mode Off Symbol Parameter min max unit tvdl Vertical Timing Low Duration 13 - ms tvdh Vertical Timing High Duration 1000 - ㎲ thdl Horizontal Timing Low Duration 16 - ㎲ thdh Horizontal Timing High Duration - 500 ㎲ NOTE: This timings apply when MADCTL ML=0 and ML=1 The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tr tf description 0.8*VDDI 0.8*VDDI 0.2*VDDI 0.2*VDDI Mode C This mode turns on the display module’s Tearing Effect output signal on the TE signal line when the display module reaches line N. The Tearing Effect Line On has one parameter that describes the Tearing Effect Output Line mode. 2012/05/11 49 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 For reference, not belong to Mode C N= 1 N= 2 N =3 N =4 N = 479 N = 480 For reference, not belong to Mode C Mode A TE …… Mode A TE 35h 44h TE Output M N 0 0 TE high in V-porch region (A) 1 0 TE high in all V-porch and H-porch region (B) 0 ≠0 TE high at N-th line (C) 1 ≠0 TE high in all V-porch and H-porch region (B) 2012/05/11 50 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Mode A, Mode B,and Mode C timing chart is shown in below: 479 th Line Porch NT35310 Bottom Line Top Line 2nd Line TE Mode C (n=1) TE Mode C (n= 479) TE Mode B TE Mode A t vdh Note: 1. During sleep-in mode, the Tearing Output pin is active Low 2. N >=" Horizontal line number" will be ignore in TE mode C. " Horizontal line number" is decided by GM[2:0] pins. 2012/05/11 51 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.5.2 Example 1: MPU write is faster than panel read Data write to Frame Memory is now synchronized to the panel scan (leading mode). It should be written next one horizontal sync pulse after FTE signal. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: Below figures are used to give examples based on 360 Horizontal lines condition. 2012/05/11 52 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.5.3 Example 2: MPU write is slower than panel read The MPU to Frame Memory write begins just after Panel Read has commenced (lagging mode). This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. Below figures are used to give examples based on 360 Horizontal lines condition. The TE interface has a minimum RAM write speed requirement. Therefore, the RAM Write Speed must be faster than the values calculated from the following formulas:TBD 2012/05/11 53 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.4 Content Adaptive Brightness Control (CABC) function 5.3.1 Dynamic Backlight Control Function The NT35310 supports Backlight-Control function to control brightness of backlight and to process image dynamically. This function enables to reduce backlight power and minimize the effect of reduced power on the display image. The display image is dynamically controlled by CABC block. The availability of this function ranges from moving picture such as TV image to still picture such as menu. The brightness of backlight and image processing coefficient are calculated so that image data is optimized. Backlight power is reduced without changing display image. The Backlight-Control function is supported for the following two architectures: 1. When bit BL of “Write CTRL Display (53h)” command is ‘1’, the PWM signal is used to directly control the LED driver IC. The LED driver IC is controlled entirely via the NT35310. Display Module HOST Image Data LEDPWM LED Driver NT 35310 Image Histogram Analysis NVT Gamma Algorithms for Display PWM Duty Estimation for Backlight Control CABC Block LED Backlight 2. When bit BL of “Write CTRL Display (53h)” command is ‘0’, the host processor reads LED brightness information internally generated by CABC processing from the NT35310. Then, the LED driver IC is controlled from the host processor. There is the time difference between brightness adjustment by PWM and displaying data processed from the NT35310. Display Module HOST Image Data RDPWM[7:0] NT 35310 Image Histogram Analysis NVT Gamma Algorithms for Display LEDPWM LED Driver PWM Duty Estimation for Backlight Control CABC Block LED Backlight 5.3.1.1 CONTENT ADAPTIVE BRIGHTNESS CONTROL A Content Adaptive Brightness Control function can be used to reduce the power consumption of the luminance source. Content adaptation means that content grey level scale can be increased while simultaneously lowering brightness of the backlight to achieve same perceived brightness. The adjusted grey level scale and thus the power consumption reduction depend on the content of the image. 2012/05/11 54 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 This function and its different modes can be controlled. See command “Write Content Adaptive Brightness Control (55h)” (bit: 0 and 1) for more information. Definition of Modes: - Off mode: Content Adaptive Brightness Control functionality is totally off. - UI [User interface] image mode: Optimized for UI image. It is kept image quality as much as possible. Target power consumption reduction ratio: 10% or less - Still picture mode: Optimized for still picture. Some image quality degradation would be acceptable. Target power consumption reduction ratio: more than 30% - Moving image mode: Optimized for moving image. It is focused on the biggest power reduction with image quality degradation. Target power consumption reduction ratio: more than 30%. 5.3.1.2 Display Backlight Dimming Control A dimming function (how fast to change the brightness from old to new level and what are brightness levels during the change) is used when changing from one brightness level to another. This dimming function curve is the same in increment and decrement directions. The basic idea is described below. Luminance Step Up Luminance Dimming Without Dimming Time With Dimming Time Dimming function can be enabled and disabled. See command “Write CTRL Display (53h)” (bits DD) for more information. From the original brightness value to the target brightness value, the transferring time steps between these two brightness values are equal making the transition linear. The dimming function is working similarly in both upward and downward directions. An upward example is illustrated below: Target Luminance Value (V+4) V+3 V+2 V+1 Original Luminance Value (V) t t+1 t+2 t+3 t+4 t+5 30 frames (400~600ms) 2012/05/11 55 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.3.1.3 BRIGHTNESS CONTROL LINE The brightness control (LEDPWM) line is sending control information to the display brightness control unit which can be a power supply for the display brightness. The Brightness Control Line Timings are described below: tPW = 1 Pulse Width LEDPWM ON OFF Off On 33% On 66% On (0d) (255d) (88d) (168d) Symbol Parameter min max unit description tPW Pulse Width 0.0333 8.33 ms Note: The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tr tf 80% 20% 80% 20% 2012/05/11 56 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6 MDDI Interface (Mobile Display Digital Interface) The NT35310 supports the Mobile Display Digital Interface (MDDI) is a differential small amplitude serial interface for high-speed data transfer through the following four lines: HSSI_D0_P/N and HSSI_CLK_P/N. The specifications of MDDI supported by the NT35310 meet the MDDI specifications Version 1.2 as published by the Video Electronics Standards Association (VESA). The NT35310 offers the Bi-direction Link to use for the register and display data read / write. For power saving, the NT35310 offers both Hibernation mode (Send shutdown packet), and enter deep standby mode to reduce power consumption. The NT35310 supports Type-1 of the MDDI specifications Version 1.2 and the application diagram is illustrated as Figure 5.6.1. Interface Pins Figure 5.6.1 MDDI Interface Application Notes: (1) Based on the system configuration, use TE signal as the reference signal for moving picture display to avoid the tearing effort. (2) When enter to the MDDI interface from other interface, the Host need to wait 100ms and can start to send any packet. For example wake up packet. (3) After shutting down the MDDI interface the Host need to wait 500ns and can start to send wake up packet to wake up the MDDI link. 2012/05/11 57 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.1 MDDI Link Protocol The NT35310’s MDDI Link Protocol is in accordance with the MDDI specifications as published by VESA; refer to these specifications for more information on the MDDI Link Protocol. Do not send any packets that are not supported by the NT35310 into a system containing the NT35310. Supported MDDI packets are as follows: Table 5.6.1 Summary of MDDI packets supported by the NT35310 NT35310 MDDI packets Link Control Packet Register Access Packet Packet Name Sub-frame Header Packet Filler Ppacket Link Shutdown Packet Reverse Link Encapsulation Packet Round-trip Delay Measurement Packet Client Capability Packet Client Request and Status Packet Register Access Packet Packet Type 15359 (0x3BFF) 0 69 (0x45) 65 (0x41) 82 (0x52) 66 (0x42) 70 (0x46) 146 (0x92) Direction Forward Forward/Reverse Forward Forward Forward Reverse Reverse Forward/Reverse Basic Media Stream Packet Video Stream Packet 16 (0x10) Forward 5.6.2 MDDI Link Packet descriptions Sub-frame Header Packet: The Sub-Frame Header Packet is the first packet of every sub-frame. Sub- frame Header Packet Packet Length Packet Type (0x3 BFF) 2 Bytes 2 Bytes Unique Word (0x 005A) 2 Bytes Reversed1 2 Bytes Sub- frame Length 4 Bytes Protocol Version Sub- frame Count 2 Bytes 2 Bytes Media- frame Count 4 Bytes CRC 2 Bytes Packet Contents : Packet Length: Packet length not including the packet length field Packet Type: Packet type is 0 x3BFF Unique Word: Unique word is 0x005A Reserved 1 : Not used Sub -frame Length : Specify the number of bytes per sub- frame Bit [15 : 2]: Set it to zero Bit [ 1 : 0]: Sub - frame operational mode 00b- Sub- frame lengths strictly followed. 01b- Sub- frame lengths are flexible. Sub- frame packets should be sent at the first opportunity after the sub-frame lengths has been transmitted. 10b - Sub- frame lengths are unlimited.No more sub -frame packets are required to be transmitted after the first sub - frame packet at startu.p Sub- frame Count: Specify the number of sub - frame header packet Media- frame Count: Specify the number of media - frames CRC: Error check Figure 5.6.2 Sub-frame Header Packet Structure 2012/05/11 58 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Filler Packet: The Filler Packet is sent when no other information is available to be sent on the forward or reverse link. Figure 5.6.3 Filler Packet Structure Link Shutdown Packet: The Link Shutdown Packet is sent from the host to the client to indicate that the MDDI data and strobe will be shut down and go into a low-power hibernation state. Figure 5.6.4 Link Shutdown Packet Structure 2012/05/11 59 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Reverse Link Encapsulation Packet: Data is transferred in the reverse direction using the Reverse Link Encapsulation Packet. NT35310 Figure 5.6.5 Reverse Link Encapsulation Packet 2012/05/11 60 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Round-Trip Delay Measurement Packet: The Round-Trip Delay Measurement Packet is used to measure the propagation delay from the host to the client plus the delay from the client back to the host. This packet is most useful when the MDDI link is running at the maximum speed intended for a particular application. The packet may be sent in Type I mode and at a lower data rate to increase the range of the Round-Trip delay measurement. Figure 5.6.6 Round-Trip Delay Measurement Packet The Figure 5.6.7 illustrates the timing of events during the Round-Trip Delay Measurement Packet. Figure 5.6.7 Round-Trip Delay Measurement Timing 2012/05/11 61 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Client Capability Packet: It is recommended that the client send a Client Capability Packet to the host after forward link synchronization is acquired, and it is required when requested by the host via the Reverse Link Flags in the Reverse Link Encapsulation Packet. Packet length not including the packet length field Packet type is 0x0042 Set it to zero Set it to 0x0002 Specify the minimum protocol version, set it to 0x0001 Specify the maximum data rate the client can receive ﴾190h﴿ Set it to 0x00 Set it to zero Specify the maximum data rate the client can receive ﴾190h﴿ Specify the width of the bitmap Specify the height of the bitmap Specify the width of the display window Specify the height of the display window Set it to zero Set it to zero Specify the resolution of RGB format ﴾0x8666﴿ Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero 0x004C8000 Specify the maximum video frame ﴾3Ch﴿ Specify the minimum video frame ﴾00h﴿ Specify the minimum sub-frame rate ﴾0x01﴿ Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero Set it to zero Set it to 0xB9F6 Set it to 0x5310 Set it to zero Set it to zero Set it to zero Set it to 0x0C Error check 2012/05/11 Figure 5.6.9 Client Capability Packet 62 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Client Request and Status Packet: The host needs a small amount of information from the client so it can configure the host-to-client link in an optimum manner. The Client Request and Status Packet is required to report errors and status to the host. Figure 5.6.10 Client Request and Status Packet 2012/05/11 63 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Register Access Packet: Register Access Packet is utilized when setting instruction to the NT35310. This packet cannot be used for RAM access.. Figure 5.6.11 Register Access Packet 2012/05/11 64 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Multi Register Write Packet Draft Version NT35310 Figure 5.6.12 Multi Register Access Packet 2012/05/11 65 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Video Stream Packet The NT35310 supports the Video Stream Packet to transfer display data including RGB data to RAM. Packet length not including the packet length field Packet type is 0x0010 Set it to zero Determines the pixel data format. Set the same pixel format as determined in Video Data Format Descriptor. Only three formats listed below are supported. Error check of the pixel data Figure 5.6.13 Video Stream Packet 2012/05/11 66 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Table 5.6.2 Pixel Data Format MDDI Data Byte D[7] RGB 5:6:5 Byte N-th Byte (N + 1)-th G1[2] R1[4] D[6] G1[1] R1[3] Draft Version D[5] G1[0] D[4] B1[4] D[3] B1[3] D[2] B1[2] D[1] B1[1] R1[2] R1[1] R1[0] G1[5] G1[4] D[0] B1[0] G1[3] Byte N-th G1[1] G1[0] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] Byte (N + 1)-th R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] RGB 6:6:6 RGB 8:8:8 Byte (N + 2)-th Byte (N + 3)-th Byte (N + 4)-th Byte (N + 5)-th Byte N-th Byte (N + 1)-th Byte (N + 2)-th B2[5] B2[4] R2[1] R2[0] B3[3] B3[2] G3[5] G3[4] B1[7] G1[7] R1[7] B1[6] G1[6] R1[6] B2[3] B2[2] B2[1] G2[5] G2[4] G2[3] B3[1] B3[0] R2[5] G3[3] G3[2] G3[1] B1[5] G1[5] R1[5] B1[4] G1[4] R1[4] B1[3] G1[3] R1[3] B2[0] R1[5] R1[4] G2[2] G2[1] G2[0] R2[4] R2[3] R2[2] G3[0] B3[5] B3[4] B1[2] G1[2] R1[2] B1[1] G1[1] R1[1] B1[0] G1[0] R1[0] NT35310 Colors 65K Colors (1 Pixel / 16-bits RGB Format) 262K Colors (1 Pixel / 18-bits RGB Format) 16.7M Colors (1 Pixel / 24-bits RGB Format) Note: NT35310 can accept 8-8-8 pixel format Video stream packet in MDDI I/F. However, due to NT35310's RAM buffer is 18 bits depth per pixel, also the Source driver is 6 bits per channel, therefore only MSB 6 bits of each R/G/B sub-pixel can be stored in memory and displayed in LCD panel. 2012/05/11 67 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.3 Writing Video Data to Memory Sequence In order to write video data to memory, the following sequence should be programmed. This packet should be followed by video stream packets. Video Data Transfer (Video Stream Packet) Video Data Transfer (Video Stream Packet Video Data Transfer (Video Stream Packet Figure 5.6.14 Writing Video Data to Memory Sequence 5.6.4 Writing Register Sequence In order to write registers, register access packet should be used. Register access packet is used to write data to register. Figure 5.6.15 Writing Register Sequence 2012/05/11 68 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.5 Reading Video Data from Memory Sequence In order to read a pixel data from memory (readable one pixel Only), the following sequence should be programmed. Memory read command (2E00h) is followed by reverse encapsulation packet. DDI transmits video pixel data through encapsulation packet. Please refer to VESA spec for detailed description. Round Trip Delay Measurement Transfer (Round Trip Delay Measurement Packet Read Memory (2E00h) Transfer (Register Access Packet) Reverse Encapsulation Transfer (Reverse Encapsulation Packet) Figure 5.6.16 Reading Video Data from Memory Sequence 5.6.6 Reading Register Sequence In order to read registers, the following sequence should be programmed. Next, register read command is followed by reverse encapsulation packet. MDDI transmits register data through encapsulation packet. Please refer to VESA spec for detailed description. Round Trip Delay Measurement Transfer (Round Trip Delay Measurement Packet) Read Register Command Transfer (Register Access Packet) Reverse Encapsulation Transfer (Reverse Encapsulation Packet) Figure 5.6.17 Reading Register Sequence 2012/05/11 69 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.7 Hibernation Setting The Client MDDI of the NT35310 provides a Hibernation setting. The methods for waking up the Hibernation mode can be determined based on actual usage. Table 5.7.3 Hibernation Wake-up Wake-up Condition Host-Initiated Wake-up Wake up the MDDI link by MDDI Host FTE-Initiated Wake-up Use the FTE to wake up the MDDI link Note: In the Hibernation state, the data is retained in RAM and the display operation is maintained. Hibernation setting and wake-up sequence must in accordance with VESA-MDDI specifications. Hibernation Setting Sequence: Figure 5.6.18 Hibernation Setting Sequence Hibernation Wake-up Sequence: In Hibernation Mode Host or FTE Initiated Wake-up Exit Hibernation Mode Figure 5.6.19 Hibernation Wake-up Sequence 2012/05/11 70 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.8 Deep Standby Mode Setting by MDDI The Client MDDI of the NT35310 includes a deep standby mode setting so it can enter a standby state and reduce power consumption during Hibernation mode. The MDDI enters Hibernation mode when a Shutdown Packet is sent. The standby power needs of the Client MDDI can be reduced, even while the MDDI Link is maintained in Hibernation mode. When entering deep standby mode, the NT35310 stops operation rather than maintaining Hibernation mode. Input low pulse 3 msec from RESX pin to cancel deep standby mode, after which a Host-Initiated Wake-up should cancel the Hibernation mode. When in deep standby mode, instruction settings and RAM data are not stored, so they must be reset after Hibernation mode is cancelled. Follow the sequence indicated in the VESA MDDI specifications when initiating or canceling the Hibernation mode. Figure 5.6.20 State Transitions in Deep Standby Mode Note: When the NT35310 is in the MDDI Hibernation mode or MDDI deep standby mode, both the links are in the link hibernation states. 2012/05/11 71 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Deep Standby Mode Sequence Draft Version NT35310 Figure 5.6.21 Deep Standby Mode Sequence Note: When in deep standby mode, instruction settings and RAM data are not stored, so they must be reset after Hibernation mode is cancelled. 2012/05/11 72 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.6.9 Vsync Based Link Wakeup In display-ON state, when the IC finishes displaying all internal GRAM data, data request must be transferred to MDDI host for new video data. As MDDI link is usually in hibernation for reducing interface power consumption, MDDI link wake-up must be done before internal GRAM update. In that case, client initiated link wake-up can be used as data request. When VSYNC based link wake-up register(0xAD00: VWAKE_EN) is set, followed by host set the link into hibernation, client initiated wake-up is executed in synchronization with the internal vertical-sync signal which generated in NT35351. Using VSYNC based link wake-up, tearingless display can be accomplished if interface speed and wake-up time is well known. The diagram illustrait a wakeup based on a VSYNC wakeup request. (A) MDDI host write to the VSYNC wakeup register(0xAD00 : VWAKE_EN) to enable a wakeup based on Vsync. (B) Link_Active goes low when the host puts the link into hibernation after all data has been sent to client. (C) Vsync signal goes high indicating that update pointer has wrapped around, and Client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. (D) Link_Active goes high after the host brings the link out of hibernation. (E) As the Link_Active goes high, MDDI_Client_Wakeup signal and the VSYNC based link wake-up register(0xAD00: VWAKE_EN) are cleared. 2012/05/11 73 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7 MIPI Interface (Mobile Industry Processing Interface) The Display Serial Interface standard defines protocols between a host processor and peripheral devices that adhere to MIPI Alliance standards for mobile device interfaces. The DSI standard builds on existing standards by adopting pixel formats and command set defined in MIPI Alliance standards. DSI-compliant peripherals support either of two basic modes of operation: Command Mode and Video Mode. Which mode is used depends on the architecture and capabilities of the peripheral. The mode definitions reflect the primary intended use of DSI for display interconnect, but are not intended to restrict DSI from operating in other applications. Typically, a peripheral is capable of Command Mode operation or Video Mode operation. Some Video Mode display modules also include a simplified from of Command Mode operation in which the display module may refresh its screen from a reduced-size, or partial, frame buffer, and the interface (DSI) to the host processor may be shut down to reduce power consumption. Command Mode refers to operation in which transactions primarily take the form of sending commands and data to a peripheral, such as a display module, that incorporates a display controller. The display controller may include local registers and a frame buffer. Systems using Command Mode write to, and read from, the registers and frame buffer memory. The host processor indirectly controls activity at the peripheral by sending commands, parameters and data to the display controller. The host processor can also read display module status information or the contents of the frame memory. Command Mode operation requires a bidirectional interface. Video Mode refers to operation in which transfers from the host processor to the peripheral take the form of a real-time pixel stream. In normal operation, the display module relies on the host processor to provide image data at sufficient bandwidth to avoid flicker or other visible artifacts in the displayed image. Video information should only be transmitted using High Speed Mode. Some Video Mode architectures may include a simple timing controller and partial frame buffer, used to maintain a partial-screen or lower-resolution image in standby or Low Power Mode. This permits the interface to be shut down to reduce power consumption. To reduce complexity and cost, systems that only operate in Video Mode may use a unidirectional data path. Configuration: Clock Lane Data Lane0 MCU (Master) Display Module (Slave) Unidirectional Lane ■ Clock Only ■ Escape Mode(ULPS Only) Bi-directional Lane ■ Forward High-Speed ■ Bi-directional Escape Mode ■ Bi-directional LPDT 2012/05/11 74 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.7.1 Display Module Pin Configuration for DSI NT35310 DSI- CLK Resistance: TBDohm typ Inductance: TBDnH typ Module Connector Capacitance: TBDpF typ Resistance: TBDohm typ Inductance: TBDnH typ Module Connector Capacitance: TBDpF typ Resistance Resistance + H S/ LP Capacitance HS/LP - HS- RX LP- RX DSI-D0 Resistance: TBDohm typ Inductance: TBDnH typ Module Connector Capacitance: TBDpF typ Resistance: TBDohm typ Inductance: TBDnH typ Module Connector Capacitance: TBDpF typ Resistance Resistance + H S/ LP HS/LP Capacitance - HS- RX LP- RX LP- TX LP- CD 2012/05/11 75 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2 Display Serial Interface (DSI) 5.7.2.1 General Description Communication sequences between the MCU and the display module are described on chapter “5.8.2.3.3 Communication Sequences”. The communication can be separated 2 different levels between the MCU and the display module: Low level communication what is done on the interface level High level communication what is done on the packet level 5.7.2.2 Interface Level Communication 5.7.2.2.1 General The display module uses data and clock lane differential pairs for DSI (DSI-3M). Both differential lane pairs can be driven Low Power (LP) or High Speed (HS) mode. Low Power mode means that each line of the differential pair is used in single end mode and a differential receiver is disable (A termination resistor of the receiver is disable) and it can be driven into a low power mode. High Speed mode means that differential pairs (The termination resistor of the receiver is enable) are not used in the single end mode. There are used different modes and protocol in each mode when there is wanted to transfer information from the MCU to the display module and vice versa. The State Codes of the High Speed (HS) and Low Power (LP) lane pair are defined below. Lane Pair State Code HS-0 HS-1 LP-00 LP-01 LP-10 LP-11 Line DC Voltage Levels Dx+ - line Dx- - line Low (HS) High (HS) High (HS) Low (HS) Low (LP) Low (LP) Low (LP) High (LP) High (LP) Low (LP) High (LP) High (LP) High Speed(HS) Burst Mode Differential-0 Differential-1 Not Defined Not Defined Not Defined Not Defined Low-Power(LP) Control Mode Escape Mode Note 1 Note 1 Note 1 Note 1 Bridge Space HS-Request Mark-0 LP-Request Mark-1 Stop Note 2 Notes: 1. Low-Power Receivers (LP-Rx) of the lane pair are checking the LP-00 state code, when the Lane Pair is in the High Speed (HS) mode. 2. If Low-Power Receivers (LP-Rx) of the lane pair recognizes LP-11 state code, the lane pair returns to LP-11 of the Control Mode. 2012/05/11 76 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.2 DSI-CLOCK Lane DSI-CLK+/- lanes can be driven into three different power modes: Low Power Mode (LPM), Ultra Low Power Mode (ULPM) or High Speed Clock Mode (HSCM). Clock lanes are in a single end mode (LP = Low Power) when there is entering or leaving Low Power Mode (LPM) or Ultra Low Power Mode (ULPM). Clock lanes are in the single end mode (LP = Low Power) when there is entering in or leaving out High Speed Clock Mode (HSCM). These entering and leaving protocols are using clock lanes in the single end mode to generate an entering or leaving sequences. The principle flow chart of the different clock lanes power modes is illustrated below Figure 5.7.1 Clock Lanes Power Mode 2012/05/11 77 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.2.1 Low Power Mode (LPM) DSI-CLK+/- lanes can be driven to the Low Power Mode (LPM), when DSI-CLK lanes are entering LP-11 State Code, in three different ways: (1) After SW Reset, HW Reset or Power On Sequence =>LP-11 (2) After DSI-CLK+/- lanes are leaving Ultra Low Power Mode (ULPM, LP-00 State Code) =>LP-10 =>LP-11 (LPM). This sequence is illustrated below. From ULPM to LPM (3) After DSI-CLK+/- lanes are leaving High Speed Clock Mode (HSCM, HS-0 or HS-1 State Code) =>HS-0 =>LP-11 (LPM). This sequence and all three mode changes are illustrated below. From High Speed Clock Mode (HSCM) to LPM 2012/05/11 78 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 All Three Mode Changes to LPM on the Flow Chart 2012/05/11 79 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.2.2 Ultra Low Power Mode (ULPM) DSI-CLK+/- lanes can be driven to the Ultra Low power Mode (ULPM), when DSI-CLK lanes are entering LP-00 State Code. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-10 =>LP-00 (ULPM). This sequence is illustrated below. The mode change is also illustrated below. From LPM to ULPM Mode Change from LPM to ULPM on the Flow Chart 2012/05/11 80 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.2.3 High Speed Clock Mode (HSCM) DSI-CLK+/- lanes can be driven to the High Speed Clock Mode (HSCM), when DSI-CLK lanes are starting to work between HS-0 and HS-1 State Codes. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-01 =>LP-00 =>HS-0 =>HS-0/1 (HSCM). This sequence is illustrated below. The mode change is also illustrated below. From LPM to HSCM Mode Change from LPM to HSCM on the Flow Chart The high speed clock (DSI-CLK+/-) is started before high speed data is sent via DSI-Dn+/- lanes. The high speed clock continues clocking after the high speed data sending has been stopped. 2012/05/11 81 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version The burst of the high speed clock consists of oEven number of transitions oStart state is HS-0 oEnd state is HS-0 LPM LP- 11 Termination Resistor is enable HSCM NT35310 Termination Resistor is disable LPM LP-11 DSI- CLK+ DSI- CLK- LP-11 LP-01 LP-00 HS-0 THE- SKIP HS-0 LP- 11 DSI-Dn+ DSI-Dn- LP-11 Time LP- 11 DSI- CLK+ DSI- CLK- Preparation from Low Power Mode to High Speed Mode (TSOT =Start of the Transmission ) TLPX THE- PREPARE HSDT DSI-Dn+ DSI-Dn- LP-11 LP-01 LP-00 THE- SETTLE Low Power Mode, Disable Rx Line Termination HS-0 0 0 0 1 1 1 0 1 Rx Synchronized Tx Synchronization High Speed Mode , Enable Rx Line Termination High Speed Data Transmission TEOT DSI- CLK+ DSI- CLK- DSI-Dn+ DSI-Dn- Note THE- SKIP The last load bit THE- TRAIL HS- 0 or HS-1 High Speed Mode, Enable Rx Line Termination Note If the last load bit Is HS-0 ,the transmitter changes from HS- 0 to HS-1. If the last load bit Is HS-1 ,the transmitter changes from HS- 1 to HS-0. h Speed Clock Burst LP- 11 THE- EXIT Low Power Mode, Disable Rx Line Termination DSI-CLK+ , DSI-Dn+ DSI-CLK- , DSI-Dn- Hig 2012/05/11 82 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.7.2.2.3 DSI-DATA Lanes 5.7.2.2.3.1 General DSI-Dn+/- Data Lanes can be driven in different modes which are: • Escape Mode(only DSI_D0+/- data lane is used) • High-Speed Data Transmission(all data lanes are used) • Bus Turnaround Request(only DSI_D0+/- data lane is used) These modes and their entering codes are defined on the following table. NT35310 Entering and Leaving Sequences Mode Escape Mode High-Speed Data Transmission Bus Turnaround Request Entering Mode Sequence LP-11=>LP-10=>LP-00=>LP-01=>LP-00 LP-11=>LP-01=>LP-00=>HS-0 LP-11=>LP-10=>LP-00=>LP-10=>LP-00 Leaving Mode Sequence LP-00=>LP-10=>LP-11(Mark-1) (HS-0 or HS-1) =>LP-11 High-Z, Note 2012/05/11 83 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.3.2 Escape Mode Data lane0 (DSI-D0+/-) can be used in different Escape Modes when data lanes are in Low Power (LP) mode. These Escape Modes are used to: • Send “Low-Power Data Transmission” (LPDT) e.g. from the MCU to the display module • Drive data lanes to “Ultra-Low Power State” (ULPS) • Indicate “Remote Application Reset” (RAR), which is reset the display module • Indicate “Tearing Effect” (TEE), which is used for a TE line event from the display module to the MCU • Indicate “Acknowledge” (ACK), which is used for a non-error event from the display module to the MCU The basic sequence of the Escape Mode is as follow • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Escape Command (EC), which is coded, when one of the data lanes is changing from low-to-high-to-low then this changed data lane is presenting a value of the current data bit (DSI-Dn+ = 1, DSI-Dn- = 0) e.g. when DSI-Dn- is changing from low-to-high-to-low, the receiver is latching a data bit, which value is logical 0. The receiver is using this low-to-high-to-low transition for its internal clock. • A load if it is needed • Exit Escape (Mark-1) LP-00 =>LP-10 =>LP-11 • End: LP-11 This basic construction is illustrated below: General Escape Mode Sequence The number of the different Escape Commands (EC) is eight. These eight different escape commands (EC) can be divided 2 different groups: Mode or Trigger. The MCU is informing to the display module that it is controlling data lanes (DSI-Dn+/-) with the mode e.g. The MCU can inform to the display module that it can put data lanes in the low power mode. The MCU is waiting from the display module event information, which has been set by the MCU, with the trigger e.g. when the display module reaches a new V-synch, the display module sent to the MCU a TE trigger (TEE), if the MCU has been requested it. Escape commands are defined on the next table. Escape Commands 2012/05/11 84 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Escape Command Low-Power Data Transmission Ultra-Low Power Mode Underfined-1, Note Underfined-2, Note Remote Application Reset Tearing Effect Acknowledge Unknow-5, Note Command Type Mode/Trigger Mode Mode Mode Mode Trigger Trigger Trigger Trigger Entry Command Pattern (First Bit => Last Bit Transmitted) 1110 0001 bin 0001 1110 bin 1001 1111 bin 1101 1110 bin 0110 0010 bin 0101 1101 bin 0010 0001 bin 1010 0000 bin Note: This Escape command support has not been implemented on the display module. 2012/05/11 85 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Low-Power Data Transmission (LPDT) The MCU can send data to the display module in Low-Power Data Transmission (LPDT) mode when data lanes are entering in Escape Mode and Low-Power Data Transmission (LPDT) command has been sent to the display module. The display module is also using the same sequence when it is sending data to the MCU. The Low Power Data Transmission (LPDT) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Low-Power Data Transmission (LPDT) command in Escape Mode: 1110 0001 (First to Last bit) • Load (Data): One or more bytes (8 bits) Data lanes are in pause mode when data lanes are stopped (Both lanes are low) between bytes • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Low-Power Data Transmission (LPDT) Pause (Example) Ultra-Low Power State (ULPS) The MCU can force data lanes in Ultra-Low Power State (ULPS) mode when data lanes are entering in Escape Mode. 2012/05/11 86 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version The Ultra-Low Power State (ULPS) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Ultra-Low Power State (ULPS) command in Escape Mode: 0001 1110 (First to Last bit) • Ultra-Low Power State (ULPS) when the MCU is keeping data lanes low • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: NT35310 Ultra-Low Power State (ULPS) 2012/05/11 87 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Remote Application Reset (RAR) The MCU can inform to the display module that it should be reset in Remote Application Reset (RAR) trigger when data lanes are entering in Escape Mode. The Remote Application Reset (RAR) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Remote Application Reset (RAR) command in Escape Mode: 0110 0010 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Remote Application Reset (RAR) 2012/05/11 88 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Tearing Effect (TEE) The display module can inform to the MCU when a tearing effect event (New V-synch) has been happen on the display module by Tearing Effect (TEE). The Tearing Effect (TEE) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 •Tearing Effect (TEE) trigger in Escape Mode: 0101 1101 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry ( EME) Mark-1 LP- 11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP- 11 Escape Mode Entry( EME) DSI-D0+ DSI-D0- Tearing Effect ( TEE) Mark-1 LP-11 0 1 0 1 1 1 0 1 Time Tearing Effect (TEE) DSI- D0 + DSI- D0 LP-11 2012/05/11 89 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Acknowledge (ACK) The display module can inform to the MCU when an error has not recognized on it by Acknowledge (ACK). The Acknowledge (ACK) is using a following sequence: • Start: LP-11 • Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 • Acknowledge (ACK) command in Escape Mode: 0010 0001 (First to Last bit) • Mark-1: LP-00 =>LP-10 =>LP-11 • End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry( EME) Mark -1 LP- 11 LP-10 LP-00 LP-01 LP-00 LP-00 LP- 10 LP- 11 Escape Mode Entry( EME) DSI-D0+ DSI-D0- Acknowledge( ACK) Mark-1 LP-11 0 0 1 0 0 0 0 1 Time Acknowledge (ACK) DSI- D0 + DSI- D0 LP-11 2012/05/11 90 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.2.3.3 High Speed Data Transmission Entering High-Speed Data Transmission ( TSOT of HSDT) The display module is entering High-Speed Data Transmission (HSDT) when Clock lanes DSI-CLK+/- have already been entered in the High-Speed Clock Mode (HSCM) by the MCU. See more information on chapter “High-Speed Clock Mode (HSCM)”. Data lanes of the display module are entering ( TSOT ) in the High-Speed Data Transmission (HSDT) as follows • Start: LP-11 • HS-Request: LP-01 • HS-Settle: LP-00 => HS-0 (Rx: Lane Termination Enable) • Rx Synchronization: 011101 (Tx (= MCU) Synchronization: 0001 1101) • End: High-Speed Data Transmission (HSDT) – Ready to receive High-Speed Data Load This same entering High-Speed Data Transmission ( TSOT of HSDT) sequence is illustrated below Ent ering High-Speed Data Transmission ( TSOT of HSDT) 2012/05/11 91 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Leaving High-Speed Data Transmission ( TEOT of HSDT) The display module is leaving the High-Speed Data Transmission ( TEOT of HSDT) when Clock lanes DSI-CLK+/- are in the High-Speed Clock Mode (HSCM) by the MCU and this HSCM is kept until data lanes are in LP-11 mode. See more information on chapter “High-Speed Clock Mode (HSCM)”. Data lanes of the display module are leaving from the High-Speed Data Transmission ( TEOT of HSDT) as follows • Start: High-Speed Data Transmission (HSDT) • Stops High-Speed Data Transmission MCU changes to HS-1, if the last load bit is HS-0 MCU changes to HS-0, if the last load bit is HS-1 • End: LP-11 (Rx: Lane Termination Disable) This same leaving High-Speed Data Transmission ( TEOT of HSDT) sequence is illustrated below Leaving High-Speed Data Transmission ( TEOT of HSDT) 2012/05/11 92 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Burst of the High-Speed Data Transmission (HSDT) The burst of the high-speed data transmission (HSDT) can consist of one data packet or several data packets. These data packets can be Long (LPa) or Short (SPa) packets. These packets are defined on chapter “Short Packet (SPa) and Long Packet (LPa) Structures“. These different burst of the High-Speed Data Transmission (HSDT) cases are illustrated for reference purposes below. LP-11 SoT LPa EoT LP-11 LP-11 SoT SPa EoT LP-11 Single Packet in High-Speed Data Transmissions LP-11 SoT LPa SP EoT LP-11 LP-11 SoT SPa SPa SPa EoT LP-11 Multiple Packets in High-Speed Data Transmission - Examples HS Transmission Examples with EoT packet disabled LP-11 LP-11 SoT SoT LPa EoT Packet SPa SPa EoT Packet SPa EoT EoT LP-11 LP-11 Single Packet in High-Speed Data Transmissions EoT Packet LP-11 SoT LPa SPa SPa EoT LP-11 EoT Packet SoT SPa SPa SPa SPa EoT LP-11 LP-11 Abbreviations Abbreviation EoT LPa LP-11 SPa SoT Multiple Packets in High-Speed Data Transmission - Examples HS Transmission Examples with EoT packet enabled Explanation End of the Transmission Long Packet Low Power Mode, Data lanes are’1’s (Stop Mode) Short Packet Start of the Transmission 2012/05/11 93 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3 Packet Level Communication 5.7.2.3.1 Short Packet (SPa) and Long Packet (LPa) Structures Short Packet (SPa) and Long Packet (LPa) are always used when data transmission is done in Low Power Data Transmission (LPDT) or High-Speed Data Transmission (HSDT) modes. The lengths of the packets are • Short Packet (SPa): 4 bytes • Long Packet (LPa): From 6 to 65,541 bytes The type (SPa or LPa) of the packet can be recognized from their package headers (PH). Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission Packet Data DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11 Time Short Packet (Spa) Structure LP-11 SoT Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) DI Word Count (WC) ECC Data 0, ? WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Time Checksum (CS) EoT LP-11 Long Packet (Lpa) Structure Note: Short Packet (SPa) Structure and Long Packet (LPa) Structure are presenting a single packet sending (= Includes LP-11, SoT and EoT for each packet sendings). The other possibility is that there is not needed SoT, EoT and LP-11 between packets if packets have sent in multiple packet format e.g. * LP-11 =>SoT =>SPa =>LPa =>SPa =>SPa =>EoT =>LP-11 * LP-11 =>SoT =>SPa =>SPa =>SPa =>EoT =>LP-11 * LP-11 =>SoT =>LPa =>LPa =>LPa =>EoT =>LP-11 2012/05/11 94 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.1.1 Bit Order of Byte on Packets The bit order of the byte, what is used on packets, is that the Least Significant Bit (LSB) of the byte is sent in the first and the Most Significant Bit (MSB) of the byte is sent in the last. This same order is illustrated for reference purposes below. 5.7.2.3.1.2 Byte Order of the Multiple Byte Information on Packets Byte order of the multiple bytes information, what is used on packets, is that the Least Significant (LS) Byte of the information is sent in the first and the Most Significant (MS) Byte of the information is sent in the last e.g. Word Count (WC) consists of 2 bytes (16 bits) when the LS byte is sent in the first and the MS byte is sent in the last. This same order is illustrated for reference purposes below. WC (Least Significant Byte) 0x01 10000000 WC (Most Significant Byte) 0x00 00000000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML M S SS S B BB B Time Byte Order of the Multiple Byte on Packet 2012/05/11 95 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.1.3 Packet Header (PH) The packet header is always consisting of 4 bytes. The content of these 4 bytes are different if it is used to Short Packet (SPa) or Long Packet (LPa). Short Packet (SPa): • 1st byte: Data Identification (DI) => Identification that this is Short Packet (SPa) • 2nd and 3rd bytes: Packet Data (PD), Data 0 and 1 • 4th byte: Error Correction Code (ECC) Long Packet (LPa): • 1st byte: Data Identification (DI) => Identification that this is Long Packet (LPa) • 2nd and 3rd bytes: Word Count (WC) • 4th byte: Error Correction Code (ECC) Data Identification (DI) Data Identification (DI) is a part of Packet Header (PH) and it consists of 2 parts: • Virtual Channel (VC), 2 bits, DI[7...6] • Data Type (DT), 6 bits, DI[5…0] The Data Identification (DI) structure is illustrated on a table below. 2012/05/11 96 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Data Identification (DI) Structure Virtual Channel (VC) Bit 7 Bit 6 Bit 5 Data Identification (DI) Data Type (DT) Bit 4 Bit 3 Bit 2 NT35310 Bit 1 Bit 0 Data Identification (DI) is illustrated on Packet Header (PH) for reference purposes below. 2012/05/11 97 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Virtual Channel (VC) Virtual Channel (VC) is a part of Data Identification (DI[7…6]) structure and it is used to address where a packet is wanted to send from the MCU. Bit of the Virtual Channel (VC) are illustrated for reference purposes below. Virtual Channel (VC) can address 4 different channels for e.g. 4 different display modules. Devices are using the same virtual channel what the MCU is using to send packets to them e.g. • The MCU is using the virtual channel 0 when it sends packets to this display module • This display module is also using the virtual channel 0 when it sends packets to the MCU This functionality is illustrated below. MCU Long and Short Packets This Display Module Virtual Channel Selector DI[7:6]=VC[1...0]=00b (This display Module) Reserved Reserved Reserved Virtual Channel (VC) Configuration 2012/05/11 98 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Data Type (DT) Data Type (DT) is a part of Data Identification (DI[5…0]) structure and it is used to define a type of the used data on a packet. Bit of the Data Type (DT) are illustrated for reference purposes below. Packet Header (PH) DI 0x29 WC (Least Significant Byte) 0x01 WC (Most Significant Byte) 0x00 ECC 0x06 10010100100000000000000001100000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Data Type (DT) on the Packet Header (PH) 2012/05/11 99 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 This Data Type (DT) also defines what the used packet is: Short Packet (SPa) or Long Packet (LPa). Data Types (DT) are different from the MCU to the display module (or other devices) and vice versa. These Data Type (DT) are defined on tables below. Data Type (DT) from MCU to the Display Module (or Other Devices) Data Type, hex Data Type, binary Description Packet Size 01h 00 0001 Sync Event, V Sync Start Short 11h 01 0001 Sync Event, V Sync End Short 21h 10 0001 Sync Event, H Sync Start Short 31h 11 0001 Sync Event, H Sync End Short 08h 00 1000 End of Transmission (EoT) packet Short 02h 00 0010 Color mode (CM) Off Command Short 12h 01 0010 Color mode (CM) On Command Short 22h 10 0010 Shut Down Peripheral Command Short 32h 11 0010 Turn On Peripheral Command Short 03h 00 0011 Generic Short Write, no parameter Short 13h 01 0011 Generic Short Write, 1 parameter Short 23h 10 0011 Generic Short Write, 2 parameter Short 29h 10 1001 Generic Long Write Long 04h 00 0100 Generic Read, no parameter Short 14h 01 0100 Generic Read, 1 parameter Short 24h 10 0100 Generic Read, 2 parameter Short 05h 00 0101 DCS WRITE, no parameters Short 15h 01 0101 DCS WRITE, 1 parameter Short 06h 00 0110 DCS READ, no parameters Short 37h 11 0111 Set Maximum Return Packet Size Short 09h 00 1001 Null Packet, no data Long 19h 01 1001 Blanking Packet, no data Long 39h 11 1001 DCS Long Write/Write_LUT Command Packet Long 0Eh 00 1110 Packed Pixel Stream,16-bits RGB, 5-6-5 Format Long 1Eh 01 1110 Packed Pixel Stream,18-bits RGB, 6-6-6 Format Long 2Eh 10 1110 Loosely Packed Pixel Stream,18-bits RGB, 6-6-6 Format Long x0h and xFh unspecified xx 0000 xx 1111 DO NOT USE All unspecified codes are reserved Note: 1. The receiver process packets with data type (Generic Write/Read) the same way as data type ( DCS Write / Read). 2. Generic Write/Read with 1 parameter: Payload Bytes = Command + 00h. 3. Generic Write/Read with 2 parameter: Payload Bytes = Command + Parameter. 4. The receiver will ignore packets with data type that neither listed in table above nor in MIPI DSI spec. Data Type (DT) from the Display Module (or Other Devices) to the MCU Note 1,2 1,3 1 1,2 1,3 2012/05/11 100 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 From the Display Module (or Other Devices) to the MCU Hex Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description Short/Lng Packet Abbreviation 02h 0 0 0 0 1 0 Acknowledge with Error Report Short AwER 08h 0 0 1 0 0 0 End of Transmission (EoT) packet Short EoT 1Ch 0 1 1 1 0 0 DCS Read Long Response Long DCSRR-L 21h 1 0 0 0 0 1 DCS Read Short Response, 1 byte returned Short DCSRR1-S 22h 1 0 0 0 1 0 DCS Read Short Response, 2 byte returned Short DCSRR2-S 1Ah 0 1 1 0 1 0 Generic Read Long Response Long GENRR-L 11h 0 1 0 0 0 1 Generic Read Short Response, 1 byte returned Short GENRR1-S 12h 0 1 0 0 1 0 Generic Read Short Response, 2 byte returned Short GENRR2-S The receiver will ignore other Data Type (DT) if they are not defined on tables: “Data Type (DT) from the MCU to the Display Module (or Other Devices)” or “ Data Type (DT) from the Display Module (or Other Devices) to the MCU”. 2012/05/11 101 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Availability of MIPI Data Type for Instruction Code (User Command Set) MIPI Data Type 03h 13h 23h 29h 04h 14h 24h 05h 15h 39h 06h (GENWN-S) (GENW1-S) (GENW2-S) (GENW-L) (GENRN-S) (GENR1-S) (GENR2-S) (DCSWN-S) (DCSW1-S) (DCSW-L) (DCSRN-S) Instruction Code Availability of MIPI Data Type 00h (NOP) 01h (SOFT_RESET) 05h (RDNUMED) 0Ah (GET_POWER_MODE) 0Bh (GET_ADDRESS_MODE) 0Ch (GET_PIXEL_FORMAT) 0Dh (GET_DISPLAY_MODE) 0Eh (GET_SIGNAL_MODE) 0Fh (RDDSDR) 10h (ENTER_SLEEP_MODE) 11h (EXIT_SLEEP_MODE) 12h (ENTER_PARTIAL_MODE) 13h (ENTER_NORMAL_MODE) 20h (EXIT_INVERT_MODE) 21h (ENTER_INVERT_MODE) 22h (ALLPOFF) 23h (ALLPON) 26h (GMASET) 28h (SET_DISPLAY_OFF) 29h (SET_DISPLAY_ON) 2Ah (SET_HORIZONTAL_ADDRESS) 2Bh (SET_VERTICAL_ADDRESS) 2Ch (WRITE_MEMORY_START) 2Dh (SET_RAM_ADDRESS) 2Eh (READ_MEMORY_START) 30h (SET_PARTIAL_AREA) 34h (SET_TEAR_OFF) 35h (SET_TEAR_ON) 36h (SET_ADDRESS_MODE) 38h (EXIT_IDLE_MODE) 39h (ENTER_IDLE_MODE) 3Ah (SET_PIXEL_FORMAT) 3Bh (RGBCTRL) 3Ch (RAMWRC) 3Eh (RAMRDC) 44h (SET_TEAR_SCANLINE) 45h (RDSCL) 4Fh (ENTER_DSTB_MODE) 51h (WRIDSBV) 52h (RDDISBV) 53h (WRCTRLD) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2012/05/11 102 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 MIPI Data Type 03h 13h 23h 29h 04h 14h 24h 05h 15h 39h 06h (GENWN-S) (GENW1-S) (GENW2-S) (GENW-L) (GENRN-S) (GENR1-S) (GENR2-S) (DCSWN-S) (DCSW1-S) (DCSW-L) (DCSRN-S) Instruction Code Availability of MIPI Data Type 54h (RDCTRLD) 55h (WRCABC) 56h (RDCABC) 5Eh (WRCABCMB) 5Fh (RDCABCMB) 60h (WRPFK) 61h (WRKEYBV) 62h (RDKEYBV) 63h (WRCTRLK) 64h (RDCTRLK) 65h (WRLSCC) 66h (RDLSCCM) 67h (RDLSCCL) 70h (RDBWLB) 71h (RDBKX) 72h (RDBKY) 73h (RDWX) 74h (RDWY) 75h (RDRGLB) 76h (RDRX) 77h (RDRY) 78h (RDGX) 79h (RDGY) 7Ah (RDBALB) 7Bh (RDBX) 7Ch (RDBY) 7Dh (RDAX) 7Eh (RDAY) A1h (RDDDBS) A8h (RDDDBC) AAh (RDFCS) AEh (SET EDGE TIMING CTRL) AFh (RDCCS) DAh (RDID1) DBh (RDID2) DCh (RDID3) E1h(IDLEMODE_BL_CTRL) E2h(IDLEMODE_BL_CTRL) E3h(WRALS) E4h(RDALS) EDh (CMD2UNLOCK) FFh( Page status) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Packet Data (PD) on the Short Packet (SPa) Packet Data (PD) of the Short Packet (SPa) is defined after Data Type (DT) of the Data Identification (DI) has indicated that Short Packet (SPa) is wanted to send. Packet Data (PD) of the Short Packet (SPa) consists of 2 data bytes: Data 0 and Data 1. Packet Data (PD) sending order is that Data 0 is sent in the first and the Data 1 is sent in the last. Bit of Data 1 are set to ‘0’ if the information length is 1 byte. 2012/05/11 103 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Packet Data (PD) of the Short Packet (SPa), when the length of the information is 1 or 2 bytes are illustrated for reference purposes below, when Virtual Channel (VC) is 0. Packet Data (PD) information: • Data 0: 35hex (Display Command Set (DCS) with 1 Parameter => DI(Data Type (DT)) = 15hex) • Data 1: 01hex (DCS’s parameter) Packet Header (PH) DI 0x15 Data 0 0x35 Data 1 0x01 ECC 0x1E 10101000101011001000000001111000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) for Short Packet (SPa), 2 Bytes Information 2012/05/11 104 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Data (PD) Information: • Data 0: 10hex (DCS without parameter => DI(Data Type (DT)) = 05hex) • Data 1: 00hex (Null) Packet Header (PH) NT35310 DI 0x05 Data 0 0x10 Data 1 (Always 0x00) 0x00 ECC 0x2C 10100000000010000000000000110100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) for Short Packet (SPa), 1 Byte Information 2012/05/11 105 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Word Count (WC) on the Long Packet (LPa) Word Count (WC) of the Long Packet (LPa) is defined after Data Type (DT) of the Data Identification (DI) has indicated that Long Packet (LPa) is wanted to send. Word Count (WC) indicates a number of the data bytes of the Packet Data (PD) what is wanted to send after Packet Header (PH) versus Packet Data (PD) of the Short Packet (SPa) is placed in the Packet Header (PH). Word Count (WC) of the Long Packet (LPa) consists of 2 bytes. These 2 bytes of the Word Count (WC) sending order is that the Least Significant (LS) Byte is sent in the first and the Most Significant (MS) Byte is sent in the last. Word Count (WC) of the Long Packet (LPa) is illustrated for reference purposes below. Packet Header (PH) DI 0x29 WC (Least Significant Byte) 0x01 WC (Most Significant Byte) 0x00 ECC 0x06 10010100100000000000000001100000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Word Count (WC) on the Long Packet (LPa) Packet Header (PH) Short Packet (SPa) Packet Data LP-11 SoT DI Data 0 Data 1 Short Packet (Spa) Structure Time ECC Long Packet (LPa) LP-11 SoT Packet Header (PH) DI Word Count (WC) ECC LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission EoT LP-11 LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) Data 0, ? WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Time Checksum (CS) EoT LP-11 Packet Data in Short and Long Packets Packet Data 2012/05/11 106 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Error Correction Code (ECC) Error Correction Code (ECC) is a part of Packet Header (PH) and its purpose is to identify an error or errors: • Short Packet (SPa): Data Identification (DI) and Packet Data (PD) bytes (24 bits: D[23…0]) • Long Packet (LPa): Data Identification (DI) and Word Count (WC) bytes (24 bits: D[23…0]) D[23…0] is illustrated for reference purposes below. Error Correction Code (ECC) can recognize one error or several errors and makes correction in one bit error case. Bit (P[7…0]) of the Error Correction Code (ECC) are defined, where the symbol ‘^’ is presenting XOR function (Pn is ‘1’ if there is odd number of ‘1’s and Pn is ‘0’ if there is even number of ‘1’s), as follows. • P7 = 0 • P6 = 0 • P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23 • P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23 • P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23 • P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22 • P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23 • P0 = D0^D1^D2^D4^D5^D7^D10^D11^D13^D16^D20^D21^D22^D23 P7 and P6 are set to ‘0’ because Error Correction Code (ECC) is based on 64 bits value ([D63…0]), but this implementation is based on 24 bits value (D[23…0]). Therefore, there is only needed 6 bits (P[5…0]) for Error Correction Code (ECC). 2012/05/11 107 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH) NT35310 DI 0x05 Data 0 0x10 Data 1 0x00 ECC 0x2C 10100000000010000000000000110100 D0 D1 D2 D4 D5 D7 D10 D11 D13 D16 D20 D21 D22 D23 P0 D0 D1 D3 D4 D6 D8 D10 D12 D14 D17 D20 D21 D22 D23 P1 D0 D2 D3 D5 D6 D9 D11 D12 D15 D18 D20 D21 D22 P2 D1 D2 D3 D7 D8 D9 D13 D14 D15 D19 D20 D21 D23 P3 D4 D5 D6 D7 D8 D9 D16 D17 D18 D19 D20 D22 D23 P4 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D21 D22 D23 P5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 P0 P1 P2 P3 P4 P5 P6 P7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time XOR Functionality on the Short Packet (SPa) Packet Header (PH) DI 0x29 WC (Least Significant Byte) 0x01 WC (Most Significant Byte) 0x00 ECC 0x06 10010100100000000000000001100000 D0 D1 D2 D4 D5 D7 D10 D11 D13 D16 D20 D21 D22 D23 P0 D0 D1 D3 D4 D6 D8 D10 D12 D14 D17 D20 D21 D22 D23 P1 D0 D2 D3 D5 D6 D9 D11 D12 D15 D18 D20 D21 D22 P2 D1 D2 D3 D7 D8 D9 D13 D14 D15 D19 D20 D21 D23 P3 D4 D5 D6 D7 D8 D9 D16 D17 D18 D19 D20 D22 D23 P4 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D21 D22 D23 P5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 P0 P1 P2 P3 P4 P5 P6 P7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time XOR Functionality on the Long Packet (LPa) 2012/05/11 108 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 The transmitter (The MCU or the Display Module) is sending data bits D[23…0] and Error Correction Code (ECC) P[7…0]. The receiver (The Display module or the MCU) is calculate an Internal Error Correction Code (IECC) and compares the received Error Correction Code (ECC) and the Internal Error Correction Code (IECC). This comparison is done when each power bit of ECC and IECC have been done XOR function. The result of this function is PO[7…0]. This functionality, where the transmitter is the MCU and the receiver is the display module, is illustrated for reference purposes below. This Display Module XOR PO 7 MCU DSI Data : D[0...15] Internal ECC ( IECC) Generator PI[0...7] ECC : P[0...7] XOR PO 0 Internal Error Correction Code ( IECC ) on the Display Module ( The Receiver ) The sent data bits (D[15…0]) and ECC (P[7…0]) are received correctly, if a value of the PO[7…0]) is 00h. The sent data bits (D[15…0]) and ECC (P[7…0]) are not received correctly, if a value of the PO[7…0]) is not 00h. ECC P[7…0] 1 1 0 0 0 0 0 0 03h IECC PI[7…0] 1 1 0 0 0 0 0 0 03h XOR(ECC,IECC) =>PO[7…0] 0 0 0 0 0 0 0 0 =00h => No Error L M S S B B Internal XOR Calculation between ECC and IECC Values – No Error ECC P[7…0] 1 1 0 0 0 0 0 0 03h IECC PI[7…0] 1 1 1 1 0 0 0 0 0Fh XOR(ECC,IECC) =>PO[7…0] 0 0 1 1 0 0 0 0 =0Ch => Error L M S S B B Internal XOR Calculation between ECC and IECC Values - Error The received Error Correction Code (ECC) can be 00h when the Error Correction Code (ECC) functionality is not used for data values D[15…0] on the transmitter side. 2012/05/11 109 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 The number of the errors (one or more) can be defined when the value of the PO[7…0] is compared to values on the following table. One Bit Error Value of the Error Correction Code (ECC) Data Bit PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Hex D[0] 0 0 0 0 0 1 1 1 07h D[1] 0 0 0 0 1 0 1 1 0Bh D[2] 0 0 0 0 1 1 0 1 0Dh D[3] 0 0 0 0 1 1 1 0 0Eh D[4] 0 0 0 1 0 0 1 1 13h D[5] 0 0 0 1 0 1 0 1 15h D[6] 0 0 0 1 0 1 1 0 16h D[7] 0 0 0 1 1 0 0 1 19h D[8] 0 0 0 1 1 0 1 0 1Ah D[9] 0 0 0 1 1 1 0 0 1Ch D[10] 0 0 1 0 0 0 1 1 23h D[11] 0 0 1 0 0 1 0 1 25h D[12] 0 0 1 0 0 1 1 0 26h D[13] 0 0 1 0 1 0 0 1 29h D[14] 0 0 1 0 1 0 1 0 2Ah D[15] 0 0 1 0 1 1 0 0 2Ch D[16] 0 0 1 1 0 0 0 1 31h D[17] 0 0 1 1 0 0 1 0 32h D[18] 0 0 1 1 0 1 0 0 34h D[19] 0 0 1 1 1 0 0 0 38h D[20] 0 0 0 1 1 1 1 1 1Fh D[21] 0 0 1 0 1 1 1 1 2Fh D[22] 0 0 1 1 0 1 1 1 37h D[23] 0 0 1 1 1 0 1 1 3Bh One error is detected if the value of the PO[7…0] is on : One Bit Error Value of the Error Correction Code (ECC) and the receiver can correct this one bit error because this found value also defines what is a location of the corrupt bit e.g. • PO[7…0] = 0Eh • The bit of the data (D[23…0]), what is not correct, is D[3] More than one error is detected if the value of the PO[7…0] is not on: One Bit Error Value of the Error Correction Code (ECC) e.g. PO[7…0] = 0Ch. 2012/05/11 110 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.1.4 Packet Data (PD) on the Long Packet (LPa) Packet Data (PD) of the Long Packet (LPa) is defined after Packet Header (PH) of the Long Packet (LPa). The number of the data bytes is defined on chapter “Word Count (WC) on the Long Packet (LPa)”. 5.7.2.3.1.5 Packet Footer (PF) on the Long Packet (LPa) Packet Footer (PF) of the Long Packet (LPa) is defined after the Packet Data (PD) of the Long Packet (LPa). The Packet Footer (PF) is a checksum value what is calculated from the Packet Data of the Long Packet (LPa). The checksum is using a 16-bits Cyclic Redundancy Check (CRC) value which is generated with a polynomial X16+X12+X5+X0 as it is illustrated below. 16bit Cyclic Redundancy Check (CRC) Calculation The 16-bits Cyclic Redundancy Check (CRC) generator is initialized to FFFFh before calculations. The Least Significant Bit (LSB) of the data byte of the Packet Data (PD) is the first bit what is inputted into the 16-bits Cyclic Redundancy Check (CRC). An example of the 16-bits Cyclic Redundancy Check (CRC), where the Packet Data (PD) of the Long Packet (LPa) is 01h, is illustrated (step-by-step) below. 2012/05/11 111 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 A value of the Packet Footer (PF) is 1E0Eh in this example. This example (Command 01h has been sent) is illustrated below. The receiver is calculated own checksum value from received Packet Data (PD). The receiver compares own checksum and the Packet Footer (PF) what the transmitter has sent. The received Packet Data (PD) and Packet Footer (PF) are correct if the own checksum of the receiver and Packet Footer (PF) are equal and vice versa the received Packet Data (PD) and Packet Footer (PF) are not correct if the own checksum of the receiver and Packet Footer (PF) are not equal. 2012/05/11 112 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.2 Packer Transmission 5.8.2.3.2.1 Packet from the MCU to the Display Module Display Command Set (DCS) Display Command Set (DCS), which is defined on chapter “Instruction Description”, is used from the MCU to the display module. This Display Command Set (DCS) is always defined on the Data 0 of the Packet Data (PD), which is included in Short Packet (SPa) and Long packet (LPa) as these are illustrated below. Short Packet (SPa) Packet Header (PH) Packet Data LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) Data 0 and Data 1: Packet Data (8+8 bit) ECC: Error Correction Code (8 bit) EoT: End of Transmission LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11 Short Packet (Spa) Structure Time Long Packet (LPa) LP-11 SoT Packet Header (PH) LP-11: Low Power – Stop State SoT: Start of Transmission DI: Data Identification (8 bit) WC: Word Count (16 bit) ECC: Error Correction Code (8 bit) DI Word Count (WC) ECC Data 0, ? WC-1): Packet Data (0 – 65,535 bytes) CS: Checksum (16 bit) = Packet Footer (PF) EoT: End of Transmission Data 0 Data 1 Data WC-2 Data WC-1 Time Checksum (CS) EoT LP-11 Packet Data Display Command Set (DCS) Display Command Set (DCS) on Short Packet (SPa) and Long Packet (LPa) 2012/05/11 113 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Generic Write, no Parameter (GENW0-S), Data Type = 00 0011 (03h) This data type is useless in normal application. NT35310 Generic Write, 1 Parameter (GENW1-S), Data Type = 01 0011 (13h) “Generic Write, 1 Parameter” (GENW1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0011b), from the MCU to the display module. The content of 2 payload bytes is “command” and 00h. "Generic Write, 1 Parameter” (GENW1-S) is used for Manufacture Command Set (CMD2, means panel function registers) writing only. Since all CMD2 registers are 1 "address" byte with 1 "parameter" byte. Therefore, this data type is useless in normal application. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 0011b • Packet Data (PD) Data 0: “POWER_CTRL15 (10h)”, the Power Control 15 in the page 0 of CMD2” Data 1: Always 00hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 114 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Generic Write, 2 Parameter (GENW2-S), Data Type = 10 0011 (23h) “Generic Write, 2 Parameter” (GENW2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0011b), from the MCU to the display module. The content of 2 payload bytes are “command” and “parameter”. "Generic Write, 2 Parameter” (GENW2-S) is used for Manufacture Command Set (CMD2, means panel function registers) writing only. Note:One Subpixel has been written. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 10 0011b • Packet Data (PD) Data 0: “3-GAMMA-R CTRL15 (3Ah)”, the Red Gamma Control in page 0 of CMD2 Data 1: 01hex, the parameter of the CMD2 • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 115 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Generic Write Long (GENW-L) , Data Type = 10 1001 (29h) “Generic Write Long” (GENW-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 10 1001b), from the MCU to the display module. The content of payload bytes are “command” with multiple “parameter”. “Generic Write Long” (GENW-L) is used for Manufacture Command Set (CMD2, means panel function registers) writing only. Long Packet (LPa), when a command (No Parameter) was sent, is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 10 1001b • Word Count (WC) Word Count (WC): 0001h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “Sleep In (10h)”, Display Command Set (DCS) • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI 0x29 WC (Least Significant Byte) 0x01 WC (Most Significant Byte) 0x00 ECC 0x06 10010100100000000000000001100000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 0 0x10 CRC (Least Significant Byte) CRC (Most Significant Byte) 0x06 0x1F 000010000110000011111000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML M S SS SS S B BB BB B Time Generic Write Long (GENW-L) with CMD2 Only - Example 2012/05/11 116 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Long Packet (LPa), when a Write (1 parameter) was sent, is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 10 1001b • Word Count (WC) Word Count (WC): 0002h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “3-GAMMA-R CTRL15 (3Ah)”, the Red Gamma Control in page 0 of CMD2 Data 1: 01hex, Parameter of the CMD2 • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI 0x29 WC (Least Significant Byte) 0x02 WC (Most Significant Byte) 0x00 ECC 0x00 10010100010000000000000000000000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time NT35310 Packet Data (PD) Data 0 (CMD2) 0x3A Data 1 (Parameter) 0x01 0101110010000000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML M S SS S B BB B Time Packet Footer (PF) CRC (Least Significant Byte) 0xE3 11000111 CRC (Most Significant Byte) 0xAA 01010101 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML M S SS S B BB B Time Generic Write Long with CMD2 and 1 Parameter - Example Generic Read, No Parameter (GENR0-S) , Data Type = 00 0100 (04h); This data type is useless in normal application. Generic Read, 1 Parameter (GENR1-S) , Data Type = 01 0100 (14h); Generic Read, 2 Parameter (GENR2-S) , Data Type = 10 0100 (24h) “Generic Read, 1 Parameter / Generic Read, 2 Parameter” (GENR1-S / GENR2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0100b) and Data Type (DT, 10 0100b), from the MCU to the display module. Generic read data type is used for Manufacture Command Set (CMD2, means panel function registers) reading only. 2012/05/11 117 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 The MCU has to define to the display module, what is the maximum size of the return packet. A command, what is used for this purpose, is “Set Maximum Return Packet Size” (SMRPS-S), which Data Type (DT) is 11 0111b and which is using Short Packet (SPa) before the MCU can send ““Generic Read, 1 Parameter"” to the display module. This same sequence is illustrated for reference purposes below. Step 1: • The MCU sends “Set Maximum Return Packet Size” (Short Packet (SPa)) (SMRPS-S) to the display module when it wants to return one byte from the display module • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 11 0111b • Maximum Return Packet Size (MRPS) Data 0: 01hex Data 1: 00hex • Error Correction Code (ECC) 2012/05/11 118 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Step 2: • The MCU wants to receive a value of the “Read ID1 (DAh)” from the display module when the MCU sends “Generic Read, 1 Parameter” to the display module • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 0100b • Packet Data (PD) Data 0: “Read ID1 (DAh)”, Display Command Set (DCS) Data 1: Always 00hex • Error Correction Code (ECC) Step 3: The display module can send 2 different information to the MCU after Bus Turnaround (BTA) 1. An acknowledge with Error Report (AwER), which is using a Short Packet (SPa), if there is an error to receive a command, See chapter “Acknowledge with Error Report (AwER)” 2. Information of the received command. Short Packet (SPa) or Long Packet (LPa) 2012/05/11 119 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Display Command Set (DCS) Write, No Parameter (DCSWN-S) , Data Type = 00 0101 (05h) “Display Command Set (DCS) Write, No Parameter” is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0101b), from the MCU to the display module. The content of payload bytes are“command” with "00h”. “Display Command Set (DCS) Write, No Parameter” is used for User Command Set (CMD1) writing only. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 00 0101b • Packet Data (PD) Data 0: “ENTER_SLEEP_MODE (10h)”, Display Command Set (DCS) Data 1: Always 00hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 120 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) , Data Type = 01 0101 (15h) “Display Command Set (DCS) Write, 1 Parameter” (DCSW1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0101b), from the MCU to the display module. The content of payload bytes are “command” with one “parameter”. “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” is used for User Command Set (CMD1) writing only. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 0101b • Packet Data (PD) Data 0: “SET_PIXEL_FORMAT (3Ah)”, Display Command Set (DCS) Data 1: 01hex, Parameter of the DCS • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 121 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Display Command Set (DCS) Write Long (DCSW-L) , Data Type = 11 1001 (39h) “Display Command Set (DCS) Write Long” (DCSW-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 11 1001b), from the MCU to the display module. The content of payload bytes are “command” with multiple"parameter”. “Display command Set (DCS) Write Long” (DCSW-L) is used for User Command Set (CMD1) writing only. Long Packet (LPa), when a command (No Parameter) was sent, is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) Word Count (WC): 0001h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “EXTER_SLEEP_MODE (10h)”, Display Command Set (DCS) • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI 0x39 WC (Least Significant Byte) 0x01 WC (Most Significant Byte) 0x00 ECC 0x15 10011100100000000000000010101000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 0 0x10 CRC (Least Significant Byte) CRC (Most Significant Byte) 0x06 0x1F 000010000110000011111000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML M S SS SS S B BB BB B Time Display Command Set (DCS) Write Long (DCSW-L) with DCS Only - Example 2012/05/11 122 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Long Packet (LPa), when a Write (1 parameter) was sent, is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) Word Count (WC): 0002h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “SET_PIXEL_FORMAT (3Ah)”, Display Command Set (DCS) Data 1: 01hex, Parameter of the DCS • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) NT35310 DI 0x39 WC (Least Significant Byte) 0x02 WC (Most Significant Byte) 0x00 ECC 0x13 10010100010000000000000000000000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (CMD2) 0x3A Data 1 (Parameter) 0x01 0101110010000000 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML M S SS S B BB B Time Packet Footer (PF) CRC (Least Significant Byte) CRC (Most Significant Byte) 0xE3 0xAA 1100011101010101 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML M S SS S B BB B Time Display Command Set (DCS) Write Long with DCS and 1 Parameter - Example 2012/05/11 123 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Long Packet (LPa), when a Write (4 parameters) was sent, is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 11 1001b • Word Count (WC) Word Count (WC): 0005h • Error Correction Code (ECC) • Packet Data (PD): Data 0: “PARLINES (30h)”, Display Command Set (DCS) Data 1: 00hex, 1st Parameter of the DCS, Start Column SC[15…8] Data 2: 00hex, 2nd Parameter of the DCS, Start Column SC[7…0] Data 3: 01hex, 3rd Parameter of the DCS, End Column EC[15…8] Data 4: 3Fhex, 4th Parameter of the DCS, End Column EC[7…0] • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. NT35310 2012/05/11 124 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Display Command Set (DCS) Read, No Parameter (DCSRN-S) , Data Type = 00 0110 (06h) “Display Command Set (DCS) Read, No Parameter” (DCSRN-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0110b), from the MCU to the display module. The content of payload bytes are “command” with "00h". Display Command Set (DCS) Read, No Parameter (DCSRN-S) is used for User Command Set (CMD1) reading only. The MCU has to define to the display module, what is the maximum size of the return packet. A command, what is used for this purpose, is “Set Maximum Return Packet Size” (SMRPS-S), which Data Type (DT) is 11 0111b and which is using Short Packet (SPa) before the MCU can send “Display Command Set (DCS) Read, No Parameter” to the display module. This same sequence is illustrated for reference purposes below. Step 1: • The MCU sends “Set Maximum Return Packet Size” (Short Packet (SPa)) (SMRPS-S) to the display module when it wants to return one byte from the display module • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 11 0111b • Maximum Return Packet Size (MRPS) Data 0: 01hex Data 1: 00hex • Error Correction Code (ECC) 2012/05/11 125 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Step 2: • The MCU wants to receive a value of the “Read ID1 (DAh)” from the display module when the MCU sends “Display Command Set (DCS) Read, No Parameter” to the display module • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 00 0110b • Packet Data (PD) Data 0: “Read ID1 (DAh)”, Display Command Set (DCS) Data 1: Always 00hex • Error Correction Code (ECC) Step 3: The display module can send 2 different information to the MCU after Bus Turnaround (BTA) 1. An acknowledge with Error Report (AwER), which is using a Short Packet (SPa), if there is an error to receive a command, See chapter “Acknowledge with Error Report (AwER)” 2. Information of the received command. Short Packet (SPa) or Long Packet (LPa) Null Packet, No Data (NP-L) , Data Type = 00 1001 (09h) “Null Packet, No Data” (NP-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 001001b), from the MCU to the display module. The purpose of this command is keeping data lanes in the high speed mode (HSDT), if it is needed. The display module is ignored Packet Data (PD) what the MCU is sending. Long Packet (LPa), when 5 random data bytes of the Packet Data (PD) were sent, is defined e.g. 2012/05/11 126 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 00 1001b • Word Count (WC) Word Count (WC): 0005hex • Error Correction Code (ECC) • Packet Data (PD): Data 0: 89hex (Random data) Data 1: 23hex (Random data) Data 2: 12hex (Random data) Data 3: A2hex (Random data) Data 4: E2hex (Random data) • Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI 0x09 WC (Least Significant Byte) 0x05 WC (Most Significant Byte) 0x00 ECC 0x30 10010000101000000000000000001100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) 0x30 Data 1 (1st Parameter) 0x23 Data 2 (2nd Parameter) 0x12 Data 3 (3rd Parameter) 0xA2 10010001110001000100100001000101 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) 0xE2 01000111 CRC (Least Significant Byte) 0x59 10011010 CRC (Most Significant Byte) 0x29 10010100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML M S SS SS S B BB BB B Time Null Packet, No Data (NP-L) - Example 2012/05/11 127 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) Sync Events are Short packets and, therefore, can time-accurately represent events like the start and end of sync pulses. As “start” and “end” are separate and distinct events, the length of sync pulses, as well as position relative to active pixel data, e.g. front and back porch display timing, may be accurately conveyed to the peripheral. The Sync Events are defined as follows: • Data Type = 00 0001 (01h) V Sync Start • Data Type = 01 0001 (11h) V Sync End • Data Type = 10 0001 (21h) H Sync Start • Data Type = 11 0001 (31h) H Sync End In order to represent timing information as accurately as possible a V Sync Start event represents the start of the VSA and also implies an H Sync Start event for the first line of the VSA. Similarly, a V Sync End event implies an H Sync Start event for the last line of the VSA. Sync events should occur in pairs, Sync Start and Sync End, if accurate 1054 pulse-length information needs to be conveyed. Alternatively, if only a single point (event) in time is required, a single sync event (normally, Sync Start) may be transmitted to the peripheral. Sync events may be concatenated with blanking packets to convey inter-line timing accurately and avoid the overhead of switching between LPS and HS for every event. Note there is a power penalty for keeping the data line in HS mode, however. Display modules that do not need traditional sync/blanking/pixel timing should transmit pixel data in a high-speed burst then put the bus in Low Power Mode, for reduced power consumption. The recommended burst size is a scan line of pixels, which may be temporarily stored in a line buffer on the display module. 2012/05/11 128 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 EoT Packet, Data Type = 00 1000 (08h) This new short packet is used for indicating the end of a HS transmission to the data link layer. As a result, detection of the end of HS transmission may be decoupled from physical layer characteristics. D-PHY defines an EoT sequence composed of a series of all 1’s or 0’s depending on the last bit of the last packet within a HS transmission. Due to potential errors, the EoT sequence could wrongly be interpreted as valid data types. Although EoT errors are not expected to happen frequently, the addition of this new packet will enhance overall system reliability. Older devices compliant to earlier revisions of DSI specification do not support EoT packet generation or detection. All Hosts and Peripheral devices compliant to this revision of DSI specification, and going forward, shall incorporate capability of supporting EoT packet. They shall also provide means for enabling and disabling this capability – implementation specific – to ensure interoperability with older DSI devices not supporting EoT packet. As mentioned earlier, the main objective of an EoT packet is to enhance overall robustness of the system during HS transmission mode. Therefore, DSI transmitters should not generate an EoT packet when transmitting in LP mode. The data link layer of DSI receivers shall detect and interpret arriving EoT packets regardless of transmission mode (HS or LP modes) in order to decouple itself from the PHY layer. Table below describes how DSI mandates EoT packet support for different transmission and reception modes. EoT Support for Host and Peripheral DSI Host (EoT capability enable) HS Mode LP Mode Receive Transmit Receive Transmit Not Applicable “Shall” “Shall” “Should not” DSI Peripheral (EoT capability enable) HS Mode LP Mode Receive Transmit Receive Transmit “Shall” Not Applicable “Shall” “Should not” Unlike other DSI packets, an EoT packet has a fixed format as follows: • Data Type = DI [5:0] = 0b001000 • Virtual Channel = DI [7:6] = 0b00 • Payload Data [15:0] = 0x0F0F • ECC [7:0] = 0x01 The virtual channel identifier associated with an EoT packet is fixed to 0, regardless of the number of different virtual channels present within the same transmission. For multi-Lane systems, the EoT packet bytes are distributed across multiple Lanes. 2012/05/11 129 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Color Mode On Command, and, Data Type = 01 0010 (12h) Color Mode On is a Short packet command that switches a Video Mode display module to 8-colors mode for power saving. Color Mode Off Command, Data Type = 00 0010 (02h) Color Mode Off is a Short packet command that returns a Video Mode display module from 8-colors mode to normal display operation. Shutdown Peripheral Command, Data Type = 10 0010 (22h) Shutdown Peripheral command is a Short packet command that turns off the display in a Video Mode display module for power saving. Note the interface shall remain powered in order to receive the turn-on, or wake-up, command. Turn On Peripheral Command, Data Type = 11 0010 (32h) Turn On Peripheral command is Short packet command that turns on the display in a Video Mode display module for normal display operation. Blanking Packet (Long), Data Type = 01 1001 (19h) A Blanking packet is used to convey blanking timing information in a Long packet. Normally, the packet represents a period between active scan lines of a Video Mode display, where traditional display timing is provided from the host processor to the display module. The blanking period may have Sync Event packets interspersed between blanking segments. Like all packets, the Blanking packet contents shall be an integer number of bytes. Blanking packets may contain arbitsrary data as payload. The Blanking packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes, and a two-byte checksum. Packed Pixel Stream, 16-bits Format, Long packet, Data Type 1228 pe 00 1110 (0Eh) 1 byte 1 byte LSB MSB LSB MSB 0 4 5 70 2 3 7 R R G GG G B B 0 4 0 23 5 0 4 5 bits 6 bits 5 bits Pixel 1 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte Data Type (0Eh) Virtual Channel Word Count ECC 5 bits 6 bits 5 bits Pixel 1 5 bits 6 bits 5 bits Pixel n Checksum Data ID Packet Header Variable Size Payload Time 16-bit per Pixel – RGB Color Format, Long packet Packet Footer 2012/05/11 130 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Packed Pixel Stream 16-Bits Format is a Long packet used to transmit image data formatted as 16-bits pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte checksum. Pixel format is five bit red, six bit green, five bit blue, in that order. Note that the “Green” component is split across two bytes. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every two bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of two bytes. Normally, the display module has no frame buffer of its own, so all image data shall be supplied by the host processor at a sufficiently high rate to avoid flicker or other visible artifacts. Packed Pixel Stream, 18-bits Format, Long packet, Data type = 01 1110 (1Eh) 1 byte 1 byte LSB MSB LSB MSB 0 5 67 0 34 7 01 R R GG G G B B BB 0 5 0 1 2 5 0 3 45 6 bits 6 bits 6 bits Pixel 1 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (1Eh) Virtual Channel Word Count ECC 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel 1 Pixel 2 Pixel 3 Pixel 4 Data ID Packet Header 1 byte 1 byte 1 byte Variable Size Payload (First Four Pixels Packed in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel n-3 Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Four Pixels Packed in Nine Bytes) Time 18-bit per Pixel (Packed)– RGB Color Format, Long packet Packet Footer 2012/05/11 131 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Packed Pixel Stream 18-Bits Format (Packed) is a Long packet. It is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bits pixels The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. Pixel format is red (6 bits), green (6 bits) and blue (6 bits), in that order. Within a color component, the LSB is sent first, the MSB last. Note that pixel boundaries only align with byte boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent (width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. If the active (displayed) horizontal width is not a multiple of four pixels, the transmitter shall send additional fill pixels at the end of the display line to make the transmitted width a multiple of four pixels. The receiving peripheral shall not display the fill pixels when refreshing the display device. For example, if a display device has an active display width of 399 pixels, the transmitter should send 400 pixels in one or more packets. The receiver should display the first 399 pixels and discard the last pixel of the transmission. With this format, the total line width (displayed plus non-displayed pixels) should be a multiple of four pixels (nine bytes). 2012/05/11 132 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Pixel Stream, 18-bits Format in Three Bytes, Long packet, Data Type = 101110 (2Eh) 1 byte 1 byte 1 byte LSB MSB LSB MSB LSB MSB 01 2 7 01 2 7 01 2 7 R RG GB B 0 50 50 5 6 bits 6 bits 6 bits Pixel 1 NT35310 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (2Eh) Virtual Channel Word Count ECC 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel 1 Pixel 2 Pixel 3 Data ID Packet Header 1 byte 1 byte 1 byte Variable Size Payload (First Three Pixels in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits 6 bits Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Three Pixels in Nine Bytes) Packet Footer Time 18-bit per Pixel (Loosely Packed)– RGB Color Format, Long packet In the 18-bits Pixel Loosely Packed format, each R, G, or B color component is six bits but is shifted to the upper bits of the byte, such that the valid pixel bits occupy bits [7:2] of each byte. Bits [1:0] of each payload byte representing active pixels are ignored. As a result, each pixel requires three bytes as it is transmitted across the Link. This requires more bandwidth than the “packed” format, but requires less shifting and multiplexing logic in the packing and unpacking functions on each end of the Link. This format is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bits pixels. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (6 bits), green (6 bits) and blue (6 bits) in that order. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. Packed Pixel Stream, 24-bits Format, Long packet, Data Type = 11 1110 (3Eh) 2012/05/11 133 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) 1 byte 1 byte 1 byte LSB MSB LSB MSB LSB MSB 0 70 70 7 R RG GB B 0 70 70 7 8 bits 8 bits 8 bits Pixel 1 NT35310 1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte Data Type (3Eh) Virtual Channel Word Count ECC 8 bits 8 bits 8 bits Pixel 1 8 bits 8 bits 8 bits Pixel 2 8 bits 8 bits 8 bits Pixel 3 Data ID Packet Header 1 byte 1 byte 1 byte Variable Size Payload (First Three Pixels in Nine Bytes) Time 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 byte 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits Pixel n-2 Pixel n-1 Pixel n Checksum Variable Size Payload (Last Three Pixels in Nine Bytes) Time 24-bit per Pixel – RGB Color Format, Long packet Packet Footer Packed Pixel Stream 24-Bit Format is a Long packet. It is used to transmit image data formatted as 24-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (8 bits), green (8 bits) and blue (8 bits), in that order. Each color component occupies one byte in the pixel stream; no components are split across byte boundaries. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. Note: NT35310 can accept MIPI DSI 8-8-8 pixel format packet in MIPI Command mode and Video mode. However, due to NT35310's RAM buffer is 18 bits depth per pixel, also the Source driver is 6 bits per channel, therefore only MSB 6 bits of each R/G/B sub-pixel can be stored in memory and displayed in LCD panel. 2012/05/11 134 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.2.2 Packet from the Display Module to the MCU Used Packet Types The display module is always using Short Packet (Spa) or Long Packet (Lpa), when it is returning information to the MCU after the MCU has requested information from the Display Module. This information can be a response of the Display Command Set (DCS) (See chapter “Display Command Set (DCS) Read, No Parameter” (DCSRN-S)) or an Acknowledge with Error Report (See chapter: “Acknowledge with Error Report (AwER)” (AwER)). The used packet type is defined on Data Type (DT). See chapter “Data Type (DT)”. A number of the return bytes are more than the maximum size of the Packet Data (PD) on Long Packet (Lpa) or Short Packet (Spa) when the display module is sending return bytes in several packets until all return bytes have been sent from the display module to the MCU. It is also possible that the display module is sending return bytes in several packets even if the maximum size of the Packet Data (PD) could be sent on a packet. Both cases are illustrated for reference purposes below. Return Bytes LP-11 SoT LPa EoT Return Bytes LP-11 LP-11 SoT SPa EoT LP-11 Return Bytes on Single Packet Return Bytes LP-11 SoT LPa SP EoT Return Bytes LP-11 SoT SPa SPa SPa EoT LP-11 LP-11 Return Bytes on Several Packets – Only for Reference Purposes 2012/05/11 135 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Data Types for Display Module-Sourced Packets Data Type, (HEX) Data Type, (BINARY) Symbol Description 02h 00 0010 AwER Acknowledge & Error Report 08h 00 1000 EoT End of Transmission (EoT) Packet 1Ch 01 1100 DCSRR-L DCS Long Read Response 21h 10 0001 DCSRR1-S DCS Short Read Response, 1 Byte returned 22h 10 0010 DCSRR2-S DCS Short Read Response, 2 Byte returned 1Ah 01 1010 GENRR-L Generic Long Read Response 11h 01 0001 GENRR1-S Generic Short Read Response, 1 Byte returned 12h 01 0010 GENRR2-S Generic Short Read Response, 2 Byte returned NT35310 Packet Size Short Short Long Short Short Long Short Short Acknowledge with Error Report (AwER), Data Type = 00 0010(02h) “Acknowledge with Error Report” (AwER) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0010b), from the display module to the MCU. The Packet Data (PD) can include bit, which are defining the current error, when a corresponding bits is set to ‘1’, as they are defined on the following table. Acknowledge with Error Report (AwER) for Long Packet (LPa) Response Bit Description 0 SoT Error 1 SoT Sync Error 2 EoT Sync Error 3 Escape Mode Entry Command Error 4 Low-Power Transmit Sync Error 5 Any Protocol Timer Time-Out 6 False Control Error 7 Contention is Detected on the Display Module 8 ECC Error, single-bit (detected and corrected) 9 ECC Error, multi-bit (detected, not corrected) 10 Checksum Error (Long packet only) 11 DSI Data Type (DT) Not Recognized 12 DSI Virtual Channel (VC) ID Invalid 13 Invalid Transmission Length 14 Reserved, Set to ‘0’ internally 15 DSI Protocol Violation 2012/05/11 136 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 These errors are only included on the last packet, which has been received from the MCU to the display module before Bus Turnaround (BTA). The display module ignores the received packet which includes error or errors. Acknowledge with Error Report (AwER) of the Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 00 0010b • Packet Data (PD) Bit 8: ECC Error, single-bit (detected and corrected) AwER: 0100h • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 137 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 It is possible that the display module has received several packets, which have included errors, from the MCU before the MCU is doing Bus Turnaround (BTA). Some examples are illustrated for reference purposes below. Packets from the MCU LP-11 SoT LPa SP EoT LP-11 Includes an error Packets from the MCU LP-11 SoT SPa SPa SPa EoT LP-11 Includes an error Errors Packets Therefore, there is needed a method to check if there has been errors on the previous packets. These errors of the previous packets can check “Read Display Signal Mode (0Eh)” and “Read Number of the Errors on DSI (05h)” commands. The bit D0 of the “Read Display Signal Mode (0Eh)” command has been set to ‘1’ if a received packet includes an error. The number of the packets, which are including an error, are calculated on the RDNUMED register, which can read “Read Number of the Errors on DSI (05h)” command. This command also sets the RDNUMED register to 00h as well as set the bits D0 of the “Read Display Signal Mode (0Eh)” command to ‘0’ after the MCU has read the RDNUMED register from the display module. The functionality of the RDNUMED register is illustrated for reference purposes below. Note1: This information can Interface or Packet Level Communication but it is always from the MCU to the display module in this case. Note2: CRC or ECC error. DCS Read Long Response (DCSRR-L), Data Type = 01 1100(1Ch) “DCS Read Long Response” (DCSRR-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 01 1100b), from the display module to the MCU. “DCS Read Long Response” (DCSRR-L) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. 2012/05/11 138 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Long Packet (LPa), which includes 5 data bytes of the Packet Data (PD), is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 1100b • Word Count (WC) Word Count (WC): 0005hex • Error Correction Code (ECC) • Packet Data (PD): Data 0: 89hex Data 1: 23hex Data 2: 12hex Data 3: A2hex Data 4: E2hex • Packet Footer (PF) NT35310 This is defined on the Long Packet (LP) as follows. Packet Header (PH) DI 0x1C WC (Least Significant Byte) 0x05 WC (Most Significant Byte) 0x00 ECC 0x29 00111000101000000000000010010100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) 0x89 Data 1 (1st Parameter) 0x23 Data 2 (2nd Parameter) 0x12 Data 3 (3rd Parameter) 0xA2 10010001110001000100100001000101 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) 0xE2 01000111 CRC (Least Significant Byte) 0x59 10011010 CRC (Most Significant Byte) 0x29 10010100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML M S SS SS S B BB BB B Time DCS Read Long Response (DCSRR-L) - Example DCS Read Short Response, 1 Byte Returned (DCSRR1-S), Data Type = 10 0001(21h) “DCS Read Short Response, 1 Byte Returned” (DCSRR1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0001b), from the display module to the MCU. “DCS Read Short Response, 1 Byte Returned” (DCSRR1-S) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 10 0001b • Packet Data (PD) Data 0: 45hex Data 1: 00hex (Always) • Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. DCS Read Short Response, 2 Bytes Returned (DCSRR2-S), Data Type = 10 0010(22h) “DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is always using a Short Packet (SPa), what is defined on Data Type 2012/05/11 139 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 (DT, 10 0010b), from the display module to the MCU. “DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is used when the display module wants to response a DCS Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 10 0010b • Packet Data (PD) Data 0: 45hex Data 1: 32hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Generic Read Long Response (GENRR-L), Data Type = 01 1010(1Ah) “Generic Read Long Response” (GENRR-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 01 1010b), from the display module to the MCU. “Generic Read Long Response” (GENRR-L) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Long Packet (LPa), which includes 5 data bytes of the Packet Data (PD), is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 1010b • Word Count (WC) Word Count (WC): 0005hex • Error Correction Code (ECC) • Packet Data (PD): Data 0: 89hex Data 1: 23hex Data 2: 12hex Data 3: A2hex Data 4: E2hex • Packet Footer (PF) This is defined on the Long Packet (LP) as follows. 2012/05/11 140 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH) NT35310 DI 0x1A WC (Least Significant Byte) 0x05 WC (Most Significant Byte) 0x00 ECC 0x2F 01011000101000000000000011110100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 (DCS) 0x89 Data 1 (1st Parameter) 0x23 Data 2 (2nd Parameter) 0x12 Data 3 (3rd Parameter) 0xA2 10010001110001000100100001000101 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Packet Footer (PF) Data 4 (4th Parameter) 0xE2 CRC (Least Significant Byte) CRC (Most Significant Byte) 0x59 0x29 010001111001101010010100 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 L ML ML M S SS SS S B BB BB B Time Generic Read Long Response (GENRR-L) - Example Generic Read Short Response, 1 Byte Returned (GENRR1-S), Data Type = 01 0001(11h) “Generic Read Short Response, 1 Byte Returned” (GENRR1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0001b), from the display module to the MCU. “Generic Read Short Response, 1 Byte Returned” (GENRR1-S) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 0001b • Packet Data (PD) Data 0: 45hex Data 1: 00hex (Always) • Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. 2012/05/11 141 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 2012/05/11 142 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Generic Read Short Response, 2 Bytes Returned (GENRR2-S), Data Type = 01 0010(12h) “Generic Read Short Response, 2 Bytes Returned” (GENRR2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0010b), from the display module to the MCU. “Generic Read Short Response, 2 Bytes Returned” (GENRR2-S) is used when the display module wants to response a Generic Read command, which the MCU has sent to the display module. Short Packet (SPa) is defined e.g. • Data Identification (DI) Virtual Channel (VC, DI[7…6]): 00b Data Type (DT, DI[5…0]): 01 0010b • Packet Data (PD) Data 0: 45hex Data 1: 32hex • Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. 2012/05/11 143 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.3 Communication Sequence 5.7.2.3.3.1 General The communication sequences can be done on interface or packet levels between the MCU and the display module. See chapters “Interface Level Communication” and “Packet Level Communication”. This communication sequence description is for DSI data lanes and it has been assumed that the needed low level communication is done on DSI clock lanes (DSI-CLK+/-) automatically. Functions of the interface level communication is described on the following table. Interface Level Communication Interface Mode Abbreviation LP-11 LPDT ULPS Low Power RAR TEE ACK BTA High Speed HSDT Interface Action Description Stop state Low power data transmission Ultra-Low power state Remote application reset Tearing effect event Acknowledge (No error) Bus turnaround High speed data transmission Functions of the packet level communication are described on the following table. Packet Level Communication Packet Sender Abbreviation DCSW1-S DCSWN-S MCU DCSW-L DCSRN-S SMRPS-S NP-L AwER Display Module DCSRR-L DCSRR1-S DCSRR2-S Packet Size SPa SPa LPa SPa SPa LPa SPa LPa SPa SPa Packet Description DCS Write, 1 Parameter DCS Write, No Parameter DCS Write, Long DCS Read, No Parameter Set maximum return packet size Null packet, No data Acknowledge with error report DCS Read, Long Response DCS Read, Short Response DCS Read, Short Response 2012/05/11 144 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.3.3.2 Sequences DCS Write, 1 Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” is defined on chapter “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” and example sequences, how this packet is used, is described on following tables. DCS Write, 1 Parameter Sequence - Example 1 MCU Display Module Line Packet Sender Information Interface Direction Mode Control Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSW1-S LPDT => - - 3 - LP-11 => - - DCS Write, 1 Parameter Sequence - Example 2 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - 2 DCSW1-S HSDT => - - 3 - LP-11 => - - Start End Comment Start End 2012/05/11 145 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DCS Write, 1 Parameter Sequence - Example 3 Line MCU Packet Sender Interface Mode Control Information Direction Display Module Interface Mode Control Packet Sender NT35310 Comment 1 - LP-11 => - - Start 2 DCSW1-S HSDT => - - 3 - LP-11 => - - 4 - BTA <=> BTA Interface control change - from the MCU to the display module 5 - - <= LP-11 - If no error => goto line 7 If error => goto line 12 6 7 - - <= ACK - No error 8 - - <= LP-11 9 - BTA <=> BTA 10 - LP-11 => - - Interface control change - from the display module to the MCU - End 11 12 - - <= LPDT AwER Error report 13 - - <= LP-11 - 14 - BTA <=> BTA - 15 - LP-11 => - - End 2012/05/11 146 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 DCS Write, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” is defined on chapter “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” and example sequences, how this packet is used, is described on following tables. DCS Write, No Parameter Sequence - Example 1 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSWN-S LPDT => - - 3 - LP-11 => - - Start End DCS Write, No Parameter Sequence - Example 2 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - 2 DCSWN-S HSDT => - - 3 - LP-11 => - - Comment Start End 2012/05/11 147 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DCS Write, No Parameter Sequence - Example 3 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - NT35310 Comment Start 2 DCSWN-S HSDT => - - 3 - LP-11 => - - 4 - BTA <=> BTA Interface control change - from the MCU to the display module 5 - - <= LP-11 - If no error => goto line 7 If error => goto line 12 6 7 - - <= ACK - No error 8 - - <= LP-11 9 - BTA <=> BTA 10 - LP-11 => - - Interface control change - from the display module to the MCU - End 11 12 - - <= LPDT AwER Error report 13 - - <= LP-11 - 14 - BTA <=> BTA - 15 - LP-11 => - - End 2012/05/11 148 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 DCS Write Long Sequence A Long Packet (LPa) of “Display Command Set (DCS) Write Long (DCSW-L)” is defined on chapter “Display Command Set (DCS) Write Long (DCSW-L)” and example sequences, how this packet is used, is described on following tables. DCS Write, Long Sequence - Example 1 MCU Line Packet Sender Interface Mode Control Information Direction Display Module Interface Mode Control Packet Sender Comment 1 - LP-11 => - - 2 DCSW-L LPDT => - - 3 - LP-11 => - - DCS Write, Long Sequence - Example 2 MCU Line Packet Sender Interface Mode Control Information Direction Display Module Interface Mode Control Packet Sender Start End Comment 1 - LP-11 => - - 2 DCSW-L HSDT => - - 3 - LP-11 => - - Start End 2012/05/11 149 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. DCS Write, Long Sequence - Example 3 MCU Line Packet Sender Interface Mode Control Draft Version Information Direction Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - NT35310 Comment Start 2 DCSW-L HSDT => - - 3 - LP-11 => - - 4 - BTA <=> BTA Interface control change - from the MCU to the display module 5 - - <= LP-11 - If no error => goto line 7 If error => goto line 12 6 7 - - <= ACK - No error 8 - - <= LP-11 9 - BTA <=> BTA 10 - LP-11 => - - Interface control change - from the display module to the MCU - End 11 12 - - <= LPDT AwER Error report 13 - - <= LP-11 - 14 - BTA <=> BTA - 15 - LP-11 => - - End 2012/05/11 150 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. DCS Write, Long Sequence - Example 4 MCU Line Packet Sender Interface Mode Control Draft Version Information Direction Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - 2 DCSW-L HSDT => - - 3 DCSW-L HSDT => - - 4 DCSW-L HSDT => - - 5 DCSW1-S HSDT => - - 6 - LP-11 => - - NT35310 Comment Start Memory Write (2Ch) Memory Write Continue(3Ch) Memory Write Continue(3Ch) Memory Write Continue(3Ch) with 1 parameter End 2012/05/11 151 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 DCS Read, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” is defined on chapter “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” and example sequences, how this packet is used, is described on following tables. DCS Read, No Parameter Sequence - Example 1 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender Comment 1 - LP-11 => 2 SMRPS-S HSDT => 3 DCSRN-S HSDT => 4 - LP-11 => 5 - BTA <=> 6 - - <= 7 8 - - <= 9 - - <= 10 - BTA <=> BTA LP-11 LPDT LP-11 BTA - Start - Define how many data byte is wanted to read : 1 byte - wanted to get a response ID1 (DAh) - Interface control change - from the MCU to the display module - If no error => goto line 8 If error => goto line 13 DCSRR1-S - - Response 1 byte return Interface control change from the display module to the MCU 11 - LP-11 => - - End 12 13 - - <= LPDT AwER 14 - - <= LP-11 - 15 - BTA <=> BTA - 16 - LP-11 => - - Error report End 2012/05/11 152 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DCS Read, No Parameter Sequence - Example 2 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - 2 SMRPS-S HSDT => - - 3 DCSRN-S HSDT => - - 4 - LP-11 => - - 5 - BTA <=> BTA - 6 - 7 8 - 9 - 10 - - BTA <= LP-11 - <= LPDT DCSRR-L <= LP-11 - <=> BTA - NT35310 Comment Start Define how many data byte is wanted to read : 200 byte wanted to get a response "Memory Read" (2Eh) Interface control change from the MCU to the display module If no error => goto line 8 If error => goto line 13 Response 200 bytes return Interface control change from the display module to the MCU 11 - LP-11 => - - End 12 13 - - <= LPDT AwER 14 - - <= LP-11 - 15 - BTA <=> BTA - 16 - LP-11 => - - Error report End 2012/05/11 153 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DCS Read, No Parameter Sequence - Example 3 MCU Line Packet Sender Information Interface Direction Mode Control Display Module Interface Mode Control Packet Sender 1 - LP-11 => - - 2 SMRPS-S HSDT => - - 3 DCSRN-S HSDT => - - 4 - LP-11 => - - 5 - BTA <=> BTA - 6 - - <= LP-11 - 7 8 - - <= LPDT DCSRR-L 9 - - <= LPDT DCSRR-L NT35310 Comment Start Define how many data byte is wanted to read : 200 byte wanted to get a response "Memory Read" (2Eh) Interface control change from the MCU to the display module If no error => goto line 8 If error => goto line 14 Response 100 bytes return Response 100 bytes return 10 - - <= LP-11 - 11 - BTA <=> BTA Interface control change - from the display module to the MCU 12 - LP-11 => - - End 13 14 - - <= LPDT AwER Error report 15 - - <= LP-11 - 16 - BTA <=> BTA - 17 - LP-11 => - - End 2012/05/11 154 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DCS Read, No Parameter Sequence - Example 4 MCU Line Packet Sender Interface Mode Control Information Direction Display Module Interface Mode Control Packet Sender NT35310 Comment 1 - LP-11 => - - Start 2 SMRPS-S HSDT => - - Define how many data byte is wanted to read : 200 byte 3 DCSRN-S HSDT => - - wanted to get a response "Memory Read" (2Eh) 4 - LP-11 => - - 5 - BTA <=> BTA Interface control change - from the MCU to the display module 6 - - <= LP-11 - If no error => goto line 8 If error => goto line 14 7 8 - - <= LPDT DCSRR-L Response 199 bytes return 9 - - <= LPDT DCSRR1-L Response 1 byte return 10 - - <= LP-11 - 11 - BTA <=> BTA Interface control change - from the display module to the MCU 12 - LP-11 => - - End 13 14 - - <= LPDT AwER Error report 15 - - <= LP-11 - 16 - BTA <=> BTA - 17 - LP-11 => - - End 2012/05/11 155 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 DCS Read, No Parameter Sequence - Example 4 MCU Line Packet Sender Interface Mode Control Information Direction 1 - LP-11 => 2 SMRPS-S HSDT => 3 DCSRN-S HSDT => 4 - LP-11 => 5 - BTA <=> 6 - - <= 7 8 - - <= 9 - - <= 10 - - <= Display Module Interface Mode Control Packet Sender - - - - - - - - BTA - LP-11 - Comment Start Define how many data byte is wanted to read : 200 byte wanted to get a response "Memory Read" (2Eh) Interface control change from the MCU to the display module If no error => goto line 8 If error => goto line 14 LPDT LPDT LP-11 DCSRR-L DCSRR2-L - Response 198 bytes return Response 2 bytes return 11 - BTA <=> BTA - Interface control change from the display module to the MCU 12 - LP-11 => - - 13 14 - - <= LPDT AwER 15 - - <= LP-11 - 16 - BTA <=> BTA - 17 - LP-11 => - - End Error report End Null Packet, No Data Sequence A Long Packet (LPa) of “Null Packet, No Data (NP-L)” is defined on chapter “Null Packet, No Data (NP-L)” and example sequences, how this packet is used, is described on following tables. Null Packet, No Parameter Sequence - Example MCU Line Packet Sender Interface Mode Control Information Direction Display Module Interface Packet Mode Control Sender 1 - LP-11 => - - 2 NP-L HSDT => - - 3 - LP-11 => - - Comment Start Only high speed data transmission is used. End 5.7.2.4 Video Mode Communication Video Mode peripherals require pixel data delivered in real time. This section specifies the format and timing of DSI traffic for this type of display module. 5.7.2.4.1 Transmission Packet Sequences DSI supports several formats, or packet sequences, for Video Mode data transmission. The peripheral’s timing requirements dictate which format is appropriate. In the following sections, Burst Mode refers to time-compression of the RGB pixel (active video) portion of the transmission. In addition, these terms are used throughout the following sections: • Non-Burst Mode with Sync Pulses – enables the peripheral to accurately reconstruct original video timing, including sync pulse widths. • Non-Burst Mode with Sync Events – similar to above, but accurate reconstruction of sync pulse widths is not required, so a single Sync Event is substituted. • Burst mode – RGB pixel packets are time-compressed, leaving more time during a scan line for LP mode (saving power) or for multiplexing other transmissions onto the DSI link. In the following figures the Blanking or Low-Power Interval (BLLP) is defined as a period during which video packets such as pixel-stream and sync event packets are not actively transmitted to the peripheral. To enable PHY synchronization the host processor 2012/05/11 156 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 should periodically end HS transmission and drive the Data Lanes to the LP state. This transition should take place at least once per frame; shown as LPM in the figures in this section. It is recommended to return to LP state once per scanline during the horizontal blanking time. Regardless of the frequency of BLLP periods, the host processor is responsible for meeting all documented peripheral timing requirements. Note, at lower frequencies BLLP periods will approach, or become, zero, and burst mode will be indistinguishable from non-burst mode. During the BLLP the DSI Link may do any of the following: • Remain in Idle Mode with the host processor in LP-11 state and the peripheral in LP-RX • Transmit one or more non-video packets from the host processor to the peripheral using Escape Mode • Transmit one or more non-video packets from the host processor to the peripheral using HS Mode • If the previous processor-to-peripheral transmission ended with BTA, transmit one or more packets from the peripheral to the host processor using Escape Mode • Transmit one or more packets from the host processor to a different peripheral using a different Virtual Channel ID The sequence of packets within the BLLP or RGB portion of a HS transmission is arbitsrary. The host processor may compose any sequence of packets, including iterations, within the limits of the packet format definitions. For all timing cases, the first line of a frame shall start with VS; all other lines shall start with HS. This is also true in the special case when VSA+VBP=0. Note that the position of synchronization packets, such as VS and HS, in time is of utmost importance since this has a direct impact on the visual performance of the display panel. Normally, RGB pixel data is sent with one full scan line of pixels in a single packet. If necessary, a horizontal scanline of active pixels may be divided into two or more packets. However, individual pixels shall not be split across packets. Transmission packet components used in the figures in this section are defined in Figure below unless otherwise specified. V S V E BL LP H S H S A H E H F P H B P R G B L P M Low Power Mode including optional BTA DSI Packet: Arbitrary sequence of pixel stream and Null Packets DSI Blanking Packet: Horizontal Back Porch DSI Blanking Packet: Horizontal Front Porch DSI Sync. Event: Horizontal Sync. End DSI Blanking Packet: Horizontal Sync. Active, No data DSI Sync. Event: Horizontal Start DSI Packet: Arbitrary sequence of non-restricted DSI packets or Low Power Mode including optional BTA. DSI Sync. Event: Packet V Sync. End. DSI Sync. Event: Packet V Sync. Start. DSI Video Mode Interface Timing Legend If a peripheral timing specification for HBP or HFP minimum period is zero, the corresponding Blanking Packet may be omitted. If the HBP or HFP maximum period is zero, the corresponding blanking packet shall be omitted. 5.7.2.4.2 Non-Burst Mode with Sync Pulses With this format, the goal is to accurately convey DPI-type timing over the DSI serial Link. This includes matching DPI pixel-transmission rates, and widths of timing events like sync pulses. Accordingly, synchronization periods are defined using packets transmitting both start and end of sync pulses. An example of this mode is shown in Figure below. 2012/05/11 157 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. tL tL tL tL Draft Version tL * (VSA+VBP+VACT+VFP) tL V BL H BL S LP S LP V BL H BL E LP S LP H BL S LP VSA Lines VBP Lines Active Video Area NT35310 tL tL tL H BL S LP H S BL LP H S B L L P L P M VFP Lines tL tHSA tHBP tHACT tHFP H S H S A H E H B P RGB HFP H S H S A H E H B P VACT Lines RGB HFP DSI Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End Normally, periods shown as HSA (Horizontal Sync Active), HBP (Horizontal Back Porch) and HFP (Horizontal Front Porch) are filled by Blanking Packets, with lengths (including packet overhead) calculated to match the period specified by the peripheral’s data sheet. Alternatively, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 5.7.2.4.3 Non-Burst Mode with Sync Events This mode is a simplification of the format described in section 5.8.2.4.2 “Non-Burst Mode with Sync Pulse” .Only the start of each synchronization pulse is transmitted. The peripheral may regenerate sync pulses as needed from each Sync Event packet received. Pixels are transmitted at the same rate as they would in a corresponding parallel display interface such as DPI-2. An example of this mode is shown in Figure below. tL * (VSA+VBP+VACT+VFP) tL tL tL tL tL tL tL tL V BL H BL S LP S LP H BL H BL S LP S LP H BL S LP VSA Lines VBP Lines Active Video Area H BL S LP H S BL LP H S B L L P L P M V S VFP Lines tL tHBP tHACT tHFP H S H B P RGB HFP H S H B P VACT Lines RGB HFP DSI Video Mode Interface Timing: Non-burst Transmission As with the previous Non-Burst Mode, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 2012/05/11 158 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.2.4.4 Burst Mode In this mode, blocks of pixel data can be transferred in a shorter time using a time-compressed burst format. This is a good strategy to reduce overall DSI power consumption, as well as enabling larger blocks of time for other data transmissions over the Link in either direction. There may be a line buffer or similar memory on the peripheral to accommodate incoming data at high speed. Following HS pixel data transmission, the bus goes to Low Power Mode, during which it may remain idle, i.e. the host processor remains in LP-11 state, or LP transmission may take place in either direction. If the peripheral takes control of the bus for sending data to the host processor, its transmission time shall be limited to ensure data underflow does not occur from its internal buffer memory to the display device. An example of this mode is shown in Figure below. tL * (VSA+VBP+VACT+VFP) tL tL tL tL tL tL tL tL V BL H BL S LP S LP H BL H BL S LP S LP H BL S LP VSA Lines VBP Lines Active Video Area H BL S LP H S BL LP H S B L L P L P M V S VFP Lines tL tHBP tHACT tHFP H S H B P RGB BLLP HFP H S H B P RGB VACT Lines BLLP HFP DSI Video Mode Interface Timing: Burst Transmission Similar to the Non-Burst Mode scenario, if there is sufficient time to transition from HS to LP mode and back again, a timed interval in LP mode may substitute for a Blanking Packet, thus saving power. 5.7.2.4.5 Parameters Below table documents the parameters used in the preceding figures. Peripheral supplier companies are responsible for specifying suitable values for all blank fields in the table. The host processor shall meet these requirements to ensure interoperability. 2012/05/11 159 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Required Peripheral Timing Parameters (Base on 320RGB x 480) Symbol Parameter Condition Min BRPHY Bit rate total on all Lanes HVGA+ (320RGB x 480) 80 tL Line time HVGA+ (320RGB x 480) - tHBP tHACT HACT tHFP VSA Horizontal back porch Time for image data Active pixels per line Horizontal front porch Vertical sync active HVGA+ (320RGB x 480) 1 1 data lane 15 HVGA+ (320RGB x 480) 1 1 NT35310 Typ - 34 (Note 1) 320 - Max 500 - (Note 3) - Units Mbps us us us pixels us H VBP Vertical back porch TBD - - H VACT Active lines per frame HVGA+ (320RGB x 480) 480 H VFP Vertical front porch Note 1: Frame rate (Typ) = 60Hz Note 2: VBP (min) value can change by register. Note 3: tHACT (max)= tL-tHFP- tHBP TBD - - H 5.7.2.4.6 Video mode ON/OFF sequence In MIPI DSI interface, If host wants to enter/exit Video mode, please used the Bypass and DM commands and follow the flow as below. Video:Vsync Video:Vsync Figure 5.8.2.4.1Turn on sequence in MIPI DSI Video mode 2012/05/11 160 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. N-2 Draft Version Display data from Host Display data from Host N-1 N Video: Hsync and Frame data Video: Hsync and Frame data NT35310 Display data from GRAM N+1 Video:Vsync Video:Vsync Video:Vsync Video mode Frame data GRAM data Figure 5.7.2.4.1 Shutdown sequence in MIPI DSI Video mode Command mode GRAM data 2012/05/11 161 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.7.3 Memory access for DSI 5.7.3.1 Memory write format Different display data formats are available for three colors depth supported by the NT35310 listed below. 65k colors, RGB 5-6-5-bits input. Register command 3Ah=”05h” 262k colors, RGB 6-6-6-bits input. Register command 3Ah=”06h” 5-6-5-bits (65K colors) 1 Pixel Data N (Red[4:0] + Green[5:3]) Data N+1 (Green[2:0] + Blue[4:0]) GGGRRRRRB B B B BGGG 3450123401234012 L ML M S SS S B BB B Time One Pixel Bit and Color Write Orders 6-6-6-bits (262K colors) 1 Pixel Data N (Red[5:0]) Data N (Green[5:0]) Data N (Blue[5:0]) RRRRRR 012345 GGGGGG 012345 BBBBBB 012345 L ML ML M S SS SS S B BB BB B Time One Pixel Bit and Color Write Orders 8-8-8-bits (16.7M colors) 1 Pixel Data a(n)-Red Data a(n+1)-Green Data a(n+2)-Blue RRRRRRRRGGGGGGGGB B B B B B B B 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time One Pixel Bit and Color Write Orders Note: NT35310 can accept MIPI DSI 8-8-8 pixel format packet in MIPI Command mode and Video mode. However, due to NT35310's RAM buffer is 18 bits depth per pixel, also the Source driver is 6 bits per channel, therefore only MSB 6 bits of each R/G/B sub-pixel can be stored in memory and displayed in LCD panel. 2012/05/11 162 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 5.7.3.2 Memory writing/Reading 24 bit/pixel writing 1 Pixel Draft Version NT35310 Data a(n)-Red Data a(n+1)-Green Data a(n+2)-Blue RRRRRRRRGGGGGGGGB B B B B B B B 012345670123456701234567 L ML ML M S SS SS S B BB BB B Time One Pixel Bit and Color Write Orders The MCU can send to the display module a following packet Packet Header (PH) DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39hex (DCSW-L) 04hex 00hex 2Chex 10011100001000000000000000110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 – DCS (Note1) Data 1 - Red Data 2 - Green Data 3 - Blue 2Chex (Memory Write) 23hex 12hex A2hex 00110100110001000100100001000101 B B B B B B B B RRRRRRRRGGGGGGGGB B B B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Footer (PF) CRC(Least Significant Byte) CRC(Most Significant Byte) 20hex D7hex 00 0 0 0 1 0 0 1 1 1 0 1 0 1 1 BB B B B B B B B B B B B B B B 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 L ML M S SS S B BB B Time One Pixel Write (DCSW-L) Notes: 1. Memory Write (2Ch) or Memory Write Continue (3Ch) 2. It is possible that one pixel information is split in two or three different packets which are ending and starting as follows: • R – GB (2 packets) • RG – B (2 packets) • R – G – B (3 packets) 3. Packet can include several pixels (Not only one pixel as in this example) 2012/05/11 163 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH) Packet Data NT35310 DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Blue 21hex 10101000001111001000000010000100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Blue Subpixel Write (DCSW1-S) Notes: 1. DCS (Data 0) cannot be “Memory Write” (2Ch) command. It must always be “Memory Write Continue”(3Ch) 2. Previous data byte was G[0:7] Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Blue 21hex 10101000001111001000000010000100 BB B B B B B B B BB B B B B BGGGGGGGGB BB B B B B B 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Green Subpixel Write (DCSW1-S) Notes: 1. DCS (Data 0) cannot be “Memory Write” (2Ch) command. It must always be “Memory Write Continue”(3Ch) 2. Previous data byte was R[0:7] Packet Header (PH) Packet Data DI Data 0 (DCS) Data 1 (Parameter) ECC 15hex (DCSW1-S) 3Chex (Memory Write Continue) 01hex - Blue 21hex 10101000001111001000000010000100 BBBBBBBBBBBBBBBBRRRRRRRRBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Red Subpixel Write (DCSW1-S) Note: DCS (Data 0) can also be “Memory Write Continue” (3Ch) command 2012/05/11 164 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 18 bits/pixel writing Draft Version The MCU can send to the display module a following packet Example1: One pixel write Packet Header (PH) NT35310 DI WC(Least Significant Byte) WC(Most Significant Byte) ECC 39 hex( DCSW-L) 04hex 00hex 2 Chex 10011100001000000000000000110100 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0 – DCS( Note1) 2C hex (Memory Write) 001101000 BBBBBBBB 01234567 L ML S SS B BB Data 1- Red 20 hex 00001000 RRRRRR 012345 ML SS BB Data 2 - Green 10 hex 00010000 GGGGGG 012345 ML SS BB Data 3 - Blue A0 hex 0000101 BBBBBB 012345 M S B Time Packet Footer(PF) CRC (Least Significant Byte) ) CRC (Most Significant Byte) 20hex D7hex 00 0 0 0 1 0 0 1 1 1 0 1 0 1 1 BB B B B B B B B B B B B B B B 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 L ML M S SS S B BB B Time One Pixel Write ( DCSW-L) Notes: 1. Memory Write (2Ch) or Memory Write Continue (3Ch) 2. It is possible that one pixel information is split in two or three different packets starting as follows: • R – GB (2 packets) • RG – B (2 packets) • R – G – B (3 packets) 3. Packet can include several pixels (Not only one pixel as in this example) Example2: Blue sub-pixel write 2012/05/11 165 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH) Packet Data NT35310 DI Data 0 ( DCS) Data 1 (Parameter) ECC 15 hex( DCSW1-S ) 3Chex (Memory Write Continue) ) 04 hex- Blue 21hex 10101000001111000010000010000100 BBBBBBBBBBBBBBBB 0123456701234567 BBBBBBBBBBBBBB 01234501234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Blue Subpixel Write ( DCSW1-S) Note: DCS (Data 0) cannot be “Memory Write” (2Ch) command. It must always be “Memory Write Continue” (3Ch) Example3: Green sub-pixel write Packet Header (PH) Packet Data DI 15 hex ( DCSW1-S) Data 0 ( DCS) Chex (Memory Write Continue) Data 1 ( Parameter) 04 hex - Green ECC 21 hex 101 01 00 00 01111 000 B B B B B BB B B B B B B B B B 0 123 45 67 01234 567 L ML ML S SS SS B BB BB 010 0000 100 00 100 G GGG GG B B B B B B B B 0 1 23 4 5 0 1 2 3 4 5 67 ML M SS S BB B Time Green Subpixel Write ( DCSW1-S) Note: DCS (Data 0) cannot be “Memory Write” (2Ch) command. It must always be “Memory Write Continue” (3Ch) Example4: Red sub-pixel write Packet Header(PH ) Packet Data DI Data 0 ( DCS) Data 1 ( Parameter) ECC 15 hex ( DCSW1-S) 2Chex (Memory Write) 04 hex- Red 21 hex 1 01 01 00 00 0 1101 00 00 10 0 00 01 0 0 00 100 B B B B B BB B B B B B B B B B 0 123 45 67 01 2345 67 R RR RRR BB B B B B B B 01 23 45 01 23 4 567 L ML ML ML M S SS SS SS S B BB BB BB B Time Red Subpixel Write (DCSW1-S) Note: DCS (Data 0) can also be “Memory Write Continue” (3Ch) command 2012/05/11 166 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 18 bits/pixel Reading 1 Pixel Draft Version NT35310 Data a (n) - Red Data a(n+1) - Green Data a (n+2) - Blue 0 0 R 0 R 1 R 2 R 3 R 4 R 5 0 0 G 0 G 1 G 2 G 3 G 4 G 5 0 0 B 0 B 1 B 2 B 3 B 4 B 5 L ML ML M S SS SS S B BB BB B Time One Pixel Bit and Color Read Orders The display module can send to the MCU following packets after the MCU has sent a read command “Memory Read (2Eh)” or “Memory Read Continue (3Eh)”. Packet Header ( PH) DI WC(Least Significant Byte) WC( Most Significant Byte ) ECC 1Chex (DCSRR-L) 03hex 00hex 16hex 00111000110000000000000001101000 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 01234567012345670123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Packet Data (PD) Data 0- Red Data 1 - Green Data 2- Blue 2Chex 20hex 10hex 001101000000010000001000 0 0 R 0 RR 12 RRR 345 0 0 G 0 G 1 G 2 G 3 G 4 G 5 0 0 B 0 B 1 B 2 B 3 B 4 B 5 L ML ML M S SS SS S B BB BB B Time Packet Footer (PF) CRC(Least Significant Byte) )CRC( Most Significant Byte) DBhex 10hex 11 0 1 1 0 1 1 0 0 0 0 1 0 0 0 BB B B B B B B B B B B B B B B 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 L ML M S SS S B BB B Time One Pixel Read Response (DCSRR-L) Note: It is possible that one pixel information is split in two or three different packets: • R – GB (2 packets) • RG – B (2 packets) • R – G – B (3 packets) 2012/05/11 167 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH ) Packet Data DI Data 0 Data1 ECC 21 hex( DCSRR1-S) 04 hex- Red 00hex 14hex 10000100001000000000000010000100 BBBBBBBB0 0 RRRRRRBBBBBBBBBBBBBBBB 01234567 0123450123456701234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Red Subpixel Response ( DCSRR1-S) Note: Data 1 is always 00h Packet Header (PH) Packet Data DI Data 0 Data 1 ECC 21 hex( DCSRR1-S) 04 hex- Green 00 hex 14 hex 1 00 0 0 1 00 0 0 1 000 0 0 0 0 00 00 00 1 0 0 00 1 00 B B B B B BB B 0 0GGGGGGB B B B B B B B BB B B B B B B 0 12 3 4 5 67 0 12 3 4 5 0 1 2 3 45 6 7 0 1 2 3 4 5 67 L ML ML ML M S SS SS SS S B BB BB BB B Time Green Subpixel Response (DCSRR1-S) Note: Data 1 is always 00h Packet Header (PH) Packet Data DI Data 0 Data 1 ECC 21 hex( DCSRR1-S) 04 hex - Blue 00 hex 14 hex 1 00 0 0 1 0 0 0 0 1 00 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 00 BB B B BBB B 0 0 B BB B B BB B B BB B B BBB B BB B B B 0 12 3 4 5 6 7 0 12 3 4 5 0 1 2 3 45 6 7 0 1 2 3 4 5 67 L ML ML ML M S SS SS SS S B BB BB BB B Time Blue Subpixel Response (DCSRR1-S) Note: Data 1 is always 00h Packet Header (PH ) Packet Data DI 22 hex ( DCSRR2-S) Data0 Data 1 10 hex- Red (Pixel n) 50 hex- Green (Pixel n) ECC 0 Ahex 01000100000010000000101001010000 B B B B B B B B 0 0 RRRRRR 0 0 GGGGGGB B B B B B B B 01234567 012345 01234501234567 L ML ML ML M S SS SS SS S B BB BB BB B Time Red and Green Subpixels Response (DCSRR2-S) NT35310 2012/05/11 168 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Packet Header (PH) Packet Data DI Data 0 Data 1 ECC 22 hex(DCSRR2-S) 10 hex- Green (Pixel n) 50 hex- Blue (Pixel n) 0 Ahex 01000100000010000000101001010000 BB 01 B 2 B 3 BB 45 B 6 B 7 0 0 G 0 G 1 G 2 G 3 G 4 G 5 0 0 B 0 B 1 B 2 B 3 B 4 B 5 B 0 B 1 B 2 B 3 B 4 BB 56 B 7 L ML ML ML M S SS SS SS S B BB BB BB B Time Green and Blue Subpixels Response (DCSRR2-S) Packet Header (PH) Packet Data DI Data0 Data1 ECC 22 hex(DCSRR2-S) 10 hex- Blue (Pixel n) 50 hex- Red (Pixel n +1) 0 Ahex 01000100000010000000101001010000 B 0 B 1 B 2 B 3 B 4 B 5 B 6 B 7 0 0 B 0 B 1 B 2 B 3 B 4 B 5 0 0 R 0 R 1 RR 23 R 4 R 5 B 0 B 1 B 2 B 3 B 4 B 5 B 6 B 7 L ML ML ML M S SS SS SS S B BB BB BB B Time Blue and Red Subpixels Response (DCSRR2-S) NT35310 2012/05/11 169 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.8 Dynamic Backlight Control Function The NT35310 supports Backlight-Control function to control brightness of backlight and to process image dynamically. This function enables to reduce backlight power consumption and minimize the effect of reduced power on the display image. The display image is dynamically controlled by CABC (Contents Adaptive Backlight Control) block. The availability of this function ranges from moving picture such as TV image to still picture such as menu. However, in order to gain a better display quality and reduce the power consumption of the backlight, the NT35310 internally uses NVT gamma algorithm to produce an optimal backlight control based on different image contents. Therefore, the power consumption of the backlight can be reduced without changing display image. The Backlight-Control function of the NT35310 supports two architectures as shown in below: Architecture 1: The brightness of backlight can directly be controlled by CABC block of the NT35310. The NT35310 will output the PWM duty via “ LEDPWM” pin, and output a “Enable/Disable” signal via “LEDON pin”. The PWM duty is determined by CABC processed results based on different image contents. As for this application, user also can set/clear the bit “BL” of register 53h to turn on/off the backlight. Besides, the user can control the brightness of the backlight by forcing a specified PWM duty. Architecture 2: The brightness of the backlight is controlled by the external host processor. In this application, the CABC block of the NT35310 also works and estimates a better gamma setting for improving the brightness of display image, the determined PWM duty information can be read from the RDPW of the NT35310. Because the backlight is controlled by host processor, user can clear the bit “BL” of the register 53h for keeping the “LEDPWM” and “LEDON” pins as ground level. LEDPWM LEDO N 2012/05/11 170 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.8.1 Content Adaptive Backlight Control (CABC) A Content Adaptive Brightness Control (CABC) function can be used to reduce the power consumption of the luminance source. Content adaptation means that content grey level scale can be increased while simultaneously decreasing brightness of the backlight to achieve same perceived brightness. The adjusted grey level scale and thus the power consumption reduction depend on the content of the image. The NVT CABC algorithm can adjust the brightness of each gray level without changing the original image contents. The NVT CABC function provides three operation modes, and these modes can be selected by the register 5500h. See command “Write Content Adaptive Brightness Control (5500h)” (CABC_COND[1 : 0]) for more information. These three modes are described as: - Off Mode: Content Adaptive Brightness Control functionality is completely turn-off. In this mode, the NT35310 will use the original Gamma 2.2 registers setting for display. And if the function of “forced PWM duty” is turn-off (i.e. “FORCE_CABC_PWM” is set as ‘0’), the PWM duty of the “LEDPWM” pin is 100%. - UI [User interface] Image Mode (UI Mode): This mode is applied to optimize for UI image. It is kept image quality as much as possible. Target power consumption reduction ratio: 10% or less. NT35310 provides flexible configuration for UI-Mode via setting the register to choose prefer quality and brightness. - Still Picture Mode (Still Mode): This mode is used to gain a better display quality for still picture. Some image quality degradation would be acceptable. Target power consumption reduction ratio: more than 30%. The NT35310 will automatically determine a better gamma setting and PWM duty based on different image contents, so the reduction ratio of the power consumption of backlight is not a constant ratio, this ratio will vary between 10% ~ 40% with different image contents. - Moving Image Mode (Moving Mode): User can select this mode to keep the moving image quality and reduce the power consumption of backlight. It is focused on the biggest power reduction with image quality degradation. Target power consumption reduction ratio: more than 30%. For this mode, user can flexibly configure a specified gamma algorithm to keep prefer image quality, and the brightness of backlight is dynamically varying with different image contents. If the “force PWM duty” function is enabled (i.e. “FORCE_CABC_PWM” is set as ‘1’) in any CABC mode, the output PWM duty of “LEDPWM” pin is followed the setting of “FORCE_CABC_DUTY[7 : 0]”. Note: The CABC can be operated only in the normal mode. 2012/05/11 171 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.8.2 Display Backlight Dimming Control A dimming function (how fast to change the brightness from old to new level and what are brightness levels during the change) is used when changing from one brightness level to another. This dimming function curve is the same in increment and decrement directions. The basic concept is described below. Dimming function can be enabled and disabled by setting the register 5300h (the setting bit name is “DD”). If “DD” is set as ‘0’, the dimming function will be disabled, otherwise dimming function will be enabled while “DD” = ‘1’. From the original brightness value to the target brightness value, the transferring time steps between these two brightness values are equal making the linearly transition.The rising dimming (increament dimming) and the falling dimming (decreament dimming) use the same registers for setting (“DIM_STEP_STILL[2:0] and DMST_C[3 : 0]”, or “DIM_STEP_MOV[2:0] and DMST_C[3 : 0]”). The Fig. 5.6.1 and Fig 5.6.2 illustrate the “Fixed-Time” dimming curves for CABC each mode. Figure 5.8.2 Dimming Mechanism in CABC Off-Mode / UI-Mode and Still-Mode Figure 5.8.2 Dimming Mechanism in CABC Moving-Mode 2012/05/11 172 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.8.3 Brightness Control Lines for Backlight The NT35310 have a “LEDPWM” pin which can output a PWM signal to the external LED driver IC. There are several control registers which are applied to control the “LEDPWM” and “LEDON” status as illustrated in below. Figure 5.8.3 Internal Display Backlight Control Combined With CABC and Manu The control bit “BL” is used to keep the LEDPWM in a fixed logic state, here are listed some application in below table: BL LEDPWPOL Status of LEDPWM 0 0 0 (Default) 0 1 1 1 0 Original polarity of PWM signal 1 1 Inversed polarity of PWM signal In the same way, “BL” is used to make the LEDON in a fixed logical state, here are listed some application in below table: BL LEDONPOL Status of LEDON 0 0 0 (Default) 0 1 1 0 1 LEDONR 1 1 Inversed LEDONR The setting bit “PWM_ENH_OE” is applied to improvement the driving ability of LEDPWM signal, here are listed two driving ability for selection: PWM_ENH_OE Status of LEDON 0 1X driving ability of LEDPWM 1 2X driving ability of LEDPWM The setting bit “LEDPWM_OEB” is applied to choose Hi-Z or output enable for “LEDPWM” pins, default 0 (output enable). LEDPWM pin output LEDPWPOL=0 & LEDPWM_OEB=0 LEDPWPOL=1 & LEDPWM_OEB=0 LEDPWM_OEB=1 (BL=1 and BCTRL=1 ) CABC off 0x55=0 VDDI (LEDPWM_duty=100%) GND (LEDPWM_duty=0%) outputs Hi-Z (BL=1 and BCTRL=1) CABC on 0x55=1,UI mode 0x55=2,still mode 0x55=3,moving mode PWM waveform (active high) PWM waveform (active low ) outputs Hi-Z CMB[7 : 0] (WRCABCMB[7 : 0]): This register setting is used to limit the minimum PWM duty in order to prevent the backlight brightness too dark. 2012/05/11 173 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 The registers PWMDIV[7 : 0] and PWM_DUTY_OFFSET[4 : 0] can change the frequency and duty compensation of the PWM signal. The PWM operation frequency “FOSC” is “not” the real PWM frequency, the “F OSC” is used to provide clock source for the internal PWM circuit. Two PWM operation frequency can be choosen by setting register “PWMF”, and the real PWM frequency can be quickly estimated by the bellow formula: PWMF Setting 0 1 PWM Operation Frequency (FOSC) 3.25 MHz 6.5 MHz Real PWM Frequency of LEDPWM PWM Freuency  3.25 MHz 256  PWMDIV[7 : 0] PWM Freuency  6.5MHz 256  PWMDIV[7 : 0] For Example: If the “PWMDIV[7 : 0]” = 0x0C, and “PWMF” = “1”, then: PWM Freuency  6.25 MHz  6.25 MHz  2.034 KHz 256  PWMDIV[7 : 0] 256 12 In this condition, when PWM duty is estimated as “4” (Reading the register “RDDISBV[7 : 0]” = 03h), then the duty time of the PWM signal can be estimated as shown in below: PWM Duty Time  4  1  7.6 sec 256 2.034 KHz PWM Non - Duty Time  (256 - 4)  1  483.9  sec 256 2.034 KHz The same, when PWM frequency is 3.255 KHz, and PWM duty of LEDPWM is 256 (Reading the register “RDDISBV[7 : 0]” = FFh), then the duty time can be estimated as shown in below: PWM Duty Time  (256)  1  307.2 sec 256 3.255 KHz 2012/05/11 174 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PWM_DUTY_OFFSET[4 : 0]: Because the external LED driver needs some stable time to drive the LED backlight, this necessary stable time will reduce the effective PWM duty period, so the PWM_DUTY_OFFSET[4 : 0] is used to compensate effective PWM duty. An example is shown in Fig. 5.4.2. When PWM duty of LEDPWM signal is 60%, the backlight brightness should be 60% of original. But user may find that the backlight brightness is 57% of original. So user can set PWM_DUTY_OFFSET[4 : 0] and let the backlight brightness becomes 60% of original. 60% 57% PWM_DUTYP_WOMF_FDSUETT[Y4_:O0F]F=SnEoTn[4-z:e0ro] =va0lue 60% PWM Duty Ratio (%) Figure 5.7.4 Duty Compensation of LEDPWM Signal 2012/05/11 175 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.9 Window Address Function The window address function allows writing RAM data consecutively within the window address area which are determined by setting the horizontal address register (XSA and XEA) and vertical address register (YSA and YEA). The MV, MX and MY bit determine the transition direction of the RAM address (refer to register 36h). The RAM address (XAD[8:0], YAD[8:0]) must be set within the window address area, and the window address must be made within the GRAM address map area. For 360RGB x 480 resolution: [Window address area setting range] (Horizontal direction)  0000h ≤ XSA ≤ XEA ≤ 013Fh (Vertical direction)  0000h ≤ YSA ≤ YEA ≤ 01DFh [RAM Address setting range] (RAM address)  XSA ≤ XAD[8:0] ≤ XEA YSA ≤ YAD[8:0] ≤ YEA 2012/05/11 176 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.10 Reduced Power Consumption Drive Settings The NT35310 supports various methods for reducing power consumption. Generally speaking, a balance will need to be found between reduced power consumption and display quality. In addition, the power consumption also depends on the characteristics of the panel. Review the various methods to determine which one will provide the optimal balance between reduced power consumption and display quality. Frame Rate Setting The NT35310 is able to change the liquid crystal polarity inversion cycle by setting the RTN bit to change the frame frequency. Setting a lower frequency in the partial display operation will reduce power consumption. For more information, refer to “Frame-Frequency Adjustment Frequency.” 5.11 Frame-Frequency Adjustment Function The NT35310 provides a function to adjust the frame frequency for driving liquid crystal by setting the RTN bits without changing the oscillation frequency. Changing the frame frequency is permissible when a moving picture or still picture is displayed on the screen; a high oscillation frequency should be set in this case. By changing the RTN settings, the NT35310 can function at a low frame frequency to display a still picture (reducing power consumption), and at a high frame frequency when displaying a moving picture (which requires data to be rewritten at high speed). Relationship between Liquid Crystal Drive Duty and the Frame Frequency The formula below is used to calculate the relationship between the liquid crystal drive duty and the frame frequency. The frame frequency is determined by setting the 1H period adjustment (RTN) bit. Equation for calculating frame frequency FrameFrequency  13MHz / 3 5%  RTN * Lines  BP  FP Hz RTN: Number of clocks per line. Line: Display Line Number FP: Number of lines for front porch. BP: Number of lines for back porch. 2012/05/11 177 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.12 GAMMA Function The structure of grayscale amplifier is shown as below. The 18 voltage levels between GVDDP/GVDDN and VGSP/VGSN determined by the gradient adjustment register, the reference adjustment register, the amplitude adjustment resister and the micro-adjustment register. 255 x R GVDDP / GVDDN Regulator V0 R V1 R V2 R V3 V 62 R V 63 R V 64 V 127 R V 128 R V 129 R V 253 R V254 R V255 VGSP / VGSN Regulator Figure 5.12.1 Gamma Architecture for NT35310 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 DAC 256 to 1 V0 ~ 255 V0 V1 V2 V4 V6 V8 V 12 V 20 V 28 V 36 V 44 V 52 V 56 V 58 V 60 V 61 V 62 V 63 2012/05/11 178 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.13 Reset Function The RESET function of NT35310 is triggered by a RESX input. After reset function triggered, the NT35310 enter a reset period, and the duration of this period must be at least 1ms. During this period, the NT35310 and its power circuit is initialized. In the meanwhile, because the NT35310 will be in a busy state, neither instruction from MPU nor GRAM data access request are not acceptable. In addition, for power-on reset case, there will be a 20 ms period for oscillator to be stable. Therefore, any instructions or GRAM access request must be made after this 20 ms period is over. Initial States of Output Pins. The following table represent the output pins and its initial state Output Pins Initial State Liquid crystal driver (Source driver output) All output VSS Liquid crystal driver (Gate driver output) All output VSS AVDD VCI AVEE Disabled (VSS level output) VCOM Disabled (VSS level output) GVDDP Disabled (VSS level output) GVDDN Disabled (VSS level output) VGH VCI VGL VSS VCL VSS VDD VDD VLPH VDD TE Disabled (VSS level output) SDO Hi-Z D17-0,SDI Hi-Z Initial States of Input / Output Pins The following table represent the input/output pins and its initial state 2012/05/11 179 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Input/Output Pins C11P/M C12P/M C13P/M C21P/M C22P/M Initial State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note: The initial states of input/output pins listed above are proper under the condition that LCD module is connected as shown in the connection example. Initial State of Instruction Set The initial state of instruction set is listed in next chapter, and the default values are shown in the parenthesis of each instruction bit cell. Initial State of RAM Data The data in RAM is not automatically initialized in RESET period, and must be initialized by software before display-on instruction is made. 2012/05/11 180 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.14 Basic Operation Mode The basic operation mode of NT35310 is illustrated below. When changing from one mode to another, make sure to follow the sequence indicated in the figure. Figure 5.14.1 2012/05/11 181 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.15 Power On/Off Sequence The power supply ON/OFF setting for Display ON/OFF, Standby Set/Exit, and Sleep Set/Exit sequences is illustrated in figure below. Power ON sequence Power Supply ON 10 ms or more Hardware reset Sleep out command Set EXIT_ SLEEP_ MODE (11h) 10 ms or more Display on command SET_ DISPALY_ ON (29h) Normal Display Power OFF sequence Normal Display Display off command SET_ DISPLAY_ OFF(28h) Sleep in command ENT_ SLEEP_ MODE (10h) Power Supply OFF 4 frames or more Figure 5.15.1 Power Supply Setting Sequence 2012/05/11 182 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.16 Instruction Setting Sequence When setting instruction to the NT35310, the sequences shown in below figures must be followed to complete the instruction setting. 5.16.1 Sleep SET/EXIT Sequences Sleep mode sequence Display OFF Sequence Sleep In Command: ENT_SLEEP_MODE(10h) Sleep Out Command: EXIT_SLEEP_MODE(11h) Delay10 mS or more Display ON Sequence Figure 5.16.1 Sleep SET/EXIT Sequences 2012/05/11 183 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.16.2 Deep Standby Mode ENTER/EXIT Sequences Set Display Off (28h) NT35310 Enter Sleep- In Mode ( Set ENTER_ SLEEP_ MODE (10h)) Enter Deep Standby Mode ( Set ENTER_ DSTB_ MODE(4Fh ) =0x01) Exit Deep Standby Mode (Set RESX pin low pulse more than 3 msec) Initial Instruction Setting, and RAM Data Setting Display- On Sequence Figure 5.16.2 Deep Standby Mode ENTER/EXIT Sequences 1st1poswt eprouwpeRr uepseRt epseertiopderiod -10 ms~+10ms InInitiitaialilzizee Operating Enter Deep standby Exit Deep standby VDDI VCI >20us RESX MDDI >10ms > 10ms Host SLPOUT wakeup cmd Initial setting >6Frame Send DISP ON MDDI Image cmd shutdown > 4 Frame …… DISP Off SLPIN …… cmd cmd DSB=1 Figure 5.16.3 Enter/Exit Deep standby mode sequence. >3 ms 2012/05/11 184 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.17 MTP Write Sequence The NT35310 provides 1 time to store Power and gamma setting related register and DDB information. And 4 times MTP to store VCOM,ID1, ID2 and ID3 information. The table 5.18.1 shows what register setting could be stored in MTP for each MTP programming procedures. Table 5.18.1 MTP Stored Contents MTP Programming MTP Storage Contents for Each Time MTP Programming First Time MTP Programming GAMMA,CABC,VCOM,ID1, ID2 and ID3,WRDDB,POWER_Control Second Time MTP Programming VCOM,ID1, ID2 and ID3,WRDDB,POWER_Control Third Time MTP Programming VCOM,ID1, ID2 and ID3,WRDDB Forth Time MTP Programming VCOM,ID1, ID2 and ID3,WRDDB 2012/05/11 185 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.17.1 First Time MTP Programming Sequence (for all MTP) Start NT35310 Power On And Hardware Reset Wait for more than 150msec IInitialized Registers (CMD1 or CMD2)for User Application ( If necessary ) Wait for more than 50msec Sleep - Out Wait for more than 150msec Display- Off Enter CMD2 and Optimize Register Setting No Read and check Setting Register value Yes Added external :7.5 V Power Source to MTP_PWR Pin Wait for more than 120msec Read NV Memory Flag Status (DDh) ( NVP_ F =1) NVP_ F= 0 NVP_ F =1 (1) Enable GMA Write(Set reg B8h= 01h) (2) Enable MTP Write(Set reg DFh=01h) (3) EPWRITE Command(Set reg Deh parameter1 = , 55h, parameter2 = AAh, parameter3 = 66h Wait for more than 200msec Wait for more than 150msec Hardware Reset or Software Reset Wait for more than 150msec (1) Enter CMD2_P0 (Set EDh=01h+FEh) (2) Margin read Set Register B8h = 04h Sleep- Out Wait for more than 150msec (1) Enter CMD2 and check all register are correct (2)Check Register DDh: NV_N0 = 1,NV_N1 = 0,NV_N2 = 0,NV_N3 = 0 Re- excute MTP programming process End Read NV Memory Flag Status (DDh) (NV_P = 1) NV_ P = 0 NV_P = 1 (1) Disable MTP Write (Set reg DFh = 00h) (2) Remove External : 7.5 V Power Source From_MTP_PWR Pin Note1: During this step, user have to ensure that all registers are optimal for display, because most registers “only” have one MTP programming chances. Note2: MTP GAMMA,please set B8h=01h before MTP Write. 2012/05/11 186 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.17.2 Second Time MTP Programming Sequence Start NT35310 Power On And Hardware Reset Wait for more than 150msec IInitialized Registers (CMD1 or CMD2)for User Application ( If necessary ) Wait for more than 50msec Sleep - Out Wait for more than 150msec Display- Off Enter CMD2 and Optimize Register Setting No Such as VCOM,ID1,ID2,ID3 Read and check Setting Register value Yes Added external :7.5 V Power Source to MTP_PWR Pin Wait for more than 120msec Read NV Memory Flag Status (DDh) ( NVP_ F =1) NVP_ F= 0 NVP_ F =1 (1) Enable MTP Write(Set reg DFh=01h) (2) EPWRITE Command(Set reg Deh parameter1 = , 55h, parameter2 = AAh, parameter3 = 66h Wait for more than 200msec Wait for more than 150msec Hardware Reset or Software Reset Wait for more than 150msec (1) Enter CMD2_P0 (Set EDh=01h+FEh) (2) Margin read Set Register B8h = 04h Sleep- Out Wait for more than 150msec (1) Enter CMD2 and check all register are correct (2)Check Register DDh: NV_N0 = 1,NV_N1 = 1,NV_N2 = 0,NV_N3 = 0 Re- excute MTP programming process End Read NV Memory Flag Status (DDh) (NV_P = 1) NV_ P = 0 NV_P = 1 (1) Disable MTP Write (Set reg DFh = 00h) (2) Remove External : 7.5 V Power Source From_MTP_PWR Pin 2012/05/11 187 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.17.3 Third Time MTP Programming Sequence (Only for VCOM, ID and WRDDB) Start NT35310 Power On And Hardware Reset Wait for more than 150msec IInitialized Registers (CMD1 or CMD2)for User Application ( If necessary ) Wait for more than 50msec Sleep - Out Wait for more than 150msec Display- Off Enter CMD2 and Optimize Register Setting No Such as VCOM,ID1,ID2,ID3 Read and check Setting Register value Yes Added external :7.5 V Power Source to MTP_PWR Pin Wait for more than 120msec Read NV Memory Flag Status (DDh) ( NVP_ F =1) NVP_ F= 0 NVP_ F =1 (1) Enable MTP Write(Set reg DFh=01h) (2) EPWRITE Command(Set reg Deh parameter1 = , 55h, parameter2 = AAh, parameter3 = 66h Wait for more than 200msec Wait for more than 150msec Hardware Reset or Software Reset Wait for more than 150msec (1) Enter CMD2_P0 (Set EDh=01h+FEh) (2) Margin read Set Register B8h = 04h Sleep- Out Wait for more than 150msec (1) Enter CMD2 and check all register are correct (2)Check Register DDh: NV_N0 = 1,NV_N1 = 1,NV_N2 = 1,NV_N3 = 0 Re- excute MTP programming process End Read NV Memory Flag Status (DDh) (NV_P = 1) NV_ P = 0 NV_P = 1 (1) Disable MTP Write (Set reg DFh = 00h) (2) Remove External : 7.5 V Power Source From_MTP_PWR Pin 2012/05/11 188 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.17.4 Fourth Time MTP Programming Sequence (Only for VCOM, ID and WRDDB) Start Power On And Hardware Reset Wait for more than 150msec IInitialized Registers (CMD1 or CMD2)for User Application ( If necessary ) Wait for more than 50msec Sleep - Out Wait for more than 150msec Display- Off Enter CMD2 and Optimize Register Setting No Such as VCOM,ID1,ID2,ID3 Read and check Setting Register value Yes Added external :7.5 V Power Source to MTP_PWR Pin Wait for more than 120msec Read NV Memory Flag Status (DDh) ( NVP_ F =1) NVP_ F= 0 NVP_ F =1 (1) Enable MTP Write(Set reg DFh=01h) (2) EPWRITE Command(Set reg Deh parameter1 = , 55h, parameter2 = AAh, parameter3 = 66h Wait for more than 200msec Wait for more than 150msec Hardware Reset or Software Reset Wait for more than 150msec (1) Enter CMD2_P0 (Set EDh=01h+FEh) (2) Margin read Set Register B8h = 04h Sleep- Out Wait for more than 150msec (1) Enter CMD2 and check all register are correct (2)Check Register DDh: NV_N0 = 1,NV_N1 = 1,NV_N2 = 1,NV_N3 = 1 Re- excute MTP programming process End Read NV Memory Flag Status (DDh) (NV_P = 1) NV_ P = 0 NV_P = 1 (1) Disable MTP Write (Set reg DFh = 00h) (2) Remove External : 7.5 V Power Source From_MTP_PWR Pin 2012/05/11 189 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 5.18 Instruction Setup Flow 5.18.1 Initializing with the Build-in Power Supply Circuit Initializing Start ( Power ON ) ‧ Power Input : VDDI and VCI Wait Until Power Stabilization ‧ RESX =“ L” Wait for more than 10us ‧ RESX = “ H” H/W Rest NT35310 Power Supply Set ‧ EXIT_SLEEP _MODE (Sleep mode OFF & OSC /Booster On ) Display Environment Set (If not used, can be skipped) ‧ ENTER _INVERT _MODE / EXIT _INVERT _MODE (Display Inversion / Normal Set ) ‧ ENTER _IDLE _MODE / EXIT _IDLE _MODE (ldle Mode On /Off ) ‧ ENTER _PARTIAL _MODE / EXIT _PARTIAL _MODE (Partial On /Off ) ‧ SET _ADDRESS _MODE (memory Data Access Control ) - Row direction (MY ), column direction (MX ), address direction (MV), scan direction ML)( and RGB order ‧ SET _PIXEL _FORMAT (Interface Pixel Format Set ) ‧ SET _GAMMA _CURVE (GAMMA 1.0, 1.8, 2.2, 2.5 curve select ) ‧ SET _TEAR _ON / SET _TEAR _OFF (Tearing effect function on /off ) ‧ SET _TEAR _SCANLINE (set the FTE output position ) ‧ If CABC / LABC is enable , set related command (ex. WRDISBV ...etc .) Display Data Write& Display On ‧ SET_COLUMN _ADDRESS / SET _ROW _ADDRESS (Row /Column Address Set ) - Start /end row address set (YS, YE ), Start /end column address set (XS , XE ) ‧ WRITE_MEMORY _START (Memory Data Write ) Wait for more than 10 ms after power control command ‧ SET_DISPLAY _ON (Display ON ) Initializing End 2012/05/11 190 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 5.18.2 Power Off Sequence Draft Version Power OFF Start ( Without H / W Reset ) ‧ SET _ DISPLAY _ OFF ( Display OFF ) NT35310 ‧ ENTER _ SLEEP _ MODE ( Sleep IN ) . Wait for more than 5 Stop the Power Supply : VCC , VCI , VDDI and VDDAM stop ( any order ) Power OFF End Power OFF Start ( With H / W Reset ) ‧ RESX = “ L " ‧ RESX = “ H " . Wait for more than 5 Stop the Power Supply : VCC , VCI , VDDI and VSSAM stop ( any order ) Power OFF End 2012/05/11 191 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.19 SLEEP OUT–COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE 5.19.1 Register loading Detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. There are compared factory values of the EEPROM and register values of the display controller by the display controller. If those both values (EEPROM and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following: Sleep In (10h) Power on sequence HW reset SW reset Sleep Out Mode Sleep In Mode RDDSDR s D7=0 Load EEPROM values to register No Sleep Out (11h) Compares EEPROM and register values Are EEPROM and Register values same ? Yes D7 inverted Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module. 2012/05/11 192 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 5.19.2 Functionality Detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is following: Sleep In (10h) Power on sequence HW reset SW reset Sleep Out Mode Sleep In Mode RDDSDR’ s D6=0 Sleep Out (11h) Check timings, voltage levels And other functionalities No Is functionality Requirement met ? Yes D6 inverted Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode. 2012/05/11 193 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 6. Command Descriptions For intergrating 2 High Speed Serial Interface, MIPI [8bits format] and MDDI [16Bits format], an algorithm of register mapping is implemented in NT35310. As for MIPI interface, the main difference for host to access these 2 groups of command sets is the Data type of the packets. The address mapping of registers for these 2 command sets is summarized as table below: Command Table XXh XXh + 1 Parameter XXh + 2 Parameters XXh + n Parameters (n > 2) User Command Set (CMD1) MIPI / CPU / SPI Interface MIPI Type Address Parameter 8-bits 8-bits DCS WRT, No Parameter Address XXh DCS WRT, 1 Parameter Address Parameter XXh PA1h Address XXh DCS LONG WRT with 2 Parameters Parameter 1 Parameter 2 PA1h PA2h DCS LONG WRT with n Parameters Address Parameter 1 Parameter 2 Parameter 3 Parameter 4 : Parameter n-th XXh PA1h PA2h PA3h PA4h : PAnh Address Parameter Address Address Parameter Address Parameter 1 Address Parameter 2 Address Parameter 1 Address Parameter2 Address Parameter3 Address Parameter4 : : MDDI 16-bits 16-bits XX00h XX00h PA1h XX00h PA1h XX01h PA2h XX00h PA1h XX01h PA2h XX02h PA3h XX03h PA4h : : CMD2 Unlock DCS WRT, 1 Parameter Address Parameter Parameter EDh 01h FEh Address Parameter n Address Parameter Address Parameter XXXnh PAnh ED00h 0001h ED01h 00FEh 2012/05/11 194 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Command Table XXh XXh + 1 Parameter XXh + 2 Parameters XXh + n Parameters (n > 2) Manufacture Command Set (Register of CMD2) MIPI / CPU / SPI Interface MIPI Type Address Parameter 8-bits 8-bits Address Parameter Generic Short Write Address XXh Address Generic Short Write, 1 Parameter Address Parameter XXh PA1h Address Parameter Address XXh Address Generic Short Write, 2 Parameter Parameter 1 Parameter 2 PA1h PA2h Parameter 1 Address Parameter 2 Address Parameter 1 XXh PA1h Address Parameter 1 Parameter 2 PA2h Address Parameter 3 Parameter 4 PA3h PA4h Parameter2 Address Generic Long Write n Parameters : Parameter n-th : PAnh Parameter3 Address Parameter4 : : Address Parameter n NT35310 MDDI 16-bits 16-bits XX00h XX00h PA1h XX00h PA1h XX01h PA2h XX00h PA1h XX01h PA2h XX02h PA3h XX03h PA4h : : XXXnh PAnh 2012/05/11 195 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 6.1 User Command Set (Command 1) Other Interface MDDI I/F CMD Parameter Address Instruction 00h 01h 04h 05h 0Ah 1st Parameter 2nd Parameter 3rd Parameter 1st Parameter 1st Parameter 0000h 0100h 0400h 0401h 0402h 0500h 0A00h NOP SOFT_REST RDID1 RDID2 RDID3 RDNUMED GET_POWER_MODE 0Bh 1st Parameter 0B00h GET_ADDRESS_MODE MDDI D[15 : D7 8] 00h ID17 00h 1 00h ID37 00h P7 00h D7 00h D7 D6 ID16 ID26 ID36 P6 D6 D6 D5 D4 D3 No Argument No Argument ID15 ID14 ID13 ID25 ID24 ID23 ID35 P5 D5 ID34 P4 D4 ID33 P3 D3 D5 D4 D3 D2 ID12 ID22 ID32 P2 D2 D2 D1 ID11 ID21 ID31 P1 D1 D1 0Ch 1st Parameter 0C00h GET_PIXEL_FORMAT 00h D7 D6 D5 D4 D3 D2 D1 0Dh 1st Parameter 0D00h GET_DISPLAY_MODE 00h D7 D6 D5 D4 D3 D2 D1 0Eh 1st Parameter 0Fh 10h 11h 12h 1st Parameter - 13h - 20h 21h 22h 23h 26h 28h 29h 2Ah 2Bh 1st Parameter 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 2Ch - 2Dh 2Eh 30h 33h 34h 35h 36h 37h 38h 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter 6th Parameter 1st Parameter 1st Parameter 1st Parameter 2nd Parameter - 0E00h GET_SIGNAL_MODE 00h 0F00h RDDSDR 00h 1000h ENTER_SLEEP_MODE 1100h EXIT_SLEEP_MODE 1200h ENTER_PARTIAL_MODE 1300h ENTER_NORMAL_MODE 2000h EXIT_INVERT_MODE 2100h ENTER_INVERT_MODE 2200h ALLPOFF 2300h ALLPON 2600h GAMSET 2800h SET_DISPLAY_OFF 2900h SET_DISPLAY_ON 2A00h 00h 2A01h SET_HORIZONTAL_ADDRE 00h 2A02h SS 00h 2A03h 00h 2B00h 00h 2B01h 00h SET_VERTICAL_ADDRESS 2B02h 00h 2B03h 00h 2C00h WRITE_MEMORY 00h START 2D00h 00h 2D01h SET_MDDI_RAM_READ_A 00h 2D02h DDRESS 00h 2D03h 00h 2E00h READ_MEMORY_START 00h 3000h 00h 3001h 00h SET_PARTIAL_AREA 3002h 00h 3003h 00h 3300h 00h 3301h 00h 3302h 00h SCRLAR 3303h 00h 3304h 00h 3305h 00h 3400h SET_TEAR_OFF 3500h SET_TEAR_ON 00h 3600h SET_ADDRESS_MODE 00h 3700h 00h VSCSAD 3701h 00h 3800h EXIT_IDLE_MODE D7 D7 0 XSA7 0 XEA7 0 YSA7 0 YEA7 D6 D6 0 XSA6 0 XEA6 0 YSA6 0 YEA6 D5 D4 D3 D5 D4 D3 No Argument No Argument No Argument No Argument No Argument No Argument No Argument No Argument GC[7:0] No Argument No Argument 0 0 0 XSA5 XSA4 XSA3 0 0 0 XEA5 XEA4 XEA3 0 0 0 YSA5 YSA4 YSA3 0 0 0 YEA5 YEA4 YEA3 D7 D6 D5 D4 D3 0 XAD7 0 YAD7 D7 0 PSL7 0 PEL7 0 TFA7 0 VSA7 0 BFA7 TEW3 MY 0 SSA7 0 XAD6 0 YAD6 D6 0 PSL6 0 PEL6 0 TFA6 0 VSA6 0 BFA6 TEW2 MX 0 SSA6 0 0 0 XAD5 XAD4 XAD3 0 0 0 YAD5 YAD4 YAD3 D5 D4 D3 0 0 0 PSL5 PSL4 PSL3 0 0 0 PEL5 PEL4 PEL3 0 0 0 TFA5 TFA4 TFA3 0 0 0 VSA5 VSA4 VSA3 0 0 0 BFA5 BFA4 BFA3 No Argument TEW1 TEW0 0 MV ML RGB 0 0 0 SSA5 SSA4 SSA3 No Argument D2 D2 0 XSA2 0 XEA2 0 YSA2 0 YEA2 D2 0 XAD2 0 YAD2 D2 0 PSL2 0 PEL2 0 TFA2 0 VSA2 0 BFA2 0 MH 0 SSA2 D1 D1 0 XSA1 0 XEA1 0 YSA1 0 YEA1 D1 0 XAD1 0 YAD1 D1 0 PSL1 0 PEL1 0 TFA1 0 VSA1 0 BFA1 TEP 0 0 SSA1 D0 ID10 ID20 ID30 P0 D0 D0 D0 D0 D0 D0 XSA8 XSA0 XEA8 XEA0 YSA8 YSA0 YEA8 YEA0 D0 XAD8 XAD0 YAD8 YAD0 D0 PSL8 PSL0 PEL8 PEL0 TFA8 TFA0 VSA8 VSA0 BFA8 BFA0 M 0 SSA8 SSA0 MTP O O O CTS 01 OO OO O NOP O NOP O NOP OO OO OO OO OO OO OO OO OO OO OO O NOP O NOP OO OO OO OO OO OO OO OO OO OO OO OO OO OO O NOP O NOP O NOP O NOP OO OO OO OO OO O NOP O NOP O NOP O NOP O NOP O NOP OO OO OO O NOP O NOP OO 2012/05/11 196 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Other Interface MDDI I/F CMD Parameter Address Instruction 39h 3Ah 3Bh 3Ch 3Eh 1st Parameter 1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter - 3900h 3A00h 3B00h 3B01h 3B02h 3B03h 3B04h 3C00h 3E00h ENTER_IDLE_MODE SET_PIXEL_FORMAT RGBCTRL RGBPRCTR RGBPRCTR RGBPRCTR RGBPRCTR RAMWRC RAMRDC 44h 45h 1st Parameter 2nd Parameter 1st Parameter 2nd Parameter 4400h 4401h 4500h 4501h SET_TEAR_SCANLINE RDSCL MDDI D[15 : D7 8] 00h 0 00h 0 00h 0 00h 0 00h 0 00h 0 00h D7 00h D7 00h 0 00h N7 00h SL15 00h SL7 D6 D5 D4 D3 No Argument VIPF2 VIPF1 VIPF0 0 CRCM 0 0 DP VBP6 VBP5 VBP4 VBP3 VFP6 VFP5 VFP4 VFP3 HBP6 HBP5 HBP4 HBP3 HFP6 HFP5 HFP4 HFP3 D6 D5 D4 D3 D6 D5 D4 D3 0 0 0 0 N6 N5 N4 N3 SL14 SL13 SL12 SL11 SL6 SL5 SL4 SL3 D2 IFPF2 EP VBP2 VFP2 HBP2 HFP2 D2 D2 0 N2 SL10 SL2 D1 IFPF1 HSP VBP1 VFP1 HBP1 HFP1 D1 D1 0 N1 SL9 SL1 D0 IFPF0 VSP VBP0 VFP0 HBP0 HFP0 D0 D0 N8 N0 SL8 SL0 4Fh 1st Parameter 4F00h ENTER_DSTB_MODE 00h 0 0 0 0 0 0 0 DSTB 51h 1st Parameter 5100h WRDISBV 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 52h 1st Parameter 5200h RDDISBV 00h DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 53h 1st Parameter 5300h WRCTRLD 00h 0 0 BCTRL 0 DD BL 0 0 54h 1st Parameter 5400h RDCTRLD 00h 0 0 BCTRL 0 DD BL 0 0 55h 1st parameter 5500h WRCABC 00h IMAGE_ENHANCEMENT [3:0] 0 0 CABC_COND [1:0] 56h 1st parameter 5600h RDCABC 00h IMAGE_ENHANCEMENT [3:0] 0 0 CABC_COND [1:0] 5Eh 1st Parameter 5E00h WRCABCMB 00h CMB[7 : 0] 5Fh 1st Parameter 5F00h RDCABCMB 00h CMB[7 : 0] 68h 1st Parameter 6800h RDDSDR 00h D7 D6 D5 D4 D3 D2 D1 D0 8Fh 1st Parameter 8F00h SET_MIPI_MDDI 00h 0 0 0 0 0 0 0 MDDI_I 1st Parameter A100h 00h SID[7 : 0]: LS Byte of Supplier ID 2nd Parameter A101h RDDDBS A1h 3rd Parameter A102h 00h SID[15 : 8]: MS Byte of Supplier ID 00h MRID[7 : 0]: LS Byte of Model Number ID 4th Parameter A103h 00h MRID[15 : 8]: MS Byte of Model Number ID 5th Parameter A104h 00h 1 1 1 1 1 1 1 1 1st Parameter A800h 00h SID[7 : 0]: LS Byte of Supplier ID 2nd Parameter A801h 00h SID[15 : 8]: MS Byte of Supplier ID A8h 3rd Parameter A802h RDDDBC 00h MRID[7 : 0]: LS Byte of Model Number ID 4th Parameter A803h 00h MRID[15 : 8]: MS Byte of Model Number ID 5th Parameter A804h 00h 1 1 1 1 1 1 1 1 AAh 1st Parameter AA00h RDFCS 00h FCS7 FCS6 FCS5 FCS4 FCS3 FCS2 FCS1 FCS0 AEh 1st Parameter AE00h STB EDGE TIMING CTRL 00h STB_EDGE_SEL[7:0] AFh 1st Parameter AF00h RDCCS 00h CCS7 CCS6 CCS5 CCS4 CCS3 CCS2 CCS1 CCS0 DAh 1st Parameter DA00h RDID1 00h ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 DBh 1st Parameter DB00h RDID2 00h 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 DCh 1st Parameter DC00h RDID3 00h ID37 ID36 ID35 E1h 1st Parameter E100h IDLEMODE_BL_Control 00h 0 0 0 E2h 1st Parameter E200h IDLEMODE_BL_Control 00h 0 0 0 ID34 0 0 ID33 0 0 ID32 0 0 ID31 ID30 IDLE_O IDLE_MO N_SIGN DE_BL_E AL_EN N IDLE_O IDLE_MO N_SIGN DE_BL_E AL_EN N FFh 1st Parameter - RD_CMDSTATUS 00h 0 0 0 0 0 CMD2_ CMD2_ CMD1 P1 P0 EDh 1st Parameter ED00h CMD2UNLOCK 2nd Parameter ED01h 00h 0 0 0 0 0 0 0 1 00h 1 1 1 1 1 1 1 0 MTP O CTS 01 OO OO O NOP O NOP O NOP O NOP O NOP OO OO OO OO OO OO O NOP OO OO OO OO OO OO OO OO OO O NOP OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Note:CTS bits is located at CMD2 register(B7h bit[3]). 2012/05/11 197 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. NOP (00h): No Operation Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] Parameter Draft Version NT35310 0000h 00h D[6] D[5] D[4] D[3] No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Value N/A Description Restriction - This command performs no operation and is ignored by the device. - Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 198 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version SOFT_RESET (01h): Software Reset Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] Parameter 0100h 01h D[5] D[4] D[3] No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W N/A Default Value N/A Description Restriction - When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset register values and all source & gate outputs are set to GND (display off). (1) It will be necessary to wait 20msec before sending new command following software reset. (2) The display module loads all display supplier’s factory default values to the registers during 5 msec. (3) If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120 msec before sending Sleep Out command. (4) Software Reset command cannot be sent during Sleep Out sequence. Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 199 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDID (04h): Read Display ID Address (MDDI I/F) Address (Other I/F) MDDI I/F Other I/F D[15 : 8] 0400h Parameter 1 00h 0401h Parameter 2 00h 0402h Parameter 3 00h D[7] ID17 1 ID37 Draft Version NT35310 0400h 04h D[6] D[5] ID16 ID15 ID26 ID25 ID36 ID35 D[4] ID14 ID24 ID34 Access Attribute Number of Parameter(s) via MIPI I/F D[3] D[2] D[1] D[0] ID13 ID12 ID11 ID10 ID23 ID22 ID21 ID20 ID33 ID32 ID31 ID30 R 1 Default Value N/A N/A N/A - This read byte returns display identification information. The 1st parameter (ID17 to ID10):LCD module’s manufacturer ID. The 2nd parameter (ID26 to ID20):LCD module/driver version ID. Description It is defined by display supplier and changes each time a revision is made to the display, material or construction specifications. See Table: ID Byte Value 80h 81h Version Version1 Version2 Changes : : 82h Version3 : Restriction The 3rd parameter (ID37 to ID30):LCD module/driver ID. - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 0400h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A 2012/05/11 200 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version RDNUMED (05h): Read Number of the Errors on DSI Address (MDDI I/F) Address (Other I/F) 0500h 05h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h D7 D6 D5 D4 D3 NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] D2 D1 D0 R 1 Default Value 00h Description - The first parameter is telling a number of the errors on DSI. The more detailed description of the bit is explained in below. D[6 : 0] bits are telling a number of the errors. D[7] is set to ‘1’ if there is overflow with P[6 : 0] bits. D[7 : 0] bits are set to ‘0’s (as well as GET_SIGNAL_MODE (0Eh)’s D0 is set ‘0’ at the same time) after there is sent the second parameter information (= The read function is completed). Please also refer to the sections: “Acknowledge with Error Report (AwER)” and “Read Display Signal Mode (0Eh)”. Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 201 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_POWER_MODE (0Ah): Read Display Power Mode Address (MDDI I/F) Address (Other I/F) 0A00h 0Ah Access Attribute R Number of Parameter(s) 1 D[15 : 8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value Parameter 00h D7 D6 D5 D4 D3 D2 0 0 08h Description - This command indicates the current status of the display as described in the table below: Bit Description Value D7 Booster Voltage Status “1”=Booster on, “0”=Booster off D6 Idle Mode On/Off “1” = Idle Mode On, “0”= Idle Mode Off D5 Partial Mode On/Off “1” = Partial Mode On, “0” = Partial Mode Off D4 Sleep In/Out “1” = Sleep Out, “0” = Sleep In D3 Display Normal Mode On/Off “1” = Normal Display On, “0” = Normal Display Off D2 Display On/Off “1” = Display On, “0” = Display Off D1 Not Used “0” D0 Not Used “0” Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 08h 08h 08h 2012/05/11 202 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_ADDRESS_MODE (0Bh): Get the Frame Memory to the Display Panel Read Order Address (MDDI I/F) Address (Other I/F) 0B00h 0Bh Access Attribute Number of Parameter(s) D[15 : 8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Parameter 00h D7 D6 D5 D4 D3 D2 0 0 R 1 Default Value 00h Description - This command indicates the current status of the display as described in the table below: Bit Description Value D7 Row Address Order (MY) “1”=Decrement (MY = 1) “0”=Increment (MY = 0) D6 Column Address Order (MX) “1”=Decrement (MX = 1) “0”=Increment (MX = 0) D5 Row/Column Order (MV) “1”= Row / column exchange (MV=1) “0”= Normal (MV=0) D4 Vertical fresh Order & Display change (ML) “1”=Decrement (ML = 1) “0”=Increment (ML = 0) D3 RGB/BGR Order “1”=BGR (register bit RGB of register 0x3600 is “1”) “0”=RGB (register bit RGB of register 0x3600 is “0”) D2 Horizontal fresh Order & Display change (MH) “1”=Decrement (MH = 1) “0”=Increment (MH = 0) D1 Not Used “0” D0 Not Used “0” Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 203 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_PIXEL_MODE (0Ch): Read Input Pixel Format Address (MDDI I/F) Address (Other I/F) 0C00h 0Ch Access Attribute R Number of Parameter(s) 1 D[15 : 8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value Parameter 00h D7 D6 D5 D4 D3 D2 D1 D0 06h Description - This command indicates the current status of the display as described in the table below: Bit Description D7 0 D6 D5 RGB Interface Color Format D4 D3 0 D2 D1 CPU interface color format. D0 Value 0 “101” = 16-bits/pixel “110” = 18-bits/pixel Others = “Not defined” “0” (Not used) “101” = 16-bits “110” = 18-bits “111” =24-bits/pixel(MIPI only) Others = “Not defined” Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Status Power On Sequence H/W Reset Defsult Value CTS=0 66h CTS=1 06h CTS=0 66h CTS=1 06h Default Value VIPF[2 : 0] = 06h (18 bits / pixel) IFPF[2 : 0] = 06h (18-bits / pixel) 2012/05/11 204 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_DISPLAY_MODE (0Dh): Read the Current Display Mode Address (MDDI I/F) Address (Other I/F) 0D00h 0Dh D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h D7 D6 D5 D4 D3 Access Attribute Number of Parameter(s) D[2] D[1] D[0] D2 D1 D0 R 1 Default Value 00h - This command indicates the current status of the display as described in the table below: Bit Description Value D7 Reserved “0” (Not used) D6 Reserved “0” (Not used) D5 Inversion On/Off “0” = Inversion is Off, “1” = Inversion is On D4 All Pixels On “0” = Normal Display, “1” = White Display D3 All Pixels Off “0” = Normal Display, “1” = Black Display Description D[2 : 0] Gamma Curve Selection D2 D1 D0 000 Others Gamma Curves Selection (Based on Registet 26h Setting) Gamma 2.2 Reserved Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 205 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 GET_SIGNAL_MODE (0Eh): Get Display Module Signaling Mode Address (MDDI I/F) Address (Other I/F) 0E00h 0Eh D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h D7 D6 D5 D4 D3 Access Attribute Number of Parameter(s) D[2] D[1] D[0] D2 D1 D0 R 1 Default Value 00h Description - This command indicates the current status of the display as described in the table below: Bit Description D7 Frame Tearing Effect Line On/Off D6 Tearing Effect Line Output Mode D5 Horizontal Sync. (RGB I/F)On/Off D4 Vertical Sync. (RGB I/F)On/Off D3 Pixel Clock (DCK, RGB I/F)On/Off D2 Data Enable (ENABLE, RGB I/F)On/Off D1 No used D0 Error on DSI “1” = On, “1” = Mode B, “1” = On, “1” = On, “1” = On, “1” = On, Value “0” = Off “0” = Mode A “0” = Off “0” = Off “0” = Off “0” = Off ”1” = Error, “0” = NO Error Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 206 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDDSDR (0Fh): Read Display Self-Diagnostic Result Address (MDDI I/F) Address (Other I/F) 0F00h 0Fh Access Attribute R Number of Parameter(s) 1 D[15 : 8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value Parameter 00h D7 D6 D5 D4 D3 D2 D1 D0 00h Description Restriction -This command indicates the status of the display self-diagnostic results after Sleep Out. This command is described in the table below. -The inverse of checksum comparison will output to GPIO pin when select this function. Normally GPIO pin remains high, when ESD occurs leads to checksum comparison fail, it will output low pulse or keep low to notify the ESD alarm to host. Bit Description Value D7 Register Loading Detection D6 Functionality Detection D5 Chip Attachment Detection “0” (Not used) D4 Display Glass Break Detection “0” (Not used) D3 Not Used “0” (Not used) D2 Not Used “0” (Not used) D1 Not Used “0” (Not used) “1”=Checksums are “0”=Checksums are D0 Checksums Compare not same same (Default) - It will be necessary to wait 300ms after there is the last write access on DCS area registers before there can read Bit D0 value. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 207 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ENTER_SLEEP_MODE (10h): Enter the Sleep-In Mode Address (MDDI I/F) Address (Other I/F) 1000h 10h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Sleep-In Mode Description Restriction - This command initiates the power-down sequence. The Sleep In profile will be executed when this command is received. - In Sleep-in mode, the power of SRAM is default to keep SRAM power. It can be changed to turned off in order to reduce leakage current by DSIN bit in page 0 of CMD2, therefore the SRAM data will be lost in Sleep-in mode. Also either write or read SRAM is not possible in Sleep-in mode. - This command has no effect when the display module is already in Sleep Mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Sleep-In Sleep-In Sleep-In 2012/05/11 208 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 EXIT_SLEEP_MODE (11h): Exit the Sleep-In Mode Address (MDDI I/F) Address (Other I/F) 1100h 11h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Sleep-In Mode Description Restriction - This command initiates the power-up sequence. The Sleep Out profile will be executed when this command is received. The Sleep Out will load register value. It will be necessary to wait 5 msec before sending next command. - This command will not cause any visible effect on the display when the display is not in Sleep Mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Sleep-In Sleep-In Sleep-In 2012/05/11 209 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ENTER_PARTIAL_MODE (12h): Partial Display Mode On Address (MDDI I/F) Address (Other I/F) 1200h 12h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Normal Mode Description Restriction - This command sets the display mode to Partial Mode in which the display is refreshed using timing and image data based upon register settings and the Partial Display Memory contents, respectively. The Partial Mode profile will be executed when this command is received in the Sleep Out state. If in the Sleep-In state, the profile will not be executed until the device is placed into the Sleep-Out state. - This command has no effect when Partial Display Mode is already active. - This command is not available in RGB interface. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Normal Display Mode Normal Display Mode Normal Display Mode 2012/05/11 210 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ENTER_NORMAL_MODE (13h): Normal Display Mode On Address (MDDI I/F) Address (Other I/F) 1300h 13h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Normal Mode Description Restriction - This command returns the display to normal mode. Normal Display Mode On means the Partial mode off, and the Scroll mode Off. Exit from NORON by the Partial mode On command (12h). There is no abnormal visual effect during the mode changes from Normal mode On to Partial mode On. - This command has no effect when Display Mode is already in Normal Display Mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Normal Display Mode Normal Display Mode Normal Display Mode 2012/05/11 211 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version EXIT_INVERT_MODE (20h): Display Inversion Off Address (MDDI I/F) Address (Other I/F) 2000h 20h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Inversion Off - This command is used to recover from display reverse mode, makes no change of contents of frame memory, and does not change any other status. Example: Description Restriction - This command has no effect when the module is already in inversion off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Display Inversion Off Display Inversion Off Display Inversion Off 2012/05/11 212 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ENTER_INVERT_MODE (21h): Display Inversion On Address (MDDI I/F) Address (Other I/F) 2100h 21h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Inversion Off - This command is used to enter display Inversion mode, makes no change of contents of frame memory, and does not change any other status. To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. Example: Description Restriction - This command has no effect when the module is already in inversion off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Display Inversion Off Display Inversion Off Display Inversion Off 2012/05/11 213 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ALLPOFF (22h): All Pixel Off Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] Parameter 2200h 22h D[6] D[5] D[4] D[3] No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Disable - This command turns the display panel black in “Sleep Out” –mode and a status of the “Display On / Off”: Register can be ‘”on” or “off”. This command makes no change of contents of frame memory. This command does not change any other status. Example: Description Restriction “All Pixels On”, “Normal Display Mode On” or “Partial Mode On” - commands are used to leave this mode. The display panel is showing the content of the frame memory after “Normal Display Mode On” and “Partial Mode On” commands. - This command has no effect when module is already in all pixels off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Disable Disable Disable 2012/05/11 214 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ALLPON (23h): All Pixel On Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] Parameter 2300h 23h D[6] D[5] D[4] D[3] No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Disable - This command turns the display panel white in “Sleep out”- mode and a status of the “Display On/Off”. Register can be “on” or “off” This command makes no change of contents of frame memory. This command does not change any other status. Example: Description Restriction "All Pixels Off", "Normal Display Mode On" or "Partial Mode On" - commands are used to leave this mode. The display is showing the content of the frame memory after "Normal Display Mode On" and "Partial Mode On" commands. - This command has no effect when module is already in all pixels on mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Disable Disable Disable 2012/05/11 215 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version GMASET (26h): Gamma Curves Selection Address (MDDI I/F) Address (Other I/F) 2600h 26h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h GC7 GC6 GC5 GC4 GC3 NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] GC2 GC1 GC0 R/W 1 Default Value 01h This command is used to select the desired Gamma curve for the current display. Only 1 fixed gamma curve can be selected. The curves are defined in Section "Gamma Curve Correction Power Supply Circuit". The curve is selected by setting the appropriate bit in the parameter as described in the Table: Description GC[7:0] 01h 02h 04h 08h Parameter GC0 GC1 GC2 GC3 Curve Selected Gamma Curve 1 (Gamma 2.2) Reversed Reversed Reversed Restriction Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid is received. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h 2012/05/11 216 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_DISPLAY_OFF (28h): Display Off Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] Parameter 2800h 28h D[5] D[4] D[3] No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Display Off - This command is used to enter to the DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page is inserted. This command makes no change of contents of frame memory, and does not change any other status. There will be no abnormal visible effects on the display. Exit from this command by the Display On command (29h) Example: Description Restriction - This command has no effect when the module is already in Display Off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Display Off Display Off Display Off 2012/05/11 217 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_DISPLAY_ON (29h): Display On Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] Parameter 2900h 29h D[5] D[4] D[3] No Argument Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Display Off - This command is used to recover from the DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory, and does not change any other status. Example: Description Restriction - This command has no effect when the module is already in Display On mode Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Display Off Display Off Display Off 2012/05/11 218 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_HORIZONTAL_ADDRESS (2Ah): Set the Column Address Address (MDDI I/F) Address (Other I/F) 2A00h ~2A03h 2Ah Address Parameter D[15 : 8] D[7] D[6] D[5] D[4] (MDDI I/F) 2A00h Parameter 1 00h 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 XSA8 2A01h Parameter 2 00h XSA7 XSA6 XSA5 XSA4 XSA3 XSA2 XSA1 XSA0 2A02h Parameter 3 00h 0 0 0 0 0 0 0 XEA8 2A03h Parameter 4 00h XEA7 XEA6 XEA5 XEA4 XEA3 XEA2 XEA1 XEA0 - This command is used to define area of frame memory where MPU can access. This command makes no change on the other driver status. The value of XSA [8 : 0] and XEA [8 : 0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. Example: XSA[ 8 : 0] XEA [ 8 : 0] R/W 4 Default Value 00h 00h By Resolution By Resolution Description Restriction (1) XSA[8 : 0] must always be equal to or less than XEA[8 : 0] (2) If XSA[8 : 0] or XEA[8 : 0] is greater than the available frame memory then the parameter is not updated. Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 2A00h ~ 2A01h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 219 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 2A02h: Default Value 2A03h: Draft Version Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h NT35310 Status Power On Sequence S/W Reset H/W Reset Default Value 3Fh 3Fh 3Fh 2012/05/11 220 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_VERTICAL_ADDRESS (2Bh): Set Page Address Address (MDDI I/F) Address (Other I/F) 2B00h ~ 2B03h 2B Address Parameter D[15 : 8] D[7] D[6] D[5] D[4] (Other I/F) 2B00h Parameter 1 00h 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 YSA8 R/W 4 Default Value 00h 2B01h Parameter 2 00h 2B02h Parameter 3 00h 2B03h Parameter 4 00h YSA7 0 YEA7 YSA6 0 YEA6 YSA5 0 YEA5 YSA4 0 YEA4 YSA3 0 YEA3 YSA2 0 YEA2 YSA1 0 YEA1 YSA0 YEA8 YEA0 00h By Resolution By Resolution - This command is used to define area of frame memory where MPU can access. This command makes no change on the other driver status. The value of YSA [8 : 0] and YEA [8 : 0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. Example: YSA [ 8 : 0] Description YEA [ 8 : 0 ] Restriction (1) YSA[8 : 0] must always be equal to or less than YEA[8 : 0] (2) If YSA[8 : 0] or YEA[8 : 0] is greater than the available frame memory then the parameter is not updated. Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 2B00h ~ 2B01h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 221 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 2B02h: 2B03h: Default Value Draft Version Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h Status Power On Sequence S/W Reset H/W Reset Default Value DFh DFh DFh NT35310 2012/05/11 222 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WRITE_MEMORY_START (2Ch): Memory Write Start Command Address (MDDI I/F) Address (Other I/F) 2C00h 2Ch D[15 : 8] D[7] D[6] D[5] D[4] D[3] Image Data 1 D0[15 : 8] D0[7] D0[6] D0[5] D0[4] D0[3] Image Data 2 : : Image Data N D1[15 : 8] : : Dn[15 : 8] D1[7] : : Dn[7] D1[6] : : Dn[6] D1[5] : : Dn[5] D1[4] : : Dn[4] D1[3] : : Dn[3] Access Attribute Number of Parameter(s) D[2] D[1] D[0] W By Application Default Value D0[2] D0[1] D0[0] N/A D1[2] D1[1] D1[0] N/A : : : : : : : : Dn[2] Dn[1] Dn[0] N/A Description - This command writes data into the partial memory. It initializes the memory write address pointer to the start of the memory. Frame pointer auto-increments when data is written. Note: About Read / Write Frame Data via all kinds of supported interface, please refer to the chapter 5 for detailed. Restriction (1) A WRITE_MEMORY_START should follow a SET_COLUMN_ADDRESS, SET_PAGE_ADDRESS or SET_ADDRESS_MODE to define the write location. Otherwise, data written with WRITE_MEMORY_START and any following WRITE_MEMORY_CONTINUE commands is written to undefined locations. (2) This command is not supported MDDI interface. Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 223 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_MDDI_RAM_READ_ADDRESS (2Dh): Set the RAM Horizontal and Vertical Address Address (MDDI I/F) Address (Other I/F) 2D00h ~ 2D03h 2Dh Address Parameter D[15 : 8] D[7] D[6] D[5] D[4] (Other I/F) 2D00h Parameter 1 00h 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 XAD8 2D01h Parameter 2 00h XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0 2D02h Parameter 3 00h 0 0 0 0 0 0 0 YAD8 2D03h Parameter 4 00h YAD7 YAD6 YAD5 YAD4 YAD3 YAD2 YAD1 YAD0 R/W 4 Default Value 00h 00h 00h 00h Description - XAD[8 : 0], YAD[8 : 0]: MDDI RAM read address, which is set initially in the AC (Address Counter). The NT35310 writes data to the internal RAM so that data is written consecutively without resetting the address in the AC. The address is not automatically updated when reading data from the internal RAM. YAD[8 : 0] — XAD[8 : 0] RAM Data Setting 20’h000:000 – 20’h000:67B Bitmap data on the 1st line 20’h001:000 – 20’h001:67B Bitmap data on the 2nd line 20’h002:000 – 20’h002:67B Bitmap data on the 3rd line 20’h003:000 – 20’h003:67B 20’h004:000 – 20’h004:67B Bitmap data on the 4th line Bitmap data on the 5th line : : 20’h1DC:000 – 20’h1DC:67B Bitmap data on the 477 line 20’h1DD:000 – 20’h1DD:67B Bitmap data on the 478 line 20’h1DE:000 – 20’h1DE:67B Bitmap data on the 479 line 20’h1DF:000 – 20’h1DF:67B Bitmap data on the 480 line Note: This table is for portrait (320RGBx480) application. Restriction - Only be applied when read RAM data via MDDI interface Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 2D00h ~ 2D03h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 224 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 READ_MEMORY_START (2Eh): Memory Read Start Command Address (MDDI I/F) Address (Other I/F) 2E00h 2Eh D[15 : 8] D[7] D[6] D[5] D[4] D[3] Image Data 1 D0[15 : 8] D0[7] D0[6] D0[5] D0[4] D0[3] Image Data 2 : : Image Data N D1[15 : 8] : : Dn[15 : 8] D1[7] : : Dn[7] D1[6] : : Dn[6] D1[5] : : Dn[5] D1[4] : : Dn[4] D1[3] : : Dn[3] Access Attribute Number of Parameter(s) D[2] D[1] D[0] R By Application Default Value D0[2] D0[1] D0[0] N/A D1[2] D1[1] D1[0] N/A : : : : : : : : Dn[2] Dn[1] Dn[0] N/A - This command is used to transfer data from frame memory to MPU. When this command is accepted, the column register and the row register are reset to the Start Column / Start Row positions. And the Start Column / Start Row positions are different in accordance with SET_ADDRESS_MODE (Register 3600h) setting. MV Physical Row MX MY Virtual to Physical Address Translator Description Note: 1. Commands "Memory Write Continuously (3C00h)" and "Memory Read Continuously (3E00h)" do not return the column counter to "Start Column" and the row counter to "Start Row". 2. Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MSET_ADDRESS_MODE bit MY, MX and MV. 2012/05/11 225 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Restriction (1) There is no restriction on length of parameters in MIPI, CPU interface and SPI. (2) MDDI interface only support single RAM read. Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 226 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_PARTIAL_AREA (30h): Defines the Partial Display Area Address (MDDI I/F) Address (Other I/F) 3000h ~ 3003h 30h Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] D[5] D[4] 3000h Parameter 1 00h 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 PSL8 R/W 4 Default Value 00h 3001h Parameter 2 00h 3002h Parameter 3 00h 3003h Parameter 4 00h PSL7 0 PEL7 PSL6 0 PEL6 PSL5 0 PEL5 PSL4 0 PEL4 PSL3 0 PEL3 PSL2 0 PEL2 PSL1 0 PEL1 PSL0 PEL8 PEL0 00h By Resolution By Resolution - This command defines the partial mode's display area. There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. If End Row > Start Row when SET_ADDRESS_MODE ML = 0: Start Row PSL[ 8 : 0] Non- display Area End Row PEL[ 8 : 0] Non- display Area If End Row > Start Row when SET_ADDRESS_MODE ML = 1: End Row PEL[ 8 : 0] Non - display Area Description Start Row PSL[ 8 : 0] Non - display Area If End Row < Start Row when SET_ADDRESS_MODE ML =0: End Row PEL [ 8 : 0] Restriction Start Row PSL [ 8 : 0] Non- display Area If End Row = Start Row, the Partial Area will be one row deep. Partial Display Area Partial Display Area Partial Display Area 2012/05/11 227 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 3000h ~ 3001h: Status Power On Sequence S/W Reset H/W Reset 3002h: Default Value 3003h: Status Power On Sequence S/W Reset H/W Reset Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h Default Value 01h 01h 01h Default Value DFh DFh DFh 2012/05/11 228 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SCRLAR (33h): Set Scroll Area Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] 3300h Parameter 1 00h 0 3301h Parameter 2 00h TFA7 3302h Parameter 3 00h 0 3303h Parameter 4 00h VSA7 3304h Parameter 5 00h 3305h Parameter 6 00h 0 BFA7 3300h ~ 3305h 33h D[6] D[5] 0 TFA6 0 0 TFA5 0 VSA6 0 BFA6 VSA5 0 BFA5 D[4] 0 TFA4 0 VSA4 0 BFA4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 TFA3 0 0 TFA2 0 0 TFA1 0 TFA8 TFA0 VSA8 VSA3 0 BFA3 VSA2 0 BFA2 VSA1 0 BFA1 VSA0 BFA8 BFA0 R/W 6 Default Value 00h 00h By Resolution By Resolution 00h 00h - This command defines the Vertical Scrolling Area of the display. When MADCTR ML = 0: TFA [8:0]: Describes the Top Fixed Area (in number of lines from Top of the Frame Memory and Display). VSA [8:0]: Describes the height of the Vertical Scrolling Area (in number of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. BFA [8:0]: Describes the Bottom Fixed Area (in number of lines from Bottom of the Frame Memory and Display). Description TFA, VSA and BFA refer to the Frame Memory row address. Top Fixed Area TFA[ 8 : 0] Top Fixed Area First read line from frame memory Vertical Scroll Area VSA[ 8 : 0] Bottom Fixed Area BFA[ 8 : 0] Bottom Fixed Area 2012/05/11 229 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description When MADCTR ML = 1: TFA [8:0]: Describes the Top Fixed Area (in number of lines from Bottom of the Frame Memory and Display). VSA [8:0]: Describes the height of the Vertical Scrolling Area (in number of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the top most line of the Top Fixed Area. BFA [8:0]: Describes the Bottom Fixed Area (in number of lines from Top of the Frame Memory and Display). (0 , 0) Bottom Fixed Area BFA[ 8 : 0] Top Fixed Area Vertical Scroll Area VSA[ 8 : 0] Top Fixed Area TFA[ 8 : 0] Top Fixed Area First read line from frame memory Restriction (1) The condition is (TFA + VSA + BFA) = Scan Line, otherwise Scrolling mode is undefined. (2) In Vertical Scroll Mode, MADCTR parameter MV should be set to '0'. It only affects the Frame Memory Write. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 230 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 3300h, 3301h, 3304h, 3305h: Status Power On Sequence S/W Reset H/W Reset 3302h: Default Value 3303h: Status Power On Sequence S/W Reset H/W Reset Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Default Value 01h 01h 01h Default Value E0h E0h E0h 2012/05/11 231 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version SET_TEAR_OFF (34h): Tearing Effect Line OFF Address (MDDI I/F) 3400h Address (Other I/F) 34h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status TE Line Off Description Restriction - This command is used to turn OFF (Active Low) the output TE trigger message from the display module. - This command has no effect when TE is already OFF. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status TE Line Off TE Line Off TE Line Off 2012/05/11 232 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_TEAR_ON (35h): Tearing Effect Line ON Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] 3500h 35h D[6] D[5] Parameter 00h TEW3 TEW2 TEW1 D[4] TEW0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 TEP M R/W 1 Default Value 00h - This command is used to turn ON the Tearing Effect output from the TE signal. This output is not affected by changing MADCTR bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. When M = 0:The Tearing Effect Output line consists of V-Blanking information only. When M = 1:The Tearing Effect Output line consists of both V-Blanking and H-Blanking information. Description Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Register 35h & 44h both define TE Output: Register 35h M Register 44h N TE Output 0 0 TE high in V-porch region (A) 1 0 TE high in all V-porch and H-porch region (B) 0 ≠0 TE high at N-th line (C) 1 ≠0 TE high in all V-porch and H-porch region (B) This command is used to turn ON the output TE trigger message from display module. This output is not affected by changing SET_ADDRESS_MODE bit ML. The Tearing Effect Line On has one parameter which describes the mode of the Tearing Effect Output Line. (X = Don’t Care). TEP: Set the polarity of FTE signal. 0: Active High. 1: Active Low. 2012/05/11 233 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version TEW[3:0]: Tearing output width control for type C. Description TE_W[3:0] 0 1 2 : 14 15 TE output period TE output 1 line period TE output 2 line period TE output 3 line period : TE output 15 line period TE output 16 line period NT35310 Restriction - This command has no effect when Tearing Effect output is already ON. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Notes TEW[3 : 0]= 0 (1 Line) TEP = 0 (Active High) M = 0(TE high in V-porch region (A)) 2012/05/11 234 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version SET_ADDRESS_MODE (36h): Memory Data Access Control Address (MDDI I/F) Address (Other I/F) 3600h 36h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h MY MX MV ML RGB NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] MH 0 0 R/W 1 Default Value 00h Description - This command defines read/write scanning direction of the frame memory. This command makes no change on the other driver status. MY: - Automatically increments (+1) or decrements (-1) the row address counter (AC) MY Function 0 Increase in vertical 1 Decrease in vertical MX: - Automatically increments (+1) or decrements (-1) the column address counter (AC) MX Function 0 Increase in horizon 1 Decrease in horizon MV: - Determines the direction in which the address counter is updated automatically as the NT35310 writes data to the internal GRAM. MV Function 0 Horizontal Direction 1 Vertical Direction ML: - This bit is used to control the LCD refresh order in vertical direction ML Function 0 Top to Bottom 1 Bottom to Top MH: - This bit is used to control the LCD refresh order in horizontal direction MH Function 0 Left to Right 1 Right to Left 2012/05/11 235 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Top -Left (0 , 0) Memory ML = '0' Top- Left (0 , 0) 1 st Send 2 nd Send 33rdd SSeenndd Display Last Send Top-Left (0 , 0) Memory ML = '1' Top- Left (0 , 0) Last Send Display 3 rd Send 2 nd Send 31 rsdt Sendd Description RGB: - Color selector switch control (0=RGB color filter panel, 1=BGR color filter panel) Note: The R,B Gamma will also swap. Note: Register SRAM Address & Source Panel Horizon SRAM Horizon SRAM MX CRL MH Source Scane Display Write Display Read 0 0 0 Increase Increase Increase Normal 0 0 1 Increase Decrease Decrease Normal 0 1 0 Increase Increase Decrease Reverse 0 1 1 Increase Decrease Increase Reverse 1 0 0 Decrease Increase Increase Reverse 1 0 1 Decrease Decrease Decrease Reverse 1 1 0 Decrease Increase Decrease Normal 1 1 1 Decrease Decrease Increase Normal 2012/05/11 236 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Register SRAM Address Panel Vertical Vertical SRAM MY ML CTB Gate Scane Display SRAM Write Display Read 0 0 0 Increase Increase Top to Bottom Normal 0 0 1 Increase Increase Bottom to Top Reverse 0 1 0 Increase Decrease Bottom to Top Normal 0 1 1 Increase Decrease Top to Bottom Reverse 1 0 0 Decrease Increase Top to Bottom Reverse 1 0 1 Decrease Increase Bottom to Top Normal 1 1 0 Decrease Decrease Bottom to Top Reverse 1 1 1 Decrease Decrease Top to Bottom Normal Restriction - This command has no effect when Tearing Effect output is already ON. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value Notes 00h MY = 0 (Increase in vertical) MX = 0 (Increase in horizon) 00h MV = 0 (Horizontal Direction) RGB = 0 (RGB sequence) 00h 2012/05/11 237 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 VSCSAD (37h): Vertical Scroll Start Address of RAM Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] 3700h Parameter 1 00h 0 3700h ~ 3701h 37h D[6] D[5] 0 0 3701h Parameter 2 00h SSA7 SSA6 SSA5 D[4] 0 SSA4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 SSA3 0 SSA2 0 SSA1 SSA8 SSA0 R/W 2 Default Value 00h 00h Description - This command is used together with Vertical Scrolling Definition. These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter that describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: When MADCTR ML = “0”: When Top Fixed Area = Bottom Fixed Area= 00, Vertical Scrolling Area = 320 and Vertical Scrolling Pointer, SSA = ’3’. (0, 0) Memory scan address Display 0 G0 1 G1 2 G2 SSA [15:0] 3 G3 : : : Scroll start address : G 317 318 G 318 319 G 319 ( 0 , 319 ) When MADCTR ML = “1”: When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320 and SSA =’ 3’ (0, 0) Memory scan address 319 G0 318 G1 : G2 SSA [15:0] : G3 : 3 : Scroll start address 2 G 317 1 G 318 0 G 319 Display ( 0 , 319 ) Note:When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. SSA refers to the Frame Memory scan address. Restriction - Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h), otherwise undesirable image will be displayed on the Panel. SSA[15:0] is based on 1-line unit. 2012/05/11 238 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 3700h ~ 3701h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes No No Yes Default Value 00h 00h 00h 2012/05/11 239 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. EXIT_IDLE_MODE (38h): Idle Mode Off Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] Parameter Draft Version 3800h 38h D[5] D[4] D[3] No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Idle Mode Off Description Restriction - This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. When the Idle Mode is “Off”: (1) LCD can display with maximum 65k or 262k-colors. (2) Normal frame frequency is applied. - This command has no effect when module is already in idle off mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status Idle Mode Off Idle Mode Off Idle Mode Off 2012/05/11 240 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version ENTER_IDLE_MODE (39h): Idle Mode On Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] Parameter 3900h 39h D[5] D[4] D[3] No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Idle Mode Off - This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. When the Idle Mode is "On": (1) Color expression is reduced. The primary and the secondary colors using MSB of each RMG and B in the Frame Memory, 8 color depth data is displayed. (2) 8-Color mode frame frequency is applied. (3) Exit from IDMON by Idle Mode Off (3800h) command (Example) Memory Display Description Color Black Blue Red Magenta Green Cyan Yellow White R5R4R3R2R1R0 0XXXXX 0XXXXX 1XXXXX 1XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX G5G4G3G2G1G0 0XXXXX 0XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX 1XXXXX 1XXXXX B5B4B3B4B1B0 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX Restriction - This command has no effect when module is already in Idle On Mode. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 241 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Default Value Draft Version NT35310 Status Power On Sequence S/W Reset H/W Reset Default Status Idle Mode Off Idle Mode Off Idle Mode Off 2012/05/11 242 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_PIXEL_FORMAT (3Ah): Set the Interface Pixel Format Address (MDDI I/F) Address (Other I/F) 3A00h 3Ah D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter 00h 0 VIPF2 VIPF1 VIPF0 0 Access Attribute Number of Parameter(s) D[2] D[1] D[0] IFPF2 IFPF1 IFPF0 R/W 1 Default Value 66h Description - This command is used to define the format of RGB picture data, which is to be transferred via the MPU Interface. The formats are shown in the table: IFPF[2 : 0]: Set the pixel format on MCU I/F IFPF[2 : 0] Binary DEC 101 5 110 6 111 7 Others are not defined. MCU Interface Color Format 16-bits / pixel 18-bits / pixel 24-bits / pixel(MIPI only) VIPF[2 : 0] : Set the pixel format on RGB I/F VIPF[2 : 0] Binary DEC 101 5 110 6 Others are not defined. RGB Interface Color Format 16 bits / pixel (1-time transfer) 18 bits / pixel (1-time transfer) Restriction - There is no visible effect until the Frame Memory is written to. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 66h 66h 66h 2012/05/11 243 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RGBCTRL (3Bh): RGB Interface Signal Control Address (MDDI I/F) Address (Other I/F) 3B00h ~ 3B04h 3Bh Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] D[6] D[5] 3B00h Parameter 1 00h 0 CRCM 0 3B01h Parameter 2 00h 0 VBP6 VBP5 3B02h Parameter 3 00h 0 VFP6 VFP5 3B03h Parameter 4 00h 0 HBP6 HBP5 3B04h Parameter 5 00h 0 HFP6 HFP5 D[4] 0 VBP4 VFP4 HBP4 HFP4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] DP VBP3 VFP3 HBP3 HFP3 EP VBP2 VFP2 HBP2 HFP2 HSP VBP1 VFP1 HBP1 HFP1 VSP VBP0 VFP0 HBP0 HFP0 R/W 5 Default Value 03h 0Ch 04h 28h 32h - Set the operation status on the RGB interface. The setting becomes effective as long as the command is received. CRCM: Determines the RGB Mode 1 & RGB Mode 2 CRCM 0 1 RGB Mode Selection RGB Mode 1 RGB Mode 2 Description RGB I/F Mode PCLK RGB Mode 1 Used RGB Mode 2 Used DE Used Not Used D[17 : 0] Used Used VS Used Used HS Used Used Register VBP[6 : 0], HBP[6 : 0], VFP[6 : 0], HFP[6 : 0] Not Used Used 2012/05/11 244 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Description Draft Version NT35310 DP / EP / HSP / VSP: Clock polarity set for RGB Interface Symbol Name DP PCLK Polarity Set EP DE Polarity Set HSP Hsync Polarity Set VSP Vsync Polarity Set Clock Polarity Set For RGB Interface ‘0’ = Data fetched at the rising edge ‘1’ = Data fetched at the falling edge ‘0’ = High enable for RGB interface ‘1’ = Low enable for RGB interface ‘0’ = High level sync clock ‘1’ = Low level sync clock ‘0’ = High level sync clock ‘1’ = Low level sync clock VBP[6 : 0], VFP[6 : 0], HBP[6 : 0], and HFP[6 : 0]: Vertical and Horizontal back and front porch control when RGB I/F mode 2 only. VBP[6 : 0]: Number of lines for the back porch of VSYNC. VFP[6 : 0]: Number of lines for the front porch of VSYNC. HBP[6 : 0]: Number of clock for the back porch of HSYNC. HFP[6 : 0]: Number of clock for the front porch of HSYNC. VBP[6 : 0] Back Porch Line Number VFP[6 : 0] Front Porch Line Number HBP[6 : 0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 01d Reserved Reserved Reserved Reserved 02d Reserved Reserved Reserved Reserved 03d 04d 4 04d 4 04d : : : : : : (STEP 1) : (STEP 1) : : : : : : 61d 61 61d 61 61d 62d 62 62d 62 62d 63d 63 63d 63 63d Back Porch Pixel clocks Reserved 1 2 3 4 : (STEP 1) : 61 62 63 HFP[6 : 0] Reserved 01d 02d 03d 04d : : : 61d 62d 63d Front Porch Pixel Clocks Reserved 1 2 3 4 : (STEP 1) : 61 62 63 Note: MIPI Video mode please keep HBP at 2us, HFP at 600UI. Restriction - There is no visible effect until the Frame Memory is written to. 2012/05/11 245 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Register Availability Default Value 3B00h: Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Status Default Value Note CRCM = '0' (RGB Mode 1) Power On Sequence 03h ICM = '0' (PCLK) H/W Reset DP = '0', EP = '0', HSP = '1' (Low Level), 03h VSP = '1' (Low Level) 3B01h: Status Default Value Note Power On Sequence 06h VBP[5 : 0] =6 H/W Reset 06h VFP[5 : 0] = 2 3B02h: Status Default Value Note Power On Sequence 02h VBP[5 : 0] = 6 H/W Reset 02h VFP[5 : 0] = 2 3B03h: Status Default Value Note Power On Sequence 14h HBP[5 : 0] = 14 H/W Reset 14h HFP[5 : 0] = 19 3B04h: Status Default Value Note Power On Sequence 19h HBP[5 : 0] = 14 H/W Reset 19h HFP[5 : 0] = 19 2012/05/11 246 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RAMWRC (3Ch): Memory Write Continuously Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] 3C00h 3Ch D[6] D[5] Image Data 1 D0[15 : 8] D0[7] D0[6] D0[5] Image Data 2 : : Image Data N D1[15 : 8] : : Dn[15 : 8] D1[7] : : Dn[7] D1[6] : : Dn[6] D1[5] : : Dn[5] D[4] D0[4] D1[4] : : Dn[4] D[3] D0[3] D1[3] : : Dn[3] Access Attribute Number of Parameter(s) D[2] D[1] D[0] W By Application Default Value D0[2] D0[1] D0[0] N/A D1[2] D1[1] D1[0] N/A : : : : : : : : Dn[2] Dn[1] Dn[0] N/A Description Restriction - This command is used to transfer data from MCU to display area, if wants to continue memory write after Memory Write (2Ch) command. - This command is not supported in MDDI I/F. Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 247 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RAMRDC (3Eh):RAM Read Continuously Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] 3E00h 3Eh D[6] D[5] Image Data 1 D0[15 : 8] D0[7] D0[6] D0[5] Image Data 2 : : Image Data N D1[15 : 8] : : Dn[15 : 8] D1[7] : : Dn[7] D1[6] : : Dn[6] D1[5] : : Dn[5] D[4] D0[4] D1[4] : : Dn[4] D[3] D0[3] D1[3] : : Dn[3] Access Attribute Number of Parameter(s) D[2] D[1] D[0] R By Application Default Value D0[2] D0[1] D0[0] N/A D1[2] D1[1] D1[0] N/A : : : : : : : : Dn[2] Dn[1] Dn[0] N/A Description Restriction - This command is used to transfer data from frame memory to MCU, if wants to continue memory write after Memory Read Start (2Eh) command. - This command is not supported in MDDI I/F. Register Availability Default Value N/A Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 248 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SET_TEAR_SCANLINE (44h): Set Tear Line Address (MDDI I/F) Address (Other I/F) 4400h ~ 4401h 44h Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] D[5] D[4] 4400h Parameter 1 00h 0 0 0 0 4401h Parameter 2 00h N7 N6 N5 N4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 N8 N3 N2 N1 N0 R/W 2 Default Value 00h 00h - The Tearing Effect Line On has one parameter that describes the Tearing Effect Output Line mode. The Tearing Effect Output line consists of V-Blanking information only. Note: (1) That TEARLINE with N = '0' is equivalent to TEON with M = '0'. (2) The Tearing Effect Output line shall be active low when the display module is in Sleep mode. Description Register 3500h, 4400h and 4401h both define TE Output: 3500h M 4400h ~ 4401h N TE Output 0 0 TE high in V-porch region (A) 1 0 TE high in all V-porch and H-porch region (B) 0 ≠0 TE high at N-th line (C) 1 ≠0 TE high in all V-porch and H-porch region (B) This command is used to set the FTE output position. Use "SET_TEAR_ON (3500h)" to set the FTE polarity and pulse width. N[8 : 0] Function Description 000h 1st Line 001h 2nd Line 002h 3rd Line 003h 4th Line : : : : 1DDh 478th Line 1DEh 479th Line 1DFh 480th Line Restriction 2012/05/11 - This command takes affect on the frame following the current frame. Therefore, if the Tear Effect (FTE) output is 249 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Register Availability Draft Version NT35310 already ON, the FTE output shall continue to operate as programmed by the previous SET_TEAR_ON, or SET_TEAR_SCANLINE, command until the end of the frame. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h Note (1) N[8 : 0] = 000h: FTE outputs at 1st line. (2) Tearing effect off and M = '0'. 2012/05/11 250 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDSCL (45h):Read Scan Line Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Address (Other I/F) D[15 : 8] 4500h Parameter 1 00h D[7] SL15 4501h Parameter 2 00h SL7 Draft Version NT35310 4500h ~ 4501h 45h D[6] D[5] SL14 SL6 SL13 SL5 D[4] SL12 SL4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] SL11 SL10 SL9 SL8 SL3 SL2 SL1 SL0 R 2 Default Value N/A N/A Description Restriction - This command is used to read scan line data. - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value N/A N/A N/A 2012/05/11 251 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 ENTER_DSTB_MODE (4Fh): Enter the Deep Standby Mode Address (MDDI I/F) Address (Other I/F) 4F00h 4Fh Address (MDDI I/F) Address (Other I/F) D[15 : 8] D[7] D[6] D[5] D[4] 4F00h Parameter 1 00h 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 DSTB R/W 1 Default Value 00h Description - This command is used to enter deep standby mode. DSTB = '1': Enter the deep standby mode. Notice 1: It can't exit deep standby mode when set DSTB from ‘1’ to '0'. Notice 2: User can not write this register in Sleep-Out or Display-On mode. Note: To exit deep standby mode, please set RESX pin low pulse more than 3 msec Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 252 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WRDISBV (51h): Write Display Brightness Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] 5100h Parameter 1 00h D[7] DBV7 5100h 51h D[6] D[5] DBV6 DBV5 D[4] DBV4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] DBV3 DBV2 DBV1 DBV0 W 1 Default Value 00h Description - This command is used to adjust or returns the brightness value of the display. In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. DBV[7:0] PWM Duty (Ratio) PWM Duty (%) 00h Off 0% 01h 2 / 256 0.78125 % 02h 3 / 256 1.171875 % 03h 4 / 256 1.5625 % : : : : : : FDh 254 / 256 99.21875 % FEh 255 / 256 99.609375 % FFh 1 (Default) 100 % Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 253 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDDISBV (52h): Read Display Brightness Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] 5200h Parameter 1 00h D[7] DBV7 5200h 52h D[6] D[5] DBV6 DBV5 D[4] DBV4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] DBV3 DBV2 DBV1 DBV0 R 1 Default Value 00h Description - This command is used to returns the brightness value of the display. In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. Please refer the register "WRDISBV (5100h)" for detailed. DBV[7 : 0] is “0” (RDDISBV, 52h) when display is in sleep-in mode. DBV[7 : 0] is "0" (RDDISBV, 52h) when bit BCTRL of "Write CTRL Display (5300h)" command is "0". DBV[7 : 0] is manual set brightness specified with "Write CTRL Display (5300h)" command when bit BCTRL is "1" . When bit BCTRL of "Write CTRL Display (5300h)" command are "1", DBV[7 : 0] output is the brightness value specified with "Write Profile Value for Display (5000h)" command according to the ambient light. Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 254 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WRCTRLD (53h): Write CTRL Display Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] 5300h Parameter 1 00h 0 5300h 53h D[6] D[5] D[4] 0 BCTRL - Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] DD BL - - W 1 Default Value 00h - This command is used to control the "LEDPWM" pin, dimming function for CABC. BCTRL: Turn On / Off the brightness control block with the dimming effect. About the register "LEDPWPOL", please refer to the register "ABC_CTRL02 (02C0h)" BCTRL LEDPWPOL LEDPWM Pin Final State Backlight Final State 0 0 Keep “LOW” (0% PWM Duty) (Default) OFF 1 0 PWM Output (High level is duty) ON 0 1 Keep “HIGH” (0% PWM Duty) OFF 1 1 Inversed PWM Output (Low level is duty) ON Description DD: Enable / Disable dimming function only for CABC. DD 0 1 CABC Dimming Function Disabled Enabled (Default) BL: Turn On/Off the backlight control without dimming effect. BL Backlight Control 0 OFF (Default) 1 ON When BL bit change from '1' to '0', backlight is turned off without gradual dimming, even if dimming-on (DD = '1') are selected. 2012/05/11 255 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Description Restriction Register Availability Default Value Draft Version NT35310 Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 256 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDCTRLD (54h): Read CTRL Display Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] 5400h Parameter 1 00h 0 5400h 54h D[6] D[5] D[4] 0 BCTRL - Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] DD BL - - R 1 Default Value 00h - This command is used to "read" the setting status of "LEDPWM" pin, dimming function for CABC. BCTRL: Turn On / Off the brightness control block with the dimming effect. About the register "LEDPWPOL", please refer to the register (19C0h) BCTRL LEDPWPOL LEDPWM Pin Final State 0 0 Keep “LOW” (0% PWM Duty) (Default) 1 0 PWM Output (High level is duty) 0 1 Keep “HIGH” (0% PWM Duty) 1 1 Inversed PWM Output (Low level is duty) Backlight Final State OFF ON OFF ON Description DD: Enable / Disable dimming function only for CABC. DD 0 1 CABC Dimming Function Disabled Enabled (Default) BL: Turn On/Off the backlight control without dimming effect. BL Backlight Control 0 OFF (Default) 1 ON When BL bit change from '1' to '0', backlight is turned off without gradual dimming, even if dimming-on (DD = '1') are selected. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 257 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WRCTRLD (55h): Write CTRL Display Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] 5500h Parameter 1 00h 5500h 55h D[7] D[6] D[5] D[4] IMAGE_ENHANCEMENT [3:0] Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 CABC_COND[1 : 0] W 1 Default Value 00h Description - This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. CABC_COND[1 : 0] Function 0 0 Off (Default) 0 1 User Interface Image (UI-Mode) 1 0 Still Picture Image (Still-Mode) 1 1 Moving Image (Moving-Mode) - The NT35310 provides 4 different Image Enhancement (IE) technologies that include Smart Contrast, Vivid Color, Smart Color and Edge Enhancement. The three sets for IE Low/Medium/High level can be selected by IMAGE_ENHANCE[3:0] as below table. User can define each IE level value of these four IE technologies independently in “CMD2 Page2” Registers. The real register addresses are also described in below table. IMAGE_ENHANCEMENT[3:0] IE Level Smart Contrast Vivid Color Smart Color Edge Enhancement 0 0 0 0 1 0 0 0 IE_Low LEVEL_01 IE and OFF LEVEL01 RATIO_SEL01 LEVEL_01 1 0 0 1 IE_Medium LEVEL_02 LEVEL02 RATIO_SEL02 LEVEL_02 1 0 1 1 IE_High LEVEL_03 LEVEL03 RATIO_SEL03 LEVEL_03 Restriction - This register is synchronized with V-sync by internal circuit. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 258 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDCABC (56h): Read Content Adaptive Brightness Control (CABC) Mode Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] 5600h Parameter 1 00h 5600h 56h D[7] D[6] D[5] D[4] IMAGE_ENHANCEMENT [3:0] Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 CABC_COND[1 : 0] R 1 Default Value 00h Description - This command is used to "read" the CABC operation mode. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. CABC_COND[1 : 0] Function 0 0 Off (Default) 0 1 User Interface Image (UI-Mode) 1 0 Still Picture Image (Still-Mode) 1 1 Moving Image (Moving-Mode) - Image Enhancement (IE) read by IMAGE_ENHANCEMENT [3:0] as below table. IMAGE_ENHANCEMENT[3:0] IE Level Smart Contrast Vivid Color Smart Color Edge Enhancement 0 0 0 0 1 0 0 0 IE_Low LEVEL_01 IE and OFF LEVEL01 RATIO_SEL01 LEVEL_01 1 0 0 1 IE_Medium LEVEL_02 LEVEL02 RATIO_SEL02 LEVEL_02 1 0 1 1 IE_High LEVEL_03 LEVEL03 RATIO_SEL03 LEVEL_03 Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 259 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version WRCABCMB (5Eh): Write CABC Minimum Brightness NT35310 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] D[7] (MDDI I/F) (Other I/F) 5E00h Parameter 1 00h 5E00h 5Eh D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] CMB[7 : 0] W 1 Default Value 00h Description - This command is used to set the minimum brightness value of the display for CABC function. 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 260 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDCABCMB (5Fh): Read CABC Minimum Brightness Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] 5F00h Parameter 1 00h 5F00h 5Fh D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] CMB[7 : 0] R 1 Default Value 00h Description - This command is used to “read” the minimum brightness value of the display for CABC function. 00h value means the lowest brightness for Full-ABC (CABC + LABC) and FFh value means the highest brightness for CABC. Restriction - Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 261 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDDSDR (68h): Read Display Self-Diagnostic Result Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) 6800h Parameter D[15 : 8] (Other I/F) Parameter 1 00h D[7] D7 6800h 68h D[6] D[5] D[4] D6 D5 D4 D[3] D3 Access Attribute Number of Parameter(s) D[2] D[1] D[0] D2 D1 D0 R 1 Default Value 00h - This command indicates the status of the display self-diagnostic results after Sleep Out. This command is described in the table below. - The inverse of checksum compare will output to GPIO pin when select this function. Normally GPIO pin remains high, when ESD occurs leads to checksum comparison fail, it will output low pulse or keep low to notify the ESD alarm to host. Description Restriction Bit Description Value D7 Register Loading Detection See section “Register Loading Detection” D6 Functionality Detection See section “Functionality Detection” D5 Chip Attachment Detection “0” (Not used) D4 Display Glass Break Detection “0” (Not used) D3 Not Used “0” (Not used) D2 Not Used “0” (Not used) D1 Not Used “0” (Not used) “1”=Checksums are “0”=Checksums are D0 Checksums Compare not same same (Default) - It will be necessary to wait 300ms after there is the last write access on DCS area registers before there can read Bit D0 value. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 262 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. SET_MDDI (8Fh) Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] 8F00h Parameter 1 00h 0 Draft Version NT35310 8F00h 8Fh Access Attribute R/W Number of Parameter(s) 1 D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value 0 0 0 0 0 0 MDDI_I 01h Description - MDDI output current selection. MDDI_I 0 1(default) Function Description 3.5mA (MDDI 1.0) 2.0mA (MDDI 1.2) Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In AE00h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 01h 01h 01h 2012/05/11 263 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDDDBS (A1h): Read DDB Start Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] D[7] (MDDI I/F) (Other I/F) A100h Parameter 1 00h A101h Parameter 2 00h A102h Parameter 3 00h A103h Parameter 4 00h A104h Parameter 5 00h Draft Version NT35310 A100h ~ A104h A1h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] SID[7 : 0] SID[15 : 8] MRID[7 : 0] MRID[15 : 8] FFh R 5 Default Value N/A N/A N/A N/A FFh Description -This command returns the supplier identification and display module mode/revision information. Note: This information is not the same what “Read ID1 (DAh)”, “Read ID2 (DBh)” and “Read ID3 (DCh)” commands are returning. SID[7:0]: LCD module’s manufacturer ID. SID[15:8]: LCD module/driver version ID MRID[7:0]: LCD module/driver ID MRID[15:8]: IC version code FFh : Exit code – there is no more data in the Descriptor Block This read sequence can be interrupted by any command and it can be continued by “Read DDB Continue (A8h)” command when the first parameter, what has been transferred, is the parameter, which has not been sent e.g. RDDDBS => 1st parameter has been sent => 2nd parameter has been sent=> interrupt => RDDDBC => 3rd parameter of the RDDDBS has been sent. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Value A100h ~ A103h: Status Power On Sequence S/W Reset H/W Reset A104h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Default Value FFh FFh FFh 2012/05/11 264 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDDDBC (A8h): Read DDB Continue Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] D[7] (MDDI I/F) (Other I/F) A800h Parameter 1 00h A801h Parameter 2 00h A802h Parameter 3 00h A803h Parameter 4 00h A804h Parameter 5 00h A800h ~ A806h A8h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] SID[7 : 0] SID[15 : 8] MRID[7 : 0] MRID[15 : 8] FFh R 7 Default Value N/A N/A N/A N/A FFh Description -A read_DDB_start command should be executed at least once before a read_DDB_continue command to define the read location. Otherwise, data read with a read_DDB_continue command is undefined. Restriction - SPI IF don’t support continune read. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Value A800h ~ A803h: Status Power On Sequence S/W Reset H/W Reset A804h: Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Default Value FFh FFh FFh 2012/05/11 265 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDFCS (AAh): Read First Checksum Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] (MDDI I/F) (Other I/F) AA00h Parameter 1 00h D[7] FCS7 AA00h AAh D[6] D[5] FCS6 FCS5 D[4] FCS4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] FCS3 FCS2 FCS1 FCS0 R 1 Default Value 00h Description Restriction - This command returns the first checksum what has been calculated from System function registers and the frame memory after the write access to those registers and/or frame memory has been done. (1) It will be necessary to wait 150 ms after there is the last write access on System function registers before there can read this checksum value. (2) The display module is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter (= more than 2 RDX cycle) on MCU interface. Only 2nd parameter is sent on DSI (The 1st parameter is not sent). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes AA00h: Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 266 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version MDDI_WAKE_TOGGLE (ADh): MDDI VSYNC BASED LINK WAKE-UP Address (MDDI I/F) Address (Other I/F) AD00h ADh D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter No Argument NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] W 0 Default Status Description - This register enables the Vsync based Link wakeup in Client for MDDI interface. After the host brings the link out of hibernation, this register is cleared. Detail please refer to Vsync Based Link Wakeup section. - Vsync based Link wakeup function is turned on when 0xAD00 is written, no matter “with” or “without” parameter. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Status 00h 00h 00h 2012/05/11 267 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. STB EDGE POSITION (AEh) Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15 : 8] D[7] AE00h Parameter 1 00h Draft Version NT35310 AE00h AEh D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] STB_EDGE_SEL[7:0] R/W 1 Default Value 00h -It is used to set a rising edge position of STB signal that refers to the falling edge of Display HSYNC. Its minimum adjusted step is one display clock period (around 230ns). STB signal is repeated at per line except VBP/VFP region and outputs from TE1 pad. It can be enable or disable by MTP register B3h of CMD2 Page0 (bit “LPM_HZ” is 0; and bit “TE1_ON” is 1). Description Restriction STB_EDGE_SEL[7:0] 00h 01h 02h : : 80h : : FFh Adjusted STB rising edge position Aligned to the falling edge of HSYNC +1 +2 : : +128 : : +255 Note: 1. In above table, “+” index that STB rising edge is set to lag the falling edge of Display HSYNC. 2. The unit of “Adjusted STB rising edge position” is number of Display Clock. - 2012/05/11 268 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In AE00h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 269 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDCCS (AFh): Read Continue Checksum Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] (MDDI I/F) (Other I/F) AF00h Parameter 1 00h D[7] CCS7 AF00h AFh D[6] D[5] CCS6 CCS5 D[4] CCS4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] CCS3 CCS2 CCS1 CCS0 R 1 Default Value 00h Description Restriction - This command returns the continue checksum what has been calculated continuously after the first checksum has calculated from System function registers and the frame memory after the write access to those registers and/or frame memory has been done. (1) It will be necessary to wait 300 ms after there is the last write access on System function registers before there can read this checksum value in the first time. (2) The display module is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter (= more than 2 RDX cycle) on MCU interface. Only 2nd parameter is sent on DSI (The 1st parameter is not sent). Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes AF00h: Default Value Status Power On Sequence S/W Reset H/W Reset Default Value 00h 00h 00h 2012/05/11 270 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDID1 (DAh): Read ID1 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] (MDDI I/F) (Other I/F) DA00h Parameter 1 00h D[7] ID17 Draft Version NT35310 DA00h DAh D[6] D[5] ID16 ID15 D[4] ID14 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] ID13 ID12 ID11 ID10 R 1 Default Value N/A Description Restriction - This read byte identifies the display module's manufacturer. - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In DA00h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A 2012/05/11 271 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDID2 (DBh): Read ID2 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] D[7] (MDDI I/F) (Other I/F) DB00h Parameter 1 00h 1 Draft Version NT35310 DB00h DBh D[6] D[5] ID26 ID25 D[4] ID24 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] ID23 ID22 ID21 ID20 R 1 Default Value N/A Description - This read byte is used to track the display module/driver version. It is defined by display supplier and changes each time a revision is made to the display, material or construction specifications. See Table: ID Byte Value 80h Version Version1 Changes : 81h Version2 : 82h Version3 : Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In DB00h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A 2012/05/11 272 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. RDID3 (DCh): Read ID3 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15 : 8] (MDDI I/F) (Other I/F) DC00h Parameter 1 00h D[7] ID37 Draft Version NT35310 DC00h DCh D[6] D[5] ID36 ID35 D[4] ID34 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] ID33 ID32 ID31 ID30 R 1 Default Value N/A Description Restriction - This read byte identifies the display module / driver. - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In DC00h: Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A 2012/05/11 273 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 IDLEMODE_BL_Control (E1h): Write IDLEMODE_BL_Control Address (MDDI I/F) E100h Address (Other I/F) E1h Address Parameter (MDDI (Other D[15 : 8] D[7] D[6] D[5] D[4] I/F) I/F) E100h Parameter 1 00h 0 0 0 0 Access Attribute W Number of Parameter(s) 1 D[3] D[2] D[1] D[0] Default Value 0 0 IDLE_ON_ SIGNAL_E N IDLE_MOD E_BL_EN 00h - The content of the register IDLEMODE_BL_control will define the functionality of the transmissive LCD display backlight behavior in idle mode which is enabled by command IDMON (39h). In this mode, the backlight power consumption will be reduced with several methods. Description IDLE_ON_SIGNAL_EN: This bits controls the HW signal called IDLE_ON, which is wired from display to handset backlight drive. This bits can be used to dim handset backlight DC drive current in the idle mode. Note that display BC output will be still controllable by the register Write Display Brightness. IDLE_ON_SIGNAL_EN Function 0 output signal IDLE_ON is disabled and set to GND 1 output signal IDLE_ON is enabled and set to logical high when idle mode is entered. (Logical high means VDDI). ※The idle on signal should toggle state upon falling edge of the BC signal. IDLE_MODE_BL_EN: 0 = Entering idle mode using command IDMON has no effect to display backlight behavior. Backlight control is controlled by Write Display Brightness (51h) and Write CTRL Display (53h) registers. 1 = Entering the idle mode will cause display to enter into idle mode specific backlight state defined by IDLE_ON_SIGNAL_EN bit. Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 274 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. E100h: Default Value Draft Version NT35310 Status Power On Sequence S/W Reset H/W Reset Default Value N/A N/A N/A 2012/05/11 275 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 IDLEMODE_BL_Control (E2h): Read IDLEMODE_BL_Control Address (MDDI I/F) E200h Address (Other I/F) E2h Address Parameter (MDDI (Other D[15 : 8] D[7] D[6] D[5] D[4] I/F) I/F) E200h Parameter 1 00h 0 0 0 0 Access Attribute R Number of Parameter(s) 1 D[3] D[2] D[1] D[0] Default Value 0 0 IDLE_ON_ SIGNAL_E N IDLE_MOD E_BL_EN 00h - The content of the register IDLEMODE_BL_control will define the functionality of the transmissive LCD display backlight behavior in idle mode which is enabled by command IDMON (39h). In this mode, the backlight power consumption will be reduced with several methods. Description IDLE_ON_SIGNAL_EN: This bits controls the HW signal called IDLE_ON, which is wired from display to handset backlight drive. This bits can be used to dim handset backlight DC drive current in the idle mode. Note that display BC output will be still controllable by the register Write Display Brightness. IDLE_ON_SIGNAL_EN Function 0 output signal IDLE_ON is disabled and set to GND 1 output signal IDLE_ON is enabled and set to logical high when idle mode is entered. (Logical high means VDDI). ※The idle on signal should toggle state upon falling edge of the BC signal. IDLE_MODE_BL_EN: 0 = Entering idle mode using command IDMON has no effect to display backlight behavior. Backlight control is controlled by Write Display Brightness (51h) and Write CTRL Display (53h) registers. 1 = Entering the idle mode will cause display to enter into idle mode specific backlight state defined by IDLE_ON_SIGNAL_EN bit. Restriction - Register Availability Default Value E200h: Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Buffer Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A 2012/05/11 276 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. PAGE_CTRL (EDh):Unlock CMD2 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] D[7] (MDDI I/F) (Other I/F) ED00h Parameter 1 0 0 ED01h Parameter 2 0 1 Draft Version NT35310 ED00h ~ ED01h EDh D[6] D[5] D[4] 0 0 0 1 1 1 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 1 1 1 1 0 W 2 Default Value 01h FEh This command is used for UNLOCK of CMD2. Note:After hardware reset or software reset input, the input of Driver Function command is locked. Description Restriction 2012/05/11 277 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Register Availability Default Value Draft Version NT35310 Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Status Default Value (ED00h) Default Value (ED01h) 2012/05/11 278 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PAGE_STATUS (FFh):PAGE unlock status Address (MDDI I/F) FF00h Access Attribute R Address (Other I/F) FFh Number of Parameter(s) 1 Address Parameter D[15:8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default (MDDI I/F) (Other I/F) Value - Parameter 1 - 0 0 0 0 0 CMD2_P1 CMD2_P0 CMD1 01h Description - This command is used for checking the current CMD accessing status (except MDDI I/F ). Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value D[15:0] 0001h 0001h 0001h 2012/05/11 279 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 6.2 CMD2_P0 register list Draft Version NT35310 Inst Para Addr. R/W Parameter D7 DISPLAY_CTRL B0h R/W 1 DSIN R/W 1 PORCH_CTRL B1h R/W 2 R/W 3 - R/W 1 FRAMERATE_C B2h R/W 2 TRL R/W 3 D6 - BPAC[8] D5 D4 D3 PT1[1:0] CRL BPAC[7:0] BPB[7:0] - BPB[8] RTNA[7:0] RTNB[7:0] RTNC[7:0] D2 CTB D1 D0 PT[1:0] FP[3:0] Code MTP 00h V 1Ch V 1Ch V 04h V 8Dh D3h V 8Dh SPI&RGB IF SETTING B3h R/W 1 SDA_EN BYPASS LPM_HZ TE1_ON - - - DM 20h V INVCTRL B4h R/W PMTCTL Partial and R/W Partial Idle B5h Mode Timing R/W Control R/W R/W R/W SOURCE EQ B6h R/W R/W R/W DISPLAY_CTRL 2 B7h R/W MTP Selection B8h R/W CABC Control BBh R/W R/W PWR_CTRL1 ADJ GVDDP/N C0h R/W R/W R/W PWR_CTRL2 AVDD C1h R/W R/W R/W PWR_CTRL3 VGH & VGL C2h PWR_CTRL4 (AVEE) C3h R/W PWR_CTRL5 VCOM C4h R/W R/W PWR_CTRL6 VCOM C5h R/W R/W R/W PWR_CTRL6 C6h R/W VGH&VGL CLAMP 1 - NLC[1:0] NLB[1:0] NLA[1:0] 0Ch V 1 INCYLB[3:0] INCYLC[3:0] 00h V 2 AVEE_NDISP_DIV VGH_NDISP_DIV VCL_NDISP_DIV AVDD_NDISP_DIV 00h 1 - - - 2 - - - 3 - - - 4 - - - 5 - - - 6 - - SDT[4:0] EQI1[4:0] EQI2[4:0] EQG[4:0] SOE_S[4:0] SOE_W[5:0] 02h 08h 08h V 08h 10h 23h 1 - - REV SRGB CTS - - - 00h V 1 - - - - - PTM[1:0] MTP_W_ 00h GMA 1 - - - - - SYNC_PWM_FR EQ[2:0] 00h V 1 - 2 - 3 - 4 - VRHP[6:0] VRHN[6:0] VGSP[6:0] VGSN[6:0] 44h 44h V 10h 10h 1 - CP1_MO PUMP_MODE[1:0 DE ] - BTP1CKA_EXT[2:0] 13h V 2 - BTP1CKB_EXT[2:0] - BTP1CKC_EXT[2:0] 33h 1 - VGHL_A[2:0] - VGHL_CLKA[2:0] 44h 2 VGHL_B[2:0] - VGHL_CLKB[2:0] 44h V 3 VGHL_C[2:0] - VGHL_CLKC[2:0] 44h 1 - - BTP5CKC_EXT[1:0] BTP5CKB_EXT[1:0] BTP5CKA_EXT[1:0] 2Ah V 1 VMDC[7:0] 40h V 1 - 2 - 3 - ISOPP[2:0] SAPPA[2:0] SAPPB[2:0] BIAS_RE DUCE - - ISOPN[2:0] SAPNA[2:0] SAPNB[2:0] 4Ch 44h V 44h 4 - SAPPC[2:0] - SAPNC[2:0] 44h 4 - - - - - - VGHCL VGLCL_ _OFF OFF 00h V VGL_CLAMPA[3:0] VGH_CLAMPA[3:0] E2h V 2012/05/11 280 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WRID1 WRID2 WRID3 RDID4 WRDDB RDVNT EPR/W MTPWR D1h R/W D2h R/W D3h R/W R R D4h R R R/W R/W D5h R/W R/W DDh R R/W DEh R/W R/W DFh R/W RDREGEXT1 EBh R/W R R RDREGEXT2 ECh : R PAGE_CTRL Into CMD2_P0 EEh W W PAGE_CTRL Lock CMD2 00h W VGL_CLAMPB[3:0] VGH_CLAMPB[3:0] E2h V VGL_CLAMPC[3:0] VGH_CLAMPC[3:0] E2h V 1 WID1[7] WID1[6] WID1[5] WID1[4] WID1[3] WID1[2] WID1[1] WID1[0] 00h V 1 1 WID2[6] WID2[5] WID2[4] WID2[3] WID2[2] WID2[1] WID2[0] 80h V 1 WID3[7] WID3[6] WID3[5] WID3[4] WID3[3] WID3[2] WID3[1] WID3[0] 00h V 1 0 0 0 0 0 0 0 1 01h 2 0 1 0 1 0 0 1 1 53h 3 0 0 0 1 0 0 0 0 10h 4 0 0 0 0 ID4[3] ID4[2] ID4[1] ID4[0] 00h 1 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 00h 2 SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 00h V 3 MRID7 MRID6 MRID5 MRID4 MRID3 MRID2 MRID1 MID0 00h 4 MRID15 MRID14 MID13 MRID12 MRID11 MRID10 MRID9 MID8 00h 1 NV_N3 NV_N2 NV_N1 NV_N0 NV_GMA 0 NVP_F NV_P 00h 1 0 1 0 1 0 1 0 1 55h 2 1 0 1 0 1 0 1 0 AAh 3 0 1 1 0 0 1 1 0 66h 1 0 0 0 nROM 0 0 0 MTP_W 00h 1 Add7 Add6 Add5 Add4 Add3 Add2 Add1 Add0 1 Para17 Para16 Para15 Para14 Para13 Para12 Para11 Para10 2 Para27 Para26 Para25 Para24 Para23 Para22 Para21 Para20 : : : : : : : : : N ParaN7 ParaN6 ParaN5 ParaN4 ParaN3 ParaN2 ParaN1 ParaN0 1 1 1 0 1 1 1 1 0 DEh 2 0 0 1 0 0 0 0 1 21h 1 1 0 1 0 1 0 1 0 AAh PAGE_CTRL Into CMD2_P1 BFh W 1 1 0 1 0 1 0 1 0 AAh 2012/05/11 281 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. DISPLAY_CTRL (B0h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) B000h Parameter 1 0 D[7] DSIN Draft Version NT35310 B000h B0h D[6] D[5] D[4] 0 PT1[1:0] Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] CRL CTB PT[1:0] R/W 1 Default Value 00h Description PT[1:0]: Source setting in non-display area at partial mode. PT[1:0] Source (Positive/Negative) 0 V63+/ V63- 1 V0+/V0- 2 VSSA/VSSA 3 Hi-Z PT1[1:0]: Source setting in porch area. PT[1:0] 0 1 2 3 Source (Positive/Negative) V63+/ V63V0+/V0VSSA/VSSA Hi-Z CTB: Gate Scan Direction Select CTB 0 1 Gate G0→G479 G479→G0 CRL: Source Scan Direction Select CRL 0 1 Source S959→S0(Default) S0→S959 Restriction Register Availability DSIN:This command is use to power on/ off the SRAM at SLP_IN mode to prevent current leakage. DSIN Power ON / OFF 0h Power OFF SRAM at SLP_IN Mode (Default) 1h Power ON SRAM at SLP_IN Mode Note: If SRAM is powered off in SLP-IN mode, the leakage current can be reduced but the SRAM data will be lost. Also either read or write SRAM is NOT possible. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes 2012/05/11 282 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Default Value Draft Version NT35310 Status Power On Sequence S/W Reset H/W Reset Default Value D[7:0] 00h 00h 00h 2012/05/11 283 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PORCH_CTRL: Front & Back Porch Setting (B1h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] D[7] (MDDI I/F) (Other I/F) B100h Parameter 1 0 B100h ~ B101h B1h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] BPAC[7:0] R/W 3 Default Value 1Ch B101h Parameter 2 0 BPB[7:0] 1Ch B102h Parameter 3 0 0 BPAC[8] 0 BPB[8] FP[3:0] 04h BPAC[9:0]:Determines the number of lines for internal display back porch period (in normal mode and idle mode). Number of Lines for Internal Display Back Porch BPAC[8:0] Back Porch period(Line periods) 000h Setting Inhibited 001h 1 lines 002h 2 lines 003h 3 lines : : 01Ch 28lines(Default) : : 1FFh 511lines Description BPB[9:0]:Determines the number of lines for internal display back porch period (in partial mode). Number of Lines for Internal Display Back Porch BPB[8:0] Back Porch period(Line periods) 000h Setting Inhibited 001h 1 lines 002h 2 lines 003h 3 lines : : 01Ch 28lines(Default) : : 1FFh 511lines FP[3:0]:Determines the number of lines for internal display front porch period (a blank period at the end of display). Number of Lines for Internal Display Front Porch FP[3:0] Back Porch period(Line periods) 0000 Setting Inhibited 0001 1 lines 0010 2 lines 0011 3 lines 0100 4 lines(Default) : : : : 1111 15 lines 2012/05/11 284 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Restriction Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out B100h, B101h, B102h: Sleep In Status Power On Sequence S/W Reset H/W Reset B100h 1Ch 1Ch 1Ch Availability Yes Yes Yes Yes Yes B101h 1Ch 1Ch 1Ch B102h 04h 04h 04h 2012/05/11 285 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. FRAMERATE_CTRL (B2h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] B200h Parameter 1 0 B201h Parameter 2 0 B202h Parameter 3 0 Draft Version NT35310 B200h ~ B202h B2h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] RTNA[7:0] RTNB[7:0] RTNC[7:0] R/W 3 Default Value 8Dh D3h 8Dh Description RTNA[7:0]:Frame rate control in full colors normal mode (Normal mode on) RTNB[7:0]:Frame rate control in Idle mode (Idle mode on) RTNC[7:0]:Frame rate control in full colors Partial mode (Partial mode on / Idle mode off) - RTNA[7:0] / RTNB[7:0] / RTNC[7:0] are used to determine the 1H (line) period when NT35310 is under internal clock synchronized display operation. - The RTNA[7:0] / RTNB[7:0] / RTNC[7:0] are set depending on the panel resolution for frame rate adjustment. The following table is the setting example of RTNA[7:0] / RTNB[7:0] / RTNC[7:0] for different panel resolutions according to the frame frequency calculation formula below. H Line no. RTNA/B/C [7:0] Fosc (MHz) BP + FP 480 141 13 32 Note: Default value for Normal mode and Partial mode Frame rate (Hz) 60 H Line no. RTNA/B/C [7:0] Fosc (MHz) 480 211 13 Note: Default value for Idle mode BP + FP 32 FrameRate  RTN * Fosc / 3 Line  BP  FP Hz Frame rate (Hz) 40 - The frame frequency can be changed by modifying the RTNA[7:0] / RTNB[7:0] / RTNC[7:0] setting. - Make sure to set the proper frame frequency whenever the number of lines to drive the liquid crystal panel is changed. 2012/05/11 286 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Description Draft Version Clocks in 1H Period (Internal clock Operation, unit: DCK) RTN[7:0] Clocks per Line RTN[7:0] Clocks per Line 000h Reserved 076h Reserved 001h Reserved 077h Reserved : : 078h Reserved : : 079h Reserved : : 07Ah Reserved 04Ch Reserved 07Bh 123 04Dh Reserved 07Ch 124 04Eh Reserved 07Dh 125 04Fh Reserved 07Eh 126 050h Reserved 07Fh 127 051h Reserved 080h 128 052h Reserved 081h 129 053h Reserved 082h 130 054h Reserved 083h 131 055h Reserved 084h 132 056h Reserved 085h 133 057h Reserved 086h 134 058h Reserved 087h 135 059h Reserved 088h 136 05Ah Reserved 089h 137 05Bh Reserved 08Ah 138 05Ch Reserved 08Bh 139 05Dh Reserved 08Ch 140 05Eh Reserved 08Dh 141 05Fh Reserved 08Eh 142 060h Reserved 08Fh 143 061h Reserved 090h 144 062h Reserved 091h 145 063h Reserved 092h 146 064h Reserved 093h 147 065h Reserved 094h 148 066h Reserved 095h 149 067h Reserved 096h 150 068h Reserved 097h 151 069h Reserved 098h 152 06Ah Reserved 099h 153 06Bh Reserved 09Ah 154 06Ch Reserved 09Bh 155 06Dh Reserved 09Ch 156 06Eh Reserved 09Dh 157 06Fh Reserved 09Eh 158 070h Reserved 09Fh 159 071h Reserved 0A0h 160 072h Reserved 0A1h 161 073h Reserved 0A2h 162 074h Reserved 0A3h 163 075h Reserved 0A4h 164 0A5h 0A6h 0A7h 0A8h 0A9h 0AAh 0ABh 0ACh 0ADh 0AEh 0AFh 0B0h 0B1h 0B2h 0B3h 0B4h 0B5h 0B6h 0B7h 0B8h 0B9h 0BAh 0BBh 0BCh 0BDh 0BEh 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In NT35310 RTN[7:0] Clocks per Line 165 0D4h 212 166 0D5h 213 167 0D6h 214 168 0D7h 215 169 0D8h 216 170 0D9h 217 171 0DAh 218 172 0DBh 219 173 0DCh 220 174 0DDh 221 175 0DEh 222 176 0DFh 223 177 0E0h 224 178 0E1h 225 179 0E2h 226 180 0E3h 227 181 0E4h 228 182 0E5h 229 183 0E6h 230 184 0E7h 231 185 0E8h 232 186 0E9h 233 187 0EAh 234 188 0EBh 235 189 0ECh 236 190 0EDh 237 191 0EEh 238 192 0EFh 239 193 0F0h 240 194 0F1h 241 195 0F2h 242 196 0F3h 243 197 0F4h 244 198 0F5h 245 199 0F6h 246 200 0F7h 247 201 0F8h 248 202 0F9h 249 203 0FAh 250 204 0FBh 251 205 0FCh 252 206 0FDh 253 207 0FEh 254 208 0FFh 255 209 210 211 Availability Yes Yes Yes Yes Yes 2012/05/11 287 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version B200h: B201h: Default Value Status Power On Sequence S/W Reset H/W Reset Status Power On Sequence S/W Reset H/W Reset Default Value 8Dh 8Dh 8Dh Default Value D3h D3h D3h B202h: Status Power On Sequence S/W Reset H/W Reset Default Value 8Dh 8Dh 8Dh NT35310 2012/05/11 288 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 SPI&RGB IF SETTING (B3h): SPI&RGB INTERFACE SETTING Address (MDDI I/F) Address (Other I/F) B300h B3h D[15 : 8] D[7] D[6] D[5] D[4] D[3] Parameter - SDA_EN BYPASS LPM_HZ TE1_ON 0 Access Attribute Number of Parameter(s) D[2] D[1] D[0] 0 0 DM W/R 1 Default Status 20h Description -This command is used to set RGB interface related register. DM bit is used to select display operation mode. The setting allows switching between display operation in synchronization with internal oscillation clock,VSYNC, or RGB signal. DM Display Mode 0 Internal oscillation clock 1 RGB Interface BYPASS: Select the display data pathe whether memory or direct to display in RGB interface. BYPASS 0 1 Interface Select Memory Direction to display SDA_EN: 3/4 wire serial interface selection SDA_EN = “0”, DIN and DOUT pins are used for 3/4 wire serial interface. SDA_EN = “1”, DIN/SDA pin is used for 3/4 wire serial interface and DOUT pin is not used. SDA_EN 0 1 Input Pin SDA SDA Output Pin Dout SDA LPM_HZ: Used with TE1_ON. LPM_HZ 0 0 1 TE1_ON 0 1 X TE1/IDLE_ON LPM function (Control by E1h) TE1output Hiz Restriction Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Status 20h 20h 20h 2012/05/11 289 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. INVCTRL (B4h): Inversion Control Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] B400h Parameter 1 0 0 Draft Version NT35310 B400h B4h D[6] D[5] D[4] 0 NLC[1:0] Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] NLB[1:0] NLA[1:0] R/W 1 Default Value 0Ch Description Restriction Display inversion mode set NLA: Inversion setting in full colors normal mode (Normal mode on) NLB: Inversion setting in Idle mode (Idle mode on) NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLA / NLB / NLC [1:0] 0 1 2 3 Inversion 1dot inversion 2dot inversion 4dot inversion column inversion Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 0Ch 0Ch 0Ch 2012/05/11 290 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PMTCTL (B5h):Partial and Idle Mode Timing Control Address (MDDI I/F) B500h~B501h Access Attribute Address (Other I/F) B5h Number of Parameter(s) Address (MDDI I/F) B500h B501h Parameter (Other I/F) Parameter 1 Parameter 2 D[15:8] 0 0 D[7] D[6] D[5] D[4] INCYLB[3:0] AVEE_NDISP_DIV VGH_NDISP_DIV D[3] D[2] D[1] D[0] INCYLC[3:0] VCL_NDISP_DIV AVDD_NDISP_DIV R/W 2 Default Value 00h 00h Interval Partial Mode: To achieve lower power driving, non-refresh frame frequency should be able to set lower than normal refresh (Normal Frame). INTCYLC[ 3:0]:This command is use to set interval cycle frames in partial mode. INTCYLC[3: 0] Interval Cycle Frame 0000 Normal Refresh 0001 Normal Refresh 0010 3 0011 5 0100 7 : : Description : : 1111 29 Note: When INTCYLC[3:0] = 4’h0 means scan by normal partial mode INTCYLB[ 3:0]:This command is use to set interval cycle frames in idle mode. INTCYLB[3: 0] Interval Cycle Frame 0000 Normal Refresh 0001 Normal Refresh 0010 3 0011 5 0100 7 : : : : 1111 29 Note: When INTCYLB[3:0] = 4’h0 means scan by idle mode AVEE_NDISP_DIV: Set the operating frequency of the step-up circuit2(AVEE) in non-refresh status. VGH_NDISP_DIV: Set the operating frequency of the step-up circuit2(VGH) in non-refresh status. VCL_NDISP_DIV: Set the operating frequency of the step-up circuit2(VCL) in non-refresh status. AVDD _NDISP_DIV: Set the operating frequency of the step-up circuit2(AVDD) in non-refresh status. 2012/05/11 291 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version AVEE_NDISP_DIV [1:0] / VGH_NDISP_DIV [1:0] / VCL_NDISP_DIV [1:0]/ AVDD _NDISP_DIV[1:0] 00 01 10 11 Note1:CP_CLK= Nomal display mode CLK Note2: BT5CKB / C_EXT[1:0] + AVEE_NDISP_DIV [1:0] < = 4 NT35310 Charge pump CLK CP_CLK CP_CLK/2 CP_CLK/4 CP_CLK/8 Restriction Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h 2012/05/11 292 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. DISPLAY_CTRL_NORM (B6h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] B600h Parameter 1 0 0 B601h Parameter 2 0 0 B602h Parameter 3 0 0 B603h Parameter 4 0 0 B604h Parameter 5 0 0 B605h Parameter 6 0 0 Draft Version NT35310 B600h ~ B603h B6h D[6] D[5] D[4] 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] SDT[4:0] EQI1[4:0] EQI2[4:0] EQG [4:0] SOE_S [4:0] SOE_W[5:0] R/W 6 Default Value 02h 08h 08h 08h 10h 23h Description SDT[4:0]: Sets the source delay time. SDT[4:0] 00h 01h 02h : 11h : 1Eh 1Fh Note: 1 clk period = 1/4.33M EQG time (clk) 0 1 2 : 17 : 30 31 EQG[4:0]: Sets the equalizing period time. EQG[4:0] 00h 01h 02h : 08h : 1Eh 1Fh Note: 1 clk period = 1/4.33M EQG time (clk) 0 1 2 : 7 : 30 31 EQI1,2[4:0]: Sets the equalizing period time. EQI1,2[4:0] 00h 01h 02h : 08h : 1Eh EQI time (clk) 0 1 2 : 7 : 30 2012/05/11 293 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Restriction Draft Version 1Fh 31 Note: 1 clk period = 1/4.33M SOE_S[4:0]: Source output enable start time. SOE_S[4:0] 00h 01h 02h 03h 04h : 1Fh Note: 1 clk period = 1/4.33M SOE Start Time (clk) 0 1 2 3 4 : 31 SOE_W[5:0]: Source output enable start time. SOE_W[5:0] 00h 01h 02h 03h 04h : 3Fh Note: 1 clk period = 1/4.33M SOE Start Time (clk) 0 1 2 3 4 : 62 - NT35310 Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset B600h 02h 02h 02h B601h 08h 08h 08h B602h 08h 08h 08h Availability Yes Yes Yes Yes Yes B603h 08h 08h 08h B604h 10h 10h 10h B605h 23h 23h 23h 2012/05/11 294 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version DISPLAY_CTRL2: Set the States for LED Control (B7h) Address (MDDI I/F) Address (Other I/F) Address (MDDI I/F) Parameter (Other I/F) D[15: 8] D[7] B700h Parameter 1 0 0 B700h B7h D[6] D[5] 0 REV D[4] SRGB D[3] CTS NT35310 Access Attribute Number of Parameter(s) D[2] D[1] D[0] 0 0 0 R/W 1 Default Value 00h CTS:This command is use to selection for CMD1 instruction code. CTS Selection for CMD1 Instruction Code 0h Support FULL Command Set (Default) 1h Only Support Nokia Command Set Description Restriction REV: Normally White or Normally Black Select. REV Panel Data Color Source 0x00 Black V0+/V0- 0 NW 0xFF White V63+/V63- 0x00 Black V63+/V63- 1 NB 0xFF White V0+/V0- Example: Using NW Panel, set REV = 0 (digital not reverse data) => Data code = ‘d0, results in BLACK, vice versa. SRGB: RGB Order Select SRGB 0 1 Order RGB BGR Gamma Normal RB Swap Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes B700h 00h 00h 00h 2012/05/11 295 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. MTP Selection (B8h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] B800h Parameter 1 0 0 Draft Version NT35310 B800h B8h D[6] D[5] D[4] 0 0 0 Access Attribute R/W Number of Parameter(s) 1 D[3] D[2] D[1] D[0] Default Value 0 PTM[1:0] MTP_W_GMA 00h Description Restriction PTM:MTP margin read mode select. PTM[1:0] 00 01 10 11 MTP_W_GMA: Used to enable/disable MTP write gamma. MTP_W_GMA 0 1 Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Function 00h(Default) Reversed Full Access Margin Reversed Function Disable Enable(Default) Availability Yes Yes Yes Yes Yes Default Value D[7:0] 00h 00h 00h 2012/05/11 296 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. PWR_CTRL1 (C0h) Draft Version NT35310 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] C000h Parameter 1 0 0 C000h ~ C001h C0h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VRHP[6:0] R/W 2 Default Value 44h C001h Parameter 2 0 0 VRHN[6:0] 44h C002h Parameter 3 0 0 C003h Parameter 4 0 0 VGSP[6:0] 10h VGSN[6:0] 10h Description Set the GVDD regulator output voltage. VRHP[6:0]: set the GVDDP regulator output voltage. DEC VRHP (V) 0 1 2 3 Reserved 4 5 6 7 00001000 8 00001001 9 00001010 10 00001011 11 00001100 12 00001101 13 00001110 14 00001111 15 00010000 16 00010001 17 00010010 18 00010011 19 00010100 20 00010101 21 00010110 22 00010111 23 00011000 24 00011001 25 00011010 26 00011011 27 00011100 28 00011101 29 00011110 30 00011111 31 00100000 32 00100001 33 2.8 01000000 2.825 01000001 2.85 01000010 2.875 01000011 2.9 01000100 2.925 01000101 2.95 01000110 2.975 01000111 3 01001000 3.025 01001001 3.05 01001010 3.075 01001011 3.1 01001100 3.125 01001101 3.15 01001110 3.175 01001111 3.2 01010000 3.225 01010001 3.25 01010010 3.275 01010011 3.3 01010100 3.325 01010101 3.35 01010110 3.375 01010111 3.4 01011000 3.425 01011001 3.45 01011010 3.475 01011011 3.5 01011100 3.525 01011101 3.55 01011110 3.575 01011111 3.6 01100000 3.625 01100001 DEC VRHP (V) 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 4.4 4.425 4.45 4.475 4.5 4.525 4.55 4.575 4.6 4.625 4.65 4.675 4.7 4.725 4.75 4.775 4.8 4.825 4.85 4.875 4.9 4.925 4.95 4.975 5 5.025 5.05 5.075 5.1 5.125 5.15 5.175 5.2 5.225 2012/05/11 297 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 34 3.65 01100010 98 5.25 35 3.675 01100011 99 5.275 36 3.7 01100100 100 5.3 37 3.725 01100101 101 5.325 38 3.75 01100110 102 5.35 39 3.775 01100111 103 5.375 40 3.8 01101000 104 5.4 41 3.825 01101001 105 5.425 42 3.85 01101010 106 5.45 43 3.875 01101011 107 5.475 44 3.9 01101100 108 5.5 45 3.925 01101101 109 46 3.95 01101110 110 47 3.975 01101111 111 48 4 01110000 112 49 4.025 01110001 113 50 4.05 01110010 114 51 4.075 01110011 115 52 4.1 01110100 116 53 4.125 01110101 117 54 4.15 01110110 118 Reserved 55 4.175 01110111 119 56 4.2 01111000 120 57 4.225 01111001 121 58 4.25 01111010 122 59 4.275 01111011 123 60 4.3 01111100 124 61 4.325 01111101 125 62 4.35 01111110 126 63 4.375 01111111 127 VRHN[6:0]: set the GVDDN regulator output voltage. DEC VRHN (V) 0 -2.8 01000000 1 -2.825 01000001 2 -2.85 01000010 Reserved 3 -2.875 01000011 4 -2.9 01000100 5 -2.925 01000101 6 -2.95 01000110 7 -2.975 01000111 00001000 8 -3 01001000 00001001 9 -3.025 01001001 00001010 10 -3.05 01001010 00001011 11 -3.075 01001011 00001100 12 -3.1 01001100 00001101 13 -3.125 01001101 00001110 14 -3.15 01001110 DEC VRHN (V) 64 -4.4 65 -4.425 66 -4.45 67 -4.475 68 -4.5 69 -4.525 70 -4.55 71 -4.575 72 -4.6 73 -4.625 74 -4.65 75 -4.675 76 -4.7 77 -4.725 78 -4.75 2012/05/11 298 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 00001111 15 -3.175 01001111 79 -4.775 00010000 16 -3.2 01010000 80 -4.8 00010001 00010010 17 -3.225 01010001 18 -3.25 01010010 81 -4.825 82 -4.85 00010011 19 -3.275 01010011 83 -4.875 00010100 00010101 20 -3.3 01010100 21 -3.325 01010101 84 -4.9 85 -4.925 00010110 22 -3.35 01010110 86 -4.95 00010111 23 -3.375 01010111 87 -4.975 00011000 24 -3.4 01011000 88 -5 00011001 25 -3.425 01011001 89 -5.025 00011010 26 -3.45 01011010 90 -5.05 00011011 27 -3.475 01011011 91 -5.075 00011100 00011101 28 -3.5 01011100 29 -3.525 01011101 92 -5.1 93 -5.125 00011110 30 -3.55 01011110 94 -5.15 00011111 31 -3.575 01011111 95 -5.175 00100000 00100001 32 -3.6 01100000 33 -3.625 01100001 96 -5.2 97 -5.225 00100010 34 -3.65 01100010 98 -5.25 00100011 35 -3.675 01100011 99 -5.275 00100100 36 -3.7 01100100 100 -5.3 00100101 37 -3.725 01100101 101 -5.325 00100110 38 -3.75 01100110 102 -5.35 00100111 39 -3.775 01100111 103 -5.375 00101000 00101001 40 -3.8 01101000 41 -3.825 01101001 104 -5.4 105 -5.425 00101010 42 -3.85 01101010 106 -5.45 00101011 00101100 43 -3.875 01101011 44 -3.9 01101100 107 -5.475 108 -5.5 00101101 00101110 45 -3.925 01101101 46 -3.95 01101110 109 Reserved 110 00101111 47 -3.975 01101111 111 00110000 48 -4 01110000 112 00110001 49 -4.025 01110001 113 00110010 50 -4.05 01110010 114 00110011 00110100 51 -4.075 01110011 115 52 -4.1 01110100 116 00110101 00110110 53 -4.125 01110101 117 54 -4.15 01110110 118 00110111 55 -4.175 01110111 119 00111000 56 -4.2 01111000 120 00111001 00111010 57 -4.225 01111001 121 58 -4.25 01111010 122 2012/05/11 299 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 00111011 00111100 00111101 00111110 00111111 59 -4.275 01111011 123 60 -4.3 01111100 124 61 -4.325 01111101 125 62 -4.35 01111110 126 63 -4.375 01111111 127 VGSP [6:0]: set the VGSP regulator output voltage. DEC Reserved 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 VGSP (V) 0 0 0010101 1 0.025 0010110 2 0.05 0010111 3 0.075 0011000 4 0.1 0011001 5 0.125 0011010 6 0.15 0011011 7 0.175 0011100 8 0.2 0011101 9 0.225 0011110 10 0.25 0011111 11 0.275 0100000 12 0.3 0100001 13 0.325 0100010 14 0.35 0100011 15 0.375 0100100 16 0.4 0100101 17 0.425 0100110 18 0.45 0100111 19 0.475 0101000 20 0.5 0101000 DEC VGSP (V) 21 0.525 22 0.55 23 0.575 24 0.6 25 0.625 26 0.65 27 0.675 28 0.7 29 0.725 30 0.75 31 0.775 32 0.8 33 0.825 34 0.85 35 0.875 36 0.9 37 0.925 38 0.95 39 0.975 40 1 Reserved VGSN [6:0]: set the VGSN regulator output voltage. Reserved 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 DEC VGSN (V) 0 0 0010110 1 -0.025 0010111 2 -0.05 0011000 3 -0.075 0011001 4 -0.1 0011010 5 -0.125 0011011 6 -0.15 0011100 7 -0.175 0011101 8 -0.2 0011110 9 -0.225 0011111 10 -0.25 0100000 11 -0.275 0100001 12 -0.3 0100010 13 -0.325 0100011 14 -0.35 0100100 15 -0.375 0100101 16 -0.4 0100110 DEC VGSN (V) 22 -0.55 23 -0.575 24 -0.6 25 -0.625 26 -0.65 27 -0.675 28 -0.7 29 -0.725 30 -0.75 31 -0.775 32 -0.8 33 -0.825 34 -0.85 35 -0.875 36 -0.9 37 -0.925 38 -0.95 2012/05/11 300 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 0010001 0010010 0010011 0010100 0010101 Draft Version 17 -0.425 0100111 18 -0.45 0101000 19 -0.475 0101001 20 -0.5 ... 21 -0.525 1111111 NT35310 39 -0.975 40 -1 Reserved Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset C000h 44h 44h 44h Availability Yes Yes Yes Yes Yes C001h 44h 44h 44h C002h 10h 10h 10h C003h 10h 10h 10h 2012/05/11 301 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PWR_CTRL2 (C1h) Address (MDDI I/F) C100h ~ C101h Access Attribute Address (Other I/F) C1h Number of Parameter(s) Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] C100h Parameter 1 0 0 CP1_mode PUMP_MODE[1:0] 0 D[2] D[1] D[0] BTP1CKA_EXT[2:0] C101h Parameter 2 0 0 BTP1CKB_EXT[2:0] 0 BTP1CKC_EXT[2:0] R/W 2 Default Value 13h 33h CP1_Mode : This bit used to enable select BTP1CKA_EXT[2:0] and PUMP_MODE[1:0]. CP1_Mode Function Selection 0 Only support AVDDx2 pump &only fixed on one operating frequency. 1 Support all case of pump mode select & operating frequency select. Description PUMP_MODE[1:0]: AVDD pump mode selection. PUMP_MODE[1:0] 00 01 10 11 Mode Selection Reserved VCI x 2 VCI x 3 Reserved BTP1CKA_EXT[2:0]: Set the operating frequency of the step-up circuit 1 in full colors normal mode.(Normal mode on) BTP1CKA_EXT[2:0] Step-up cycle for step-up circuit 1 000 Reserved 001 DCCLK/4 010 DCCLK/8 011 DCCLK/16 100 DCCLK/32 101 DCCLK/64 110 DCCLK/128 111 Reserved BTP1CKB_EXT[2:0]: Set the operating frequency of the step-up circuit 1 in idle mode.(Idle mode on) BTP1CKB_EXT[2:0] Step-up cycle for step-up circuit 1 000 Reserved 001 DCCLK/4 010 DCCLK/8 011 DCCLK/16 100 DCCLK/32 101 DCCLK/64 110 DCCLK/128 111 Reserved BTP1CKC_EXT[2:0]: Set the operating frequency of the step-up circuit 1 in full colors partial mode.(Partial mode on / Idle mode off) BTP1CKC_EXT[2:0] Step-up cycle for step-up circuit 1 000 Reserved 001 DCCLK/4 010 DCCLK/8 011 DCCLK/16 100 DCCLK/32 101 DCCLK/64 110 DCCLK/128 111 Reserved Note: DCCLK is 8 times the unit frequency of one line. 2012/05/11 302 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Default Value Draft Version Status Power On Sequence S/W Reset H/W Reset C100h 13h 13h 13h NT35310 C101h 33h 33h 33h 2012/05/11 303 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. PWR_CTRL3 (C2h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] C200h Parameter 1 0 0 C201h Parameter 2 0 0 C202h Parameter 3 0 0 Draft Version NT35310 C200h ~ C202h C2h D[6] D[5] D[4] VGHLA[2:0] VGHLB[2:0] VGHLC[2:0] Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 VGHL_CLKA[2:0] 0 VGHL_CLKB[2:0] 0 VGHL_CLKC[2:0] R/W 3 Default Value 44h 44h 44h Description VGHA[2:0]: VGH charge pump circuit selection in full colors normal mode.(Normal mode on) VGHB[2:0]: VGH charge pump circuit selection in idle mode.(Idle mode on) VGHC[2:0]: VGH charge pump circuit selection in full colors partial mode.(Partial mode on / Idle mode off) VGHLA[2:0] / VGHLB [2:0] / VGHLC[2:0] Charge pump level for VGHLA/B/C VGH VGL 000 3xAVDD -3xAVDD 001 3xAVDD -2xAVDD 010 3xAVDD -2xAVDD 011 VCI+2xAVDD -VCI-2xAVDD 100 VCI+2xAVDD -2xAVDD 101 Reserved Reserved 110 2xAVDD -2xAVDD 111 Reserved Reserved VGHL_CLKA[2:0]: Set the operating frequency of the step-up circuit2 (VGH) in full colors normal mode.(Normal mode on) VGHL_CLKB[2:0]: Set the operating frequency of the step-up circuit2 (VGH) in idle mode.(Idle mode on) VGHL_CLKC[2:0]: Set the operating frequency of the step-up circuit2 (VGH) in full colors partial mode.(Partial mode on / Idle mode off) VGHL_CLKA[2:0] / VGHL_CLKB[2:0] / VGHL_CLKC[2:0] 000 001 010 011 100 101 110 111 Step-up cycle for VGHL step-up circuit DCCLK DCCLK/2 DCCLK/4 DCCLK/8 DCCLK/16 DCCLK/32 DCCLK/64 DCCLK/128 Default Value Status Power On Sequence S/W Reset H/W Reset C200h 44h 44h 44h C201h 44h 44h 44h C202h 44h 44h 44h 2012/05/11 304 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PWR_CTRL4 (C3h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] C300h Parameter 1 0 0 C300h ~ C301h Access Attribute R/W C3h Number of Parameter(s) 1 D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value 0 BTP5CKC_EXT[1:0] BTP5CKB_EXT[1:0] BTP5CKA_EXT[1:0] 2Ah Description BTP5CKA_EXT[1:0]: Set the operating frequency of the step-up circuit 5 in full colors normal mode.(Normal mode on) BTP5CKA_EXT[1:0] Step-up cycle for step-up circuit 5 00 Reserved 01 DCCLK/4 10 DCCLK/8 11 DCCLK/16 BTP5CKB_EXT[1:0]: Set the operating frequency of the step-up circuit 5 in idle mode.(Idle mode on) BTP5CKB_EXT[1:0] Step-up cycle for step-up circuit 5 00 Reserved 01 DCCLK/4 10 DCCLK/8 11 DCCLK/16 BTP5CKC_EXT[1:0]: Set the operating frequency of the step-up circuit 5 in full colors partial mode.(Partial mode on / Idle mode off) BTP5CKC_EXT[1:0] Step-up cycle for step-up circuit 5 00 Reserved 01 DCCLK/4 10 DCCLK/8 11 DCCLK/16 Default Value Status Power On Sequence S/W Reset H/W Reset C300h 2Ah 2Ah 2Ah 2012/05/11 305 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. PWR_ CTRL5 (C4h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] C400h Parameter 1 0 Draft Version NT35310 C400h C4h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VMDC[7:0] R/W 1 Default Value 40h Description VMDC[7:0]: set the VCOM voltage. VMDC[7:0] VCOMDC(V) VMDC[7:0] 00000000 0 01000101 69 00000001 1 01000110 70 : : 01000111 71 : : Reserved 01001000 72 : : 01001001 73 00001110 14 01001010 74 00001111 15 01001011 75 00010000 16 -0.2000 01001100 76 00010001 17 -0.2125 01001101 77 00010010 18 -0.2250 01001110 78 00010011 19 -0.2375 01001111 79 00010100 20 -0.2500 01010000 80 00010101 21 -0.2625 01010001 81 00010110 22 -0.2750 01010010 82 00010111 23 -0.2875 01010011 83 00011000 24 -0.3000 01010100 84 00011001 25 -0.3125 01010101 85 00011010 26 -0.3250 01010110 86 00011011 27 -0.3375 01010111 87 00011100 28 -0.3500 01011000 88 00011101 29 -0.3625 01011001 89 00011110 30 -0.3750 01011010 90 00011111 31 -0.3875 01011011 91 00100000 32 -0.4000 01011100 92 00100001 33 -0.4125 01011101 93 00100010 34 -0.4250 01011110 94 00100011 35 -0.4375 01011111 95 00100100 36 -0.4500 01100000 96 00100101 37 -0.4625 01100001 97 00100110 38 -0.4750 01100010 98 00100111 39 -0.4875 01100011 99 00101000 40 -0.5000 01100100 100 00101001 41 -0.5125 01100101 101 00101010 42 -0.5250 01100110 102 00101011 43 -0.5375 01100111 103 00101100 44 -0.5500 01101000 104 00101101 45 -0.5625 01101001 105 00101110 46 -0.5750 01101010 106 00101111 47 -0.5875 01101011 107 00110000 48 -0.6000 01101100 108 00110001 49 -0.6125 01101101 109 00110010 50 -0.6250 01101110 110 00110011 51 -0.6375 01101111 111 00110100 52 -0.6500 01110000 112 00110101 53 -0.6625 01110001 113 00110110 54 -0.6750 01110010 114 00110111 55 -0.6875 01110011 115 00111000 56 -0.7000 01110100 116 00111001 57 -0.7125 01110101 117 00111010 58 -0.7250 01110110 118 00111011 59 -0.7375 01110111 119 00111100 60 -0.7500 01111000 120 00111101 61 -0.7625 01111001 121 00111110 62 -0.7750 01111010 122 00111111 63 -0.7875 01111011 123 01000000 64 -0.8000 01111100 124 01000001 65 -0.8125 01111101 125 01000010 66 -0.8250 01111110 126 01000011 67 -0.8375 01111111 127 01000100 68 -0.8500 10000000 128 VCOMDC(V) -0.8625 -0.8750 -0.8875 -0.9000 -0.9125 -0.9250 -0.9375 -0.9500 -0.9625 -0.9750 -0.9875 -1.0000 -1.0125 -1.0250 -1.0375 -1.0500 -1.0625 -1.0750 -1.0875 -1.1000 -1.1125 -1.1250 -1.1375 -1.1500 -1.1625 -1.1750 -1.1875 -1.2000 -1.2125 -1.2250 -1.2375 -1.2500 -1.2625 -1.2750 -1.2875 -1.3000 -1.3125 -1.3250 -1.3375 -1.3500 -1.3625 -1.3750 -1.3875 -1.4000 -1.4125 -1.4250 -1.4375 -1.4500 -1.4625 -1.4750 -1.4875 -1.5000 -1.5125 -1.5250 -1.5375 -1.5500 -1.5625 -1.5750 -1.5875 -1.6000 VMDC[7:0] 10000001 129 10000010 130 10000011 131 10000100 132 10000101 133 10000110 134 10000111 135 10001000 136 10001001 137 10001010 138 10001011 139 10001100 140 10001101 141 10001110 142 10001111 143 10010000 144 10010001 145 10010010 146 10010011 147 10010100 148 10010101 149 10010110 150 10010111 151 10011000 152 10011001 153 10011010 154 10011011 155 10011100 156 10011101 157 10011110 158 10011111 159 10100000 160 10100001 161 10100010 162 10100011 163 10100100 164 10100101 165 10100110 166 10100111 167 10101000 168 10101001 169 10101010 170 10101011 171 10101100 172 10101101 173 10101110 174 10101111 175 10110000 176 10110001 177 10110010 178 10110011 179 10110100 180 10110101 181 10110110 182 10110111 183 10111000 184 10111001 185 10111010 186 10111011 187 10111100 188 VCOMDC(V) -1.6125 -1.6250 -1.6375 -1.6500 -1.6625 -1.6750 -1.6875 -1.7000 -1.7125 -1.7250 -1.7375 -1.7500 -1.7625 -1.7750 -1.7875 -1.8000 -1.8125 -1.8250 -1.8375 -1.8500 -1.8625 -1.8750 -1.8875 -1.9000 -1.9125 -1.9250 -1.9375 -1.9500 -1.9625 -1.9750 -1.9875 -2.0000 -2.0125 -2.0250 -2.0375 -2.0500 -2.0625 -2.0750 -2.0875 -2.1000 -2.1125 -2.1250 -2.1375 -2.1500 -2.1625 -2.1750 -2.1875 -2.2000 -2.2125 -2.2250 -2.2375 -2.2500 -2.2625 -2.2750 -2.2875 -2.3000 -2.3125 -2.3250 -2.3375 -2.3500 VMDC[7:0] 10111101 189 10111110 190 10111111 191 11000000 192 11000001 193 11000010 194 11000011 195 11000100 196 11000101 197 11000110 198 11000111 199 11001000 200 11001001 201 11001010 202 11001011 203 11001100 204 11001101 205 11001110 206 11001111 207 11010000 208 11010001 209 11010010 210 11010011 211 11010100 212 11010101 213 11010110 214 11010111 215 11011000 216 11011001 217 11011010 218 11011011 219 11011100 220 11011101 221 11011110 222 11011111 223 11100000 224 11100001 225 11100010 226 11100011 227 11100100 228 11100101 229 11100110 230 11100111 231 11101000 232 11101001 233 11101010 234 11101011 235 11101100 236 11101101 237 11101110 238 11101111 239 11110000 240 11110001 241 11110010 242 : : : : : : : : 11111110 254 11111111 255 VCOMDC(V) -2.3625 -2.3750 -2.3875 -2.4000 -2.4125 -2.4250 -2.4375 -2.4500 -2.4625 -2.4750 -2.4875 -2.5000 -2.5125 -2.5250 -2.5375 -2.5500 -2.5625 -2.5750 -2.5875 -2.6000 -2.6125 -2.6250 -2.6375 -2.6500 -2.6625 -2.6750 -2.6875 -2.7000 -2.7125 -2.7250 -2.7375 -2.7500 -2.7625 -2.7750 -2.7875 -2.8000 -2.8125 -2.8250 -2.8375 -2.8500 -2.8625 -2.8750 -2.8875 -2.9000 -2.9125 -2.9250 -2.9375 -2.9500 -2.9625 -2.9750 -2.9875 -3.0000 Reserved 2012/05/11 306 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Default Value Draft Version Status Power On Sequence S/W Reset H/W Reset C400h 40h 40h 40h NT35310 2012/05/11 307 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PWR_ CTRL6 (C5h) Address (MDDI I/F) C500h ~ C504h Access Attribute Address (Other I/F) C5h Number of Parameter(s) Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] C500h Parameter 1 0 0 C501h Parameter 2 0 0 C502h Parameter 3 0 0 C503h Parameter 4 0 0 D[6] D[5] D[4] D[3] D[2] ISOPP[2:0] SAPPA[2:0] SAPPB[2:0] SAPPC[2:0] BIAS_REDUCE 0 0 0 D[1] D[0] ISOPN[2:0] SAPNA[2:0] SAPNB[2:0] SAPNC[2:0] R/W 4 Default Value 4Ch 44h 44h 44h Description ISOPP[2:0]: Positive Source OP output stage current control ISOPN[2:0]: Negative Source OP output stage current control SAPPA[2:0]: Positive Source OP current control in full colors normal mode.(Normal mode on) SAPPB[2:0]: Positive Source OP current control in idle mode.(Idle mode on) SAPPC[2:0]: Positive Source OP current control in full colors partial mode.(Partial mode on / Idle mode off) SAPPA [2:0] / SAPPB [2:0] / SAPPC [2:0] 000 Amount of Positive Source OP Current Slight 001 Very Small 010 Small 011 Medium Low 100 Medium (Default) 101 Medium High 110 Large 111 Very Large SAPNA[2:0]: Negative Source OP current control in full colors normal mode.(Normal mode on) SAPNB[2:0]: Negative Source OP current control in idle mode.(Idle mode on) SAPNC[2:0]: Negative Source OP current control in full colors partial mode.(Partial mode on / Idle mode off) SAPNA [2:0] / SAPNB [2:0] / SAPNC [2:0] Amount of Negative Source OP Current 000 Slight 001 Very Small 010 Small 011 Medium Low 100 Medium (Default) 101 Medium High 110 Large 111 Very Large 2012/05/11 308 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Default Value Draft Version Parameter1 ~ Parameter4: Status Power On Sequence S/W Reset H/W Reset NT35310 Default Value 44h 44h 44h 2012/05/11 309 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PWR_ CTRL7 (C6h) Address (MDDI I/F) C600h ~ C603h Address (Other I/F) C6h Address Parameter D[17:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] C600h Parameter 1 0 0 0 0 0 0 C601h Parameter 2 0 VGL_CLAMPA[2:0] C602h Parameter 3 0 VGL_CLAMPB[2:0] C603h Parameter 4 0 VGL_CLAMPC[2:0] Access Attribute R/W Number of Parameter(s) 4 D[2] D[1] D[0] Default Value 0 VGHCL_OFF VGLCL_OFF 00h VGH_CLAMPA[2:0] E2h VGH_CLAMPB[2:0] E2h VGH_CLAMPC[2:0] E2h Description VGLA[2:0]: VGL clamp voltage selection in full colors normal mode.(Normal mode on) VGLB[2:0]: VGL clamp voltage selection in idle mode.(Idle mode on) VGLC[2:0]: VGL clamp voltage selection in full colors partial mode.(Partial mode on / Idle mode off) VGL_CLAMPA[3:0] / VGL_CLAMPB[3:0] / VGL_CLAMPC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VGL Clamp Voltage -17V -16.5V -16V -15.5V -15V -14.5V -14V -13.5V -13V -12.5V -12V -11.5V -11V -10.5V -10V -9.5V VGHA[2:0]: VGH clamp voltage selection in full colors normal mode.(Normal mode on) VGHB[2:0]: VGH clamp voltage selection in idle mode.(Idle mode on) VGHC[2:0]: VGH clamp voltage selection in full colors partial mode.(Partial mode on / Idle mode off) VGH_CLAMPA[3:0] / VGH_CLAMPB[3:0] / VGH_CLAMPC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VGH Clamp Voltage 17V 16.5V 16V 15.5V 15V 14.5V 14V 13.5V 13V 12.5V 12V Reserved Reserved Reserved Reserved Reserved 2012/05/11 310 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version VGHCL_OFF/VGLCL_OFF:To enable or disable the VGH and VGL VGHCL_OFF/VGLCL_OFF 0 1 NT35310 VGH Clamp Voltage CLAMP ON CLAMP OFF Default Value Status Power On Sequence S/W Reset H/W Reset C600h 00h 00h 00h C601h E2h E2h E2h C602h E2h E2h E2h C603h E2h E2h E2h 2012/05/11 311 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. WID_CTRL1 (D1h): WID1 Draft Version NT35310 Address (MDDI I/F) D100h Access Attribute Address (Other I/F) D1h Number of Parameter(s) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D100h Parameter 1 0 D[7] WID1[7] D[6] WID1[6] D[5] WID1[5] D[4] WID1[4] D[3] WID1[3] D[2] WID1[2] D[1] WID1[1] D[0] WID1[0] W 1 Default Value - Description Write 8-bit project ID to save it to NV memory. WID1[7:0]: LCD module’s manufacturer ID. (specified by handset company). Restriction Write only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset D100h - 2012/05/11 312 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WID_CTRL2 (D2h): WID2 Address (MddI I/F) D200h Access Attribute W Address (Other I/F) D2h Number of Parameter(s) 1 Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value D200h Parameter 1 0 1 WID2[6] WID2[5] WID2[4] WID2[3] WID2[2] WID2[1] WID2[0] - Description Write 7-bit LCD module/driver version ID to save it to NV memory. WID2[6:0]: LCD module/driver version ID(specified by module supplier). Restriction Write only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset D200h - 2012/05/11 313 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 WID_CTRL3 (D3h): WID3 Address (MDDI I/F) D300h Access Attribute Address (Other I/F) D3h Number of Parameter(s) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D300h Parameter 1 0 D[7] WID3[7] D[6] WID3[6] D[5] WID3[5] D[4] WID3[4] D[3] WID3[3] D[2] WID3[2] D[1] WID3[1] D[0] WID3[0] W 1 Default Value - Description Write 8-bit project ID to save it to NV memory. WID3[7:0]: project ID (specified by handset company). Restriction Write only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset D300h - 2012/05/11 314 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. READID4 (D4h): Read ID4 Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D400h Parameter 1 0 0 D401h Parameter 2 0 0 D402h Parameter 3 0 0 D403h Parameter 4 0 0 Draft Version NT35310 D400h ~ D403h D4h D[6] D[5] D[4] 0 0 0 1 0 1 0 0 1 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 0 0 0 1 0 0 1 1 0 0 0 1 ID43[3:0] R 4 Default Value 01h 53h 10h 01h Description 1st parameter: Vender ID code. “01” means Novatek. 2nd and 3rd parameter: Chip ID code. “5310” means NT35310. 4th parameter: ID43-ID40: Chip version code. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset D400h 01h 01h 01h D401h 53h 53h 53h D402h 11h 11h 11h D403h - 2012/05/11 315 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. DDB_CTRL (D5h):Write DDB Info Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D500h Parameter 1 00h D501h Parameter 2 00h D502h Parameter 3 00h D503h Parameter 4 00h Draft Version NT35310 D500h ~ D505h D5h D[6] D[5] Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] SID [7:0] SID[15:8] MRID[7:0] MRID[15:8] R/W 4 Default Value 00h 00h 00h 00h Description Restriction This command is use to store supplier identification and display module model / revision information for MTP programming. Notes: Parameter 1:SID[7:0] ~ LS byte of Supplier ID Parameter 2:SID[15:8] ~ MS byte of Supplier ID Parameter 3:MRID[7:0] ~ LS byte of Supplier Elective Data Parameter 4:MRID[15:8] ~ MS byte of Supplier Elective Data such as model number - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset D500h 00h 00h 00h Default Value D501h D502h 00h 00h 00h 00h 00h 00h D503h 00h 00h 00h 2012/05/11 316 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDVNT (DDh): Read NV Memory Flag Status Address (MDDI I/F) DD00h Access Attribute Address (Other I/F) DDh Number of Parameter(s) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] D[2] DD00h Parameter 1 0 NV_N3 NV_N2 NV_N1 NV_N0 NV_GMA 0 D[1] NVP_F D[0] NV_P R 1 Default Value - Description NV_P: - Both commands indicate the current status of the NV memory as shown below: Flag Description Value NV_P NV Memory Program Finish Status ‘0’ = NV Memory Program Unready, ‘1’ = NV Memory Program Finish, NVP_F: NV Memory Power Flag Status ‘0’ = NV Memory External Power unready. ‘1’ = NV Memory External Power ready. NV_GMA : To detect GAMMA be program or not. If NV_GMA=1,GAMMA was program already. If NV_GMA=0,GAMMA Program Unready. NV_N[3 : 0]: - The NV_N represent the Record NV Memory Program Times NV_N3 0 0 0 0 1 NV_N2 0 0 0 1 1 NV_N1 0 0 1 1 1 NV_N0 0 1 1 1 1 NV Memory Program Times 0 time (Default) 1 time 2 times 3 times 4 times Restriction Read only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset DD00h - 2012/05/11 317 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 EPWRITE (DEh): NV Memory Write Command Address (MDDI I/F) DE00h Access Attribute W Address (Other I/F) DEh Number of Parameter(s) 3 Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value DE00h Parameter 1 0 0 1 0 1 0 1 0 1 55h DE01h Parameter 2 0 1 0 1 0 1 0 1 0 AAh DE02h Parameter 3 0 0 1 1 0 0 1 1 0 66h Description EPWRITE1-2-3: - These are NV memory write command. - The NV memory writing sequence: (1) For MDDI: (DE00h=0X0055)(DE01h=0X00AA)(DE02h=0X0066) (2) For other interface: DEh 0X55  0XAA  0X66 Restriction Write only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset DE00h - DE01h - DE02h - 2012/05/11 318 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 MTPPWR (DFh): MTP Write function enable Address (MIPI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] DF00h Parameter 1 0 0 DF00h DFh D[6] D[5] D[4] D[3] 0 0 nROM 0 Access Attribute Number of Parameter(s) D[2] D[1] 0 0 R/W 1 D[0] Default Value MTP_W 00h MTP_W: This instruction is used to enable the MTP write function. MTP_W MTP Write Function 0 Disable 1 Enable Description nROM: The nROM is used to set MTP reload or not after SLPOUT. nROM MTP Source 0 Reload MTP after SLPOUT (Default) 1 Don’t Reload MTP after SLPOUT Restriction Write only Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Value Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes DF00h 00h 00h 00h 2012/05/11 319 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDREGEXT1 (EBh):Register read command in SPI interface Address (MDDI I/F) Address (Other I/F) Parameter (SPI I/F) Parameter 1 D[7] Add7 Not Support EBh D[6] D[5] Add6 Add5 D[4] Add4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] Add3 Add2 Add1 Add0 R/W 1 Default Value - Register read command in SPI interface Description Restriction Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value D[15:0] 0000h 0000h 0000h 2012/05/11 320 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 RDREGEXT2 (ECh):Register read command in SPI interface Address (MDDI I/F) Address (Other I/F) Parameter (SPI I/F) Parameter 1 Not Support ECh D[7] D[6] D[5] D[4] Para17 Para16 Para15 Para14 Parameter 2 Para27 Para26 Para25 Para24 : : : : : Parameter N ParaN7 ParaN6 ParaN5 ParaN4 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] Para13 Para23 : ParaN3 Para12 Para22 : ParaN2 Para11 Para21 : ParaN1 Para10 Para20 : ParaN0 R N Default Value - - - - Register read command in SPI interface Description Restriction Register Availability Default Value Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value D[15:0] 0000h 0000h 0000h 2012/05/11 321 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PAGE_LOCK (EFh):Set the Register to command1 Address (MDDI I/F) EF00h Access Attribute W Address (Other I/F) EFh Number of Parameter(s) 1 Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default Value EF00h Parameter 1 0 1 0 1 0 1 0 1 0 AAh Description This command is used for LOCK of CMD2 register access. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value D[15:0] - 2012/05/11 322 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PAGE_LOCK (BFh):Set the Register to command2 Page 1 Address (MDDI I/F) BF00h Address (Other I/F) BFh Address Parameter D[15:8] D[7] D[6] D[5] D[4] (MDDI I/F) (Other I/F) BF00h Parameter 1 0 1 0 1 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 1 0 1 0 W 1 Default Value AAh Description This command is used for goto CMD2_P1 register access. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value D[15:0] - 2012/05/11 323 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 6.3 CMD2_P1 register list Inst / Para Addr. R/W Parameter D7 D6 D5 D4 D3 D2 D1 D0 Code MTP R/W 1 VP0[7] VP0[6] VP0[5] VP0[4] VP0[3] VP0[2] VP0[1] VP0[0] 01h 2 0 0 0 0 0 0 0 0 R/W 3 VP1[7] VP1[6] VP1[5] VP1[4] VP1[3] VP1[2] VP1[1] VP1[0] 19h 4 0 0 0 0 0 0 0 0 R/W 5 VP2[7] VP2[6] VP2[5] VP2[4] VP2[3] VP2[2] VP2[1] VP2[0] 25h 6 0 0 0 0 0 0 0 0 R/W 7 VP4[7] VP4[6] VP4[5] VP4[4] VP4[3] VP4[2] VP4[1] VP4[0] 3Eh 8 0 0 0 0 0 0 0 0 R/W 9 VP6[7] VP6[6] VP6[5] VP6[4] VP6[3] VP6[2] VP6[1] VP6[0] 4Ah 10 0 0 0 0 0 0 0 0 R/W 11 VP8[7] VP8[6] VP8[5] VP8[4] VP8[3] VP8[2] VP8[1] VP8[0] 55h 12 0 0 0 0 0 0 0 0 R/W 13 VP12[7] VP12[6] VP12[5] VP12[4] VP12[3] VP12[2] VP12[1] VP12[0] 66h 14 0 0 0 0 0 0 0 0 R/W 15 VP20[7] VP20[6] VP20[5] VP20[4] VP20[3] VP20[2] VP20[1] VP20[0] 7Ch 16 0 0 0 0 0 0 0 0 R/W 17 VP28[7] VP28[6] VP28[5] VP28[4] VP28[3] VP28[2] VP28[1] VP28[0] 8Dh GMACTRL1 18 0 0 0 0 0 0 0 0 (Must set reg E0h V APR2_EN = 1) R/W 19 VP36 [7] VP36 [6] VP36 [5] VP36 [4] VP36 [3] VP36 [2] VP36 [1] VP36 [0] 9Eh 20 0 0 0 0 0 0 0 0 R/W 21 VP44[7] VP44[6] VP44[5] VP44[4] VP44[3] VP44[2] VP44[1] VP44[0] ACh 22 0 0 0 0 0 0 0 0 R/W 23 VP52[7] VP52[6] VP52[5] VP52[4] VP52[3] VP52[2] VP52[1] VP52[0] BFh 24 0 0 0 0 0 0 0 0 R/W 25 VP56[7] VP56[6] VP56[5] VP56[4] VP56[3] VP56[2] VP56[1] VP56[0] CAh 26 0 0 0 0 0 0 0 0 R/W 27 VP58[7] VP58[6] VP58[5] VP58[4] VP58[3] VP58[2] VP58[1] VP58[0] D3h 28 0 0 0 0 0 0 0 0 R/W 29 VP60[7] VP60[6] VP60[5] VP60[4] VP60[3] VP60[2] VP60[1] VP60[0] DDh 30 0 0 0 0 0 0 0 0 R/W 31 VP61[7] VP61[6] VP61[5] VP61[4] VP61[3] VP61[2] VP61[1] VP61[0] E2h 32 0 0 0 0 0 0 0 0 R/W 33 VP62[7] VP62[6] VP62[5] VP62[4] VP62[3] VP62[2] VP62[1] VP62[0] E9h 34 0 0 0 0 0 0 0 0 R/W 35 VP63[7] VP63[6] VP63[5] VP63[4] VP63[3] VP63[2] VP63[1] VP63[0] F3h 36 0 0 0 0 0 0 0 0 GMACTRL2 E1h R/W 1 VN0[7] VN0[6] VN0[5] VN0[4] VN0[3] VN0[2] VN0[1] VN0[0] 00h V (Must set reg APR2_EN = 1) 2 0 0 0 0 0 0 0 0 R/W 3 VN1[7] VN1[6] VN1[5] VN1[4] VN1[3] VN1[2] VN1[1] VN1[0] 19h 4 0 0 0 0 0 0 0 0 R/W 5 VN2[7] VN2[6] VN2[5] VN2[4] VN2[3] VN2[2] VN2[1] VN2[0] 25h 2012/05/11 6 0 0 0 0 0 0 0 0 R/W 7 VN4[7] VN4[6] VN4[5] VN4[4] VN4[3] VN4[2] VN4[1] VN4[0] 3Eh 8 0 0 0 0 0 0 0 0 324 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 R/W 9 VN6[7] VN6[6] VN6[5] VN6[4] VN6[3] VN6[2] VN6[1] VN6[0] 4Ah 10 0 0 0 0 0 0 0 0 R/W 11 VN8[7] VN8[6] VN8[5] VN8[4] VN8[3] VN8[2] VN8[1] VN8[0] 55h 12 0 0 0 0 0 0 0 0 R/W 13 VN12[7] VN12[6] VN12[5] VN12[4] VN12[3] VN12[2] VN12[1] VN12[0] 66h 14 0 0 0 0 0 0 0 0 R/W 15 VN20[7] VN20[6] VN20[5] VN20[4] VN20[3] VN20[2] VN20[1] VN20[0] 7Ch 16 0 0 0 0 0 0 0 0 R/W 17 VN28[7] VN28[6] VN28[5] VN28[4] VN28[3] VN28[2] VN28[1] VN28[0] 8Dh 18 0 0 0 0 0 0 0 0 R/W 19 VN36 [7] VN36 [6] VN36 [5] VN36 [4] VN36 [3] VN36 [2] VN36 [1] VN36 [0] 9Eh 20 0 0 0 0 0 0 0 0 R/W 21 VN44[7] VN44[6] VN44[5] VN44[4] VN44[3] VN44[2] VN44[1] VN44[0] ACh 22 0 0 0 0 0 0 0 0 R/W 23 VN52[7] VN52[6] VN52[5] VN52[4] VN52[3] VN52[2] VN52[1] VN52[0] BFh 24 0 0 0 0 0 0 0 0 R/W 25 VN56[7] VN56[6] VN56[5] VN56[4] VN56[3] VN56[2] VN56[1] VN56[0] CAh 26 0 0 0 0 0 0 0 0 R/W 27 VN58[7] VN58[6] VN58[5] VN58[4] VN58[3] VN58[2] VN58[1] VN58[0] D3h 28 0 0 0 0 0 0 0 0 R/W 29 VN60[7] VN60[6] VN60[5] VN60[4] VN60[3] VN60[2] VN60[1] VN60[0] DDh 30 0 0 0 0 0 0 0 0 R/W 31 VN61[7] VN61[6] VN61[5] VN61[4] VN61[3] VN61[2] VN61[1] VN61[0] E2h 32 0 0 0 0 0 0 0 0 R/W 33 VN62[7] VN62[6] VN62[5] VN62[4] VN62[3] VN62[2] VN62[1] VN62[0] E9h 34 0 0 0 0 0 0 0 0 R/W 35 VN63[7] VN63[6] VN63[5] VN63[4] VN63[3] VN63[2] VN63[1] VN63[0] F3h 36 0 0 0 0 0 0 0 0 GMACTRL3 E2h R/W 1 VP0[7] VP0[6] VP0[5] VP0[4] VP0[3] VP0[2] VP0[1] VP0[0] 01h V (Must set reg APR2_EN = 1) 2 0 0 0 0 0 0 0 0 R/W 3 VP1[7] VP1[6] VP1[5] VP1[4] VP1[3] VP1[2] VP1[1] VP1[0] 19h 4 0 0 0 0 0 0 0 0 R/W 5 VP2[7] VP2[6] VP2[5] VP2[4] VP2[3] VP2[2] VP2[1] VP2[0] 25h 6 0 0 0 0 0 0 0 0 R/W 7 VP4[7] VP4[6] VP4[5] VP4[4] VP4[3] VP4[2] VP4[1] VP4[0] 3Eh 8 0 0 0 0 0 0 0 0 R/W 9 VP6[7] VP6[6] VP6[5] VP6[4] VP6[3] VP6[2] VP6[1] VP6[0] 4Ah 10 0 0 0 0 0 0 0 0 R/W 11 VP8[7] VP8[6] VP8[5] VP8[4] VP8[3] VP8[2] VP8[1] VP8[0] 55h 12 0 0 0 0 0 0 0 0 R/W 13 VP12[7] VP12[6] VP12[5] VP12[4] VP12[3] VP12[2] VP12[1] VP12[0] 66h 14 0 0 0 0 0 0 0 0 R/W 15 VP20[7] VP20[6] VP20[5] VP20[4] VP20[3] VP20[2] VP20[1] VP20[0] 7Ch 16 0 0 0 0 0 0 0 0 R/W 17 VP28[7] VP28[6] VP28[5] VP28[4] VP28[3] VP28[2] VP28[1] VP28[0] 8Dh 18 0 0 0 0 0 0 0 0 2012/05/11 325 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 R/W 19 VP36 [7] VP36 [6] VP36 [5] VP36 [4] VP36 [3] VP36 [2] VP36 [1] VP36 [0] 9Eh 20 0 0 0 0 0 0 0 0 R/W 21 VP44[7] VP44[6] VP44[5] VP44[4] VP44[3] VP44[2] VP44[1] VP44[0] ACh 22 0 0 0 0 0 0 0 0 R/W 23 VP52[7] VP52[6] VP52[5] VP52[4] VP52[3] VP52[2] VP52[1] VP52[0] BFh 24 0 0 0 0 0 0 0 0 R/W 25 VP56[7] VP56[6] VP56[5] VP56[4] VP56[3] VP56[2] VP56[1] VP56[0] CAh 26 0 0 0 0 0 0 0 0 R/W 27 VP58[7] VP58[6] VP58[5] VP58[4] VP58[3] VP58[2] VP58[1] VP58[0] D3h 28 0 0 0 0 0 0 0 0 R/W 29 VP60[7] VP60[6] VP60[5] VP60[4] VP60[3] VP60[2] VP60[1] VP60[0] DDh 30 0 0 0 0 0 0 0 0 R/W 31 VP61[7] VP61[6] VP61[5] VP61[4] VP61[3] VP61[2] VP61[1] VP61[0] E2h 32 0 0 0 0 0 0 0 0 R/W 33 VP62[7] VP62[6] VP62[5] VP62[4] VP62[3] VP62[2] VP62[1] VP62[0] E9h 34 0 0 0 0 0 0 0 0 R/W 35 VP63[7] VP63[6] VP63[5] VP63[4] VP63[3] VP63[2] VP63[1] VP63[0] F3h 36 0 0 0 0 0 0 0 0 GMACTRL4 E3h R/W 1 VN0[7] VN0[6] VN0[5] VN0[4] VN0[3] VN0[2] VN0[1] VN0[0] 00h V (Must set reg APR2_EN = 1) 2 0 0 0 0 0 0 0 0 R/W 3 VN1[7] VN1[6] VN1[5] VN1[4] VN1[3] VN1[2] VN1[1] VN1[0] 19h 4 0 0 0 0 0 0 0 0 R/W 5 VN2[7] VN2[6] VN2[5] VN2[4] VN2[3] VN2[2] VN2[1] VN2[0] 25h 6 0 0 0 0 0 0 0 0 R/W 7 VN4[7] VN4[6] VN4[5] VN4[4] VN4[3] VN4[2] VN4[1] VN4[0] 3Eh 8 0 0 0 0 0 0 0 0 R/W 9 VN6[7] VN6[6] VN6[5] VN6[4] VN6[3] VN6[2] VN6[1] VN6[0] 4Ah 10 0 0 0 0 0 0 0 0 R/W 11 VN8[7] VN8[6] VN8[5] VN8[4] VN8[3] VN8[2] VN8[1] VN8[0] 55h 12 0 0 0 0 0 0 0 0 R/W 13 VN12[7] VN12[6] VN12[5] VN12[4] VN12[3] VN12[2] VN12[1] VN12[0] 66h 14 0 0 0 0 0 0 0 0 R/W 15 VN20[7] VN20[6] VN20[5] VN20[4] VN20[3] VN20[2] VN20[1] VN20[0] 7Ch 16 0 0 0 0 0 0 0 0 R/W 17 VN28[7] VN28[6] VN28[5] VN28[4] VN28[3] VN28[2] VN28[1] VN28[0] 8Dh 18 0 0 0 0 0 0 0 0 R/W 19 VN36 [7] VN36 [6] VN36 [5] VN36 [4] VN36 [3] VN36 [2] VN36 [1] VN36 [0] 9Eh 20 0 0 0 0 0 0 0 0 R/W 21 VN44[7] VN44[6] VN44[5] VN44[4] VN44[3] VN44[2] VN44[1] VN44[0] ACh 22 0 0 0 0 0 0 0 0 R/W 23 VN52[7] VN52[6] VN52[5] VN52[4] VN52[3] VN52[2] VN52[1] VN52[0] BFh 24 0 0 0 0 0 0 0 0 R/W 25 VN56[7] VN56[6] VN56[5] VN56[4] VN56[3] VN56[2] VN56[1] VN56[0] CAh 26 0 0 0 0 0 0 0 0 R/W 27 VN58[7] VN58[6] VN58[5] VN58[4] VN58[3] VN58[2] VN58[1] VN58[0] D3h 28 0 0 0 0 0 0 0 0 2012/05/11 326 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 R/W 29 VN60[7] VN60[6] VN60[5] VN60[4] VN60[3] VN60[2] VN60[1] VN60[0] DDh 30 0 0 0 0 0 0 0 0 R/W 31 VN61[7] VN61[6] VN61[5] VN61[4] VN61[3] VN61[2] VN61[1] VN61[0] E2h 32 0 0 0 0 0 0 0 0 R/W 33 VN62[7] VN62[6] VN62[5] VN62[4] VN62[3] VN62[2] VN62[1] VN62[0] E9h 34 0 0 0 0 0 0 0 0 R/W 35 VN63[7] VN63[6] VN63[5] VN63[4] VN63[3] VN63[2] VN63[1] VN63[0] F3h 36 0 0 0 0 0 0 0 0 R/W 1 VP0[7] VP0[6] VP0[5] VP0[4] VP0[3] VP0[2] VP0[1] VP0[0] 01h 2 0 0 0 0 0 0 0 0 R/W 3 VP1[7] VP1[6] VP1[5] VP1[4] VP1[3] VP1[2] VP1[1] VP1[0] 19h 4 0 0 0 0 0 0 0 0 R/W 5 VP2[7] VP2[6] VP2[5] VP2[4] VP2[3] VP2[2] VP2[1] VP2[0] 25h 6 0 0 0 0 0 0 0 0 R/W 7 VP4[7] VP4[6] VP4[5] VP4[4] VP4[3] VP4[2] VP4[1] VP4[0] 3Eh 8 0 0 0 0 0 0 0 0 R/W 9 VP6[7] VP6[6] VP6[5] VP6[4] VP6[3] VP6[2] VP6[1] VP6[0] 4Ah 10 0 0 0 0 0 0 0 0 R/W 11 VP8[7] VP8[6] VP8[5] VP8[4] VP8[3] VP8[2] VP8[1] VP8[0] 55h 12 0 0 0 0 0 0 0 0 R/W 13 VP12[7] VP12[6] VP12[5] VP12[4] VP12[3] VP12[2] VP12[1] VP12[0] 66h 14 0 0 0 0 0 0 0 0 R/W 15 VP20[7] VP20[6] VP20[5] VP20[4] VP20[3] VP20[2] VP20[1] VP20[0] 7Ch 16 0 0 0 0 0 0 0 0 R/W 17 VP28[7] VP28[6] VP28[5] VP28[4] VP28[3] VP28[2] VP28[1] VP28[0] 8Dh GMACTRL5 18 0 0 0 0 0 0 0 0 V (Must set reg E4h APR2_EN = 1) R/W 19 VP36 [7] VP36 [6] VP36 [5] VP36 [4] VP36 [3] VP36 [2] VP36 [1] VP36 [0] 9Eh 20 0 0 0 0 0 0 0 0 R/W 21 VP44[7] VP44[6] VP44[5] VP44[4] VP44[3] VP44[2] VP44[1] VP44[0] ACh 22 0 0 0 0 0 0 0 0 R/W 23 VP52[7] VP52[6] VP52[5] VP52[4] VP52[3] VP52[2] VP52[1] VP52[0] BFh 24 0 0 0 0 0 0 0 0 R/W 25 VP56[7] VP56[6] VP56[5] VP56[4] VP56[3] VP56[2] VP56[1] VP56[0] CAh 26 0 0 0 0 0 0 0 0 R/W 27 VP58[7] VP58[6] VP58[5] VP58[4] VP58[3] VP58[2] VP58[1] VP58[0] D3h 28 0 0 0 0 0 0 0 0 R/W 29 VP60[7] VP60[6] VP60[5] VP60[4] VP60[3] VP60[2] VP60[1] VP60[0] DDh 30 0 0 0 0 0 0 0 0 R/W 31 VP61[7] VP61[6] VP61[5] VP61[4] VP61[3] VP61[2] VP61[1] VP61[0] E2h 32 0 0 0 0 0 0 0 0 R/W 33 VP62[7] VP62[6] VP62[5] VP62[4] VP62[3] VP62[2] VP62[1] VP62[0] E9h 34 0 0 0 0 0 0 0 0 R/W 35 VP63[7] VP63[6] VP63[5] VP63[4] VP63[3] VP63[2] VP63[1] VP63[0] F3h 36 0 0 0 0 0 0 0 0 GMACTRL6 E5h R/W 1 VN0[7] VN0[6] VN0[5] VN0[4] VN0[3] VN0[2] VN0[1] VN0[0] 00h V (Must set reg APR2_EN = 1) 2 0 0 0 0 0 0 0 0 2012/05/11 327 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CABC Gamma E6h R/W offset (R+/R-) (Must set reg APR2_EN = 1) R/W R/W R/W R/W R/W Draft Version NT35310 3 VN1[7] VN1[6] VN1[5] VN1[4] VN1[3] VN1[2] VN1[1] VN1[0] 19h 4 0 0 0 0 0 0 0 0 5 VN2[7] VN2[6] VN2[5] VN2[4] VN2[3] VN2[2] VN2[1] VN2[0] 25h 6 0 0 0 0 0 0 0 0 7 VN4[7] VN4[6] VN4[5] VN4[4] VN4[3] VN4[2] VN4[1] VN4[0] 3Eh 8 0 0 0 0 0 0 0 0 9 VN6[7] VN6[6] VN6[5] VN6[4] VN6[3] VN6[2] VN6[1] VN6[0] 4Ah 10 0 0 0 0 0 0 0 0 11 VN8[7] VN8[6] VN8[5] VN8[4] VN8[3] VN8[2] VN8[1] VN8[0] 55h 12 0 0 0 0 0 0 0 0 13 VN12[7] VN12[6] VN12[5] VN12[4] VN12[3] VN12[2] VN12[1] VN12[0] 66h 14 0 0 0 0 0 0 0 0 15 VN20[7] VN20[6] VN20[5] VN20[4] VN20[3] VN20[2] VN20[1] VN20[0] 7Ch 16 0 0 0 0 0 0 0 0 17 VN28[7] VN28[6] VN28[5] VN28[4] VN28[3] VN28[2] VN28[1] VN28[0] 8Dh 18 0 0 0 0 0 0 0 0 19 VN36 [7] VN36 [6] VN36 [5] VN36 [4] VN36 [3] VN36 [2] VN36 [1] VN36 [0] 9Eh 20 0 0 0 0 0 0 0 0 21 VN44[7] VN44[6] VN44[5] VN44[4] VN44[3] VN44[2] VN44[1] VN44[0] ACh 22 0 0 0 0 0 0 0 0 23 VN52[7] VN52[6] VN52[5] VN52[4] VN52[3] VN52[2] VN52[1] VN52[0] BFh 24 0 0 0 0 0 0 0 0 25 VN56[7] VN56[6] VN56[5] VN56[4] VN56[3] VN56[2] VN56[1] VN56[0] CAh 26 0 0 0 0 0 0 0 0 27 VN58[7] VN58[6] VN58[5] VN58[4] VN58[3] VN58[2] VN58[1] VN58[0] D3h 28 0 0 0 0 0 0 0 0 29 VN60[7] VN60[6] VN60[5] VN60[4] VN60[3] VN60[2] VN60[1] VN60[0] DDh 30 0 0 0 0 0 0 0 0 31 VN61[7] VN61[6] VN61[5] VN61[4] VN61[3] VN61[2] VN61[1] VN61[0] E2h 32 0 0 0 0 0 0 0 0 33 VN62[7] VN62[6] VN62[5] VN62[4] VN62[3] VN62[2] VN62[1] VN62[0] E9h 34 0 0 0 0 0 0 0 0 35 VN63[7] VN63[6] VN63[5] VN63[4] VN63[3] VN63[2] VN63[1] VN63[0] F3h 36 0 0 0 0 0 0 0 0 1 VN_OFF1[3] VN_OFF1[2] VN_OFF1[1] VN_OFF1[0 ] VP_OFF1[3] VP_OFF1[2 ] VP_OFF1[1] VP_OFF1[0] 22h V 2 0 0 0 0 0 0 0 0 3 VN_OFF2[3] VN_OFF2[2] VN_OFF2[1] VN_OFF2[0 ] VP_OFF2[3] VP_OFF2[2 ] VP_OFF2[1] VP_OFF2[0] 44h 4 0 0 0 0 0 0 0 0 5 VN_OFF4[3] VN_OFF4[2] VN_OFF4[1] VN_OFF4[0 ] VP_OFF4[3] VP_OFF4[2 ] VP_OFF4[1] VP_OFF4[0] 44h 6 0 0 0 0 0 0 0 0 7 VN_OFF6[3] VN_OFF6[2] VN_OFF6[1] VN_OFF6[0 ] VP_OFF6[3] VP_OFF6[2 ] VP_OFF6[1] VP_OFF6[0] 66h 8 0 0 0 0 0 0 0 0 9 VN_OFF8[3] VN_OFF8[2] VN_OFF8[1] VN_OFF8[0 ] VP_OFF8[3] VP_OFF8[2 ] VP_OFF8[1] VP_OFF8[0] 66h 10 0 0 0 0 0 0 0 0 11 VN_OFF12[ 3] VN_OFF12[ 2] VN_OFF12[ 1] VN_OFF12[ 0] VP_OFF12[3] VP_OFF12[ 2] VP_OFF12[1 ] VP_OFF12[0] 77h 12 0 0 0 0 0 0 0 0 2012/05/11 328 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CABC Gamma E7h R/W offset (R+/R-) (Must set reg APR2_EN = 1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Draft Version NT35310 13 VN_OFF20[ 3] VN_OFF20[ 2] VN_OFF20[ 1] VN_OFF20[ 0] VP_OFF20[3] VP_OFF20[ 2] VP_OFF20[1 ] VP_OFF20[0] 77h 14 0 0 0 0 0 0 0 0 15 VN_OFF28[ 3] VN_OFF28[ 2] VN_OFF28[ 1] VN_OFF28[ 0] VP_OFF28[3] VP_OFF28[ 2] VP_OFF28[1 ] VP_OFF28[0] AAh 16 17 VN_OFF36[ 3] VN_OFF36[ 2] VN_OFF36[ 1] VN_OFF36[ 0] VP_OFF36[3] VP_OFF36[ 2] VP_OFF36[1 ] VP_OFF36[0] BBh 18 0 0 0 0 0 0 0 0 19 VN_OFF44[ 3] VN_OFF44[ 2] VN_OFF44[ 1] VN_OFF44[ 0] VP_OFF44[3] VP_OFF44[ 2] VP_OFF44[1 ] VP_OFF44[0] 99h 20 21 VN_OFF52[ 3] VN_OFF52[ 2] VN_OFF52[ 1] VN_OFF52[ 0] VP_OFF52[3] VP_OFF52[ 2] VP_OFF52[1 ] VP_OFF52[0] 76h 22 0 0 0 0 0 0 0 0 23 VN_OFF56[ 3] VN_OFF56[ 2] VN_OFF56[ 1] VN_OFF56[ 0] VP_OFF56[3] VP_OFF56[ 2] VP_OFF56[1 ] VP_OFF56[0] 87h 24 25 VN_OFF58[ 3] VN_OFF58[ 2] VN_OFF58[ 1] VN_OFF58[ 0] VP_OFF58[3] VP_OFF58[ 2] VP_OFF58[1 ] VP_OFF58[0] 45h 26 0 0 0 0 0 0 0 0 27 VN_OFF60[ 3] VN_OFF60[ 2] VN_OFF60[ 1] VN_OFF60[ 0] VP_OFF60[3] VP_OFF60[ 2] VP_OFF60[1 ] VP_OFF60[0] 43h 28 29 VN_OFF61[ 3] VN_OFF61[ 2] VN_OFF61[ 1] VN_OFF61[ 0] VP_OFF61[3] VP_OFF61[ 2] VP_OFF61[1 ] VP_OFF61[0] 33h 30 0 0 0 0 0 0 0 0 31 VN_OFF62[ 3] VN_OFF62[ 2] VN_OFF62[ 1] VN_OFF62[ 0] VP_OFF62[3] VP_OFF62[ 2] VP_OFF62[1 ] VP_OFF62[0] 32h 32 0 0 0 0 0 0 0 0 1 VN_OFF1[3] VN_OFF1[2] VN_OFF1[1] VN_OFF1[0 ] VP_OFF1[3] VP_OFF1[2 ] VP_OFF1[1] VP_OFF1[0] 22h V 2 0 0 0 0 0 0 0 0 3 VN_OFF2[3] VN_OFF2[2] VN_OFF2[1] VN_OFF2[0 ] VP_OFF2[3] VP_OFF2[2 ] VP_OFF2[1] VP_OFF2[0] 44h 4 0 0 0 0 0 0 0 0 5 VN_OFF4[3] VN_OFF4[2] VN_OFF4[1] VN_OFF4[0 ] VP_OFF4[3] VP_OFF4[2 ] VP_OFF4[1] VP_OFF4[0] 44h 6 0 0 0 0 0 0 0 0 7 VN_OFF6[3] VN_OFF6[2] VN_OFF6[1] VN_OFF6[0 ] VP_OFF6[3] VP_OFF6[2 ] VP_OFF6[1] VP_OFF6[0] 66h 8 0 0 0 0 0 0 0 0 9 VN_OFF8[3] VN_OFF8[2] VN_OFF8[1] VN_OFF8[0 ] VP_OFF8[3] VP_OFF8[2 ] VP_OFF8[1] VP_OFF8[0] 66h 10 0 0 0 0 0 0 0 0 11 VN_OFF12[ 3] VN_OFF12[ 2] VN_OFF12[ 1] VN_OFF12[ 0] VP_OFF12[3] VP_OFF12[ 2] VP_OFF12[1 ] VP_OFF12[0] 77h 12 0 0 0 0 0 0 0 0 13 VN_OFF20[ 3] VN_OFF20[ 2] VN_OFF20[ 1] VN_OFF20[ 0] VP_OFF20[3] VP_OFF20[ 2] VP_OFF20[1 ] VP_OFF20[0] 77h 14 0 0 0 0 0 0 0 0 15 VN_OFF28[ 3] VN_OFF28[ 2] VN_OFF28[ 1] VN_OFF28[ 0] VP_OFF28[3] VP_OFF28[ 2] VP_OFF28[1 ] VP_OFF28[0] AAh 16 17 VN_OFF36[ 3] VN_OFF36[ 2] VN_OFF36[ 1] VN_OFF36[ 0] VP_OFF36[3] VP_OFF36[ 2] VP_OFF36[1 ] VP_OFF36[0] BBh 18 0 0 0 0 0 0 0 0 19 VN_OFF44[ 3] VN_OFF44[ 2] VN_OFF44[ 1] VN_OFF44[ 0] VP_OFF44[3] VP_OFF44[ 2] VP_OFF44[1 ] VP_OFF44[0] 99h 20 21 VN_OFF52[ 3] VN_OFF52[ 2] VN_OFF52[ 1] VN_OFF52[ 0] VP_OFF52[3] VP_OFF52[ 2] VP_OFF52[1 ] VP_OFF52[0] 76h 22 0 0 0 0 0 0 0 0 23 VN_OFF56[ 3] VN_OFF56[ 2] VN_OFF56[ 1] VN_OFF56[ 0] VP_OFF56[3] VP_OFF56[ 2] VP_OFF56[1 ] VP_OFF56[0] 87h 24 25 VN_OFF58[ 3] VN_OFF58[ 2] VN_OFF58[ 1] VN_OFF58[ 0] VP_OFF58[3] VP_OFF58[ 2] VP_OFF58[1 ] VP_OFF58[0] 45h 26 0 0 0 0 0 0 0 0 2012/05/11 329 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CABC Gamma R/W offset (R+/R-) E8h (Must set reg R/W APR2_EN = 1) R/W R/W R/W R/W R/W R/W R/W PAGE_CTRL Into CMD2 00h W PAGE0 PAGE_CTRL Into CMD1 EFh W Draft Version NT35310 27 VN_OFF60[ 3] VN_OFF60[ 2] VN_OFF60[ 1] VN_OFF60[ 0] VP_OFF60[3] VP_OFF60[ 2] VP_OFF60[1 ] VP_OFF60[0] 43h 28 29 VN_OFF61[ 3] VN_OFF61[ 2] VN_OFF61[ 1] VN_OFF61[ 0] VP_OFF61[3] VP_OFF61[ 2] VP_OFF61[1 ] VP_OFF61[0] 33h 30 0 0 0 0 0 0 0 0 31 VN_OFF62[ 3] VN_OFF62[ 2] VN_OFF62[ 1] VN_OFF62[ 0] VP_OFF62[3] VP_OFF62[ 2] VP_OFF62[1 ] VP_OFF62[0] 32h 32 0 0 0 0 0 0 0 0 1 VN_OFF1[3] VN_OFF1[2] VN_OFF1[1] VN_OFF1[0 ] VP_OFF1[3] VP_OFF1[2 ] VP_OFF1[1] VP_OFF1[0] 22h 2 0 0 0 0 0 0 0 0 3 VN_OFF2[3] VN_OFF2[2] VN_OFF2[1] VN_OFF2[0 ] VP_OFF2[3] VP_OFF2[2 ] VP_OFF2[1] VP_OFF2[0] 44h 4 0 0 0 0 0 0 0 0 5 VN_OFF4[3] VN_OFF4[2] VN_OFF4[1] VN_OFF4[0 ] VP_OFF4[3] VP_OFF4[2 ] VP_OFF4[1] VP_OFF4[0] 44h 6 0 0 0 0 0 0 0 0 7 VN_OFF6[3] VN_OFF6[2] VN_OFF6[1] VN_OFF6[0 ] VP_OFF6[3] VP_OFF6[2 ] VP_OFF6[1] VP_OFF6[0] 66h 8 0 0 0 0 0 0 0 0 9 VN_OFF8[3] VN_OFF8[2] VN_OFF8[1] VN_OFF8[0 ] VP_OFF8[3] VP_OFF8[2 ] VP_OFF8[1] VP_OFF8[0] 66h 10 0 0 0 0 0 0 0 0 11 VN_OFF12[ 3] VN_OFF12[ 2] VN_OFF12[ 1] VN_OFF12[ 0] VP_OFF12[3] VP_OFF12[ 2] VP_OFF12[1 ] VP_OFF12[0] 77h 12 0 0 0 0 0 0 0 0 13 VN_OFF20[ 3] VN_OFF20[ 2] VN_OFF20[ 1] VN_OFF20[ 0] VP_OFF20[3] VP_OFF20[ 2] VP_OFF20[1 ] VP_OFF20[0] 77h 14 0 0 0 0 0 0 0 0 15 VN_OFF28[ 3] VN_OFF28[ 2] VN_OFF28[ 1] VN_OFF28[ 0] VP_OFF28[3] VP_OFF28[ 2] VP_OFF28[1 ] VP_OFF28[0] AAh 16 V 17 VN_OFF36[ 3] VN_OFF36[ 2] VN_OFF36[ 1] VN_OFF36[ 0] VP_OFF36[3] VP_OFF36[ 2] VP_OFF36[1 ] VP_OFF36[0] BBh 18 0 0 0 0 0 0 0 0 19 VN_OFF44[ 3] VN_OFF44[ 2] VN_OFF44[ 1] VN_OFF44[ 0] VP_OFF44[3] VP_OFF44[ 2] VP_OFF44[1 ] VP_OFF44[0] 99h 20 21 VN_OFF52[ 3] VN_OFF52[ 2] VN_OFF52[ 1] VN_OFF52[ 0] VP_OFF52[3] VP_OFF52[ 2] VP_OFF52[1 ] VP_OFF52[0] 76h 22 0 0 0 0 0 0 0 0 23 VN_OFF56[ 3] VN_OFF56[ 2] VN_OFF56[ 1] VN_OFF56[ 0] VP_OFF56[3] VP_OFF56[ 2] VP_OFF56[1 ] VP_OFF56[0] 87h 24 25 VN_OFF58[ 3] VN_OFF58[ 2] VN_OFF58[ 1] VN_OFF58[ 0] VP_OFF58[3] VP_OFF58[ 2] VP_OFF58[1 ] VP_OFF58[0] 45h 26 0 0 0 0 0 0 0 0 27 VN_OFF60[ 3] VN_OFF60[ 2] VN_OFF60[ 1] VN_OFF60[ 0] VP_OFF60[3] VP_OFF60[ 2] VP_OFF60[1 ] VP_OFF60[0] 43h 28 29 VN_OFF61[ 3] VN_OFF61[ 2] VN_OFF61[ 1] VN_OFF61[ 0] VP_OFF61[3] VP_OFF61[ 2] VP_OFF61[1 ] VP_OFF61[0] 33h 30 0 0 0 0 0 0 0 0 31 VN_OFF62[ 3] VN_OFF62[ 2] VN_OFF62[ 1] VN_OFF62[ 0] VP_OFF62[3] VP_OFF62[ 2] VP_OFF62[1 ] VP_OFF62[0] 32h 32 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 DEh 1 1 0 1 0 1 0 1 0 AAh 2012/05/11 330 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 3GAMMAR_CTRL _RED_P (E0h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E080h Parameter 1 0 E081h Parameter 2 0 0 E082h Parameter 3 0 E083h Parameter 4 0 0 E084h Parameter 5 0 E085h Parameter 6 0 0 E086h Parameter 7 0 E087h Parameter 8 0 0 E088h Parameter 9 0 E089h Parameter 10 0 0 E08Ah Parameter 11 0 E08Bh Parameter 12 0 0 E08Ch Parameter 13 0 E08Dh Parameter 14 0 0 E08Eh Parameter 15 0 E08Fh Parameter 16 0 0 E090h Parameter 17 0 E091h Parameter 18 0 0 E092h Parameter 19 0 E093h Parameter 20 0 0 E094h Parameter 21 0 E095h Parameter 22 0 0 E096h Parameter 23 0 E097h Parameter 24 0 0 E098h Parameter 25 0 E099h Parameter 26 0 0 E09Ah Parameter 27 0 E09Bh Parameter 28 0 0 E09Ch Parameter 29 0 E09Dh Parameter 30 0 0 E09Eh Parameter 31 0 E09Fh Parameter 32 0 0 E0A0h Parameter 33 0 E0A1h Parameter 34 0 0 E0A2h Parameter 35 0 E0A3h Parameter 36 0 0 Draft Version NT35310 E080h ~ E0A3h E0h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VP0[7:0] 0 0 0 0 0 VP1[7:0] 0 0 0 0 0 VP2[7:0] 0 0 0 0 0 VP4[7:0] 0 0 0 0 0 VP6[7:0] 0 0 0 0 0 VP8[7:0] 0 0 0 0 0 VP12[7:0] 0 0 0 0 0 VP20[7:0] 0 0 0 0 0 VP28[7:0] 0 0 0 0 0 VP36[7:0] 0 0 0 0 0 VP44[7:0] 0 0 0 0 0 VP52[7:0] 0 0 0 0 0 VP56[7:0] 0 0 0 0 0 VP58[7:0] 0 0 0 0 0 VP60[7:0] 0 0 0 0 0 VP61[7:0] 0 0 0 0 0 VP62[7:0] 0 0 0 0 0 VP63[7:0] 0 0 0 0 0 R/W 36 Default Value 01h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D3h 0 DDh 0 E2h 0 E9h 0 F3h 0 2012/05/11 331 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/05/11 332 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 3GAMAR_CTRL _RED_N (E1h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E180h Parameter 1 0 E181h Parameter 2 0 0 E182h Parameter 3 0 E183h Parameter 4 0 0 E184h Parameter 5 0 E185h Parameter 6 0 0 E186h Parameter 7 0 E187h Parameter 8 0 0 E188h Parameter 9 0 E189h Parameter 10 0 0 E18Ah Parameter 11 0 E18Bh Parameter 12 0 0 E18Ch Parameter 13 0 E18Dh Parameter 14 0 0 E18Eh Parameter 15 0 E18Fh Parameter 16 0 0 E190h Parameter 17 0 E191h Parameter 18 0 0 E192h Parameter 19 0 E193h Parameter 20 0 0 E194h Parameter 21 0 E195h Parameter 22 0 0 E196h Parameter 23 0 E197h Parameter 24 0 0 E198h Parameter 25 0 E199h Parameter 26 0 0 E19Ah Parameter 27 0 E19Bh Parameter 28 0 0 E19Ch Parameter 29 0 E19Dh Parameter 30 0 0 E19Eh Parameter 31 0 E19Fh Parameter 32 0 0 E1A0h Parameter 33 0 E1A1h Parameter 34 0 0 E1A2h Parameter 35 0 E1A3h Parameter 36 0 0 Draft Version NT35310 E180h ~ E1A3h E1h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VN0[7:0] 0 0 0 0 0 VN1[7:0] 0 0 0 0 0 VN2[7:0] 0 0 0 0 0 VN4[7:0] 0 0 0 0 0 VN6[7:0] 0 0 0 0 0 VN8[7:0] 0 0 0 0 0 VN12[7:0] 0 0 0 0 0 VN20[7:0] 0 0 0 0 0 VN28[7:0] 0 0 0 0 0 VN36[7:0] 0 0 0 0 0 VN44[7:0] 0 0 0 0 0 VN52[7:0] 0 0 0 0 0 VN56[7:0] 0 0 0 0 0 VN58[7:0] 0 0 0 0 0 VN60[7:0] 0 0 0 0 0 VN61[7:0] 0 0 0 0 0 VN62[7:0] 0 0 0 0 0 VN63[7:0] 0 0 0 0 0 R/W 36 Default Value 00h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D4h 0 DCh 0 E2h 0 E8h 0 F3h 0 2012/05/11 333 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/05/11 334 Version 0.04 With respect to the information represented in this document, NOVATEK makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 3GAMMAR_CTRL _GREEN_P (E2h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E280h Parameter 1 0 E281h Parameter 2 0 0 E282h Parameter 3 0 E283h Parameter 4 0 0 E284h Parameter 5 0 E285h Parameter 6 0 0 E286h Parameter 7 0 E287h Parameter 8 0 0 E288h Parameter 9 0 E289h Parameter 10 0 0 E28Ah Parameter 11 0 E28Bh Parameter 12 0 0 E28Ch Parameter 13 0 E28Dh Parameter 14 0 0 E28Eh Parameter 15 0 E28Fh Parameter 16 0 0 E290h Parameter 17 0 E291h Parameter 18 0 0 E292h Parameter 19 0 E293h Parameter 20 0 0 E294h Parameter 21 0 E295h Parameter 22 0 0 E296h Parameter 23 0 E297h Parameter 24 0 0 E298h Parameter 25 0 E299h Parameter 26 0 0 E29Ah Parameter 27 0 E29Bh Parameter 28 0 0 E29Ch Parameter 29 0 E29Dh Parameter 30 0 0 E29Eh Parameter 31 0 E29Fh Parameter 32 0 0 E2A0h Parameter 33 0 E2A1h Parameter 34 0 0 E2A2h Parameter 35 0 E2A3h Parameter 36 0 0 Draft Version NT35310 E280h ~ E2A3h E2h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VP0[7:0] 0 0 0 0 0 VP1[7:0] 0 0 0 0 0 VP2[7:0] 0 0 0 0 0 VP4[7:0] 0 0 0 0 0 VP6[7:0] 0 0 0 0 0 VP8[7:0] 0 0 0 0 0 VP12[7:0] 0 0 0 0 0 VP20[7:0] 0 0 0 0 0 VP28[7:0] 0 0 0 0 0 VP36[7:0] 0 0 0 0 0 VP44[7:0] 0 0 0 0 0 VP52[7:0] 0 0 0 0 0 VP56[7:0] 0 0 0 0 0 VP58[7:0] 0 0 0 0 0 VP60[7:0] 0 0 0 0 0 VP61[7:0] 0 0 0 0 0 VP62[7:0] 0 0 0 0 0 VP63[7:0] 0 0 0 0 0 R/W 36 Default Value 01h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D3h 0 DDh 0 E2h 0 E9h 0 F3h 0 2012/5/11 335 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value N/A 2012/5/11 336 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 3GAMMAR_CTRL _GREEN_N (E3h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E380h Parameter 1 0 E381h Parameter 2 0 0 E382h Parameter 3 0 E383h Parameter 4 0 0 E384h Parameter 5 0 E385h Parameter 6 0 0 E386h Parameter 7 0 E387h Parameter 8 0 0 E388h Parameter 9 0 E389h Parameter 10 0 0 E38Ah Parameter 11 0 E38Bh Parameter 12 0 0 E38Ch Parameter 13 0 E38Dh Parameter 14 0 0 E38Eh Parameter 15 0 E38Fh Parameter 16 0 0 E390h Parameter 17 0 E391h Parameter 18 0 0 E392h Parameter 19 0 E393h Parameter 20 0 0 E394h Parameter 21 0 E395h Parameter 22 0 0 E396h Parameter 23 0 E397h Parameter 24 0 0 E398h Parameter 25 0 E399h Parameter 26 0 0 E39Ah Parameter 27 0 E39Bh Parameter 28 0 0 E39Ch Parameter 29 0 E39Dh Parameter 30 0 0 E39Eh Parameter 31 0 E39Fh Parameter 32 0 0 E3A0h Parameter 33 0 E3A1h Parameter 34 0 0 E3A2h Parameter 35 0 E3A3h Parameter 36 0 0 E380h ~ E3A3h E3h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VN0[7:0] 0 0 0 0 0 VN1[7:0] 0 0 0 0 0 VN2[7:0] 0 0 0 0 0 VN4[7:0] 0 0 0 0 0 VN6[7:0] 0 0 0 0 0 VN8[7:0] 0 0 0 0 0 VN12[7:0] 0 0 0 0 0 VN20[7:0] 0 0 0 0 0 VN28[7:0] 0 0 0 0 0 VN36[7:0] 0 0 0 0 0 VN44[7:0] 0 0 0 0 0 VN52[7:0] 0 0 0 0 0 VN56[7:0] 0 0 0 0 0 VN58[7:0] 0 0 0 0 0 VN60[7:0] 0 0 0 0 0 VN61[7:0] 0 0 0 0 0 VN62[7:0] 0 0 0 0 0 VN63[7:0] 0 0 0 0 0 R/W 36 Default Value 00h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D4h 0 DCh 0 E2h 0 E8h 0 F3h 0 2012/5/11 337 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Description Restriction Draft Version NT35310 These registers are used for gamma correction. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/5/11 338 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 3GAMMAR_CTRL _BLUE_P (E4h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E480h Parameter 1 0 E481h Parameter 2 0 0 E482h Parameter 3 0 E483h Parameter 4 0 0 E484h Parameter 5 0 E485h Parameter 6 0 0 E486h Parameter 7 0 E487h Parameter 8 0 0 E488h Parameter 9 0 E489h Parameter 10 0 0 E48Ah Parameter 11 0 E48Bh Parameter 12 0 0 E48Ch Parameter 13 0 E48Dh Parameter 14 0 0 E48Eh Parameter 15 0 E48Fh Parameter 16 0 0 E490h Parameter 17 0 E491h Parameter 18 0 0 E492h Parameter 19 0 E493h Parameter 20 0 0 E494h Parameter 21 0 E495h Parameter 22 0 0 E496h Parameter 23 0 E497h Parameter 24 0 0 E498h Parameter 25 0 E499h Parameter 26 0 0 E49Ah Parameter 27 0 E49Bh Parameter 28 0 0 E49Ch Parameter 29 0 E49Dh Parameter 30 0 0 E49Eh Parameter 31 0 E49Fh Parameter 32 0 0 E4A0h Parameter 33 0 E4A1h Parameter 34 0 0 E4A2h Parameter 35 0 E4A3h Parameter 36 0 0 E480h ~ E4A3h E4h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VP0[7:0] 0 0 0 0 0 VP1[7:0] 0 0 0 0 0 VP2[7:0] 0 0 0 0 0 VP4[7:0] 0 0 0 0 0 VP6[7:0] 0 0 0 0 0 VP8[7:0] 0 0 0 0 0 VP12[7:0] 0 0 0 0 0 VP20[7:0] 0 0 0 0 0 VP28[7:0] 0 0 0 0 0 VP36[7:0] 0 0 0 0 0 VP44[7:0] 0 0 0 0 0 VP52[7:0] 0 0 0 0 0 VP56[7:0] 0 0 0 0 0 VP58[7:0] 0 0 0 0 0 VP60[7:0] 0 0 0 0 0 VP61[7:0] 0 0 0 0 0 VP62[7:0] 0 0 0 0 0 VP63[7:0] 0 0 0 0 0 R/W 36 Default Value 01h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D4h 0 DCh 0 E2h 0 E8h 0 F3h 0 2012/5/11 339 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/5/11 340 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 3GAMMAR_CTRL _BLUE_N (E5h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E580h Parameter 1 0 E581h Parameter 2 0 0 E582h Parameter 3 0 E583h Parameter 4 0 0 E584h Parameter 5 0 E585h Parameter 6 0 0 E586h Parameter 7 0 E587h Parameter 8 0 0 E588h Parameter 9 0 E589h Parameter 10 0 0 E58Ah Parameter 11 0 E58Bh Parameter 12 0 0 E58Ch Parameter 13 0 E58Dh Parameter 14 0 0 E58Eh Parameter 15 0 E58Fh Parameter 16 0 0 E590h Parameter 17 0 E591h Parameter 18 0 0 E592h Parameter 19 0 E593h Parameter 20 0 0 E594h Parameter 21 0 E595h Parameter 22 0 0 E596h Parameter 23 0 E597h Parameter 24 0 0 E598h Parameter 25 0 E599h Parameter 26 0 0 E59Ah Parameter 27 0 E59Bh Parameter 28 0 0 E59Ch Parameter 29 0 E59Dh Parameter 30 0 0 E59Eh Parameter 31 0 E59Fh Parameter 32 0 0 E5A0h Parameter 33 0 E5A1h Parameter 34 0 0 E5A2h Parameter 35 0 E5A3h Parameter 36 0 0 Draft Version NT35310 E580h ~ E5A3h E5h D[6] D[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access Attribute Number of Parameter(s) D[4] D[3] D[2] D[1] D[0] VN0[7:0] 0 0 0 0 0 VN1[7:0] 0 0 0 0 0 VN2[7:0] 0 0 0 0 0 VN4[7:0] 0 0 0 0 0 VN6[7:0] 0 0 0 0 0 VN8[7:0] 0 0 0 0 0 VN12[7:0] 0 0 0 0 0 VN20[7:0] 0 0 0 0 0 VN28[7:0] 0 0 0 0 0 VN36[7:0] 0 0 0 0 0 VN44[7:0] 0 0 0 0 0 VN52[7:0] 0 0 0 0 0 VN56[7:0] 0 0 0 0 0 VN58[7:0] 0 0 0 0 0 VN60[7:0] 0 0 0 0 0 VN61[7:0] 0 0 0 0 0 VN62[7:0] 0 0 0 0 0 VN63[7:0] 0 0 0 0 0 R/W 36 Default Value 00h 0 19h 0 25h 0 3Eh 0 4Ah 0 55h 0 66h 0 7Ch 0 8Dh 0 9Eh 0 ACh 0 BFh 0 CAh 0 D4h 0 DCh 0 E2h 0 E8h 0 F3h 0 2012/5/11 341 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/5/11 342 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. CABC GAMMA offset (E6h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E680h Parameter 1 0 E681h Parameter 2 0 0 E682h Parameter 3 0 E683h Parameter 4 0 0 E684h Parameter 5 0 E685h Parameter 6 0 0 E686h Parameter 7 0 E687h Parameter 8 0 0 E688h Parameter 9 0 E689h Parameter 10 0 0 E68Ah Parameter 11 0 E68Bh Parameter 12 0 0 E68Ch Parameter 13 0 E68Dh Parameter 14 0 0 E68Eh Parameter 15 0 E68Fh Parameter 16 0 0 E690h Parameter 17 0 E691h Parameter 18 0 0 E692h Parameter 19 0 E693h Parameter 20 0 0 E694h Parameter 21 0 E695h Parameter 22 0 0 E696h Parameter 23 0 E697h Parameter 24 0 0 E698h Parameter 25 0 E699h Parameter 26 0 0 E69Ah Parameter 27 0 E69Bh Parameter 28 0 0 E69Ch Parameter 29 0 E69Dh Parameter 30 0 0 E69Eh Parameter 31 0 E69Fh Parameter 32 0 0 Draft Version NT35310 E680h ~ E6A3h E6h D[6] D[5] D[4] VN_OFF1[3:0] 0 0 VN_OFF2[3:0] 0 0 VN_OFF4[3:0] 0 0 VN_OFF6[3:0] 0 0 VN_OFF8[3:0] 0 0 VN_OFF12[3:0] 0 0 VN_OFF20[3:0] 0 0 VN_OFF28[3:0] 0 0 VN_OFF36[3:0] 0 0 VN_OFF44[3:0] 0 0 VN_OFF52[3:0] 0 0 VN_OFF56[3:0] 0 0 VN_OFF58[3:0] 0 0 VN_OFF60:0] 0 0 VN_OFF61[3:0] 0 0 VN_OFF62[3:0] 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] VP_OFF1[3:0] 0 0 0 0 VP_OFF2[3:0] 0 0 0 0 VP_OFF4[3:0] 0 0 0 0 VP_OFF6[3:0] 0 0 0 0 VP_OFF8[3:0] 0 0 0 0 VP_OFF12[3:0] 0 0 0 0 VP_OFF20[3:0] 0 0 0 0 VP_OFF28[3:0] 0 0 0 0 VP_OF36[3:0] 0 0 0 0 VP_OFF44[3:0] 0 0 0 0 VP_OFF52[3:0] 0 0 0 0 VP_OFF56[3:0] 0 0 0 0 VP_OFF58[3:0] 0 0 0 0 VP_OFF60[3:0] 0 0 0 0 VP_OFF61[3:0] 0 0 0 0 VP_OFF62[3:0] 0 0 0 0 R/W 32 Default Value 22h 0 44h 0 44h 0 66h 0 66h 0 77h 0 77h 0 AAh 0 BBh 0 99h 0 76h 0 87h 0 45h 0 43h 0 33h 0 32h 0 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. 2012/5/11 343 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Register Availability Default Value Draft Version Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In NT35310 Availability Yes Yes Yes Yes Yes 2012/5/11 344 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. CABC GAMMA offset (E7h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E780h Parameter 1 0 E781h Parameter 2 0 0 E782h Parameter 3 0 E783h Parameter 4 0 0 E784h Parameter 5 0 E785h Parameter 6 0 0 E786h Parameter 7 0 E787h Parameter 8 0 0 E788h Parameter 9 0 E789h Parameter 10 0 0 E78Ah Parameter 11 0 E78Bh Parameter 12 0 0 E78Ch Parameter 13 0 E78Dh Parameter 14 0 0 E78Eh Parameter 15 0 E78Fh Parameter 16 0 0 E790h Parameter 17 0 E791h Parameter 18 0 0 E792h Parameter 19 0 E793h Parameter 20 0 0 E794h Parameter 21 0 E795h Parameter 22 0 0 E796h Parameter 23 0 E797h Parameter 24 0 0 E798h Parameter 25 0 E799h Parameter 26 0 0 E79Ah Parameter 27 0 E79Bh Parameter 28 0 0 E79Ch Parameter 29 0 E79Dh Parameter 30 0 0 E79Eh Parameter 31 0 E79Fh Parameter 32 0 0 Draft Version NT35310 E780h ~ E7A3h E7h D[6] D[5] D[4] VN_OFF1[3:0] 0 0 0 VN_OFF2[3:0] 0 0 0 VN_OFF4[3:0] 0 0 0 VN_OFF6[3:0] 0 0 0 VN_OFF8[3:0] 0 0 0 VN_OFF12[3:0] 0 0 0 VN_OFF20[3:0] 0 0 0 VN_OFF28[3:0] 0 0 0 VN_OFF36[3:0] 0 0 0 VN_OFF44[3:0] 0 0 0 VN_OFF52[3:0] 0 0 0 VN_OFF56[3:0] 0 0 0 VN_OFF58[3:0] 0 0 0 VN_OFF60:0] 0 0 0 VN_OFF61[3:0] 0 0 0 VN_OFF62[3:0] 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] VP_OFF1[3:0] 0 0 0 0 VP_OFF2[3:0] 0 0 0 0 VP_OFF4[3:0] 0 0 0 0 VP_OFF6[3:0] 0 0 0 0 VP_OFF8[3:0] 0 0 0 0 VP_OFF12[3:0] 0 0 0 0 VP_OFF20[3:0] 0 0 0 0 VP_OFF28[3:0] 0 0 0 0 VP_OF36[3:0] 0 0 0 0 VP_OFF44[3:0] 0 0 0 0 VP_OFF52[3:0] 0 0 0 0 VP_OFF56[3:0] 0 0 0 0 VP_OFF58[3:0] 0 0 0 0 VP_OFF60[3:0] 0 0 0 0 VP_OFF61[3:0] 0 0 0 0 VP_OFF62[3:0] 0 0 0 0 R/W 32 Default Value 22h 0 44h 0 44h 0 66h 0 66h 0 77h 0 77h 0 AAh 0 BBh 0 99h 0 76h 0 87h 0 45h 0 43h 0 33h 0 32h 0 2012/5/11 345 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/5/11 346 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. CABC GAMMA offset (E8h) Address (MDDI I/F) Address (Other I/F) Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] E880h Parameter 1 0 E881h Parameter 2 0 0 E882h Parameter 3 0 E883h Parameter 4 0 0 E884h Parameter 5 0 E885h Parameter 6 0 0 E886h Parameter 7 0 E887h Parameter 8 0 0 E888h Parameter 9 0 E889h Parameter 10 0 0 E88Ah Parameter 11 0 E88Bh Parameter 12 0 0 E88Ch Parameter 13 0 E88Dh Parameter 14 0 0 E88Eh Parameter 15 0 E88Fh Parameter 16 0 0 E890h Parameter 17 0 E891h Parameter 18 0 0 E892h Parameter 19 0 E893h Parameter 20 0 0 E894h Parameter 21 0 E895h Parameter 22 0 0 E896h Parameter 23 0 E897h Parameter 24 0 0 E898h Parameter 25 0 E899h Parameter 26 0 0 E89Ah Parameter 27 0 E89Bh Parameter 28 0 0 E89Ch Parameter 29 0 E89Dh Parameter 30 0 0 E89Eh Parameter 31 0 E89Fh Parameter 32 0 0 Draft Version NT35310 E880h ~ E8A3h E8h D[6] D[5] D[4] VN_OFF1[3:0] 0 0 0 VN_OFF2[3:0] 0 0 0 VN_OFF4[3:0] 0 0 0 VN_OFF6[3:0] 0 0 0 VN_OFF8[3:0] 0 0 0 VN_OFF12[3:0] 0 0 0 VN_OFF20[3:0] 0 0 0 VN_OFF28[3:0] 0 0 0 VN_OFF36[3:0] 0 0 0 VN_OFF44[3:0] 0 0 0 VN_OFF52[3:0] 0 0 0 VN_OFF56[3:0] 0 0 0 VN_OFF58[3:0] 0 0 0 VN_OFF60:0] 0 0 0 VN_OFF61[3:0] 0 0 0 VN_OFF62[3:0] 0 0 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] VP_OFF1[3:0] 0 0 0 0 VP_OFF2[3:0] 0 0 0 0 VP_OFF4[3:0] 0 0 0 0 VP_OFF6[3:0] 0 0 0 0 VP_OFF8[3:0] 0 0 0 0 VP_OFF12[3:0] 0 0 0 0 VP_OFF20[3:0] 0 0 0 0 VP_OFF28[3:0] 0 0 0 0 VP_OF36[3:0] 0 0 0 0 VP_OFF44[3:0] 0 0 0 0 VP_OFF52[3:0] 0 0 0 0 VP_OFF56[3:0] 0 0 0 0 VP_OFF58[3:0] 0 0 0 0 VP_OFF60[3:0] 0 0 0 0 VP_OFF61[3:0] 0 0 0 0 VP_OFF62[3:0] 0 0 0 0 R/W 32 Default Value 22h 0 44h 0 44h 0 66h 0 66h 0 77h 0 77h 0 AAh 0 BBh 0 99h 0 76h 0 87h 0 45h 0 43h 0 33h 0 32h 0 2012/5/11 347 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 Description Restriction These registers are used for gamma correction. ※ Note1: Please access this command in command2_P1. ※ Note2: This command only can be read on display off. ※ Note3: Please access all gamma table at 1 time. To avoid contection during register accessing, please make sure that the CABC functions are disabled. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 2012/5/11 348 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 PAGE_LOCK (00h):Set the Register to command2 Page 0 Address (MDDI I/F) 0080h Address (Other I/F) 00h Address Parameter D[15:8] (MDDI I/F) (Other I/F) D[7] D[6] D[5] D[4] 0080h Parameter 1 0 1 0 1 0 Access Attribute Number of Parameter(s) D[3] D[2] D[1] D[0] 1 0 1 0 W 1 Default Value AAh Description This command is used for goto CMD2_P0 register access. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Status Power On Sequence S/W Reset H/W Reset Default Value D[15:0] - 2012/5/11 349 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 7. Electrical Characteristics 7.1 ABSOLUTE MAXIMUM RATINGS Item Supply voltage Supply voltage Driver supply Voltage Operating temperature range Storage Temperature range Logic Input voltage range Logic Output voltage range Supply voltage (MTP) Max Voltage of VGH-VGL Differential Input Voltage Humidity Symbol VDDI VCI-AVSS AVDD-AVSS TOPR TSTG VIN VO MTP_PWR - AVSS VGH-VGL DSI-CLK+, DSI-CLK+ DSI-D0+,DSI-D0- Rating -0.3~+5.5 -0.3~+5.5 -0.3 ~ +6.5 -30 ~ +75 -30 ~ +85 -0.3~+3.6 -0.3~+3.6 -0.3~7.8 < 32 -0.3~+1.8 5% to 95% Unit V V V ℃ ℃ V V V V V % NOTE: If the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. 2012/5/11 350 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 7.2 DC CHARACTERISTICS 7.2.1 Basic Characteristics Parameter Symbol Conditions Power & Operation Voltage Analog Operating voltage MDDI/MIPI Operating voltage VCI Digital Operating voltage Operating Voltage MDDI/MIPI Supply voltage Specification Unit MIN TYP MAX Notes 2.3 2.8 3.3 V Note 1, 10 I/O operating voltage VDDI I/O supply voltage 1.65 1.8 3.3 V Note 1, 10 Input / Output Logic High level input voltage VIH 0.7*VDDI - Logic Low level input voltage VIL - VSS - Logic High level output voltage VOH IOH = -1mA 0.8VDDI - Logic Low level output voltage VOL IOL = +1mA VSS - Logic High level leakage (Except MDDI / MIPI) ILIH1 Vin = 0 to VDDI Logic Low level leakage (Except MDDI / MIPI) ILIL1 Vin = 0 to VDDI -1 Logic High level leakage ILIH2 (MDDI) Vin = 0 to VDDI (MDDI / MIPI) ILIH2 (MIPI) Vin = 0 to VDDI Logic Low level leakage (MDDI / MIPI) ILIL2 (MDDI) Vin = 0 to 1.3V ILIL2 (MIPI) Vin = 0 to 1.3V -10 VCOM Operation VCOM voltage VCOM Operating Voltage -3 - Source Driver Gamma reference voltage GVDDP GVDDN GVMP AVEE+0.3 -5.5 - Output deviation voltage (Source Positive output) V,dev1 Sout>= +4.2V, Sout<= +0.8V - - V,dev2 +0.8V= -0.8V, Sout<= -4.2V -4.2V=4.2V, Sout<=0.8V Max (S1, S2, S3, …. , S1080) – Min (S1, S2, S3, …. , S1080) <= 35mV -When 4.2V>Sout>0.8V Max (S1, S2, S3, …. , S1080) – Min (S1, S2, S3, …. , S1080) <= 25mV -Example When Sout level is 3.95V (Gray scale voltage) Max (S1, S2, S3, …. , S1080) = 3.969V Min (S1, S2, S3, …. , S1080) = 3.943V Sout deviation = Max (S1, S2, S3, …. , S1080) – Min (S1, S2, S3, …. , S1080) = 26mV <- Out Spec 2012/5/11 365 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 8. REFERENCE APPLICATIONS Draft Version NT35310 External Components Table1: Case1 : Appropriate for light panel loading (1) CP1_MODE = 0, PUMP_MODE[1:0] = 01 (AVDD = VCI X 2) Pad Name Connection VDDI Interface Power VDDI ------||------ GND (Option) VCI VSS,AVSS VDD VCOM VLPH C11P, C11M C12P, C12M C13P, C13M C21P, C21M DC-DC, Analog and Regulator Power VCI ------||------ GND (Option) Connect to GND Connect to Capacitor (Max 10V): VDD ------||------ GND Connect to Capacitor (Max 10V): VCOM ------||------ GND (Option) Connect to Capacitor (Max 10V): VLPH ------||------ GND (Option) Connect to Capacitor (Max 10V): C11P ------||------ C11M Connect to Capacitor (Max 10V): C12P ------||------ C12M Connect to Capacitor (Max 16V): C13P ------||------ C13M Connect to Capacitor (Max 10V): C21P ------||------ C21M C22P, C22M Connect to Capacitor (Max 10V): C22P ------||------ C22M AVDD Connect to Capacitor (Max 10V): AVDD ------||------ GND (Option) AVEE Connect to Capacitor (Max 10V): AVEE ------||------ GND (Option) VCL Connect to Capacitor (Max 10V): VCL ------||------ GND (Option) VGH Connect to Capacitor (Max 26V): VGH ------||------ GND VGL Connect to Capacitor (Max 26V): VGL ------||------ GND Note: 1. The capacitor of VLPH can be removed when MIPI DSI and MDDI is not applied. Total : 8 Cap. Note2: In case1,AVDD/AVEE/VCL can’t be adjust. Note3:AVDD = 2 * VCI. Typical Value 2.2μF 2.2μF 1.0μF 2.2μF 1.0μF (Note 1) 1.0μF 1.0μF 1.0μF 1.0μF 1.0μF 1.0μF ~ 2.2μF 1.0μF ~ 2.2μF 2.2μF 1.0μF 1.0μF 2012/5/11 366 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 External Components Table2: Case2 : Appropriate for heavier panel loading (1) CP1_MODE = 1, PUMP_MODE[1:0] = 01 or 10 (AVDD = VCI x 2 or VCI X 3) Pad Name Connection VDDI VCI VSS,AVSS VDD VCOM VLPH Interface Power VDDI ------||------ GND (Option) DC-DC, Analog and Regulator Power VCI ------||------ GND (Option) Connect to GND Connect to Capacitor (Max 10V): VDD ------||------ GND Connect to Capacitor (Max 10V): VCOM ------||------ GND (Option) Connect to Capacitor (Max 10V): VLPH ------||------ GND (Option) C11P, C11M C12P, C12M C13P, C13M C21P, C21M C22P, C22M AVDD AVEE VCL VGH Connect to Capacitor (Max 10V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 16V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 10V): Connect to Capacitor (Max 26V): C11P ------||------ C11M C12P ------||------ C12M C13P ------||------ C13M C21P ------||------ C21M C22P ------||------ C22M AVDD ------||------ GND AVEE ------||------ GND (Option) VCL ------||------ GND VGH ------||------ GND VGL Connect to Capacitor (Max 26V): VGL ------||------ GND Note: 1. The capacitor of VLPH can be removed when MIPI DSI and MDDI is not applied. Total : 10 Cap. Note2: In case2,AVDD/AVEE/VCL/VGH/VGL can fine tune Pump CLK. Note3: AVDD = 2 * VCI or 3*VCI. Typical Value 2.2μF 2.2μF 1.0μF 2.2μF 1.0μF (Note 1) 1.0μF 1.0μF 1.0μF 1.0μF 1.0μF 1.0μF ~ 2.2μF 1.0μF ~ 2.2μF 2.2μF 1.0μF 1.0μF 2012/5/11 367 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 8.1 Connect example with external components Case 1: CP1_MODE = 0, PUMP_MODE[1:0] = 01 (AVDD = VCI X 2) NT35310 VCI C11 C12 VCL C11P C11M C12P C12M CP1 CS1 (option) AVDD CS2 (option) VCI C13 VGH CS3 VGL CS4 C13P C13M CP 2/3 VCI VCI AVDD AVEE Power Block AVEE Internal reference generating circuit VREF VDD regulator VDD CS6 VCOM regulator VCOM CS7 (option) C21 C22 AVEE CS5 (option) C21P C21M C22P C22M CP5 AVDD VCI AVDD AVEE GVDD regulator GVDDP GVDDN VLPH regulator VLPH CS8 (option) 2012/5/11 368 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Case 2 : CP1_MODE = 1, PUMP_MODE[1:0] = 01 or 10 (AVDD = VCI x 2 or VCI X 3) NT35310 VCI C11 C12 VCL C11P C11M C12P C12M CP1 CS1 AVDD CS2 VCI C13 VGH CS3 VGL CS4 C13P C13M CP 2/3 VCI VCI AVDD AVEE Power Block AVEE Internal reference generating circuit VREF VDD regulator VDD CS6 VCOM regulator VCOM CS7 (option) C21 C22 AVEE CS5 (option) C21P C21M C22P C22M CP5 AVDD VCI AVDD AVEE GVDD regulator GVDDP GVDDN VLPH regulator VLPH CS8 (option) 2012/5/11 369 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 8.2 Power Scheme Draft Version NT35310 VGH (2AVDD, VCI+2AVDD, 3AVDD) AVDD (VCI x 2, VCI x 3) GVDDP VGSP (3V~5.5V, 25mV step) (0.2V~3.0V, 25mV step) VCI (2.3V – 3.3V) VDDI (1.65V - 3.3V) VSS AVSS VCL GVDDN (-3V~-5.5V, 25mV step) VREF VDD VLPH VGSN (-0.2V~-3.0V, 25mV step) VCOMDC ( -0.2V ~ -3V, 12.5 mV step) AVEE (-AVDD) VGL (-2AVDD, -VCL-2AVDD, -3AVDD) 2012/5/11 370 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 8.3 Maximum Series Resistance The driver will operate in ‘Chip on Glass’ applications with series resistances (due to ITO track resistance). Voltages are specified at module I/O assuming maximum values as in below table. Maximum series resistance on module Name Type Maximum Series Resistance Unit MTP_PWR Power supply 10 Ω VDDI Power supply 3 Ω VCI Power supply 3 Ω AVSS Power supply 3 Ω VSS Power supply 3 Ω IM[2:0] Input 100 Ω RDX, WRX_SCL, DCX, CSX, DIN_SDA, DOUT Input 100 Ω RESX Input 100 Ω TE, LEDPWM1, LEDPWM2, TE1/IDLE_ON Output 100 Ω DB[17:0] I/O 100 Ω HSSI_CLK_P, HSSI_CLK_N HSSI_D0_P, HSSI_D0_N I/O 10 Ω PCLK, DE, VSYNC, HSYNC Input 100 Ω VGH Output 10 Ω VGL Output 10 Ω VLPH Capacitor connection 20 Ω VCOM Capacitor connection 5 Ω AVDD Capacitor connection 3 Ω AVEE Capacitor connection 3 Ω VDD Capacitor connection 5 Ω VCL Capacitor connection 5 Ω GVDDP,GVDDN, VREF Output 10 Ω C13P, C13M, Capacitor connection 5 Ω C11P, C11M, C12P, C12M C21P, C21M, C22P, C22M Capacitor connection 3 Ω 2012/5/11 371 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 9. CHIP INFORMATION 9.1 CHIP INFORMATION 9.1.1 CHIP OVERVIEW Chip size: 22780um x 761um Coordinate origin: Chip center Bump size: Input PAD = 81um(height) x 50(width) Output PAD = 99um(height) x 15(width) 95 um 761 um 225 um 70 um 90 um ALK_L NO1 MTP_PWR MTP_PWR VSS VSS VSS_DUM VSS_DUM VSS_DUM VSS_DUM LED_PWM1 VCI VCI VCI VLPH VLPH VLPH HSSI_D0_N HSSI_D0_N HSSI_D0_P HSSI_D0_P HSSI_CLK_N HSSI_CLK_N HSSI_CLK_P HSSI_CLK_P VSS_DUM VSS_DUM VSS_DUM VSS_DUM VSS_DUM Note NO 1776 VCOM G1 VCOM G5 G3 G7 G9 G11 G13 G17 G15 G29 231.5um 107.5um 185 um ALK_L 15um 15um 10um 20um 10um 10um 15um 20um 15um 10um 10um 5um 70um ALK_R 10um 15um 20um 15um 10um 70um 5um 10um 10um 20um 10um 15um 15um View point : Top view Note: Pad position please follow the table as below: Chip center = (0, 0) 22780um 70 um C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P NO 320 225 um 98.5 um ALK_R G14 G16 G12 G11 G8 G10 G4 G6 G2 G0 VCOM VCOM NO 321 185 um 2012/5/11 372 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 9.1.2 Application Circuit Case1: CP1_MODE = 0, PUMP_MODE[1:0] = 01 (AVDD = VCI X 2) FPC Pad for Booster circuit Regulator output External power supply GND Gate output Source output Host control signal Floa ting PANEL VCOM 2.3V~3.3V ( Option ) ( Option ) ( Option ) ( Option ) ( Option ) 1.6V~3.3V TE CSX DCX WRX_SCL RDX DIN_SDA DOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DE PCLK HSYNC VSYNC RESX IM2 IM1 IM0 LEDPWM2 HSSI_CLK_P HSSI_CLK_N HSSI_D0_ P HSSI_D0_N 2.3V~3.3V LEDPWM1 MTP_PWR ( Option ) C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C13P C13P C13P C13P C13P C13P C13M C13M C13M C13M C13M C13M VGH VGH VGH VGH VGH VGH VGH VGH AVSS AVSS AVSS VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL C12P C12P C12P C12P C12P C12P C12P C12P C12P C12P C12M C12M C12M C12M C12M C12M C12M C12M C12M C12M C11P C11P C11P C11P C11P C11P C11P C11P C11P C11P C11P C11M C11M C11M C11M C11M C11M C11M C11M C11M C11M C11M VSS_DUM VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VCL VCL VCL VCL VCL VCL VCL VCL VCL VSS_DUM GVDDP GVDDP GVDDP GVDDP GVDDN GVDDN GVDDN GVDDN GVDDN GVDDN GVDDN VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS VSS_DUM VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDI VDDI VDDI VDDI VDDI VDDI VDDI TE CSX DCX WRX_SCL RDX DIN_SDA DOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DE PCLK HSYNC VSYNC RESX IM2 IM1 IM0 LEDPWM2 TE1/IDLE_ON FRM TESTM OSC VSS_DUM VSS_DUM VSS_DUM VSS_DUM VSS_DUM VSS_DUM HSSI_CLK_P HSSI_CLK_P HSSI_CLK_N HSSI_CLK_N HSSI_D0_P HSSI_D0_P HSSI_D0_N HSSI_D0_N VLPH VLPH VLPH VCI VCI VCI LEDPWM1 VSS_DUM VSS_DUM VSS_DUM VSS_DUM VSS VSS MTP_PWR MTP_PWR VCOM VCOM G[0] G[2] G[4] G[6] G[8] G[10] G[470] G[472] G[474] G[476] G[478] VCOM VCOM VCOM VCOM S[959] S[958] S[957] Bump Down NT35310 S[483] S[482] S[481] S[480] DUMMY DUMMY DUMMY DUMMY S[479] S[478] S[477] S[476] S[3 ] S[2 ] S[1 ] S[0 ] VCOM VCOM VCOM VCOM G[ 479 ] G[ 477 ] G[ 475 ] G[ 473 ] G[11] G[9 ] G[7 ] G[5 ] G[3 ] G[1 ] VCOM VCOM Gate Output Source Output Gate Output VCOM NT35310 2012/5/11 373 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version Case 2: CP1_MODE = 1, PUMP_MODE[1:0] = 01 or 10 (AVDD = VCI x 2 or VCI X 3) FPC 2.3V~3.3V ( Option ) ( Option ) ( Option ) 1.6V~3.3V TE CSX DCX WRX_SCL RDX DIN_SDA DOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DE PCLK HSYNC VSYNC RESX IM2 IM1 IM0 LEDPWM2 HSSI_CLK_P HSSI_CLK_N HS SI_D0_P HSSI_D0_N 2.3V~3.3V LEDPWM1 MTP_PWR ( Option ) Pad for Booster circuit Regulator output External power supply GND Gate output Source output Host control signal Floating PANEL VCOM C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22P C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C22M C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21P C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C21M C13P C13P C13P C13P C13P C13P C13M C13M C13M C13M C13M C13M VGH VGH VGH VGH VGH VGH VGH VGH AVSS AVSS AVSS VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL C12P C12P C12P C12P C12P C12P C12P C12P C12P C12P C12M C12M C12M C12M C12M C12M C12M C12M C12M C12M C11P C11P C11P C11P C11P C11P C11P C11P C11P C11P C11P C11M C11M C11M C11M C11M C11M C11M C11M C11M C11M C11M VSS_DUM VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVEE AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VCL VCL VCL VCL VCL VCL VCL VCL VCL VSS_DUM GVDDP GVDDP GVDDP GVDDP GVDDN GVDDN GVDDN GVDDN GVDDN GVDDN GVDDN VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS VSS_DUM VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDI VDDI VDDI VDDI VDDI VDDI VDDI TE CSX DCX WRX_SCL RDX DIN_SDA DOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DE PCLK HSYNC VSYNC RESX IM2 IM1 IM0 LEDPWM2 TE1/IDLE_ON FRM TESTM OSC VS S_DUM VS S_DUM VSS_DUM VSS_DUM VSS_DUM VSS_DUM HSSI_CLK_P HSSI_CLK_P HSSI_CLK_N HSSI_CLK_N HSSI_D0_P HSSI_D0_P HSSI_D0_N HSSI_D0_N VLPH VLPH VLPH VCI VCI VCI LEDPWM1 VSS_DUM VSS_DUM VSS_DUM VSS_DUM VSS VSS MTP_PWR MTP_PWR VCOM VCOM G[0] G[2] G[4] G[6] G[8] G[10 ] G [470 ] G [472 ] G [474 ] G [476 ] G [478 ] VCOM VCOM VCOM VCOM S [959 ] S [958 ] S [957 ] Bump Down NT35310 S [483 ] S [482 ] S [481 ] S [480 ] DUMMY DUMMY DUMMY DUMMY S [479 ] S [478 ] S [477 ] S [476 ] S[3] S[2] S[1] S[0] VCOM VCOM VCOM VCOM G[479] G[477] G[475] G[473] G[11] G[9] G[7] G[5] G[3] G[1] VCOM VCOM Gate Output Source Output Gate Output VCOM NT35310 2012/5/11 374 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version 9.2 BUMP INFORMATION 9.2.1 Input PAD Format Item Pad pitch Bump width Bump height Bump to bump gap Bump area Chip boundary to bump edge Symbol A C H K C*H L NT35310 Size 70 um 50 um 81 um 20 um 4050 um2 58 um A C K H L 2012/5/11 375 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 9.2.2 Output PAD Fotmat Draft Version Item Pad pitch Bump width Bump height Bump to bump gap (Vertical) Bump to bump gap (Horizontal) Bump area Chip boundary to bump edge Symbol A C H J K C*H L NT35310 Size 15 um 15 um 99 um 25 um 15 um 1485um2 58 um Boundary (include scribe Lane) L K C H J A 2012/5/11 376 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 9.2.3 Alignment Mark Information 10 um 15 um 20 um 10um 15 um 10 um Draft Version 70 um 70 um NT35310 10um 10 um 15 um 20 um 15 um 10 um 10 um 15 um 20 um 15 um 10 um 10 um 15 um 20 um 15 um 10 um 2012/5/11 377 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 9.3 PAD COORDINATES 9.3.1 For Panel Resolution: 320(RGB)*480 Note: NT35310H-DP,please follow pad coordinates(No.16 to 23) on left side.NT35310H-DP01, please follow pad coordinates(No.16 to 23) on right side. N o Name X 1 MTP_PWR -11165 2 MTP_PWR -11095 3 VSS -11025 4 VSS -10955 5 VSS_DUM -10885 6 VSS_DUM -10815 7 VSS_DUM -10745 8 VSS_DUM -10675 9 LEDPWM1 -10605 10 VCI -10535 11 VCI -10465 12 VCI -10395 13 VLPH -10325 14 VLPH -10255 15 VLPH -10185 16 HSSI_CLK_P HSSI_D0_N -10115 17 HSSI_CLK_P HSSI_D0_N -10045 18 HSSI_CLK_N HSSI_D0_P -9975 19 HSSI_CLK_N HSSI_D0_P -9905 20 HSSI_D0_P HSSI_CLK_N -9835 21 HSSI_D0_P HSSI_CLK_N -9765 22 HSSI_D0_N HSSI_CLK_P -9695 23 HSSI_D0_N HSSI_CLK_P -9625 24 VSS_DUM -9555 25 VSS_DUM -9485 26 VSS_DUM -9415 27 VSS_DUM -9345 28 VSS_DUM -9275 29 VSS_DUM -9205 30 OSC -9135 31 TESTM -9065 32 FRM -8995 33 TE1/IDLE_ON -8925 34 LEDPWM2 -8855 35 IM0 -8785 36 IM1 -8715 37 IM2 -8645 38 RESX -8575 39 VS -8505 40 HS -8435 41 PCLK -8365 42 DE -8295 43 D17 -8225 44 D16 -8155 45 D15 -8085 46 D14 -8015 47 D13 -7945 48 D12 -7875 49 D11 -7805 Y -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 No Name 53 D7 54 D6 55 D5 56 D4 57 D3 58 D2 59 D1 60 D0 61 DOUT 62 DIN_SDA 63 RDX 64 WRX_SCL 65 DCX 66 CSX 67 TE 68 VDDI 69 VDDI 70 VDDI 71 VDDI 72 VDDI 73 VDDI 74 VDDI 75 VDD 76 VDD 77 VDD 78 VDD 79 VDD 80 VDD 81 VDD 82 VDD 83 VDD 84 VDD 85 VDD 86 VSS 87 VSS 88 VSS 89 VSS 90 VSS 91 VSS 92 VSS 93 VSS 94 VSS 95 VSS 96 VSS_DUM 97 AVSS 98 AVSS 99 AVSS 100 AVSS 101 AVSS X -7525 -7455 -7385 -7315 -7245 -7175 -7105 -7035 -6965 -6895 -6825 -6755 -6685 -6615 -6545 -6475 -6405 -6335 -6265 -6195 -6125 -6055 -5985 -5915 -5845 -5775 -5705 -5635 -5565 -5495 -5425 -5355 -5285 -5215 -5145 -5075 -5005 -4935 -4865 -4795 -4725 -4655 -4585 -4515 -4445 -4375 -4305 -4235 -4165 Y -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 No Name X Y 105 AVSS -3885 -282 106 AVSS -3815 -282 107 VCOM -3745 -282 108 VCOM -3675 -282 109 VCOM -3605 -282 110 VCOM -3535 -282 111 VCOM -3465 -282 112 VCOM -3395 -282 113 VCOM -3325 -282 114 VCOM -3255 -282 115 VCOM -3185 -282 116 VCOM -3115 -282 117 VCOM -3045 -282 118 VCOM -2975 -282 119 VCOM -2905 -282 120 VCOM -2835 -282 121 VCOM -2765 -282 122 VCOM -2695 -282 123 VREF -2625 -282 124 VREF -2555 -282 125 VREF -2485 -282 126 VREF -2415 -282 127 VREF -2345 -282 128 VREF -2275 -282 129 VREF -2205 -282 130 VREF -2135 -282 131 VREF -2065 -282 132 VREF -1995 -282 133 GVDDN -1925 -282 134 GVDDN -1855 -282 135 GVDDN -1785 -282 136 GVDDN -1715 -282 137 GVDDN -1645 -282 138 GVDDN -1575 -282 139 GVDDN -1505 -282 140 GVDDP -1435 -282 141 GVDDP -1365 -282 142 GVDDP -1295 -282 143 GVDDP -1225 -282 144 VSS_DUM -1155 -282 145 VCL -1085 -282 146 VCL -1015 -282 147 VCL -945 -282 148 VCL -875 -282 149 VCL -805 -282 150 VCL -735 -282 151 VCL -665 -282 152 VCL -595 -282 153 VCL -525 -282 2012/5/11 378 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 50 D10 -7735 -282 102 AVSS -4095 -282 154 AVDD -455 -282 51 D9 -7665 -282 103 AVSS -4025 -282 155 AVDD -385 -282 52 D8 -7595 -282 104 AVSS -3955 -282 156 AVDD -315 -282 2012/5/11 379 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No Name 157 AVDD 158 AVDD 159 AVDD 160 AVDD 161 AVDD 162 AVDD 163 AVEE 164 AVEE 165 AVEE 166 AVEE 167 AVEE 168 AVEE 169 AVEE 170 AVEE 171 AVEE 172 AVEE 173 AVEE 174 VCI 175 VCI 176 VCI 177 VCI 178 VCI 179 VCI 180 VCI 181 VCI 182 VCI 183 VCI 184 VCI 185 VCI 186 VCI 187 VCI 188 VCI 189 VCI 190 VCI 191 VCI 192 VCI 193 VSS_DUM 194 C11M 195 C11M 196 C11M 197 C11M 198 C11M 199 C11M 200 C11M 201 C11M 202 C11M 203 C11M 204 C11M 205 C11P 206 C11P 207 C11P 208 C11P X -245 -175 -105 -35 35 105 175 245 315 385 455 525 595 665 735 805 875 945 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205 2275 2345 2415 2485 2555 2625 2695 2765 2835 2905 2975 3045 3115 3185 3255 3325 Y -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 Draft Version No Name 209 C11P 210 C11P 211 C11P 212 C11P 213 C11P 214 C11P 215 C11P 216 C12M 217 C12M 218 C12M 219 C12M 220 C12M 221 C12M 222 C12M 223 C12M 224 C12M 225 C12M 226 C12P 227 C12P 228 C12P 229 C12P 230 C12P 231 C12P 232 C12P 233 C12P 234 C12P 235 C12P 236 VGL 237 VGL 238 VGL 239 VGL 240 VGL 241 VGLO 242 VGLO 243 VGLO 244 VGLO 245 VGLO 246 CVSS 247 CVSS 248 CVSS 249 VGH 250 VGH 251 VGH 252 VGH 253 VGH 254 VGH 255 VGH 256 VGH 257 C13M 258 C13M 259 C13M 260 C13M X 3395 3465 3535 3605 3675 3745 3815 3885 3955 4025 4095 4165 4235 4305 4375 4445 4515 4585 4655 4725 4795 4865 4935 5005 5075 5145 5215 5285 5355 5425 5495 5565 5635 5705 5775 5845 5915 5985 6055 6125 6195 6265 6335 6405 6475 6545 6615 6685 6755 6825 6895 6965 Y -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 -282 NT35310 No Name X Y 261 C13M 7035 -282 262 C13M 7105 -282 263 C13P 7175 -282 264 C13P 7245 -282 265 C13P 7315 -282 266 C13P 7385 -282 267 C13P 7455 -282 268 C13P 7525 -282 269 C21M 7595 -282 270 C21M 7665 -282 271 C21M 7735 -282 272 C21M 7805 -282 273 C21M 7875 -282 274 C21M 7945 -282 275 C21M 8015 -282 276 C21M 8085 -282 277 C21M 8155 -282 278 C21M 8225 -282 279 C21M 8295 -282 280 C21M 8365 -282 281 C21M 8435 -282 282 C21M 8505 -282 283 C21P 8575 -282 284 C21P 8645 -282 285 C21P 8715 -282 286 C21P 8785 -282 287 C21P 8855 -282 288 C21P 8925 -282 289 C21P 8995 -282 290 C21P 9065 -282 291 C21P 9135 -282 292 C21P 9205 -282 293 C21P 9275 -282 294 C21P 9345 -282 295 C21P 9415 -282 296 C22M 9485 -282 297 C22M 9555 -282 298 C22M 9625 -282 299 C22M 9695 -282 300 C22M 9765 -282 301 C22M 9835 -282 302 C22M 9905 -282 303 C22M 9975 -282 304 C22M 10045 -282 305 C22M 10115 -282 306 C22M 10185 -282 307 C22M 10255 -282 308 C22P 10325 -282 309 C22P 10395 -282 310 C22P 10465 -282 311 C22P 10535 -282 312 C22P 10605 -282 2012/5/11 380 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. Draft Version NT35310 No Name 313 C22P 314 C22P 315 C22P 316 C22P 317 C22P 318 C22P 319 C22P 320 C22P 321 VCOM 322 VCOM 323 G0 324 G2 325 G4 326 G6 327 G8 328 G10 329 G12 330 G14 331 G16 332 G18 333 G20 334 G22 335 G24 336 G26 337 G28 338 G30 339 G32 340 G34 341 G36 342 G38 343 G40 344 G42 345 G44 346 G46 347 G48 348 G50 349 G52 350 G54 351 G56 352 G58 353 G60 354 G62 355 G64 356 G66 357 G68 358 G70 359 G72 360 G74 361 G76 362 G78 363 G80 364 G82 X Y No 10675 -282 365 10745 -282 366 10815 -282 367 10885 -282 368 10955 -282 369 11025 -282 370 11095 -282 371 11165 -282 372 11205 149 373 11190 273 374 11175 149 375 11160 273 376 11145 149 377 11130 273 378 11115 149 379 11100 273 380 11085 149 381 11070 273 382 11055 149 383 11040 273 384 11025 149 385 11010 273 386 10995 149 387 10980 273 388 10965 149 389 10950 273 390 10935 149 391 10920 273 392 10905 149 393 10890 273 394 10875 149 395 10860 273 396 10845 149 397 10830 273 398 10815 149 399 10800 273 400 10785 149 401 10770 273 402 10755 149 403 10740 273 404 10725 149 405 10710 273 406 10695 149 407 10680 273 408 10665 149 409 10650 273 410 10635 149 411 10620 273 412 10605 149 413 10590 273 414 10575 149 415 10560 273 416 Name G84 G86 G88 G90 G92 G94 G96 G98 G100 G102 G104 G106 G108 G110 G112 G114 G116 G118 G120 G122 G124 G126 G128 G130 G132 G134 G136 G138 G140 G142 G144 G146 G148 G150 G152 G154 G156 G158 G160 G162 G164 G166 G168 G170 G172 G174 G176 G178 G180 G182 G184 G186 X Y 10545 149 10530 273 10515 149 10500 273 10485 149 10470 273 10455 149 10440 273 10425 149 10410 273 10395 149 10380 273 10365 149 10350 273 10335 149 10320 273 10305 149 10290 273 10275 149 10260 273 10245 149 10230 273 10215 149 10200 273 10185 149 10170 273 10155 149 10140 273 10125 149 10110 273 10095 149 10080 273 10065 149 10050 273 10035 149 10020 273 10005 149 9990 273 9975 149 9960 273 9945 149 9930 273 9915 149 9900 273 9885 149 9870 273 9855 149 9840 273 9825 149 9810 273 9795 149 9780 273 No Name 417 G188 418 G190 419 G192 420 G194 421 G196 422 G198 423 G200 424 G202 425 G204 426 G206 427 G208 428 G210 429 G212 430 G214 431 G216 432 G218 433 G220 434 G222 435 G224 436 G226 437 G228 438 G230 439 G232 440 G234 441 G236 442 G238 443 G240 444 G242 445 G244 446 G246 447 G248 448 G250 449 G252 450 G254 451 G256 452 G258 453 G260 454 G262 455 G264 456 G266 457 G268 458 G270 459 G272 460 G274 461 G276 462 G278 463 G280 464 G282 465 G284 466 G286 467 G288 468 G290 X Y 9765 149 9750 273 9735 149 9720 273 9705 149 9690 273 9675 149 9660 273 9645 149 9630 273 9615 149 9600 273 9585 149 9570 273 9555 149 9540 273 9525 149 9510 273 9495 149 9480 273 9465 149 9450 273 9435 149 9420 273 9405 149 9390 273 9375 149 9360 273 9345 149 9330 273 9315 149 9300 273 9285 149 9270 273 9255 149 9240 273 9225 149 9210 273 9195 149 9180 273 9165 149 9150 273 9135 149 9120 273 9105 149 9090 273 9075 149 9060 273 9045 149 9030 273 9015 149 9000 273 2012/5/11 381 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No Name 469 G292 470 G294 471 G296 472 G298 473 G300 474 G302 475 G304 476 G306 477 G308 478 G310 479 G312 480 G314 481 G316 482 G318 483 G320 484 G322 485 G324 486 G326 487 G328 488 G330 489 G332 490 G334 491 G336 492 G338 493 G340 494 G342 495 G344 496 G346 497 G348 498 G350 499 G352 500 G354 501 G356 502 G358 503 G360 504 G362 505 G364 506 G366 507 G368 508 G370 509 G372 510 G374 511 G376 512 G378 513 G380 514 G382 515 G384 516 G386 517 G388 518 G390 519 G392 520 G394 X Y 8985 149 8970 273 8955 149 8940 273 8925 149 8910 273 8895 149 8880 273 8865 149 8850 273 8835 149 8820 273 8805 149 8790 273 8775 149 8760 273 8745 149 8730 273 8715 149 8700 273 8685 149 8670 273 8655 149 8640 273 8625 149 8610 273 8595 149 8580 273 8565 149 8550 273 8535 149 8520 273 8505 149 8490 273 8475 149 8460 273 8445 149 8430 273 8415 149 8400 273 8385 149 8370 273 8355 149 8340 273 8325 149 8310 273 8295 149 8280 273 8265 149 8250 273 8235 149 8220 273 Draft Version No Name 521 G396 522 G398 523 G400 524 G402 525 G404 526 G406 527 G408 528 G410 529 G412 530 G414 531 G416 532 G418 533 G420 534 G422 535 G424 536 G426 537 G428 538 G430 539 G432 540 G434 541 G436 542 G438 543 G440 544 G442 545 G444 546 G446 547 G448 548 G450 549 G452 550 G454 551 G456 552 G458 553 G460 554 G462 555 G464 556 G466 557 G468 558 G470 559 G472 560 G474 561 G476 562 G478 563 VCOM 564 VCOM 565 VCOM 566 VCOM 567 S959 568 S958 569 S957 570 S956 571 S955 572 S954 X Y 8205 149 8190 273 8175 149 8160 273 8145 149 8130 273 8115 149 8100 273 8085 149 8070 273 8055 149 8040 273 8025 149 8010 273 7995 149 7980 273 7965 149 7950 273 7935 149 7920 273 7905 149 7890 273 7875 149 7860 273 7845 149 7830 273 7815 149 7800 273 7785 149 7770 273 7755 149 7740 273 7725 149 7710 273 7695 149 7680 273 7665 149 7650 273 7635 149 7620 273 7605 149 7590 273 7575 149 7560 273 7395 149 7380 273 7365 149 7350 273 7335 149 7320 273 7305 149 7290 273 NT35310 No Name X Y 573 S953 7275 149 574 S952 7260 273 575 S951 7245 149 576 S950 7230 273 577 S949 7215 149 578 S948 7200 273 579 S947 7185 149 580 S946 7170 273 581 S945 7155 149 582 S944 7140 273 583 S943 7125 149 584 S942 7110 273 585 S941 7095 149 586 S940 7080 273 587 S939 7065 149 588 S938 7050 273 589 S937 7035 149 590 S936 7020 273 591 S935 7005 149 592 S934 6990 273 593 S933 6975 149 594 S932 6960 273 595 S931 6945 149 596 S930 6930 273 597 S929 6915 149 598 S928 6900 273 599 S927 6885 149 600 S926 6870 273 601 S925 6855 149 602 S924 6840 273 603 S923 6825 149 604 S922 6810 273 605 S921 6795 149 606 S920 6780 273 607 S919 6765 149 608 S918 6750 273 609 S917 6735 149 610 S916 6720 273 611 S915 6705 149 612 S914 6690 273 613 S913 6675 149 614 S912 6660 273 615 S911 6645 149 616 S910 6630 273 617 S909 6615 149 618 S908 6600 273 619 S907 6585 149 620 S906 6570 273 621 S905 6555 149 622 S904 6540 273 623 S903 6525 149 624 S902 6510 273 2012/5/11 382 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No Name 625 S901 626 S900 627 S899 628 S898 629 S897 630 S896 631 S895 632 S894 633 S893 634 S892 635 S891 636 S890 637 S889 638 S888 639 S887 640 S886 641 S885 642 S884 643 S883 644 S882 645 S881 646 S880 647 S879 648 S878 649 S877 650 S876 651 S875 652 S874 653 S873 654 S872 655 S871 656 S870 657 S869 658 S868 659 S867 660 S866 661 S865 662 S864 663 S863 664 S862 665 S861 666 S860 667 S859 668 S858 669 S857 670 S856 671 S855 672 S854 673 S853 674 S852 675 S851 676 S850 X Y 6495 149 6480 273 6465 149 6450 273 6435 149 6420 273 6405 149 6390 273 6375 149 6360 273 6345 149 6330 273 6315 149 6300 273 6285 149 6270 273 6255 149 6240 273 6225 149 6210 273 6195 149 6180 273 6165 149 6150 273 6135 149 6120 273 6105 149 6090 273 6075 149 6060 273 6045 149 6030 273 6015 149 6000 273 5985 149 5970 273 5955 149 5940 273 5925 149 5910 273 5895 149 5880 273 5865 149 5850 273 5835 149 5820 273 5805 149 5790 273 5775 149 5760 273 5745 149 5730 273 Draft Version No Name 677 S849 678 S848 679 S847 680 S846 681 S845 682 S844 683 S843 684 S842 685 S841 686 S840 687 S839 688 S838 689 S837 690 S836 691 S835 692 S834 693 S833 694 S832 695 S831 696 S830 697 S829 698 S828 699 S827 700 S826 701 S825 702 S824 703 S823 704 S822 705 S821 706 S820 707 S819 708 S818 709 S817 710 S816 711 S815 712 S814 713 S813 714 S812 715 S811 716 S810 717 S809 718 S808 719 S807 720 S806 721 S805 722 S804 723 S803 724 S802 725 S801 726 S800 727 S799 728 S798 X Y 5715 149 5700 273 5685 149 5670 273 5655 149 5640 273 5625 149 5610 273 5595 149 5580 273 5565 149 5550 273 5535 149 5520 273 5505 149 5490 273 5475 149 5460 273 5445 149 5430 273 5415 149 5400 273 5385 149 5370 273 5355 149 5340 273 5325 149 5310 273 5295 149 5280 273 5265 149 5250 273 5235 149 5220 273 5205 149 5190 273 5175 149 5160 273 5145 149 5130 273 5115 149 5100 273 5085 149 5070 273 5055 149 5040 273 5025 149 5010 273 4995 149 4980 273 4965 149 4950 273 NT35310 No Name X Y 729 S797 4935 149 730 S796 4920 273 731 S795 4905 149 732 S794 4890 273 733 S793 4875 149 734 S792 4860 273 735 S791 4845 149 736 S790 4830 273 737 S789 4815 149 738 S788 4800 273 739 S787 4785 149 740 S786 4770 273 741 S785 4755 149 742 S784 4740 273 743 S783 4725 149 744 S782 4710 273 745 S781 4695 149 746 S780 4680 273 747 S779 4665 149 748 S778 4650 273 749 S777 4635 149 750 S776 4620 273 751 S775 4605 149 752 S774 4590 273 753 S773 4575 149 754 S772 4560 273 755 S771 4545 149 756 S770 4530 273 757 S769 4515 149 758 S768 4500 273 759 S767 4485 149 760 S766 4470 273 761 S765 4455 149 762 S764 4440 273 763 S763 4425 149 764 S762 4410 273 765 S761 4395 149 766 S760 4380 273 767 S759 4365 149 768 S758 4350 273 769 S757 4335 149 770 S756 4320 273 771 S755 4305 149 772 S754 4290 273 773 S753 4275 149 774 S752 4260 273 775 S751 4245 149 776 S750 4230 273 777 S749 4215 149 778 S748 4200 273 779 S747 4185 149 780 S746 4170 273 2012/5/11 383 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No Name 781 S745 782 S744 783 S743 784 S742 785 S741 786 S740 787 S739 788 S738 789 S737 790 S736 791 S735 792 S734 793 S733 794 S732 795 S731 796 S730 797 S729 798 S728 799 S727 800 S726 801 S725 802 S724 803 S723 804 S722 805 S721 806 S720 807 S719 808 S718 809 S717 810 S716 811 S715 812 S714 813 S713 814 S712 815 S711 816 S710 817 S709 818 S708 819 S707 820 S706 821 S705 822 S704 823 S703 824 S702 825 S701 826 S700 827 S699 828 S698 829 S697 830 S696 831 S695 832 S694 X Y 4155 149 4140 273 4125 149 4110 273 4095 149 4080 273 4065 149 4050 273 4035 149 4020 273 4005 149 3990 273 3975 149 3960 273 3945 149 3930 273 3915 149 3900 273 3885 149 3870 273 3855 149 3840 273 3825 149 3810 273 3795 149 3780 273 3765 149 3750 273 3735 149 3720 273 3705 149 3690 273 3675 149 3660 273 3645 149 3630 273 3615 149 3600 273 3585 149 3570 273 3555 149 3540 273 3525 149 3510 273 3495 149 3480 273 3465 149 3450 273 3435 149 3420 273 3405 149 3390 273 Draft Version No Name 833 S693 834 S692 835 S691 836 S690 837 S689 838 S688 839 S687 840 S686 841 S685 842 S684 843 S683 844 S682 845 S681 846 S680 847 S679 848 S678 849 S677 850 S676 851 S675 852 S674 853 S673 854 S672 855 S671 856 S670 857 S669 858 S668 859 S667 860 S666 861 S665 862 S664 863 S663 864 S662 865 S661 866 S660 867 S659 868 S658 869 S657 870 S656 871 S655 872 S654 873 S653 874 S652 875 S651 876 S650 877 S649 878 S648 879 S647 880 S646 881 S645 882 S644 883 S643 884 S642 X Y 3375 149 3360 273 3345 149 3330 273 3315 149 3300 273 3285 149 3270 273 3255 149 3240 273 3225 149 3210 273 3195 149 3180 273 3165 149 3150 273 3135 149 3120 273 3105 149 3090 273 3075 149 3060 273 3045 149 3030 273 3015 149 3000 273 2985 149 2970 273 2955 149 2940 273 2925 149 2910 273 2895 149 2880 273 2865 149 2850 273 2835 149 2820 273 2805 149 2790 273 2775 149 2760 273 2745 149 2730 273 2715 149 2700 273 2685 149 2670 273 2655 149 2640 273 2625 149 2610 273 NT35310 No Name X Y 885 S641 2595 149 886 S640 2580 273 887 S639 2565 149 888 S638 2550 273 889 S637 2535 149 890 S636 2520 273 891 S635 2505 149 892 S634 2490 273 893 S633 2475 149 894 S632 2460 273 895 S631 2445 149 896 S630 2430 273 897 S629 2415 149 898 S628 2400 273 899 S627 2385 149 900 S626 2370 273 901 S625 2355 149 902 S624 2340 273 903 S623 2325 149 904 S622 2310 273 905 S621 2295 149 906 S620 2280 273 907 S619 2265 149 908 S618 2250 273 909 S617 2235 149 910 S616 2220 273 911 S615 2205 149 912 S614 2190 273 913 S613 2175 149 914 S612 2160 273 915 S611 2145 149 916 S610 2130 273 917 S609 2115 149 918 S608 2100 273 919 S607 2085 149 920 S606 2070 273 921 S605 2055 149 922 S604 2040 273 923 S603 2025 149 924 S602 2010 273 925 S601 1995 149 926 S600 1980 273 927 S599 1965 149 928 S598 1950 273 929 S597 1935 149 930 S596 1920 273 931 S595 1905 149 932 S594 1890 273 933 S593 1875 149 934 S592 1860 273 935 S591 1845 149 936 S590 1830 273 2012/5/11 384 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No Name 937 S589 938 S588 939 S587 940 S586 941 S585 942 S584 943 S583 944 S582 945 S581 946 S580 947 S579 948 S578 949 S577 950 S576 951 S575 952 S574 953 S573 954 S572 955 S571 956 S570 957 S569 958 S568 959 S567 960 S566 961 S565 962 S564 963 S563 964 S562 965 S561 966 S560 967 S559 968 S558 969 S557 970 S556 971 S555 972 S554 973 S553 974 S552 975 S551 976 S550 977 S549 978 S548 979 S547 980 S546 981 S545 982 S544 983 S543 984 S542 985 S541 986 S540 987 S539 988 S538 X Y 1815 149 1800 273 1785 149 1770 273 1755 149 1740 273 1725 149 1710 273 1695 149 1680 273 1665 149 1650 273 1635 149 1620 273 1605 149 1590 273 1575 149 1560 273 1545 149 1530 273 1515 149 1500 273 1485 149 1470 273 1455 149 1440 273 1425 149 1410 273 1395 149 1380 273 1365 149 1350 273 1335 149 1320 273 1305 149 1290 273 1275 149 1260 273 1245 149 1230 273 1215 149 1200 273 1185 149 1170 273 1155 149 1140 273 1125 149 1110 273 1095 149 1080 273 1065 149 1050 273 Draft Version No 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 Name S537 S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 X Y 1035 149 1020 273 1005 149 990 273 975 149 960 273 945 149 930 273 915 149 900 273 885 149 870 273 855 149 840 273 825 149 810 273 795 149 780 273 765 149 750 273 735 149 720 273 705 149 690 273 675 149 660 273 645 149 630 273 615 149 600 273 585 149 570 273 555 149 540 273 525 149 510 273 495 149 480 273 465 149 450 273 435 149 420 273 405 149 390 273 375 149 360 273 345 149 330 273 315 149 300 273 285 149 270 273 NT35310 No 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 Name S485 S484 S483 S482 S481 S480 DUMMY DUMMY DUMMY DUMMY S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 X Y 255 149 240 273 225 149 210 273 195 149 180 273 165 149 150 273 -150 273 -165 149 -180 273 -195 149 -210 273 -225 149 -240 273 -255 149 -270 273 -285 149 -300 273 -315 149 -330 273 -345 149 -360 273 -375 149 -390 273 -405 149 -420 273 -435 149 -450 273 -465 149 -480 273 -495 149 -510 273 -525 149 -540 273 -555 149 -570 273 -585 149 -600 273 -615 149 -630 273 -645 149 -660 273 -675 149 -690 273 -705 149 -720 273 -735 149 -750 273 -765 149 -780 273 -795 149 2012/5/11 385 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 Name S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 X Y -810 273 -825 149 -840 273 -855 149 -870 273 -885 149 -900 273 -915 149 -930 273 -945 149 -960 273 -975 149 -990 273 -1005 149 -1020 273 -1035 149 -1050 273 -1065 149 -1080 273 -1095 149 -1110 273 -1125 149 -1140 273 -1155 149 -1170 273 -1185 149 -1200 273 -1215 149 -1230 273 -1245 149 -1260 273 -1275 149 -1290 273 -1305 149 -1320 273 -1335 149 -1350 273 -1365 149 -1380 273 -1395 149 -1410 273 -1425 149 -1440 273 -1455 149 -1470 273 -1485 149 -1500 273 -1515 149 -1530 273 -1545 149 -1560 273 -1575 149 Draft Version No 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 Name S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 X Y -1590 273 -1605 149 -1620 273 -1635 149 -1650 273 -1665 149 -1680 273 -1695 149 -1710 273 -1725 149 -1740 273 -1755 149 -1770 273 -1785 149 -1800 273 -1815 149 -1830 273 -1845 149 -1860 273 -1875 149 -1890 273 -1905 149 -1920 273 -1935 149 -1950 273 -1965 149 -1980 273 -1995 149 -2010 273 -2025 149 -2040 273 -2055 149 -2070 273 -2085 149 -2100 273 -2115 149 -2130 273 -2145 149 -2160 273 -2175 149 -2190 273 -2205 149 -2220 273 -2235 149 -2250 273 -2265 149 -2280 273 -2295 149 -2310 273 -2325 149 -2340 273 -2355 149 NT35310 No 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 Name S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 X Y -2370 273 -2385 149 -2400 273 -2415 149 -2430 273 -2445 149 -2460 273 -2475 149 -2490 273 -2505 149 -2520 273 -2535 149 -2550 273 -2565 149 -2580 273 -2595 149 -2610 273 -2625 149 -2640 273 -2655 149 -2670 273 -2685 149 -2700 273 -2715 149 -2730 273 -2745 149 -2760 273 -2775 149 -2790 273 -2805 149 -2820 273 -2835 149 -2850 273 -2865 149 -2880 273 -2895 149 -2910 273 -2925 149 -2940 273 -2955 149 -2970 273 -2985 149 -3000 273 -3015 149 -3030 273 -3045 149 -3060 273 -3075 149 -3090 273 -3105 149 -3120 273 -3135 149 2012/5/11 386 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 Name S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 X Y -3150 273 -3165 149 -3180 273 -3195 149 -3210 273 -3225 149 -3240 273 -3255 149 -3270 273 -3285 149 -3300 273 -3315 149 -3330 273 -3345 149 -3360 273 -3375 149 -3390 273 -3405 149 -3420 273 -3435 149 -3450 273 -3465 149 -3480 273 -3495 149 -3510 273 -3525 149 -3540 273 -3555 149 -3570 273 -3585 149 -3600 273 -3615 149 -3630 273 -3645 149 -3660 273 -3675 149 -3690 273 -3705 149 -3720 273 -3735 149 -3750 273 -3765 149 -3780 273 -3795 149 -3810 273 -3825 149 -3840 273 -3855 149 -3870 273 -3885 149 -3900 273 -3915 149 Draft Version No 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 Name S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 X Y -3930 273 -3945 149 -3960 273 -3975 149 -3990 273 -4005 149 -4020 273 -4035 149 -4050 273 -4065 149 -4080 273 -4095 149 -4110 273 -4125 149 -4140 273 -4155 149 -4170 273 -4185 149 -4200 273 -4215 149 -4230 273 -4245 149 -4260 273 -4275 149 -4290 273 -4305 149 -4320 273 -4335 149 -4350 273 -4365 149 -4380 273 -4395 149 -4410 273 -4425 149 -4440 273 -4455 149 -4470 273 -4485 149 -4500 273 -4515 149 -4530 273 -4545 149 -4560 273 -4575 149 -4590 273 -4605 149 -4620 273 -4635 149 -4650 273 -4665 149 -4680 273 -4695 149 NT35310 No 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 Name S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 X Y -4710 273 -4725 149 -4740 273 -4755 149 -4770 273 -4785 149 -4800 273 -4815 149 -4830 273 -4845 149 -4860 273 -4875 149 -4890 273 -4905 149 -4920 273 -4935 149 -4950 273 -4965 149 -4980 273 -4995 149 -5010 273 -5025 149 -5040 273 -5055 149 -5070 273 -5085 149 -5100 273 -5115 149 -5130 273 -5145 149 -5160 273 -5175 149 -5190 273 -5205 149 -5220 273 -5235 149 -5250 273 -5265 149 -5280 273 -5295 149 -5310 273 -5325 149 -5340 273 -5355 149 -5370 273 -5385 149 -5400 273 -5415 149 -5430 273 -5445 149 -5460 273 -5475 149 2012/5/11 387 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 Name S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 X Y -5490 273 -5505 149 -5520 273 -5535 149 -5550 273 -5565 149 -5580 273 -5595 149 -5610 273 -5625 149 -5640 273 -5655 149 -5670 273 -5685 149 -5700 273 -5715 149 -5730 273 -5745 149 -5760 273 -5775 149 -5790 273 -5805 149 -5820 273 -5835 149 -5850 273 -5865 149 -5880 273 -5895 149 -5910 273 -5925 149 -5940 273 -5955 149 -5970 273 -5985 149 -6000 273 -6015 149 -6030 273 -6045 149 -6060 273 -6075 149 -6090 273 -6105 149 -6120 273 -6135 149 -6150 273 -6165 149 -6180 273 -6195 149 -6210 273 -6225 149 -6240 273 -6255 149 Draft Version No 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 Name S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 X Y -6270 273 -6285 149 -6300 273 -6315 149 -6330 273 -6345 149 -6360 273 -6375 149 -6390 273 -6405 149 -6420 273 -6435 149 -6450 273 -6465 149 -6480 273 -6495 149 -6510 273 -6525 149 -6540 273 -6555 149 -6570 273 -6585 149 -6600 273 -6615 149 -6630 273 -6645 149 -6660 273 -6675 149 -6690 273 -6705 149 -6720 273 -6735 149 -6750 273 -6765 149 -6780 273 -6795 149 -6810 273 -6825 149 -6840 273 -6855 149 -6870 273 -6885 149 -6900 273 -6915 149 -6930 273 -6945 149 -6960 273 -6975 149 -6990 273 -7005 149 -7020 273 -7035 149 NT35310 No 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 Name S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VCOM VCOM VCOM VCOM G479 G477 G475 G473 G471 G469 G467 G465 G463 G461 G459 G457 G455 G453 G451 G449 G447 G445 G443 G441 G439 G437 G435 G433 G431 G429 X Y -7050 273 -7065 149 -7080 273 -7095 149 -7110 273 -7125 149 -7140 273 -7155 149 -7170 273 -7185 149 -7200 273 -7215 149 -7230 273 -7245 149 -7260 273 -7275 149 -7290 273 -7305 149 -7320 273 -7335 149 -7350 273 -7365 149 -7380 273 -7395 149 -7560 273 -7575 149 -7590 273 -7605 149 -7620 273 -7635 149 -7650 273 -7665 149 -7680 273 -7695 149 -7710 273 -7725 149 -7740 273 -7755 149 -7770 273 -7785 149 -7800 273 -7815 149 -7830 273 -7845 149 -7860 273 -7875 149 -7890 273 -7905 149 -7920 273 -7935 149 -7950 273 -7965 149 2012/5/11 388 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 Name G427 G425 G423 G421 G419 G417 G415 G413 G411 G409 G407 G405 G403 G401 G399 G397 G395 G393 G391 G389 G387 G385 G383 G381 G379 G377 G375 G373 G371 G369 G367 G365 G363 G361 G359 G357 G355 G353 G351 G349 G347 G345 G343 G341 G339 G337 G335 G333 G331 G329 G327 G325 X Y -7980 273 -7995 149 -8010 273 -8025 149 -8040 273 -8055 149 -8070 273 -8085 149 -8100 273 -8115 149 -8130 273 -8145 149 -8160 273 -8175 149 -8190 273 -8205 149 -8220 273 -8235 149 -8250 273 -8265 149 -8280 273 -8295 149 -8310 273 -8325 149 -8340 273 -8355 149 -8370 273 -8385 149 -8400 273 -8415 149 -8430 273 -8445 149 -8460 273 -8475 149 -8490 273 -8505 149 -8520 273 -8535 149 -8550 273 -8565 149 -8580 273 -8595 149 -8610 273 -8625 149 -8640 273 -8655 149 -8670 273 -8685 149 -8700 273 -8715 149 -8730 273 -8745 149 Draft Version No 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 Name G323 G321 G319 G317 G315 G313 G311 G309 G307 G305 G303 G301 G299 G297 G295 G293 G291 G289 G287 G285 G283 G281 G279 G277 G275 G273 G271 G269 G267 G265 G263 G261 G259 G257 G255 G253 G251 G249 G247 G245 G243 G241 G239 G237 G235 G233 G231 G229 G227 G225 G223 G221 X Y -8760 273 -8775 149 -8790 273 -8805 149 -8820 273 -8835 149 -8850 273 -8865 149 -8880 273 -8895 149 -8910 273 -8925 149 -8940 273 -8955 149 -8970 273 -8985 149 -9000 273 -9015 149 -9030 273 -9045 149 -9060 273 -9075 149 -9090 273 -9105 149 -9120 273 -9135 149 -9150 273 -9165 149 -9180 273 -9195 149 -9210 273 -9225 149 -9240 273 -9255 149 -9270 273 -9285 149 -9300 273 -9315 149 -9330 273 -9345 149 -9360 273 -9375 149 -9390 273 -9405 149 -9420 273 -9435 149 -9450 273 -9465 149 -9480 273 -9495 149 -9510 273 -9525 149 NT35310 No 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 Name G219 G217 G215 G213 G211 G209 G207 G205 G203 G201 G199 G197 G195 G193 G191 G189 G187 G185 G183 G181 G179 G177 G175 G173 G171 G169 G167 G165 G163 G161 G159 G157 G155 G153 G151 G149 G147 G145 G143 G141 G139 G137 G135 G133 G131 G129 G127 G125 G123 G121 G119 G117 X Y -9540 273 -9555 149 -9570 273 -9585 149 -9600 273 -9615 149 -9630 273 -9645 149 -9660 273 -9675 149 -9690 273 -9705 149 -9720 273 -9735 149 -9750 273 -9765 149 -9780 273 -9795 149 -9810 273 -9825 149 -9840 273 -9855 149 -9870 273 -9885 149 -9900 273 -9915 149 -9930 273 -9945 149 -9960 273 -9975 149 -9990 273 -10005 149 -10020 273 -10035 149 -10050 273 -10065 149 -10080 273 -10095 149 -10110 273 -10125 149 -10140 273 -10155 149 -10170 273 -10185 149 -10200 273 -10215 149 -10230 273 -10245 149 -10260 273 -10275 149 -10290 273 -10305 149 2012/5/11 389 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. No 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 Name G115 G113 G111 G109 G107 G105 G103 G101 G99 G97 G95 G93 G91 G89 G87 G85 G83 G81 G79 G77 G75 G73 G71 G69 G67 G65 G63 G61 G59 G57 G55 G53 G51 G49 G47 G45 G43 G41 G39 G37 G35 G33 G31 G29 G27 G25 G23 G21 G19 G17 G15 G13 X Y -10320 273 -10335 149 -10350 273 -10365 149 -10380 273 -10395 149 -10410 273 -10425 149 -10440 273 -10455 149 -10470 273 -10485 149 -10500 273 -10515 149 -10530 273 -10545 149 -10560 273 -10575 149 -10590 273 -10605 149 -10620 273 -10635 149 -10650 273 -10665 149 -10680 273 -10695 149 -10710 273 -10725 149 -10740 273 -10755 149 -10770 273 -10785 149 -10800 273 -10815 149 -10830 273 -10845 149 -10860 273 -10875 149 -10890 273 -10905 149 -10920 273 -10935 149 -10950 273 -10965 149 -10980 273 -10995 149 -11010 273 -11025 149 -11040 273 -11055 149 -11070 273 -11085 149 Draft Version No 1769 1770 1771 1772 1773 1774 1775 1776 Name G11 G9 G7 G5 G3 G1 VCOM VCOM ALK_L ALK_R X -11100 -11115 -11130 -11145 -11160 -11175 -11190 -11205 -11300 11300 Y 273 149 273 149 273 149 273 149 -285.5 -285.5 NT35310 No Name X Y 2012/5/11 390 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information. 9.4 SELECTION GUIDE Draft Version Pad No. NT35310H-DP01 NT35310H-DP 16 HSSI_D0_N HSSI_CLK_P 17 HSSI_D0_N HSSI_CLK_P 18 HSSI_D0_P HSSI_CLK_N 19 HSSI_D0_P HSSI_CLK_N 20 HSSI_CLK_N HSSI_D0_P 21 HSSI_CLK_N HSSI_D0_P 22 HSSI_CLK_P HSSI_D0_N 23 HSSI_CLK_P HSSI_D0_N NT35310 2012/5/11 391 Version 0.04 With respect to the information represented in this document, NOVATek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, and non-infringement, nor assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any such information.

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