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4520 CMOS 双二进制加法计数器.pdf

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标签: 4520CMOS双二进制加法计数器

4520 CMOS 双二进制加法计数器.pdf

CD4518BMS, CD4520BMS December 1992 CMOS Dual Up Counters Features Pinout • High Voltage Types (20V Rating) • CD4518BMS Dual BCD Up Counter • CD4520BMS Dual Binary Up Counter • Medium Speed Operation - 6MHz Typical Clock Frequency at 10V • Positive or Negative Edge Triggering • Synchronous Internal Carry Propagation • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD4518BMS, CD4520BMS TOP VIEW CLOCK A 1 ENABLE A 2 Q1A 3 Q2A 4 Q3A 5 Q4A 6 RESET A 7 VSS 8 16 VDD 15 RESET B 14 Q4B 13 Q3B 12 Q2B 11 Q1B 10 ENABLE B 9 CLOCK B Functional Diagram Applications • Multistage Synchronous Counting • Multistage Ripple Counting • Frequency Dividers Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. CLOCK A 1 ENABLE A 2 RESET A 7 CLOCK B 9 ENABLE B 10 RESET B 15 ÷10/÷16 C R 3 Q1A 4 Q2A 5 Q3A 6 Q4A ÷10/÷16 C R 11 Q1B 12 Q2B 13 Q3B 14 Q4B The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4518B Only H4S H1F *H6P †H6W †CD4520B Only VSS = 8 VDD = 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1206 File Number 3342 Specifications CD4518BMS, CD4520BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja Ceramic DIP and FRIT Package . . . . . 80oC/W θjc 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE LIMITS MIN MAX UNITS Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 VDD = 20V, VIN = VDD or GND 7 +25oC +25oC VOH > VOL < V VDD/2 VDD/2 VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit implemented. is 0.050V max. 2. Go/No Go test with limits applied to inputs. 7-1207 Specifications CD4518BMS, CD4520BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Output Propagation Delay Reset to Ouput Transition Time (Note 2) Maximum Clock Input Frequency SYMBOL CONDITIONS (NOTE 1, 2) TPHL1 VDD = 5V, VIN = VDD or GND TPLH1 TPHL2 VDD = 5V, VIN = VDD or GND TTHL TTLH FCL VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND GROUP A SUBGROUPS 9 10, 11 9 10, 11 9 10, 11 9 10, 11 TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. LIMITS MIN MAX - 560 - 756 - 650 - 878 - 200 - 270 1.5 - 1.11 - UNITS ns ns ns ns ns ns MHz MHz TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL CONDITIONS IDD VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VDD = 5V, No Load VOL VDD = 10V, No Load VOH VDD = 5V, No Load VOH VDD = 10V, No Load IOL5 VDD = 5V, VOUT = 0.4V Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low Input Voltage High VIL VDD = 10V, VOH > 9V, VOL < 1V VIH VDD = 10V, VOH > 9V, VOL < 1V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC LIMITS MIN MAX - 5 - 150 - 10 - 300 - 10 - 600 - 50 - 50 4.95 - 9.95 - 0.36 - 0.64 - 0.9 - 1.6 - 2.4 - 4.2 - - -0.36 - -0.64 - -1.15 - -2.0 - -0.9 - -1.6 - -2.4 - -4.2 - 3 +7 - UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V 7-1208 Specifications CD4518BMS, CD4520BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS Propagation Delay Clock to Output TPHL1 VDD = 10V TPLH1 VDD = 15V Propagation Delay Reset to Output TPHL2 VDD = 10V VDD = 15V Transition Time TTHL TTLH VDD = 10V VDD = 15V Maximum Clock Input Frequency FCL VDD = 10V VDD = 15V Maximum Clock Rise and Fall Time TRCL VDD = 5V TFCL VDD = 10V VDD = 15V Minimum Enable Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE MIN +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC 3 +25oC 4 +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX 230 160 225 170 100 80 15 5 5 400 200 140 250 110 80 200 100 70 7.5 UNITS ns ns ns ns ns ns MHz MHz µs µs µs ns ns ns ns ns ns ns ns ns pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC LIMITS MIN MAX - 25 -2.8 -0.2 - ±1 1, 4 +25oC 0.2 2.8 1, 4 +25oC - ±1 1 1, 2, 3, 4 +25oC +25oC 3. See Table 2 for +25oC limit. 4. Read and Record VOH > VOL < VDD/2 VDD/2 - 1.35 x +25oC Limit UNITS µA V V V V V ns 7-1209 Specifications CD4518BMS, CD4520BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD TEST PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 READ AND RECORD PRE-IRRAD POST-IRRAD 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Static Burn-In 1 3-6, 11-14 1, 2, 7-10, 15 16 Note 1 Static Burn-In 2 Note 1 3-6, 11-14 8 1, 2, 7, 9, 10, 15, 16 Dynamic Burn- - In Note 1 7, 8, 15 2, 10, 16 3-6, 11-14 1, 9 Irradiation Note 2 3-6, 11-14 8 1, 2, 7, 9, 10, 15, 16 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1210 Logic Diagrams VDD CD4518BMS, CD4520BMS Q1 3/11 Q2 4/12 Q3 5/13 Q4 6/14 * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK RESET * 7/15 VSS ENABLE * 2/10 CLOCK * 1/9 DQ CQ R DQ CQ R DQ CQ R DQ CQ R FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS VDD Q1 3/11 Q2 4/12 Q3 5/13 Q4 6/14 * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS RESET * 7/15 DQ CQ R DQ CQ R DQ CQ R DQ CQ R ENABLE * 2/10 CLOCK * 1/9 FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS CLOCK 0 X 1 X X = Don’t Care TRUTH TABLE ENABLE RESET 1 0 0 X 0 0 0 0 0 X 1 1 ≡ High State 0 ≡ Low State ACTION Increment Counter Increment Counter No Change No Change No Change No Change Q1 thru Q4 = 0 7-1211 CD4518BMS, CD4520BMS Typical Performance Curves AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10 -15 -10V -20 -25 -15V -30 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) PROPAGATION DELAY TIME (tPLH, tPHL) (ns) FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 350 AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 250 200 150 10V 100 15V 50 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 100 FIGURE 7. TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, CLOCK OR ENABLE TO OUTPUT PROPAGATION DELAY TIME (tPHL, tPLH) (ns) FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 350 AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 250 200 150 10V 100 15V 50 0 10 20 30 40 50 60 70 80 90 100 110 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE, RESET TO OUTPUT 7-1212 CD4518BMS, CD4520BMS Typical Performance Curves TRANSITION TIME (tTHL, tTLH) (ns) POWER DISSIPATION /CONVERTER (PD) (µW) MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz) AMBIENT TEMPERATURE (TA) = +25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 AMBIENT TEMPERATURE (TA) = +25oC 15 LOAD CAPACITANCE (CL) = 50PF 10 100 10V 5 15V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY vs SUPPLY VOLTAGE Timing Diagrams 104 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 103 8 6 4 2 102 8 6 4 2 10 8 6 4 2 1 2 0.1 10V 10V 5V CL = 50pF CL = 15pF AMBIENT TEMPERATURE (TA) = +25oC 4 68 2 4 68 2 4 68 2 4 68 2 4 68 1 10 102 103 104 FREQUENCY (f) (kHz) FIGURE 11. TYPICAL POWER DISSIPATION CHARACTERISTICS CLOCK ENABLE RESET Q1 Q2 CD4518BMS Q3 Q4 Q1 Q2 CD4520BMS Q3 Q4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS 7-1213 CD4518BMS, CD4520BMS CLOCK INPUT VDD 1 2 7 CLOCK ENABLE RESET A A A 9 10 15 CLOCK ENABLE RESET B B B Q1A Q2A Q3A Q4A 3456 Q1B Q2B Q3B Q4B 11 12 13 14 CD4518BMS/20BMS 1 2 7 CLOCK ENABLE RESET A A A 9 10 15 CLOCK ENABLE RESET B B B Q1A Q2A Q3A Q4A 3456 Q1B Q2B Q3B Q4B 11 12 13 14 CD4518BMS/20BMS FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING CLOCK* INPUT CD4071 CD4071 1 2 3 CLOCK ENABLE RESET A A A 9 10 15 CLOCK ENABLE RESET B B B Q1A Q2A Q3A Q4A 3456 CD4520BMS CD4012A Q1B Q2B Q3B Q4B 11 12 13 14 CD4012A 1 2 3 CLOCK ENABLE RESET A A A 9 10 15 CLOCK ENABLE RESET B B B Q1A Q2A Q3A Q4A 3456 CD4520BMS CD4012A Q1B Q2B Q3B Q4B 11 12 13 14 CD4520BMS * For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the output driver stage for the estimated capacitive load. FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING 7-1214 CD4518BMS, CD4520BMS Chip Dimensions and Pad Layouts CD4518BMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). CD4520BMS METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1215
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