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H High CMR, High Speed TTL Compatible Optocouplers Technical Data 6N137 HCNW137 HCNW2601 HCNW2611 HCPL-0600 HCPL-0601 HCPL-0611 HCPL-0630 HCPL-0631 HCPL-0661 HCPL-2601 HCPL-2611 HCPL-2630 HCPL-2631 HCPL-4661 Features • 5 kV/µs Minimum Common Mode Rejection (CMR) at VCM = 50 V for HCPL-X601/ X631, HCNW2601 and 10 kV/µs Minimum CMR at VCM = 1000 V for HCPLX611/X661, HCNW2611 • High Speed: 10 MBd Typical • LSTTL/TTL Compatible • Low Input Current Capability: 5 mA • Guaranteed ac and dc Performance over Temperature: -40°C to +85°C • Available in 8-Pin DIP, SOIC-8, Widebody Packages • Strobable Output (Single Channel Products Only) • Safety Approval UL Recognized - 2500 V rms for 1 minute and 5000 V rms* for 1 minute per UL1577 CSA Approved VDE 0884 Approved with VIORM = 630 V peak for HCPL-2611 Option 060 and VIORM = 1414 V peak for HCNW137/26X1 BSI Certified (HCNW137/26X1 Only) • MIL-STD-1772 Version Available (HCPL-56XX/ 66XX) Applications • Isolated Line Receiver • Computer-Peripheral Interfaces • Microprocessor System Interfaces • Digital Isolation for A/D, D/A Conversion • Switching Power Supply • Instrument Input/Output Isolation • Ground Loop Elimination • Pulse Transformer Replacement Functional Diagram 6N137, HCPL-2601/2611 HCPL-0600/0601/0611 HCNW137/2601/2611 NC 1 8 VCC ANODE 2 7 VE CATHODE 3 6 VO NC 4 SHIELD 5 GND TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H • Power Transistor Isolation in Motor Drives • Isolation of High Speed Logic Systems Description The 6N137, HCPL-26XX/06XX/ 4661, HCNW137/26X1 are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is HCPL-2630/2631/4661 HCPL-0630/0631/0661 ANODE 1 1 8 VCC CATHODE 1 2 7 VO1 CATHODE 2 3 6 VO2 ANODE 2 4 5 GND SHIELD TRUTH TABLE (POSITIVE LOGIC) LED ON OFF OUTPUT L H *5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only. A 0.1 µF bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1-146 5965-3594E an open collector Schottkyclamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/µs for the HCPL-X601/X631 and HCNW2601, and 10,000 V/µs for the HCPL-X611/X661 and HCNW2611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to +85°C allowing troublefree system performance. The 6N137, HCPL-26XX, HCPL06XX, HCPL-4661, HCNW137, and HCNW26X1 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. Selection Guide Minimum CMR dV/dt VCM (V/µs) (V) Input OnCurrent (mA) Output Enable NA NA 5 YES NO 5,000 50 YES NO 10,000 1,000 YES NO 1,000 50 YES 3, 500 300 YES 1,000 50 3 YES NO 1,000[2] 1,000 YES NO 1,000 50 12.5 [3] 8-Pin DIP (300 Mil) Single Channel Package 6N137 HCPL-2601 HCPL-2611 HCPL-2602[1] HCPL-2612[1] HCPL-261A[1] HCPL-261N[1] Dual Channel Package HCPL-2630 HCPL-2631 HCPL-4661 HCPL-263A[1] HCPL-263N[1] Small-Outline SO-8 Widebody (400 Mil) Single Channel Package HCPL-0600 HCPL-0601 HCPL-0611 Dual Channel Package HCPL-0630 HCPL-0631 HCPL-0661 Single Channel Package HCNW137 HCNW2601 HCNW2611 Hermetic Single and Dual Channel Packages HCPL-061A[1] HCPL-063A[1] HCPL-061N[1] HCPL-063N[1] HCPL-193X[1] HCPL-56XX[1] HCPL-66XX[1] Notes: 1. Technical data are on separate HP publications. 2. 15 kV/µs with VCM = 1 kV can be achieved using HP application circuit. 3. Enable is available for single channel products only, except for HCPL-193X devices. 1-147 Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-2611#XXX 020 = 5000 V rms/1 minute UL Rating Option* 060 = VDE 0884 VIORM = 630 Vpeak Option** 300 = Gull Wing Surface Mount Option† 500 = Tape and Reel Packaging Option Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor for information. *For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only. **For HCPL-2611 only. Combination of Option 020 and Option 060 is not available. †Gull wing surface mount option applies to through hole parts only. Schematic 6N137, HCPL-2601/2611 HCPL-0600/0601/0611 IF HCNW137, HCNW2601/2611 2+ ICC IO 8 VCC 6 VO VF – 3 SHIELD IE 7 VE USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5). GND 5 1 IF1 + VF1 – 2 3 IF2 – VF2 + 4 HCPL-2630/2631/4661 HCPL-0630/0631/0661 SHIELD SHIELD ICC 8 VCC IO1 7 VO1 IO2 6 VO2 GND 5 1-148 Package Outline Drawings 8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661) TYPE NUMBER 1.19 (0.047) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 87 65 HP XXXXZ YYWW UR 12 34 OPTION CODE* DATE CODE UL RECOGNITION 1.78 (0.070) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 6.35 ± 0.25 (0.250 ± 0.010) 4.70 (0.185) MAX. 5° TYP. 0.254 + 0.076 - 0.051 (0.010+- 0.003) 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.010) **JEDEC Registered Data (for 6N137 only). DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 8-pin DIP Package with Gull Wing Surface Mount Option 300 (6N137, HCPL-2601/11/30/31, HCPL-4661) 1.19 (0.047) MAX. 9.65 ± 0.25 (0.380 ± 0.010) PAD LOCATION (FOR REFERENCE ONLY) 1.016 (0.040) 1.194 (0.047) 8 7 6 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 4 (40..812960)TYP. 9.398 (0.370) 9.906 (0.390) 1.194 (0.047) 1.778 (0.070) 0.381 (0.015) 0.635 (0.025) 1.780 (0.070) MAX. (04..11695)MAX. 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) 0.254 + - 0.076 0.051 (0.010+- 0.003) 0.002) 1.080 ± 0.320 (0.043 ± 0.013) 2.54 (0.100) BSC 0.635 ± 0.130 (0.025 ± 0.005) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 0.635 ± 0.25 (0.025 ± 0.010) 12° NOM. 1-149 Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61) 8765 3.937 ± 0.127 (0.155 ± 0.005) XXX YWW 1234 5.842 ± 0.203 (0.236 ± 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE 0.381 ± 0.076 (0.016 ± 0.003) 1.270 BSG (0.050) 5.080 ± 0.127 (0.200 ± 0.005) 7° 45° X 0.432 (0.017) 3.175 ± 0.127 (0.125 ± 0.005) 1.524 (0.060) 0.228 ± 0.025 (0.009 ± 0.001) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 0.152 ± 0.051 (0.006 ± 0.002) 0.305 MIN. (0.012) 8-Pin Widebody DIP Package (HCNW137, HCNW2601/11) 11.15 ± 0.15 (0.442 ± 0.006) 8 7 6 5 HP HCNWXXXX YYWW 1 2 3 4 TYPE NUMBER DATE CODE 1.55 (0.061) MAX. 11.00 (0.433) MAX. 9.00 ± 0.15 (0.354 ± 0.006) 10.16 (0.400) TYP. 7° TYP. (05.2.1001)MAX. 0.254 + 0.076 - 0.0051 (0.010+- 0.003) 0.002) 2.54 (0.100) TYP. 1.78 ± 0.15 (0.070 ± 0.006) 3.10 (0.122) 3.90 (0.154) 0.51 (0.021) MIN. 0.40 (0.016) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES). 1-150 8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW137, HCNW2601/11) 11.15 ± 0.15 (0.442 ± 0.006) PAD LOCATION (FOR REFERENCE ONLY) 8 7 6 5 9.00 ± 0.15 (0.354 ± 0.006) 1 2 3 4 (06.2.1452)TYP. 12.30 ± 0.30 (0.484 ± 0.012) 1.55 (0.061) MAX. (04..10508)MAX. 1.3 (0.051) 0.9 (0.035) 12.30 ± 0.30 (0.484 ± 0.012) 11.00 (0.433) MAX. 1.78 ± 0.15 (0.070 ± 0.006) 2.54 (0.100) BSC 0.75 ± 0.25 (0.030 ± 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 1.00 ± 0.15 (0.039 ± 0.006) + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 7° NOM. Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount Option 300 Parts) TEMPERATURE – °C 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 ∆T = 115°C, 0.3°C/SEC ∆T = 100°C, 1.5°C/SEC 1 23 4 5 6 7 8 TIME – MINUTES ∆T = 145°C, 1°C/SEC 9 10 11 12 Note: Use of nonchlorine activated fluxes is highly recommended. 1-151 Regulatory Information The 6N137, HCPL-26XX/06XX/ 46XX, and HCNW137/26XX have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92. (HCPL-2611 Option 060 and HCNW137/26X1 only) BSI Certification according to BS415:1994 (BS EN60065:1994), BS7002:1992 (BS EN60950:1992) and EN41003:1993 for Class II applications. (HCNW137/26X1 only) Insulation and Safety Related Specifications Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Symbol L(101) L(102) 8-pin DIP (300 Mil) Value 7.1 7.4 0.08 SO-8 Value 4.9 4.8 0.08 Widebody (400 Mil) Value Units 9.6 mm 10.0 mm 1.0 mm Minimum Internal Tracking (Internal Creepage) Tracking Resistance CTI (Comparative Tracking Index) Isolation Group NA NA 4.0 mm 200 200 200 Volts IIIa IIIa IIIa Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Measured from input terminals to output terminals, along internal cavity. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802. 1-152 VDE 0884 Insulation Related Characteristics (HCPL-2611 Option 060 Only) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic Units VIORM VPR I-IV I-III 55/85/21 2 630 1181 V peak V peak VPR 945 V peak VIOTM 6000 V peak TS IS,INPUT PS,OUTPUT RS 175 230 600 ≥ 109 °C mA mW Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only) Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 600 V rms for rated mains voltage ≤ 1000 V rms Climatic Classification (DIN IEC 68 part 1) I-IV I-III 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VIORM VPR 1414 2651 Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V VPR VIOTM 2121 8000 TS IS,INPUT PS,OUTPUT RS 150 400 700 ≥ 109 Units V peak V peak V peak V peak °C mA mW Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. 1-153 Absolute Maximum Ratings* (No Derating Required up to 85°C) Parameter Symbol Package** Min. Max. Units Storage Temperature Operating Temperature† Average Forward Input Current TS -55 125 °C TA - 40 85 °C IF Single 8-Pin DIP Single SO-8 20 mA Widebody Dual 8-Pin DIP 15 Dual SO-8 Reverse Input Voltage VR 8-Pin DIP, SO-8 Widebody 5 V 3 Input Power Dissipation Supply Voltage (1 Minute Maximum) PI Widebody VCC 40 mW 7 V Enable Input Voltage (Not to Exceed VCC by more than 500 mV) VE Single 8-Pin DIP Single SO-8 Widebody VCC + 0.5 V Enable Input Current IE Output Collector Current IO Output Collector Voltage VO (Selection for Higher Output Voltages up to 20 V is Available.) 5 mA 50 mA 7 V Output Collector Power Dissipation PO Single 8-Pin DIP Single SO-8 Widebody 85 mW Dual 8-Pin DIP 60 Dual SO-8 Lead Solder Temperature (Through Hole Parts Only) TLS 8-Pin DIP 260°C for 10 sec., 1.6 mm below seating plane Widebody 260°C for 10 sec., up to seating plane Solder Reflow Temperature Profile (Surface Mount Parts Only) SO-8 and Option 300 See Package Outline Drawings section Note 2 1, 3 1 1 1 1, 4 *JEDEC Registered Data (for 6N137 only). **Ratings apply to all devices except otherwise noted in the Package column. †0°C to 70°C on JEDEC Registration. Recommended Operating Conditions Parameter Input Current, Low Level Input Current, High Level[1] Power Supply Voltage Low Level Enable Voltage† High Level Enable Voltage† Operating Temperature Fan Out (at RL = 1 kΩ)[1] Output Pull-up Resistor Symbol IFL* IFH** VCC VEL VEH TA N RL Min. 0 5 4.5 0 2.0 -40 330 Max. 250 15 5.5 0.8 VCC 85 5 4k Units µA mA V V V °C TTL Loads Ω *The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts. **The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband. †For single channel products only. 1-154 Electrical Specifications Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V, TA = 25°C. All enable test conditions apply to single channel products only. See note 5. Parameter High Level Output Current Input Threshold Current Low Level Output Voltage High Level Supply Current Sym. IOH* Package All ITH VOL* ICCH Single Channel Widebody Dual Channel 8-Pin DIP SO-8 Widebody Single Channel Dual Channel Min. Typ. 5.5 2.0 2.5 0.35 0.4 7.0 6.5 10 Max. 100 5.0 0.6 10.0* 15 Units µA mA V mA Test Conditions VCC = 5.5 V, VE = 2.0 V, VO = 5.5 V, IF = 250 µA VCC = 5.5 V, VE = 2.0 V, VO = 0.6 V, IOL (Sinking) = 13 mA VCC = 5.5 V, VE = 2.0 V, IF = 5 mA, IOL (Sinking) = 13 mA VE = 0.5 V VE = VCC Both Channels VCC = 5.5 V IF = 0 mA Fig. 1 2, 3 2, 3, 4, 5 Note 1, 6, 19 19 1, 19 7 Low Level Supply Current ICCL Single Channel Dual Channel 9.0 13.0* mA VE = 0.5 V VCC = 5.5 V 8 8.5 VE = VCC IF = 10 mA 13 21 Both Channels High Level Enable IEH Single Channel Current -0.7 -1.6 mA VCC = 5.5 V, VE = 2.0 V Low Level Enable IEL* Current -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V 9 High Level Enable VEH 2.0 V 19 Voltage Low Level Enable VEL Voltage Input Forward VF Voltage 8-Pin DIP SO-8 Widebody 0.8 V 1.4 1.5 1.75* V TA = 25°C IF = 10 mA 6, 7 1 1.3 1.80 1.25 1.64 1.85 TA = 25°C 1.2 2.05 Input Reverse Breakdown Voltage Input Diode Temperature Coefficient BVR* ∆VF / ∆TA 8-Pin DIP SO-8 Widebody 8-Pin DIP SO-8 Widebody 5 3 -1.6 -1.9 V IR = 10 µA 1 IR = 100 µA, TA = 25°C mV/°C IF = 10 mA 7 1 Input Capacitance CIN 8-Pin DIP 60 pF f = 1 MHz, VF = 0 V 1 SO-8 Widebody 70 *JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C. 1-155 Switching Specifications (AC) Over Recommended Temperature (TA = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. All Typicals at TA = 25°C, VCC = 5 V. Parameter Propagation Delay Time to High Output Level Sym. tPLH Package** Min. Typ. 20 48 Max. 75* 100 Units Test Conditions Fig. ns TA = 25°C RL = 350 Ω 8, 9, CL = 15 pF 10 Note 1, 10, 19 Propagation Delay tPHL Time to Low Output Level 25 50 75* 100 ns TA = 25°C 1, 11, 19 Pulse Width Distortion |tPHL - tPLH| 8-Pin DIP SO-8 Widebody 3.5 35 ns 40 8, 9, 13, 19 10, 11 Propagation Delay tPSK Skew 40 ns 12, 13, 19 Output Rise tr Time (10-90%) 24 ns 12 1, 19 Output Fall tf Time (90-10%) 10 ns 12 1, 19 Propagation Delay tELH Single Channel 30 Time of Enable from VEH to VEL Propagation Delay tEHL Single Channel 20 Time of Enable from VEL to VEH ns RL = 350 Ω, CL = 15 pF, VEL = 0 V, VEH = 3 V ns 13, 14 14 15 *JEDEC registered data for the 6N137. **Ratings apply to all devices except otherwise noted in the Package column. Parameter Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity Sym. |CMH| |CML| Device 6N137 HCPL-2630 HCPL-0600/0630 HCNW137 HCPL-2601/2631 HCPL-0601/0631 HCNW2601 HCPL-2611/4661 HCPL-0611/0661 HCNW2611 6N137 HCPL-2630 HCPL-0600/0630 HCNW137 HCPL-2601/2631 HCPL-0601/0631 HCNW2601 HCPL-2611/4661 HCPL-0611/0661 HCNW2611 Min. Typ. 10,000 Units V/µs Test Conditions |VCM| = 10 V VCC = 5 V, IF = 0 mA, VO(MIN) = 2 V, RL = 350 Ω, TA = 25°C 5,000 10,000 |VCM| = 50 V 10,000 15,000 |VCM| = 1 kV 10,000 V/µs |VCM| = 10 V VCC = 5 V, IF = 7.5 mA, VO(MAX) = 0.8 V, RL = 350 Ω, TA = 25°C 5,000 10,000 |VCM| = 50 V 10,000 15,000 |VCM| = 1 kV Fig. Note 15 1, 16, 18, 19 15 1, 17, 18, 19 1-156 Package Characteristics All Typicals at TA = 25°C. Parameter Sym. Package Input-Output Insulation II-O* Single 8-Pin DIP Single SO-8 Input-Output VISO 8-Pin DIP, SO-8 Momentary With- Widebody stand Voltage** OPT 020† Input-Output Resistance RI-O 8-Pin DIP, SO-8 Widebody Input-Output Capacitance CI-O 8-Pin DIP, SO-8 Widebody Input-Input II-I Insulation Leakage Current Dual Channel Resistance (Input-Input) RI-I Dual Channel Capacitance (Input-Input) CI-I Dual 8-Pin DIP Dual SO-8 Min. Typ. Max. 1 2500 5000 5000 1012 1011 1012 1013 0.6 0.5 0.6 0.005 1011 0.03 0.25 Units µA V rms Test Conditions 45% RH, t = 5 s, VI-O = 3 kV dc, TA = 25°C RH ≤ 50%, t = 1 min, TA = 25°C Ω VI-O = 500 V dc TA = 25°C TA = 100°C pF f = 1 MHz, TA = 25°C µA RH ≤ 45%, t = 5 s, VI-I = 500 V Ω pF f = 1 MHz Fig. Note 20, 21 20, 21 20, 22 1, 20, 23 1, 20, 23 24 24 24 *JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. HP specifies -40°C to 85°C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” †For 6N137, HCPL-2601/2611/2630/2631/4661 only. Notes: 1. Each channel. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. 4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package. 5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 µA. HP guarantees a maximum IOH of 100 µA. 7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. HP guarantees a maximum ICCH of 10 mA. 8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. HP guarantees a maximum ICCL of 13 mA. 9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. HP guarantees a maximum IEL of -1.6 mA. 10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions. 13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V). 17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V). 18. For sinusoidal voltages, (|dVCM | / dt)max = π fCMVCM(p-p). 1-157 19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. For single channel products only. 20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only. 24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only. IOH – HIGH LEVEL OUTPUT CURRENT – µA 15 VCC = 5.5 V VO = 5.5 V VE = 2.0 V* IF = 250 µA 10 * FOR SINGLE CHANNEL PRODUCTS ONLY 5 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C VO – OUTPUT VOLTAGE – V 8-PIN DIP, SO-8 6 VCC = 5 V 5 TA = 25 °C 4 RL = 350 Ω 3 RL = 1 KΩ 2 RL = 4 KΩ 1 0 0 1 2 34 5 6 IF – FORWARD INPUT CURRENT – mA VO – OUTPUT VOLTAGE – V WIDEBODY 6 VCC = 5 V 5 TA = 25 °C 4 RL = 350 Ω 3 RL = 1 KΩ 2 RL = 4 KΩ 1 0 01 23456 IF – FORWARD INPUT CURRENT – mA Figure 1. Typical High Level Output Current vs. Temperature. Figure 2. Typical Output Voltage vs. Forward Input Current. ITH – INPUT THRESHOLD CURRENT – mA 8-PIN DIP, SO-8 6 VCC = 5.0 V 5 VO = 0.6 V 4 RL = 350 KΩ 3 RL = 1 KΩ 2 1 RL = 4 KΩ 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C ITH – INPUT THRESHOLD CURRENT – mA WIDEBODY 6 VCC = 5.0 V VO = 0.6 V 5 4 3 RL = 350 Ω RL = 1 KΩ 2 1 RL = 4 KΩ 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 3. Typical Input Threshold Current vs. Temperature. 1-158 VOL – LOW LEVEL OUTPUT VOLTAGE – V 8-PIN DIP, SO-8 0.8 VCC = 5.5 V 0.7 VE = 2.0 V* IF = 5.0 mA * FOR SINGLE CHANNEL PRODUCTS ONLY 0.6 0.5 IO = 16 mA IO = 12.8 mA 0.4 0.3 IO = 9.6 mA 0.2 IO = 6.4 mA 0.1 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C VOL – LOW LEVEL OUTPUT VOLTAGE – V WIDEBODY 0.8 VCC = 5.5 V 0.7 VE = 2.0 V IF = 5.0 mA 0.6 IO = 16 mA 0.5 IO = 12.8 mA 0.4 0.3 IO = 9.6 mA 0.2 IO = 6.4 mA 0.1 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C IOL – LOW LEVEL OUTPUT CURRENT – mA 70 VCC = 5.0 V VE = 2.0 V* VOL = 0.6 V 60 * FOR SINGLE CHANNEL PRODUCTS ONLY IF = 10-15 mA 50 40 IF = 5.0 mA 20 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 4. Typical Low Level Output Voltage vs. Temperature. Figure 5. Typical Low Level Output Current vs. Temperature. IF – FORWARD CURRENT – mA 1000 100 10 1.0 8-PIN DIP, SO-8 TA = 25 °C IF + VF – 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 1.6 VF – FORWARD VOLTAGE – V IF – FORWARD CURRENT – mA WIDEBODY 110 TA = 25 °C 100 IF + 10 VF – 1.0 0.1 0.01 0.001 1.2 1.3 1.4 1.5 1.6 1.7 VF – FORWARD VOLTAGE – V Figure 6. Typical Input Diode Forward Characteristic. dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C 8-PIN DIP, SO-8 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 0.1 1 10 100 IF – PULSE INPUT CURRENT – mA dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C WIDEBODY -2.3 -2.2 -2.1 -2.0 -1.9 -1.8 0.1 1 10 100 IF – PULSE INPUT CURRENT – mA Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current. 1-159 PULSE GEN. IF ZO = 50 Ω tf = tr = 5 ns INPUT MONITORING NODE RM SINGLE CHANNEL 1 VCC 8 2 7 3 6 4 GND 5 +5 V PULSE GEN. Z O = 50 Ω tf = t r = 5 ns IF 0.1µF BYPASS *CL INPUT RL MONITORING NODE OUTPUT VO MONITORING NODE RM DUAL CHANNEL 1 VCC 8 2 7 3 6 4 5 GND +5 V RL 0.1µF BYPASS OUTPUT VO MONITORING NODE CL* *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. INPUT IF tPHL tPLH IF = 7.50 mA IF = 3.75 mA OUTPUT VO 1.5 V Figure 8. Test Circuit for tPHL and tPLH. tP – PROPAGATION DELAY – ns 100 VCC = 5.0 V IF = 7.5 mA 80 tPLH , RL = 4 KΩ tPHL , RL = 350 Ω 1 KΩ 60 4 KΩ 40 tPLH , RL = 1 KΩ tPLH , RL = 350 Ω 20 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 9. Typical Propagation Delay vs. Temperature. tP – PROPAGATION DELAY – ns 105 VCC = 5.0 V TA = 25°C 90 tPLH , RL = 4 KΩ 75 tPLH , RL = 350 Ω 60 tPLH , RL = 1 KΩ 45 tPHL , RL = 350 Ω 1 KΩ 30 4 KΩ 5 7 9 11 13 15 IF – PULSE INPUT CURRENT – mA Figure 10. Typical Propagation Delay vs. Pulse Input Current. PWD – PULSE WIDTH DISTORTION – ns 40 RL = 4 kΩ 30 VCC = 5.0 V IF = 7.5 mA 20 RL = 350 Ω 10 0 -10 -60 -40 -20 RL = 1 kΩ 0 20 40 60 80 100 TA – TEMPERATURE – °C tr, tf – RISE, FALL TIME – ns VCC = 5.0 V IF = 7.5 mA tRISE tFALL 300 RL = 4 kΩ 290 60 RL = 1 kΩ 40 20 RL = 350 Ω 0 RL = 350 Ω, 1 kΩ, 4 kΩ -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 11. Typical Pulse Width Distortion vs. Temperature. 1-160 Figure 12. Typical Rise and Fall Time vs. Temperature. PULSE GEN. ZO = 50 Ω t f = t r = 5 ns INPUT VE MONITORING NODE 1 7.5 mA IF 2 3 4 VCC 8 7 6 5 GND +5 V 0.1 µF BYPASS RL OUTPUT VO MONITORING *CL NODE INPUT VE OUTPUT VO t EHL t ELH 3.0 V 1.5 V 1.5 V *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 13. Test Circuit for t and t . EHL ELH tE – ENABLE PROPAGATION DELAY – ns 120 VCC = 5.0 V VEH = 3.0 V VEL = 0 V 90 IF = 7.5 mA tELH, RL = 4 kΩ 60 tELH, RL = 1 kΩ 30 tELH, RL = 350 Ω 0 tEHL, RL = 350 Ω, 1 kΩ, 4 kΩ -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 14. Typical Enable Propagation Delay vs. Temperature. IF B A VFF SINGLE CHANNEL 1 VCC 8 2 7 3 6 4 GND 5 +5 V 0.1 µF BYPASS RL OUTPUT VO MONITORING NODE IF B A VFF VCM +– PULSE GENERATOR ZO = 50 Ω VCM (PEAK) VCM 0 V 5 V SWITCH AT A: IF = 0 mA VO VO (MIN.) SWITCH AT B: IF = 7.5 mA VO 0.5 V VO (MAX.) DUAL CHANNEL 1 VCC 8 2 7 3 6 4 GND 5 VCM +– PULSE GENERATOR ZO = 50 Ω CMH CML RL 0.1 µF BYPASS +5 V OUTPUT VO MONITORING NODE Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 1-161 OUTPUT POWER – PS, INPUT CURRENT – IS OUTPUT POWER – PS, INPUT CURRENT – IS HCPL-2611 OPTION 060 800 PS (mW) 700 IS (mA) 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C HCNWXXXX PS (mW) IS (mA) 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 TS – CASE TEMPERATURE – °C Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884. VCC BUS (FRONT) NC NC GND BUS (BACK) 0.1µF 10 mm MAX. (SEE NOTE 5) ENABLE OUTPUT SINGLE CHANNEL DEVICE ILLUSTRATED. Figure 17. Recommended Printed Circuit Board Layout. 1-162 VCC1 5 V GND 1 1 SINGLE CHANNEL DEVICE 470 Ω D1* IF 2 + VF –3 SHIELD VE 7 8 390 Ω 6 5V VCC2 0.1 µF BYPASS 5 2 GND 2 *DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. VCC1 5 V GND 1 1 DUAL CHANNEL DEVICE CHANNEL 1 SHOWN 470 Ω D1* IF 1 + VF –2 SHIELD 8 390 Ω 7 5V VCC2 0.1 µF BYPASS 5 2 GND 2 Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. 1-163 Propagation Delay, PulseWidth Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure 8). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-l, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applica- tions where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 19, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 20 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 20 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. 1-164 IF 50% VO 1.5 V DATA INPUTS CLOCK IF 50% VO 1.5 V t PSK DATA OUTPUTS CLOCK t PSK t PSK Figure 19. Illustration of Propagation Delay Skew - tPSK. Figure 20. Parallel Data Transmission Example. 1-165 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

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