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MC14513B BCD-To-Seven Segment Latch/Decoder/Driver CMOS MSI (Low–Power Complementary MOS) The MC14513B BCD–to–seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven segment decoder, and has output drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are used to test the display, to turn–off or pulse modulate the brightness of the display, and to store a BCD code, respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output (RBO) can be used to suppress either leading or trailing zeroes. It can be used with seven–segment light emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly. Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. • Low Logic Circuit Power Dissipation • High–current Sourcing Outputs (Up to 25 mA) • Latch Storage of Binary Input • Blanking Input • Lamp Test Provision • Readout Blanking on all Illegal Input Combinations • Lamp Intensity Modulation Capability • Time Share (Multiplexing) Capability • Adds Ripple Blanking In, Ripple Blanking Out to MC14511B • Supply Voltage Range = 3.0 V to 18 V • Capable of Driving Two Low–Power TTL Loads, One Low–power Schottky TTL Load to Two HTL Loads Over the Rated Temperature Range. MAXIMUM RATINGS (Voltages Referenced to VSS) (1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V I DC Current Drain per Input Pin 10 mA PD Power Dissipation, per Package (2.) 500 mW TA Operating Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C IOHmax Maximum Continuous Output 25 mA Drive Current (Source) per Output POHmax Maximum Continuous Output 50 mW Power (Source) per Output (3.) http://onsemi.com PDIP–18 P SUFFIX CASE 707 MARKING DIAGRAMS 18 MC14513BCP AWLYYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device Package Shipping MC14513BCP PDIP–18 20/Rail This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high– impedance circuit. A destructive high current mode v v may occur if Vin and Vout are not constrained to the range VSS (Vin or Vout) VDD. Due to the sourcing capability of this circuit, dam- age can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 3. POHmax = IOH (VDD – VOH) © Semiconductor Components Industries, LLC, 2000 1 March, 2000 – Rev. 3 This Material Copyrighted By Its Respective Manufacturer Publication Order Number: MC14513B/D MC14513B PIN ASSIGNMENT B1 C2 18 VDD 17 f LT 3 16 g BI 4 15 a LE 5 14 b D6 13 c A7 12 d RBI 8 VSS 9 11 e 10 RBO DISPLAY a f gb e c d 012 345 6789 TRUTH TABLE Inputs Outputs RBI LE BI LT D C B A RBO a b c d e f g Display X X X 0 XXXX + 1 1 1 1 1 1 1 8 X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank 0 0 1 1 0000 0 1111110 0 X 0 1 1 00 01 0 0110000 1 X 0 1 1 0010 0 1101101 2 X 0 1 1 0011 0 1111001 3 X 0 1 1 0100 0 0110011 4 X 0 1 1 0101 0 1011011 5 X 0 1 1 0110 0 1011111 6 X 0 1 1 0111 0 1110000 7 X 0 1 1 1000 0 1111111 8 X 0 1 1 1001 0 1111011 9 X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank X 1 1 1 XXX X † * * X = Don’t Care †RBO = RBI (D C B A), indicated by other rows of table *Depends upon the BCD code previously applied when LE = 0 This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 2 MC14513B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) VDD – 55_C 25_C 125_C Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit Output Voltage — Segment Outputs VOL “0” Level 5.0 Vin = VDD or 0 10 15 — 0.05 — — 0.05 — — 0.05 — Vdc 0 0.05 — 0.05 0 0.05 — 0.05 0 0.05 — 0.05 Vin = 0 or VDD “1” Level VOH 5.0 4.1 — 4.1 5.0 10 9.1 — 9.1 10 15 14.1 — 14.1 15 — 4.1 — Vdc — 9.1 — — 14.1 — Output Voltage — RBO Output VOL “0” Level 5.0 Vin = VDD or 0 10 15 — 0.05 — — 0.05 — — 0.05 — Vdc 0 0.05 — 0.05 0 0.05 — 0.05 0 0.05 — 0.05 Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 10 9.95 — 9.95 10 15 14.95 — 14.95 15 — 4.95 — Vdc — 9.95 — — 14.95 — Input Voltage (4.) “0” Level VIL (VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — (VO = 8.8 or 1.0 Vdc) 10 — 3.0 — (VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 2.25 4.50 6.75 Vdc 1.5 — 1.5 3.0 — 3.0 4.0 — 4.0 (VO = 0.5 or 3.8 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 (VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 (VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 3.5 — Vdc — 7.0 — — 11 — Output Drive Voltage — Segments VOH (IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 (IOH = 5.0 mA) — — — 4.24 (IOH = 10 mA) 3.9 — 3.9 4.12 (IOH = 15 mA) — — — 3.94 (IOH = 20 mA) 3.4 — 3.4 3.70 (IOH = 25 mA) — — — 3.54 Vdc — 4.1 — — — — — 3.5 — — — — — 3.0 — — — — (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) 10 9.1 — 9.1 9.58 — — — 9.26 9.0 — 9.0 9.17 — — — 9.04 8.6 — 8.6 8.90 — — — 8.75 — 9.1 — Vdc — — — — 8.6 — — — — — 8.2 — — — — (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) 15 14.1 — 14.1 14.59 — — — 14.27 14 — 14 14.18 — — — 14.07 13.6 — 13.6 13.95 — — — 13.80 — 14.1 — Vdc — — — — 13.6 — — — — — 13.2 — — — — (continued) This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 3 MC14513B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS) VDD – 55_C 25_C 125_C Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit Output Drive Current — RBO Output IOH (VOH = 2.5 V) Source (VOH = 9.5 V) (VOH = 13.5 V) 5.0 – 0.40 — – 0.32 – 0.64 10 – 0.21 — – 0.17 – 0.34 15 – 0.81 — – 0.66 – 1.30 mAdc — – 0.22 — — – 0.12 — — – 0.46 — (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Sink IOL 5.0 0.18 — 0.15 0.29 10 0.47 — 0.38 0.75 15 1.80 — 1.50 2.90 — 0.10 — mAdc — 0.26 — — 1.0 — Output Drive Current — Segments IOL (VOL = 0.4 V) Sink (VOL = 0.5 V) (VOL = 1.5 V) Input Current Iin 5.0 0.64 — 0.51 0.88 10 1.6 — 1.3 2.25 15 4.2 — 3.4 8.8 mAdc — 0.36 — — 0.9 — — 2.4 — 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Cin — — — — 5.0 7.5 — — pF IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc 10 — 10 — 0.010 10 — 300 15 — 20 — 0.015 20 — 600 IT 5.0 10 15 IT = (1.9 µA/kHz) f + IDD IT = (3.8 µA/kHz) f + IDD IT = (5.7 µA/kHz) f + IDD µAdc 4. Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency. Input LE and RBI low, and Inputs D, BI and LT high. f in respect to a system clock. All outputs connected to respective CL loads. 20 ns A, B, AND C 20 ns 90% VDD 50% 1 10% VSS 2f 50% DUTY CYCLE VOH ANY OUTPUT 50% VOL Figure 1. Dynamic Power Dissipation Signal Waveforms This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 4 MC14513B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) VDD All Types Characteristic Symbol Vdc Min Typ Max Unit Output Rise Time — Segment Outputs tTLH ns 5.0 — 40 80 10 — 30 60 15 — 25 50 Output Rise Time — RBO Output tTLH ns 5.0 — 480 960 10 — 240 480 15 — 190 380 Output Fall Time — Segment Outputs (7.) tTHL = (1.5 ns/pF) CL + 50 ns tTHL = (0.75 ns/pF) CL + 37.5 ns tTHL = (0.55 ns/pF) CL + 37.5 ns Output Fall Time — RBO Outputs tTHL = (3.25 ns/pF) CL + 107.5 ns tTHL = (1.35 ns/pF) CL + 67.5 ns tTHL = (0.95 ns/pF) CL + 62.5 ns Propagation Delay Time — A, B, C, D Inputs (7.) tPLH = (0.40 ns/pF) CL + 620 ns tPLH = (0.25 ns/pF) CL + 237.5 ns tPLH = (0.20 ns/pF) CL + 165 ns tTHL ns 5.0 — 125 250 10 — 75 150 15 — 65 130 tTHL ns 5.0 — 270 540 10 — 135 270 15 — 110 220 tPLH ns 5.0 — 640 1280 10 — 250 500 15 — 175 350 tPHL = (1.3 ns/pF) CL + 655 ns tPHL = (0.60 ns/pF) CL + 260 ns tPHL = (0.35 ns/pF) CL + 182.5 ns tPHL 5.0 — 720 1440 ns 10 — 290 580 15 — 200 400 Propagation Delay Time — RBI and BI Inputs (7.) tPLH = (1.05 ns/pF) CL + 547.5 ns tPLH = (0.45 ns/pF) CL + 177.5 ns tPLH = (0.30 ns/pF) CL + 135 ns tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL = (0.45 ns/pF) CL + 177.5 ns tPHL = (0.35 ns/pF) CL + 142.5 ns Propagation Delay Time — LT Input (7.) tPLH = (0.45 ns/pF) CL + 290.5 ns tPLH = (0.25 ns/pF) CL + 112.5 ns tPLH = (0.20 ns/pF) CL + 80 ns tPHL = (1.3 ns/pF) CL + 248 ns tPHL = (0.45 ns/pF) CL + 102.5 ns tPHL = (0.35 ns/pF) CL + 72.5 ns tPLH ns 5.0 — 600 750 10 — 200 300 15 — 150 220 tPHL 5.0 — 485 970 ns 10 — 200 400 15 — 160 320 tPLH ns 5.0 — 313 625 10 — 125 250 15 — 90 180 tPHL 5.0 — 313 625 ns 10 — 125 250 15 — 90 180 Setup Time tsu 5.0 100 — — ns 10 40 — — 15 30 — — Hold Time th 5.0 60 — — ns 10 40 — — 15 30 — — Latch Enable Pulse Width tWL(LE) 5.0 520 260 — ns 10 220 110 — 15 130 65 — 7. The formulas given are for the typical characteristics only. This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 5 MC14513B 20 ns INPUT C tPLH OUTPUT g tTLH 90% 50% 10% tPHL tTHL 20 ns VDD VSS VOH VOL a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high. 20 ns INPUT C tPLH OUTPUT RBO tTLH 90% 50% 10% tPHL 90% 50% 10% tTHL 20 ns VDD VSS VOH VOL b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high. 20 ns 90% VDD LE 50% 10% th VSS tsu VDD INPUT C 50% VSS VOH OUTPUT g VOL c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high. 20 ns 90% 50% LE 10% tWL(LE) 20 ns VDD VSS d. Pulse Width: Data DCBA strobed into latches. Figure 2. Dynamic Signal Waveforms This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 6 MC14513B CONNECTIONS TO VARIOUS DISPLAY READOUTS LIGHT EMITTING DIODE (LED) READOUT VDD VDD COMMON CATHODE LED COMMON ANODE LED ≈ 1.7 V ≈ 1.7 V VSS INCANDESCENT READOUT VDD VDD VSS FLUORESCENT READOUT VDD ** DIRECT (LOW BRIGHTNESS) VSS GAS DISCHARGE READOUT APPROPRIATE VDD VOLTAGE FILAMENT (SUPPLY) VSS VSS OR APPROPRIATE VOLTAGE BELOW VSS. LIQUID CRYSTAL (LC) READOUT EXCITATION (SQUARE WAVE, VDD VSS TO VDD) 1/4 OF MC14070B VSS ** A filament pre–warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. VSS Direct dc drive of LC’s not recommended for life of LC readouts. This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 7 MC14513B LOGIC DIAGRAM BI 4 15 a A7 14 b 13 c B1 12 d 11 e 17 f C2 16 g LT 30 RBI 8 10 RBO D6 LE 5 This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 8 MC14513B TYPICAL APPLICATIONS FOR RIPPLE BLANKING LEADING EDGE ZERO SUPPRESSION DISPLAYS a––– ––g CONNECT TO RBI RBO VDD (1) D C B A 1 a–– – –– g RBI RBO DC B A 1 a–– – –– g RBI RBO DC B A 0 a–– – –– g RBI RBO DC B A 0 a–– – –– g RBI RBO DC B A 0 a–– – – –g RBI RBO DC B A 0 INPUT CODE MC14513B 00 00 (0) MC14513B 0000 (0) MC14513B 0101 (5) MC14513B 0000 (0) MC14513B 0001 (1) MC14513B 0011 (3) TRAILING EDGE ZERO SUPPRESSION DISPLAYS a–– – –– g 0 RBO RBI a–– – ––g RBO RBI a –– – ––g RBO RBI a–– – –– g RBO RBI a –– – ––g RBO RBI a – – – – – g CONNECT TO RBO RBI D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1) MC14513B 01 01 (5) MC14513B 0000 (0) MC14513B 0001 (1) MC14513B 0011 (3) MC14513B 0000 (0) MC14513B 0000 (0) INPUT CODE This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 9 18 1 A F D H G MC14513B PACKAGE DIMENSIONS PDIP–18 P SUFFIX PLASTIC DIP PACKAGE CASE 707–02 ISSUE C J 10 B L 9 M C NK SEATING PLANE NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. INCHES DIM MIN MAX A 0.875 0.915 B 0.240 0.260 C 0.140 0.180 D 0.014 0.022 F 0.050 0.070 G 0.100 BSC H 0.040 0.060 J 0.008 0.012 K 0.115 0.135 L 0.300 BSC M 0_ 15_ N 0.020 0.040 MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0 _ 15_ 0.51 1.02 This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 10 Notes MC14513B This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 11 MC14513B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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This Material Copyrighted By Its Respective Manufacturer http://onsemi.com 12 MC14513B/D

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