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4032 CMOS 3位正逻辑串行加法器.pdf

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4032 CMOS 3位正逻辑串行加法器.pdf

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple Serial Adders MC14032B MC14038B The MC14032B and MC14038B triple serial adders have the clock and carry reset inputs common to all three adders. The carry is added on the positive–going clock transition for the MC14032B, and on the negative– going clock transition for the MC14038B. Typical applications include serial arithmetic units, digital correlators, digital servo control systems, datalink computers, and flight control computers. L SUFFIX CERAMIC CASE 620 • Buffered Outputs • Single–Phase Clocking • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Pin–for–Pin Replacement for CD4032B and CD4038B. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DC Supply Voltage – 0.5 to + 18.0 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ lin, lout Input or Output Current (DC or Transient), ± 10 mA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ per Pin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package† ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature (8–Second Soldering) 500 mW – 65 to + 150 _C 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAM A1 10 B1 11 INVERT 1 7 ADDER 1 9 S1 A2 13 B2 12 INVERT 2 5 A3 15 B3 14 INVERT 3 2 CLOCK 3 CARRY RESET 6 ADDER 2 4 S2 VDD = PIN 16 VSS = PIN 8 ADDER 3 1 S3 MC14032B LOGIC DIAGRAMS (ONE SECTION AND COMMON INPUTS SHOWN) MC14038B A A B S B S INVERT CARRY RESET CLOCK DQ C REV 3 1/94 ©MMCot1or4o0la3, I2nBc. 1M99C514038B 128 DQ CR TO NEXT STAGE INVERT CARRY RESET CLOCK DQ C DQ CR TO NEXT STAGE MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic VDD Symbol Vdc – 55_C Min Max ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VDD or 0 “0” Level VOL 5.0 — 0.05 10 — 0.05 15 — 0.05 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 10 9.95 — 15 14.95 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage “0” Level VIL (VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 9.0 or 1.0 Vdc) 10 — 3.0 (VO = 13.5 or 1.5 Vdc) 15 — 4.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ “1”Level VIH (VO = 0.5 or 4.5 Vdc) 5.0 3.5 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 or 9.0 Vdc) 10 7.0 — (VO = 1.5 or 13.5 Vdc) 15 11 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 2.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 13.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.4 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Capacitance ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Vin = 0) IOH Source Sink IOL Iin Cin 5.0 – 3.0 — 5.0 – 0.64 — 10 – 1.6 — 15 – 4.2 — 5.0 0.64 — 10 1.6 — 15 4.2 — 15 — ± 0.1 — — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Quiescent Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Per Package) IDD 5.0 — 5.0 10 — 10 15 — 20 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Total Supply Current**† ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Dynamic plus Quiescent, ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Per Package) (CL = 50 pF on all outputs, all ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ buffers switching) IT 5.0 10 15 25_C Min Typ # Max — 0 0.05 — 0 0.05 — 0 0.05 4.95 5.0 — 9.95 10 — 14.95 15 — — 2.25 1.5 — 4.50 3.0 — 6.75 4.0 3.5 2.75 — 7.0 5.50 — 11 8.25 — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 0.51 0.88 1.3 2.25 3.4 8.8 — ± 0.00001 — 5.0 — — — — — — — ± 0.1 7.5 — 0.005 5.0 — 0.010 10 — 0.015 20 IT = (0.96 µA/kHz) f + IDD IT = (1.93 µA/kHz) f + IDD IT = (2.80 µA/kHz) f + IDD 125_C Min Max — 0.05 — 0.05 — 0.05 4.95 — 9.95 — 14.95 — — 1.5 — 3.0 — 4.0 3.5 — 7.0 — 11 — – 1.7 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 — — — — — — — — — ± 1.0 — — 150 — 300 — 600 Unit Vdc Vdc Vdc Vdc mAdc mAdc µAdc pF µAdc µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003. PIN ASSIGNMENT S3 1 INV 3 2 C3 S2 4 INV 2 5 CARRY RESET 6 INV 1 7 VSS 8 16 VDD 15 A3 14 B3 13 A2 12 B2 11 B1 10 A1 9 S1 MOTOROLA CMOS LOGIC DATA MC14032B MC14038B 129 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise and Fall Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (1.5 ns/pF) CL + 25 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ A, B or Invert to Sum ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.5 ns/pF) CL + 65 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock to Sum ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.5 ns/pF) CL + 110 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Setup Time Symbol tTLH, tTHL tPLH, tPHL tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency fcl ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Rise and Fall Times tTHL, tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min Typ # Max Unit ns — 100 200 — 50 100 — 40 80 ns — 280 1400 — 120 300 — 90 230 ns — 500 2400 — 180 600 — 135 450 10 – 10 — ns 10 0 — 10 0 — — 4.0 1.0 MHz — 10 2.5 — 12 4.0 — — 15 µs — — 5 — — 4 * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MC14032B TIMING DIAGRAMS MC14038B WORD 1 + WORD 2 A B C INV CR S TRUE SUM WORD 1: 0.0111100 = + 60 WORD 2: 0.0110010 = + 50 0.1101110 = + 110 WORD 3 + WORD 4 COMPLEMENTED SUM WORD 3: 1.1011011 = – 37 WORD 4: 1.1001110 = – 50 1.0101001 = – 87 NOTE: Unused input pins must be connected to either VDD or VSS. WORD 1 + WORD 2 A B C INV CR S TRUE SUM WORD 1: 1.1000011 = – 61 WORD 2: 1.1001101 = – 51 1.0010000 = – 112 WORD 3 + WORD 4 COMPLEMENTED SUM WORD 3: 0.0100100 = + 36 WORD 4: 0.0110001 = + 49 0.1010101 = + 85 MC14032B MC14038B 130 MOTOROLA CMOS LOGIC DATA VDS = VOH – VDD VDD = – VGS VOH VDD A1 S1 B1 INV1 A2 B2 INV2 S2 A3 B3 INV3 CLOCK CR S3 VSS IOH EXTERNAL POWER SUPPLY Figure 1. Typical Output Source Test Circuit VDD = VGS VDS = VOL VOL VDD A1 S1 B1 INV1 A2 B2 INV2 S2 A3 B3 INV3 CLOCK CR S3 VSS IOL EXTERNAL POWER SUPPLY Figure 2. Typical Output Sink Test Circuit 500 pF PROGRAMMABLE PULSE GENERATOR VDD ID VDD A1 S1 B1 INV1 A2 B2 INV2 S2 A3 B3 INV3 CLOCK CR S3 VSS 0.01 µF CERAMIC CL CL CL CLOCK A,B 50% VARIABLE WIDTH 90% 10% tTHL 20 ns 20 ns 90% VDD 10% VSS VDD VSS tTLH Figure 3. Power Dissipation Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA MC14032B MC14038B 131 PROGRAMMABLE PULSE GENERATOR VDD A1 S1 B1 INV1 A2 B2 INV2 S2 A3 CL B3 INV3 CL CLOCK CR S3 VSS CL A 50% B CLOCK SUM tPLH 90% 50% 10% tTLH MC14032B tPHL tTHL 50% tPLH VDD VSS VDD 50% VSS tsu VDD VSS tPHL VOH VOL A 50% B CLOCK SUM tPHL 90% 50% 10% tTHL MC14038B tPLH tTLH 50% tPHL VDD VSS VDD 50% VSS tsu VDD VSS tPLH VOH VOL Figure 4. Switching Time Test Circuit and Waveforms MC14032B MC14038B 132 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 –B– 1 8 C L –T– SEATING PLANE F N K E G D 16 PL 0.25 (0.010) M T A S M J 16 PL 0.25 (0.010) M T B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0_ 15_ 0_ 15_ N 0.020 0.040 0.51 1.01 –A– 16 1 H G P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 9 B 8 F C L S –T– SEATING PLANE K J M D 16 PL 0.25 (0.010) M T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0_ 10_ 0_ 10 _ S 0.020 0.040 0.51 1.01 MOTOROLA CMOS LOGIC DATA MC14032B MC14038B 133 –A– 16 1 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J 9 –B– P 8 PL 8 0.25 (0.010) M B S G –T– SEATING PLANE K C D 16 PL 0.25 (0.010) M T B S A S F R X 45_ M J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14032B MC14038B ◊ 134 *MC14032B/D* MOTOROLA CMOS LMOCG14I0C32DBA/DTA

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