首页资源分类电子电路数字电路 > 4076 CMOS 4位三态输出D寄存器.pdf

4076 CMOS 4位三态输出D寄存器.pdf

已有 462294个资源

下载专区


TI最新应用解决方案

工业电子 汽车电子 个人消费电子

电子电路热门资源

本周本月全部

文档信息举报收藏

标    签: 4076CMOS4位三态输出D寄存器

分    享:

文档简介

4076 CMOS 4位三态输出D寄存器.pdf

文档预览

CD4076BMS December 1992 CMOS 4 -Bit D-Type Registers Features Pinout • High Voltage Type (20V Rating) • Three State Outputs • Input Disabled Without Gating the Clock • Gated Output Control Lines for Enabling or Disabling the Outputs • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description CD4076BMS types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance. The CD4076BMS is supplied in these 16 lead outline packages: CD4076BMS TOP VIEW OUTPUT DISABLE M1 N2 Q1 3 Q2 4 Q3 5 Q4 6 CLOCK 7 VSS 8 16 VDD 15 RESET 14 DATA 1 13 DATA 2 12 DATA 3 11 DATA 4 10 G2 DATA INPUT 9 G1 DISABLE Functional Diagram DATA INPUT DISABLE G1 G2 9 10 14 D1 13 D2 12 D3 11 D4 CLOCK 7 4D - TYPE FLIP-FLOPS WITH AND-OR LOGIC 15 RESET OUTPUT DISABLE M N 1 2 3 Q1 4 Q2 5 Q3 6 Q4 VSS = 8 VDD = 16 Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1029 File Number 3325 Specifications CD4076BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja Ceramic DIP and FRIT Package . . . . . 80oC/W θjc 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current Output Voltage SYMBOL CONDITIONS (NOTE 1) IDD VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND IIL VIN = VDD or GND VDD = 20 VDD = 18V IIH VIN = VDD or GND VDD = 20 VDD = 18V VOL15 VDD = 15V, No Load GROUP A SUBGROUP S 1 2 3 1 2 3 1 2 3 1, 2, 3 Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage IOL5 IOL10 IOL15 IOH5A VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V IOH5B VDD = 5V, VOUT = 2.5V IOH10 VDD = 10V, VOUT = 9.5V IOH15 VDD = 15V, VOUT = 13.5V VNTH VPTH F VIL VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V, VOH > 4.5V, VOL < 0.5V VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VIL VIH IOZL VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VDD = 20V VOUT = 0V VDD = 18V 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC +125oC -55oC LIMITS MIN - -100 -1000 -100 - MAX 10 1000 10 100 1000 100 50 UNIT S µA µA µA nA nA nA nA nA nA mV 14.95 - V 0.53 - mA 1.4 - mA 3.5 - mA - -0.53 mA - -1.8 mA - -1.4 mA - -3.5 mA -2.8 -0.7 V 0.7 2.8 V VOH > VOL V VDD/2 < VDD/2 - 1.5 V 3.5 - V - 4 V 11 - V -0.4 - µA -12 - µA -0.4 - µA 7-1030 Specifications CD4076BMS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Tri-State Output Leakage SYMBOL CONDITIONS (NOTE 1) IOZH VIN = VDD or GND VDD = 20V VOUT = VDD VDD = 18V GROUP A SUBGROUP S 1 2 3 TEMPERATURE +25oC +125oC -55oC LIMITS MIN MAX - 0.4 - 12 - 0.4 UNIT S µA µA µA NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. implemented. Limit is 0.050V max. 2. Go/No Go test with limits applied to inputs. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Q Output Transition Time SYMBOL CONDITIONS (Notes 1, 2) TPHL VDD = 5V, VIN = VDD or GND TPLH TTHL VDD = 5V, VIN = VDD or GND TTLH GROUP A SUBGROUPS TEMPERATURE 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC LIMITS MIN MAX - 600 - 810 - 200 - 270 UNITS ns ns ns ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS IDD VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VDD = 5V, No Load VOL VDD = 10V, No Load VOH VDD = 5V, No Load VOH VDD = 10V, No Load IOL5 VDD = 5V, VOUT = 0.4V Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC MIN - - 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - MAX 5 150 10 300 10 600 50 UNITS µA µA µA µA µA µA mV 50 mV - V - V - mA - mA - mA - mA - mA - mA -0.36 mA -0.64 mA -1.15 mA -2.0 mA -0.9 mA -2.6 mA 7-1031 Specifications CD4076BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low Input Voltage High Propagation Delay Clock to Q Output Propagation Delay Reset Propagation Delay 3 - State Propagation Delay 3 - State Transition Time Transition Time Maximum Clock Input Frequency Minimum Data Setup Time Minimum Data Hold Time Reset Pulse Width Minimum Clock Pulse Width Minimum Data Input SetUp Time Maximum Clock Input Rise and Fall Time Input Capacitance VIL VIH TPHL1 TPLH1 TPHL2 TPHZ TPLZ TPZH TPZL TTHL TTLH TTLH FCL TS TW TW TS TRCL TFCL CIN VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Any Input NOTES 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 1, 2 TEMPERATURE MIN +125oC - -55oC - +25oC, +125oC, - -55oC +25oC, +125oC, 7 -55oC +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC 3 +25oC 6 +25oC 8 +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX -2.4 -4.2 3 - 250 180 460 200 150 300 150 120 300 150 120 100 80 200 80 60 120 50 40 200 100 80 180 100 70 15 5 5 7.5 UNITS mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs pF 7-1032 Specifications CD4076BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. NOTES 1, 4 1, 4 1, 4 TEMPERATURE MIN +25oC - +25oC -2.8 +25oC - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC UNITS µA V V V V V ns PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A DELTA LIMIT ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 7-1033 Specifications CD4076BMS CONFORMANCE GROUPS Group E Subgroup 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD TEST PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 READ AND RECORD PRE-IRRAD POST-IRRAD 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Static Burn-In 1 Note 1 3-6 1, 2, 7 - 15 16 Static Burn-In 2 Note 1 3-6 8 1, 2, 7, 9 -16 Dynamic Burn-In Note 1 - 1, 2, 8 - 10, 15 16 3-6 7 11 - 14 Irradiation (Note 2) 3-6 8 1, 2, 7, 9 - 16 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V M1 * OUTPUT DISABLE N2 * DATA * 1 14 DATA * G1 9 INPUT DISABLE G2 10 * DATA * 2 13 * CLOCK 7 DQ CL Q R DQ CL Q R 16 VDD 3 Q1 4 Q2 DATA 3 * 12 * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VDD DATA * 4 11 * VSS RESET 15 FIGURE 1. CD4076BMS LOGIC DIAGRAM DQ CL Q R DQ CL Q R 5 Q3 6 Q4 8 VSS 7-1034 CD4076BMS TRUTH TABLE DATA INPUT DISABLE DATA NEXT STATE OUTPUT RESET CLOCK G1 G2 D Q 1 X X X X 0 0 0 X X X Q NC 0 1 X X Q NC 0 X 1 X Q NC 0 0 0 1 1 0 0 0 0 0 0 1 X X X Q NC 0 X X X Q NC When either Output Disable M or N is high, the outputs are disabled (high impedance state), however sequential operation of the flip-flops is not affected. 1 = High Level X = Don’t Care 0 = Low Level NC = No Change Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10V -15V 0 0 -5 -10 -15 -20 -25 -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1035 CD4076BMS Typical Performance Characteristics (Continued) TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 500 AMBIENT TEMPERATURE (TA) = +25oC 400 SUPPLY VOLTAGE (VDD) = 5V 300 200 SUPPLY VOLTAGE (VDD) = 5V 150 200 10V 100 15V 0 20 40 60 80 100 120 140 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (CLOCK TO Q) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF 15 10 5 MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz) 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) FIGURE 8. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs SUPPLY VOLTAGE tW tW POWER DISSIPATION PER GATE (PD) (µW) 100 10V 5V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 105 8 6 4 2 104 8 6 4 103 2 8 6 4 2 102 8 6 4 2 10 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V 8 6 CL = 50pF 4 2 CL = 15pF 1 2 46 8 2 468 2 468 2 468 2 468 2 468 10-1 1 10 102 103 104 INPUT FREQUENCY (f) (kHz) FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY CLOCK DATA INPUT DIABLE 50% tS tS 50% RESET tS 50% tW 50% tTHL Q OUTPUT tPHL 90% 50% 10% tTLH tPLH tPHL FIGURE 10. FUNCTIONAL WAVEFORM 7-1036 CD4076BMS 50% OUTPUT DISABLE tPLZ Q OUTPUT Q OUTPUT 10% 90% 50% tPZL 90% 10% tPHZ tPZH FIGURE 11. FUNCTIONAL WAVEFORM VDD VSS VDD VOL VOH VSS Chip Dimensions and Pad Layout CHARACTER tPHZ tPLZ tPZL tPZH TEST AT D VDD VSS VSS VDD VOLTAGE AT Q VSS VDD VDD VSS Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1037

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。