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4530 CMOS 双5输入优势逻辑门.pdf

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4530 CMOS 双5输入优势逻辑门.pdf

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 5-Input Majority Logic Gate The MC14530B dual five–input majority logic gate is constructed with P–channel and N–channel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtainable with the more basic gates. This device can also provide numerous logic functions by using the W and some of the logic (A thru E) inputs as control inputs. • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DC Supply Voltage – 0.5 to + 18.0 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), ± 10 mA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ per Pin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package† 500 mW ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature – 65 to + 150 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature (8–Second Soldering) 260 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C LOGIC TABLE INPUTS A B C D E W Z For all combinations of inputs where three or 0 1 more inputs are logical “0”. 1 0 For all combinations of inputs where three or 0 0 more inputs are logical “1”. 1 1 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. REV 3 1/94 ©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA MC14530B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. W BLOCK DIAGRAM 6 1 A 2 B 7 3 C M5 Z 4 D 5 E * Z = M5 Z = M5 Z = M5 W = (ABC+ABD+ABE+ACD+ W = (ACE+ADE+BCD+BCE+ W = (BDE+CDE) W 9 A 10 B 11 C M5 12 D 15 Z 13 E 14 W * M5 is a logical “1” if any three or more inputs are logical “1”.   Exclusive NOR Exclusive OR TRUTH TABLE M5 W Z 001 010 100 111 VDD = PIN 16 VSS = PIN 8 MC14530B 1 ÎÎÎÎEÎÎÎÎLEÎÎÎÎCTRÎÎÎÎICAÎÎÎÎL CÎÎÎÎHAÎÎÎÎRACÎÎÎÎTEÎÎÎÎRISÎÎÎÎTICÎÎÎÎS (VÎÎÎÎoltagÎÎÎÎesVRÎÎÎÎDefDeÎÎÎÎrencÎÎÎÎedtoÎÎÎΖV5S5ÎÎÎÎS_C) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ25_ÎÎÎÎC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ125ÎÎÎÎ_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 — 0.05 — 10 — 0.05 — 15 — 0.05 — 0 0.05 — 0.05 Vdc 0 0.05 — 0.05 0 0.05 — 0.05 Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 10 9.95 — 9.95 10 15 14.95 — 14.95 15 — 4.95 — Vdc — 9.95 — — 14.95 — Input Voltage “0” Level VIL Vdc (VO = 4.5 or 0.5 Vdc) 5.0 — 1.2 — 2.25 1.25 — 1.15 (VO = 9.0 or 1.0 Vdc) 10 — 2.5 — 4.50 2.5 — 2.4 (VO = 13.5 or 1.5 Vdc) 15 — 3.0 — 6.75 3.0 — 2.9 “1” Level VIH (VO = 0.5 or 4.5 Vdc) 5.0 3.85 — 3.75 2.75 (VO = 1.0 or 9.0 Vdc) 10 7.6 — 7.5 5.50 (VO = 1.5 or 13.5 Vdc) 15 12.1 — 12 8.25 Vdc — 3.75 — — 7.5 — — 12 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) IOH Source Sink IOL Iin Cin IDD 5.0 – 3.0 — – 2.4 – 4.2 5.0 – 0.64 — – 0.51 – 0.88 10 – 1.6 — – 1.3 – 2.25 15 – 4.2 — – 3.4 – 8.8 mAdc — – 1.7 — — – 0.36 — — – 0.9 — — – 2.4 — 5.0 0.64 — 0.51 0.88 10 1.6 — 1.3 2.25 15 4.2 — 3.4 8.8 — 0.36 — mAdc — 0.9 — — 2.4 — 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc — — — — 5.0 7.5 — — pF 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc 10 — 0.5 — 0.0010 0.5 — 15 15 — 1.0 — 0.0015 1.0 — 30 Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (0.75 µA/kHz) f + IDD IT = (1.50 µA/kHz) f + IDD IT = (2.25 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. * To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. PIN ASSIGNMENT AA 1 BA 2 CA 3 DA 4 EA 5 WA 6 ZA 7 VSS 8 16 VDD 15 ZB 14 WB 13 EB 12 DB 11 CB 10 BB 9 AB MC14530B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, ns tTHL 5.0 — 100 200 10 — 50 100 15 — 40 80 Propagation Delay Time A, C, W = VDD; B, E = Gnd; D = Pulse Generator tPLH = (1.7 ns/pF) CL + 290 ns tPLH = (0.66 ns/pF) CL + 127 ns tPLH = (0.5 ns/pF) CL + 85 ns tPLH ns 5.0 — 375 960 10 — 160 400 15 — 110 300 tPHL = (1.7 ns/pF) CL + 345 ns tPHL = (0.66 ns/pF) CL + 162 ns tPHL = (0.5 ns/pF) CL + 95 ns tPHL 5.0 — 430 1200 ns 10 — 195 540 15 — 120 410 A, B, C, D, E = Pulse Generator; W = VDD tPLH = (1.7 ns/pF) CL + 170 ns tPLH = (0.66 ns/pF) CL + 87 ns tPLH = (0.5 ns/pF) CL + 60 ns tPLH ns 5.0 — 255 640 10 — 120 300 15 — 86 210 tPHL = (1.7 ns/pF) CL + 195 ns tPHL = (0.66 ns/pF) CL + 92 ns tPHL = (0.5 ns/pF) CL + 75 ns tPHL 5.0 — 280 750 ns 10 — 125 330 15 — 100 250 A, B, C, D, E = Gnd; W = Pulse Generator tPHL, tPLH = (1.7 ns/pF) CL + 145 ns tPHL, tPLH = (0.66 ns/pF) CL + 72 ns tPHL, tPLH = (0.5 ns/pF) CL + 50 ns tPLH, ns tPHL 5.0 — 230 575 10 — 105 265 15 — 75 190 * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 16 PULSE GENERATOR A B Z C D E CL W A B C Z D E W CL 20 ns 20 ns 8 VSS VDD Vin 50% DUTY VSS CYCLE Figure 1. Power Dissipation Test Circuit and Waveform MOTOROLA CMOS LOGIC DATA MC14530B 3 1 W 0 A 1 B x C y D E 0 W 0 A 1 B x C y D E t 1 W x A y B z C D E SEQUENTIAL LOGIC APPLICATIONS COINCIDENT FLIP–FLOP Z x y Qn+1 00 0 01 Q A flip–flop that will change only when both inputs agree. 00 Q 11 1 ASTABLE MULTIVIBRATOR Z x y Qn+1 00 1 A flip–flop with three output conditions, where the third state is 01 2τ 10 2τ in oscillation between “1” and “0”. The period of oscillation is twice the delay of the gate and the feedback element. 11 1 COINCIDENT FLIP–FLOP tx y z Qn+1 Z 000 0 The flip–flop changes state only when all “1’s” or all “0’s” are 001 Qn entered. This configuration may be extended by cascading M5 010 Qn gates to cover n–inputs where all inputs must be “1’s” or “0’s” 011 Qn before the output will change. As an example, this configura- 100 Qn tion is useful for controlling an n–stage up/down counter that is 101 Qn to cycle from a minimum to maximum count and back again 110 Qn without flipping over (from all “1’s” to all “0’s”.) 111 1 MC14530B 4 MOTOROLA CMOS LOGIC DATA BASIC COMBINATIONAL FUNCTIONS W 1 W 0 A A B Z B Z C D M5 C D M5 E E W 1 1 0 A B C W 1 1 1 A B C 5–INPUT MAJORITY GATES W 0 Z 1 0 M3 A B C 3–INPUT MAJORITY GATES W 0 Z 1 1 OR3 A B C Z M3 Z NOR3 3–INPUT OR GATE W 1 0 0 A B C 3–INPUT AND GATE Z AND3 3–INPUT NOR GATE W 0 0 0 A B C Z NAND3 3–INPUT NAND GATE 5–INPUT MAJORITY LOGIC GATE APPLICATIONS Each package labeled M5 is a single majority logic gate using five inputs, A thru E, and one output Z. 1. Majority Logic Gate Array yielding the symmetric function of 1 thru 7 variables true, out of 7 input variables (X1... X7) (e.g., if any two–input variables are true (logical “1”), Z1 and Z2 are true (logical “1”) 0A 0 B C M5 Z7 D E 0 A B C M5 Z6 D E 0 0 M5 A B C M5 Z5 D E DOUBLING THE WEIGHT OF INPUT VARIABLE A BY TYING IT TO ANY TWO INPUTS WW A A B Z (AB + AC + AD + BCD) W C D 0 M5 A B C M5 Z4 D E To W S0 A S1 B S2 C S3 D S4 E W To CORRELATION OF MULTIPLE SAMPLES WITH A TEST BIT Z CORRELATION OF 60%, 80%, 100% The gate will have a “1” output if the test bit To matches or correlates with 3, 4 or 5 of the sample bits S0–S4. 0 0 M5 0 1 M5 M5 1 M5 A B C M5 Z3 D E 1A B C D M5 Z2 E To A S0 B S1 C S2 D S3 E W To Z CORRELATION OF 75%, 100% 1 1 M5 1 1 M5 1A 1B C M5 Z1 D E To A To B S0 C S1 D S2 E Z CORRELATION OF 100% X1 X3 X2 X4 X5 X6 X7 MOTOROLA CMOS LOGIC DATA MC14530B 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 –B– 1 8 C L –T– SEATING PLANE F N K E G D 16 PL 0.25 (0.010) M T A S M J 16 PL 0.25 (0.010) M T B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0_ 15_ 0_ 15_ N 0.020 0.040 0.51 1.01 –A– 16 1 H G P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 9 B 8 F C L S –T– SEATING PLANE K J M D 16 PL 0.25 (0.010) M T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0_ 10_ 0_ 10 _ S 0.020 0.040 0.51 1.01 MC14530B 6 MOTOROLA CMOS LOGIC DATA –A– 16 1 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J 9 –B– P 8 PL 8 0.25 (0.010) M B S G –T– SEATING PLANE K C D 16 PL 0.25 (0.010) M T B S A S F R X 45_ M J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC D◊ATA *MC14530B/D* MCM1C4513405B3/0DB 7

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