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a Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp AD824 FEATURES Single Supply Operation: 3 V to 30 V Very Low Input Bias Current: 2 pA Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 500 ␮A/Amp Wide Bandwidth: 2 MHz Slew Rate: 2 V/␮s No Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control and Protection Medical Instrumentation Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier PIN CONFIGURATIONS 14-Lead Epoxy DIP (N Suffix) 14-Lead Epoxy SO (R Suffix) OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 AD824 14 OUT D 13 –IN D 12 +IN D 11 V– 10 +IN C 9 –IN C 8 OUT C OUT A 1 14 OUT D –IN A 2 13 –IN D +IN A 3 AD824 12 +IN D V+ 4 TOP VIEW 11 V– +INB 5 (Not to Scale) 10 +IN C –INB 6 9 –IN C OUTB 7 8 OUT C TOP VIEW 16-Lead Epoxy SO (R Suffix) GENERAL DESCRIPTION The AD824 is a quad, FET input, single supply amplifier, featuring rail-to-rail outputs. The combination of FET inputs and rail-to-rail outputs makes the AD824 useful in a wide variety of low voltage applications where low input current is a primary consideration. The AD824 is guaranteed to operate from a 3 V single supply up to ± 15 volt dual supplies. Fabricated on ADI’s complementary bipolar process, the AD824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latchup. The output voltage swings to within 15 millivolts of the supplies. Capacitive loads to 350 pF can be handled without oscillation. The FET input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets below 300 µV. This enables high accuracy designs even with high source impedances. Precision is combined with low noise, making the AD824 ideal for use in battery powered medical equipment. OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 NC 8 AD824 16 OUT D 15 –IN D 14 +IN D 13 V– 12 +IN C 11 –IN C 10 OUT C 9 NC NC = NO CONNECT Applications for the AD824 include portable medical equipment, photo diode preamplifiers and high impedance transducer amplifiers. The ability of the output to swing rail-to-rail enables designers to build multistage filters in single supply systems and maintain high signal-to-noise ratios. The AD824 is specified over the extended industrial (–40°C to +85°C) temperature range and is available in 14-pin DIP and narrow 14-pin and 16-pin SO packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ VS = +5.0 V, VCM = 0 V, VOUT = 0.2 V, TA = +25؇C unless otherwise noted) Parameter Symbol Conditions Min Typ Max INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio VOS VOS IB IOS CMRR Input Impedance Large Signal Voltage Gain AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH Output Voltage Low VOL Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation ISC ZOUT PSRR ISY SR BWP tS GBP φo CS TMIN to TMAX TMIN to TMAX TMIN to TMAX TMIN to TMAX VCM = 0 V to 2 V VCM = 0 V to 3 V TMIN to TMAX VO = 0.2 V to 4.0 V RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source TMIN to TMAX f = 1 MHz, AV = 1 VS = 2.7 V to 12 V TMIN to TMAX TMIN to TMAX RL = 10 kΩ, AV = 1 1% Distortion, VO = 4 V p-p VOUT = 0.2 V to 4.5 V, to 0.01% No Load f = 1 kHz, RL = 2 kΩ –0.2 66 60 60 20 50 250 180 4.975 4.97 4.80 4.75 70 66 0.1 1.0 1.5 300 900 2 12 300 4000 2 10 300 3.0 80 74 1013ʈ3.3 40 100 1000 400 2 4.988 4.985 4.85 4.82 15 25 20 30 120 150 140 200 ± 12 ± 10 100 80 500 600 2 150 2.5 2 50 –123 NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion en p-p en in THD 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f = 10 kHz, RL = 0, AV = +1 2 16 0.8 0.005 Units mV mV µV µV pA pA pA pA V dB dB dB ΩʈpF V/mV V/mV V/mV V/mV µV/°C V V V V mV mV mV mV mA mA Ω dB dB µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % –2– REV. A ELECTRICAL SPECIFICATIONS (@ VS = ؎15.0 V, VOUT = 0 V, TA = +25؇C unless otherwise noted) Parameter Symbol Conditions Min Typ Max INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B Input Bias Current Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain VOS VOS IB IB IOS CMRR AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH Output Voltage Low VOL Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISC ZOUT PSRR ISY SR BWP tS GBP φo CS en p-p en in THD TMIN to TMAX TMIN to TMAX VCM = 0 V TMIN to TMAX VCM = –10 V TMIN to TMAX VCM = –15 V to 13 V TMIN to TMAX Vo = –10 V to +10 V; RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ 0.5 2.5 0.6 4.0 0.5 1.5 0.6 2.5 4 35 500 4000 25 3 20 500 –15 13 70 80 66 1013ʈ3.3 12 50 50 200 300 2000 200 1000 2 ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source, TMIN to TMAX f = 1 MHz, AV = 1 14.975 14.970 14.80 14.75 ±8 14.988 14.985 14.85 14.82 –14.985 –14.98 –14.88 –14.86 ± 20 100 –14.975 –14.97 –14.85 –14.8 VS = 2.7 V to 15 V 70 TMIN to TMAX 68 VO = 0 V TMIN to TMAX RL = 10 kΩ, AV = 1 1% Distortion, VO = 20 V p-p VOUT = 0 V to 10 V, to 0.01% f = 1 kHz, RL =2 kΩ 80 560 625 675 2 33 6 2 50 –123 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz f =10 kHz, VO = 3 V rms, RL = 10 kΩ 2 16 1.1 0.005 AD824 Units mV mV mV mV pA pA pA pA pA V dB dB ΩʈpF V/mV V/mV V/mV V/mV µV/°C V V V V V V V V mA Ω dB dB µA µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % REV. A –3– AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ VS = +3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = +25؇C unless otherwise noted) Parameter Symbol Conditions Min Typ Max INPUT CHARACTERISTICS Offset Voltage AD824A -3 V Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain VOS IB IOS CMRR AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High ∆VOS/∆T VOH Output Voltage Low VOL Short Circuit Limit Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion ISC ISC ZOUT PSRR ISY SR BWP tS GBP φo CS en p-p en in THD TMIN to TMAX TMIN to TMAX TMIN to TMAX VCM = 0 V to 1 V TMIN to TMAX VO = 0.2 V to 2.0 V RL = 2 kΩ RL = 10 kΩ RL = 100 kΩ TMIN to TMAX, RL = 100 kΩ 0.2 1.0 1.5 2 12 250 4000 2 10 250 0 1 58 74 56 1013ʈ3.3 10 20 30 65 180 500 90 250 2 ISOURCE = 20 µA TMIN to TMAX ISOURCE = 2.5 mA TMIN to TMAX ISINK = 20 µA TMIN to TMAX ISINK = 2.5 mA TMIN to TMAX Sink/Source Sink/Source, TMIN to TMAX f = 1 MHz, AV = 1 2.975 2.988 2.97 2.985 2.8 2.85 2.75 2.82 15 25 20 30 120 150 140 200 ±8 ±6 100 VS = 2.7 V to 12 V, TMIN to TMAX VO = 0.2 V, TMIN to TMAX 70 66 500 600 RL =10 kΩ, AV = 1 1% Distortion, VO = 2 V p-p VOUT = 0.2 V to 2.5 V, to 0.01% f = 1 kHz, RL = 2 kΩ 2 300 2 2 50 –123 0.1 Hz to 10 Hz 2 f = 1 kHz 16 0.8 f = 10 kHz, RL = 0, AV = +1 0.01 Units mV mV pA pA pA pA V dB dB ΩʈpF V/mV V/mV V/mV V/mV µV/°C V V V V mV mV mV mV mA mA Ω dB dB µA V/µs kHz µs MHz Degrees dB µV p-p nV/√Hz fA/√Hz % –4– REV. A AD824 WAFER TEST LIMITS (@ VS = +5.0 V, VCM = 0 V, TA = +25؇C unless otherwise noted) Parameter Symbol Conditions Limit Units Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage High Output Voltage Low Supply Current/Amplifier VOS IB IOS VCM CMRR PSRR AVO VOH VOL ISY VCM = 0 V to 2 V V = + 2.7 V to +12 V RL = 2 kΩ ISOURCE = 20 µA ISINK = 20 µA VO = 0 V, RL = ∞ 1.0 12 20 –0.2 to 3.0 66 70 15 4.975 25 600 NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. DICE CHARACTERISTICS mV max pA max pA V min dB min µV/V V/mV min V min mV max µA max ABSOLUTE MAXIMUM RATINGS1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V Output Short Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range N, R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type θJA2 θJC Units AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 143. 14-Pin Plastic DIP (N) 76 33 °C/W 14-Pin SOIC (R) 120 36 °C/W 16-Pin SOIC (R) 92 27 °C/W NOTES 1Absolute maximum ratings apply to both DICE and packaged parts unless otherwise noted. 2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC package. Model ORDERING GUIDE Temperature Range Package Option AD824AN AD824BN AD824AR AD824AR-3V AD824AN-3V AD824AR-14 AD824AR-14-3V AD824AR-16 AD824AChips –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C 14-Pin Plastic DIP 14-Pin Plastic DIP 14-Pin SOIC 14-Pin SOIC 14-Pin Plastic DIP 14-Pin SOIC 14-Pin SOIC 16-Pin SOIC DICE VCC R1 R2 I5 I6 Q18 Q29 R9 Q21 Q27 Q4 Q6 C3 +IN J1 J2 Q5 Q19 Q20 Q7 R7 R13 R15 –IN C2 Q22 Q23 C4 VOUT Q24 Q25 Q8 C1 Q2 Q3 R12 R14 I1 I2 I3 I4 Q31 Q28 Q26 R17 VEE CAUTION Figure 1. Simplified Schematic of 1/4 AD824 ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. A –5– GAIN – dB PHASE – Degrees GAIN – dB PHASE – Degrees AD824–Typical Characteristics 80 VS = ±15V NO LOAD 60 40 45 20 90 135 0 180 100 1k 10k 100k 1M 10M 100 90 80 VS = +5V NO LOAD 60 40 45 20 90 135 0 180 100 1k 10k 100k 1M 10M 100 90 GAIN – dB PHASE – Degrees GAIN – dB PHASE – Degrees 10 0% 50mV 1µs Figure 2. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, No Load 80 VS = ±15V CL = 100pF 60 40 45 20 90 135 0 180 100 1k 10k 100k 1M 10M 10 0% 50mV 1µs Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = +5 V, No Load 60 40 20 0 –20 1k VS = +5V CL = 220pF 45 90 135 180 10k 100k 1M 10M 100 100 90 90 10 0% 50mV 1µs 10 0% 50mV 1µs Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, CL = 100 pF Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = +5 V, CL = 220 pF –6– REV. A GAIN – dB PHASE – Degrees 60 40 20 0 –20 1k VS = +3V NO LOAD 45 90 135 180 10k 100k 1M 10M AD824 t 9.950 µs 100 90 10 0% 5V 100 90 2µs t 10.810 µs 100 90 10 0% 5V 2µs 10 0% 50mV 1µs Figure 8. Slew Rate, RL = 10k GAIN – dB PHASE – Degrees OUTPUT TO RAIL – Volts Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = +3 V, No Load 60 40 20 0 –20 1k VS = +3V CL = 220pF 45 90 135 180 10k 100k 1M 10M 100 90 10 0% 50mV 1µs 100 90 VOUT 10 0% 5V 100µs Figure 9. Phase Reversal with Inputs Exceeding Supply by 1 Volt 0.8 0.7 0.6 0.5 SOURCE 0.4 0.3 0.2 SINK 0.1 0 1µ 5µ 10µ 50µ 100µ 500µ 1m 5m 10m LOAD CURRENT – A Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = +3 V, CL = 220 pF Figure 10. Output Voltage to Supply Rail vs. Sink and Source Load Currents REV. A –7– AD824–Typical Characteristics NOISE DENSITY – nV/√Hz +3V ≤ VS ≤ ±15V 60 40 20 5 10 15 20 FREQUENCY – kHz Figure 11. Voltage Noise Density THD+N – % 0.1 0.010 0.001 0.0001 20 VS = +3 VS = +5 VS = ±15 RL = 0 AV = +1 100 1k FREQUENCY – Hz 10k 20k NUMBER OF UNITS Figure 12. Total Harmonic Distortion 280 COUNT = 860 240 200 160 120 80 40 0 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 OFFSET VOLTAGE – mV Figure 13. Input Offset Distribution, VS = 5, 0 NUMBER OF UNITS 14 COUNT = 60 12 10 8 6 4 2 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 OFFSET VOLTAGE DRIFT Figure 14. TC VOS Distribution, –55°C to +125°C, VS = 5, 0 INPUT OFFSET CURRENT – pA 150 VS = 5, 0 125 100 75 50 25 0 –25 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 15. Input Offset Current vs. Temperature INPUT BIAS CURRENT – pA 100k 10k VS = 5, 0 1k 100 10 1 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 16. Input Bias Current vs. Temperature –8– REV. A COMMON-MODE REJECTION – dB 120 100 80 60 40 20 0 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 17. Common-Mode Rejection vs. Frequency –40 –60 THD – dB –80 –100 –120 100 1k 10k FREQUENCY – Hz 100k Figure 18. THD vs. Frequency, 3 V rms OPEN-LOOP GAIN – dB 100 100 80 80 60 60 ±15V 40 40 +3, 0V 20 20 0 0 –20 –20 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 19. Open-Loop Gain and Phase vs. Frequency PHASE MARGIN – Degrees OUTPUT VOLTAGE – Volts AD824 .. 1k INPUT VOLTAGE NOISE – nV/√Hz 100 10 1 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 20. Input Voltage Noise Spectral Density vs. Frequency POWER SUPPLY REJECTION – dB 120 100 80 60 40 20 0 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 21. Power Supply Rejection vs. Frequency 30 25 20 15 10 5 0 1k 3k 10k 30k 100k 300k 1M INPUT FREQUENCY – Hz Figure 22. Large Signal Frequency Response REV. A –9– AD824 –80 –90 –100 –110 –120 –130 –140 10 CROSSTALK – dB 1 TO 4 1 TO 2 1 TO 3 100 1k 10k FREQUENCY – Hz 100k Figure 23. Crosstalk vs. Frequency OUTPUT IMPEDANCE – Ω 10k 1k 100 10 1 .1 .01 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 24. Output Impedance vs. Frequency, Gain = +1 20mV 100 90 500ns 10 0% Figure 25. Small Signal Response, Unity Gain Follower, 10kʈ100 pF Load OUTPUT SATURATION VOLTAGE – mV SUPPLY CURRENT – µA 5V 100 90 10 0% 5µs Figure 26. Large Signal Response 2750 2500 2250 VS = ±15V 2000 1750 VS = 3, 0 1500 1250 1000 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 27. Supply Current vs. Temperature 1000 VS = ±15V VS = 3, 0 100 VOL – VS 10 VS – VOH 0 0.01 0.10 1.0 10.0 LOAD CURRENT – mA Figure 28. Output Saturation Voltage –10– REV. A AD824 APPLICATION NOTES INPUT CHARACTERISTICS In the AD824, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from 0.2 V below –VS to 1 V less than +VS. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth. The AD824 does not exhibit phase reversal for input voltages up to and including +VS. Figure 29a shows the response of an AD824 voltage follower to a 0 V to +5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output wave form. For input voltages greater than +VS, a resistor in series with the AD824’s noninverting input will prevent phase reversal at the expense of greater input voltage noise. This is illustrated in Figure 29b. 1V 100 90 2µs 10 GND 0% 1V 1V 100 +VS 90 (a) 1V 10µs 10 GND 0% 1V RP VIN (b) +5V VOUT Figure 29. (a) Response with RP = 0; VIN from 0 to +VS (b) VIN = 0 to + VS + 200 m V VOUT = 0 to + VS RP = 49.9 kΩ Since the input stage uses n-channel JFETs, input current during normal operation is positive; the current flows out from the input terminals. If the input voltage is driven more positive than +VS – 0.4 V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in Figure 9. A current-limiting resistor should be used in series with the input of the AD824 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV or if an input voltage will be applied to the AD824 when ± VS = 0. The amplifier will be damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than –VS are a completely different story. The amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. OUTPUT CHARACTERISTICS The AD824’s unique bipolar rail-to-rail output stage swings within 15 mV of the positive and negative supply voltages. The AD824’s approximate output saturation resistance is 100 Ω for both sourcing and sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, the saturation voltage will be 0.5 volts from either supply with a 5 mA current load. For load resistances over 20 kΩ, the AD824’s input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. If the AD824’s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 µs of its input returning to the amplifier’s linear operating region. Direct capacitive loads will interact with the amplifier’s effective output impedance to form an additional pole in the amplifier’s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figures 5 and 7 show the AD824’s pulse response as a unity gain follower driving 220 pF. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. Figure 30 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit will drive 5,000 pF with a 10% overshoot. +VS 0.01µF 8 VIN 1/4 AD824 100Ω 0.01µF 4 VOUT –VS CL 20kΩ 20pF Figure 30. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF REV. A –11– AD824 APPLICATIONS Single Supply Voltage-to-Frequency Converter The circuit shown in Figure 31 uses the AD824 to drive a low power timer, which produces a stable pulse of width t1. The positive going output pulse is integrated by R1-C1 and used as one input to the AD824, which is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD824 output drives the timer trigger input, closing the overall feedback loop. +10V C5 0.1µF U4 REF02 2 6 VREF = 5V 3 5 RSCALE ** 10k 4 CMOS 74HCO4 U3B U3A 4 32 1 C3 0.1µF R2 499k, 1% R1 VI N 499k, 1% 0V TO 2.5V FULL SCALE C2 0.01µF, 2% 0.01µF, 2% U1 R3* C1 116k 1/4 AD824B C6 390pF 5% (NPO) U2 CMOS 555 48 6R THR 2 TR 7 DIS V+ 3 OUT 5 CV GND 1 C4 0.01µF OUT2 OUT1 NOTES: fOUT = VIN /(VREF*t1), t1 = 1.1*R3*C6 = 25kHz fS AS SHOWN. * = 1% METAL FILM, <50ppm/°C TC ** = 10%, 20T FILM, <100ppm/°C TC t1 = 33µs FOR fOUT = 20kHz @ VIN = 2.0V Figure 31. Single Supply Voltage-to-Frequency Converter Typical AD824 bias currents of 2 pA allow megaohm-range source impedances with negligible dc errors. Linearity errors on the order of 0.01% full scale can be achieved with this circuit. This performance is obtained with a 5 volt single supply, which delivers less than 3 mA to the entire circuit. Single Supply Programmable Gain Instrumentation Amplifier The AD824 can be configured as a single supply instrumentation amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ± 15 V. AD824 FET inputs’ 2 pA bias currents minimize offset errors caused by high unbalanced source impedances. An array of precision thin-film resistors sets the in amp gain to be either 10 or 100. These resistors are laser-trimmed to ratio match to 0.01% and have a maximum differential TC of 5 ppm/°C. Table I. AD824 In Amp Performance Parameters VS = 3 V, 0 V VS = ؎5 V CMRR Common-Mode Voltage Range 3 dB BW, G = 10 G = 100 tSETTLING 2 V Step (VS = 0 V, 3 V) 5 V (VS = ± 5 V) Noise @ f = 1 kHz, G = 10 G = 100 74 dB 80 dB –0.2 V to +2 V –5.2 V to +4 V 180 kHz 180 kHz 18 kHz 18 kHz 2 µs 270 nV/√Hz 2.2 µV/√Hz 5 µs 270 nV/√Hz 2.2 µV/√Hz 5µs 100 90 10 0% 1V Figure 32a. Pulse Response of In Amp to a 500 mV p-p Input Signal; VS = +5 V, 0 V; Gain = 10 VREF R1 R2 R3 R4 R5 R6 90k 9k 1k 1k 9k 90k OHMTEK PART # 1043 G =10 G =100 G =100 +VS 0.1µF G =10 2 6 RP VIN1 1/4 8 1 3 AD824 1kΩ RP 1/4 7 5 AD824 11 VOUT VIN2 1kΩ (G =10) VOUT = (VIN1 – VIN2) (1+ R6 R4 + R5 ) +VREF (G =100) VOUT = (VIN1 – VIN2 ) (1+ R5 + R6 R4 ) +VREF FOR R1 = R6, R2 = R5 AND R3 = R4 Figure 32b. A Single Supply Programmable Instrumentation Amplifier –12– REV. A AD824 3 Volt, Single Supply Stereo Headphone Driver The AD824 exhibits good current drive and THD+N performance, even at 3 V single supplies. At 1 kHz, total harmonic distortion plus noise (THD+N) equals –62 dB (0.079%) for a 300 mV p-p output signal. This is comparable to other single supply op amps that consume more power and cannot run on 3 V power supplies. In Figure 33, each channel’s input signal is coupled via a 1 µF Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies (+1.5 V). The gain is 1.5. Each half of the AD824 can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 500 µF capacitors and the headphones, which can be modeled as 32 ohm load resistors to ground. This ensures that all signals in the audio frequency range (20 Hz–20 kHz) are delivered to the headphones. CHANNEL 1 1µF MYLAR 95.3k CHANNEL 2 1µF MYLAR +3V 95.3k 0.1µF 0.1µF 1/4 47.5k AD824 500µF 4.99k L 10k HEADPHONES 32Ω IMPEDANCE 10k R 4.99k 47.5k 1/4 AD824 500µF Figure 33. 3 Volt Single Supply Stereo Headphone Driver Low Dropout Bipolar Bridge Driver The AD824 can be used for driving a 350 ohm Wheatstone bridge. Figure 34 shows one half of the AD824 being used to buffer the AD589—a 1.235 V low power reference. The output 49.9k +1.235V AD589 10k 1% 10k 1% +VS 1/4 AD824 26.4k, 1% 350Ω 350Ω 10k 1% 1/4 AD824 R1 20Ω TO A/D CONVERTER REFERENCE INPUT 350Ω 350Ω RG +VS 3 7 AD620 6 5 24 VREF –VS –4.5V R2 20Ω –VS +VS 0.1µF GND 0.1µF –VS +5V 1µF 1µF –5V Figure 34. Low Dropout Bipolar Bridge Driver of +4.5 V can be used to drive an A/D converter front end. The other half of the AD824 is configured as a unity-gain inverter and generates the other bridge input of –4.5 V. Resistors R1 and R2 provide a constant current for bridge excitation. The AD620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD620 is programmed using an external resistor RG and determined by: G = 49.4 kΩ + 1 RG A 3.3 Volt/5 Volt Precision Sample-and-Hold Amplifier In battery-powered applications, low supply voltage operational amplifiers are required for low power consumption. Also, low supply voltage applications limit the signal range in precision analog circuitry. Circuits like the sample-and-hold circuit shown in Figure 35, illustrate techniques for designing precision analog circuitry in low supply voltage applications. To maintain high signal-to-noise ratios (SNRs) in a low supply voltage application requires the use of rail-to-rail, input/output operational amplifiers. This design highlights the ability of the AD824 to operate rail-to-rail from a single +3 V/+5 V supply, with the advantages of high input impedance. The AD824, a quad JFET-input op amp, is well suited to S/H circuits due to its low input bias currents (3 pA, typical) and high input impedances (3 × 1013 Ω, typical). The AD824 also exhibits very low supply currents so the total supply current in this circuit is less than 2.5 mA. 3.3/5V 3.3/5V R1 AD824A 0.1µF 50k 3 4 1 2 A1 FALSE GROUND (FG) R2 11 50k R4 2kΩ R5 2kΩ SAMPLE/ HOLD 3.3/5V 13 15 14 ADG513 16 10 11 AD824B 5 7 2 6 A2 7 AD824D 12 FG 4 14 13 A4 9 3 1 6 8 5 FG CH 500pF 10 8 9 A3 AD824C C 500pF FG + – VOUT Figure 35. 3.3 V/5.5 V Precision Sample and Hold In many single supply applications, the use of a false ground generator is required. In this circuit, R1 and R2 divide the supply voltage symmetrically, creating the false ground voltage at one-half the supply. Amplifier A1 then buffers this voltage creating a low impedance output drive. The S/H circuit is configured in an inverting topology centered around this false ground level. REV. A –13– AD824 A design consideration in sample-and-hold circuits is voltage droop at the output caused by op amp bias and switch leakage currents. By choosing a JFET op amp and a low leakage CMOS switch, this design minimizes droop rate error to better than 0.1 µV/µs in this circuit. Higher values of CH will yield a lower droop rate. For best performance, CH and C2 should be polystyrene, polypropylene or Teflon capacitors. These types of capacitors exhibit low leakage and low dielectric absorption. Additionally, 1% metal film resistors were used throughout the design. In the sample mode, SW1 and SW4 are closed, and the output is VOUT = –VIN. The purpose of SW4, which operates in parallel with SW1, is to reduce the pedestal, or hold step, error by injecting the same amount of charge into the noninverting input of A3 that SW1 injects into the inverting input of A3. This creates a common-mode voltage across the inputs of A3 and is then rejected by the CMR of A3; otherwise, the charge injection from SW1 would create a differential voltage step error that would appear at VOUT. The pedestal error for this circuit is less than 2 mV over the entire 0 V to 3.3 V/5 V signal range. Another method of reducing pedestal error is to reduce the pulse amplitude applied to the control pins. In order to control the ADG513, only 2.4 V are required for the “ON” state and 0.8 V for the “OFF” state. If possible, use an input control signal whose amplitude ranges from 0.8 V to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum pedestal error. Other circuit features include an acquisition time of less than 3 µs to 1%; reducing CH and C2 will speed up the acquisition time further, but an increased pedestal error will result. Settling time is less than 300 ns to 1%, and the sample-mode signal BW is 80 kHz. The ADG513 was chosen for its ability to work with 3 V/5 V supplies and for having normally-open and normally-closed precision CMOS switches on a dielectrically isolated process. SW2 is not required in this circuit; however, it was used in parallel with SW3 to provide a lower RON analog switch. –14– REV. A AD824 * AD824 SPICE Macro-model 9/94, Rev. A * ARG/ADI * * Copyright 1994 by Analog Devices, Inc. * * Refer to “README.DOC” file for License Statement. Use of this model indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * || | | | .SUBCKT AD824 1 2 99 50 25 * * INPUT STAGE & POLE AT 3.1 MHz * R3 5 99 1.193E3 R4 6 99 1.193E3 CIN 1 2 4E-12 C2 5 6 19.229E-12 I1 4 50 108E-6 IOS 1 2 1E-12 EOS 7 1 POLY(1) (12,98) 100E-6 1 J1 4 2 5 JX J2 4 7 6 JX * * GAIN STAGE & DOMINANT POLE * EREF 98 0 (30,0) 1 R5 9 98 2.205E6 C3 9 25 54E-12 G1 98 9 (6,5) 0.838E-3 V1 8 98 -1 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz * R21 11 12 1E6 R22 12 98 100 C14 11 12 159E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHz * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 (9,98) 1E-6 * * OUTPUT STAGE * ES 26 98 (18,98) 1 RS 26 22 500 IB1 98 21 2.404E-3 IB2 23 98 2.404E-3 D10 21 98 DY D11 98 23 DY C16 20 25 2E-12 C17 24 25 2E-12 DQ1 97 20 DQ Q2 20 21 22 NPN Q3 24 23 22 PNP DQ2 24 51 DQ Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 (99,0) 1 EN 52 0 (50,0) 1 R25 30 99 5E6 R26 30 50 5E6 FSY1 99 0 VP 1 FSY2 0 50 VN 1 DC1 25 99 DX DC2 50 25 DX * * MODELS USED * .MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 RC=550 IS=1E-16) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 RC=750 IS=1E-16) .MODEL DX D(IS=1E-15) .MODEL DY D() .MODEL DQ D(IS=1E-16) .ENDS AD824 REV. A –15– AD824 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Pin Plastic (N) Package (N-14) 14 PIN 1 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 8 0.280 (7.11) 0.240 (6.10) 7 0.795 (20.19) 0.725 (18.42) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE 14-Pin SOIC (R) Package (R-14) 14 PIN 1 1 8 0.1574 (4.00) 0.1497 (3.80) 7 0.2440 (6.20) 0.2284 (5.80) 0.0098 (0.25) 0.0040 (0.10) 0.3444 (8.75) 0.3367 (8.55) 0.0196 (0.50) 0.0099 (0.25) x 45 ° 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) BSC 0.0138 (0.35) 8° 0.0098 (0.25) 0° 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 16-Pin SOIC Package (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) x 45° 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8° SEATING 0.0125 (0.32) 0° PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) –16– 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. REV. A C1988a–2–1/97

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