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40109 CMOS 四三态输出低到高电平移位器.pdf

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40109 CMOS 四三态输出低到高电平移位器.pdf

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CD40109BMS December 1992 CMOS Quad Low-to-High Voltage Level Shifter Features Description • High Voltage Type (20V Rating) • Independence of Power Supply Sequence Considerations - VCC can Exceed VDD - Input Signals can Exceed Both VCC and VDD • Up and Down Level Shifting Capability • Three-State Outputs with Separate Enable Controls • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VCC = 5V, VDD = 10V - 2V at VCC = 10V, VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD40109BMS contains four low-to-high voltage level shifting circuits. Each circuit will shift a low voltage digital logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS. The CD40109BMS, unlike other low-to-high level shifting circuits, does not require the presence of the high voltage supply (VDD) before the application of either the low voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109BMS will operate as a high-to-low level shifter. The CD40109BMS also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high impedance state in the corresponding output. Applications • High or Low Level Shifting with Three-State Outputs for Unidirectional or Bidirectional Bussing • Isolation of Logic Subsystems Using Separate Power Supplies from Supply Sequencing, Supply Loss and Supply Regulation Considerations The CD40109BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W Pinout CD40109BMS TOP VIEW VCC 1 ENABLE A 2 A3 E4 F5 B6 ENABLE B 7 VSS 8 16 VDD 15 ENABLE D 14 D 13 H 12 NC 11 G 10 C 9 ENABLE C Functional Diagram 1 OF 4 UNITS VCC VDD LEVEL A SHIFTER E ENABLE A LEVEL SHIFTER CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-36 File Number 3196 Specifications CD40109BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja Ceramic DIP and FRIT Package . . . . . 80oC/W θjc 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL CONDITIONS (NOTE 1) IDD VDD = 20V, VIN = VDD or GND Input Leakage Current VDD = 18V, VIN = VDD or GND IIL VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS 1 2 3 1 2 TEMPERATURE +25oC +125oC -55oC +25oC +125oC LIMITS MIN MAX UNITS - 2 µA - 200 µA - 2 µA -100 - nA -1000 - nA Input Leakage Current VDD = 18V IIH VIN = VDD or GND VDD = 20 Output Voltage VDD = 18V VOL15 VDD = 15V, No Load 3 1 2 3 1, 2, 3 -55oC -100 - nA +25oC - 100 nA +125oC - 1000 nA -55oC - 100 nA +25oC, +125oC, -55oC - 50 mV Output Voltage Output Current (Sink) Output Current (Sink) VOH15 IOL5 IOL10 VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 0.53 - mA 1 +25oC 1.4 - mA Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA N Threshold Voltage P Threshold Voltage Functional Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage Tri-State Output Leakage VNTH VPTH F VIL VIH VIL VIH IOZL IOZH VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 15V, VOH > 13.5V, VOL < 1.5V, VCC = 10V VDD = 15V, VOH > 13.5V, VOL < 1.5V, VCC = 10V VIN = VDD or GND VDD = 20V VOUT = 0V VIN = VDD or GND VOUT = VDD VDD = 18V VDD = 20V VDD = 18V 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC -2.8 -0.7 V +25oC 0.7 2.8 V +25oC VOH > VOL < V +25oC VDD/2 VDD/2 +125oC -55oC +25oC, +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V +25oC, +125oC, -55oC - 3 V +25oC, +125oC, -55oC 7 - V +25oC +125oC -55oC +25oC +125oC -55oC -0.4 - µA -12 - µA -0.4 - µA - 0.4 µA - 12 µA - 0.4 µA NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit implemented. is 0.050V max. 2. Go/No Go test with limits applied to inputs. 7-37 Specifications CD40109BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode H-L Propagation Delay Data In to Out Shift Mode H-L Transition Time Shift Mode L-H Transition Time Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L SYMBOL TPHL1 CONDITIONS VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 1, 2) GROUP A SUBGROUPS 9 10, 11 TEMPERATURE +25oC +125oC, -55oC TPLH1 VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 1, 2) 9 10, 11 +25oC +125oC, -55oC TPHL2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 1, 2) 9 10, 11 +25oC +125oC, -55oC TPLH2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 1, 2) 9 10, 11 +25oC +125oC, -55oC TTHL1 VDD = 10V, VIN = VDD or GND TTLH1 VCC = 5V (Notes 1, 2) TTHL2 VDD = 5V, VIN = VDD or GND TTLH2 VCC = 10V (Notes 1, 2) TPHZ1 VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) TPHZ2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) TPLZ1 VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) TPLZ2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) TPZH1 VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) TPZH2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) TPZL1 VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) TPZL2 VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. LIMITS MIN MAX - 600 - 810 - 260 - 351 - 500 - 675 - 460 - 621 - 100 - 135 - 200 - 270 - 120 - 162 - 400 - 540 - 740 - 999 - 500 - 675 - 640 - 864 - 600 - 810 - 200 - 270 - 400 - 540 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER Supply Current Output Voltage TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS SYMBOL CONDITIONS IDD VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND VOL VDD = 5V, No Load NOTES 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC LIMITS MIN MAX - 1 - 30 - 2 - 60 - 2 - 120 - 50 UNITS µA µA µA µA µA µA mV 7-38 Specifications CD40109BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Voltage Output Voltage Output Voltage Output Current (Sink) SYMBOL CONDITIONS VOL VDD = 10V, No Load VOH VDD = 5V, No Load VOH VDD = 10V, No Load IOL5 VDD = 5V, VOUT = 0.4V Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low Input Voltage High Propagation Delay Data In to Data Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode H-L Propagation Delay Data In to Out Shift Mode H-L Transition Time Shift Mode L-H Transition Time Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H VIL VIH TPHL1 VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPLH1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPHL2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPLH2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TTHL1 TTLH1 TTHL2 TTLH2 TPHZ1 TPHZ2 TPLZ1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V VDD = 5V, VCC = 5V VDD = 10V, VCC = 15V VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN - 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - 3.5 - - - - - MAX 50 - - -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 1.5 - 440 360 240 140 500 240 460 160 80 80 200 100 150 70 400 80 600 500 UNITS mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7-39 Specifications CD40109BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L SYMBOL CONDITIONS TPLZ2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPZH1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPZH2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPZL1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPZL2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V NOTES 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 TEMPERATURE MIN +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX 500 260 460 360 600 260 160 80 400 80 UNITS ns ns ns ns ns ns ns ns ns ns NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE MIN +25oC - +25oC -2.8 +25oC - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 7.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD 100% 5004 GROUP A SUBGROUPS 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A 7-40 Specifications CD40109BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD POST-IRRAD 1, 7, 9 Table 4 READ AND RECORD PRE-IRRAD POST-IRRAD 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Static Burn-In 1 (Note 1) 4, 5, 11-13 2, 3, 6-10, 14, 15 1, 16 Static Burn-In 2 (Note 1) 4, 5, 11-13 8 16 1-3, 4, 7, 9, 10, 14, 15 Dynamic Burn-In (Note 4) 12 8 16 1, 4, 5, 11, 13 3, 6, 10, 14 2, 7, 9, 15 (Note 3) (Note 3) Irradiation (Note 2) 4, 5, 11-13 8 1-3, 6, 7, 9, 10, 14-16 NOTES: 1. Each pin except Pin 1, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except Pin 1, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 3. Pin voltage is VDD/2 4. Each pin except Pin 1, VDD and GND will have a series resistor of 4.75K ±5%, VDD = 18V ±0.5V. Logic Diagram VCC VDD A* 3 (6, 10, 14) LEVEL SHIFTER ENABLE A * 2 (7, 9, 15) LEVEL SHIFTER VDD VDD E 4 (5, 11, 13) VCC = 1 VDD = 16 VSS = 8 VSS * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. 1 OF 4 UNITS TRUTH TABLE INPUTS OUTPUTS A, B, C, D ENABLE A, B, C, D E, F, G, H 0 1 0 1 1 1 X 0 Z Logic 0 = Low(VSS) X = Don’t care Z = High impedance Logic 1 = VCC at Inputs and VDD at Outputs 7-41 CD40109BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10V -15V 0 0 -5 -10 -15 -20 -25 -30 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 350 VCC = 5V, VDD = 10V 300 HIGH-TO-LOW PROPAGATION DELAY TIME (tPHL) (ns) 250 VCC = 5V, VDD = 15V 200 VCC = 10V, VDD = 15V 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL HIGH-TO-LOW PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 7-42 CD40109BMS Typical Performance Characteristics (Continued) LOW-TO-HIGH PROPAGATION DELAY TIME (tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 175 150 VCC = 5V, VDD = 10V 125 VCC = 5V, VDD = 15V 100 75 VCC = 10V, VDD = 15V 50 25 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL LOW-TO-HIGH PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 25 SUPPLY VOLTAGE (VDD) (V) 20 15 RECOMMENDED OPERATING 10 BOUNDARY 5 0 0 5 10 15 20 25 SUPPLY VOLTAGE (VCC) (V) FIGURE 10. HIGH LEVEL SUPPLY VOLTAGE vs LOW LEVEL SUPPLY VOLTAGE INPUT SWITCHING VOLTAGE (VSWITCH) (V) AMBIENT TEMPERATURE (TA) = +25oC 10 VIN VSS 8 VOUT 6 VSS VCC *VSWITCH VDD 50% ENABLE = VCC VCC = 15V 4 VCC = 10V 2 VCC = 5V * VSWITCH = INPUT VOLTAGE AT WHICH OUTPUT LEVEL IS 50% OF VDD - VSS 0 2.5 5 7.5 10 12.5 15 17.5 20 SUPPLY VOLTAGE (VDD) (V) FIGURE 9. TYPICAL INPUT SWITCHING AS A FUNCTION OF HIGH LEVEL SUPPLY VOLTAGE DISSIPATION PER LEVEL SHIFTER (PD) (µW) 105 8 6 AMBIENT TEMPERATURE (TA) = +25oC 4 2 104 8 6 4 2 103 8 6 4 2 102 8 6 4 2 VCC = 5V, VDD = 15V VCC = 5V, VDD = 10V VCC = 10V, VDD = 15V VCC = 5V, VDD = 10V LOAD CAPACITANCE CL = 50pF CL = 15pF 10 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 1 10 102 103 104 105 INPUT FREQUENCY (fi) (kHz) FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY Test Circuit and Waveform A INPUT (SEE TABLE) VCC 1 2 3 4 5 6 7 8 VSS VDD 16 15 14 13 12 11 10 9 PULSE GENERATOR 1K B RS (SEE CL TABLE) 50pF OUTPUT CHAR tPHZ tPLZ tPZL tPZH TEST VOLTAGE AT A AT B VCC VSS VSS VDD VSS VDD VCC VSS ENABLE 50% INPUT tPLZ OUTPUT OUTPUT tPHZ 10% 90% VCC 50% VSS tPZL 90% VDD VOL VOH 10% VSS tPZH FIGURE 12. OUTPUT ENABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS 7-43 CD40109BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 44

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