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4572 CMOS 六门电路.pdf

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4572 CMOS 六门电路.pdf

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Gate The MC14572UB hex functional gate is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. The chip contains four inverters, one NOR gate and one NAND gate. • Diode Protection on All Inputs • Single Supply Operation • Supply Voltage Range = 3.0 Vdc to 18 Vdc • NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter • NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter • NOR Output Pin Adjacent to Inverter Input Pin For OR Application • NAND Output Pin Adjacent to Inverter Input Pin For AND Application • Capable of Driving Two Low–power TTL Loads or One Low–Power ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Schottky TTL Load over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), ± 10 mA per Pin PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C CIRCUIT SCHEMATIC VDD VDD VDD 7 2 1 6 VSS 5 14 15 VSS 13 VSS MC14572UB L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXUBCP MC14XXXUBCL MC14XXXUBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. LOGIC DIAGRAM 2 1 4 3 6 5 7 10 9 12 11 14 13 15 VDD = PIN 16 VSS = PIN 8 REV 3 1/94 ©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA MC14572UB 1 ÎÎÎÎEÎÎÎÎLEÎÎÎÎCTRÎÎÎÎICAÎÎÎÎL CÎÎÎÎHAÎÎÎÎRACÎÎÎÎTEÎÎÎÎRISÎÎÎÎTICÎÎÎÎS (VÎÎÎÎoltagÎÎÎÎesVRÎÎÎÎDefDeÎÎÎÎrencÎÎÎÎedtoÎÎÎΖV5S5ÎÎÎÎS_C) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ25_ÎÎÎÎC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ125ÎÎÎÎ_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 — 0.05 — 10 — 0.05 — 15 — 0.05 — 0 0.05 — 0.05 Vdc 0 0.05 — 0.05 0 0.05 — 0.05 Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 10 9.95 — 9.95 10 15 14.95 — 14.95 15 — 4.95 — Vdc — 9.95 — — 14.95 — Input Voltage “0” Level VIL (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) IOH Source 5.0 — 1.0 10 — 2.0 15 — 2.5 5.0 4.0 — 10 8.0 — 15 12.5 — 5.0 – 1.2 — 5.0 – 0.25 — 10 – 0.62 — 15 – 1.8 — — 2.25 — 4.50 — 6.75 4.0 2.75 8.0 5.50 12.5 8.25 – 1.0 – 0.2 – 0.5 – 1.5 – 1.7 – 0.36 – 0.9 – 3.5 Vdc 1.0 — 1.0 2.0 — 2.0 2.5 — 2.5 Vdc — 4.0 — — 8.0 — — 12.5 — mAdc — – 0.7 — — – 0.14 — — – 0.35 — — – 1.1 — (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Sink IOL Iin Cin IDD 5.0 0.64 — 0.51 0.88 10 1.6 — 1.3 2.25 15 4.2 — 3.4 8.8 — 0.36 — mAdc — 0.9 — — 2.4 — 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc — — — — 5.0 7.5 — — pF 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc 10 — 0.5 — 0.0010 0.5 — 15 15 — 1.0 — 0.0015 1.0 — 30 Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (1.89 µA/kHz) f + IDD IT = (3.80 µA/kHz) f + IDD IT = (5.68 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. PIN ASSIGNMENT OUTA 1 INA 2 OUTB 3 INB 4 OUTC 5 IN 1C 6 IN 2C 7 VSS 8 16 VDD 15 IN 2F 14 IN 1F 13 OUTF 12 INE 11 OUTE 10 IND 9 OUTD MC14572UB 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH ns 5.0 — 180 360 10 — 90 180 15 — 65 130 Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL ns 5.0 — 100 200 10 — 50 100 15 — 40 80 Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 5 ns tPLH, tPHL = (0.66 ns/pF) CL + 17 ns tPLH, tPHL = (0.5 ns/pF) CL + 15 ns tPLH, ns tPHL 5.0 — 90 180 10 — 50 100 15 — 40 80 * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. PULSE GENERATOR VDD INPUT 16 2 8 VSS OUTPUT 1 CL PULSE GENERATOR VDD INPUT 7 16 6 8 VSS OUTPUT 5 CL PULSE GENERATOR VDD 16 INPUT 14 15 8 VSS OUTPUT 13 CL INPUT OUTPUT 20 ns 90% 50% 10% tPHL 90% 50% 10% tf 90% 50% 10% tPLH 90% 50% 10% tr 20 ns VDD VSS VOH VOL Figure 1. Switching Time Test Circuits and Waveforms MOTOROLA CMOS LOGIC DATA MC14572UB 3 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 –B– 1 8 C L –T– SEATING PLANE F N K E G D 16 PL 0.25 (0.010) M T A S M J 16 PL 0.25 (0.010) M T B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0_ 15_ 0_ 15_ N 0.020 0.040 0.51 1.01 –A– 16 1 H G P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 9 B 8 F C L S –T– SEATING PLANE K J M D 16 PL 0.25 (0.010) M T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0_ 10_ 0_ 10 _ S 0.020 0.040 0.51 1.01 MC14572UB 4 MOTOROLA CMOS LOGIC DATA –A– 16 1 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J 9 –B– P 8 PL 8 0.25 (0.010) M B S G –T– SEATING PLANE K C D 16 PL 0.25 (0.010) M T B S A S F R X 45_ M J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC D◊ATA *MC14572UB/D* MCM1C4157425U7B2U/DB 5

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