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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Industrial Control Unit The MC14500B Industrial Control Unit (ICU) is a single–bit CMOS processor. The ICU is designed for use in systems requiring decisions based on successive single–bit information. An external ROM stores the control program. With a program counter (and output latches and input multiplexers, if required) the ICU in a system forms a stored–program controller that replaces combinatorial logic. Applications include relay logic processing, serial data manipulation and control. The ICU also may control an MPU or be controlled by an MPU. • 16 Instructions • DC to 1.0 MHz Operation at VDD = 5 V • On–Chip Clock (Oscillator) • Executes One Instruction per Clock Cycle • 3 to 18 V Operation • Low Quiescent Current Characteristic of CMOS Devices • Capable of Driving One Low–Power Schottky Load or Two Low–Power TTL Loads over Full Temperature Range DATA 3 D C IEN X1 14 X2 13 OSC I0 7 6 I1 INST I2 5 REG 4 I3 1 RST BLOCK DIAGRAM D C LU D OEN STO STOC MUX C RESULT REG. (RR) X1 — OSCILLATOR OUTPUT X2 — OSCILLATOR INPUT 2 WRITE 16 +V VDD 8 VSS 15 RR 12 JMP 11 RTN 10 FLAG O 9 FLAG F MC14500B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. PIN ASSIGNMENT RST 1 WRITE 2 16 VDD 15 RR DATA 3 14 X1 I3 4 13 X2 I2 5 12 JMP I1 6 11 RTN I0 7 10 FLAG O VSS 8 9 FLAG F REV 3 1/94 ©MMCot1or4o5la0, I0nBc. 1995 306 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DC Supply Voltage – 0.5 to + 18.0 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iin, Iout Input or Output Current (DC or Transient), ± 10 mA per Pin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package† 500 mW ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature – 65 to + 150 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature (8–Second Soldering) 260 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ †Temperature Derating: ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper v v operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic VDD – 55_C 25_C 125_C Symbol Vdc Min Max Min Typ # Max Min Max ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VDD or 0 “0” Level VOL 5.0 — 0.05 — 10 — 0.05 — 15 — 0.05 — 0 0.05 — 0.05 0 0.05 — 0.05 0 0.05 — 0.05 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 10 9.95 — 9.95 10 15 14.95 — 14.95 15 — 4.95 — — 9.95 — — 14.95 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage “0” Level VIL RST, D, X2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0 (VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ “1”Level VIH (VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 — (VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage # “0” Level VIL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I0, I1, I2, I3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 4.5 or 0.5 Vdc) 5.0 — 0.8 — 1.1 0.8 — 0.8 (VO = 9.0 or 1.0 Vdc) 10 — 1.6 — 2.2 1.6 — 1.6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 13.5 or 1.5 Vdc) 15 — 2.4 — 3.4 2.4 — 2.4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ “1”Level VIH (VO = 0.5 or 4.5 Vdc) 5.0 2.0 — 2.0 1.9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 or 9.0 Vdc) 10 6.0 — 6.0 3.1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.5 or 13.5 Vdc) 15 10 — 10 4.3 — 2.0 — — 6.0 — — 10 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current Data, Write ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 4.6 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.4 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source IOH Sink IOL 5.0 – 1.2 — – 1.0 – 2.0 10 – 3.6 — – 3.0 – 6.0 15 – 7.2 — – 6.0 – 12 5.0 1.9 — 1.6 3.2 10 3.6 — 3.0 6.0 15 7.2 — 6.0 12 — – 0.7 — — – 2.1 — — – 4.2 — — 1.1 — — 2.1 — — 4.2 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Other Outputs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 9.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 13.5 Vdc) Source IOH 5.0 – 3.0 — – 2.4 – 4.2 5.0 – 0.64 — – 0.51 – 0.88 10 – 1.6 — – 1.3 – 2.25 15 – 4.2 — – 3.4 – 8.8 — – 1.7 — — – 0.36 — — – 0.9 — — – 2.4 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 1.5 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 10 1.6 — 1.3 2.25 15 4.2 — 3.4 8.8 — 0.36 — — 0.9 — — 2.4 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Unit Vdc Vdc Vdc Vdc Vdc Vdc mAdc mAdc mAdc mAdc MOTOROLA CMOS LOGIC DATA MC14500B 307 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic VDD –55_C 25_C 125_C Symbol Vdc Min Max Min Typ # Max Min Max ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Current, RST Iin 15 25 — — 150 — — 250 Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Capacitance (Data) Cin — — — — 15 — — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Capacitance (All Other Inputs) Cin — — — — 5.0 7.5 — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Quiescent Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Per Package) Iout = 0 µA, Vin = 0 or VDD IDD 5.0 — 5.0 — 0.005 5.0 — 150 10 — 10 — 0.010 10 — 300 15 — 20 — 0.015 20 — 600 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ **Total Supply Current at an IT — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ External Load Capacitance (CL) on All Outputs IT = (1.5 µA/kHz) f + IDD IT = (3.0 µA/kHz) f + IDD IT = (4.5 µA/kHz) f + IDD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ **The formulas given are for the typical characteristics only at 25_C. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Unit µAdc µAdc pF pF µAdc µAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (TA = 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F; ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ CL = 130 pF + 1 TTL load for Data and Write.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Symbol VDD Vdc All Types Min Typ # Max Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time, X1 to RR tPLH, 5.0 — 250 500 ns tPHL 10 — 125 250 15 — 100 200 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ X1 to Flag F, Flag O, RTN, JMP 5.0 — 200 400 10 — 100 200 15 — 85 170 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ X1 to Write 5.0 — 225 450 10 — 125 250 15 — 100 200 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ X1 to Data 5.0 — 250 500 10 — 120 240 15 — 100 200 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RST to RR 5.0 — 250 500 10 — 125 250 15 — 100 200 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RST to X1 5.0 — 450 Note 1 10 — 200 15 — 150 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RST to Flag F, Flag O, RTN, JMP 5.0 — 400 800 10 — 200 400 15 — 150 300 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RST to Write, Data 5.0 — 450 900 10 — 225 450 15 — 175 350 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width, X1 tW(cl) 5.0 400 200 10 200 100 15 180 90 — ns — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Rent Pulse Width, RST tW(R) 5.0 500 250 10 250 125 15 200 100 — ns — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Time — Instruction tsu(l) 5.0 400 200 10 250 125 15 180 90 — ns — — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Data tsu(D) 5.0 200 100 — 10 100 50 — 15 80 40 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Time — Instruction th(l) 5.0 100 0 — ns 10 50 0 — 15 50 0 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Data th(D) 5.0 200 100 — 10 100 50 — 15 100 50 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE 1. Maximum Reset Delay may extend to one–half clock period. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MC14500B 308 MOTOROLA CMOS LOGIC DATA f Clk , CLOCK FREQUENCY (Hz) 1M 100 k 10 k ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10kΩ 100 kΩ 1 MΩ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RC, CLOCK FREQUENCY RESISTOR ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 1. Typical Clock Frequency ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ versus Resistor (RC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Chip Reset Write Pulse Data In/Out MSB Instruction Word Bit 2 Instruction Word Bit 1 Instruction Word LSB Instruction Word Negative Supply (Ground) Flag on NOP F Flag on NOP O Subroutine Return Flag Jump Instruction Flag Oscillator Input Oscillator Output Result Register Positive Supply ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Instruction Code ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 0 0000 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 1 0001 2 0010 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 3 0011 4 0100 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 5 0101 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6 0110 7 0111 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 8 1000 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 9 1001 A 1010 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ B 1011 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ C 1100 D 1101 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ E 1110 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ F 1111 Table 1. MC14500B Instruction Set Mnemonic NOPO LD LDC AND ANDC OR ORC XNOR STO STOC IEN OEN JMP RTN SKZ NOPF Action ³ ³ No change in registers. RR RR, Flag O ³ Load result register. Data RR ³ Load complement. Data RR ³ Logical AND. RR  Data RR ³ Logical AND complement. RR  Data RR ³ Logical OR. RR + Data RR ³ Logical OR complement. RR + Data RR ³ Exclusive NOR. If RR = Data, RR 1 ³ ³ Store. RR Data Pin, Write ³ ³ Store complement. RR Data Pin, Write ³ Input enable. Data IEN Register ³ Output enable. Data OEN Register ³ Jump. JMP Flag ³ Return. RTN Flag and skip next instruction ³ ³ Skip next instruction if RR = 0 No change in registers. RR RR, Flag F Symbols RST Write Data I3 I2 I1 I0 VSS Flag F Flag O RTN JMP X2 X1 RR VDD ADDITIONAL OUTPUT DEVICES MEMORY I/O ADDRESS MC14599B 8–BIT ADDRESSABLE LATCH WITH BIDIRECTIONAL DATA 8 OUTPUTS MC14512 8–CHANNEL DATA SELECTOR 8 INPUTS TO PERIPHERAL DEVICES MEMORY ADDRESS 4 BIT OP CODE DATA BUS PROGRAM COUNTER CLOCK I0, I1, I2, I3 MC14500B ICU DATA ADDITIONAL INPUT DEVICES Figure 2. Outline of a Typical Organization for a MC14500B–Based System MOTOROLA CMOS LOGIC DATA MC14500B 309 X1 RST IEN REGISTER OEN REGISTER RR 4–BIT INSTRUCTION FLAG 0 FLAG F TIMING WAVEFORMS Instructions NOPO, NOPF Instructions RR, IEN, OEN remain unaffected tW(R) tPHL (RESET TO XI) tPHL (RESET TO RR) NOP0 NOPF tPLH tPHL (DATA TO FLAG) NOPO Instructions SKZ, JMP, RTN Instructions RR, IEN, OEN remain unaffected X1 tW(cl) 4–BIT INSTRUCTION SKZ * JMP RTN * JMP RST RR JMP FLAG RTN FLAG SKP F/F INTERNAL * Instructions Ignored. tPHL (RESET TO JUMP) MC14500B 310 MOTOROLA CMOS LOGIC DATA TIMING WAVEFORMS Instructions STO, STOC, OEN X1 4–BIT INSTRUCTION DATA SSTTÉÉÉÉOOC ÉÉÉÉÉÉÉÉÉÉÉÉ1 ÉÉÉÉSSTTOOÉÉÉÉC NOP OEN RR OEN REGISTER (INTERNAL) tPLH, tPHL (X1 TO DATA) WRITE tPHL tPLH NOTE 1. Valid output data. STO STOC VALID WHEN RST = L X1 4–BIT INSTRUCTION DATA RR IEN REGISTER (INTERNAL) Instructions LD, LDC, AND, ANDC Instructions OR, ORC, XNOR, IEN LD, etc. tsu(I) NOP IEN th(I) tsu(D) th(D) tPLH, tPHL (X1 TO RR) LD, etc. VALID WHEN RST = L MOTOROLA CMOS LOGIC DATA MC14500B 311 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 –B– 1 8 C L –T– SEATING PLANE F N K E G D 16 PL 0.25 (0.010) M T A S M J 16 PL 0.25 (0.010) M T B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0_ 15_ 0_ 15_ N 0.020 0.040 0.51 1.01 –A– 16 1 H G P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 9 B 8 F C L S –T– SEATING PLANE K J M D 16 PL 0.25 (0.010) M T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0_ 10_ 0_ 10 _ S 0.020 0.040 0.51 1.01 MC14500B 312 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS –A– 16 9 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–02 ISSUE A –B– 8X P 0.010 (0.25) M B M 1 8 J 16X D 0.010 (0.25) M T A S B S F 14X G C –T– K SEATING PLANE R X 45_ M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC D◊ATA *MC14500B/D* MCM1C4510405B0/0DB 313

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