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4033 CMOS 十进制计数器-消隐7段显示.pdf

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4033 CMOS 十进制计数器-消隐7段显示.pdf

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CD4033BMS December 1992 CMOS Decade Counter/Divider Features Description • High Voltage Types (20V Rating) • Decoded 7 Segment Display Outputs and Ripple Blanking • Counter and 7 Segment Decoding in One Package • Easily Interfaced with 7 Segment Display Types • Fully Static Counter Operation DC to 6MHz (typ.) at VDD = 10V • Ideal for Low-Power Displays • “Ripple Blanking” and Lamp Test • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Schmitt-Triggered Clock Inputs • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s Applications CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. This device is particularly advantageous in display applications where low power dissipation and/or low package count is important. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment outputs go high on selection. • Decade Counting 7 Segment Decimal Display • Frequency Division 7 Segment Decimal Displays • Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/ Display • Counter/Display Driver For Meter Applications Pinout CD4033BMS TOP VIEW CLOCK 1 CLOCK INHIBIT 2 RIPPLE BLANKING IN 3 RIPPLE BLANKING OUT 4 CARRY OUT 5 f6 g7 VSS 8 16 VDD 15 RESET 14 LAMP TEST 13 c 12 b 11 e 10 a 9d Functional Diagram VDD 16 1 CLOCK 2 CLOCK INHIBIT 15 RESET 14 LAMP TEST 3 RIPPLE BLK IN 10 a 7 DECODED OUTPUTS 12 b 13 c 9d 11 e 6f 7g 8 VSS 5 CARRY OUT 4 RIPPLE BLK OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-826 File Number 3301 CD4033BMS The CD4033BMS has provisions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be displayed as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the CD4033BMS associated with the most significant digit in the display to a low-level voltage and connecting the RBO terminal of that stage to the RBI terminal of the CD4033BMS in the next-lower significant position in the display. This procedure is continued for each succeeding CD4033BMS on the interger side of the display. On the fraction side of the display the RBI of the CD4033BMS associated with the least significant bit is connected to a low-level voltage and the RBO of that CD4033BMS is connected to the RBI terminal of the CD4033BMS in the next more-significant-bit position. Again, this procedure is continued for all CD4033BMS’s on the fraction side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more-significant-stage). For example: optional zero → 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the CD4033BMS associated with it to a high-level voltage. Ripple blanking of non-significant zeros provides an appreciable savings in display power. The CD4033BMS has a LAMP TEST input which, when connected to a high-level voltage, overrides normal decoder operation and enables a check to be made on possible display malfunctions by putting the seven outputs in the high state. The CD4033BMS are supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H2R H6W Logic Diagram *LAMP TEST 14 DQ CL CL Q 15* R DQ CL CL Q R DQ CL CL Q R DQ CL CL Q R DQ CL CL Q R RESET COUT (CLOCK ÷ 10) 5 10 a 12 b 1 *CLOCK *CLOCK CL INHIBIT 2 3 *RBI 16 VDD 8 GND *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK VDD VSS FIGURE 1. CD4033BMS a fg e d b SEGMENT DESIGNATIONS c 13 c 9 d 11 e 6 f 7 g 4 RBO 7-827 Specifications CD4033BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja Ceramic DIP and FRIT Package . . . . . 80oC/W θjc 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE LIMITS MIN MAX UNITS Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 VDD = 20V, VIN = VDD or GND 7 +25oC +25oC VOH > VOL < V VDD/2 VDD/2 VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit implemented. is 0.050V max. 2. Go/No Go test with limits applied to inputs. 7-828 Specifications CD4033BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock To Carry Out Propagation Delay Clock To Decode Out Propagation Delay Reset To Carry Out Propagation Delay Reset To Decode Out Transition Time Maximum Clock Input Frequency SYMBOL CONDITIONS (NOTE 1, 2) TPHL1 VDD = 5V, VIN = VDD or GND TPLH1 TPHL2 VDD = 5V, VIN = VDD or GND TPLH2 TPLH3 VDD = 5V, VIN = VDD or GND TPHL4 VDD = 5V, VIN = VDD or GND TPLH4 TTHL VDD = 5V, VIN = VDD or GND TTLH FCL VDD = 5V, VIN = VDD or GND GROUP A SUBGROUPS TEMPERATURE 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC 9 +25oC 10, 11 +125oC, -55oC NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. LIMITS MIN MAX - 500 - 675 - 700 - 945 - 550 - 743 - 600 - 810 - 200 - 270 2.5 - 1.85 - UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL CONDITIONS IDD VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VDD = 5V, No Load VOL VDD = 10V, No Load VOH VDD = 5V, No Load VOH VDD = 10V, No Load IOL5 VDD = 5V, VOUT = 0.4V Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC LIMITS MIN MAX - 5 - 150 - 10 - 300 - 10 - 600 - 50 - 50 4.95 - 9.95 - 0.36 - 0.64 - 0.9 - 1.6 - 2.4 - 4.2 - - -0.36 - -0.64 - -1.15 - -2.0 - -0.9 - -2.6 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA 7-829 Specifications CD4033BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V Propagation Delay Clock To Carry Out Propagation Delay Clock To Decode Out Propagation Delay Reset To Carry Out Propagation Delay Reset To Decode Out Transition Time Maximum Clock Input Frequency Minimum Reset Pulse Width Minimum Reset Removal Time Minimum Clock Pulse Width Input Capacitance TPHL1 TPLH1 TPHL2 TPLH2 TPLH3 TPHL4 TPLH4 TTHL TTLH FCL TW TREM TW CIN VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Any Input NOTES 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE MIN +125oC - -55oC - +25oC, +125oC, - -55oC +25oC, +125oC, +7 -55oC +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC 5.5 +25oC 8 +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - +25oC - MAX -2.4 -4.2 3 UNITS mA mA V - V 200 ns 150 ns 250 ns 180 ns 240 ns 160 ns 250 ns 180 ns 100 ns 50 ns - MHz - MHz 120 ns 100 ns 50 ns 30 ns 15 ns 10 ns 220 ns 100 ns 80 ns 7 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA NOTES 1, 4 1, 4 1, 4 TEMPERATURE MIN +25oC - +25oC -2.8 +25oC - MAX 25 -0.2 ±1 VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 1, 4 +25oC - ±1 F VDD = 18V, VIN = VDD or GND 1 VDD = 3V, VIN = VDD or GND +25oC VOH > VOL < VDD/2 VDD/2 UNITS µA V V V V V 7-830 Specifications CD4033BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Propagation Delay Time SYMBOL CONDITIONS TPHL VDD = 5V TPLH NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 2, 3, 4 TEMPERATURE MIN +25oC - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 1.35 x +25oC Limit UNITS ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD TEST PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 READ AND RECORD PRE-IRRAD POST-IRRAD 1, 9( Table 4 FUNCTION OPEN PART NUMBER Static Burn-In 1 (Note 1) 4 - 7, 9 - 14 Static Burn-In 2 (Note 1) 1, 2, 14, 15 Dynamic Burn- - In (Note 1) Irradiation (Note 2) 4 - 7, 9 - 14 PART NUMBER CD4033BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS GROUND VDD 9V ± -0.5V OSCILLATOR 50kHz 25kHz 1 - 3, 8, 15 16 3 - 6, 8, 10 - 13 7, 9, 16 2, 8, 15 3, 16 4 - 7, 9 - 13 1 8 1 - 3, 15, 16 7-831 Specifications CD4033BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Static Burn-In 1 4 - 7, 9 - 13 1 - 3, 8, 14, 15 16 Note 1 Static Burn-In 2 Note 1 4 - 7, 9 - 13 8 1 - 3, 14 - 16 Dynamic Burn- - 2, 3, 8, 14, 15 16 4 - 7, 9 - 13 1 In Note 1 Irradiation Note 2 4 - 7, 9 - 13 8 1 - 3, 14 - 16 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Timing Diagram CLOCK RESET CLOCK INHIBIT LAMP TEST RBI COUT (CLOCK ÷ 10) a b c d e f g RBO 0 1 234 5 6 78 9 0 1 8 4 56 7 8 9 12 FIGURE 2. CD4033BMS TIMING DIAGRAM R CL p D n CL CL p DQ n CL Q ≡ R CL CL CL CL p n CL CL Q Q CL p n CL FIGURE 3. DETAIL OF TYPICAL FLIP-FLOP STAGE 7-832 CD4033BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -10V -15V 0 0 -5 -10 -15 -20 -25 -30 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 5. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) PROPAGATION DELAY TIME (tPLH, tPHL) (µs) FIGURE 6. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 600 400 SUPPLY VOLTAGE (VDD) = 5V 200 10V 15V 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR DECODED OUTPUTS PROPAGATION DELAY TIME (tPLH, tPHL) (µs) FIGURE 7. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FOR CARRY-OUT OUTPUTS 7-833 CD4033BMS Typical Performance Characteristics (Continued) MAXIMUM CLOCK INPUT - FREQUENCY (fCL) (MHz) POWER DISSIPATION (PD) (µW) 20 AMBIENT TEMPERATURE (TA) = +25oC tr = tf = 20ns 15 10 5 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (VDD) (V) FIGURE 10. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 105 8 6 AMBIENT TEMPERATURE (TA) = +25oC 4 2 104 8 6 4 SUPPLY VOLTAGE (VDD) = 5V 2 103 8 6 4 2 102 8 6 4 2 10 2 1 10V 10V 15V (CL) = 15pF LOAD CAPACITANCE (CL) = 50pF 4 68 2 4 68 2 4 68 2 4 68 2 4 68 10 102 103 104 105 INPUT PULSE FREQUENCY (fCL) (MHz) FIGURE 11. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY Light Emitting Diode Displays MONSANTO MAN 3 OR EQUIVALENT (LOW POWER) VDD IB VDD 1/7 CA3082 OR EQUIVALENT CLOCK INHIBIT RESET CD4033BMS 7 SEGMENTS A A R IB G MAN 3 A IF VDD ≥ 3.5V IF ≈ 5mA/SEGMENT 100% DUTY CYCLE VP - VBE - VF(LED) R= ILED VSS G R G WHERE VP = INPUT PULSE VF = FORWARD DROP ACROSS DIODE MONSANTO MAN 1 OR EQUIVALENT VDD 1/7 CA3082 OR EQUIVALENT VDD AR MAN 1 R A CLOCK INHIBIT RESET CD4033BMS 7 SEGMENTS A IB GG R VSS IB IF R G VDD 5V (MIN) IB 0.4mA IF 12mA/Seg.(100% DUTY CYCLE) bdc(MIN) 30 VCE(SAT) £ 0.5V VDD - VCE(sat)-VF(LED) R= ILED WHERE VF = FORWARD DROP ACROSS DIODE FIGURE 12. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE LIGHT EMITTING DIODE DISPLAYS 7-834 CD4033BMS 7-Segment Display Devices VDD 1/7 SEGMENTS IB VT IT CLOCK INHIBIT RESET CD4033BMS 7 SEGMENTS VSS 1/7 CA3081 OR EQUIVALENT VT VCC 1 OF 7 SEGMENTS 1/6 CA4049UB IT INCANDESCENT READOUTS Numitron DR2000 Series TUBE REQUIREMENTS VT = 3.5 - 5V IT = 24mA Segment ASSUMED TRANSISTOR CHARACTERISTICS βdc (min) ≥ 25 VCE (sat) ≤ 0.5V VDD = 8V (min) IB = 1mA (min) IT = 24mA (min) CD4049UB at VCC = 10V (min) Vo “0” ≤ 2V IT = 8mA (min) VT ≈ 3.5V to 6V CD4049UB at VCC = 10V (min) Vo “0” ≤ 0.6V IT = 8mA (min) LOW-POWER INCANDESCENT READOUTS PINLITES INC-Series O and R TUBE REQUIREMENTS 0-03-15 0-04-30 0-06-30 R-R3-20 R-R4-30 VT(V) 1.5 3 3 2 3 mA/Segment 8 8 8 4.3 4.3 ASSUMED TRANSISTOR CHARACTERISTICS βdc (min) ≥ 30 VCE (sat) ≤ 0.5V VCC ≥ 3.5V (min) IB ≥ 0.25mA (min) IT ≤ 7.5mA (min) at VCC = 6V (min) Vo “0” ≤ 1V IT = 5mA (min) VT ≈ 1.5V to 3.5V *The interfacing buffers shown, while a necessity with the CD4033A, are not required when using the “B” devices; the “B” outputs (≈ 10 times the “A” outputs) can drive most display devices directly especially at voltages above 10V. VDD VT ª 170V DC 1 OF 7 SEGMENTS VDD CLOCK INHIBIT RESET CD4033BMS 7 SEGMENTS VSS CLOCK 13.5V INHIBIT LOGIC RESET VOLTAGE CD4033BMS 7 SEGMENTS VSS ≈ 4.5V edc f b g a NEON READOUT (NIXIE TUBE**) 1. Alco Electronics - MG19 2. Burroughs - B5971, B7971, B8971 WITH VON = 18V MEDIUM BRIGHTNESS IN LOW AMBIENT LIGHT BACKGROUND WILL RESULT. THE POINT OF NO NOTICEABLE GLOW IS VOFF ≈ 4.5V 1.6V AC OR DC TUBE REQUIREMENTS Alco MG19 Burroughs B5971 Burroughs B7971, B8971 VT(Vdc) 180 170 170 **(Trademark) Burroughs Corp. TRANSISTOR CHARACTERISTICS Leakage with transistor cutoff - 0.05mA V(BR)CER >VT βdc (min) ≥ 30 mA/Segment 0.5 3 6 LOW VOLTAGE VACUUM FLORESCENT READOUTS 1. Tung-Sol DIGIVAC S/G ‡ Type DT1704A or DT1705C 2. Nippon Electric (NEC): Type DG12E or LD915 TUBE REQUIREMENTS: 100 to 300 µA/segment at tube voltages of 12V to 25V depending on required brightness Filament requirement 45mA at 1.6V, ac or dc. ‡ (Trademark) Wagner Electric Co. FIGURE 13. INTERFACING THE CD4033BMS WITH COMMERCIALLY AVAILABLE 7-SEGMENT DISPLAY DEVICES* 7-835 CD4033BMS Chip Dimensions and Pad Layouts Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 836

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