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Rev. 0.0, Jan.2009 S5PV210 RISC Microprocessor Revision 1.00 February 2010 User's Manual © 2010 Samsung Electronics Co., Ltd. All rights reserved. Rev. 0.0, Jan.2009 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S5PV210 RISC Microprocessor User's Manual, Revision 1.00 Copyright © 2010 Samsung Electronics Co., Ltd. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City, Gyeonggi-Do, Korea 446-711 TEL : (82)-(31)-209-0810 FAX : (82)-(31)-209-0837 Home Page: http://www.samsungsemi.com Printed in the Republic of Korea Rev. 0.0, Jan.2009 Revision History Revision No. 0.00 Date February 27, 2010 - Initial draft Description Author(s) S.H Yoon Section 1 OVERVIEW Table of Contents 1 Overview of S5PV210.................................................................................1-1 1.1 Architectural Overview ............................................................................................................................. 1-1 1.2 Block Diagram of S5PV210 ..................................................................................................................... 1-2 1.3 Key Features of S5PV210 ....................................................................................................................... 1-3 1.3.1 Microprocessor ................................................................................................................................. 1-4 1.3.2 Memory Subsystem .......................................................................................................................... 1-5 1.3.3 Multimedia ........................................................................................................................................ 1-6 1.3.4 Audio Subsystem.............................................................................................................................. 1-9 1.3.5 Security Subsystem .......................................................................................................................... 1-9 1.3.6 Connectivity .................................................................................................................................... 1-10 1.3.7 System Peripheral .......................................................................................................................... 1-13 1.4 Conventions ........................................................................................................................................... 1-15 1.4.1 Register R/W Conventions ............................................................................................................. 1-15 1.4.2 Register Value Conventions ........................................................................................................... 1-15 2 Memory Map ...............................................................................................2-1 2.1 Memory Address Map.............................................................................................................................. 2-1 2.1.1 Device Specific Address Space........................................................................................................ 2-2 2.1.2 Special Function Register Map......................................................................................................... 2-4 3 SIZE & BALL MAP .........................................................................................1 3.1 Pin Assignment ............................................................................................................................................1 3.1.1 Pin Assignment Diagram - 584-ball FCFBGA ......................................................................................1 3.1.2 Pin Number Order.................................................................................................................................2 3.1.3 Power Pins..........................................................................................................................................10 3.2 Pin Discription ........................................................................................................................................ 3-13 3.2.1 Power Domain ................................................................................................................................ 3-38 3.2.2 Package Dimension........................................................................................................................ 3-51 List of Figures Figure Number Title Page Number Figure 1-1 S5PV210 Block Diagram .................................................................................................................. 1-2 Figure 2-1 Address Map..................................................................................................................................... 2-1 Figure 2-2 Internal Memory Address Map.......................................................................................................... 2-3 Figure 3-1 Figure 3-2 Figure 3-3 S5PV210 Pin Assignment (584-FCFBGA) Bottom View ......................................................................1 S5PV210 Package Dimension (584-FCFBGA) − Top View ........................................................... 3-51 S5PV210 Package Dimension (584-FCFBGA) − Side View .......................................................... 3-52 List of Tables Table Number Title Page Number Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (1/4) .....................................................2 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (2/4) .....................................................4 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (3/4) .....................................................6 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (4/4) .....................................................8 S5PV210 Power Pin to Ball Assignment (1/2) .....................................................................................10 S5PV210 Power Pin to Ball Assignment (2/2) .....................................................................................12 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1 OVERVIEW OF S5PV210 1.1 ARCHITECTURAL OVERVIEW S5PV210 is a 32-bit RISC cost-effective, low power, and high performance microprocessor solution for mobile phones and general applications. It integrates the ARM Cortex-A8 core, which implements the ARM architecture V7-A with supporting peripherals. To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PV210 adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as motion video processing, display control, and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG-1/2/4, H.263, and H.264, and decoding of VC1 and Divx. This hardware accelerator (MFC) supports real-time video conferencing and Analog TV out, HDMI for NTSC, and PAL mode. S5PV210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths. DRAM controller supports LPDDR1 (mobile DDR), DDR2, or LPDDR2. Flash/ ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory. To reduce the total system cost and enhance the overall functionality, S5PV210 includes many hardware peripherals such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for power management, ATA interface, four UARTs, 24-channel DMA, four Timers, General I/O Ports, three I2S, S/PDIF, three IIC-BUS interface, two HS-SPI, USB Host 2.0, USB 2.0 OTG operating at high speed (480Mbps), four SD Host and high-speed Multimedia Card Interface, and four PLLs for clock generation. Package on Package (POP) option with MCP is available for small form factor applications. 1-1 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.2 BLOCK DIAGRAM OF S5PV210 Figure 1-1 shows the complete block diagram of S5PV210. System Peripheral RTC PLL x4 Timer with PWM(4ch) Watchdog Timer DMA ( 24ch) Keypad(14x8) TS- ADC(12bit/10ch) CPU Core CortexA8 32KB/32KB I/ D cache 800MHz/1 GHz @ 1.1V/1.2V 512KB L 2 cache NEON Connectivity Audio IF IIS x 3 / PCM x3 SPDIF / AC97 Storage IF HSMMC/ SD x4 ATA Connectivity USB Host 2. 0 / OTG2.0 UART x4 IIC x 3 HS- SPI x2 Modem IF(16KB DPSRAM ) GPIO 96 KB RAM 64 KB ROM Multi layer AHB / AXI Bus Crypto Engines Audio DSP Power Management Clock gating/ Power gating/ Dynamic Voltage Frequency Scaling Multimedia 12 MP Camera IF/ MIPI CSI-2 1080p 30 fps MFC Codec H. 263/H. 264/ MPEG4 Decoder MPEG2/VC-1/ Divx 2 D VG / 3 D Graphics engine NTSC / PAL TV out & HDMI JPEG Codec TFT LCD controller XGA resolution Memory Interface SRAM / ROM ( Flex) OneNAND SLC / MLC NAND with 16 bit ECC LPDDR1 / OneDRAM LPDDR2 / DDR2 Figure 1-1 S5PV210 Block Diagram 1-2 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3 KEY FEATURES OF S5PV210 The key features of S5PV210 include: • ARM CortexTM-A8 based CPU Subsystem with NEON − 32/ 32 KB I/D Cache, 512 KB L2 Cache − Operating frequency up to 800 MHz at 1.1V, 1 GHz at 1.2V • 64-bit Multi-layer bus architecture − MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller • Operating frequency up to 200 MHz at 1.1V − DSYS domain mainly for Display IPs (such as LCD controller, Camera interface, and TVout), and MDMA • Operating frequency up to 166 MHz at 1.1V − PSYS domain mainly for other system component such as system peripherals, external memory interface, peri DMAs, connectivity IPs, and Audio interfaces. • Operating frequency up to 133 MHz at 1.1V − Audio domain for low power audio play • Advanced power management for mobile applications • 64 KB ROM for secure booting and 128 KB RAM for security function • 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution • Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30fps and decoding of MPEG-2/VC1/Divx video up to 1080p@30 fps • JPEG codec supports up to 80 Mpixels/s • 3D Graphics Acceleration with Programmable Shader up to 20M triangles/s and 1000 Mpixels/s • 2D Graphics Acceleration up to 160Mpixels/s • 1/ 2/ 4/ 8 bpp Palletized or 8/ 16/ 24 bpp Non-Palletized Color TFT recommend up to XGA resolution • TV-out and HDMI interface support for NTSC and PAL mode with image enhancer • MIPI-DSI and MIPI-CSI interface support • One AC-97 audio codec interface and 3-channel PCM serial audio interface • Three 24-bit I2S interface support • One TX only S/PDIF interface support for digital audio • Three I2C interface support • Two SPI support • Four UART supports three Mbps ports for Bluetooth 2.0 • On-chip USB 2.0 OTG supports high-speed (480 Mbps, on-chip transceiver) • On-chip USB 2.0 Host support • Asynchronous Modem Interface support • Four SD/ SDIO/ HS-MMC interface support • ATA/ ATAPI-6 standard interface support 1-3 S5PV210_UM 1 0BOVERVIEW OF S5PV210 • 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) • Supports 14x8 key matrix • 10-channel 12-bit multiplexed ADC • Configurable GPIOs • Real time clock, PLL, timer with PWM and watch dog timer • System timer support for accurate tick time in power down mode (except sleep mode) • Memory Subsystem − Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus − NAND Interface with x8 data bus − Muxed/ Demuxed OneNAND Interface with x16 data bus − LPDDR1 Interface with x16 or x32 data bus (266~400 Mbps/ pin DDR) − DDR2 interface with x16 or x32 data bus (400 Mbps/ pin DDR) − LPDDR2 interface (400 Mbps/ pin DDR) 1.3.1 MICROPROCESSOR The key features of this microprocessor include: • The ARM CortexTM-A8 processor is the first application processor based on ARMv7 architecture. • With the ability to scale in speed from 600 MHz to 1 GHz (or more), the ARM CortexTM-A8 processor meets the requirements of power-optimized mobile devices, which require operation in less than 300mW; and performance-optimized consumer applications require 2000 Dhrystone MIPS. • Supports first superscalar processor featuring technology from ARM for enhanced code density and performance, NEONTM technology for multimedia and signal processing, and Jazelle® RCT technology for ahead-of-time and just-in-time compilation of Java and other byte code languages. • Other features of ARM CortexTM-A8 include: − Thumb-2 technology for greater performance, energy efficiency, and code density − NEONTM signal processing extensions − Jazelle RCT Java-acceleration technology − TrustZone technology for secure transactions and DRM − 13-stage main integer pipeline − 10-stage NEONTM media pipeline − Integrated L2 Cache using standard compiled RAMs − Optimized L1 caches for performance and power 1-4 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3.2 MEMORY SUBSYSTEM The key features of memory subsystem include: • High bandwidth Memory Matrix subsystem • Two independent external memory ports (1 x16 Static Hybrid Memory port and 2 x32 DRAM port) • Matrix architecture increases the overall bandwidth with simultaneous access capability − SRAM/ ROM/ NOR Interface o x8 or x16 data bus o Address range support: 23-bit o Supports asynchronous interface o Supports byte and half-word access − OneNAND Interface o x16 data bus o Address range support: 16-bit o Supports byte and half-word access o Supports 2 KB page mode for OneNAND and 4 KB page mode for Flex OneNAND o Supports dedicated DMA − NAND Interface o Supports industry standard NAND interface o x8 data bus − LPDDR1 Interface o x32 data bus with 400 Mbps/ pin Double Data Rate (DDR) o 1.8V interface voltage o Density support up to 4-Gb per port (2CS) − DDR2 Interface o x32 data bus with 400 Mbps/ pin double data rate (DDR) o 1.8V interface voltage o Density support up to 1-Gb per port (2CS, when 4bank DDR2) o Density support up to 4-Gb per port (1CS, when 8bank DDR2) − LPDDR2 interface o x32 data bus with up to 400 Mbps/pin o 1.2V interface voltage o Density support up to 4-Gb per port (2CS) 1-5 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3.3 MULTIMEDIA The key features of multimedia include: • Camera Interface − Multiple input support o ITU-R BT 601/656 mode o DMA (AXI 64-bit interface) mode o MIPI (CSI) mode − Multiple output support o DMA (AXI 64-bit interface) mode o Direct FIFO mode − Digital Zoom In (DZI) capability − Multiple camera input support − Programmable polarity of video sync signals − Input horizontal size support up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution − Image mirror and rotation (X-axis mirror, Y-axis mirror, 90°, 180°, and 270° rotation) − Various image formats generation − Capture frame control support − Image effect support • Multi-Format video Codec (MFC) − ITU-T H.264, ISO/IEC 14496-10 o Decoding supports Baseline/ Main/ High Profile Level 4.0 (except Flexible Macro-block Ordering (FMO), Arbitrary Slice Ordering (ASO) and Redundant Slice (RS)) o Encoding supports Baseline/ Main/ High Profile (except FMO, ASO, and RS) − ITU-T H.263 Profile level 3 o Decoding supports Profile3, restricted up to SD resolution 30 fps (H.263 Annexes to be supported) - Annex I: Advanced Intra Coding - Annex J: De-blocking (in-loop) filter - Annex K: Slice Structured Mode without FMO & ASO - Annex T: Modified Quantization - Annex D: Unrestricted Motion Vector Mode - Annex F: Advanced Prediction Mode except overlapped motion compensation for luminance o Encoding supports Baseline Profile (supports customer size up to 1920x1088) − ISO/IEC 14496-2 MPEG-4 and DivX o Decoding supports MPEG-4 Simple/ Advanced Simple Profile Level5 o Decoding supports DivX Home Theater Profile (version 3.xx, 4.xx, 5.xx, and 6.1), Xvid − Encoding supports MPEG-4 Simple/ Advanced Simple Profile 1-6 S5PV210_UM 1 0BOVERVIEW OF S5PV210 − ISO/IEC 13818-2 MPEG-2 o Decoding supports Main Profile High level o Decoding supports MPEG-1 except D-picture − SMPTE 421M VC-1 o Decoding supports Simple Profile Medium Level/ Main Profile High Level/ Advanced Profile Level4 • JPEG Codec − Supports Compression/ decompression up to 65536x65536 − Supported format of compression o Input raw image: YCbCr4:2:2 or RGB565 o Output JPEG file: Baseline JPEG of YCbCr4:2:2 or YCbCr4:2:0 − Supported format of decompression (Refer to Chapter 9.13. JPEG) o Input JPEG file: Baseline JPEG of YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0, or gray o Output raw image: YCbCr4:2:2 or YCbCr4:2:0 − Supports general-purpose color-space converter • 3D Graphic Engine (SGX540) − Supports 3D graphics, vector graphics, and video encode and decode on common hardware − Tile-based architecture − Universal Scalable Shader Engine – multi-threaded engine incorporating Pixel and Vertex Shader functionality − Industry standard API support –OGL-ES 1.1 and 2.0 and OpenVG 1.0 − Fine grained task switching, load balancing, and power management − Advanced geometry DMA driven operation for minimum CPU interaction − Programmable high-quality image anti-aliasing − Fully virtualized memory addressing for functioning of operating system in a unified memory architecture • 2D Graphic Engine − BitBLT − Supports maximum 8000x8000 image size − Window clipping, 90°/180°/270°Rotation, X Flip / Y Flip − Reverse Addressing (X positive/negative, Y positive/negative) − Totally 4-operand raster operation (ROP4) − Alpha blending (fixed alpha value / per-pixel alpha value) − Arbitrary size pixel pattern drawing, Pattern cache − 16/24/32-bpp. Packed 24-bpp color format • Analog TV interface − Out video format: NTSC-M/ NTSC-J/ NTSC4.43/ PAL-B, D, G, H, I/ PAL-M/ PAL-N/ PAL-Nc/ PAL-60 compliant − Supported input format: ITU-R BT.601 (YCbCr 4 :4 :4) − Supports 480i/p and 576i resolutions − Supports Composite/ S-Video/ Component interface 1-7 S5PV210_UM 1 0BOVERVIEW OF S5PV210 • Digital TV Interface − High-definition Multimedia Interface (HDMI) 1.3 − Supports up to 1080p 30Hz and 8-channel/ 112 kHz/ 24-bit audio − Supports 480p, 576p, 720p, 1080i, 1080p (cannot support 480i) − Supports HDCP v1.1 • Rotator − Supported image format: YCbCr422 (interleave), YCbCr420 (non-interleave), RGB565 and RGB888 (unpacked) − Supported rotate degree: 90, 180, 270, flip vertical, and flip horizontal • Video processor: The video processor supports: − BOB/ 2D-IPC mode − Produces YCbCr 4:4:4 output to help the mixer blend video and graphics − 1/4X to 16X vertical scaling with 4-tap/ 16-phase polyphase filter − 1/4X to 16X horizontal scaling with 8-tap/ 16-phase polyphase filter − Pan and scan, Letterbox, and NTSC/ PAL conversion using scaling − Flexible scaled video positioning within display area − 1/16 pixel resolution Pan and Scan modes − Flexible post video processing o Color saturation, Brightness/ Contrast enhancement, Edge enhancement o Color space conversion between BT.601 and BT.709 − Video input source size up to 1920x1080 • Video Mixer The Video Mixer supports: − Overlapping and blending input video and graphic layers − 480i/p, 576i/p, 720p, and 1080i/p display size − Four layers (1 video layer, 2 graphic layer, and 1 background layer) • TFT-LCD Interface The TFT-LCD Interface supports: − 24/ 18/ 16-bpp parallel RGB Interface LCD − 8/ 6 bpp serial RGB Interface − Dual i80 Interface LCD − 1/ 2/ 4/ 8 bpp Palletized or 8/16/24-bpp Non-Palletized Color TFT − Typical actual screen size: 1024x768, 800x480, 640x480, 320x240, 160x160, and so on − Virtual image up to 16M pixel (4K pixel x4K pixel) − Five Window Layers for PIP or OSD − Real-time overlay plane multiplexing − Programmable OSD window positioning − 8-bit Alpha blending (Plane/Pixel) − ITU-BT601/656 format output 1-8 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3.4 AUDIO SUBSYSTEM The key features of audio subsystem include: • Audio processing is progressed by Reconfigurable Processor (RP) • Low power audio subsystem − 5.1ch I2S with 32-bit-width 64-depth FIFO − 128 KB audio play output buffer − Hardware mixer mixes primary and secondary sounds 1.3.5 SECURITY SUBSYSTEM The key features of security subsystem include: • On-chip secure boot ROM − 64 KB secure boot ROM for secure boot • On-chip secure RAM − 128 KB secure RAM for security function • Hardware Crypto Accelerator − Securely integrated DES/ TDES, AES, SHA-1, PRNG and PKA − Access control (Security Domain Manager with the ARM TrustZone Hardware) − Enables enhanced secure platform for separate (secure/ non-secure) execution environment for security sensitive application • Secure JTAG − Authentication of JTAG user − Access control in JTAG mode 1-9 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3.6 CONNECTIVITY The key features of connectivity include: • PCM Audio Interface − 16-bit mono audio interface − Master mode only − Supports three port PCM interface • AC97 Audio Interface − Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In − 16-bit stereo (2-channel) audio − Variable sampling rate AC97 Codec interface (48 kHz and below) − Supports AC97 Full Specification • SPDIF Interface (TX only) − Linear PCM up to 24-bit per sample support − Non-Linear PCM formats such as AC3, MPEG1, and MPEG2 support − 2x24-bit buffers that are alternately filled with data • I2S Bus Interface − Three I2S-bus for audio-codec interface with DMA-based operation − Serial, 8/ 16/ 24-bit per channel data transfers − Supports I2S, MSB-justified, and LSB-justified data format − Supports PCM 5.1 channel − Various bit clock frequency and codec clock frequency support o 16, 24, 32, 48 fs of bit clock frequency o 256, 384, 512, 768 fs of codec clock − Supports one port for 5.1 channel I2S (in Audio Subsystem) and two ports for 2 channel I2S • Modem Interface − Asynchronous direct/ indirect 16-bit SRAM-style interface − On-chip 16 KB dual-ported SRAM buffer for direct interface • I2C Bus Interface − Three Multi-Master IIC-Bus − Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode − Up to 400 Kbit/s in the fast mode • ATA Controller − Compatible with the ATA/ATAPI-6 standard 1-10 S5PV210_UM 1 0BOVERVIEW OF S5PV210 • UART − Four UART with DMA-based or interrupt-based operation − Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/ receive − Rx/Tx independent 256 byte FIFO for UART0, 64 byte FIFO for UART1 and 16 byte FIFO for UART2/3 − Programmable baud rate − Supports IrDA 1.0 SIR (115.2 Kbps) mode − Loop back mode for testing − Non-integer clock divides in Baud clock generation • USB 2.0 OTG − Complies with the OTG Revision 1.0a supplement to the USB 2.0 − Supports high-speed up to 480 Mbps − On-chip USB transceiver • USB Host 2.0 − Complies with the USB Host 2.0 − Supports high-speed up to 480 Mbps − On-chip USB transceiver • HS-MMC/ SDIO Interface − Multimedia Card Protocol version 4.0 compatible (HS-MMC) − SD Memory Card Protocol version 2.0 compatible − DMA based or Interrupt based operation − 128 word FIFO for Tx/Rx − Four ports HS-MMC or four ports SDIO • SPI Interface − Complies with three Serial Peripheral Interface Protocol version 2.11 − Rx/Tx independent 64-Word FIFO for SPI0 and 16-Word FIFO for SPI1 − DMA-based or interrupt-based operation 1-11 S5PV210_UM 1 0BOVERVIEW OF S5PV210 • GPIO − 237 multi-functional input/ output ports − Controls 178 External Interrupts − GPA0: 8 in/out port – 2xUART with flow control − GPA1: 4 in/out port – 2xUART without flow control or 1xUART with flow control − GPB: 8 in/out port – 2x SPI − GPC0: 5 in/out port – I2S, PCM, AC97 − GPC1: 5 in/out port – I2S, SPDIF, LCD_FRM − GPD0: 4 in/out port – PWM − GPD1: 6 in/out port – 3xI2C, PWM, IEM − GPE0,1: 13 in/out port – Camera Interface − GPF0,1,2,3: 30 in/out port – LCD Interface − GPG0,1,2,3: 28 in/out port – 4xMMC channel (Channel 0 and 2 support 4-bit and 8-bit modes, but channel 1 and 3 support only 4-bit mode) − GPH0,1,2,3: 32 in/out port – Key pad, External Wake-up (up-to 32-bit), HDMI − GPI: Low power I2S, PCM − GPJ0,1,2,3,4: 35 in/out port – Modem IF, CAMIF, CFCON, KEYPAD, SROM ADDR[22:16] − MP0_1,2,3: 20 in/out port – Control signals of EBI (SROM, NF, CF, and OneNAND) − MP0_4,5,6,7: 32 in/out memory port – EBI (For more information about EBI configuration, refer to Chapter 5.6. EBI) 1-12 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.3.7 SYSTEM PERIPHERAL The key features of system peripheral include: • Real Time Clock − Full clock features: sec, min, hour, date, day, month, and year − 32.768kHz operation − Alarm interrupt − Time-tick interrupt • PLL − Four on-chip PLLs, APLL/MPLL/EPLL/VPLL − APLL generates ARM core and MSYS clocks − MPLL generates a system bus clock and special clocks − EPLL generates special clocks − VPLL generates clocks for video interface • Keypad − 14x8 Key Matrix support − Provides internal de-bounce filter • Timer with Pulse Width Modulation − Five channel 32-bit internal timer with interrupt-based operation − Three channel 32-bit Timer with PWM − Programmable duty cycle, frequency, and polarity − Dead-zone generation − Supports external clock source • System timer − Accurate timer provides exact 1ms tick at any power mode except sleep − Interrupt interval can be changed without stopping reference tick timer • DMA − Micro-code programming based DMA − The specific instruction set provides flexibility to program DMA transfers − Supports linked list DMA function − Supports three enhanced built-in DMA with eight channels per DMA, so the total number of channels supported are 24 − Supports one Memory-to-memory type optimized DMA and two Peripheral-to-memory type optimized DMA − M2M DMA supports up to 16 burst and P2M DMA supports up to 8 burst • A/D Converter and Touch Screen Interface − 10 channel multiplexed ADC − Maximum 500Ksamples/sec and 12-bit resolution • Watch Dog Timer • 16-bit watch dog timer 1-13 S5PV210_UM 1 0BOVERVIEW OF S5PV210 • Vectored Interrupt Controller − Software such as Interrupt device driver can mask out particular interrupt requests − Prioritization of interrupt sources for interrupt nesting • Power Management − Clock-gating control for components − Various low power modes are available such as Idle, Stop, Deep Stop, Deep Idle, and Sleep modes − Wake up sources in sleep mode are external interrupts, RTC alarm, Tick timer and the key interface. − Stop and Deep Stop mode’s wake up sources are MMC, Touch screen interface, system timer, and entire wake up sources of Sleep mode. − Deep Idle mode’s wake up sources are 5.1ch I2S and wake up source of Stop mode. 1-14 S5PV210_UM 1 0BOVERVIEW OF S5PV210 1.4 CONVENTIONS 1.4.1 REGISTER R/W CONVENTIONS Symbol R W R/W R/WC R/WS Definition Read Only Write Only Read & Write Read & Write to clear Read & Write to set Description The application has permission to read the Register field. Writes to read-only fields have no effect. The application has permission to write in the Register field. The application has permission to read and writes in the Register field. The application sets this field by writing 1’b1 and clears it by writing 1’b0. The application has permission to read and writes in the Register field. The application clears this field by writing 1’b1. A register write of 1'b0 has no effect on this field. The application has permission to read and writes in the Register field. The application sets this field by writing 1’b1. A register write of 1'b0 has no effect on this field. 1.4.2 REGISTER VALUE CONVENTIONS Expression x X ? Device dependent Pin value Description Undefined bit Undefined multiple bits Undefined, but depends on the device or pin status The value depends on the device The value depends on the pin status 1-15 S5PV210_UM 2 MEMORY MAP This chapter describes the memory map available in S5PV210 processor. 2.1 MEMORY ADDRESS MAP 0 xFFFF _ FFFF 0 xE 000 _ 0000 0 xDFFF _ FFFF 0 xD 000 _ 0000 0 xCFFF _ FFFF 0 xC 000 _ 0000 0 xBFFF _ FFFF 0 xB 000 _ 0000 0 xAFFF _ FFFF 0 xA 000 _ 0000 0 x9 FFF _ FFFF 0 x 9000 _ 0000 0 x 8 FFF _ FFFF 0 x 8000 _ 0000 0 x 7 FFF _ FFFF 0 x 6000 _ 0000 0 x 5 FFF _ FFFF SFRS DMZ ROM IROM & IRAM Low Power Audio SRAM ONENAND / NAND SROMC _ BANK 5 SROMC _ BANK 4 SROMC _ BANK 3 SROMC _ BANK 2 SROMC _ BANK 1 SROMC _ BANK 0 Reserved 0 x 4000 _ 0000 0 x 3 FFF _ FFFF DRAM 0 x 2000 _ 0000 0 x1 FFF _ FFFF 0 x 0000 _ 0000 Reserved IROM & IRAM Figure 2-1 Address Map 2 1BMEMORY MAP 2-1 S5PV210_UM 2 1BMEMORY MAP 2.1.1 DEVICE SPECIFIC ADDRESS SPACE Address Size 0x0000_0000 0x1FFF_FFFF 512MB 0x2000_0000 0x4000_0000 0x8000_0000 0x8800_0000 0x9000_0000 0x9800_0000 0xA000_0000 0xA800_0000 0x3FFF_FFFF 0x5FFF_FFFF 0x87FF_FFFF 0x8FFF_FFFF 0x97FF_FFFF 0x9FFF_FFFF 0xA7FF_FFFF 0xAFFF_FFFF 512MB 512MB 128MB 128MB 128MB 128MB 128MB 128MB 0xB000_0000 0xBFFF_FFFF 256MB 0xC000_0000 0xD000_0000 0xD001_0000 0xD002_0000 0xD800_0000 0xE000_0000 0xCFFF_FFFF 0xD000_FFFF 0xD001_FFFF 0xD003_FFFF 0xDFFF_FFFF 0xFFFF_FFFF 256MB 64KB 96KB 128KB 128MB 512MB Description Boot area DRAM 0 DRAM 1 SROM Bank 0 SROM Bank 1 SROM Bank 2 SROM Bank 3 SROM Bank 4 SROM Bank 5 OneNAND/NAND Controller and SFR MP3_SRAM output buffer IROM Reserved IRAM DMZ ROM SFR region Note Mirrored region depending on the boot mode. 2-2 S5PV210_UM 2 1BMEMORY MAP TZPCR0SIZE[5:0] (TZPC0) 0xD000_0000 0xD000_FFFF 0xD001_0000 iROM (64KB) Secure area Not Available 0xD001_FFFF 0xD002_0000 iRAM(128KB) 0xD003_FFFF 0xD004_0000 Secure area Non Secure area Not Available 0xD800_0000 DMZ ROM Non Secure area 0xDFFF_FFFF Figure 2-2 Internal Memory Address Map NOTE: TZPCR0SIZE[5:0](TZPC0); (in TZPC SFR) - 4KByte chunks - Recommended value: 6'b00_0000 ~ 6'b10_0000 * if (TZPCR0SIZE[5](TZPC0) == 1'b1), the full address range in iSRAM is configured as secure. * if (TZPCR0SIZE(TZPC0) == 6'b00_0000), there is non-secure region in iSRAM (0kB). * if (TZPCR0SIZE(TZPC0) == 6'b00_0001), the minimum secure region size is 4kB. * if (TZPCR0SIZE(TZPC0) == 6'b01_0000), the 64KB from iSRAM start address specifies the secure region. - iROM is always secure area 2-3 S5PV210_UM 2 1BMEMORY MAP 2.1.2 SPECIAL FUNCTION REGISTER MAP Address 0xE000_0000 0xE00F_FFFF 0xE010_0000 0xE01F_FFFF 0xE020_0000 0xE02F_FFFF 0xE030_0000 0xE03F_FFFF 0xE040_0000 0xE04F_FFFF 0xE050_0000 0xE05F_FFFF 0xE060_0000 0xE06F_FFFF 0xE070_0000 0xE07F_FFFF 0xE080_0000 0xE08F_FFFF 0xE090_0000 0xE09F_FFFF 0xE0A0_0000 0xE0AF_FFFF 0xE0D0_0000 0xE0DF_FFFF 0xE0E0_0000 0xE0EF_FFFF 0xE0F0_0000 0xE0FF_FFFF 0xE110_0000 0xE11F_FFFF 0xE120_0000 0xE12F_FFFF 0xE130_0000 0xE13F_FFFF 0xE140_0000 0xE14F_FFFF 0xE160_0000 0xE16F_FFFF 0xE170_0000 0xE17F_FFFF 0xE180_0000 0xE18F_FFFF 0xE1A0_0000 0xE1AF_FFFF 0xE1B0_0000 0xE1BF_FFFF 0xE1C0_0000 0xE1CF_FFFF 0xE1D0_0000 0xE1DF_FFFF 0xE1F0_0000 0xE1FF_FFFF 0xE210_0000 0xE21F_FFFF 0xE220_0000 0xE22F_FFFF 0xE230_0000 0xE23F_FFFF 0xE250_0000 0xE25F_FFFF 0xE260_0000 0xE26F_FFFF 0xE270_0000 0xE27F_FFFF 0xE280_0000 0xE28F_FFFF 0xE290_0000 0xE29F_FFFF 0xE800_0000 0xE80F_FFFF Description CHIPID SYSCON GPIO AXI_DMA AXI_PSYS AXI_PSFR TZPC2 IEM_APC IEM_IEC PDMA0 PDMA1 CORESIGHT SECKEY ASYNC_AUDIO_PSYS SPDIF PCM1 SPI0 SPI1 KEYIF TSADC I2C0 (general) I2C2 (PMIC) HDMI_CEC TZPC3 AXI_GSYS ASYNC_PSFR_AUDIO I2S1 AC97 PCM0 PWM ST WDT RTC_APBIF UART SROMC 2-4 S5PV210_UM 2 1BMEMORY MAP Address 0xE820_0000 0xE82F_FFFF 0xEA00_0000 0xEA0F_FFFF 0xEB00_0000 0xEB0F_FFFF 0xEB10_0000 0xEB1F_FFFF 0xEB20_0000 0xEB2F_FFFF 0xEB30_0000 0xEB3F_FFFF 0xEB40_0000 0xEB4F_FFFF 0xEC00_0000 0xEC0F_FFFF 0xEC10_0000 0xEC1F_FFFF 0xEC20_0000 0xEC2F_FFFF 0xEC30_0000 0xEC3F_FFFF 0xED00_0000 0xED0F_FFFF 0xED10_0000 0xED1F_FFFF 0xEE00_0000 0xEE8F_FFFF 0xEE90_0000 0xEE9F_FFFF 0xEEA0_0000 0xEEAF_FFFF 0xEEB0_0000 0xEEBF_FFFF 0xEEC0_0000 0xEECF_FFFF 0xEED0_0000 0xEEDF_FFFF 0xEEE0_0000 0xEEEF_FFFF 0xEEF0_0000 0xEEFF_FFFF 0xF000_0000 0xF00F_FFFF 0xF100_0000 0xF10F_FFFF 0xF110_0000 0xF11F_FFFF 0xF120_0000 0xF12F_FFFF 0xF140_0000 0xF14F_FFFF 0xF150_0000 0xF15F_FFFF 0xF160_0000 0xF16F_FFFF 0xF170_0000 0xF17F_FFFF 0xF180_0000 0xF18F_FFFF 0xF190_0000 0xF19F_FFFF 0xF1A0_0000 0xF1AF_FFFF 0xF1B0_0000 0xF1BF_FFFF 0xF1C0_0000 0xF1CF_FFFF 0xF1D0_0000 0xF1DF_FFFF 0xF1E0_0000 0xF1EF_FFFF Description CFCON SECSS SDMMC0 SDMMC1 SDMMC2 SDMMC3 TSI USBOTG USBOTG_PHY_CON USBHOST_EHCI USBHOST_OHCI MODEM HOST AUDIO_SS AUDIO_SS/ASS_DMA AUDIO_SS/ASS_IBUF0 AUDIO_SS/ASS_IBUF1 AUDIO_SS/ASS_OBUF0 AUDIO_SS/ASS_OBUF1 AUDIO_SS/ASS_APB AUDIO_SS/ASS_ODO DMC0_SFR AXI_MSYS AXI_MSFR AXI_VSYS DMC1_SFR TZPC0 SDM MFC ASYNC_MFC_VSYS0 ASYNC_MFC_VSYS1 ASYNC_DSYS_MSYS0 ASYNC_DSYS_MSYS1 ASYNC_MSFR_DSFR ASYNC_MSFR_PSFR ASYNC_MSYS_DMC0 2-5 S5PV210_UM 2 1BMEMORY MAP Address 0xF1F0_0000 0xF1FF_FFFF 0xF200_0000 0xF20F_FFFF 0xF210_0000 0xF21F_FFFF 0xF220_0000 0xF22F_FFFF 0xF230_0000 0xF23F_FFFF 0xF280_0000 0xF28F_FFFF 0xF290_0000 0xF29F_FFFF 0xF2A0_0000 0xF2AF_FFFF 0xF2B0_0000 0xF2BF_FFFF 0xF300_0000 0xF3FF_FFFF 0xF800_0000 0xF80F_FFFF 0xF900_0000 0xF90F_FFFF 0xF910_0000 0xF91F_FFFF 0xF920_0000 0xF92F_FFFF 0xFA10_0000 0xFA1F_FFFF 0xFA20_0000 0xFA2F_FFFF 0xFA40_0000 0xFA4F_FFFF 0xFA50_0000 0xFA5F_FFFF 0xFA60_0000 0xFA6F_FFFF 0xFA70_0000 0xFA7F_FFFF 0xFA80_0000 0xFA8F_FFFF 0xFA90_0000 0xFA9F_FFFF 0xFAA0_0000 0xFAAF_FFFF 0xFAB0_0000 0xFABF_FFFF 0xFAC0_0000 0xFACF_FFFF 0xFAD0_0000 0xFADF_FFFF 0xFAF0_0000 0xFAFF_FFFF 0xFB10_0000 0xFB1F_FFFF 0xFB20_0000 0xFB2F_FFFF 0xFB30_0000 0xFB3F_FFFF 0xFB40_0000 0xFB4F_FFFF 0xFB60_0000 0xFB6F_FFFF 0xFB70_0000 0xFB7F_FFFF Description ASYNC_MSFR_MPERI VIC0 VIC1 VIC2 VIC3 TZIC0 TZIC1 TZIC2 TZIC3 G3D FIMD TVENC VP MIXER HDMI_LINK SMDMA AXI_LSYS DSIM CSIS AXI_DSYS AXI_DSFR I2C_HDMI_PHY AXI_TSYS I2C_HDMI_DDC AXI_XSYS TZPC1 ASYNC_PSYS_DSYS_u0 ROT FIMC0 FIMC1 FIMC2 JPEG IPC 2-6 S5PV210_UM 3 SIZE & BALL MAP 3.1 PIN ASSIGNMENT 3.1.1 PIN ASSIGNMENT DIAGRAM - 584-BALL FCFBGA 3 2BSIZE & BALL MAP Figure 3-1 S5PV210 Pin Assignment (584-FCFBGA) Bottom View 3-1 S5PV210_UM 3 2BSIZE & BALL MAP 3.1.2 PIN NUMBER ORDER Table 3-1 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (1/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name A1 VSS AA16 VSS_UHOST_AC AC6 XVVD_22 AD21 XUOTGDP A2 XMSMDATA_15 AA17 XCIDATA_7 AC7 XVVD_13 AD22 XI2C1SCL A3 XMSMIRQN AA18 XCICLKENB AC8 XVVD_11 AD23 XUHOSTPWREN A4 XMSMADVN AA19 XCIDATA_3 AC9 XVVD_7 AD24 XEINT_28 A5 XMMC0DATA_1 AA20 XEINT_29 AC10 XADCAIN_3 AD25 XEINT_26 A6 XMMC1DATA_2 AA21 XEINT_20 AC11 XADCAIN_0 AE1 VSS A7 XURTSN_0 AA22 XEINT_4 AC12 XADCAIN_1 AE2 XI2S0SDI A8 XPWMTOUT_2 AA23 XEINT_21 AC13 XURXD_3 AE3 XI2S0LRCK A9 XMMC3CLK AA24 XEINT_12 AC14 XUTXD_2 AE4 XVSYS_OE A10 XMMC3DATA_3 AA25 XEINT_7 AC15 XMIPIVREG_0P4V AE5 XVVD_15 A11 XSPIMOSI_1 AB1 XPCM0FSYNC AC16 XI2C2SDA AE6 XVVD_10 A12 XM1DATA_31 AB2 XPCM0SIN AC17 XUHOSTREXT AE7 XVVD_6 A13 XM1DATA_29 AB3 XI2S1CDCLK AC18 XUOTGVBUS AE8 XMIPISDN3 A14 XM1DATA_26 AB4 XI2S1SDO AC19 XUOTGDRVVBUS AE9 XMIPISDN2 A15 XM1DQS_2 AB5 XVVD_20 AC20 XURXD_2 AE10 XMIPISDNCLK A16 XM1SCLK AB6 XVVD_5 AC21 XCIPCLK AE11 XMIPISDN1 A17 XM1DATA_13 AB7 XVVD_3 AC22 XUHOSTOVERCU R AE12 XMIPISDN0 A18 XM1DQSN_1 AB8 XVVD_2 AC23 XEINT_13 AE13 XMIPIMDP3 A19 XM1DATA_11 AB9 XVVD_1 AC24 XEINT_24 AE14 XMIPIMDP2 A20 XM1DATA_10 AB10 XVVDEN AC25 XEINT_22 AE15 XMIPIMDPCLK A21 XM1DATA_5 AB11 XADCAIN_2 AD1 XI2S1SCLK AE16 XMIPIMDP1 A22 XM1DQSN_0 AB12 XADCAIN_9 AD2 XI2S0SCLK AE17 XMIPIMDP0 A23 XM1DATA_3 AB13 XUTXD_3 AD3 XI2S0SDO_0 AE18 XUOTGREXT A24 XM1DATA_0 AB14 XCIHREF AD4 XEFFSOURCE_0 AE19 XUHOSTDP A25 VSS AB15 XCIDATA_0 AD5 XVVD_18 AE20 XUSBXTO AA1 XPCM0EXTCLK AB16 XCIDATA_1 AD6 XVVD_14 AE21 XUOTGDM AA2 XPCM0SCLK AB17 XCIDATA_6 AD7 XVVD_16 AE22 XI2C2SCL AA3 XI2S0SDO_2 AB18 XDDR2SEL AD8 XMIPISDP3 AE23 XI2C1SDA AA4 XMMC2CDN AB19 XCIFIELD AD9 XMIPISDP2 AE24 XCLKOUT AA5 XI2S1SDI AB20 XCIDATA_2 AD10 XMIPISDPCLK AE25 VSS AA6 XVVD_19 AB21 XCIDATA_4 AD11 XMIPISDP1 B1 XMSMDATA_10 AA7 XVVD_17 AB22 XEINT_25 AD12 XMIPISDP0 B2 XMSMDATA_13 AA8 XVVD_8 AB23 XEINT_31 AD13 XMIPIMDN3 B3 XMSMDATA_14 AA9 XVVD_0 AB24 XEINT_19 AD14 XMIPIMDN2 B4 XMSMWEN 3-2 S5PV210_UM 3 2BSIZE & BALL MAP Ball AA10 AA11 AA12 AA13 AA14 AA15 Pin Name XVVCLK XADCAIN_8 XADCAIN_7 XVHSYNC XCIVSYNC VSS_UHOST_A Ball AB25 AC1 AC2 AC3 AC4 AC5 Pin Name XEINT_14 XPCM0SOUT XI2S1LRCK XI2S0SDO_1 XI2S0CDCLK XVVD_21 Ball AD15 AD16 AD17 AD18 AD19 AD20 Pin Name XMIPIMDNCLK XMIPIMDN1 XMIPIMDN0 XUOTGID XUHOSTDM XUSBXTI Ball Pin Name B5 XMMC0CLK B6 XMMC1CLK B7 XSPICLK_0 B8 XUCTSN_1 B9 XPWMTOUT_1 B10 XMMC3DATA_0 3-3 S5PV210_UM 3 2BSIZE & BALL MAP Table 3-2 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (2/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name B11 XSPICSN_1 D1 XMSMDATA_4 E16 XM1ADDR_14 G6 XMSMADDR_1 B12 XM1DATA_30 D2 XMSMDATA_6 E17 XM1ADDR_2 G7 VSS B13 XM1DATA_28 D3 XMSMDATA_3 E18 XM1ADDR_8 G8 XMSMCSN B14 XM1DATA_25 D4 XMSMDATA_9 E19 XM1ADDR_12 G9 XMSMRN B15 XM1DQSN_2 D5 XMSMADDR_7 E20 XM1ADDR_1 G10 XURXD_1 B16 XM1NSCLK D6 XMMC0DATA_2 E21 XM1ADDR_0 G11 VDD_EXT2 B17 XM1DATA_14 D7 XMMC1DATA_0 E22 XM2DQM_3 G12 XSPICLK_1 B18 XM1DQS_1 D8 XUTXD_0 E23 XM2DATA_23 G13 XSPIMISO_1 B19 XM1DATA_8 D9 XUCTSN_0 E24 XM2DATA_22 G14 XM1CSN_1 B20 XM1DATA_9 D10 XMMC3CMD E25 XM2DATA_21 G15 XM1CKE_0 B21 XM1DATA_4 D11 XMMC3DATA_2 F1 XMSMADDR_10 G16 XM1CKE_1 B22 XM1DQS_0 D12 XM1DQS_3 F2 XMSMADDR_13 G17 XM1WEN B23 XM1DATA_2 D13 XM1DATA_24 F3 XMSMDATA_0 G18 XM1CSN_0 B24 XM2DATA_31 D14 XM1DQM_2 F4 XM0ADDR_14 G19 VSS B25 XM2DATA_29 D15 XM1DATA_18 F5 XMSMADDR_6 G20 XM2ADDR_8 C1 XMSMDATA_7 D16 XM1DATA_16 F6 XMSMADDR_8 G21 XM2CKE_1 C2 XMSMDATA_8 D17 XM1DQM_1 F7 XMMC0CDN G22 XM2DATA_19 C3 XMSMDATA_11 D18 XM1ADDR_4 F8 XMMC1CMD G23 XM2DATA_18 C4 XMSMDATA_12 D19 XM1ADDR_6 F9 XMMC1DATA_3 G24 XM2SCLK C5 XMMC0DATA_0 D20 XM1ADDR_7 F10 XUTXD_1 G25 XM2NSCLK C6 XMMC0DATA_3 D21 XM1ADDR_15 F11 XI2C0SDA H1 XMSMADDR_0 C7 XMMC1CDN D22 XM2DATA_28 F12 XPWMTOUT_3 H2 XMSMADDR_5 C8 XURXD_0 D23 XM2DATA_26 F13 XM1DATA_22 H3 XM0ADDR_15 C9 XI2C0SCL D24 XM2DATA_25 F14 XM1ADDR_11 H4 XM0ADDR_8 C10 XMMC3DATA_1 D25 XM2DATA_24 F15 XM1ADDR_5 H5 XM0ADDR_3 C11 XM1DQM_3 E1 XMSMDATA_2 F16 XM1ADDR_9 H6 XM0ADDR_12 C12 XM1DQSN_3 E2 XMSMDATA_1 F17 XM1CASN H7 XMSMADDR_3 C13 XM1DATA_27 E3 XMSMDATA_5 F18 XM1ADDR_13 H19 XM2ADDR_9 C14 XM1DATA_23 E4 XMSMADDR_2 F19 XM1ADDR_10 H20 XM2ADDR_13 C15 XM1DATA_19 E5 XMSMADDR_12 F20 XM2ADDR_5 H21 XM2DQM_2 C16 XM1DATA_17 E6 XMMC0CMD F21 XM2ADDR_4 H22 XM2ADDR_6 C17 XM1DATA_15 E7 XMMC1DATA_1 F22 XM2DATA_27 H23 XM2ADDR_11 C18 XM1DATA_12 E8 XPWMTOUT_0 F23 XM2DATA_20 H24 XM2DATA_17 C19 XM1DATA_7 E9 XSPICSN_0 F24 XM2DQS_2 H25 XM2DATA_16 C20 XM1DATA_6 E10 XURTSN_1 F25 XM2DQSN_2 J1 XM0CSN_2 C21 XM1DQM_0 E11 XMMC3CDN G1 XMSMADDR_4 J2 XM0FWEN 3-4 S5PV210_UM 3 2BSIZE & BALL MAP Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name C22 XM1DATA_1 E12 XM1RASN G2 XMSMADDR_9 J3 XM0ADDR_10 C23 XM2DATA_30 E13 XM1DATA_20 G3 XMSMADDR_11 J4 XM0ADDR_2 C24 XM2DQS_3 E14 XM1DATA_21 G4 XM0ADDR_9 J5 XM0ADDR_7 C25 XM2DQSN_3 E15 XM1ADDR_3 G5 XM0ADDR_13 J6 XM0ADDR_4 3-5 S5PV210_UM 3 2BSIZE & BALL MAP Table 3-3 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (3/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name J7 VDD_MODEM L1 XM0DATA_8 M20 VDD_APLL P14 VDD_ARM J9 XSPIMISO_0 L2 XM0DATA_9 M21 XM2DATA_8 P15 VDD_ARM J10 VDD_EXT0 L3 XM0DATA_1 M22 XM2DATA_5 P16 VSS J11 XSPIMOSI_0 L4 XM0DATA_10 M23 XM2DATA_7 P17 VDD_CKO J12 VSS L5 XM0DATA_2 M24 XM2DATA_9 P19 VSS_VPLL J13 VDD_M1 L6 XM0FRNB_3 M25 XM2DATA_11 P20 VDD_VPLL J14 VDD_M1 L7 XM0ADDR_1 N1 XM0DATA_4 P21 VDD_RTC J15 VDD_M1 L9 VSS N2 XM0DATA_5 P22 XM2WEN J16 VDD_M1 L10 VDD_INT N3 XM0CSN_4 P23 XM2DATA_0 J17 VDD_M2 L11 VDD_INT N4 XM0DATA_7 P24 XM2DATA_3 J19 XM2ADDR_7 L12 VSS N5 XM0DATA_14 P25 XM2DQM_0 J20 XM2ADDR_14 L13 VDD_ARM N6 XM0BEN_1 R1 XHDMITXCN J21 XM2RASN L14 VDD_ARM N7 XM0CSN_5 R2 XHDMITXCP J22 XM2ADDR_12 L15 VDD_ARM N9 XM0CSN_3 R3 XM0FRNB_0 J23 XM2CASN L16 VSS N10 VDD_INT R4 XM0OEN J24 XM2CKE_0 L17 VDD_M2 N11 VDD_INT R5 XJTMS J25 XM2DATA_14 L19 XM2ADDR_1 N12 VSS R6 VDD_HDMI_PLL K1 XM0FCLE L20 XM2ADDR_0 N14 VDD_ARM R7 VSS_HDMI K2 XM0FALE L21 XM2ADDR_2 N15 VDD_ARM R9 VSS K3 XM0DATA_0 L22 XM2DQM_1 N16 VDD_ARM R10 VSS K4 XM0ADDR_5 L23 XM2DATA_10 N17 VSS R11 VDD_INT K5 XM0ADDR_0 L24 XM2DQS_1 N19 VSS_MPLL R12 VDD_INT K6 XM0ADDR_6 L25 XM2DQSN_1 N20 VDD_MPLL R13 VDD_INT K7 XM0ADDR_11 M1 XM0DATA_11 N21 XM2CSN_0 R14 VSS K9 VDD_M0 M2 XM0FREN N22 XM2DATA_6 R15 VSS K10 VSS M3 XM0DATA_12 N23 XM2DATA_4 R16 VSS K11 VSS M4 XM0DATA_3 N24 XM2DQS_0 R17 VDD_ALIVE K12 VSS M5 XM0DATA_13 N25 XM2DQSN_0 R19 VSS_EPLL K13 VDD_INT M6 XM0FRNB_1 P1 XM0DATA_6 R20 VDD_EPLL K14 VDD_INT M7 XM0DATA_RDN P2 XM0DATA_15 R21 XEPLLFILTER K15 VDD_INT M9 VDD_M0 P3 XJDBGSEL R22 XRTCCLKO K16 VSS M10 VSS P4 XM0WEN R23 XM2ADDR_3 K17 VDD_M2 M11 VDD_INT P5 XJTRSTN R24 XM2DATA_1 K19 VSS M12 VSS P6 VDD_HDMI R25 XM2DATA_2 K20 XM2ADDR_15 M13 VDD_ARM P7 VSS_HDMI_PLL T1 XHDMITX0N K21 XM2CSN_1 M14 VDD_ARM P9 VDD_SYS0 T2 XHDMITX0P 3-6 S5PV210_UM 3 2BSIZE & BALL MAP Ball Pin Name Ball Pin Name Ball K22 XM2ADDR_10 M15 VDD_ARM P10 K23 XM2DATA_13 M16 VSS P11 K24 XM2DATA_15 M17 VDD_M2 P12 K25 XM2DATA_12 M19 VSS_APLL P13 Pin Name VSS VDD_INT VSS VSS Ball Pin Name T3 XM0BEN_0 T4 XM0CSN_1 T5 XJTDI T6 VSS_HDMI_OSC 3-7 S5PV210_UM 3 2BSIZE & BALL MAP Table 3-4 S5PV210 584 FCFBGA Pin Assignment − Pin Number Order (4/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball T7 VDD_HDMI_OSC V1 XHDMITX2N Y2 XHDMIXTI T9 VDD_EXT1 V2 XHDMITX2P Y3 XMMC2DATA_2 T10 VSS V3 XM0FRNB_2 Y4 XMMC2DATA_0 T11 VDD_INT V4 XDACCOMP Y5 XMMC2DATA_1 T12 VSS V5 XDACVREF Y6 XMMC2CLK T13 VSS V6 VSS_DAC Y7 XVVD_23 T14 VSS V7 VDD_DAC Y8 XVVD_12 T15 VSS V19 VDD_CAM Y9 XVVD_4 T16 VSS V20 XEINT_8 Y10 XVVSYNC T17 VDD_KEY V21 XEINT_18 Y11 XADCAIN_4 T19 VDD_SYS1 V22 XEINT_9 Y12 XADCAIN_6 T20 XNRSTOUT V23 XOM_2 Y13 VDD_MIPI_A T21 XNWRESET V24 XOM_5 Y14 VSS_UHOST_D T22 XOM_1 V25 XOM_4 Y15 VSS_UOTG_AC T23 XOM_0 W1 XHDMIREXT Y16 VDD_UHOST_A T24 XRTCXTI W2 XM0WAITN Y17 VSS_UOTG_A T25 XRTCXTO W3 XJTDO Y18 XCIDATA_5 U1 XHDMITX1N W4 XMMC2DATA_3 Y19 XEINT_30 U2 XHDMITX1P W5 XDACIREF Y20 XEINT_23 U3 XM0CSN_0 W6 XMMC2CMD Y21 XEINT_0 U4 XJTCK W7 VSS Y22 XEINT_27 U5 XDACOUT W8 XVVSYNC_LDI Y23 XEINT_17 U6 VSS_DAC_A W9 XVVD_9 Y24 XEINT_10 U7 VDD_DAC_A W10 VDD_ADC Y25 XEINT_3 U9 VDD_AUD W11 VSS_ADC U10 VDD_LCD W12 XADCAIN_5 U11 VSS_MIPI W13 VDD_UHOST_D U12 VDD_MIPI_D W14 VDD_MIPI_PLL U13 VDD_MIPI_D W15 VDD_ALIVE U14 VSS_MIPI W16 VDD_UOTG_A U15 VDD_UOTG_D W17 VSS_UOTG_D U16 VDD_SYS0 W18 VDD_EXT1 U17 VDD_SYS0 W19 VSS U19 VDD_AUD W20 XEINT_15 U20 XEINT_16 W21 XEINT_6 U21 XOM_3 W22 XEINT_11 Pin Name 3-8 S5PV210_UM 3 2BSIZE & BALL MAP Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name U22 XPWRRGTON W23 XEINT_2 U23 XNRESET W24 XEINT_5 U24 XXTI W25 XEINT_1 U25 XXTO Y1 XHDMIXTO 3-9 S5PV210_UM 3 2BSIZE & BALL MAP 3.1.3 POWER PINS Power Group Digital I/O Internal Logic Analog & High Speed Table 3-5 S5PV210 Power Pin to Ball Assignment (1/2) Pin Name VDD_M2 VDD_M1 VDD_M0 VDD_LCD VDD_CAM VDD_AUD VDD_MODEM VDD_KEY VDD_SYS0 VDD_SYS1 VDD_EXT0 VDD_EXT1 VDD_EXT2 VDD_CKO VDD_RTC VDD_INT VDD_ARM VDD_ALIVE VDD_ADC VDD_DAC_A VDD_DAC VDD_MIPI_A VDD_MIPI_D VDD_MIPI_PLL VDD_HDMI VDD_HDMI_PLL VDD_HDMI_OSC VDD_UOTG_A VDD_UOTG_D VDD_UHOST_A VDD_UHOST_D VDD_APLL Ball Description J17, K17, L17, M17 MDDR 2 J13, J14, J15, J16 MDDR 1 K9, M9 OneNAND(EBI) U10 LCD V19 CAMIF U9, U19 AUDIO(I2S) J7 MSM T17 KEY P9, U16, U17 SYS0(EINT0~7,Clock, OM,Reset) T19 SYS1(EINT8~15) J10 EXT0 T9, W18 EXT1 G11 EXT2 P17 RTC CLKO P21 RTC K13, K14, K15, L10, L11, M11, N10, N11, P11, R11, R12, R13, T11 Internal logic L13, L14, L15, M13, M14, M15, N14, N15, N16, P14, P15 Cortex-A8 core R17, W15 Alive logic W10 ADC U7 DAC Analog V7 DAC Digital Y13 MIPI 1.8V U12, U13 MIPI 1.1V W14 MIPI PLL P6 HDMI TX R6 HDMI PLL T7 HDMI OSC W16 USB OTG 3.3V U15 USB OTG 1.1V Y16 USB HOST 3.3V W13 USB HOST 1.1V M20 APLL 3-10 S5PV210_UM Power Group Pin Name VDD_MPLL VDD_VPLL VDD_EPLL 3 2BSIZE & BALL MAP Ball Description N20 MPLL P20 VPLL R20 EPLL 3-11 S5PV210_UM 3 2BSIZE & BALL MAP Power Group Table 3-6 S5PV210 Power Pin to Ball Assignment (2/2) Pin Name Ball Internal Logic Digital I/O VSS Analog IO VSS_APLL VSS_EPLL VSS_MPLL VSS_VPLL VSS_ADC VSS_DAC VSS_DAC_A VSS_HDMI VSS_HDMI_OSC VSS_HDMI_PLL VSS_MIPI VSS_UHOST_A VSS_UHOST_AC VSS_UHOST_D VSS_UOTG_A VSS_UOTG_AC VSS_UOTG_D A1, A25, AE1, AE25, G19, G7, J12, K10, K11, K12, K16, K19, L12, L16, L9, M10, M12, M16, M19, N12, N17, N19, P10, P12, P13, P16, P19, R10, R14, R15, R16, R19, R9, T10, T12, T13, T14, T15, T16, W19, W7 M20 R20 N20 P20 W11 V6 U6 R7 T6 P7 U11, U14 AA15 AA16 Y14 Y17 Y15 W17 3-12 S5PV210_UM 3 2BSIZE & BALL MAP 3.2 PIN DISCRIPTION • UART0 / UART1 / UART2 / UART3 / UART AUDIO Ball Name XURXD_0 XUTXD_0 XUCTSN_0 XURTSN_0 XURXD_1 XUTXD_1 XUCTSN_1 XURTSN_1 XURXD_2 XUTXD_2 XURXD_3 XUTXD_3 Func0 Signal IO UART_0_RXD I UART_0_TXD O UART_0_CTSn I UART_0_RTSn O UART_1_RXD I UART_1_TXD O UART_1_CTSn I UART_1_RTSn O UART_2_RXD I UART_2_TXD O UART_3_RXD I UART_3_TXD O Func1 Signal UART_2_CTSn UART_2_RTSn Func2 Default Reset IO Signal IO GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) UART_AUDIO_RXD I GPI I(L) UART_AUDIO_TXD O GPI I(L) I GPI I(L) O GPI I(L) Signal UART_0_RXD UART_0_TXD UART_0_CTSn UART_0_RTSn UART_1_RXD UART_1_TXD UART_1_CTSn UART_1_RTSn UART_2_RXD UART_2_TXD UART_3_RXD UART_3_TXD UART_2_CTSn UART_2_RTSn UART_AUDIO_RXD UART_AUDIO_TXD I/O Description I UART 0 receives data input O UART 0 transmits data output I UART 0 clear to send input signal O UART 0 request to send output signal I UART 1 receives data input O UART 1 transmits data output I UART 1 clear to send input signal O UART 1 request to send output signal I UART 2 receive data input O UART 2 transmits data output I UART 3 receives data input O UART 3 transmits data output I UART 2 clear to send input signal O UART 2 request to send output signal I UART AUDIO receives data input O UART AUDIO transmits data output 3-313 S5PV210_UM 3 2BSIZE & BALL MAP • SPI0 / SPI1 Ball Name Func0 Signal IO XSPICLK_0 SPI_0_CLK IO XSPICSN_0 SPI_0_nSS IO XSPIMISO_0 SPI_0_MISO IO XSPIMOSI_0 SPI_0_MOSI IO XSPICLK_1 SPI_1_CLK IO XSPICSN_1 SPI_1_nSS IO XSPIMISO_1 SPI_1_MISO IO XSPIMOSI_1 SPI_1_MOSI IO Func1 Signal IO Func2 Signal IO Default GPI GPI GPI GPI GPI GPI GPI GPI Reset I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) Signal SPI_0_CLK SPI_0_nSS SPI_0_MISO SPI_0_MOSI SPI_1_CLK SPI_1_nSS SPI_1_MISO SPI_1_MOSI I/O Description IO SPI clock for channel 0 IO SPI chip select (only for slave mode) for channel 0 IO SPI master input / slave output line for channel 0 IO SPI master output / slave input line for channel 0 IO SPI clock for channel 1 IO SPI chip select (only for slave mode) for channel 1 IO SPI master input / slave output line for channel 1 IO SPI master output / slave input line for channel 1 3-314 S5PV210_UM 3 2BSIZE & BALL MAP • I2S1 / I2S2 / PCM0 / PCM1 / SPDIF / AC97 Ball Name Func0 Signal IO XI2S1SCLK I2S_1_SCLK IO XI2S1CDCLK I2S_1_CDCLK IO XI2S1LRCK I2S_1_LRCK IO XI2S1SDI I2S_1_SDI I XI2S1SDO I2S_1_SDO O XPCM0SCLK PCM_0_SCLK O XPCM0EXTCLK PCM_0_EXTCLK I XPCM0FSYNC PCM_0_FSYNC O XPCM0SIN PCM_0_SIN I XPCM0SOUT PCM_0_SOUT O Func1 Signal PCM_1_SCLK PCM_1_EXTCLK PCM_1_FSYNC PCM_1_SIN PCM_1_SOUT SPDIF_0_OUT SPDIF_EXTCLK LCD_FRM Func2 Default Reset IO Signal IO O AC97BITCLK I GPI I(L) I AC97RESETn O GPI I(L) O AC97SYNC O GPI I(L) I AC97SDI I GPI I(L) O AC97SDO O GPI I(L) O I2S_2_SCLK IO GPI I(L) I I2S_2_CDCLK IO GPI I(L) O I2S_2_LRCK IO GPI I(L) I2S_2_SDI I GPI I(L) I2S_2_SDO O GPI I(L) Signal I2S_1_SCLK I2S_1_CDCLK I2S_1_LRCK I2S_1_SDI I2S_1_SDO PCM_0_SCLK PCM_0_EXTCLK PCM_0_FSYNC PCM_0_SIN PCM_0_SOUT PCM_1_SCLK PCM_1_EXTCLK PCM_1_FSYNC PCM_1_SIN PCM_1_SOUT SPDIF_0_OUT SPDIF_EXTCLK LCD_FRM AC97BITCLK AC97RESETn I/O Description IO IIS-bus serial clock for channel 1 IO IIS CODEC system clock for channel 1 IO IIS-bus channel select clock for channel 1 I IIS-bus serial data input for channel 1 O IIS-bus serial data output for channel 1 O PCM Serial Shift Clock for channel 0 I PCM External Clock for channel 0 O PCM Sync indicating start of word for channel 0 I PCM Serial Data Input for channel 0 O PCM Serial Data Output for channel 0 O PCM Serial Shift Clock for channel 1 I PCM External Clock for channel 1 O PCM Sync indicating start of word for channel 1 I PCM Serial Data Input for channel 1 O PCM Serial Data Output for channel 1 O SPDIFOUT data output I SPDIF Global Audio Main Clock Input O FRM SYNC Signal I AC-Link bit clock (12.288 MHz) from AC97 Codec to AC97 Controller O AC-link Reset to Codec 3-315 S5PV210_UM Signal AC97SYNC AC97SDI AC97SDO I2S_2_SCLK I2S_2_CDCLK I2S_2_LRCK I2S_2_SDI I2S_2_SDO 3 2BSIZE & BALL MAP I/O Description O AC-link Frame Synchronization (Sampling Frequency 48 Khz) from AC97 Controller to AC97 Codec I AC-link Serial Data input from AC97 Codec O AC-link Serial Data output to AC97 Codec IO IIS-bus serial clock for channel 2 IO IIS CODEC system clock for channel 2 IO IIS-bus channel select clock for channel 2 I IIS-bus serial data input for channel 2 O IIS-bus serial data output for channel 2 • PWM / I2C0 Ball Name XPWMTOUT_0 XPWMTOUT_1 XPWMTOUT_2 XPWMTOUT_3 XI2C0SDA XI2C0SCL XI2C1SDA XI2C1SCL XI2C2SDA XI2C2SCL Func0 Signal TOUT_0 TOUT_1 TOUT_2 TOUT_3 I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL I2C2_SDA I2C2_SCL Func1 IO Signal IO O O O O PWM_MIE/PWM_MDNIE O IO IO IO IO IO IEM_SCLK IO IO IEM_SPWI IO Func2 Signal Default Reset IO GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) Signal TOUT_0/1/2/3 I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL I2C2_SDA I2C2_SCL PWM_MIE IEM_SCLK IEM_SPWI I/O O PWM Timer Output IO IIC-bus clock for channel 0 IO IIC-bus data for channel 0 IO IIC-bus clock for channel 1 IO IIC-bus data for channel 1 IO IIC-bus clock for channel 0 IO IIC-bus data for channel 0 O PWM output from MIE IO PWI Clock IO PWI Serial data Description 3-316 S5PV210_UM 3 2BSIZE & BALL MAP 3-317 S5PV210_UM 3 2BSIZE & BALL MAP • CAMIF A Ball Name Func0 Signal IO XCIPCLK CAM_A_PCLK I XCIVSYNC CAM_A_VSYNC I XCIHREF CAM_A_HREF I XCIDATA_0 CAM_A_DATA[0] I XCIDATA_1 CAM_A_DATA[1] I XCIDATA_2 CAM_A_DATA[2] I XCIDATA_3 CAM_A_DATA[3] I XCIDATA_4 CAM_A_DATA[4] I XCIDATA_5 CAM_A_DATA[5] I XCIDATA_6 CAM_A_DATA[6] I XCIDATA_7 CAM_A_DATA[7] I XCICLKENB CAM_A_CLKOUT O XCIFIELD CAM_A_FIELD I Func1 Signal IO Func2 Signal Default Reset IO GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) Signal CAM_A_PCLK CAM_A_VSYNC CAM_A_HREF CAM_A_DATA[7:0] CAM_A_CLKOUT CAM_A_FIELD I/O Description O Pixel Clock, driven by the Camera processor A IO Vertical Sync, driven by the Camera processor A IO Horizontal Sync, driven by the Camera processor A IO Pixel Data for YCbCr in 8-bit mode or for Y in 16-bit mode, driven by the Camera processor A IO Master Clock to the Camera processor A IO Software Reset or Power Down for the external Camera processor 3-318 S5PV210_UM 3 2BSIZE & BALL MAP • LCD Ball Name Func0 Signal IO XVHSYNC LCD_HSYNC O XVVSYNC LCD_VSYNC O XVVDEN LCD_VDEN O XVVCLK LCD_VCLK O XVVD_0 LCD_VD[0] O XVVD_1 LCD_VD[1] O XVVD_2 LCD_VD[2] O XVVD_3 LCD_VD[3] O XVVD_4 LCD_VD[4] O XVVD_5 LCD_VD[5] O XVVD_6 LCD_VD[6] O XVVD_7 LCD_VD[7] O XVVD_8 LCD_VD[8] O XVVD_9 LCD_VD[9] O XVVD_10 LCD_VD[10] O XVVD_11 LCD_VD[11] O XVVD_12 LCD_VD[12] O XVVD_13 LCD_VD[13] O XVVD_14 LCD_VD[14] O XVVD_15 LCD_VD[15] O XVVD_16 LCD_VD[16] O XVVD_17 LCD_VD[17] O XVVD_18 LCD_VD[18] O XVVD_19 LCD_VD[19] O XVVD_20 LCD_VD[20] O XVVD_21 LCD_VD[21] O XVVD_22 LCD_VD[22] O XVVD_23 LCD_VD[23] O XVVSYNC_LDI O XVSYS_OE O Func1 Signal SYS_CS0 SYS_CS1 SYS_RS SYS_WE SYS_VD[0] SYS_VD[1] SYS_VD[2] SYS_VD[3] SYS_VD[4] SYS_VD[5] SYS_VD[6] SYS_VD[7] SYS_VD[8] SYS_VD[9] SYS_VD[10] SYS_VD[11] SYS_VD[12] SYS_VD[13] SYS_VD[14] SYS_VD[15] SYS_VD[16] SYS_VD[17] SYS_VD[18] SYS_VD[19] SYS_VD[20] SYS_VD[21] SYS_VD[22] SYS_VD[23] VSYNC_LDI SYS_OE Func2 IO Signal O VEN_HSYNC O VEN_VSYNC O VEN_HREF O V601_CLK IO VEN_DATA[0] IO VEN_DATA[1] IO VEN_DATA[2] IO VEN_DATA[3] IO VEN_DATA[4] IO VEN_DATA[5] IO VEN_DATA[6] IO VEN_DATA[7] IO V656_DATA[0] IO V656_DATA[1] IO V656_DATA[2] IO V656_DATA[3] IO V656_DATA[4] IO V656_DATA[5] IO V656_DATA[6] IO V656_DATA[7] IO IO IO IO IO IO IO IO V656_CLK O O VEN_FIELD Default Reset IO O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) O GPI I(L) O GPI I(L) O GPI I(L) 3-319 S5PV210_UM 3 2BSIZE & BALL MAP Signal LCD_HSYNC LCD_VSYNC LCD_VDEN LCD_VCLK LCD_VD[23:0] VSYNC_LDI SYS_OE SYS_CS0 SYS_CS1 SYS_RS SYS_WE SYS_VD[23:0] SYS_OE VEN_HSYNC VEN_VSYNC VEN_HREF V601_CLK VEN_DATA[7:0] V656_DATA[7:0] V656_CLK VEN_FIELD I/O Description O Horizontal Sync Signal for RGB interface O Vertical Sync Signal for RGB interface O Data Enable for RGB interface O Video Clock for RGB interface O LCD pixel data output for RGB interface O LCD i80 VSYNC Interface O Output Enable for RGB interface O Chip select LCD0 for LCD Indirect i80 System interface O Chip select LCD1 for LCD Indirect i80 System interface O Register/ State Select Signal for LCD Indirect i80 System interface O Write Enable for LCD Indirect i80 System interface IO Video data input/ output for LCD Indirect i80 System interface O Output Enable for LCD Indirect i80 System interface O Horizontal Sync Signal for 601 interface O Vertical Sync Signal for 601 interface O Data Enable for 601 interface O Data Clock for 601 interface O YUV422 format data output for 601 interface O YUV422 format data output for 656 interface O Data Clock for 656 interface O Field Signal for 601 interface 3-320 S5PV210_UM 3 2BSIZE & BALL MAP • SDMMC0 / SDMMC1 / SDMMC2 / SDMMC3 Ball Name Func0 Signal IO Func1 Signal IO XMMC0CLK SD_0_CLK O XMMC0CMD SD_0_CMD IO XMMC0CDN SD_0_CDn I XMMC0DATA_0 SD_0_DATA[0] IO XMMC0DATA_1 SD_0_DATA[1] IO XMMC0DATA_2 SD_0_DATA[2] IO XMMC0DATA_3 SD_0_DATA[3] IO XMMC1CLK SD_1_CLK O XMMC1CMD SD_1_CMD IO XMMC1CDN SD_1_CDn I XMMC1DATA_0 SD_1_DATA[0] IO SD_0_DATA[4] IO XMMC1DATA_1 SD_1_DATA[1] IO SD_0_DATA[5] IO XMMC1DATA_2 SD_1_DATA[2] IO SD_0_DATA[6] IO XMMC1DATA_3 SD_1_DATA[3] IO SD_0_DATA[7] IO XMMC2CLK SD_2_CLK O SPI_2_CLK IO XMMC2CMD SD_2_CMD IO SPI_2_nSS IO XMMC2CDN SD_2_CDn I SPI_2_MISO IO XMMC2DATA_0 SD_2_DATA[0] IO SPI_2_MOSI IO XMMC2DATA_1 SD_2_DATA[1] IO XMMC2DATA_2 SD_2_DATA[2] IO XMMC2DATA_3 SD_2_DATA[3] IO XMMC3CLK SD_3_CLK O XMMC3CMD SD_3_CMD IO XMMC3CDN SD_3_CDn I XMMC3DATA_0 SD_3_DATA[0] IO SD_2_DATA[4] IO XMMC3DATA_1 SD_3_DATA[1] IO SD_2_DATA[5] IO XMMC3DATA_2 SD_3_DATA[2] IO SD_2_DATA[6] IO XMMC3DATA_3 SD_3_DATA[3] IO SD_2_DATA[7] IO Func2 Signal Default Reset IO GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) 3-321 S5PV210_UM 3 2BSIZE & BALL MAP Signal SD_0_CLK SD_0_CMD SD_0_CDn SD_0_DATA[3:0] SD_1_CLK SD_1_CMD SD_1_CDn SD_1_DATA[3:0] SD_2_CLK SD_2_CMD SD_2_CDn SD_2_DATA[3:0] SD_3_CLK SD_3_CMD SD_3_CDn SD_3_DATA[3:0] SD_0_DATA[7:4] SPI_2_CLK SPI_2_nSS SPI_2_MISO SPI_2_MOSI SD_2_DATA[7:4] I/O Description O CLOCK (SD/ SDIO/ MMC card interface channel 0) IO COMMAND/ RESPONSE (SD/SDIO/ MMC card interface channel 0) I CARD DETECT (SD/ SDIO/ MMC card interface channel 0) IO DATA[3:0] (SD/ SDIO/ MMC card interface channel 0) O CLOCK (SD/ SDIO/ MMC card interface channel 1) IO COMMAND/RESPONSE (SD/ SDIO/ MMC card interface channel 1) I CARD DETECT (SD/ SDIO/ MMC card interface channel 1) IO DATA[3:0] (SD/ SDIO/ MMC card interface channel 1) O CLOCK (SD/ SDIO/ MMC card interface channel 2) IO COMMAND/RESPONSE (SD/ SDIO/ MMC card interface channel 2) I CARD DETECT (SD/ SDIO/ MMC card interface channel 2) IO DATA[3:0] (SD/ SDIO/ MMC card interface channel 2) O CLOCK (SD/ SDIO/ MMC card interface channel 3) IO COMMAND/ RESPONSE (SD/ SDIO/ MMC card interface channel 3) I CARD DETECT (SD/ SDIO/ MMC card interface channel 3) IO DATA[3:0] (SD/ SDIO /MMC card interface channel 3) IO DATA[7:4] (SD/ SDIO/ MMC card interface channel 0) IO SPI clock for channel 0 IO SPI chip select (only for slave mode) for channel 0 IO SPI master input / slave output line for channel 0 IO SPI master output / slave input line for channel 0 IO DATA[7:4] (SD/ SDIO/ MMC card interface channel 2) 3-322 S5PV210_UM 3 2BSIZE & BALL MAP • EINT / KEYPAD Ball Name XEINT_0 XEINT_1 XEINT_2 XEINT_3 XEINT_4 XEINT_5 XEINT_6 XEINT_7 XEINT_8 XEINT_9 XEINT_10 XEINT_11 XEINT_12 XEINT_13 XEINT_14 XEINT_15 XEINT_16 XEINT_17 XEINT_18 XEINT_19 XEINT_20 XEINT_21 XEINT_22 XEINT_23 XEINT_24 XEINT_25 XEINT_26 XEINT_27 XEINT_28 XEINT_29 XEINT_30 XEINT_31 Func0 Signal IO I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Func1 Signal KP_COL[0] KP_COL[1] KP_COL[2] KP_COL[3] KP_COL[4] KP_COL[5] KP_COL[6] KP_COL[7] KP_ROW[0] KP_ROW[1] KP_ROW[2] KP_ROW[3] KP_ROW[4] KP_ROW[5] KP_ROW[6] KP_ROW[7] Func2 Default Reset IO Signal IO GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) HDMI_CEC IO GPI I(L) HDMI_HPD I GPI I(L) GPI I(L) GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) IO GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) I GPI I(L) 3-323 S5PV210_UM 3 2BSIZE & BALL MAP 3-324 S5PV210_UM Signal XEINT[31:0] KP_COL[7:0] KP_ROW[7:0] HDMI_CEC HDMI_HPD I/O I External interrupts O KeyIF_Column_data[7:0] I KeyIF_Row_data[7:0] IO HDMI CEC port I HDMI Hot plug Description 3 2BSIZE & BALL MAP • I2S0 / PCM2 Ball Name Func0 Signal IO XI2S0SCLK I2S_0_SCLK IO XI2S0CDCLK I2S_0_CDCLK IO XI2S0LRCK I2S_0_LRCK IO XI2S0SDI I2S_0_SDI I XI2S0SDO_0 I2S_0_SDO[0] O XI2S0SDO_1 I2S_0_SDO[1] O XI2S0SDO_2 I2S_0_SDO[2] O Func1 Signal IO PCM_2_SCLK O PCM_2_EXTCLK I PCM_2_FSYNC O PCM_2_SIN I PCM_2_SOUT O Func2 Signal Default Reset IO Func0 O(L) Func0 O(L) Func0 O(L) Func0 I(L) Func0 O(L) Func0 O(L) Func0 O(L) Signal I2S_0_SCLK I2S_0_CDCLK I2S_0_LRCK I2S_0_SDI I2S_0_SDO[2:0] PCM_2_SCLK PCM_2_EXTCLK PCM_2_FSYNC PCM_2_SIN PCM_2_SOUT I/O Description IO IIS-bus serial clock for channel 0 (Lower Power Audio) IO IIS CODEC system clock for channel 0 (Lower Power Audio) IO IIS-bus channel select clock for channel 0 (Lower Power Audio) I IIS-bus serial data input for channel 0 (Lower Power Audio) O IIS-bus serial data output for channel 0 (Lower Power Audio) O PCM Serial Shift Clock for channel 2 I PCM External Clock for channel 2 O PCM Sync indicating start of word for channel 2 I PCM Serial Data Input for channel 2 O PCM Serial Data Output for channel 2 3-325 S5PV210_UM 3 2BSIZE & BALL MAP • Modem / CAMIF / CFCON / MIPI / KEYPAD / SROM (ADDR16_22) Pin Name Func0 Signal IO Func1 Signal IO Func2 Signal IO Func3 Signal IO Defaul t Reset XMSMADDR _0 MSM_ADDR[ 0] I CAM_B_DATA [0] I CF_ADDR[0] O MIPI_BYTE_ CLK O GPI I(L) XMSMADDR _1 MSM_ADDR[ 1] I CAM_B_DATA [1] I CF_ADDR[1] O MIPI_ESC_C LK O GPI I(L) XMSMADDR _2 MSM_ADDR[ 2] I CAM_B_DATA [2] I CF_ADDR[2] O TS_CLK I GPI I(L) XMSMADDR _3 MSM_ADDR[ 3] I CAM_B_DATA [3] I CF_IORDY I TS_SYNC I GPI I(L) XMSMADDR _4 MSM_ADDR[ 4] I CAM_B_DATA [4] I CF_INTRQ I TS_VAL I GPI I(L) XMSMADDR _5 MSM_ADDR[ 5] I CAM_B_DATA [5] I CF_DMARQ I TS_DATA I GPI I(L) XMSMADDR _6 MSM_ADDR[ 6] I CAM_B_DATA [6] I CF_DRESETN O TS_ERROR I GPI I(L) XMSMADDR _7 MSM_ADDR[ 7] I CAM_B_DATA [7] I CF_DMACKN O GPI I(L) XMSMADDR _8 MSM_ADDR[ 8] I CAM_B_PCLK I SROM_ADDR_16to2 2[0] O GPI I(L) XMSMADDR _9 MSM_ADDR[ 9] I CAM_B_VSYN C I SROM_ADDR_16to2 2[1] O GPI I(L) XMSMADDR _10 MSM_ADDR[ 10] I CAM_B_HREF I SROM_ADDR_16to2 2[2] O GPI I(L) XMSMADDR MSM_ADDR[ _11 11] I CAM_B_FIEL D I SROM_ADDR_16to2 2[3] O GPI I(L) XMSMADDR _12 MSM_ADDR[ 12] I CAM_B_CLKO UT O SROM_ADDR_16to2 2[4] O GPI I(L) XMSMADDR _13 MSM_ADDR[ 13] I KP_COL[0] IO SROM_ADDR_16to2 2[5] O GPI I(L) XMSMDATA_ 0 MSM_DATA[0 ] IO KP_COL[1] IO CF_DATA[0] IO GPI I(L) XMSMDATA_ 1 MSM_DATA[1 ] IO KP_COL[2] IO CF_DATA[1] IO GPI I(L) XMSMDATA_ 2 MSM_DATA[2 ] IO KP_COL[3] IO CF_DATA[2] IO GPI I(L) XMSMDATA_ 3 MSM_DATA[3 ] IO KP_COL[4] IO CF_DATA[3] IO GPI I(L) XMSMDATA_ 4 MSM_DATA[4 ] IO KP_COL[5] IO CF_DATA[4] IO GPI I(L) 3-326 S5PV210_UM XMSMDATA_ 5 MSM_DATA[5 ] IO KP_COL[6] IO CF_DATA[5] IO XMSMDATA_ 6 MSM_DATA[6 ] IO KP_COL[7] IO CF_DATA[6] IO XMSMDATA_ 7 MSM_DATA[7 ] IO KP_ROW[0] I CF_DATA[7] IO XMSMDATA_ 8 MSM_DATA[8 ] IO KP_ROW[1] I CF_DATA[8] IO XMSMDATA_ 9 MSM_DATA[9 ] IO KP_ROW[2] I CF_DATA[9] IO XMSMDATA_ 10 MSM_DATA[1 0] IO KP_ROW[3] I CF_DATA[10] IO XMSMDATA_ 11 MSM_DATA[1 1] IO KP_ROW[4] I CF_DATA[11] IO XMSMDATA_ 12 MSM_DATA[1 2] IO KP_ROW[5] I CF_DATA[12] IO XMSMDATA_ 13 MSM_DATA[1 3] IO KP_ROW[6] I CF_DATA[13] IO XMSMDATA_ 14 MSM_DATA[1 4] IO KP_ROW[7] I CF_DATA[14] IO XMSMDATA_ 15 MSM_DATA[1 5] IO KP_ROW[8] I CF_DATA[15] IO XMSMCSN MSM_CSn I KP_ROW[9] I CF_CSn[0] O XMSMWEN MSM_WEn I KP_ROW[10] I CF_CSn[1] O XMSMRN MSM_Rn I KP_ROW[11] I CF_IORN O XMSMIRQN MSM_IRQn O KP_ROW[12] I CF_IOWN O XMSMADVN MSM_ADVN I KP_ROW[13] I SROM_ADDR_16to2 2[6] O 3 2BSIZE & BALL MAP GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) GPI I(L) 3-327 S5PV210_UM 3 2BSIZE & BALL MAP Signal MSM_ADDR[13:0] MSM_DATA[15:0] MSM_CSn MSM_WEn MSM_Rn MSM_IRQn MSM_ADVN CAM_B_DATA[7:0] CAM_B_PCLK CAM_B_VSYNC CAM_B_HREF CAM_B_FIELD CAM_B_CLKOUT KP_COL[7:0] KP_ROW[13:0] CF_ADDR[2:0] CF_IORDY CF_INTRQ CF_DMARQ CF_DRESETN CF_DMACKN SROM_ADDR_16to22[6:0] CF_DATA[15:0] CF_CSn[0] CF_CSn[1] CF_IORN CF_IOWN MIPI_BYTE_CLK MIPI_ESC_CLK TS_CLK TS_SYNC TS_VAL TS_DATA TS_ERROR I/O Description I MODEM (MSM) IF Address (MSM_ADDR[13] should be ‘0’) IO MODEM (MSM) IF Data I MODEM (MSM) IF Chip Select I MODEM (MSM) IF Write enable I MODEM (MSM) IF Read enable O MODEM (MSM) IF Interrupt to MODEM I MODEM (MSM) IF Address Valid from MODEM Chip I Pixel Data driven by the external Video Player I Pixel Clock, driven by the external Video Player I Frame Sync, driven by the external Video Player I Horizontal Sync, driven by the external Video Player I FIELD signal, driven by the external Video Player O Master Clock to the Camera processor B O KeyIF_Column_data[7:0] I KeyIF_Row_data[13:0] O CF CARD address for ATAPI I CF Wait signal from CF card I CF Interrupt from CF card I CF DMA Request O CF DMA Reset O CF DMA Acknowledge O SROM Address bus [22:16] IO CF card DATA O CF chip select bank 0 O CF chip select bank 1 O CF Read strobe for I/O mode O CF Write strobe for I/O mode O MIPI BYTE clock for monitoring O MIPI ESC clock for monitoring I TSI system clock, 66MHz I TSI synchronization control signal I TSI valid signal I TSI input data I TSI error indicate signal 3-328 S5PV210_UM 3 2BSIZE & BALL MAP • Memory port 0 Pin Name Func0 Signal Func1 IO Signal IO XM0CSN_0 SROM_CSn[0] O XM0CSN_1 SROM_CSn[1] O XM0CSN_2 SROM_CSn[2] O NFCSn[0] O XM0CSN_3 SROM_CSn[3] O NFCSn[1] O XM0CSN_4 SROM_CSn[4] O NFCSn[2] O XM0CSN_5 SROM_CSn[5] O NFCSn[3] O XM0OEN EBI_OEn O XM0WEN EBI_WEn O XM0BEN_0 EBI_BEn[0] O XM0BEN_1 EBI_BEn[1] O XM0WAITN SROM_WAITn I XM0DATA_RD N EBI_DATA_RDn O XM0FCLE XM0FALE XM0FWEN XM0FREN XM0FRNB_0 XM0FRNB_1 XM0FRNB_2 XM0FRNB_3 XM0ADDR_0 XM0ADDR_1 XM0ADDR_2 XM0ADDR_3 XM0ADDR_4 XM0ADDR_5 XM0ADDR_6 XM0ADDR_7 XM0ADDR_8 XM0ADDR_9 XM0ADDR_10 NF_CLE O NF_ALE O NF_FWEn O NF_FREn O NF_RnB[0] I NF_RnB[1] I NF_RnB[2] I NF_RnB[3] I EBI_ADDR[0] O EBI_ADDR[1] O EBI_ADDR[2] O EBI_ADDR[3] O EBI_ADDR[4] O EBI_ADDR[5] O EBI_ADDR[6] O EBI_ADDR[7] O EBI_ADDR[8] O EBI_ADDR[9] O EBI_ADDR[10] O Func2 Signal IO Func3 Signal ONANDXL_CSn[0] ONANDXL_CSn[1] IO Defaul t Reset Func0 O(H) Func0 O(H) Func1 O(H) Func1 O(H) O Func3 O(H) O Func3 O(H) Func0 O(H) Func0 O(H) Func0 O(H) Func0 O(H) Func0 I Func0 O(L) ONANDXL_ADDRVALI D O Func3 O(L) ONANDXL_SMCLK O Func3 O(L) ONANDXL_RPn O Func3 O(H) Func3 O(H) ONANDXL_INT[0] I Func3 I ONANDXL_INT[1] I Func3 I Func3 I Func3 I Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) 3-329 S5PV210_UM Pin Name XM0ADDR_11 XM0ADDR_12 XM0ADDR_13 XM0ADDR_14 XM0ADDR_15 XM0DATA_0 XM0DATA_1 XM0DATA_2 XM0DATA_3 XM0DATA_4 XM0DATA_5 XM0DATA_6 XM0DATA_7 XM0DATA_8 XM0DATA_9 XM0DATA_10 XM0DATA_11 XM0DATA_12 XM0DATA_13 XM0DATA_14 XM0DATA_15 Func0 Signal IO EBI_ADDR[11] O EBI_ADDR[12] O EBI_ADDR[13] O EBI_ADDR[14] O EBI_ADDR[15] O EBI_DATA[0] IO EBI_DATA[1] IO EBI_DATA[2] IO EBI_DATA[3] IO EBI_DATA[4] IO EBI_DATA[5] IO EBI_DATA[6] IO EBI_DATA[7] IO EBI_DATA[8] IO EBI_DATA[9] IO EBI_DATA[10] IO EBI_DATA[11] IO EBI_DATA[12] IO EBI_DATA[13] IO EBI_DATA[14] IO EBI_DATA[15] IO Func1 Func2 Signal IO Signal IO 3 2BSIZE & BALL MAP Func3 Signal IO Defaul t Reset Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Func0 O(L) Signal SROM_CSn[5:4] SROM_CSn[3:2] SROM_CSn[1:0] EBI_OEn EBI_WEn EBI_BEn[1:0] SROM_WAITn EBI_DATA_RDn NF_CLE NF_ALE NF_FWEn I/O Description O Memory Port 0 SROM Chip select support up to 2 memory bank O Memory Port 0 SROM Chip select support up to 2 memory bank O Memory Port 0 SROM Chip select support up to 2 memory bank O Memory Port 0 SROM / OneNAND Output Enable O Memory Port 0 SROM / OneNAND Write Enable O Memory Port 0 SROM Byte Enable I Memory Port 0 SROM nWait O Memory Port 0 SROM/OneNAND/NAND/CF Output Enable O Memory Port 0 NAND Command Latch Enable O Memory Port 0 NAND Address Latch Enable O Memory Port 0 NAND Flash Write Enable 3-330 S5PV210_UM 3 2BSIZE & BALL MAP Signal NF_FREn NF_RnB[3:0] EBI_ADDR[15:0] EBI_DATA[15:0] NFCSn[0] NFCSn[1] NFCSn[2] NFCSn[3] ONANDXL_ADDRVALID ONANDXL_SMCLK ONANDXL_RPn ONANDXL_INT[1:0] I/O Description O Memory Port 0 NAND Flash Read Enalbe I Memory Port 0 NAND Flash Ready/Busy O Memory port 0 Address bus IO Memory port 0 Data bus O Memory Port 0 NAND Chip Select bank 0 O Memory Port 0 NAND Chip Select bank 1 O Memory Port 0 NAND Chip Select bank 2 O Memory Port 0 NAND Chip Select bank 3 O OneNANDXL Flash Address valid O OneNANDXL Flash clock O OneNANDXL Flash reset I OneNANDXL Flash Interrupt signal from OneNAND Device • Memory port 1 (Dedicated) Ball Name XM1ADDR_0 ~ XM1ADDR_15 XM1DATA_0 ~XM1DATA_31 XM1DQS_0 ~XM1DQS_3 XM1DQSn_0 ~XM1DQSn_3 XM1DQM_0 ~XM1DQM_3 XM1CKE_0 ~XM1CKE_1 XM1SCLK XM1nSCLK XM1CSn_0 ~XM1CSn_1 XM1RASn XM1CASn XM1WEn XM1GateIn I/O Description IO Memory port 1DRAM Address bus (16-bit) IO Memory port 1DRAM Data bus.(32-bit) IO Memory port 1DRAM Data Strobe (4-bit) IO Memory port 1DRAM Data Differential Strobe neg (4-bit) IO Memory port 1DRAM Data Mask (4-bit) IO Memory port 1DRAM Clock Enable (2-bit) IO Memory port 1DRAM Clock IO Memory port 1DRAM Inverted Clock of Xm1SCLK IO Memory port 1DRAM Chip Select support up to 2 memory bank (2-bit) IO Memory port 1DRAM Row Address Strobe IO Memory port 1DRAM Column Address Strobe IO Memory port 1DRAM Write Enable I Input signal for DQS cleaning signal Input 3-331 S5PV210_UM XM1GateOut O Output signal to DQS cleaning signal output 3 2BSIZE & BALL MAP 3-332 S5PV210_UM 3 2BSIZE & BALL MAP • Memory port 2 (Dedicated) Ball Name XM2ADDR_0 ~XM2ADDR_15 XM2DATA_0 ~XM2DATA_31 XM2DQS_0 ~XM2DQS_3 XM2DQSn_0 ~XM2DQSn_3 XM2DQM_0 ~XM2DQM_3 XM2CKE_0 ~XM2CKE_1 XM2SCLK XM2nSCLK XM2CSn_0 ~XM2CSn_1 XM2RASn XM2CASn XM2WEn XM2GateIn XM2GateOut I/O Description IO Memory port 2DRAM Address bus (16-bit) IO Memory port 2DRAM Data bus (32-bit) IO Memory port 2DRAM Data Strobe (4-bit) IO Memory port 2DRAM Data Differential Strobe neg (4-bit) IO Memory port 2DRAM Data Mask (4-bit) IO Memory port 2DRAM Clock Enable (2-bit) IO Memory port 2DRAM Clock IO Memory port 2DRAM Inverted Clock of Xm1SCLK IO Memory port 2DRAM Chip Select support up to 2 memory bank (2-bit) IO Memory port 2DRAM Row Address Strobe IO Memory port 2DRAM Column Address Strobe IO Memory port 2DRAM Write Enable I Input signal for DQS cleaning signal Input O Output signal to DQS cleaning signal output 3-333 S5PV210_UM 3 2BSIZE & BALL MAP • JTAG (Dedicated) Ball Name I/O XJTRSTN I XJTMS I XJTCK I XJTDI I Description XjTRSTn (TAP Controller Reset) resets the TAP controller at start. If debugger (black ICE) is not used, XjTRSTn pin must be at L or low active pulse. Pull-down resistor is connected. XjTMS (TAP Controller Mode Select) controls the sequence of the TAP controller’s states. Pull-up resistor is connected. XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic. Pull-down resistor is connected. XjTDI (TAP Controller Data Input) is the serial input for test instructions and data. Pull-up resistor is connected. XJTDO XJDBGSEL O XjTDO (TAP Controller Data Output) is the serial output for test instructions and data. I JTAG selection. 0: CORTEXA8 Core JTAG, 1: Peripherals JTAG • RESET / etc (Dedicated) Ball Name XOM_0 ~ XOM_5 XDDR2SEL XPWRRGTON XNRESET XCLKOUT XNRSTOUT XNWRESET XRTCCLKO I/O Description I Operating Mode control signals (6-bit) I Selection DDR type (LPDDR1/2 or DDR2). 0: LPDDR1/2, 1: DDR2 O Power Regulator enable I System Reset O Clock out signal I For External device reset control I System Warm Reset. O RTC Clock out • Clock (Dedicated) Ball Name I/O XRTCXTI I XRTCXTO O XXTI I XXTO O XUSBXTI I XUSBXTO O Description 32 KHz crystal input for RTC 32 KHz crystal output for RTC Crystal Input for internal osc circuit Crystal output for internal osc circuit. Crystal Input for internal USB circuit Crystal output for internal USB circuit 3-334 S5PV210_UM 3 2BSIZE & BALL MAP 3-335 S5PV210_UM - ADC/ DAC / HDMI/ MIPI (Dedicated) Ball Name XADCAIN_0 ~XADCAIN_9 XDACOUT XDACIREF XDACVREF XDACCOMP XHDMITX0P XHDMITX0N XHDMITX1P XHDMITX1N XHDMITX2P XHDMITX2N XHDMITXCP XHDMITXCN XHDMIREXT XHDMIXTI XHDMIXTO XMIPIMDP0 XMIPIMDP1 XMIPIMDP2 XMIPIMDP3 XMIPIMDN0 XMIPIMDN1 XMIPIMDN2 XMIPIMDN3 XMIPISDP0 XMIPISDP1 XMIPISDP2 XMIPISDP3 XMIPISDN0 XMIPISDN1 XMIPISDN2 XMIPISDN3 I/O Description I ADC Analog Input (10-bit) O Analog output of DAC I External resistor connection I Reference voltage input O External capacitor connection O HDMI Phy TX0 P O HDMI Phy TX0 N O HDMI Phy TX1 P O HDMI Phy TX1 N O HDMI Phy TX2 P O HDMI Phy TX2 N O HDMI Phy TX Clock P O HDMI Phy TX Clock N I HDMI Phy Registance I HDMI crystal input O HDMI crystal output IO Master DATA LANE0 DP for MIPI-DPHY IO Master DATA LANE1 DP for MIPI-DPHY IO Master DATA LANE2 DP for MIPI-DPHY IO Master DATA LANE3 DP for MIPI-DPHY IO Master DATA LANE0 DN for MIPI-DPHY IO Master DATA LANE1 DN for MIPI-DPHY IO Master DATA LANE2 DN for MIPI-DPHY IO Master DATA LANE3 DN for MIPI-DPHY IO Slave DATA LANE0 DP for MIPI-DPHY IO Slave DATA LANE1 DP for MIPI-DPHY IO Slave DATA LANE2 DP for MIPI-DPHY IO Slave DATA LANE3 DP for MIPI-DPHY IO Slave DATA LANE0 DN for MIPI-DPHY IO Slave DATA LANE1 DN for MIPI-DPHY IO Slave DATA LANE2 DN for MIPI-DPHY IO Slave DATA LANE3 DN for MIPI-DPHY 36 3 2BSIZE & BALL MAP 3-3- S5PV210_UM XMIPIMDPCLK XMIPIMDNCLK XMIPISDPCLK XMIPISDNCLK XMIPIVREG_0P4V IO Master CLK Lane DP for MIPI-DPHY IO Master CLK Lane DN for MIPI-DPHY IO Slave CLK Lane DP for MIPI-DPHY IO Slave CLK Lane DN for MIPI-DPHY IO Regulator capacitor for MIPI-DPHY 3 2BSIZE & BALL MAP • USB OTG / USB HOST 1.1 (Dedicated) Ball Name XUOTGDRVVUBS XUHOSTPWREN XUHOSTOVERCUR XUOTGDP XUOTGREXT XUOTGDM XUHOSTDP XUHOSTREXT XUHOSTDM XUOTGID XUOTGVBUS I/O Description O USB OTG charge pump enable O USB HOST charge pump enable I USB HOST over current flag IO USB OTG Data pin DATA(+) IO USB OTG External 44.2ohm (+/- 1%) resistor connection IO USB OTG Data pin DATA(-) IO USB HOST Data pin DATA(+) IO USB HOST External 44.2ohm (+/- 1%) resistor connection IO USB HOST Data pin DATA(-) IO USB OTG Mini-Receptacle Identifier IO USB OTG Mini-Receptacle Vbus • E-fuse / ABB (Dedicated) Ball Name XEFFSOURCE_0 XABBNBBG XABBPBBG I/O Description I Power PAD for efuse ROM's FSOURCE IO Analog Outout for NMOS body IO Analog Output for PMOS body 3-337 S5PV210_UM 3.2.1 POWER DOMAIN • Analog IO Power Power Domain Analog IO ADC DAC MIPI DPHY 38 3 2BSIZE & BALL MAP Ball Name XADCAIN_0 XADCAIN_1 XADCAIN_2 XADCAIN_3 XADCAIN_4 XADCAIN_5 XADCAIN_6 XADCAIN_7 XADCAIN_8 XADCAIN_9 VDD_ADC VSS_ADC XDACCOMP XDACIREF XDACOUT XDACVREF VDD_DAC_A VSS_DAC_A VDD_DAC VSS_DAC XMIPIMDN0 XMIPIMDN1 XMIPIMDN2 XMIPIMDN3 XMIPIMDNCLK XMIPIMDP0 XMIPIMDP1 XMIPIMDP2 XMIPIMDP3 XMIPIMDPCLK XMIPISDN0 XMIPISDN1 XMIPISDN2 XMIPISDN3 Ball No. AC11 AC12 AB11 AC10 Y11 W12 Y12 AA12 AA11 AB12 W10 W11 V4 W5 U5 V5 U7 U6 V7 V6 AD17 AD16 AD14 AD13 AD15 AE17 AE16 AE14 AE13 AE15 AE12 AE11 AE9 AE8 3-3- S5PV210_UM Power Domain HDMI PHY USB OTG 39 Ball Name XMIPISDNCLK XMIPISDP0 XMIPISDP1 XMIPISDP2 XMIPISDP3 XMIPISDPCLK XMIPIVREG_0P4V VDD_MIPI_A VDD_MIPI_D VDD_MIPI_PLL VSS_MIPI XHDMIREXT XHDMITX0N XHDMITX0P XHDMITX1N XHDMITX1P XHDMITX2N XHDMITX2P XHDMITXCN XHDMITXCP XHDMIXTI XHDMIXTO VDD_HDMI VDD_HDMI_PLL VDD_HDMI_OSC VSS_HDMI VSS_HDMI_PLL VSS_HDMI_OSC XUOTGDM XUOTGDP XUOTGID XUOTGREXT XUOTGVBUS VDD_UOTG_A VDD_UOTG_D VSS_UOTG_A 3 2BSIZE & BALL MAP Ball No. AE10 AD12 AD11 AD9 AD8 AD10 AC15 Y13 U12, U13 W14 U11, U14 W1 T1 T2 U1 U2 V1 V2 R1 R2 Y2 Y1 P6 R6 T7 R7 P7 T6 AE21 AD21 AD18 AE18 AC18 W16 U15 Y17 3-3- S5PV210_UM Power Domain USB HOST APLL MPLL VPLL EPLL Ball Name VSS_UOTG_AC VSS_UOTG_D XUHOSTDM XUHOSTDP XUHOSTREXT VDD_UHOST_A VDD_UHOST_D VSS_UHOST_A VSS_UHOST_AC VSS_UHOST_D VDD_APLL VSS_APLL VDD_MPLL VSS_MPLL VDD_VPLL VSS_VPLL VDD_EPLL VSS_EPLL 3 2BSIZE & BALL MAP Ball No. Y15 W17 AD19 AE19 AC17 Y16 W13 AA15 AA16 Y14 M20 M19 N20 N19 P20 P19 R20 R19 3-340 S5PV210_UM • Digital IO Power Power Domain Digital IO MDDR port 2 MDDR port 1 OneNAND(EBI) 41 Ball Name VDD_M2 VDD_M1 XM0ADDR_0 XM0ADDR_1 XM0ADDR_10 XM0ADDR_11 XM0ADDR_12 XM0ADDR_13 XM0ADDR_14 XM0ADDR_15 XM0ADDR_2 XM0ADDR_3 XM0ADDR_4 XM0ADDR_5 XM0ADDR_6 XM0ADDR_7 XM0ADDR_8 XM0ADDR_9 XM0BEN_0 XM0BEN_1 XM0CSN_0 XM0CSN_1 XM0CSN_2 XM0CSN_3 XM0CSN_4 XM0CSN_5 XM0DATA_0 XM0DATA_1 XM0DATA_10 XM0DATA_11 XM0DATA_12 XM0DATA_13 XM0DATA_14 XM0DATA_15 3 2BSIZE & BALL MAP Ball No. J17, K17, L17, M17 J13, J14, J15, J16 K5 L7 J3 K7 H6 G5 F4 H3 J4 H5 J6 K4 K6 J5 H4 G4 T3 N6 U3 T4 J1 N9 N3 N7 K3 L3 L4 M1 M3 M5 N5 P2 3-3- S5PV210_UM Power Domain LCD 42 Ball Name XM0DATA_2 XM0DATA_3 XM0DATA_4 XM0DATA_5 XM0DATA_6 XM0DATA_7 XM0DATA_8 XM0DATA_9 XM0DATA_RDN XM0FALE XM0FCLE XM0FREN XM0FRNB_0 XM0FRNB_1 XM0FRNB_2 XM0FRNB_3 XM0FWEN XM0OEN XM0WAITN XM0WEN VDD_M0 XVHSYNC XVSYS_OE XVVCLK XVVD_0 XVVD_1 XVVD_10 XVVD_11 XVVD_12 XVVD_13 XVVD_14 XVVD_15 XVVD_16 XVVD_17 XVVD_18 XVVD_19 3 2BSIZE & BALL MAP Ball No. L5 M4 N1 N2 P1 N4 L1 L2 M7 K2 K1 M2 R3 M6 V3 L6 J2 R4 W2 P4 K9, M9 AA13 AE4 AA10 AA9 AB9 AE6 AC8 Y8 AC7 AD6 AE5 AD7 AA7 AD5 AA6 3-3- S5PV210_UM Power Domain CAMERA AUDIO 43 Ball Name XVVD_2 XVVD_20 XVVD_21 XVVD_22 XVVD_23 XVVD_3 XVVD_4 XVVD_5 XVVD_6 XVVD_7 XVVD_8 XVVD_9 XVVDEN XVVSYNC XVVSYNC_LDI VDD_LCD XCICLKENB XCIDATA_0 XCIDATA_1 XCIDATA_2 XCIDATA_3 XCIDATA_4 XCIDATA_5 XCIDATA_6 XCIDATA_7 XCIFIELD XCIHREF XCIPCLK XCIVSYNC VDD_CAM XI2S0CDCLK XI2S0LRCK XI2S0SCLK XI2S0SDI XI2S0SDO_0 XI2S0SDO_1 3 2BSIZE & BALL MAP Ball No. AB8 AB5 AC5 AC6 Y7 AB7 Y9 AB6 AE7 AC9 AA8 W9 AB10 Y10 W8 U10 AA18 AB15 AB16 AB20 AA19 AB21 Y18 AB17 AA17 AB19 AB14 AC21 AA14 V19 AC4 AE3 AD2 AE2 AD3 AC3 3-3- S5PV210_UM Power Domain MODEM 44 Ball Name XI2S0SDO_2 XI2S1CDCLK XI2S1LRCK XI2S1SCLK XI2S1SDI XI2S1SDO XPCM0EXTCLK XPCM0FSYNC XPCM0SCLK XPCM0SIN XPCM0SOUT XCLKOUT VDD_AUD XMSMADDR_0 XMSMADDR_1 XMSMADDR_10 XMSMADDR_11 XMSMADDR_12 XMSMADDR_13 XMSMADDR_2 XMSMADDR_3 XMSMADDR_4 XMSMADDR_5 XMSMADDR_6 XMSMADDR_7 XMSMADDR_8 XMSMADDR_9 XMSMADVN XMSMCSN XMSMDATA_0 XMSMDATA_1 XMSMDATA_10 XMSMDATA_11 XMSMDATA_12 XMSMDATA_13 XMSMDATA_14 3 2BSIZE & BALL MAP Ball No. AA3 AB3 AC2 AD1 AA5 AB4 AA1 AB1 AA2 AB2 AC1 AE24 U9, U19 H1 G6 F1 G3 E5 F2 E4 H7 G1 H2 F5 D5 F6 G2 A4 G8 F3 E2 B1 C3 C4 B2 B3 3-3- S5PV210_UM Power Domain KEY System 0 45 Ball Name XMSMDATA_15 XMSMDATA_2 XMSMDATA_3 XMSMDATA_4 XMSMDATA_5 XMSMDATA_6 XMSMDATA_7 XMSMDATA_8 XMSMDATA_9 XMSMIRQN XMSMRN XMSMWEN VDD_MODEM XEINT_16 XEINT_17 XEINT_18 XEINT_19 XEINT_20 XEINT_21 XEINT_22 XEINT_23 XEINT_24 XEINT_25 XEINT_26 XEINT_27 XEINT_28 XEINT_29 XEINT_30 XEINT_31 VDD_KEY XXTI XXTO XOM_0 XOM_1 XOM_2 XOM_3 3 2BSIZE & BALL MAP Ball No. A2 E1 D3 D1 E3 D2 C1 C2 D4 A3 G9 B4 J7 U20 Y23 V21 AB24 AA21 AA23 AC25 Y20 AC24 AB22 AD25 Y22 AD24 AA20 Y19 AB23 T17 U24 U25 T23 T22 V23 U21 3-3- S5PV210_UM Power Domain System 1 46 Ball Name XOM_4 XOM_5 XPWRRGTON XNRESET XNRSTOUT XNWRESET XEINT_0 XEINT_1 XEINT_2 XEINT_3 XEINT_4 XEINT_5 XEINT_6 XEINT_7 XUOTGDRVVBUS XUHOSTPWREN XUHOSTOVERCUR XDDR2SEL XUSBXTI XUSBXTO XJTRSTN XJTMS XJTCK XJTDI XJTDO XJDBGSEL VDD_SYS0 XEINT_8 XEINT_9 XEINT_10 XEINT_11 XEINT_12 XEINT_13 XEINT_14 XEINT_15 VDD_SYS1 3 2BSIZE & BALL MAP Ball No. V25 V24 U22 U23 T20 T21 Y21 W25 W23 Y25 AA22 W24 W21 AA25 AC19 AD23 AC22 AB18 AD20 AE20 P5 R5 U4 T5 W3 P3 P9, U16, U17 V20 V22 Y24 W22 AA24 AC23 AB25 W20 T19 3-3- S5PV210_UM Power Domain External Peri 0 External Peri 1 47 Ball Name XMMC0CDN XMMC0CLK XMMC0CMD XMMC0DATA_0 XMMC0DATA_1 XMMC0DATA_2 XMMC0DATA_3 XMMC1CDN XMMC1CLK XMMC1CMD XMMC1DATA_0 XMMC1DATA_1 XMMC1DATA_2 XMMC1DATA_3 XSPICLK_0 XSPICSN_0 XSPIMISO_0 XSPIMOSI_0 XURXD_0 XUTXD_0 XUCTSN_0 XURTSN_0 XURXD_1 XUTXD_1 XUCTSN_1 XURTSN_1 XI2C0SDA XI2C0SCL XPWMTOUT_0 XPWMTOUT_1 XPWMTOUT_2 XPWMTOUT_3 VDD_EXT0 XMMC2CDN XMMC2CLK XMMC2CMD 3 2BSIZE & BALL MAP Ball No. F7 B5 E6 C5 A5 D6 C6 C7 B6 F8 D7 E7 A6 F9 B7 E9 J9 J11 C8 D8 D9 A7 G10 F10 B8 E10 F11 C9 E8 B9 A8 F12 J10 AA4 Y6 W6 3-3- S5PV210_UM Power Domain External Peri 2 RTC Clock Out RTC EFUSE(Security) Ball Name XMMC2DATA_0 XMMC2DATA_1 XMMC2DATA_2 XMMC2DATA_3 XI2C1SCL XI2C1SDA XI2C2SCL XI2C2SDA XURXD_2 XUTXD_2 XURXD_3 XUTXD_3 VDD_EXT1 XMMC3CDN XMMC3CLK XMMC3CMD XMMC3DATA_0 XMMC3DATA_1 XMMC3DATA_2 XMMC3DATA_3 XSPICLK_1 XSPICSN_1 XSPIMISO_1 XSPIMOSI_1 VDD_EXT2 XRTCCLKO VDD_CKO XRTCXTI XRTCXTO VDD_RTC XEFFSOURCE_0 3 2BSIZE & BALL MAP Ball No. Y4 Y5 Y3 W4 AD22 AE23 AE22 AC16 AC20 AC14 AC13 AB13 T9, W18 E11 A9 D10 B10 C10 D11 A10 G12 B11 G13 A11 G11 R22 P17 T24 T25 P21 AD4 3-348 S5PV210_UM • Internal Power Power Domain Internal Internal Logic ARM (Cortex-A8) Alive Ball Name VDD_INT VDD_ARM VDD_ALIVE 3 2BSIZE & BALL MAP Ball No. K13, K14, K15, L10, L11, M11, N10, N11, P11, R11, R12, R13, T11 L13, L14, L15, M13, M14, M15, N14, N15, N16, P14, P15 R17, W15 3-349 S5PV210_UM • Common GND Power Domain Internal Logic, Digital IO Common GND Analog IO 3 2BSIZE & BALL MAP Ball Name VSS VSS_APLL VSS_EPLL VSS_MPLL VSS_VPLL VSS_ADC VSS_DAC VSS_DAC_A VSS_HDMI VSS_HDMI_OSC VSS_HDMI_PLL VSS_MIPI VSS_UHOST_A VSS_UHOST_AC VSS_UHOST_D VSS_UOTG_A VSS_UOTG_AC VSS_UOTG_D Ball No. A1, A25, AE1, AE25, G19, G7, J12, K10, K11, K12, K16, K19, L12, L16, L9, M10, M12, M16, M19, N12, N17, N19, P10, P12, P13, P16, P19, R10, R14, R15, R16, R19, R9, T10, T12, T13, T14, T15, T16, W19, W7 M20 R20 N20 P20 W11 V6 U6 R7 T6 P7 U11, U14 AA15 AA16 Y14 Y17 Y15 W17 3-350 S5PV210_UM 3.2.2 PACKAGE DIMENSION 3 2BSIZE & BALL MAP Figure 3-2 S5PV210 Package Dimension (584-FCFBGA) − Top View 3-351 S5PV210_UM 3 2BSIZE & BALL MAP Figure 3-3 S5PV210 Package Dimension (584-FCFBGA) − Side View 3-352 Section 2 SYSTEM Table of Contents 1 Chip ID.........................................................................................................1-1 1.1 Overview of CHIP ID................................................................................................................................ 1-1 1.2 Register Description................................................................................................................................. 1-1 1.2.1 Register Map .................................................................................................................................... 1-1 2 General Purpose Input/ Output .................................................................2-2 2.1 Overview .................................................................................................................................................. 2-2 2.1.1 Features............................................................................................................................................ 2-3 2.1.2 Input/ Output Configuration .............................................................................................................. 2-3 2.1.3 S5PV210 Input/ Output Types.......................................................................................................... 2-3 2.1.4 IO Driver strength ............................................................................................................................. 2-4 2.1.5 Input/ Output Description.................................................................................................................. 2-8 2.2 Register Description............................................................................................................................... 2-25 2.2.1 Register Map .................................................................................................................................. 2-25 2.2.2 Port Group GPA0 Control Register ................................................................................................ 2-43 2.2.3 Port Group GPA1 Control Register ................................................................................................ 2-45 2.2.4 Port Group GPB Control Register .................................................................................................. 2-47 2.2.5 Port Group GPC0 Control Register ................................................................................................ 2-49 2.2.6 Port Group GPC1 Control Register ................................................................................................ 2-51 2.2.7 Port Group GPD0 Control Register ................................................................................................ 2-53 2.2.8 Port Group GPD1 Control Register ................................................................................................ 2-55 2.2.9 Port Group GPE0 Control Register ................................................................................................ 2-57 2.2.10 Port Group GPE1 Control Register .............................................................................................. 2-59 2.2.11 Port Group GPF0 Control Register............................................................................................... 2-61 2.2.12 Port Group GPF1 Control Register............................................................................................... 2-64 2.2.13 Port Group GPF2 Control Register............................................................................................... 2-67 2.2.14 Port Group GPF3 Control Register............................................................................................... 2-70 2.2.15 Port Group GPG0 Control Register .............................................................................................. 2-72 2.2.16 Port Group GPG1 Control Register .............................................................................................. 2-74 2.2.17 Port Group GPG2 Control Register .............................................................................................. 2-76 2.2.18 Port Group GPG3 Control Register .............................................................................................. 2-78 2.2.19 Port Group GPI Control Register.................................................................................................. 2-80 2.2.20 Port Group GPJ0 Control Register ............................................................................................... 2-82 2.2.21 Port Group GPJ1 Control Register ............................................................................................... 2-85 2.2.22 Port Group GPJ2 Control Register ............................................................................................... 2-87 2.2.23 Port Group GPJ3 Control Register ............................................................................................... 2-90 2.2.24 Port Group GPJ4 Control Register ............................................................................................... 2-93 2.2.25 Port Group MP0_1 Control Register............................................................................................. 2-95 2.2.26 Port Group MP0_2 Control Register............................................................................................. 2-97 2.2.27 Port Group MP0_3 Control Register............................................................................................. 2-99 2.2.28 Port Group MP0_4 Control Register........................................................................................... 2-102 2.2.29 Port Group MP0_5 Control Register........................................................................................... 2-104 2.2.30 Port Group MP0_6 Control Register........................................................................................... 2-106 2.2.31 Port Group MP0_7 Control Register........................................................................................... 2-108 2.2.32 Port Group MP1_0 Control Register........................................................................................... 2-110 2.2.33 Port Group MP1_1 Control Register........................................................................................... 2-110 2.2.34 Port Group MP1_2 Control Register........................................................................................... 2-111 2.2.35 Port Group MP1_3 Control Register........................................................................................... 2-111 2.2.36 Port Group MP1_4 Control Register........................................................................................... 2-112 2.2.37 Port Group MP1_5 Control Register........................................................................................... 2-112 2.2.38 Port Group MP1_6 Control Register........................................................................................... 2-113 2.2.39 Port Group MP1_7 Control Register........................................................................................... 2-113 2.2.40 Port Group MP1_8 Control Register........................................................................................... 2-114 2.2.41 Port Group MP2_0 Control Register........................................................................................... 2-114 2.2.42 Port Group MP2_1 Control Register........................................................................................... 2-115 2.2.43 Port Group MP2_2 Control Register........................................................................................... 2-115 2.2.44 Port Group MP2_3 Control Register........................................................................................... 2-116 2.2.45 Port Group MP2_4 Control Register........................................................................................... 2-116 2.2.46 Port Group MP2_5 Control Register........................................................................................... 2-117 2.2.47 Port Group MP2_6 Control Register........................................................................................... 2-117 2.2.48 Port Group MP2_7 Control Register........................................................................................... 2-118 2.2.49 Port Group MP2_8 Control Register........................................................................................... 2-118 2.2.50 Port Group ETC0 Control Register............................................................................................. 2-119 2.2.51 Port Group ETC1 Control Register............................................................................................. 2-120 2.2.52 Port Group ETC2 Control Register............................................................................................. 2-122 2.2.53 Port Group ETC3 is reserved ..................................................................................................... 2-124 2.2.54 Port Group ETC4 ........................................................................................................................ 2-124 2.2.55 GPIO Interrupt Control Registers ............................................................................................... 2-125 2.2.56 Port Group GPH0 Control Register ............................................................................................ 2-234 2.2.57 Port Group GPH1 Control Register ............................................................................................ 2-236 2.2.58 Port Group GPH2 Control Register ............................................................................................ 2-238 2.2.59 Port Group GPH3 Control Register ............................................................................................ 2-240 2.2.60 External Interrupt Control Registers ........................................................................................... 2-242 2.2.61 Extern Pin Configuration Registers in Power down Mode ......................................................... 2-262 3 Clock Controller .........................................................................................3-1 3.1 Clock Domains ......................................................................................................................................... 3-1 3.2 Clock Declaration ..................................................................................................................................... 3-2 3.2.1 Clocks from Clock Pads ................................................................................................................... 3-2 3.2.2 Clocks from CMU.............................................................................................................................. 3-3 3.3 Clock Relationship ................................................................................................................................... 3-4 3.3.1 Recommended PLL PMS Value for APLL........................................................................................ 3-5 3.3.2 Recommended PLL PMS Value for MPLL ....................................................................................... 3-6 3.3.3 Recommended PLL PMS Value for EPLL........................................................................................ 3-6 3.3.4 Recommended PLL PMS Value for VPLL........................................................................................ 3-7 3.4 Clock Generation ..................................................................................................................................... 3-8 3.5 Clock Configuration Procedure .............................................................................................................. 3-11 3.5.1 Clock Gating ................................................................................................................................... 3-11 3.6 Special Clock Description ...................................................................................................................... 3-12 3.6.1 Special Clock Table ........................................................................................................................ 3-12 3.7 Register Description............................................................................................................................... 3-14 3.7.1 Register Map .................................................................................................................................. 3-14 3.7.2 PLL Control Registers .................................................................................................................... 3-18 3.7.3 Clock Source Control Registers ..................................................................................................... 3-25 3.7.4 Clock Divider Control Register ....................................................................................................... 3-34 3.7.5 Clock Gating Control Register ........................................................................................................ 3-39 3.7.6 Clock Output Configuration Register .............................................................................................. 3-52 3.7.7 Clock Divider Status SFRs ............................................................................................................. 3-54 3.7.8 Clock MUX Status SFRs ................................................................................................................ 3-56 3.7.9 Other SFRs..................................................................................................................................... 3-58 3.7.10 IEM Control SFRs......................................................................................................................... 3-58 3.7.11 Miscellaneous SFRs..................................................................................................................... 3-64 4 Power Management....................................................................................4-1 4.1 Overview of PMU ..................................................................................................................................... 4-1 4.2 FunctionAL Description of PMU............................................................................................................... 4-2 4.3 System Power Mode................................................................................................................................ 4-4 4.3.1 Overview........................................................................................................................................... 4-4 4.3.2 Normal Mode .................................................................................................................................... 4-7 4.3.3 IDLE Mode........................................................................................................................................ 4-9 4.3.4 DEEP-IDLE Mode............................................................................................................................. 4-9 4.3.5 STOP Mode .................................................................................................................................... 4-11 4.3.6 DEEP-STOP Mode ......................................................................................................................... 4-13 4.3.7 SLEEP Mode .................................................................................................................................. 4-15 4.4 System Power Mode Transition ............................................................................................................. 4-17 4.4.1 Transition Entering/ Exiting Condition ............................................................................................ 4-19 4.5 Cortex-A8 Power Mode.......................................................................................................................... 4-21 4.5.1 Overview......................................................................................................................................... 4-21 4.5.2 Cortex-A8 Power Mode Transition ................................................................................................. 4-21 4.5.3 State Save and Restore ................................................................................................................. 4-24 4.6 Wakeup Sources.................................................................................................................................... 4-25 4.6.1 External Interrupts .......................................................................................................................... 4-25 4.6.2 RTC Alarm ...................................................................................................................................... 4-25 4.6.3 System Timer.................................................................................................................................. 4-25 4.7 External Power Control .......................................................................................................................... 4-26 4.7.1 USB OTG PHY ............................................................................................................................... 4-27 4.7.2 HDMI PHY ...................................................................................................................................... 4-27 4.7.3 MIPI D-PHY .................................................................................................................................... 4-28 4.7.4 PLL ................................................................................................................................................. 4-28 4.7.5 DAC ................................................................................................................................................ 4-29 4.7.6 ADC I/O .......................................................................................................................................... 4-30 4.7.7 POR ................................................................................................................................................ 4-30 4.8 Internal memory control ......................................................................................................................... 4-31 4.8.1 SRAM ............................................................................................................................................. 4-31 4.8.2 ROM ............................................................................................................................................... 4-32 4.9 Reset Control ......................................................................................................................................... 4-33 4.9.1 Reset Types.................................................................................................................................... 4-33 4.9.2 Hardware Reset.............................................................................................................................. 4-33 4.10 Register Description............................................................................................................................. 4-38 4.10.1 Register Map ................................................................................................................................ 4-38 4.10.2 Clock Control Register.................................................................................................................. 4-40 4.10.3 Reset Control Register ................................................................................................................. 4-41 4.10.4 Power Management Register ....................................................................................................... 4-42 4.10.5 MISC Register .............................................................................................................................. 4-53 5 Intelligent Energy Management ................................................................5-1 5.1 Overview OF Intelligent Energy Management ......................................................................................... 5-1 5.1.1 Key Features of Intelligent Energy Management ............................................................................. 5-2 5.1.2 Block Diagram .................................................................................................................................. 5-3 5.2 Functional Description of Intelligent Energy Management ...................................................................... 5-4 5.2.1 IEM System Components................................................................................................................. 5-4 5.2.2 IEM System Operation ..................................................................................................................... 5-9 5.3 IEM Implementation and Driver Setting ................................................................................................. 5-13 5.3.1 Definition of Performance ............................................................................................................... 5-13 5.3.2 HPM Structure and Closed-Loop Behavior .................................................................................... 5-14 5.3.3 Initialization Sequence.................................................................................................................... 5-17 5.4 I/O Description ....................................................................................................................................... 5-18 5.5 Register Description............................................................................................................................... 5-19 5.5.1 Register Map .................................................................................................................................. 5-19 5.5.2 IEC Related Registers .................................................................................................................... 5-22 5.5.3 APC1 Related Registers................................................................................................................. 5-34 6 BOOTING SEQUENCE ...............................................................................6-1 6.1 Overview of Booting Sequence................................................................................................................ 6-1 6.2 Scenario Description................................................................................................................................ 6-3 6.2.1 Reset Status ..................................................................................................................................... 6-3 6.2.2 Booting Sequence Example ............................................................................................................. 6-4 6.2.3 Fixed PLL and Clock Setting ............................................................................................................ 6-6 6.2.4 OM Pin Configuration ....................................................................................................................... 6-7 6.2.5 Secure Booting ................................................................................................................................. 6-9 List of Figures Figure Number Title Page Number Figure 2-1 GPIO Block Diagram ........................................................................................................................ 2-8 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 S5PV210 Clock Domains ................................................................................................................. 3-1 S5PV210 Top-Level Clocks.............................................................................................................. 3-2 S5PV210 Clock Generation Circuit 1 ............................................................................................... 3-9 CLKOUT Waveform with DCLK Divider ......................................................................................... 3-53 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 State Transition Diagram of Power Mode....................................................................................... 4-17 Internal Operation During Power Mode Transition ......................................................................... 4-18 Cortex-A8 Power Mode Transition Diagram................................................................................... 4-22 Power-ON/OFF Reset Sequence ................................................................................................... 4-34 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Intelligent Energy Manager Solution................................................................................................. 5-1 IEM Block Diagram ........................................................................................................................... 5-3 PowerWise Performance Tracking and Voltage Adjustment............................................................ 5-6 IEM Closed-Loop Voltage Generation Flow in HPM and APC1..................................................... 5-14 IEM Closed-Loop Control Flow in APC1 HPM Delay ..................................................................... 5-15 HPM Delay Tap structure in S5PV210 ........................................................................................... 5-16 Figure 6-1 Figure 6-2 Figure 6-3 Block Diagram of Booting Time Operation ....................................................................................... 6-2 Total Booting Code Sequence Flow Chart ....................................................................................... 6-4 Secure Booting Diagram................................................................................................................. 6-10 List of Tables Table Number Title Page Number Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 APLL PMS Value ............................................................................................................................... 3-5 MPLL PMS Value............................................................................................................................... 3-6 EPLL PMS Value ............................................................................................................................... 3-6 VPLL PMS Value ............................................................................................................................... 3-7 Maximum Operating Frequency for Each Sub-block ....................................................................... 3-10 Special Clocks in S5PV210 ............................................................................................................. 3-12 I/O Clocks in S5PV210 .................................................................................................................... 3-13 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Comparison of Power Saving Techniques......................................................................................... 4-2 S5PV210 Power Domains of Internal Logic....................................................................................... 4-3 Power Mode Summary ...................................................................................................................... 4-5 Power Saving Mode Entering/Exiting Condition .............................................................................. 4-19 Cortex-A8 Power Control ................................................................................................................. 4-23 Relationship Among Power Mode Wakeup Sources ....................................................................... 4-25 S5PV210 External Power Control.................................................................................................... 4-26 The Status of MPLL and SYSCLK After Wake-Up .......................................................................... 4-29 S5PV210 Internal Memory Control .................................................................................................. 4-31 Register Initialization Due to Various Resets................................................................................. 4-37 Table 5-1 Example Divider Values for 1600MHz PLL Output.......................................................................... 5-13 Table 5-2 Example Divider Values for 833MHz PLL Output............................................................................ 5-13 Table 6-1 Table 6-2 Table 6-3 Functions Needed for Various Reset Status...................................................................................... 6-3 First Boot Loader's Clock Speed at 24 MHz External Crystal ........................................................... 6-6 OM Pin Setting for Various Booting Option ....................................................................................... 6-7 S5PV210_UM 1 0BCHIP ID 1 CHIP ID 1.1 OVERVIEW OF CHIP ID The S5PV210 includes a Chip ID block for the software (SW) that sends and receives APB interface signals to the bus system. Chip ID is placed on the first address of the SFR region (0xE0000_0000). The product ID register supplies product ID, revision number and device ID. Except product ID, electrical fuse ROM (e-from) provides all information bits. 1-1 S5PV210_UM 1 0BCHIP ID 1.2 REGISTER DESCRIPTION 1.2.1 REGISTER MAP Register PRO_ID Address 0xE000_0000 R/W Description R Product information Reset Value 0x43110020 1.2.1.1 Product ID Register (PRO_ID, R, Address = 0xE000_0000) PRO_ID Product ID Reserved Rev. Number Bit [31:12] [11:8] [7:4] Description Product ID The product ID allocated to S5PV210 is “0x43110” Reserved bits Revision Number Device ID [3:0] Device ID Initial State 0x43110 0x2 0x0 NOTE: 1. PRO_ID register[7:0] depends on the e-fuse ROM value. As power on sequence is progressing, the e-fuse ROM values are loaded to the registers. It can read the loaded current e-fuse ROM values. 1-1 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2 GENERAL PURPOSE INPUT/ OUTPUT This chapter describes the General Purpose Input/ Output (GPIO). 2.1 OVERVIEW S5PV210 includes 237 multi-functional input/ output port pins and 142 memory port pins. There are 34 general port groups and 2 memory port groups as listed below: • GPA0: 8 in/out port - 2xUART with flow control • GPA1: 4 in/out port - 2xUART without flow control or 1xUART with flow control • GPB: 8 in/out port - 2x SPI • GPC0: 5 in/out port - I2S, PCM, AC97 • GPC1: 5 in/out port - I2S, SPDIF, LCD_FRM • GPD0: 4 in/out port - PWM • GPD1: 6 in/out port - 3xI2C, PWM, IEM • GPE0,1: 13 in/out port - Camera I/F • GPF0,1,2,3: 30 in/out port - LCD I/F • GPG0,1,2,3: 28 in/out port - 4xMMC channel (Channel 0 and 2 support 4-bit and 8-bit mode, but channel 1, and channel 3 support only 4-bit mode) • GPH0,1,2,3: 32 in/out port - Key pad, External Wake-up (up-to 32-bit). (GPH* groups are in Alive region) • GPI: Low Power I2S, PCM (in/out port is not used), PDN configuration for power down is controlled by AUDIO_SS PDN Register. • GPJ0,1,2,3,4: 35 in/out port - Modem IF, CAMIF, CFCON, KEYPAD, SROM ADDR[22:16] • MP0_1,2,3: 20 in/out port - Control signals of EBI (SROM, NF, OneNAND) • MP0_4,5,6,7: 32 in/out memory port - EBI (For more information about EBI configuration, refer to Chapter 5, and 6) • MP1_0~8: 71 DRAM1 ports (in/out port is not used) • MP2_0~8: 71 DRAM2 ports (in/out port is not used) • ETC0, ETC1, ETC2, ETC4: 28 in/out ETC ports - JTAG, Operating Mode, RESET, CLOCK (ETC3 is reserved) 2-2 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.1 FEATURES The key features of GPIO include: • Controls 146 GPIO Interrupts • Controls 32 External Interrupts • 237 multi-functional input / output ports • Controls pin states in Sleep Mode except GPH0, GPH1, GPH2, and GPH3 ( GPH* pins are alive-pads) 2.1.2 INPUT/ OUTPUT CONFIGURATION Configurable Input/ Output (I/O) is subdivided into Type A and Type B. 2.1.3 S5PV210 INPUT/ OUTPUT TYPES I/O Types A I/O Group GPA0, GPA1, GPC0, GPC1, GPD0, GPD1, GPE0, GPE1, GPF0, GPF1, GPF2, GPF3, GPH0, GPH1, GPH2, GPH3, GPI, GPJ0, GPJ1, GPJ2, GPJ3, GPJ4 B GPB, GPG0, GPG1, GPG2, GPG3, MP0 C MP1, MP2 Description Normal I/O (3.3V I/O) Fast I/O (3.3V I/O) DRAM I/O (1.8V IO) 2-3 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.4 IO DRIVER STRENGTH 2.1.4.1 Type A IO Driver Strength ( VDD=3.3V±0.3V) Parameter Driver Type 3.3V IO DS0=0,DS1=0 DS0=0,DS1=1 DS0=1,DS1=0 DS0=1,DS1=1 Isink Isource Isink Isource Isink Isource Isink Isource Currents Worst Typical Best VDD=3.00V VDD=3.30V VDD=3.60V T=125℃ T=25℃ T=-40℃ Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V 7.005 mA 11.19 mA 15.92 mA -7.103 mA -10.88 mA -15.63 mA 11.69 mA 18.67 mA 26.54 mA -11.37 mA -17.42 mA -25.02 mA 16.35 mA 26.12 mA 37.15 mA -17.06 mA -26.14 mA -37.53 mA 30.38 mA 48.52 mA 69.01 mA -28.44 mA -43.56 mA -62.55 mA ( VDD=2.5V±0.2V) Parameter Driver Type DS0=0,DS1=0 3.3V IO DS0=0,DS1=1 DS0=1,DS1=0 DS0=1,DS1=1 Isink Isource Isink Isource Isink Isource Isink Isource Currents Worst Typical Best VDD=2.30V T=125℃ VDD=2.50V T=25℃ VDD=2.70V T=-40℃ Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V 4.497 mA 7.461 mA 11.12 mA -4.405 mA -6.993 mA -10.42 mA 7.501 mA 12.44 mA 18.55 mA -7.053 mA -11.19 mA -16.67 mA 10.50 mA 17.41 mA 25.96 mA -10.58 mA -16.79 mA -24.75 mA 19.50 mA 32.35 mA 48.22 mA -17.63 mA -27.98 mA -41.68 mA 2-4 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT ( VDD=1.8V±0.15V) Parameter Driver Type Currents Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=12 ℃ T=25℃ T=-40℃ Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V DS0=0,DS1=0 Isink Isource 2.263 mA -2.272 mA 4.057 mA -3.835 mA 6.568 mA -6.081 mA 3.3V IO DS0=0,DS1=1 DS0=1,DS1=0 Isink Isource Isink Isource 3.775 mA -3.636 mA 5.282 mA -5.454 mA 6.767 mA -6.136 mA 9.469 mA -9.204 mA 10.95 mA -9.729 mA 15.33 mA -14.59 mA DS0=1,DS1=1 Isink Isource 9.813 mA -9.091 mA 17.59 mA -15.34 mA 28.48 mA -24.32 mA NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD - Mesured point is different from measurement spec of 65nm IO Driver 2.1.4.2 Type B IO Driver Strength ( VDD=3.3V±0.3V ) Parameter Driver Type DS0=0,DS1=0 3.3V IO DS0=0,DS1=1 DS0=1,DS1=0 DS0=1,DS1=1 Isink Isource Isink Isource Isink Isource Isink Isource Currents Worst VDD=3.00V T=125℃ Process=Slow Isink at VDD*0.2V Isource at VDD*0.8V Typical Best VDD=3.30V VDD=3.60V T=25℃ T=-40℃ Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V 2.79mA 4.49mA 6.47mA -2.78mA -4.26mA -6.12mA 11.18mA 17.98mA 25.88mA -11.11mA -17.04mA -24.49mA 19.56mA 31.46mA 45.29mA -19.44mA -29.81mA -42.86mA 27.95mA 44.94mA 64.7mA -27.77mA -42.59mA -61.24mA 2-5 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT ( VDD=2.5V±0.2V ) Parameter Driver Type DS0=0,DS1=0 3.3V IO DS0=0,DS1=1 DS0=1,DS1=0 DS0=1,DS1=1 Isink Isource Isink Isource Isink Isource Isink Isource Currents Worst VDD=2.30V T=125℃ Process=Slow Isink at VDD*0.2V Isource at VDD*0.8V Typical Best VDD=2.50V T=25℃ VDD=2.70V T=-40℃ Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V 1.85mA 3.05mA 4.53mA -1.72mA -2.73mA -4.08mA 7.41mA 12.22mA 18.11mA -6.88mA -10.93mA -16.3mA 12.97mA 21.38mA 31.69mA -12.04mA -19.12mA -28.52mA 18.53mA 30.54mA 45.27mA -17.19mA -27.32mA -40.75mA ( VDD=1.8V±0.15V ) Parameter Driver Type Currents Worst VDD=1.65V T=12 ℃ Process=Slow Isink at VDD*0.2V Isource at VDD*0.8V Typical Best VDD=1.80V VDD=1.95V T=25℃ T=-40℃ Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V DS0=0,DS1=0 Isink Isource 0.99mA -0.91mA 1.73mA -1.53mA 2.74mA -2.41mA 3.3V IO DS0=0,DS1=1 DS0=1,DS1=0 Isink Isource Isink Isource 3.96mA -3.63mA 6.93mA -6.35mA 6.93mA -6.1mA 12.12mA -10.68mA 10.94mA -9.64mA 19.14mA -16.88mA DS0=1,DS1=1 Isink Isource 9.9mA -9.06mA 17.32mA -15.26mA 27.35mA -24.11mA NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD - Mesured point is different from measurement spec of 65nm IO Driver 2-6 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.4.3 Type C IO Driver Strength ( VDD=1.8V±VDDx10% ) Parameter Driver Type DS0=0,DS1=0 DS0=0,DS1=1 1.8V MDDR IO DS0=1,DS1=0 DS0=1,DS1=1 Isink Isource Isink Isource Isink Isource Isink Isource Currents Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=125℃ T=25℃ T=-25℃ Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V 3.37mA 5.60mA 8.36mA -2.62mA -4.32mA -6.67mA 6.74mA 11.21mA 16.73mA -6.10mA -10.08mA -15.58mA 10.10mA 16.80mA 25.07mA -6.97mA -11.51mA -17.80mA 11.77mA 19.59mA 29.24mA -11.32mA -18.70mA -28.90mA ( VDD=1.2V±VDDx10% ) Parameter Driver Type Currents Worst Typical Best VDD=1.045V T=125℃ VDD=1.1V T=25℃ VDD=1.155V T=-25℃ Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V DS0=0,DS1=0 Isink Isource 1.10mA -1.05mA 2.22mA -1.92mA 3.95mA -3.30mA DS0=0,DS1=1 1.8V MDDR IO DS0=1,DS1=0 Isink Isource Isink Isource 2.20mA -2.45mA 3.30mA -2.80mA 4.45mA -4.49mA 6.67mA -5.12mA 7.91mA -7.70mA 11.86mA -8.79mA DS0=1,DS1=1 Isink Isource 3.85mA -4.55mA 7.78mA -8.32mA 13.82mA -14.29mA NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD - Mesured point is different from measurement spec of 65nm IO Driver 2-7 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.5 INPUT/ OUTPUT DESCRIPTION 2.1.5.1 General Purpose Input/Output Block Diagram GPIO consists of two parts, namely, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part keep their values during sleep mode. Register File Mux control Pad control APB Bus APB Interface Off Part External Interrupt Control Interrupt Controller Async Interface Mux control Pad control Register File External Interrupt Control Alive Part Figure 2-1 GPIO Block Diagram Interrupt Controller & Wake -up controller 2-8 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.5.2 Pin Summary I/O Control Type A1 A2 A3 A4 A5 B1 B2 Function Description Control at power down mode is possible, power down mode is released by S/W (ENABLE_GPIO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W (ENABLE_UART_IO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W (ENABLE_MMC_IO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by H/W automatically Control at power down mode is possible, power down mode is released by H/W (ENABLE_CF_IO bit of OTHERS register at PMU) No Retention (Alive IO) No Retention (Analog IO) 2-9 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.5.3 Pin Mux Description Pin Name GPIO Func0 Func1 Func2 Func3 XuRXD[0] XuTXD[0] XuCTSn[0] XuRTSn[0] XuRXD[1] XuTXD[1] XuCTSn[1] XuRTSn[1] XuRXD[2] XuTXD[2] XuRXD[3] XuTXD[3] XspiCLK[0] XspiCSn[0] XspiMISO[0] XspiMOSI[0] XspiCLK[1] XspiCSn[1] XspiMISO[1] XspiMOSI[1] Xi2s1SCLK Xi2s1CDCLK Xi2s1LRCK Xi2s1SDI Xi2s1SDO Xpcm2SCLK Xpcm2EXTCLK Xpcm2FSYNC Xpcm2SIN Xpcm2SOUT XpwmTOUT[0] XpwmTOUT[1] XpwmTOUT[2] GPA0[0] UART_0_RXD GPA0[1] UART_0_TXD GPA0[2] UART_0_CTSn GPA0[3] UART_0_RTSn GPA0[4] UART_1_RXD GPA0[5] UART_1_TXD GPA0[6] UART_1_CTSn GPA0[7] UART_1_RTSn GPA1[0] UART_2_RXD UART_AUDIO_ RXD GPA1[1] UART_2_TXD UART_AUDIO_ TXD GPA1[2] UART_3_RXD UART_2_CTSn GPA1[3] UART_3_TXD UART_2_RTSn GPB[0] SPI_0_CLK GPB[1] SPI_0_nSS GPB[2] SPI_0_MISO GPB[3] SPI_0_MOSI GPB[4] SPI_1_CLK GPB[5] SPI_1_nSS GPB[6] SPI_1_MISO GPB[7] SPI_1_MOSI GPC0[0] I2S_1_SCLK PCM_1_SCLK AC97BITCLK GPC0[1] I2S_1_CDCLK PCM_1_EXTCLK AC97RESETn GPC0[2] I2S_1_LRCK PCM_1_FSYNC AC97SYNC GPC0[3] I2S_1_SDI PCM_1_SIN AC97SDI GPC0[4] I2S_1_SDO PCM_1_SOUT AC97SDO GPC1[0] PCM_2_SCLK SPDIF_0_OUT I2S_2_SCLK GPC1[1] PCM_2_EXTCLK SPDIF_EXTCLK I2S_2_CDCLK GPC1[2] PCM_2_FSYNC LCD_FRM I2S_2_LRCK GPC1[3] PCM_2_SIN I2S_2_SDI GPC1[4] PCM_2_SOUT I2S_2_SDO GPD0[0] TOUT_0 GPD0[1] TOUT_1 GPD0[2] TOUT_2 Default GPI GPI GPI GPI GPI GPI GPI GPI @Reset PUD I/O PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) Sleep State Pad Type A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G GPI PD I(L) A2 PBIDIRSE_G GPI PD I(L) A2 PBIDIRSE_G GPI PD I(L) A2 PBIDIRSE_G GPI PD I(L) A2 PBIDIRSE_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRF_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G GPI PD I(L) A1 PBIDIRSE_G 2-10 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Func1 Func2 Func3 XpwmTOUT[3] Xi2c0SDA Xi2c0SCL Xi2c1SDA Xi2c1SCL Xi2c2SDA Xi2c2SCL XciPCLK XciVSYNC XciHREF XciDATA[0] XciDATA[1] XciDATA[2] XciDATA[3] XciDATA[4] XciDATA[5] XciDATA[6] XciDATA[7] XciCLKenb XciFIELD XvHSYNC XvVSYNC XvVDEN XvVCLK XvVD[0] XvVD[1] XvVD[2] XvVD[3] XvVD[4] XvVD[5] XvVD[6] XvVD[7] XvVD[8] XvVD[9] XvVD[10] XvVD[11] GPD0[3] TOUT_3 GPD1[0] I2C0_SDA GPD1[1] I2C0_SCL GPD1[2] I2C1_SDA GPD1[3] I2C1_SCL GPD1[4] I2C2_SDA GPD1[5] I2C2_SCL GPE0[0] CAM_A_PCLK GPE0[1] CAM_A_VSYNC GPE0[2] CAM_A_HREF GPE0[3] CAM_A_DATA[0] GPE0[4] CAM_A_DATA[1] GPE0[5] CAM_A_DATA[2] GPE0[6] CAM_A_DATA[3] GPE0[7] CAM_A_DATA[4] GPE1[0] CAM_A_DATA[5] GPE1[1] CAM_A_DATA[6] GPE1[2] CAM_A_DATA[7] GPE1[3] CAM_A_CLKOUT GPE1[4] CAM_A_FIELD GPF0[0] LCD_HSYNC GPF0[1] LCD_VSYNC GPF0[2] LCD_VDEN GPF0[3] LCD_VCLK GPF0[4] LCD_VD[0] GPF0[5] LCD_VD[1] GPF0[6] LCD_VD[2] GPF0[7] LCD_VD[3] GPF1[0] LCD_VD[4] GPF1[1] LCD_VD[5] GPF1[2] LCD_VD[6] GPF1[3] LCD_VD[7] GPF1[4] LCD_VD[8] GPF1[5] LCD_VD[9] GPF1[6] LCD_VD[10] GPF1[7] LCD_VD[11] IEM_SCLK IEM_SPWI SYS_CS0 SYS_CS1 SYS_RS SYS_WE SYS_VD[0] SYS_VD[1] SYS_VD[2] SYS_VD[3] SYS_VD[4] SYS_VD[5] SYS_VD[6] SYS_VD[7] SYS_VD[8] SYS_VD[9] SYS_VD[10] SYS_VD[11] VEN_HSYNC VEN_VSYNC VEN_HREF V601_CLK VEN_DATA[0] VEN_DATA[1] VEN_DATA[2] VEN_DATA[3] VEN_DATA[4] VEN_DATA[5] VEN_DATA[6] VEN_DATA[7] V656_DATA[0] V656_DATA[1] V656_DATA[2] V656_DATA[3] Default GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI @Reset PUD I/O PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) Sleep State Pad Type A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G 2-11 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Func1 Func2 Func3 XvVD[12] XvVD[13] XvVD[14] XvVD[15] XvVD[16] XvVD[17] XvVD[18] XvVD[19] XvVD[20] XvVD[21] XvVD[22] XvVD[23] XvVSYNC_LDI XvSYS_OE Xmmc0CLK Xmmc0CMD Xmmc0CDn Xmmc0DATA[0] Xmmc0DATA[1] Xmmc0DATA[2] Xmmc0DATA[3] Xmmc1CLK Xmmc1CMD Xmmc1CDn Xmmc1DATA[0] Xmmc1DATA[1] Xmmc1DATA[2] Xmmc1DATA[3] Xmmc2CLK Xmmc2CMD Xmmc2CDn Xmmc2DATA[0] Xmmc2DATA[1] Xmmc2DATA[2] Xmmc2DATA[3] Xmmc3CLK GPF2[0] GPF2[1] GPF2[2] GPF2[3] GPF2[4] GPF2[5] GPF2[6] GPF2[7] GPF3[0] GPF3[1] GPF3[2] GPF3[3] GPF3[4] GPF3[5] GPG0[0] GPG0[1] GPG0[2] GPG0[3] GPG0[4] GPG0[5] GPG0[6] GPG1[0] GPG1[1] GPG1[2] GPG1[3] GPG1[4] GPG1[5] GPG1[6] GPG2[0] GPG2[1] GPG2[2] GPG2[3] GPG2[4] GPG2[5] GPG2[6] GPG3[0] LCD_VD[12] LCD_VD[13] LCD_VD[14] LCD_VD[15] LCD_VD[16] LCD_VD[17] LCD_VD[18] LCD_VD[19] LCD_VD[20] LCD_VD[21] LCD_VD[22] LCD_VD[23] SD_0_CLK SD_0_CMD SD_0_CDn SD_0_DATA[0] SD_0_DATA[1] SD_0_DATA[2] SD_0_DATA[3] SD_1_CLK SD_1_CMD SD_1_CDn SD_1_DATA[0] SD_1_DATA[1] SD_1_DATA[2] SD_1_DATA[3] SD_2_CLK SD_2_CMD SD_2_CDn SD_2_DATA[0] SD_2_DATA[1] SD_2_DATA[2] SD_2_DATA[3] SD_3_CLK SYS_VD[12] SYS_VD[13] SYS_VD[14] SYS_VD[15] SYS_VD[16] SYS_VD[17] SYS_VD[18] SYS_VD[19] SYS_VD[20] SYS_VD[21] SYS_VD[22] SYS_VD[23] VSYNC_LDI SYS_OE V656_DATA[4] V656_DATA[5] V656_DATA[6] V656_DATA[7] V656_CLK VEN_FIELD SD_0_DATA[4] SD_0_DATA[5] SD_0_DATA[6] SD_0_DATA[7] Default GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI @Reset PUD I/O PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) Sleep State Pad Type A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G 2-12 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Func1 Func2 Func3 Xmmc3CMD Xmmc3CDn Xmmc3DATA[0] Xmmc3DATA[1] Xmmc3DATA[2] Xmmc3DATA[3] XEINT[0] XEINT[1] XEINT[2] XEINT[3] XEINT[4] XEINT[5] XEINT[6] XEINT[7] XEINT[8] XEINT[9] XEINT[10] XEINT[11] XEINT[12] XEINT[13] XEINT[14] XEINT[15] XEINT[16] XEINT[17] XEINT[18] XEINT[19] XEINT[20] XEINT[21] XEINT[22] XEINT[23] XEINT[24] XEINT[25] XEINT[26] XEINT[27] XEINT[28] XEINT[29] GPG3[1] GPG3[2] GPG3[3] GPG3[4] GPG3[5] GPG3[6] GPH0[0] GPH0[1] GPH0[2] GPH0[3] GPH0[4] GPH0[5] GPH0[6] GPH0[7] GPH1[0] GPH1[1] GPH1[2] GPH1[3] GPH1[4] GPH1[5] GPH1[6] GPH1[7] GPH2[0] GPH2[1] GPH2[2] GPH2[3] GPH2[4] GPH2[5] GPH2[6] GPH2[7] GPH3[0] GPH3[1] GPH3[2] GPH3[3] GPH3[4] GPH3[5] SD_3_CMD SD_3_CDn SD_3_DATA[0] SD_3_DATA[1] SD_3_DATA[2] SD_3_DATA[3] SD_2_DATA[4] SD_2_DATA[5] SD_2_DATA[6] SD_2_DATA[7] KP_COL[0] KP_COL[1] KP_COL[2] KP_COL[3] KP_COL[4] KP_COL[5] KP_COL[6] KP_COL[7] KP_ROW[0] KP_ROW[1] KP_ROW[2] KP_ROW[3] KP_ROW[4] KP_ROW[5] HDMI_CEC HDMI_HPD Default GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI @Reset PUD I/O PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) Sleep State Pad Type A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G A3 PBIDIRF_G B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV B1 PBIDIR_ALV 2-13 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Func1 Func2 Func3 Default XEINT[30] XEINT[31] Xi2s0SCLK Xi2s0CDCLK Xi2s0LRCK Xi2s0SDI Xi2s0SDO[0] Xi2s0SDO[1] Xi2s0SDO[2] XmsmADDR[0] XmsmADDR[1] XmsmADDR[2] XmsmADDR[3] XmsmADDR[4] XmsmADDR[5] XmsmADDR[6] XmsmADDR[7] XmsmADDR[8] XmsmADDR[9] XmsmADDR[10] XmsmADDR[11] XmsmADDR[12] XmsmADDR[13] XmsmDATA[0] XmsmDATA[1] XmsmDATA[2] XmsmDATA[3] XmsmDATA[4] XmsmDATA[5] GPH3[6] GPH3[7] GPI[0] GPI[1] GPI[2] GPI[3] GPI[4] GPI[5] GPI[6] GPJ0[0] GPJ0[1] GPJ0[2] GPJ0[3] GPJ0[4] GPJ0[5] GPJ0[6] GPJ0[7] GPJ1[0] GPJ1[1] GPJ1[2] GPJ1[3] GPJ1[4] GPJ1[5] GPJ2[0] GPJ2[1] GPJ2[2] GPJ2[3] GPJ2[4] GPJ2[5] KP_ROW[6] KP_ROW[7] I2S_0_SCLK PCM_0_SCLK I2S_0_CDCLK PCM_0_EXTCLK I2S_0_LRCK PCM_0_FSYNC I2S_0_SDI PCM_0_SIN I2S_0_SDO[0] PCM_0_SOUT I2S_0_SDO[1] I2S_0_SDO[2] MSM_ADDR[0] CAM_B_DATA[0] MIPI_BYT CF_ADDR[0] E_CLK MSM_ADDR[1] CAM_B_DATA[1] MIPI_ESC CF_ADDR[1] _CLK MSM_ADDR[2] CAM_B_DATA[2] CF_ADDR[2] TS_CLK MSM_ADDR[3] CAM_B_DATA[3] CF_IORDY TS_SYNC MSM_ADDR[4] CAM_B_DATA[4] CF_INTRQ TS_VAL MSM_ADDR[5] CAM_B_DATA[5] CF_DMARQ TS_DATA TS_ERRO MSM_ADDR[6] CAM_B_DATA[6] CF_DRESETN R MSM_ADDR[7] CAM_B_DATA[7] CF_DMACKN MHL_D0 MSM_ADDR[8] SROM_ADDR_1 CAM_B_PCLK MHL_D1 6to22[0] MSM_ADDR[9] SROM_ADDR_1 CAM_B_VSYNC MHL_D2 6to22[1] MSM_ADDR[10] SROM_ADDR_1 CAM_B_HREF MHL_D3 6to22[2] MSM_ADDR[11] SROM_ADDR_1 CAM_B_FIELD MHL_D4 6to22[3] SROM_ADDR_1 MSM_ADDR[12] CAM_B_CLKOUT MHL_D5 6to22[4] MSM_ADDR[13] KP_COL[0] SROM_ADDR_1 MHL_D6 6to22[5] MSM_DATA[0] KP_COL[1] CF_DATA[0] MHL_D7 MSM_DATA[1] KP_COL[2] CF_DATA[1] MHL_D8 MSM_DATA[2] KP_COL[3] CF_DATA[2] MHL_D9 MSM_DATA[3] KP_COL[4] CF_DATA[3] MHL_D10 MSM_DATA[4] KP_COL[5] CF_DATA[4] MHL_D11 MSM_DATA[5] KP_COL[6] CF_DATA[5] MHL_D12 GPI GPI Func0 Func0 Func0 Func0 Func0 Func0 Func0 GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI @Reset PUD I/O PD I(L) PD I(L) PD O(L) PD O(L) PD O(L) PD I(L) PD O(L) PD O(L) PD O(L) Sleep State Pad Type B1 PBIDIR_ALV B1 PBIDIR_ALV A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G 2-14 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Func1 Func2 Func3 Default XmsmDATA[6] XmsmDATA[7] XmsmDATA[8] XmsmDATA[9] XmsmDATA[10] XmsmDATA[11] XmsmDATA[12] XmsmDATA[13] XmsmDATA[14] XmsmDATA[15] XmsmCSn GPJ2[6] GPJ2[7] GPJ3[0] GPJ3[1] GPJ3[2] GPJ3[3] GPJ3[4] GPJ3[5] GPJ3[6] GPJ3[7] GPJ4[0] MSM_DATA[6] MSM_DATA[7] MSM_DATA[8] MSM_DATA[9] MSM_DATA[10] MSM_DATA[11] MSM_DATA[12] MSM_DATA[13] MSM_DATA[14] MSM_DATA[15] MSM_CSn XmsmWEn GPJ4[1] MSM_WEn XmsmRn GPJ4[2] MSM_Rn XmsmIRQn GPJ4[3] MSM_IRQn XmsmADVN GPJ4[4] MSM_ADVN Xm0CSn[0] Xm0CSn[1] Xm0CSn[2] Xm0CSn[3] MP0_1[0] MP0_1[1] MP0_1[2] MP0_1[3] SROM_CSn[0] SROM_CSn[1] SROM_CSn[2] SROM_CSn[3] Xm0CSn[4] MP0_1[4] SROM_CSn[4] Xm0CSn[5] MP0_1[5] SROM_CSn[5] Xm0OEn MP0_1[6] EBI_OEn Xm0WEn MP0_1[7] EBI_WEn Xm0BEn[0] MP0_2[0] EBI_BEn[0] Xm0BEn[1] MP0_2[1] EBI_BEn[1] Xm0WAITn MP0_2[2] SROM_WAITn Xm0DATA_RDn MP0_2[3] EBI_DATA_RDn Xm0FCLE MP0_3[0] NF_CLE Xm0FALE MP0_3[1] NF_ALE KP_COL[7] KP_ROW[0] KP_ROW[1] KP_ROW[2] KP_ROW[3] KP_ROW[4] KP_ROW[5] KP_ROW[6] KP_ROW[7] KP_ROW[8] KP_ROW[9] KP_ROW[10] KP_ROW[11] KP_ROW[12] KP_ROW[13] CF_DATA[6] MHL_D13 CF_DATA[7] MHL_D14 CF_DATA[8] MHL_D15 CF_DATA[9] MHL_D16 CF_DATA[10] MHL_D17 CF_DATA[11] MHL_D18 CF_DATA[12] MHL_D19 CF_DATA[13] MHL_D20 CF_DATA[14] MHL_D21 CF_DATA[15] MHL_D22 CF_CSn[0] MHL_D23 MHL_HSY CF_CSn[1] NC CF_IORN MHL_IDC K CF_IOWN MHL_VSY NC SROM_ADDR_1 MHL_DE 6to22[6] NFCSn[0] NFCSn[1] NFCSn[2] NFCSn[3] ONANDX L_CSn[0] ONANDX L_CSn[1] ONANDX L_ADDRV ALID ONANDX L_SMCLK GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI Func0 Func0 Func1 Func1 Func3 Func3 Func0 Func0 Func0 Func0 Func0 Func0 Func3 Func3 @Reset PUD I/O PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) PD I(L) Sleep State Pad Type A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G PD I(L) A5 PBIDIRSE_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - O(H) A4 PBIDIRF_G - I A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G 2-15 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm0FWEn MP0_3[2] Xm0FREn MP0_3[3] Xm0FRnB[0] MP0_3[4] NF_FWEn NF_FREn NF_RnB[0] Xm0FRnB[1] MP0_3[5] NF_RnB[1] Xm0FRnB[2] Xm0FRnB[3] Xm0ADDR[0] Xm0ADDR[1] Xm0ADDR[2] Xm0ADDR[3] Xm0ADDR[4] Xm0ADDR[5] Xm0ADDR[6] Xm0ADDR[7] Xm0ADDR[8] Xm0ADDR[9] Xm0ADDR[10] Xm0ADDR[11] Xm0ADDR[12] Xm0ADDR[13] Xm0ADDR[14] Xm0ADDR[15] Xm0DATA[0] Xm0DATA[1] Xm0DATA[2] Xm0DATA[3] Xm0DATA[4] Xm0DATA[5] Xm0DATA[6] Xm0DATA[7] Xm0DATA[8] Xm0DATA[9] Xm0DATA[10] Xm0DATA[11] MP0_3[6] MP0_3[7] MP0_4[0] MP0_4[1] MP0_4[2] MP0_4[3] MP0_4[4] MP0_4[5] MP0_4[6] MP0_4[7] MP0_5[0] MP0_5[1] MP0_5[2] MP0_5[3] MP0_5[4] MP0_5[5] MP0_5[6] MP0_5[7] MP0_6[0] MP0_6[1] MP0_6[2] MP0_6[3] MP0_6[4] MP0_6[5] MP0_6[6] MP0_6[7] MP0_7[0] MP0_7[1] MP0_7[2] MP0_7[3] NF_RnB[2] NF_RnB[3] EBI_ADDR[0] EBI_ADDR[1] EBI_ADDR[2] EBI_ADDR[3] EBI_ADDR[4] EBI_ADDR[5] EBI_ADDR[6] EBI_ADDR[7] EBI_ADDR[8] EBI_ADDR[9] EBI_ADDR[10] EBI_ADDR[11] EBI_ADDR[12] EBI_ADDR[13] EBI_ADDR[14] EBI_ADDR[15] EBI_DATA[0] EBI_DATA[1] EBI_DATA[2] EBI_DATA[3] EBI_DATA[4] EBI_DATA[5] EBI_DATA[6] EBI_DATA[7] EBI_DATA[8] EBI_DATA[9] EBI_DATA[10] EBI_DATA[11] Func1 Func2 Func3 ONANDX L_RPn ONANDX L_INT[0] ONANDX L_INT[1] Default Func3 Func3 Func3 Func3 Func3 Func3 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O Sleep State Pad Type - O(H) A4 PBIDIRF_G - I A4 PBIDIRF_G - I A4 PBIDIRF_G - I A4 PBIDIRF_G - I A4 PBIDIRF_G - I A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G - O(L) A4 PBIDIRF_G 2-16 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm0DATA[12] Xm0DATA[13] Xm0DATA[14] Xm0DATA[15] Xm1ADDR[0] Xm1ADDR[1] Xm1ADDR[2] Xm1ADDR[3] Xm1ADDR[4] Xm1ADDR[5] Xm1ADDR[6] Xm1ADDR[7] Xm1ADDR[8] Xm1ADDR[9] Xm1ADDR[10] Xm1ADDR[11] Xm1ADDR[12] Xm1ADDR[13] Xm1ADDR[14] Xm1ADDR[15] Xm1DATA[0] Xm1DATA[1] Xm1DATA[2] Xm1DATA[3] Xm1DATA[4] Xm1DATA[5] Xm1DATA[6] Xm1DATA[7] Xm1DATA[8] Xm1DATA[9] Xm1DATA[10] Xm1DATA[11] Xm1DATA[12] Xm1DATA[13] Xm1DATA[14] Xm1DATA[15] MP0_7[4] MP0_7[5] MP0_7[6] MP0_7[7] MP1_0[0] MP1_0[1] MP1_0[2] MP1_0[3] MP1_0[4] MP1_0[5] MP1_0[6] MP1_0[7] MP1_1[0] MP1_1[1] MP1_1[2] MP1_1[3] MP1_1[4] MP1_1[5] MP1_1[6] MP1_1[7] MP1_2[0] MP1_2[1] MP1_2[2] MP1_2[3] MP1_2[4] MP1_2[5] MP1_2[6] MP1_2[7] MP1_3[0] MP1_3[1] MP1_3[2] MP1_3[3] MP1_3[4] MP1_3[5] MP1_3[6] MP1_3[7] EBI_DATA[12] EBI_DATA[13] EBI_DATA[14] EBI_DATA[15] LD0_ADDR[0] LD0_ADDR[1] LD0_ADDR[2] LD0_ADDR[3] LD0_ADDR[4] LD0_ADDR[5] LD0_ADDR[6] LD0_ADDR[7] LD0_ADDR[8] LD0_ADDR[9] LD0_ADDR[10] LD0_ADDR[11] LD0_ADDR[12] LD0_ADDR[13] LD0_ADDR[14] LD0_ADDR[15] LD0_DATA[0] LD0_DATA[1] LD0_DATA[2] LD0_DATA[3] LD0_DATA[4] LD0_DATA[5] LD0_DATA[6] LD0_DATA[7] LD0_DATA[8] LD0_DATA[9] LD0_DATA[10] LD0_DATA[11] LD0_DATA[12] LD0_DATA[13] LD0_DATA[14] LD0_DATA[15] Func1 Func2 Func3 Default Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - O(L) - I - I - I - I - I - I - I - I - I - I - I - I - I - I - I - I Sleep State Pad Type A4 PBIDIRF_G A4 PBIDIRF_G A4 PBIDIRF_G A4 PBIDIRF_G A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR A4 PBIDIR_MDDR 2-17 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm1DATA[16] Xm1DATA[17] Xm1DATA[18] Xm1DATA[19] Xm1DATA[20] Xm1DATA[21] Xm1DATA[22] Xm1DATA[23] Xm1DATA[24] Xm1DATA[25] Xm1DATA[26] Xm1DATA[27] Xm1DATA[28] Xm1DATA[29] Xm1DATA[30] Xm1DATA[31] Xm1DQS[0] Xm1DQS[1] Xm1DQS[2] Xm1DQS[3] Xm1DQSn[0] Xm1DQSn[1] Xm1DQSn[2] Xm1DQSn[3] Xm1DQM[0] Xm1DQM[1] Xm1DQM[2] Xm1DQM[3] Xm1CKE[0] Xm1CKE[1] Xm1SCLK Xm1nSCLK Xm1CSn[0] Xm1CSn[1] Xm1RASn Xm1CASn MP1_4[0] MP1_4[1] MP1_4[2] MP1_4[3] MP1_4[4] MP1_4[5] MP1_4[6] MP1_4[7] MP1_5[0] MP1_5[1] MP1_5[2] MP1_5[3] MP1_5[4] MP1_5[5] MP1_5[6] MP1_5[7] MP1_6[0] MP1_6[1] MP1_6[2] MP1_6[3] MP1_6[4] MP1_6[5] MP1_6[6] MP1_6[7] MP1_7[0] MP1_7[1] MP1_7[2] MP1_7[3] MP1_7[4] MP1_7[5] MP1_7[6] MP1_7[7] MP1_8[0] MP1_8[1] MP1_8[2] MP1_8[3] LD0_DATA[16] LD0_DATA[17] LD0_DATA[18] LD0_DATA[19] LD0_DATA[20] LD0_DATA[21] LD0_DATA[22] LD0_DATA[23] LD0_DATA[24] LD0_DATA[25] LD0_DATA[26] LD0_DATA[27] LD0_DATA[28] LD0_DATA[29] LD0_DATA[30] LD0_DATA[31] LD0_DQS[0] LD0_DQS[1] LD0_DQS[2] LD0_DQS[3] LD0_DQSn[0] LD0_DQSn[1] LD0_DQSn[2] LD0_DQSn[3] LD0_DQM[0] LD0_DQM[1] LD0_DQM[2] LD0_DQM[3] LD0_CKE[0] LD0_CKE[1] LD0_SCLK LD0_nSCLK LD0_CSn_0 LD0_CSn_1 LD0_RASn LD0_CASn Func1 Func2 Func3 Default Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O Sleep State Pad Type - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR 2-18 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm1WEn Xm1GateIn Xm1GateOut Xm2ADDR[0] Xm2ADDR[1] Xm2ADDR[2] Xm2ADDR[3] Xm2ADDR[4] Xm2ADDR[5] Xm2ADDR[6] Xm2ADDR[7] Xm2ADDR[8] Xm2ADDR[9] Xm2ADDR[10] Xm2ADDR[11] Xm2ADDR[12] Xm2ADDR[13] Xm2ADDR[14] Xm2ADDR[15] Xm2DATA[0] Xm2DATA[1] Xm2DATA[2] Xm2DATA[3] Xm2DATA[4] Xm2DATA[5] Xm2DATA[6] Xm2DATA[7] Xm2DATA[8] Xm2DATA[9] Xm2DATA[10] Xm2DATA[11] Xm2DATA[12] Xm2DATA[13] Xm2DATA[14] Xm2DATA[15] MP1_8[4] LD0_WEn MP1_8[5] LD0_IOGATE_IN LD0_IOGATE_O MP1_8[6] UT MP2_0[0] LD1_ADDR[0] MP2_0[1] LD1_ADDR[1] MP2_0[2] LD1_ADDR[2] MP2_0[3] LD1_ADDR[3] MP2_0[4] LD1_ADDR[4] MP2_0[5] LD1_ADDR[5] MP2_0[6] LD1_ADDR[6] MP2_0[7] LD1_ADDR[7] MP2_1[0] LD1_ADDR[8] MP2_1[1] LD1_ADDR[9] MP2_1[2] LD1_ADDR[10] MP2_1[3] LD1_ADDR[11] MP2_1[4] LD1_ADDR[12] MP2_1[5] LD1_ADDR[13] MP2_1[6] LD1_ADDR[14] MP2_1[7] LD1_ADDR[15] MP2_2[0] LD1_DATA[0] MP2_2[1] LD1_DATA[1] MP2_2[2] LD1_DATA[2] MP2_2[3] LD1_DATA[3] MP2_2[4] LD1_DATA[4] MP2_2[5] LD1_DATA[5] MP2_2[6] LD1_DATA[6] MP2_2[7] LD1_DATA[7] MP2_3[0] LD1_DATA[8] MP2_3[1] LD1_DATA[9] MP2_3[2] LD1_DATA[10] MP2_3[3] LD1_DATA[11] MP2_3[4] LD1_DATA[12] MP2_3[5] LD1_DATA[13] MP2_3[6] LD1_DATA[14] MP2_3[7] LD1_DATA[15] Func1 Func2 Func3 Default Func0 Func0 @Reset PUD I/O Sleep State Pad Type - O(H) A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR Func0 - O A4 PBIDIR_MDDR Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR 2-19 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm2DATA[16] Xm2DATA[17] Xm2DATA[18] Xm2DATA[19] Xm2DATA[20] Xm2DATA[21] Xm2DATA[22] Xm2DATA[23] Xm2DATA[24] Xm2DATA[25] Xm2DATA[26] Xm2DATA[27] Xm2DATA[28] Xm2DATA[29] Xm2DATA[30] Xm2DATA[31] Xm2DQS[0] Xm2DQS[1] Xm2DQS[2] Xm2DQS[3] Xm2DQSn[0] Xm2DQSn[1] Xm2DQSn[2] Xm2DQSn[3] Xm2DQM[0] Xm2DQM[1] Xm2DQM[2] Xm2DQM[3] Xm2CKE[0] Xm2CKE[1] Xm2SCLK Xm2nSCLK Xm2CSn[0] Xm2CSn[1] Xm2RASn Xm2CASn MP2_4[0] MP2_4[1] MP2_4[2] MP2_4[3] MP2_4[4] MP2_4[5] MP2_4[6] MP2_4[7] MP2_5[0] MP2_5[1] MP2_5[2] MP2_5[3] MP2_5[4] MP2_5[5] MP2_5[6] MP2_5[7] MP2_6[0] MP2_6[1] MP2_6[2] MP2_6[3] MP2_6[4] MP2_6[5] MP2_6[6] MP2_6[7] MP2_7[0] MP2_7[1] MP2_7[2] MP2_7[3] MP2_7[4] MP2_7[5] MP2_7[6] MP2_7[7] MP2_8[0] MP2_8[1] MP2_8[2] MP2_8[3] LD1_DATA[16] LD1_DATA[17] LD1_DATA[18] LD1_DATA[19] LD1_DATA[20] LD1_DATA[21] LD1_DATA[22] LD1_DATA[23] LD1_DATA[24] LD1_DATA[25] LD1_DATA[26] LD1_DATA[27] LD1_DATA[28] LD1_DATA[29] LD1_DATA[30] LD1_DATA[31] LD1_DQS[0] LD1_DQS[1] LD1_DQS[2] LD1_DQS[3] LD1_DQSn[0] LD1_DQSn[1] LD1_DQSn[2] LD1_DQSn[3] LD1_DQM[0] LD1_DQM[1] LD1_DQM[2] LD1_DQM[3] LD1_CKE[0] LD1_CKE[1] LD1_SCLK LD1_nSCLK LD1_CSn_0 LD1_CSn_1 LD1_RASn LD1_CASn Func1 Func2 Func3 Default Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O Sleep State Pad Type - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(L) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR - O(H) A4 PBIDIR_MDDR 2-20 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 Xm2WEn MP2_8[4] LD1_WEn Xm2GateIn MP2_8[5] LD1_IOGATE_IN Xm2GateOut LD1_IOGATE_O MP2_8[6] UT XjTRSTn ETC0[0] XjTRSTn XjTMS ETC0[1] XjTMS XjTCK ETC0[2] XjTCK XjTDI ETC0[3] XjTDI XjTDO ETC0[4] XjTDO XjDBGSEL ETC0[5] XjDBGSEL XOM[0] ETC1[0] XOM[0] XOM[1] ETC1[1] XOM[1] XOM[2] ETC1[2] XOM[2] XOM[3] ETC1[3] XOM[3] XOM[4] ETC1[4] XOM[4] XOM[5] ETC1[5] XOM[5] XDDR2SEL ETC1[6] XDDR2_SEL XPWRRGTON ETC1[7] XPWRRGTON XnRESET ETC2[0] XnRESET XCLKOUT ETC2[1] CLKOUT XnRSTOUT ETC2[2] XnRSTOUT XnWRESET ETC2[3] XnWRESET XRTCCLKO ETC2[4] RTC_CLKOUT XuotgDRVVBUS ETC2[5] XuotgDRVVBUS XuhostPWREN ETC2[6] XuhostPWREN XuhostOVERCU R ETC2[7] XuhostOVERCU R XrtcXTI ETC4[0] XrtcXTI XrtcXTO ETC4[1] XrtcXTO XXTI ETC4[2] XXTI XXTO ETC4[3] XXTO XusbXTI ETC4[4] XusbXTI XusbXTO ETC4[5] XusbXTO XadcAIN[0] ANALOG AIN[0] XadcAIN[1] ANALOG AIN[1] XadcAIN[2] ANALOG AIN[2] Func1 Func2 Func3 Default Func0 Func0 @Reset PUD I/O Sleep State Pad Type - O(H) A4 PBIDIR_MDDR - I A4 PBIDIR_MDDR Func0 - O A4 PBIDIR_MDDR Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 PD I(L) PU I(H) PD I(L) PU I(H) - O(L) - I - I - I - I - I - I - I - I - O(L) - I - O(L) - O(L) PU I(H) - O(L) - O(L) - O(L) A4 PBIDIRSE_G A4 PBIDIRSE_G A4 PBIDIRSE_G A4 PBIDIRSE_G A4 PBIDIRSE_G A4 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G A1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G B1 PBIDIRSE_G A1 PBIDIRSE_G A1 PBIDIRSE_G Func0 - I A1 PBIDIRSE_G Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 - I B1 POSC1A - O(L) B1 POSC1A - I B1 POSCP - O(L) B1 POSCP - I B1 POSCPB - O(L) B1 POSCPB - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS 2-21 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 XadcAIN[3] XadcAIN[4] XadcAIN[5] XadcAIN[6] XadcAIN[7] XadcAIN[8] XadcAIN[9] XdacOUT XdacIREF XdacVREF XdacCOMP XhdmiTX0P XhdmiTX0N XhdmiTX1P XhdmiTX1N XhdmiTX2P XhdmiTX2N XhdmiTXCP XhdmiTXCN XhdmiREXT XhdmiXTI XhdmiXTO XmipiMDP0 XmipiMDP1 XmipiMDP2 XmipiMDP3 XmipiMDN0 XmipiMDN1 XmipiMDN2 XmipiMDN3 XmipiSDP0 XmipiSDP1 XmipiSDP2 XmipiSDP3 XmipiSDN0 XmipiSDN1 ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG AIN[3] AIN[4] AIN[5] AIN[6] AIN[7] AIN[8] AIN[9] XdacOUT XdacIREF XdacVREF XdacCOMP HDMI_TX0P HDMI_TX0N HDMI_TX1P HDMI_TX1N HDMI_TX2P HDMI_TX2N HDMI_TXCP HDMI_TXCN HDMI_REXT HDMI_XI HDMI_XO MIPI_MDP_0 MIPI_MDP_1 MIPI_MDP_2 MIPI_MDP_3 MIPI_MDN_0 MIPI_MDN_1 MIPI_MDN_2 MIPI_MDN_3 MIPI_SDP_0 MIPI_SDP_1 MIPI_SDP_2 MIPI_SDP_3 MIPI_SDN_0 MIPI_SDN_1 Func1 Func2 Func3 Default Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O Sleep State Pad Type - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - O(H) B2 PANALOGSW - I B2 PANALOGSW - I B2 PANALOGSW - O(H) B2 PANALOGSW - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - O(H) B2 PANALOGS - I B2 PANALOGS - I B2 POSCP - O(L) B2 POSCP - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS - I B2 PANALOGS 2-22 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Pin Name GPIO Func0 XmipiSDN2 ANALOG MIPI_SDN_2 XmipiSDN3 ANALOG MIPI_SDN_3 XmipiMDPCLK ANALOG MIPI_CLK_TX_P XmipiMDNCLK ANALOG MIPI_CLK_TX_N XmipiSDPCLK ANALOG MIPI_CLK_RX_P XmipiSDNCLK ANALOG MIPI_CLK_RX_N XmipiVREG_0P4 ANALOG V MIPI_Reg_cap XuotgDP ANALOG XuotgDP XuotgREXT ANALOG XuotgREXT XuotgDM ANALOG XuotgDM XuotgANTEST XuotgANALOGTE ANALOG ST XefFSOURCE_0 ANALOG efrom_fsource_0 XefFSOURCE_1 ANALOG efrom_fsource_1 XefFSOURCE_2 ANALOG efrom_fsource_2 XabbNBBG ANALOG XabbNBBG XabbPBBG ANALOG XabbPBBG XuhostDP ANALOG XuhostDP XuhostREXT ANALOG XuhostREXT XuhostDM ANALOG XuhostDM XuhostANALOGT XuhostANTEST ANALOG EST XuotgID ANALOG XuotgID XuotgVBUS ANALOG XuotgVBUS Func1 Func2 Func3 Default Func0 Func0 Func0 Func0 Func0 Func0 @Reset PUD I/O - I - I - I - I - I - I Sleep State Pad Type B2 PANALOGS B2 PANALOGS B2 PANALOGS B2 PANALOGS B2 PANALOGS B2 PANALOGS Func0 - I B2 PANALOGS PVHTBR_33_5 Func0 - I B2 T Func0 - I B2 PANALOGS PVHTBR_33_5 Func0 - I B2 T Func0 - O(L) B2 PANALOGS Func0 Func0 Func0 Func0 Func0 Func0 Func0 Func0 - I B2 PV_EFUSE - I B2 PV_EFUSE - I B2 PV_EFUSE - I B2 PVDRAM - I B2 PVDRAM PVHTBR_33_5 - I B2 T - O(L) B2 PANALOGS PVHTBR_33_5 - O(L) B2 T Func0 - O(L) B2 PANALOGS Func0 - I B2 PANALOGS PVHTBR_33_5 Func0 - I B2 T 2-23 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.1.5.4 Pad Type Description Cell Name PBIDIRSE_G PBIDIRF_G PBIDIR_MDDR PVHTBR_33_5T PANALOGS PANALOGSW POSCP POSCPB POSC1A PV_EFUSE Function Description Wide-range I/O supply, programmable bi-direction I/O with cmos / schmitt trigger input, input disable, pull-up/down and 4-step strength output Wide-range I/O supply, programmable bi-direction Fast I/O with cmos / schmitt trigger input, input disable, pull-up/down and 4-step strength output Wide-range I/O supply, programmable bi-direction I/O with cmos / schmitt trigger input, input disable, pull-up/down and 4-step strength output Wide-range I/O supply, 5V tolerant bi-direction path-through pad with 3 different paths which have no resistor, 50ohm or 200ohm resistor Analog input (Note: This cell does not support fail-safe operation) Analog input (Note: This cell does not support fail-safe operation) Pin port wide type Wide-range I/O supply, programmable and retention oscillator for 32kHz~50MHz frequency Wide-range I/O supply, programmable and retention oscillator for 32kHz~50MHz frequency with 3.3V clock output Wide-range I/O supply, 32kHz oscillator for RTC interface. Wide-range I/O supply, bi-direction path-through pad with 2 different paths which have no resistor, 10ohm for EFUSE memory. 2-24 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2 REGISTER DESCRIPTION 2.2.1 REGISTER MAP Each Port Group has 2 types of control registers. One works in normal mode, and the other works in power down mode (STOP, DEEP-STOP, SLEEP mode) Normal registers (For example, GPA0CON, GPA0DAT, GPA0PUD, and GPA0DRV) are the former, and power down registers (For example, GPA0CONPDN, and GPA0PUDPDN) are the latter. If, S5PV210 enter the power down mode, all configurations and Pull-down controls are selected by power down registers Register GPA0CON GPA0DAT GPA0PUD GPA0DRV GPA0CONPDN GPA0PUDPDN GPA1CON GPA1DAT GPA1PUD GPA1DRV GPA1CONPDN GPA1PUDPDN GPBCON GPBDAT GPBPUD GPBDRV GPBCONPDN GPBPUDPDN GPC0CON GPC0DAT Address R/W Description 0xE020_0000 R/W Port Group GPA0 Configuration Register 0xE020_0004 R/W Port Group GPA0 Data Register 0xE020_0008 R/W Port Group GPA0 Pull-up/down Register 0xE020_000C R/W Port Group GPA0 Drive Strength Control Register 0xE020_0010 R/W Port Group GPA0 Power Down Mode Configuration Register 0xE020_0014 R/W Port Group GPA0 Power Down Mode Pullup/down Register 0xE020_0020 R/W Port Group GPA1 Configuration Register 0xE020_0024 R/W Port Group GPA1 Data Register 0xE020_0028 R/W Port Group GPA1 Pull-up/down Register 0xE020_002C R/W Port Group GPA1 Drive Strength Control Register 0xE020_0030 R/W Port Group GPA1 Power Down Mode Configuration Register 0xE020_0034 R/W Port Group GPA1 Power Down Mode Pullup/down Register 0xE020_0040 R/W Port Group GPB Configuration Register 0xE020_0044 R/W Port Group GPB Data Register 0xE020_0048 R/W Port Group GPB Pull-up/down Register 0xE020_004C R/W Port Group GPB Drive Strength Control Register 0xE020_0050 R/W Port Group GPB Power Down Mode Configuration Register 0xE020_0054 R/W Port Group GPB Power Down Mode Pullup/down Register 0xE020_0060 R/W Port Group GPC0 Configuration Register 0xE020_0064 R/W Port Group GPC0 Data Register Reset Value 0x00000000 0x00 0x5555 0x0000 0x00 0x00 0x00000000 0x00 0x0055 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 0x00 0x00000000 0x00 2-25 S5PV210_UM Register GPC0PUD GPC0DRV GPC0CONPDN GPC0PUDPDN GPC1CON GPC1DAT GPC1PUD GPC1DRV GPC1CONPDN GPC1PUDPDN GPD0CON GPD0DAT GPD0PUD GPD0DRV GPD0CONPDN GPD0PUDPDN GPD1CON GPD1DAT GPD1PUD GPD1DRV GPD1CONPDN GPD1PUDPDN GPE0CON GPE0DAT GPE0PUD GPE0DRV 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_0068 R/W Port Group GPC0 Pull-up/down Register 0xE020_006C R/W Port Group GPC0 Drive Strength Control Register 0xE020_0070 R/W Port Group GPC0 Power Down Mode Configuration Register 0xE020_0074 R/W Port Group GPC0 Power Down Mode Pullup/down Register 0xE020_0080 R/W Port Group GPC1 Configuration Register 0xE020_0084 R/W Port Group GPC1 Data Register 0xE020_0088 R/W Port Group GPC1 Pull-up/down Register 0xE020_008C R/W Port Group GPC1 Drive Strength Control Register 0xE020_0090 R/W Port Group GPC1 Power Down Mode Configuration Register 0xE020_0094 R/W Port Group GPC1 Power Down Mode Pullup/down Register 0xE020_00A0 R/W Port Group GPD0 Configuration Register 0xE020_00A4 R/W Port Group GPD0 Data Register 0xE020_00A8 R/W Port Group GPD0 Pull-up/down Register 0xE020_00AC R/W Port Group GPD0 Drive Strength Control Register 0xE020_00B0 R/W Port Group GPD0 Power Down Mode Configuration Register 0xE020_00B4 R/W Port Group GPD0 Power Down Mode Pullup/down Register 0xE020_00C0 R/W Port Group GPD1 Configuration Register 0xE020_00C4 R/W Port Group GPD1 Data Register 0xE020_00C8 R/W Port Group GPD1 Pull-up/down Register 0xE020_00CC R/W Port Group GPD1 Drive Strength Control Register 0xE020_00D0 R/W Port Group GPD1 Power Down Mode Configuration Register 0xE020_00D4 R/W Port Group GPD1 Power Down Mode Pullup/down Register 0xE020_00E0 R/W Port Group GPE0 Configuration Register 0xE020_00E4 R/W Port Group GPE0 Data Register 0xE020_00E8 R/W Port Group GPE0 Pull-up/down Register 0xE020_00EC R/W Port Group GPE0 Drive Strength Control Register Reset Value 0x0155 0x0000 0x00 0x00 0x00000000 0x00 0x0155 0x0000 0x00 0x00 0x00000000 0x00 0x0055 0x0000 0x00 0x00 0x00000000 0x00 0x0555 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 2-26 S5PV210_UM Register GPE0CONPDN GPE0PUDPDN GPE1CON GPE1DAT GPE1PUD GPE1DRV GPE1CONPDN GPE1PUDPDN GPF0CON GPF0DAT GPF0PUD GPF0DRV GPF0CONPDN GPF0PUDPDN GPF1CON GPF1DAT GPF1PUD GPF1DRV GPF1CONPDN GPF1PUDPDN GPF2CON GPF2DAT GPF2PUD GPF2DRV GPF2CONPDN GPF2PUDPDN 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_00F0 R/W Port Group GPE0 Power Down Mode Configuration Register 0xE020_00F4 R/W Port Group GPE0 Power Down Mode Pullup/down Register 0xE020_0100 R/W Port Group GPE1 Configuration Register 0xE020_0104 R/W Port Group GPE1 Data Register 0xE020_0108 R/W Port Group GPE1 Pull-up/down Register 0xE020_010C R/W Port Group GPE1 Drive Strength Control Register 0xE020_0110 R/W Port Group GPE1 Power Down Mode Configuration Register 0xE020_0114 R/W Port Group GPE1 Power Down Mode Pullup/down Register 0xE020_0120 R/W Port Group GPF0 Configuration Register 0xE020_0124 R/W Port Group GPF0 Data Register 0xE020_0128 R/W Port Group GPF0 Pull-up/down Register 0xE020_012C R/W Port Group GPF0 Drive Strength Control Register 0xE020_0130 R/W Port Group GPF0 Power Down Mode Configuration Register 0xE020_0134 R/W Port Group GPF0 Power Down Mode Pullup/down Register 0xE020_0140 R/W Port Group GPF1 Configuration Register 0xE020_0144 R/W Port Group GPF1 Data Register 0xE020_0148 R/W Port Group GPF1 Pull-up/down Register 0xE020_014C R/W Port Group GPF1 Drive Strength Control Register 0xE020_0150 R/W Port Group GPF1 Power Down Mode Configuration Register 0xE020_0154 R/W Port Group GPF1 Power Down Mode Pullup/down Register 0xE020_0160 R/W Port Group GPF2 Configuration Register 0xE020_0164 R/W Port Group GPF2 Data Register 0xE020_0168 R/W Port Group GPF2 Pull-up/down Register 0xE020_016C R/W Port Group GPF2 Drive Strength Control Register 0xE020_0170 R/W Port Group GPF2 Power Down Mode Configuration Register 0xE020_0174 R/W Port Group GPF2 Power Down Mode Pullup/down Register Reset Value 0x00 0x00 0x00000000 0x00 0x0155 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 0x00 2-27 S5PV210_UM Register GPF3CON GPF3DAT GPF3PUD GPF3DRV GPF3CONPDN GPF3PUDPDN GPG0CON GPG0DAT GPG0PUD GPG0DRV GPG0CONPDN GPG0PUDPDN GPG1CON GPG1DAT GPG1PUD GPG1DRV GPG1CONPDN GPG1PUDPDN GPG2CON GPG2DAT GPG2PUD GPG2DRV GPG2CONPDN GPG2PUDPDN GPG3CON GPG3DAT GPG3PUD 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_0180 R/W Port Group GPF3 Configuration Register 0xE020_0184 R/W Port Group GPF3 Data Register 0xE020_0188 R/W Port Group GPF3 Pull-up/down Register 0xE020_018C R/W Port Group GPF3 Drive Strength Control Register 0xE020_0190 R/W Port Group GPF3 Power Down Mode Configuration Register 0xE020_0194 R/W Port Group GPF3 Power Down Mode Pullup/down Register 0xE020_01A0 R/W Port Group GPG0 Configuration Register 0xE020_01A4 R/W Port Group GPG0 Data Register 0xE020_01A8 R/W Port Group GPG0 Pull-up/down Register 0xE020_01AC R/W Port Group GPG0 Drive Strength Control Register 0xE020_01B0 R/W Port Group GPG0 Power Down Mode Configuration Register 0xE020_01B4 R/W Port Group GPG0 Power Down Mode Pullup/down Register 0xE020_01C0 R/W Port Group GPG1 Configuration Register 0xE020_01C4 R/W Port Group GPG1 Data Register 0xE020_01C8 R/W Port Group GPG1 Pull-up/down Register 0xE020_01CC R/W Port Group GPG1 Drive Strength Control Register 0xE020_01D0 R/W Port Group GPG1 Power Down Mode Configuration Register 0xE020_01D4 R/W Port Group GPG1 Power Down Mode Pullup/down Register 0xE020_01E0 R/W Port Group GPG2 Configuration Register 0xE020_01E4 R/W Port Group GPG2 Data Register 0xE020_01E8 R/W Port Group GPG2 Pull-up/down Register 0xE020_01EC R/W Port Group GPG2 Drive Strength Control Register 0xE020_01F0 R/W Port Group GPG2 Power Down Mode Configuration Register 0xE020_01F4 R/W Port Group GPG2 Power Down Mode Pullup/ down Register 0xE020_0200 R/W Port Group GPG3 Configuration Register 0xE020_0204 R/W Port Group GPG3 Data Register 0xE020_0208 R/W Port Group GPG3 Pull-up/down Register Reset Value 0x00000000 0x00 0x0555 0x0000 0x00 0x00 0x00000000 0x00 0x1555 0x2AAA 0x00 0x00 0x00000000 0x00 0x1555 0x0000 0x00 0x00 0x00000000 0x00 0x1555 0x0000 0x00 0x00 0x00000000 0x00 0x1555 2-28 S5PV210_UM Register GPG3DRV GPG3CONPDN GPG3PUDPDN GPICON GPIDAT GPIPUD GPIDRV GPICONPDN GPIPUDPDN GPJ0CON GPJ0DAT GPJ0PUD GPJ0DRV GPJ0CONPDN GPJ0PUDPDN GPJ1CON GPJ1DAT GPJ1PUD GPJ1DRV GPJ1CONPDN GPJ1PUDPDN GPJ2CON GPJ2DAT GPJ2PUD GPJ2DRV GPJ2CONPDN 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_020C R/W Port Group GPG3 Drive Strength Control Register 0xE020_0210 R/W Port Group GPG3 Power Down Mode Configuration Register 0xE020_0214 R/W Port Group GPG3 Power Down Mode Pullup/ down Register 0xE020_0220 R/W Port Group GPI Configuration Register 0xE020_0224 R/W Reserved GPI is only used for I2S0 and PCM2 0xE020_0228 R/W Port Group GPI Pull-up/ down Register 0xE020_022C R/W Port Group GPI Drive Strength Control Register 0xE020_0230 R/W Reserved (Controlled by PAD_PDN_CTRL register at AUDIO_SS) 0xE020_0234 R/W Reserved (Controlled by GPIPUD register) 0xE020_0240 R/W Port Group GPJ0 Configuration Register 0xE020_0244 R/W Port Group GPJ0 Data Register 0xE020_0248 R/W Port Group GPJ0 Pull-up/ down Register 0xE020_024C R/W Port Group GPJ0 Drive Strength Control Register 0xE020_0250 R/W Port Group GPJ0 Power Down Mode Configuration Register 0xE020_0254 R/W Port Group GPJ0 Power Down Mode Pullup/ down Register 0xE020_0260 R/W Port Group GPJ1 Configuration Register 0xE020_0264 R/W Port Group GPJ1 Data Register 0xE020_0268 R/W Port Group GPJ1 Pull-up/ down Register 0xE020_026C R/W Port Group GPJ1 Drive Strength Control Register 0xE020_0270 R/W Port Group GPJ1 Power Down Mode Configuration Register 0xE020_0274 R/W Port Group GPJ1 Power Down Mode Pullup/down Register 0xE020_0280 R/W Port Group GPJ2 Configuration Register 0xE020_0284 R/W Port Group GPJ2 Data Register 0xE020_0288 R/W Port Group GPJ2 Pull-up/ down Register 0xE020_028C R/W Port Group GPJ2 Drive Strength Control Register 0xE020_0290 R/W Port Group GPJ2 Power Down Mode Configuration Register Reset Value 0x0000 0x00 0x00 0x02222222 0x00 0x1555 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 0x00 0x00000000 0x00 0x0555 0x0000 0x00 0x00 0x00000000 0x00 0x5555 0x0000 0x00 2-29 S5PV210_UM Register GPJ2PUDPDN GPJ3CON GPJ3DAT GPJ3PUD GPJ3DRV GPJ3CONPDN GPJ3PUDPDN GPJ4CON GPJ4DAT GPJ4PUD GPJ4DRV GPJ4CONPDN GPJ4PUDPDN MP0_1CON MP0_1DAT MP0_1PUD MP0_1DRV MP0_1CONPDN MP0_1PUDPDN MP0_2CON MP0_2DAT MP0_2PUD MP0_2DRV MP0_2CONPDN MP0_2PUDPDN MP0_3CON MP0_3DAT 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description Reset Value 0xE020_0294 R/W Port Group GPJ2 Power Down Mode Pullup/down Register 0x00 0xE020_02A0 R/W Port Group GPJ3 Configuration Register 0x00000000 0xE020_02A4 R/W Port Group GPJ3 Data Register 0x00 0xE020_02A8 R/W Port Group GPJ3 Pull-up/ down Register 0x5555 0xE020_02AC R/W Port Group GPJ3 Drive Strength Control Register 0x0000 0xE020_02B0 R/W Port Group GPJ3 Power Down Mode Configuration Register 0x00 0xE020_02B4 R/W Port Group GPJ3 Power Down Mode Pullup/down Register 0x00 0xE020_02C0 R/W Port Group GPJ4 Configuration Register 0x00000000 0xE020_02C4 R/W Port Group GPJ4 Data Register 0x00 0xE020_02C8 R/W Port Group GPJ4 Pull-up/ down Register 0x0155 0xE020_02CC R/W Port Group GPJ4 Drive Strength Control Register 0x0000 0xE020_02D0 R/W Port Group GPJ4 Power Down Mode Configuration Register 0x00 0xE020_02D4 R/W Port Group GPJ4 Power Down Mode Pullup/down Register 0x00 0xE020_02E0 R/W Port Group MP0_1 Configuration Register 0x22553322 0xE020_02E4 R/W Port Group MP0_1 Data Register 0x00 0xE020_02E8 R/W Port Group MP0_1 Pull-up/down Register 0x0000 0xE020_02EC R/W Port Group MP0_1 Drive Strength Control Register 0xAAAA 0xE020_02F0 R/W Port Group MP0_1 Power Down Mode Configuration Register 0x00 0xE020_02F4 R/W Port Group MP0_1 Power Down Mode Pullup/ down Register 0x00 0xE020_0300 R/W Port Group MP0_2 Configuration Register 0x00002222 0xE020_0304 R/W Port Group MP0_2 Data Register 0x00 0xE020_0308 R/W Port Group MP0_2 Pull-up/ down Register 0x0000 0xE020_030C R/W Port Group MP0_2 Drive Strength Control Register 0x00AA 0xE020_0310 R/W Port Group MP0_2 Power Down Mode Configuration Register 0x00 0xE020_0314 R/W Port Group MP0_2 Power Down Mode Pullup/ down Register 0x00 0xE020_0320 R/W Port Group MP0_3 Configuration Register 0x22552555 0xE020_0324 R/W Port Group MP0_3 Data Register 0x00 2-30 S5PV210_UM Register MP0_3PUD MP0_3DRV MP0_3CONPDN MP0_3PUDPDN MP0_4CON MP0_4DAT MP0_4PUD MP0_4DRV MP0_4CONPDN MP0_4PUDPDN MP0_5CON MP0_5DAT MP0_5PUD MP0_5DRV MP0_5CONPDN MP0_5PUDPDN MP0_6CON MP0_6DAT MP0_6PUD MP0_6DRV MP0_6CONPDN MP0_6PUDPDN MP0_7CON MP0_7DAT MP0_7PUD MP0_7DRV 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description Reset Value 0xE020_0328 R/W Port Group MP0_3 Pull-up/down Register 0x0000 0xE020_032C R/W Port Group MP0_3 Drive Strength Control Register 0xAAAA 0xE020_0330 R/W Port Group MP0_3 Power Down Mode Configuration Register 0x00 0xE020_0334 R/W Port Group MP0_3 Power Down Mode Pullup/ down Register 0x00 0xE020_0340 R/W Port Group MP0_4 Configuration Register 0x22222222 0xE020_0344 R/W Port Group MP0_4 Data Register 0x00 0xE020_0348 R/W Port Group MP0_4 Pull-up/ down Register 0x0000 0xE020_034C R/W Port Group MP0_4 Drive Strength Control Register 0xAAAA 0xE020_0350 R/W Port Group MP0_4 Power Down Mode Configuration Register 0x00 0xE020_0354 R/W Port Group MP0_4 Power Down Mode Pullup/ down Register 0x00 0xE020_0360 R/W Port Group MP0_5 Configuration Register 0x22222222 0xE020_0364 R/W Port Group MP0_5 Data Register 0x00 0xE020_0368 R/W Port Group MP0_5 Pull-up/ down Register 0x0000 0xE020_036C R/W Port Group MP0_5 Drive Strength Control Register 0xAAAA 0xE020_0370 R/W Port Group MP0_5 Power Down Mode Configuration Register 0x00 0xE020_0374 R/W Port Group MP0_5 Power Down Mode Pullup/ down Register 0x00 0xE020_0380 R/W Port Group MP0_6 Configuration Register 0x22222222 0xE020_0384 R/W Port Group MP0_6 Data Register 0x00 0xE020_0388 R/W Port Group MP0_6 Pull-up/ down Register 0x0000 0xE020_038C R/W Port Group MP0_6 Drive Strength Control Register 0xAAAA 0xE020_0390 R/W Port Group MP0_6 Power Down Mode Configuration Register 0x00 0xE020_0394 R/W Port Group MP0_6 Power Down Mode Pullup/ down Register 0x00 0xE020_03A0 R/W Port Group MP0_7 Configuration Register 0x22222222 0xE020_03A4 R/W Port Group MP0_7 Data Register 0x00 0xE020_03A8 R/W Port Group MP0_7 Pull-up/ down Register 0x0000 0xE020_03AC R/W Port Group MP0_7 Drive Strength Control Register 0xAAAA 2-31 S5PV210_UM Register MP0_7CONPDN MP0_7PUDPDN MP1_0CON MP1_0DAT MP1_0PUD MP1_0DRV MP1_0CONPDN MP1_0PUDPDN MP1_1CON MP1_1DAT MP1_1PUD MP1_1DRV MP1_1CONPDN MP1_1PUDPDN MP1_2CON MP1_2DAT MP1_2PUD MP1_2DRV MP1_2CONPDN MP1_2PUDPDN MP1_3CON MP1_3DAT MP1_3PUD MP1_3DRV MP1_3CONPDN MP1_3PUDPDN MP1_4CON MP1_4DAT MP1_4PUD MP1_4DRV MP1_4CONPDN 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description Reset Value 0xE020_03B0 R/W Port Group MP0_7 Power Down Mode Configuration Register 0x00 0xE020_03B4 R/W Port Group MP0_7 Power Down Mode Pullup/down Register 0x00 0xE020_03C0 R/W Reserved (Do not use this register) 0x22222222 0xE020_03C4 R/W Reserved (Do not use this register) 0x00 0xE020_03C8 R/W Reserved (Do not use this register) 0x0000 0xE020_03CC R/W Port Group MP1_0 Drive Strength Control Register 0xAAAA 0xE020_03D0 R/W Reserved (Do not use this register) 0x00 0xE020_03D4 R/W Reserved (Do not use this register) 0x00 0xE020_03E0 R/W Reserved (Do not use this register) 0x22222222 0xE020_03E4 R/W Reserved (Do not use this register) 0x00 0xE020_03E8 R/W Reserved (Do not use this register) 0x0000 0xE020_03EC R/W Port Group MP1_1 Drive Strength Control Register 0xAAAA 0xE020_03F0 R/W Reserved (Do not use this register) 0x00 0xE020_03F4 R/W Reserved (Do not use this register) 0x00 0xE020_0400 R/W Reserved (Do not use this register) 0x22222222 0xE020_0404 R/W Reserved (Do not use this register) 0x00 0xE020_0408 R/W Reserved (Do not use this register) 0x0000 0xE020_040C R/W Port Group MP1_2 Drive Strength Control Register 0xAAAA 0xE020_0410 R/W Reserved (Do not use this register) 0x00 0xE020_0414 R/W Reserved (Do not use this register) 0x00 0xE020_0420 R/W Reserved (Do not use this register) 0x22222222 0xE020_0424 R/W Reserved (Do not use this register) 0x00 0xE020_0428 R/W Reserved (Do not use this register) 0x0000 0xE020_042C R/W Port Group MP1_3 Drive Strength Control Register 0xAAAA 0xE020_0430 R/W Reserved (Do not use this register) 0x00 0xE020_0434 R/W Reserved (Do not use this register) 0x00 0xE020_0440 R/W Reserved (Do not use this register) 0x22222222 0xE020_0444 R/W Reserved (Do not use this register) 0x00 0xE020_0448 R/W Reserved (Do not use this register) 0x0000 0xE020_044C R/W Port Group MP1_4 Drive Strength Control Register 0xAAAA 0xE020_0450 R/W Reserved (Do not use this register) 0x00 2-32 S5PV210_UM Register MP1_4PUDPDN MP1_5CON MP1_5DAT MP1_5PUD MP1_5DRV MP1_5CONPDN MP1_5PUDPDN MP1_6CON MP1_6DAT MP1_6PUD MP1_6DRV MP1_6CONPDN MP1_6PUDPDN MP1_7CON MP1_7DAT MP1_7PUD MP1_7DRV MP1_7CONPDN MP1_7PUDPDN MP1_8CON MP1_8DAT MP1_8PUD MP1_8DRV MP1_8CONPDN MP1_8PUDPDN MP2_0CON MP2_0DAT MP2_0PUD MP2_0DRV MP2_0CONPDN MP2_0PUDPDN MP2_1CON MP2_1DAT 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_0454 R/W Reserved (Do not use this register) 0xE020_0460 R/W Reserved (Do not use this register) 0xE020_0464 R/W Reserved (Do not use this register) 0xE020_0468 R/W Reserved (Do not use this register) 0xE020_046C R/W Port Group MP1_5 Drive Strength Control Register 0xE020_0470 R/W Reserved (Do not use this register) 0xE020_0474 R/W Reserved (Do not use this register) 0xE020_0480 R/W Reserved (Do not use this register) 0xE020_0484 R/W Reserved (Do not use this register) 0xE020_0488 R/W Reserved (Do not use this register) 0xE020_048C R/W Port Group MP1_6 Drive Strength Control Register 0xE020_0490 R/W Reserved (Do not use this register) 0xE020_0494 R/W Reserved (Do not use this register) 0xE020_04A0 R/W Reserved (Do not use this register) 0xE020_04A4 R/W Reserved (Do not use this register) 0xE020_04A8 R/W Reserved (Do not use this register) 0xE020_04AC R/W Port Group MP1_7 Drive Strength Control Register 0xE020_04B0 R/W Reserved (Do not use this register) 0xE020_04B4 R/W Reserved (Do not use this register) 0xE020_04C0 R/W Reserved (Do not use this register) 0xE020_04C4 R/W Reserved (Do not use this register) 0xE020_04C8 R/W Reserved (Do not use this register) 0xE020_04CC R/W Port Group MP1_8 Drive Strength Control Register 0xE020_04D0 R/W Reserved (Do not use this register) 0xE020_04D4 R/W Reserved (Do not use this register) 0xE020_04E0 R/W Reserved (Do not use this register) 0xE020_04E4 R/W Reserved (Do not use this register) 0xE020_04E8 R/W Reserved (Do not use this register) 0xE020_04EC R/W Port Group MP2_0 Drive Strength Control Register 0xE020_04F0 R/W Reserved (Do not use this register) 0xE020_04F4 R/W Reserved (Do not use this register) 0xE020_0500 R/W Reserved (Do not use this register) 0xE020_0504 R/W Reserved (Do not use this register) Reset Value 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x02222222 0x00 0x0000 0x2AAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 2-33 S5PV210_UM Register MP2_1PUD MP2_1DRV MP2_1CONPDN MP2_1PUDPDN MP2_2CON MP2_2DAT MP2_2PUD MP2_2DRV MP2_2CONPDN MP2_2PUDPDN MP2_3CON MP2_3DAT MP2_3PUD MP2_3DRV MP2_3CONPDN MP2_3PUDPDN MP2_4CON MP2_4DAT MP2_4PUD MP2_4DRV MP2_4CONPDN MP2_4PUDPDN MP2_5CON MP2_5DAT MP2_5PUD MP2_5DRV MP2_5CONPDN MP2_5PUDPDN MP2_6CON MP2_6DAT MP2_6PUD MP2_6DRV 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_0508 R/W Reserved (Do not use this register) 0xE020_050C R/W Port Group MP2_1 Drive Strength Control Register 0xE020_0510 R/W Reserved (Do not use this register) 0xE020_0514 R/W Reserved (Do not use this register) 0xE020_0520 R/W Reserved (Do not use this register) 0xE020_0524 R/W Reserved (Do not use this register) 0xE020_0528 R/W Reserved (Do not use this register) 0xE020_052C R/W Port Group MP2_2 Drive Strength Control Register 0xE020_0530 R/W Reserved (Do not use this register) 0xE020_0534 R/W Reserved (Do not use this register) 0xE020_0540 R/W Reserved (Do not use this register) 0xE020_0544 R/W Reserved (Do not use this register) 0xE020_0548 R/W Reserved (Do not use this register) 0xE020_054C R/W Port Group MP2_3 Drive Strength Control Register 0xE020_0550 R/W Reserved (Do not use this register) 0xE020_0554 R/W Reserved (Do not use this register) 0xE020_0560 R/W Reserved (Do not use this register) 0xE020_0564 R/W Reserved (Do not use this register) 0xE020_0568 R/W Reserved (Do not use this register) 0xE020_056C R/W Port Group MP2_4 Drive Strength Control Register 0xE020_0570 R/W Reserved (Do not use this register) 0xE020_0574 R/W Reserved (Do not use this register) 0xE020_0580 R/W Reserved (Do not use this register) 0xE020_0584 R/W Reserved (Do not use this register) 0xE020_0588 R/W Reserved (Do not use this register) 0xE020_058C R/W Port Group MP2_5 Drive Strength Control Register 0xE020_0590 R/W Reserved (Do not use this register) 0xE020_0594 R/W Reserved (Do not use this register) 0xE020_05A0 R/W Reserved (Do not use this register) 0xE020_05A4 R/W Reserved (Do not use this register) 0xE020_05A8 R/W Reserved (Do not use this register) 0xE020_05AC R/W Port Group MP2_6 Drive Strength Control Register Reset Value 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 2-34 S5PV210_UM Register MP2_6CONPDN MP2_6PUDPDN MP2_7CON MP2_7DAT MP2_7PUD MP2_7DRV MP2_7CONPDN MP2_7PUDPDN MP2_8CON MP2_8DAT MP2_8PUD MP2_8DRV MP2_8CONPDN MP2_8PUDPDN ETC0PUD ETC0DRV ETC1PUD ETC1DRV ETC2PUD ETC2DRV GPA0_INT_CON GPA1_INT_CON GPB_INT_CON GPC0_INT_CON GPC1_INT_CON GPD0_INT_CON GPD1_INT_CON 2 1BGENERAL PURPOSE INPUT/ OUTPUT Address R/W Description 0xE020_05B0 R/W Reserved (Do not use this register) 0xE020_05B4 R/W Reserved (Do not use this register) 0xE020_05C0 R/W Reserved (Do not use this register) 0xE020_05C4 R/W Reserved (Do not use this register) 0xE020_05C8 R/W Reserved (Do not use this register) 0xE020_05CC R/W Port Group MP2_7 Drive Strength Control Register 0xE020_05D0 R/W Reserved (Do not use this register) 0xE020_05D4 R/W Reserved (Do not use this register) 0xE020_05E0 R/W Reserved (Do not use this register) 0xE020_05E4 R/W Reserved (Do not use this register) 0xE020_05E8 R/W Reserved (Do not use this register) 0xE020_05EC R/W Port Group MP2_8 Drive Strength Control Register 0xE020_05F0 R/W Reserved (Do not use this register) 0xE020_05F4 R/W Reserved (Do not use this register) 0xE020_0608 R/W Port Group ETC0 Pull-up/ down Register 0xE020_060C R/W Port Group ETC0 Drive Strength Control Register 0xE020_0628 R/W Port Group ETC1 Pull-up/ down Register 0xE020_062C R/W Port Group ETC1 Drive Strength Control Register 0xE020_0648 R/W Port Group ETC2 Pull-up/down Register 0xE020_064C R/W Port Group ETC2 Drive Strength Control Register 0xE020_0700 R/W GPIO Interrupt GPA0_INT Configuration Register 0xE020_0704 R/W GPIO Interrupt GPA1_INT Configuration Register 0xE020_0708 R/W GPIO Interrupt GPB_INT Configuration Register 0xE020_070C R/W GPIO Interrupt GPC0_INT Configuration Register 0xE020_0710 R/W GPIO Interrupt GPC1_INT Configuration Register 0xE020_0714 R/W GPIO Interrupt GPD0_INT Configuration Register 0xE020_0718 R/W GPIO Interrupt GPD1_INT Configuration Register Reset Value 0x00 0x00 0x22222222 0x00 0x0000 0xAAAA 0x00 0x00 0x02222222 0x00 0x0000 0x2AAA 0x00 0x00 0x0000 0x0000 0x0000 0x0000 0x0000 0x0202 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-35 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPE0_INT_CON GPE1_INT_CON GPF0_INT_CON GPF1_INT_CON GPF2_INT_CON GPF3_INT_CON GPG0_INT_CON GPG1_INT_CON GPG2_INT_CON GPG3_INT_CON GPJ0_INT_CON GPJ1_INT_CON GPJ2_INT_CON GPJ3_INT_CON GPJ4_INT_CON GPA0_INT_FLTCON0 GPA0_INT_FLTCON1 GPA1_INT_FLTCON0 GPA1_INT_FLTCON1 GPB_INT_FLTCON0 GPB_INT_FLTCON1 Address R/W Description 0xE020_071C R/W GPIO Interrupt GPE0_INT Configuration Register 0xE020_0720 R/W GPIO Interrupt GPE1_INT Configuration Register 0xE020_0724 R/W GPIO Interrupt GPF0_INT Configuration Register 0xE020_0728 R/W GPIO Interrupt GPF1_INT Configuration Register 0xE020_072C R/W GPIO Interrupt GPF2_INT Configuration Register 0xE020_0730 R/W GPIO Interrupt GPF3_INT Configuration Register 0xE020_0734 R/W GPIO Interrupt GPG0_INT Configuration Register 0xE020_0738 R/W GPIO Interrupt GPG1_INT Configuration Register 0xE020_073C R/W GPIO Interrupt GPG2_INT Configuration Register 0xE020_0740 R/W GPIO Interrupt GPG3_INT Configuration Register 0xE020_0744 R/W GPIO Interrupt GPJ0_INT Configuration Register 0xE020_0748 R/W GPIO Interrupt GPJ1_INT Configuration Register 0xE020_074C R/W GPIO Interrupt GPJ2_INT Configuration Register 0xE020_0750 R/W GPIO Interrupt GPJ3_INT Configuration Register 0xE020_0754 R/W GPIO Interrupt GPJ4_INT Configuration Register 0xE020_0800 R/W GPIO Interrupt GPA0_INT Filter Configuration Register 0 0xE020_0804 R/W GPIO Interrupt GPA0_INT Filter Configuration Register 1 0xE020_0808 R/W GPIO Interrupt GPA1_INT Filter Configuration Register 0 0xE020_080C R/W GPIO Interrupt GPA1_INT Filter Configuration Register 1 0xE020_0810 R/W GPIO Interrupt GPB_INT Filter Configuration Register 0 0xE020_0814 R/W GPIO Interrupt GPB_INT Filter Configuration Register 1 Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-36 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPC0_INT_FLTCON0 GPC0_INT_FLTCON1 GPC1_INT_FLTCON0 GPC1_INT_FLTCON1 GPD0_INT_FLTCON0 GPD0_INT_FLTCON1 GPD1_INT_FLTCON0 GPD1_INT_FLTCON1 GPE0_INT_FLTCON0 GPE0_INT_FLTCON1 GPE1_INT_FLTCON0 GPE1_INT_FLTCON1 GPF0_INT_FLTCON0 GPF0_INT_FLTCON1 GPF1_INT_FLTCON0 GPF1_INT_FLTCON1 GPF2_INT_FLTCON0 GPF2_INT_FLTCON1 GPF3_INT_FLTCON0 GPF3_INT_FLTCON1 GPG0_INT_FLTCON0 Address R/W Description 0xE020_0818 R/W GPIO Interrupt GPC0_INT Filter Configuration Register 0 0xE020_081C R/W GPIO Interrupt GPC0_INT Filter Configuration Register 1 0xE020_0820 R/W GPIO Interrupt GPC1_INT Filter Configuration Register 0 0xE020_0824 R/W GPIO Interrupt GPC1_INT Filter Configuration Register 1 0xE020_0828 R/W GPIO Interrupt GPD0_INT Filter Configuration Register 0 0xE020_082C R/W GPIO Interrupt GPD0_INT Filter Configuration Register 1 0xE020_0830 R/W GPIO Interrupt GPD1_INT Filter Configuration Register 0 0xE020_0834 R/W GPIO Interrupt GPD1_INT Filter Configuration Register 1 0xE020_0838 R/W GPIO Interrupt GPE0_INT Filter Configuration Register 0 0xE020_083C R/W GPIO Interrupt GPE0_INT Filter Configuration Register 1 0xE020_0840 R/W GPIO Interrupt GPE1_INT Filter Configuration Register 0 0xE020_0844 R/W GPIO Interrupt GPE1_INT Filter Configuration Register 1 0xE020_0848 R/W GPIO Interrupt GPF0_INT Filter Configuration Register 0 0xE020_084C R/W GPIO Interrupt GPF0_INT Filter Configuration Register 1 0xE020_0850 R/W GPIO Interrupt GPF1_INT Filter Configuration Register 0 0xE020_0854 R/W GPIO Interrupt GPF1_INT Filter Configuration Register 1 0xE020_0858 R/W GPIO Interrupt GPF2_INT Filter Configuration Register 0 0xE020_085C R/W GPIO Interrupt GPF2_INT Filter Configuration Register 1 0xE020_0860 R/W GPIO Interrupt GPF3_INT Filter Configuration Register 0 0xE020_0864 R/W GPIO Interrupt GPF3_INT Filter Configuration Register 1 0xE020_0868 R/W GPIO Interrupt GPG0_INT Filter Configuration Register 0 Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-37 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPG0_INT_FLTCON1 GPG1_INT_FLTCON0 GPG1_INT_FLTCON1 GPG2_INT_FLTCON0 GPG2_INT_FLTCON1 GPG3_INT_FLTCON0 GPG3_INT_FLTCON1 GPJ0_INT_FLTCON0 GPJ0_INT_FLTCON1 GPJ1_INT_FLTCON0 GPJ1_INT_FLTCON1 GPJ2_INT_FLTCON0 GPJ2_INT_FLTCON1 GPJ3_INT_FLTCON0 GPJ3_INT_FLTCON1 GPJ4_INT_FLTCON0 GPJ4_INT_FLTCON1 GPA0_INT_MASK GPA1_INT_MASK GPB_INT_MASK GPC0_INT_MASK GPC1_INT_MASK GPD0_INT_MASK GPD1_INT_MASK Address R/W Description 0xE020_086C R/W GPIO Interrupt GPG0_INT Filter Configuration Register 1 0xE020_0870 R/W GPIO Interrupt GPG1_INT Filter Configuration Register 0 0xE020_0874 R/W GPIO Interrupt GPG1_INT Filter Configuration Register 1 0xE020_0878 R/W GPIO Interrupt GPG2_INT Filter Configuration Register 0 0xE020_087C R/W GPIO Interrupt GPG2_INT Filter Configuration Register 1 0xE020_0880 R/W GPIO Interrupt GPG3_INT Filter Configuration Register 0 0xE020_0884 R/W GPIO Interrupt GPG3_INT Filter Configuration Register 1 0xE020_0888 R/W GPIO Interrupt GPJ0_INT Filter Configuration Register 0 0xE020_088C R/W GPIO Interrupt GPJ0_INT Filter Configuration Register 1 0xE020_0890 R/W GPIO Interrupt GPJ1_INT Filter Configuration Register 0 0xE020_0894 R/W GPIO Interrupt GPJ1_INT Filter Configuration Register 1 0xE020_0898 R/W GPIO Interrupt GPJ2_INT Filter Configuration Register 0 0xE020_089C R/W GPIO Interrupt GPJ2_INT Filter Configuration Register 1 0xE020_08A0 R/W GPIO Interrupt GPJ3_INT Filter Configuration Register 0 0xE020_08A4 R/W GPIO Interrupt GPJ3_INT Filter Configuration Register 1 0xE020_08A8 R/W GPIO Interrupt GPJ4_INT Filter Configuration Register 0 0xE020_08AC R/W GPIO Interrupt GPJ4_INT Filter Configuration Register 1 0xE020_0900 R/W GPIO Interrupt GPA0_INT Mask Register 0xE020_0904 R/W GPIO Interrupt GPA1_INT Mask Register 0xE020_0908 R/W GPIO Interrupt GPB_INT Mask Register 0xE020_090C R/W GPIO Interrupt GPC0_INT Mask Register 0xE020_0910 R/W GPIO Interrupt GPC1_INT Mask Register 0xE020_0914 R/W GPIO Interrupt GPD0_INT Mask Register 0xE020_0918 R/W GPIO Interrupt GPD1_INT Mask Register Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x000000FF 0x0000000F 0x000000FF 0x0000001F 0x0000001F 0x0000000F 0x0000003F 2-38 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPE0_INT_MASK GPE1_INT_MASK GPF0_INT_MASK GPF1_INT_MASK GPF2_INT_MASK GPF3_INT_MASK GPG0_INT_MASK GPG1_INT_MASK GPG2_INT_MASK GPG3_INT_MASK GPJ0_INT_MASK GPJ1_INT_MASK GPJ2_INT_MASK GPJ3_INT_MASK GPJ4_INT_MASK GPA0_INT_PEND GPA1_INT_PEND GPB_INT_PEND GPC0_INT_PEND GPC1_INT_PEND GPD0_INT_PEND GPD1_INT_PEND GPE0_INT_PEND GPE1_INT_PEND GPF0_INT_PEND GPF1_INT_PEND GPF2_INT_PEND GPF3_INT_PEND GPG0_INT_PEND GPG1_INT_PEND GPG2_INT_PEND Address R/W Description Reset Value 0xE020_091C R/W GPIO Interrupt GPE0_INT Mask Register 0x000000FF 0xE020_0920 R/W GPIO Interrupt GPE1_INT Mask Register 0x0000001F 0xE020_0924 R/W GPIO Interrupt GPF0_INT Mask Register 0x000000FF 0xE020_0928 R/W GPIO Interrupt GPF1_INT Mask Register 0x000000FF 0xE020_092C R/W GPIO Interrupt GPF2_INT Mask Register 0x000000FF 0xE020_0930 R/W GPIO Interrupt GPF3_INT Mask Register 0x0000003F 0xE020_0934 R/W GPIO Interrupt GPG0_INT Mask Register 0x0000007F 0xE020_0938 R/W GPIO Interrupt GPG1_INT Mask Register 0x0000007F 0xE020_093C R/W GPIO Interrupt GPG2_INT Mask Register 0x0000007F 0xE020_0940 R/W GPIO Interrupt GPG3_INT Mask Register 0x0000007F 0xE020_0944 R/W GPIO Interrupt GPJ0_INT Mask Register 0x000000FF 0xE020_0948 R/W GPIO Interrupt GPJ1_INT Mask Register 0x0000003F 0xE020_094C R/W GPIO Interrupt GPJ2_INT Mask Register 0x000000FF 0xE020_0950 R/W GPIO Interrupt GPJ3_INT Mask Register 0x000000FF 0xE020_0954 R/W GPIO Interrupt GPJ4_INT Mask Register 0x0000001F 0xE020_0A00 R/W GPIO Interrupt GPA0_INT Pending Register 0x0 0xE020_0A04 R/W GPIO Interrupt GPA1_INT Pending Register 0x0 0xE020_0A08 R/W GPIO Interrupt GPB_INT Pending Register 0x0 0xE020_0A0C R/W GPIO Interrupt GPC0_INT Pending 0x0 Register 0xE020_0A10 R/W GPIO Interrupt GPC1_INT Pending 0x0 Register 0xE020_0A14 R/W GPIO Interrupt GPD0_INT Pending 0x0 Register 0xE020_0A18 R/W GPIO Interrupt GPD1_INT Pending 0x0 Register 0xE020_0A1C R/W GPIO Interrupt GPE0_INT Pending Register 0x0 0xE020_0A20 R/W GPIO Interrupt GPE1_INT Pending Register 0x0 0xE020_0A24 R/W GPIO Interrupt GPF0_INT Pending Register 0x0 0xE020_0A28 R/W GPIO Interrupt GPF1_INT Pending Register 0x0 0xE020_0A2C R/W GPIO Interrupt GPF2_INT Pending Register 0x0 0xE020_0A30 R/W GPIO Interrupt GPF3_INT Pending Register 0x0 0xE020_0A34 R/W GPIO Interrupt GPG0_INT Pending 0x0 Register 0xE020_0A38 R/W GPIO Interrupt GPG1_INT Pending 0x0 Register 0xE020_0A3C R/W GPIO Interrupt GPG2_INT Pending 0x0 Register 2-39 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register Address R/W Description Reset Value GPG3_INT_PEND 0xE020_0A40 R/W GPIO Interrupt GPG3_INT Pending 0x0 Register GPJ0_INT_PEND 0xE020_0A44 R/W GPIO Interrupt GPJ0_INT Pending Register 0x0 GPJ1_INT_PEND 0xE020_0A48 R/W GPIO Interrupt GPJ1_INT Pending Register 0x0 GPJ2_INT_PEND 0xE020_0A4C R/W GPIO Interrupt GPJ2_INT Pending Register 0x0 GPJ3_INT_PEND 0xE020_0A50 R/W GPIO Interrupt GPJ3_INT Pending Register 0x0 GPJ4_INT_PEND 0xE020_0A54 R/W GPIO Interrupt GPJ4_INT Pending Register 0x0 GPIO_INT_GRPPRI 0xE020_0B00 R/W GPIO Interrupt Group Priority Control 0x0 Register GPIO_INT_PRIORITY 0xE020_0B04 R/W GPIO Interrupt Priority Control Register 0x00 GPIO_INT_SERVICE 0xE020_0B08 R Current Service Register 0x00 GPIO_INT_SERVICE_ 0xE020_0B0C R Current Service Pending Register PEND 0x00 GPIO_INT_GRPFIXPRI 0xE020_0B10 R/W GPIO Interrupt Group Fixed Priority Control Register 0x00 GPA0_INT_FIXPRI 0xE020_0B14 R/W GPIO Interrupt 1 Fixed Priority Control Register 0x00 GPA1_INT_FIXPRI 0xE020_0B18 R/W GPIO Interrupt 2 Fixed Priority Control Register 0x00 GPB_INT_FIXPRI 0xE020_0B1C R/W GPIO Interrupt 3 Fixed Priority Control Register 0x00 GPC0_INT_FIXPRI 0xE020_0B20 R/W GPIO Interrupt 4 Fixed Priority Control Register 0x00 GPC1_INT_FIXPRI 0xE020_0B24 R/W GPIO Interrupt 5 Fixed Priority Control Register 0x00 GPD0_INT_FIXPRI 0xE020_0B28 R/W GPIO Interrupt 6 Fixed Priority Control Register 0x00 GPD1_INT_FIXPRI 0xE020_0B2C R/W GPIO Interrupt 7 Fixed Priority Control Register 0x00 GPE0_INT_FIXPRI 0xE020_0B30 R/W GPIO Interrupt 8 Fixed Priority Control Register 0x00 GPE1_INT_FIXPRI 0xE020_0B34 R/W GPIO Interrupt 9 Fixed Priority Control Register 0x00 GPF0_INT_FIXPRI 0xE020_0B38 R/W GPIO Interrupt 10 Fixed Priority Control Register 0x00 GPF1_INT_FIXPRI 0xE020_0B3C R/W GPIO Interrupt 11 Fixed Priority Control Register 0x00 GPF2_INT_FIXPRI 0xE020_0B40 R/W GPIO Interrupt 12 Fixed Priority Control Register 0x00 GPF3_INT_FIXPRI 0xE020_0B44 R/W GPIO Interrupt 13 Fixed Priority Control Register 0x00 2-40 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPG0_INT_FIXPRI GPG1_INT_FIXPRI GPG2_INT_FIXPRI GPG3_INT_FIXPRI GPJ0_INT_FIXPRI GPJ1_INT_FIXPRI GPJ2_INT_FIXPRI GPJ3_INT_FIXPRI GPJ4_INT_FIXPRI GPH0CON GPH0DAT GPH0PUD GPH0DRV GPH1CON GPH1DAT GPH1PUD GPH1DRV GPH2CON GPH2DAT GPH2PUD GPH2DRV GPH3CON GPH3DAT GPH3PUD GPH3DRV EXT_INT_0_CON Address R/W Description Reset Value 0xE020_0B48 R/W GPIO Interrupt 14 Fixed Priority Control Register 0x00 0xE020_0B4C R/W GPIO Interrupt 15 Fixed Priority Control Register 0x00 0xE020_0B50 R/W GPIO Interrupt 16 Fixed Priority Control Register 0x00 0xE020_0B54 R/W GPIO Interrupt 17 Fixed Priority Control Register 0x00 0xE020_0B58 R/W GPIO Interrupt 18 Fixed Priority Control Register 0x00 0xE020_0B5C R/W GPIO Interrupt 19 Fixed Priority Control Register 0x00 0xE020_0B60 R/W GPIO Interrupt 20 Fixed Priority Control Register 0x00 0xE020_0B64 R/W GPIO Interrupt 21 Fixed Priority Control Register 0x00 0xE020_0B68 R/W GPIO Interrupt 22 Fixed Priority Control Register 0x00 0xE020_0C00 R/W Port Group GPH0 Configuration Register 0x00000000 0xE020_0C04 R/W Port Group GPH0 Data Register 0x00 0xE020_0C08 R/W Port Group GPH0 Pull-up/down Register 0x5555 0xE020_0C0C R/W Port Group GPH0 Drive Strength Control Register 0x0000 0xE020_0C20 R/W Port Group GPH1 Configuration Register 0x00000000 0xE020_0C24 R/W Port Group GPH1 Data Register 0x00 0xE020_0C28 R/W Port Group GPH1 Pull-up/ down Register 0x5555 0xE020_0C2C R/W Port Group GPH1 Drive Strength Control Register 0x0000 0xE020_0C40 R/W Port Group GPH2 Configuration Register 0x00000000 0xE020_0C44 R/W Port Group GPH2 Data Register 0x00 0xE020_0C48 R/W Port Group GPH2 Pull-up/ down Register 0x5555 0xE020_0C4C R/W Port Group GPH2 Drive Strength Control Register 0x0000 0xE020_0C60 R/W Port Group GPH3 Configuration Register 0x00000000 0xE020_0C64 R/W Port Group GPH3 Data Register 0x00 0xE020_0C68 R/W Port Group GPH3 Pull-up/ down Register 0x5555 0xE020_0C6C R/W Port Group GPH3 Drive Strength Control Register 0x0000 0xE020_0E00 R/W External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x0 Configuration Register 2-41 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register Address R/W Description Reset Value EXT_INT_1_CON 0xE020_0E04 R/W External Interrupt EXT_INT[8] ~ 0x0 EXT_INT[15] Configuration Register EXT_INT_2_CON 0xE020_0E08 R/W External Interrupt EXT_INT[16] ~ 0x0 EXT_INT[23] Configuration Register EXT_INT_3_CON 0xE020_0E0C R/W External Interrupt EXT_INT[24] ~ 0x0 EXT_INT[31] Configuration Register EXT_INT_0_FLTCON0 0xE020_0E80 R/W External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x80808080 Filter Configuration Register 0 EXT_INT_0_FLTCON1 0xE020_0E84 R/W External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x80808080 Filter Configuration Register 1 EXT_INT_1_FLTCON0 0xE020_0E88 R/W External Interrupt EXT_INT[8] ~ 0x80808080 EXT_INT[15] Filter Configuration Register 0 EXT_INT_1_FLTCON1 0xE020_0E8C R/W External Interrupt EXT_INT[8] ~ 0x80808080 EXT_INT[15] Filter Configuration Register 1 EXT_INT_2_FLTCON0 0xE020_0E90 R/W External Interrupt EXT_INT[16] ~ 0x80808080 EXT_INT[23] Filter Configuration Register 0 EXT_INT_2_FLTCON1 0xE020_0E94 R/W External Interrupt EXT_INT[16] ~ 0x80808080 EXT_INT[23] Filter Configuration Register 1 EXT_INT_3_FLTCON0 0xE020_0E98 R/W External Interrupt EXT_INT[24] ~ 0x80808080 EXT_INT[31] Filter Configuration Register 0 EXT_INT_3_FLTCON1 0xE020_0E9C R/W External Interrupt EXT_INT[24] ~ 0x80808080 EXT_INT[31] Filter Configuration Register 1 EXT_INT_0_MASK 0xE020_0F00 R/W External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x000000FF Mask Register EXT_INT_1_MASK 0xE020_0F04 R/W External Interrupt EXT_INT[8] ~ EXT_INT[15] Mask Register 0x000000FF EXT_INT_2_MASK 0xE020_0F08 R/W External Interrupt EXT_INT[16] ~ EXT_INT[23] Mask Register 0x000000FF EXT_INT_3_MASK 0xE020_0F0C R/W External Interrupt EXT_INT[24] ~ EXT_INT[31] Mask Register 0x000000FF EXT_INT_0_PEND 0xE020_0F40 R/W External Interrupt EXT_INT[0] ~ EXT_INT[7] 0x0 Pending Register EXT_INT_1_PEND 0xE020_0F44 R/W External Interrupt EXT_INT[8] ~ 0x0 EXT_INT[15] Pending Register EXT_INT_2_PEND 0xE020_0F48 R/W External Interrupt EXT_INT[16] ~ 0x0 EXT_INT[23] Pending Register EXT_INT_3_PEND 0xE020_0F4C R/W External Interrupt EXT_INT[24] ~ 0x0 EXT_INT[31] Pending Register PDNEN 0xE020_0F80 R/W Power down mode Pad Configure Register 0 2-42 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.2 PORT GROUP GPA0 CONTROL REGISTER There are six control registers, namely, GPA0CON, GPA0DAT, GPA0PUD, GPA0DRV, GPA0CONPDN and GPA0PUDPDN in the Port Group GPA0 Control Registers. 2.2.2.1 Port Group GPA0 Control Register (GPA0CON, R/W, Address = 0xE020_0000) GPA0CON GPA0CON[7] GPA0CON[6] GPA0CON[5] GPA0CON[4] GPA0CON[3] GPA0CON[2] GPA0CON[1] GPA0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = UART_1_RTSn 0011 ~ 1110 = Reserved 1111 = GPA0_INT[7] 0000 = Input 0001 = Output 0010 = UART_1_CTSn 0011 ~ 1110 = Reserved 1111 = GPA0_INT[6] 0000 = Input 0001 = Output 0010 = UART_1_TXD 0011 ~ 1110 = Reserved 1111 = GPA0_INT[5] 0000 = Input 0001 = Output 0010 = UART_1_RXD 0011 ~ 1110 = Reserved 1111 = GPA0_INT[4] 0000 = Input 0001 = Output 0010 = UART_0_RTSn 0011 ~ 1110 = Reserved 1111 = GPA0_INT[3] 0000 = Input 0001 = Output 0010 = UART_0_CTSn 0011 ~ 1110 = Reserved 1111 = GPA0_INT[2] 0000 = Input 0001 = Output 0010 = UART_0_TXD 0011 ~ 1110 = Reserved 1111 = GPA0_INT[1] 0000 = Input 0001 = Output 0010 = UART_0_RXD 0011 ~ 1110 = Reserved 1111 = GPA0_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 0000 2-43 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.2.2 Port Group GPA0 Control Register (GPA0DAT, R/W, Address = 0xE020_0004) GPA0DAT GPA0DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.2.3 Port Group GPA0 Control Register (GPA0PUD, R/W, Address = 0xE020_0008) GPA0PUD GPA0PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.2.4 Port Group GPA0 Control Register (GPA0DRV, R/W, Address = 0xE020_000C) GPA0DRV GPA0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.2.5 Port Group GPA0 Control Register (GPA0CONPDN, R/W, Address = 0xE020_0010) GPA0CONPDN GPA0[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.2.6 Port Group GPA0 Control Register (GPA0PUDPDN, R/W, Address = 0xE020_0014) GPA0PUDPDN GPA0[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-44 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.3 PORT GROUP GPA1 CONTROL REGISTER There are six control registers, namely, GPA1CON, GPA1DAT, GPA1PUD, GPA1DRV, GPA1CONPDN and GPA1PUDPDN in the Port Group GPA1 Control Registers. 2.2.3.1 Port Group GPA1 Control Register (GPA1CON, R/W, Address = 0xE020_0020) GPA1CON GPA1CON[3] GPA1CON[2] GPA1CON[1] GPA1CON[0] Bit [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = UART_3_TXD 0011 = UART_2_RTSn 0100 ~ 1110 = Reserved 1111 = GPA1_INT[3] 0000 = Input 0001 = Output 0010 = UART_3_RXD 0011 = UART_2_CTSn 0100 ~ 1110 = Reserved 1111 = GPA1_INT[2] 0000 = Input 0001 = Output 0010 = UART_2_TXD 0011 = Reserved 0100 = UART_AUDIO_TXD 0101 ~ 1110 = Reserved 1111 = GPA1_INT[1] 0000 = Input 0001 = Output 0010 = UART_2_RXD 0011 = Reserved 0100 = UART_AUDIO_RXD 0101 ~ 1110 = Reserved 1111 = GPA1_INT[0] Initial State 0000 0000 0000 0000 2-45 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.3.2 Port Group GPA1 Control Register (GPA1DAT, R/W, Address = 0xE020_0024) GPA1DAT GPA1DAT[3:0] Bit Description [3:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.3.3 Port Group GPA1 Control Register (GPA1PUD, R/W, Address = 0xE020_0028) GPA1PUD GPA1PUD[n] Bit Description [2n+1:2n] n=0~3 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0055 2.2.3.4 Port Group GPA1 Control Register (GPA1DRV, R/W, Address = 0xE020_002C) GPA1DRV GPA1DRV[n] Bit [2n+1:2n] n=0~3 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.3.5 Port Group GPA1 Control Register (GPA1CONPDN, R/W, Address = 0xE020_0030) GPA1CONPDN GPA1[n] Bit [2n+1:2n] n=0~3 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.3.6 Port Group GPA1 Control Register (GPA1PUDPDN, R/W, Address = 0xE020_0034) GPA1PUDPDN GPA1[n] Bit Description [2n+1:2n] n=0~3 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-46 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.4 PORT GROUP GPB CONTROL REGISTER There are six control registers, namely, GPBCON, GPBDAT, GPBPUD, GPBDRV, GPBCONPDN and GPBPUDPDN in the Port Group GPB Control Registers. 2.2.4.1 Port Group GPB Control Register (GPBCON, R/W, Address = 0xE020_0040) GPBCON GPBCON[7] GPBCON[6] GPBCON[5] GPBCON[4] GPBCON[3] GPBCON[2] GPBCON[1] GPBCON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = SPI_1_MOSI 0011 ~ 1110 = Reserved 1111 = GPB_INT[7] 0000 = Input 0001 = Output 0010 = SPI_1_MISO 0011 ~ 1110 = Reserved 1111 = GPB_INT[6] 0000 = Input 0001 = Output 0010 = SPI_1_nSS 0011 ~ 1110 = Reserved 1111 = GPB_INT[5] 0000 = Input 0001 = Output 0010 = SPI_1_CLK 0011 ~ 1110 = Reserved 1111 = GPB_INT[4] 0000 = Input 0001 = Output 0010 = SPI_0_MOSI 0011 ~ 1110 = Reserved 1111 = GPB_INT[3] 0000 = Input 0001 = Output 0010 = SPI_0_MISO 0011 ~ 1110 = Reserved 1111 = GPB_INT[2] 0000 = Input 0001 = Output 0010 = SPI_0_nSS 0011 ~ 1110 = Reserved 1111 = GPB_INT[1] 0000 = Input 0001 = Output 0010 = SPI_0_CLK 0011 ~ 1110 = Reserved 1111 = GPB_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 0000 2-47 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.4.2 Port Group GPB Control Register (GPBDAT, R/W, Address = 0xE020_0044) GPBDAT GPBDAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.4.3 Port Group GPB Control Register (GPBPUD, R/W, Address = 0xE020_0048) GPBPUD GPBPUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.4.4 Port Group GPB Control Register (GPBDRV, R/W, Address = 0xE020_004C) GPBDRV GPBDRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.4.5 Port Group GPB Control Register (GPBCONPDN, R/W, Address = 0xE020_0050) GPBCONPDN GPB[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.4.6 Port Group GPB Control Register (GPBPUDPDN, R/W, Address = 0xE020_0054) GPBPUDPDN GPB[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-48 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.5 PORT GROUP GPC0 CONTROL REGISTER There are six control registers, namely, GPC0CON, GPC0DAT, GPC0PUD, GPC0DRV, GPC0CONPDN and GPC0PUDPDN in the Port Group GPC0 Control Registers. 2.2.5.1 Port Group GPC0 Control Register (GPC0CON, R/W, Address = 0xE020_0060) GPC0CON GPC0CON[4] GPC0CON[3] GPC0CON[2] GPC0CON[1] GPC0CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = I2S_1_SDO 0011 = PCM_1_SOUT 0100 = AC97SDO 0101 ~ 1110 = Reserved 1111 = GPC0_INT[4] 0000 = Input 0001 = Output 0010 = I2S_1_SDI 0011 = PCM_1_SIN 0100 = AC97SDI 0101 ~ 1110 = Reserved 1111 = GPC0_INT[3] 0000 = Input 0001 = Output 0010 = I2S_1_LRCK 0011 = PCM_1_FSYNC 0100 = AC97SYNC 0101 ~ 1110 = Reserved 1111 = GPC0_INT[2] 0000 = Input 0001 = Output 0010 = I2S_1_CDCLK 0011 = PCM_1_EXTCLK 0100 = AC97RESETn 0101 ~ 1110 = Reserved 1111 = GPC0_INT[1] 0000 = Input 0001 = Output 0010 = I2S_1_SCLK 0011 = PCM_1_SCLK 0100 = AC97BITCLK 0101 ~ 1110 = Reserved 1111 = GPC0_INT[0] Initial State 0000 0000 0000 0000 0000 2-49 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.5.2 Port Group GPC0 Control Register (GPC0DAT, R/W, Address = 0xE020_0064) GPC0DAT GPC0DAT[4:0] Bit Description [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.5.3 Port Group GPC0 Control Register (GPC0PUD, R/W, Address = 0xE020_0068) GPC0PUD GPC0PUD[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0155 2.2.5.4 Port Group GPC0 Control Register (GPC0DRV, R/W, Address = 0xE020_006C) GPC0DRV GPC0DRV[n] Bit [2n+1:2n] n=0~4 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.5.5 Port Group GPC0 Control Register (GPC0CONPDN, R/W, Address = 0xE020_0070) GPC0CONPDN GPC0[n] Bit [2n+1:2n] n=0~4 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.5.6 Port Group GPC0 Control Register (GPC0PUDPDN, R/W, Address = 0xE020_0074) GPC0PUDPDN GPC0[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-50 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.6 PORT GROUP GPC1 CONTROL REGISTER There are six control registers, namely, GPC1CON, GPC1DAT, GPC1PUD, GPC1DRV, GPC1CONPDN and GPC1PUDPDN in the Port Group GPC1 Control Registers. 2.2.6.1 Port Group GPC1 Control Register (GPC1CON, R/W, Address = 0xE020_0080) GPC1CON GPC1CON[4] GPC1CON[3] GPC1CON[2] GPC1CON[1] GPC1CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = PCM_2_SOUT 0011 = Reserved 0100 = I2S_2_SDO 0101 ~ 1110 = Reserved 1111 = GPC1_INT[4] 0000 = Input 0001 = Output 0010 = PCM_2_SIN 0011 = Reserved 0100 = I2S_2_SDI 0101 ~ 1110 = Reserved 1111 = GPC1_INT[3] 0000 = Input 0001 = Output 0010 = PCM_2_FSYNC 0011 = LCD_FRM 0100 = I2S_2_LRCK 0101 ~ 1110 = Reserved 1111 = GPC1_INT[2] 0000 = Input 0001 = Output 0010 = PCM_2_EXTCLK 0011 = SPDIF_EXTCLK 0100 = I2S_2_CDCLK 0101 ~ 1110 = Reserved 1111 = GPC1_INT[1] 0000 = Input 0001 = Output 0010 = PCM_2_SCLK 0011 = SPDIF_0_OUT 0100 = I2S_2_SCLK 0101 ~ 1110 = Reserved 1111 = GPC1_INT[0] Initial State 0000 0000 0000 0000 0000 2-51 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.6.2 Port Group GPC1 Control Register (GPC1DAT, R/W, Address = 0xE020_0084) GPC1DAT GPC1DAT[4:0] Bit Description [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.6.3 Port Group GPC1 Control Register (GPC1PUD, R/W, Address = 0xE020_0088) GPC1PUD GPC1PUD[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0155 2.2.6.4 Port Group GPC1 Control Register (GPC1DRV, R/W, Address = 0xE020_008C) GPC1DRV GPC1DRV[n] Bit [2n+1:2n] n=0~4 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.6.5 Port Group GPC1 Control Register (GPC1CONPDN, R/W, Address = 0xE020_0090) GPC1CONPDN GPC1[n] Bit [2n+1:2n] n=0~4 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.6.6 Port Group GPC1 Control Register (GPC1PUDPDN, R/W, Address = 0xE020_0094) GPC1PUDPDN GPC1[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-52 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.7 PORT GROUP GPD0 CONTROL REGISTER There are six control registers, namely, GPD0CON, GPD0DAT, GPD0PUD, GPD0DRV, GPD0CONPDN and GPD0PUDPDN in the Port Group GPD0 Control Registers. 2.2.7.1 Port Group GPD0 Control Register (GPD0CON, R/W, Address = 0xE020_00A0) GPD0CON GPD0CON[3] GPD0CON[2] GPD0CON[1] GPD0CON[0] Bit [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = TOUT_3 0011 ~ 1110 = Reserved 1111 = GPD0_INT[3] 0000 = Input 0001 = Output 0010 = TOUT_2 0011 ~ 1110 = Reserved 1111 = GPD0_INT[2] 0000 = Input 0001 = Output 0010 = TOUT_1 0011 ~ 1110 = Reserved 1111 = GPD0_INT[1] 0000 = Input 0001 = Output 0010 = TOUT_0 0011 ~ 1110 = Reserved 1111 = GPD0_INT[0] Initial State 0000 0000 0000 0000 2.2.7.2 Port Group GPD0 Control Register (GPD0DAT, R/W, Address = 0xE020_00A4) GPD0DAT GPD0DAT[3:0] Bit Description [3:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.7.3 Port Group GPD0 Control Register (GPD0PUD, R/W, Address = 0xE020_00A8) GPD0PUD GPD0PUD[n] Bit Description [2n+1:2n] n=0~3 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0055 2-53 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.7.4 Port Group GPD0 Control Register (GPD0DRV, R/W, Address = 0xE020_00AC) GPD0DRV GPD0DRV[n] Bit [2n+1:2n] n=0~3 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.7.5 Port Group GPD0 Control Register (GPD0CONPDN, R/W, Address = 0xE020_00B0) GPD0CONPDN GPD0[n] Bit [2n+1:2n] n=0~3 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.7.6 Port Group GPD0 Control Register (GPD0PUDPDN, R/W, Address = 0xE020_00B4) GPD0PUDPDN GPD0[n] Bit Description [2n+1:2n] n=0~3 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-54 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.8 PORT GROUP GPD1 CONTROL REGISTER There are six control registers, namely, GPD1CON, GPD1DAT, GPD1PUD, GPD1DRV, GPD1CONPDN and GPD1PUDPDN in the Port Group GPD1 Control Registers. 2.2.8.1 Port Group GPD1 Control Register (GPD1CON, R/W, Address = 0xE020_00C0) GPD1CON GPD1CON[5] GPD1CON[4] GPD1CON[3] GPD1CON[2] GPD1CON[1] GPD1CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = I2C2_SCL 0011 = IEM_SPWI 0100 ~ 1110 = Reserved 1111 = GPD1_INT[5] 0000 = Input 0001 = Output 0010 = I2C2_SDA 0011 = IEM_SCLK 0100 ~ 1110 = Reserved 1111 = GPD1_INT[4] 0000 = Input 0001 = Output 0010 = I2C1_SCL 0011 ~ 1110 = Reserved 1111 = GPD1_INT[3] 0000 = Input 0001 = Output 0010 = I2C1_SDA 0011 ~ 1110 = Reserved 1111 = GPD1_INT[2] 0000 = Input 0001 = Output 0010 = I2C0_SCL 0011 ~ 1110 = Reserved 1111 = GPD1_INT[1] 0000 = Input 0001 = Output 0010 = I2C0_SDA 0011 ~ 1110 = Reserved 1111 = GPD1_INT[0] Initial State 0000 0000 0000 0000 0000 0000 2-55 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.8.2 Port Group GPD1 Control Register (GPD1DAT, R/W, Address = 0xE020_00C4) GPD1DAT GPD1DAT[5:0] Bit Description [5:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.8.3 Port Group GPD1 Control Register (GPD1PUD, R/W, Address = 0xE020_00C8) GPD1PUD GPD1PUD[n] Bit Description [2n+1:2n] n=0~5 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0555 2.2.8.4 Port Group GPD1 Control Register (GPD1DRV, R/W, Address = 0xE020_00CC) GPD1DRV GPD1DRV[n] Bit [2n+1:2n] n=0~5 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.8.5 Port Group GPD1 Control Register (GPD1CONPDN, R/W, Address = 0xE020_00D0) GPD1CONPDN GPD1[n] Bit [2n+1:2n] n=0~5 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.8.6 Port Group GPD1 Control Register (GPD1PUDPDN, R/W, Address = 0xE020_00D4) GPD1PUDPDN GPD1[n] Bit Description [2n+1:2n] n=0~5 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-56 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.9 PORT GROUP GPE0 CONTROL REGISTER There are six control registers, namely, GPE0CON, GPE0DAT, GPE0PUD, GPE0DRV, GPE0CONPDN and GPE0PUDPDN in the Port Group GPE0 Control Registers. 2.2.9.1 Port Group GPE0 Control Register (GPE0CON, R/W, Address = 0xE020_00E0) GPE0CON GPE0CON[7] GPE0CON[6] GPE0CON[5] GPE0CON[4] GPE0CON[3] GPE0CON[2] GPE0CON[1] GPE0CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = CAM_A_DATA[4] 0011 ~ 1110 = Reserved 1111 = GPE0_INT[7] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[3] 0011 ~ 1110 = Reserved 1111 = GPE0_INT[6] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[2] 0011 ~ 1110 = Reserved 1111 = GPE0_INT[5] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[1] 0011 ~ 1110 = Reserved 1111 = GPE0_INT[4] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[0] 0011 ~ 1110 = Reserved 1111 = GPE0_INT[3] 0000 = Input 0001 = Output 0010 = CAM_A_HREF 0011 ~ 1110 = Reserved 1111 = GPE0_INT[2] 0000 = Input 0001 = Output 0010 = CAM_A_VSYNC 0011 ~ 1110 = Reserved 1111 = GPE0_INT[1] 0000 = Input 0001 = Output 0010 = CAM_A_PCLK 0011 ~ 1110 = Reserved 1111 = GPE0_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 0000 2-57 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.9.2 Port Group GPE0 Control Register (GPE0DAT, R/W, Address = 0xE020_00E4) GPE0DAT GPE0DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.9.3 Port Group GPE0 Control Register (GPE0PUD, R/W, Address = 0xE020_00E8) GPE0PUD GPE0PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.9.4 Port Group GPE0 Control Register (GPE0DRV, S/W, Address = 0xE020_00EC) GPE0DRV GPE0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.9.5 Port Group GPE0 Control Register (GPE0CONPDN, S/W, Address = 0xE020_00F0) GPE0CONPDN GPE0[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.9.6 Port Group GPE0 Control Register (GPE0PUDPDN, S/W, Address = 0xE020_00F4) GPE0PUDPDN GPE0[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-58 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.10 PORT GROUP GPE1 CONTROL REGISTER There are six control registers, namely, GPE1CON, GPE1DAT, GPE1PUD, GPE1DRV, GPE1CONPDN and GPE1PUDPDN in the Port Group GPE1 Control Registers. 2.2.10.1 Port Group GPE1 Control Register (GPE1CON, R/W, Address = 0xE020_0100) GPE1CON GPE1CON[4] GPE1CON[3] GPE1CON[2] GPE1CON[1] GPE1CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = CAM_A_FIELD 0011 ~ 1110 = Reserved 1111 = GPE1_INT[4] 0000 = Input 0001 = Output 0010 = CAM_A_CLKOUT 0011 ~ 1110 = Reserved 1111 = GPE1_INT[3] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[7] 0011 ~ 1110 = Reserved 1111 = GPE1_INT[2] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[6] 0011 ~ 1110 = Reserved 1111 = GPE1_INT[1] 0000 = Input 0001 = Output 0010 = CAM_A_DATA[5] 0011 ~ 1110 = Reserved 1111 = GPE1_INT[0] Initial State 0000 0000 0000 0000 0000 2.2.10.2 Port Group GPE1 Control Register (GPE1DAT, R/W, Address = 0xE020_0104) GPE1DAT GPE1DAT[4:0] Bit Description [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2-59 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.10.3 Port Group GPE1 Control Register (GPE1PUD, R/W, Address = 0xE020_0108) GPE1PUD GPE1PUD[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0155 2.2.10.4 Port Group GPE1 Control Register (GPE1DRV, R/W, Address = 0xE020_010C) GPE1DRV GPE1DRV[n] Bit [2n+1:2n] n=0~4 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.10.5 Port Group GPE1 Control Register (GPE1CONPDN, R/W, Address = 0xE020_0110) GPE1CONPDN GPE1[n] Bit [2n+1:2n] n=0~4 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.10.6 Port Group GPE1 Control Register (GPE1PUDPDN, R/W, Address = 0xE020_0114) GPE1PUDPDN GPE1[n] Bit Description [2n+1:2n] n=0~4 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-60 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.11 PORT GROUP GPF0 CONTROL REGISTER There are six control registers, namely, GPF0CON, GPF0DAT, GPF0PUD, GPF0DRV, GPF0CONPDN and GPF0PUDPDN in the Port Group GPF0 Control Registers. 2.2.11.1 Port Group GPF0 Control Register (GPF0CON, R/W, Address = 0xE020_0120) GPF0CON GPF0CON[7] GPF0CON[6] GPF0CON[5] GPF0CON[4] GPF0CON[3] GPF0CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = LCD_VD[3] 0011 = SYS_VD[3] 0100 = VEN_DATA[3] 0101 ~ 1110 = Reserved 1111 = GPF0_INT[7] 0000 = Input 0001 = Output 0010 = LCD_VD[2] 0011 = SYS_VD[2] 0100 = VEN_DATA[2] 0101 ~ 1110 = Reserved 1111 = GPF0_INT[6] 0000 = Input 0001 = Output 0010 = LCD_VD[1] 0011 = SYS_VD[1] 0100 = VEN_DATA[1] 0101 ~ 1110 = Reserved 1111 = GPF0_INT[5] 0000 = Input 0001 = Output 0010 = LCD_VD[0] 0011 = SYS_VD[0] 0100 = VEN_DATA[0] 0101 ~ 1110 = Reserved 1111 = GPF0_INT[4] 0000 = Input 0001 = Output 0010 = LCD_VCLK 0011 = SYS_WE 0100 = V601_CLK 0101 ~ 1110 = Reserved 1111 = GPF0_INT[3] 0000 = Input 0001 = Output 0010 = LCD_VDEN 0011 = SYS_RS 0100 = VEN_HREF 0101 ~ 1110 = Reserved 1111 = GPF0_INT[2] Initial State 0000 0000 0000 0000 0000 0000 2-61 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF0CON GPF0CON[1] GPF0CON[0] Bit Description [7:4] 0000 = Input 0001 = Output 0010 = LCD_VSYNC 0011 = SYS_CS1 0100 = VEN_VSYNC 0101 ~ 1110 = Reserved 1111 = GPF0_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = LCD_HSYNC 0011 = SYS_CS0 0100 = VEN_HSYNC 0101 ~ 1110 = Reserved 1111 = GPF0_INT[0] Initial State 0000 0000 2.2.11.2 Port Group GPF0 Control Register (GPF0DAT, R/W, Address = 0xE020_0124) GPF0DAT GPF0DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.11.3 Port Group GPF0 Control Register (GPF0PUD, R/W, Address = 0xE020_0128) GPF0PUD GPF0PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.11.4 Port Group GPF0 Control Register (GPF0DRV, R/W, Address = 0xE020_012C) GPF0DRV GPF0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2-62 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.11.5 Port Group GPF0 Control Register (GPF0CONPDN, R/W, Address = 0xE020_0130) GPF0CONPDN GPF0[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.11.6 Port Group GPF0 Control Register (GPF0PUDPDN, R/W, Address = 0xE020_0134) GPF0PUDPDN GPF0[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-63 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.12 PORT GROUP GPF1 CONTROL REGISTER There are six control registers, namely, GPF1CON, GPF1DAT, GPF1PUD, GPF1DRV, GPF1CONPDN and GPF1PUDPDN in the Port Group GPF1 Control Registers. 2.2.12.1 Port Group GPF1 Control Register (GPF1CON, S/W, Address = 0xE020_0140) GPF1CON GPF1CON[7] GPF1CON[6] GPF1CON[5] GPF1CON[4] GPF1CON[3] GPF1CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = LCD_VD[11] 0011 = SYS_VD[11] 0100 = V656_DATA[3] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[7] 0000 = Input 0001 = Output 0010 = LCD_VD[10] 0011 = SYS_VD[10] 0100 = V656_DATA[2] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[6] 0000 = Input 0001 = Output 0010 = LCD_VD[9] 0011 = SYS_VD[9] 0100 = V656_DATA[1] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[5] 0000 = Input 0001 = Output 0010 = LCD_VD[8] 0011 = SYS_VD[8] 0100 = V656_DATA[0] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[4] 0000 = Input 0001 = Output 0010 = LCD_VD[7] 0011 = SYS_VD[7] 0100 = VEN_DATA[7] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[3] 0000 = Input 0001 = Output 0010 = LCD_VD[6] 0011 = SYS_VD[6] 0100 = VEN_DATA[6] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[2] Initial State 0000 0000 0000 0000 0000 0000 2-64 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF1CON GPF1CON[1] GPF1CON[0] Bit Description [7:4] 0000 = Input 0001 = Output 0010 = LCD_VD[5] 0011 = SYS_VD[5] 0100 = VEN_DATA[5] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = LCD_VD[4] 0011 = SYS_VD[4] 0100 = VEN_DATA[4] 0101 ~ 1110 = Reserved 1111 = GPF1_INT[0] Initial State 0000 0000 2.2.12.2 Port Group GPF1 Control Register (GPF1DAT, S/W, Address = 0xE020_0144) GPF1DAT GPF1DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.12.3 Port Group GPF1 Control Register (GPF1PUD, S/W, Address = 0xE020_0148) GPF1PUD GPF1PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.12.4 Port Group GPF1 Control Register (GPF1DRV, S/W, Address = 0xE020_014C) GPF1DRV GPF1DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2-65 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.12.5 Port Group GPF1 Control Register (GPF1CONPDN, S/W, Address = 0xE020_0150) GPF1CONPDN GPF1[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.12.6 Port Group GPF1 Control Register (GPF1PUDPDN, S/W, Address = 0xE020_0154) GPF1PUDPDN GPF1[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-66 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.13 PORT GROUP GPF2 CONTROL REGISTER There are six control registers, namely, GPF2CON, GPF2DAT, GPF2PUD, GPF2DRV, GPF2CONPDN and GPF2PUDPDN in the Port Group GPF2 Control Registers. 2.2.13.1 Port Group GPF2 Control Register (GPF2CON, R/W, Address = 0xE020_0160) GPF2CON GPF2CON[7] GPF2CON[6] GPF2CON[5] GPF2CON[4] GPF2CON[3] GPF2CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = LCD_VD[19] 0011 = SYS_VD[19] 0100 ~ 1110 = Reserved 1111 = GPF2_INT[7] 0000 = Input 0001 = Output 0010 = LCD_VD[18] 0011 = SYS_VD[18] 0100 ~ 1110 = Reserved 1111 = GPF2_INT[6] 0000 = Input 0001 = Output 0010 = LCD_VD[17] 0011 = SYS_VD[17] 0100 ~ 1110 = Reserved 1111 = GPF2_INT[5] 0000 = Input 0001 = Output 0010 = LCD_VD[16] 0011 = SYS_VD[16] 0100 ~ 1110 = Reserved 1111 = GPF2_INT[4] 0000 = Input 0001 = Output 0010 = LCD_VD[15] 0011 = SYS_VD[15] 0100 = V656_DATA[7] 0101 ~ 1110 = Reserved 1111 = GPF2_INT[3] 0000 = Input 0001 = Output 0010 = LCD_VD[14] 0011 = SYS_VD[14] 0100 = V656_DATA[6] 0101 ~ 1110 = Reserved 1111 = GPF2_INT[2] Initial State 0000 0000 0000 0000 0000 0000 2-67 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF2CON GPF2CON[1] GPF2CON[0] Bit Description [7:4] 0000 = Input 0001 = Output 0010 = LCD_VD[13] 0011 = SYS_VD[13] 0100 = V656_DATA[5] 0101 ~ 1110 = Reserved 1111 = GPF2_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = LCD_VD[12] 0011 = SYS_VD[12] 0100 = V656_DATA[4] 0101 ~ 1110 = Reserved 1111 = GPF2_INT[0] Initial State 0000 0000 2.2.13.2 Port Group GPF2 Control Register (GPF2DAT, R/W, Address = 0xE020_0164) GPF2DAT GPF2DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.13.3 Port Group GPF2 Control Register (GPF2PUD, R/W, Address = 0xE020_0168) GPF2PUD GPF2PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.13.4 Port Group GPF2 Control Register (GPF2DRV, S/W, Address = 0xE020_016C) GPF2DRV GPF2DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2-68 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.13.5 Port Group GPF2 Control Register (GPF2CONPDN, S/W, Address = 0xE020_0170) GPF2CONPDN GPF2[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.13.6 Port Group GPF2 Control Register (GPF2PUDPDN, S/W, Address = 0xE020_0174) GPF2PUDPDN GPF2[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-69 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.14 PORT GROUP GPF3 CONTROL REGISTER There are six control registers, namely, GPF3CON, GPF3DAT, GPF3PUD, GPF3DRV, GPF3CONPDN and GPF3PUDPDN in the Port Group GPF3 Control Registers. 2.2.14.1 Port Group GPF3 Control Register (GPF3CON, R/W, Address = 0xE020_0180) GPF3CON GPF3CON[5] GPF3CON[4] GPF3CON[3] GPF3CON[2] GPF3CON[1] GPF3CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = Reserved 0011 = SYS_OE 0100 = VEN_FIELD 0101 ~ 1110 = Reserved 1111 = GPF3_INT[5] 0000 = Input 0001 = Output 0010 = Reserved 0011 = VSYNC_LDI 0100 ~ 1110 = Reserved 1111 = GPF3_INT[4] 0000 = Input 0001 = Output 0010 = LCD_VD[23] 0011 = SYS_VD[23] 0100 = V656_CLK 0101 ~ 1110 = Reserved 1111 = GPF3_INT[3] 0000 = Input 0001 = Output 0010 = LCD_VD[22] 0011 = SYS_VD[22] 0100 ~ 1110 = Reserved 1111 = GPF3_INT[2] 0000 = Input 0001 = Output 0010 = LCD_VD[21] 0011 = SYS_VD[21] 0100 ~ 1110 = Reserved 1111 = GPF3_INT[1] 0000 = Input 0001 = Output 0010 = LCD_VD[20] 0011 = SYS_VD[20] 0100 ~ 1110 = Reserved 1111 = GPF3_INT[0] Initial State 0000 0000 0000 0000 0000 0000 2-70 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.14.2 Port Group GPF3 Control Register (GPF3DAT, R/W, Address = 0xE020_0184) GPF3DAT GPF3DAT[5:0] Bit Description [5:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.14.3 Port Group GPF3 Control Register (GPF3PUD, R/W, Address = 0xE020_0188) GPF3PUD GPF3PUD[n] Bit Description [2n+1:2n] n=0~5 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0555 2.2.14.4 Port Group GPF3 Control Register (GPF3DRV, R/W, Address = 0xE020_018C) GPF3DRV GPF3DRV[n] Bit [2n+1:2n] n=0~5 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.14.5 Port Group GPF3 Control Register (GPF3CONPDN, R/W, Address = 0xE020_0190) GPF3CONPDN GPF3[n] Bit [2n+1:2n] n=0~5 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.14.6 Port Group GPF3 Control Register (GPF3PUDPDN, R/W, Address = 0xE020_0194) GPF3PUDPDN GPF3[n] Bit Description [2n+1:2n] n=0~5 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-71 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.15 PORT GROUP GPG0 CONTROL REGISTER There are six control registers, namely, GPG0CON, GPG0DAT, GPG0PUD, GPG0DRV, GPG0CONPDN and GPG0PUDPDN in the Port Group GPG0 Control Registers. 2.2.15.1 Port Group GPG0 Control Register (GPG0CON, R/W, Address = 0xE020_01A0) GPG0CON GPG0CON[6] GPG0CON[5] GPG0CON[4] GPG0CON[3] GPG0CON[2] GPG0CON[1] GPG0CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = SD_0_DATA[3] 0011 ~ 1110 = Reserved 1111 = GPG0_INT[6] 0000 = Input 0001 = Output 0010 = SD_0_DATA[2] 0011 ~ 1110 = Reserved 1111 = GPG0_INT[5] 0000 = Input 0001 = Output 0010 = SD_0_DATA[1] 0011 ~ 1110 = Reserved 1111 = GPG0_INT[4] 0000 = Input 0001 = Output 0010 = SD_0_DATA[0] 0011 ~ 1110 = Reserved 1111 = GPG0_INT[3] 0000 = Input 0001 = Output 0010 = SD_0_CDn 0011 ~ 1110 = Reserved 1111 = GPG0_INT[2] 0000 = Input 0001 = Output 0010 = SD_0_CMD 0011 ~ 1110 = Reserved 1111 = GPG0_INT[1] 0000 = Input 0001 = Output 0010 = SD_0_CLK 0011 ~ 1110 = Reserved 1111 = GPG0_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 2-72 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.15.2 Port Group GPG0 Control Register (GPG0DAT, R/W, Address = 0xE020_01A4) GPG0DAT GPG0DAT[6:0] Bit Description [6:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.15.3 Port Group GPG0 Control Register (GPG0PUD, R/W, Address = 0xE020_01A8) GPG0PUD GPG0PUD[n] Bit Description [2n+1:2n] n=0~6 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x1555 2.2.15.4 Port Group GPG0 Control Register (GPG0DRV, R/W, Address = 0xE020_01AC) GPG0DRV GPG0DRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x2AAA 2.2.15.5 Port Group GPG0 Control Register (GPG0CONPDN, R/W, Address = 0xE020_01B0) GPG0CONPDN GPG0[n] Bit [2n+1:2n] n=0~6 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.15.6 Port Group GPG0 Control Register (GPG0PUDPDN, R/W, Address = 0xE020_01B4) GPG0PUDPDN GPG0[n] Bit Description [2n+1:2n] n=0~6 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-73 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.16 PORT GROUP GPG1 CONTROL REGISTER There are six control registers, namely, GPG1CON, GPG1DAT, GPG1PUD, GPG1DRV, GPG1CONPDN and GPG1PUDPDN in the Port Group GPG1 Control Registers. 2.2.16.1 Port Group GPG1 Control Register (GPG1CON, R/W, Address = 0xE020_01C0) GPG1CON GPG1CON[6] GPG1CON[5] GPG1CON[4] GPG1CON[3] GPG1CON[2] GPG1CON[1] GPG1CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = SD_1_DATA[3] 0011 = SD_0_DATA[7] 0100 ~ 1110 = Reserved 1111 = GPG1_INT[6] 0000 = Input 0001 = Output 0010 = SD_1_DATA[2] 0011 = SD_0_DATA[6] 0100 ~ 1110 = Reserved 1111 = GPG1_INT[5] 0000 = Input 0001 = Output 0010 = SD_1_DATA[1] 0011 = SD_0_DATA[5] 0100 ~ 1110 = Reserved 1111 = GPG1_INT[4] 0000 = Input 0001 = Output 0010 = SD_1_DATA[0] 0011 = SD_0_DATA[4] 0100 ~ 1110 = Reserved 1111 = GPG1_INT[3] 0000 = Input 0001 = Output 0010 = SD_1_CDn 0011 ~ 1110 = Reserved 1111 = GPG1_INT[2] 0000 = Input 0001 = Output 0010 = SD_1_CMD 0011 ~ 1110 = Reserved 1111 = GPG1_INT[1] 0000 = Input 0001 = Output 0010 = SD_1_CLK 0011 ~ 1110 = Reserved 1111 = GPG1_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 2-74 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.16.2 Port Group GPG1 Control Register (GPG1DAT, R/W, Address = 0xE020_01C4) GPG1DAT GPG1DAT[6:0] Bit Description [6:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.16.3 Port Group GPG1 Control Register (GPG1PUD, R/W, Address = 0xE020_01C8) GPG1PUD GPG1PUD[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x1555 2.2.16.4 Port Group GPG1 Control Register (GPG1DRV, R/W, Address = 0xE020_01CC) GPG1DRV GPG1DRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.16.5 Port Group GPG1 Control Register (GPG1CONPDN, R/W, Address = 0xE020_01D0) GPG1CONPDN GPG1[n] Bit [2n+1:2n] n=0~6 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.16.6 Port Group GPG1 Control Register (GPG1PUDPDN, R/W, Address = 0xE020_01D4) GPG1PUDPDN GPG1[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-75 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.17 PORT GROUP GPG2 CONTROL REGISTER There are six control registers, namely, GPG2CON, GPG2DAT, GPG2PUD, GPG2DRV, GPG2CONPDN and GPG2PUDPDN in the Port Group GPG2 Control Registers. 2.2.17.1 Port Group GPG2 Control Register (GPG2CON, R/W, Address = 0xE020_01E0) GPG2CON GPG2CON[6] GPG2CON[5] GPG2CON[4] GPG2CON[3] GPG2CON[2] GPG2CON[1] GPG2CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = SD_2_DATA[3] 0011 ~ 1110 = Reserved 1111 = GPG2_INT[6] 0000 = Input 0001 = Output 0010 = SD_2_DATA[2] 0011 ~ 1110 = Reserved 1111 = GPG2_INT[5] 0000 = Input 0001 = Output 0010 = SD_2_DATA[1] 0011 ~ 1110 = Reserved 1111 = GPG2_INT[4] 0000 = Input 0001 = Output 0010 = SD_2_DATA[0] 0011 ~ 1110 = Reserved 1111 = GPG2_INT[3] 0000 = Input 0001 = Output 0010 = SD_2_CDn 0011 ~ 1110 = Reserved 1111 = GPG2_INT[2] 0000 = Input 0001 = Output 0010 = SD_2_CMD 0011 ~ 1110 = Reserved 1111 = GPG2_INT[1] 0000 = Input 0001 = Output 0010 = SD_2_CLK 0011 ~ 1110 = Reserved 1111 = GPG2_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 2-76 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.17.2 Port Group GPG2 Control Register (GPG2DAT, R/W, Address = 0xE020_01E4) GPG2DAT GPG2DAT[6:0] Bit [6:0] Description When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.17.3 Port Group GPG2 Control Register (GPG2PUD, R/W, Address = 0xE020_01E8) GPG2PUD GPG2PUD[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x1555 2.2.17.4 Port Group GPG2 Control Register (GPG2DRV, R/W, Address = 0xE020_01EC) GPG2DRV GPG2DRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.17.5 Port Group GPG2 Control Register (GPG2CONPDN, R/W, Address = 0xE020_01F0) GPG2CONPDN GPG2[n] Bit [2n+1:2n] n=0~6 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.17.6 Port Group GPG2 Control Register (GPG2PUDPDN, R/W, Address = 0xE020_01F4) GPG2PUDPDN GPG2[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-77 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.18 PORT GROUP GPG3 CONTROL REGISTER There are six control registers, namely, GPG3CON, GPG3DAT, GPG3PUD, GPG3DRV, GPG3CONPDN and GPG3PUDPDN in the Port Group GPG3 Control Registers. 2.2.18.1 Port Group GPG3 Control Register (GPG3CON, R/W, Address = 0xE020_0200) GPG3CON GPG3CON[6] GPG3CON[5] GPG3CON[4] GPG3CON[3] GPG3CON[2] GPG3CON[1] GPG3CON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = SD_3_DATA[3] 0011 = SD_2_DATA[7] 0100 ~ 1110 = Reserved 1111 = GPG3_INT[6] 0000 = Input 0001 = Output 0010 = SD_3_DATA[2] 0011 = SD_2_DATA[6] 0100 ~ 1110 = Reserved 1111 = GPG3_INT[5] 0000 = Input 0001 = Output 0010 = SD_3_DATA[1] 0011 = SD_2_DATA[5] 0100 ~ 1110 = Reserved 1111 = GPG3_INT[4] 0000 = Input 0001 = Output 0010 = SD_3_DATA[0] 0011 = SD_2_DATA[4] 0100 ~ 1110 = Reserved 1111 = GPG3_INT[3] 0000 = Input 0001 = Output 0010 = SD_3_CDn 0011 ~ 1110 = Reserved 1111 = GPG3_INT[2] 0000 = Input 0001 = Output 0010 = SD_3_CMD 0011 ~ 1110 = Reserved 1111 = GPG3_INT[1] 0000 = Input 0001 = Output 0010 = SD_3_CLK 0011 ~ 1110 = Reserved 1111 = GPG3_INT[0] Initial State 0000 0000 0000 0000 0000 0000 0000 2-78 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.18.2 Port Group GPG3 Control Register (GPG3DAT, R/W, Address = 0xE020_0204) GPG3DAT GPG3DAT[6:0] Bit Description [6:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.18.3 Port Group GPG3 Control Register (GPG3PUD, R/W, Address = 0xE020_0208) GPG3PUD GPG3PUD[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x1555 2.2.18.4 Port Group GPG3 Control Register (GPG3DRV, R/W, Address = 0xE020_020C) GPG3DRV GPG3DRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.18.5 Port Group GPG3 Control Register (GPG3CONPDN, R/W, Address = 0xE020_0210) GPG3CONPDN GPG3[n] Bit [2n+1:2n] n=0~6 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.18.6 Port Group GPG3 Control Register (GPG3PUDPDN, R/W, Address = 0xE020_0214) GPG3PUDPDN GPG3[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-79 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.19 PORT GROUP GPI CONTROL REGISTER There are four control registers, namely, GPICON, GPIPUD and GPIDRV in the Port Group GPI Control Registers. This port group is used to only functional port (I2S_0 and PCM_0), not GPIO and EXT_INT. 2.2.19.1 Port Group GPI Control Register (GPICON, R/W, Address = 0xE020_0220) GPICON GPICON[6] GPICON[5] GPICON[4] GPICON[3] GPICON[2] GPICON[1] GPICON[0] Bit [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0010 = I2S_0_SDO[2] 0010 = I2S_0_SDO[1] 0010 = I2S_0_SDO[0] 0011 = PCM_0_SOUT 0010 = I2S_0_SDI 0011 = PCM_0_SIN 0010 = I2S_0_LRCK 0011 = PCM_0_FSYNC 0010 = I2S_0_CDCLK 0011 = PCM_0_EXTCLK 0010 = I2S_0_SCLK 0011 = PCM_0_SCLK Initial State 0010 0010 0010 0010 0010 0010 0010 2.2.19.2 Port Group GPI Control Register (GPIDAT, R/W, Address = 0xE020_0224) GPIDAT GPIDAT[6:0] Bit [31:0] Reserved Description Initial State 0x00 2.2.19.3 Port Group GPI Control Register (GPIPUD, R/W, Address = 0xE020_0228) GPIPUD GPIPUD[n] Bit [2n+1:2n] n=0~6 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x1555 2-80 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.19.4 Port Group GPI Control Register (GPIDRV, R/W, Address = 0xE020_022C) GPIDRV GPIDRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.19.5 Port Group GPI Control Register (GPICONPDN, R/W, Address = 0xE020_0230) GPICONPDN GPI[n] Bit [2n+1:2n] n=0~6 Description Reserved (Controlled by PAD_CON_CTRL register at AUDIO_SS) Initial State 0x00 2.2.19.6 Port Group GPI Control Register (GPIPUDPDN, R/W, Address = 0xE020_0234) GPIPUDPDN GPI[n] Bit [2n+1:2n] n=0~6 Description Reserved (Controlled by GPIPUD register) For GPI PDN control in power down mode, PAD_PDN_CTRL Register of GPI is at AUDIO_SS. For more information, refer to Chapter 10.01, Low Power Audio Subsystem. Initial State 0x00 2-81 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.20 PORT GROUP GPJ0 CONTROL REGISTER There are six control registers, namely, GPJ0CON, GPJ0DAT, GPJ0PUD, GPJ0DRV, GPJ0CONPDN and GPJ0PUDPDN in the Port Group GPJ0 Control Registers. 2.2.20.1 Port Group GPJ0 Control Register (GPJ0CON, R/W, Address = 0xE020_0240) GPJ0CON GPJ0CON[7] GPJ0CON[6] GPJ0CON[5] GPJ0CON[4] GPJ0CON[3] GPJ0CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = MSM_ADDR[7] 0011 = CAM_B_DATA[7] 0100 = CF_DMACKNs 0101 = MHL_D0 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[7] 0000 = Input 0001 = Output 0010 = MSM_ADDR[6] 0011 = CAM_B_DATA[6] 0100 = CF_DRESETN 0101 = TS_ERROR 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[6] 0000 = Input 0001 = Output 0010 = MSM_ADDR[5] 0011 = CAM_B_DATA[5] 0100 = CF_DMARQ 0101 = TS_DATA 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[5] 0000 = Input 0001 = Output 0010 = MSM_ADDR[4] 0011 = CAM_B_DATA[4] 0100 = CF_INTRQ 0101 = TS_VAL 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[4] 0000 = Input 0001 = Output 0010 = MSM_ADDR[3] 0011 = CAM_B_DATA[3] 0100 = CF_IORDY 0101 = TS_SYNC 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[3] 0000 = Input 0001 = Output 0010 = MSM_ADDR[2] Initial State 0000 0000 0000 0000 0000 0000 2-82 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ0CON GPJ0CON[1] GPJ0CON[0] Bit Description 0011 = CAM_B_DATA[2] 0100 = CF_ADDR[2] 0101 = TS_CLK 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[2] [7:4] 0000 = Input 0001 = Output 0010 = MSM_ADDR[1] 0011 = CAM_B_DATA[1] 0100 = CF_ADDR[1] 0101 = MIPI_ESC_CLK 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = MSM_ADDR[0] 0011 = CAM_B_DATA[0] 0100 = CF_ADDR[0] 0101 = MIPI_BYTE_CLK 0110 ~ 1110 = Reserved 1111 = GPJ0_INT[0] Initial State 0000 0000 2.2.20.2 Port Group GPJ0 Control Register (GPJ0DAT, R/W, Address = 0xE020_0244) GPJ0DAT GPJ0DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.20.3 Port Group GPJ0 Control Register (GPJ0PUD, R/W, Address = 0xE020_0248) GPJ0PUD GPJ0PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2-83 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.20.4 Port Group GPJ0 Control Register (GPJ0DRV, R/W, Address = 0xE020_024C) GPJ0DRV GPJ0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.20.5 Port Group GPJ0 Control Register (GPJ0CONPDN, R/W, Address = 0xE020_0250) GPJ0CONPDN GPJ0[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.20.6 Port Group GPJ0 Control Register (GPJ0PUDPDN, R/W, Address = 0xE020_0254) GPJ0PUDPDN GPJ0[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-84 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.21 PORT GROUP GPJ1 CONTROL REGISTER There are six control registers, namely, GPJ1CON, GPJ1DAT, GPJ1PUD, GPJ1DRV, GPJ1CONPDN and GPJ1PUDPDN in the Port Group GPJ1 Control Registers. 2.2.21.1 Port Group GPJ1 Control Register (GPJ1CON, R/W, Address = 0xE020_0260) GPJ0CON GPJ1CON[5] GPJ1CON[4] GPJ1CON[3] GPJ1CON[2] GPJ1CON[1] GPJ1CON[0] Bit [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = MSM_ADDR[13] 0011 = KP_COL[0] 0100 = SROM_ADDR_16to22[5] 0101 = MHL_D6 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[5] 0000 = Input 0001 = Output 0010 = MSM_ADDR[12] 0011 = CAM_B_CLKOUT 0100 = SROM_ADDR_16to22[4] 0101 = MHL_D5 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[4] 0000 = Input 0001 = Output 0010 = MSM_ADDR[11] 0011 = CAM_B_FIELD 0100 = SROM_ADDR_16to22[3] 0101 = MHL_D4 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[3] 0000 = Input 0001 = Output 0010 = MSM_ADDR[10] 0011 = CAM_B_HREF 0100 = SROM_ADDR_16to22[2] 0101 = MHL_D3 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[2] 0000 = Input 0001 = Output 0010 = MSM_ADDR[9] 0011 = CAM_B_VSYNC 0100 = SROM_ADDR_16to22[1] 0101 = MHL_D2 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[1] 0000 = Input 0001 = Output 0010 = MSM_ADDR[8] 0011 = CAM_B_PCLK 0100 = SROM_ADDR_16to22[0] 0101 = MHL_D1 0110 ~ 1110 = Reserved 1111 = GPJ1_INT[0] Initial State 0000 0000 0000 0000 0000 0000 2-85 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.21.2 Port Group GPJ1 Control Register (GPJ1DAT, R/W, Address = 0xE020_0264) GPJ1DAT GPJ1DAT[5:0] Bit Description [5:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.21.3 Port Group GPJ1 Control Register (GPJ1PUD, R/W, Address = 0xE020_0268) GPJ1PUD GPJ1PUD[n] Bit [2n+1:2n] n=0~5 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0555 2.2.21.4 Port Group GPJ1 Control Register (GPJ1DRV, R/W, Address = 0xE020_026C) GPJ1DRV GPJ1DRV[n] Bit [2n+1:2n] n=0~5 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.21.5 Port Group GPJ1 Control Register (GPJ1CONPDN, R/W, Address = 0xE020_0270) GPJ1CONPDN GPJ1[n] Bit [2n+1:2n] n=0~5 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.21.6 Port Group GPJ1 Control Register (GPJ1PUDPDN, R/W, Address = 0xE020_0274) GPJ1PUDPDN GPJ1[n] Bit [2n+1:2n] n=0~5 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-86 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.22 PORT GROUP GPJ2 CONTROL REGISTER There are six control registers, namely, GPJ2CON, GPJ2DAT, GPJ2PUD, GPJ2DRV, GPJ2CONPDN and GPJ2PUDPDN in the Port Group GPJ2 Control Registers. 2.2.22.1 Port Group GPJ2 Control Register (GPJ2CON, R/W, Address = 0xE020_0280) GPJ2CON GPJ2CON[7] GPJ2CON[6] GPJ2CON[5] GPJ2CON[4] GPJ2CON[3] GPJ2CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = MSM_DATA[7] 0011 = KP_ROW[0] 0100 = CF_DATA[7] 0101 = MHL_D14 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[7] 0000 = Input 0001 = Output 0010 = MSM_DATA[6] 0011 = KP_COL[7] 0100 = CF_DATA[6] 0101 = MHL_D13 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[6] 0000 = Input 0001 = Output 0010 = MSM_DATA[5] 0011 = KP_COL[6] 0100 = CF_DATA[5] 0101 = MHL_D12 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[5] 0000 = Input 0001 = Output 0010 = MSM_DATA[4] 0011 = KP_COL[5] 0100 = CF_DATA[4] 0101 = MHL_D11 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[4] 0000 = Input 0001 = Output 0010 = MSM_DATA[3] 0011 = KP_COL[4] 0100 = CF_DATA[3] 0101 = MHL_D10 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[3] 0000 = Input 0001 = Output 0010 = MSM_DATA[2] Initial State 0000 0000 0000 0000 0000 0000 2-87 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ2CON GPJ2CON[1] GPJ2CON[0] Bit Description 0011 = KP_COL[3] 0100 = CF_DATA[2] 0101 = MHL_D9 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[2] [7:4] 0000 = Input 0001 = Output 0010 = MSM_DATA[1] 0011 = KP_COL[2] 0100 = CF_DATA[1] 0101 = MHL_D8 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = MSM_DATA[0] 0011 = KP_COL[1] 0100 = CF_DATA[0] 0101 = MHL_D7 0110 ~ 1110 = Reserved 1111 = GPJ2_INT[0] Initial State 0000 0000 2.2.22.2 Port Group GPJ2 Control Register (GPJ2DAT, R/W, Address = 0xE020_0284) GPJ2DAT GPJ2DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.22.3 Port Group GPJ2 Control Register (GPJ2PUD, R/W, Address = 0xE020_0288) GPJ2PUD GPJ2PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2-88 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.22.4 Port Group GPJ2 Control Register (GPJ2DRV, R/W, Address = 0xE020_028C) GPJ2DRV GPJ2DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.22.5 Port Group GPJ2 Control Register (GPJ2CONPDN, R/W, Address = 0xE020_0290) GPJ2CONPDN GPJ2[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.22.6 Port Group GPJ2 Control Register (GPJ2PUDPDN, R/W, Address = 0xE020_0294) GPJ2PUDPDN GPJ2[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-89 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.23 PORT GROUP GPJ3 CONTROL REGISTER There are six control registers, namely, GPJ3CON, GPJ3DAT, GPJ3PUD, GPJ3DRV, GPJ3CONPDN and GPJ3PUDPDN in the Port Group GPJ3 Control Registers. 2.2.23.1 Port Group GPJ3 Control Register (GPJ3CON, R/W, Address = 0xE020_02A0) GPJ3CON GPJ3CON[7] GPJ3CON[6] GPJ3CON[5] GPJ3CON[4] GPJ3CON[3] GPJ3CON[2] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] Description 0000 = Input 0001 = Output 0010 = MSM_DATA[15] 0011 = KP_ROW[8] 0100 = CF_DATA[15] 0101 = MHL_D22 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[7] 0000 = Input 0001 = Output 0010 = MSM_DATA[14] 0011 = KP_ROW[7] 0100 = CF_DATA[14] 0101 = MHL_D21 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[6] 0000 = Input 0001 = Output 0010 = MSM_DATA[13] 0011 = KP_ROW[6] 0100 = CF_DATA[13] 0101 = MHL_D20 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[5] 0000 = Input 0001 = Output 0010 = MSM_DATA[12] 0011 = KP_ROW[5] 0100 = CF_DATA[12] 0101 = MHL_D19 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[4] 0000 = Input 0001 = Output 0010 = MSM_DATA[11] 0011 = KP_ROW[4] 0100 = CF_DATA[11] 0101 = MHL_D18 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[3] 0000 = Input 0001 = Output 0010 = MSM_DATA[10] Initial State 0000 0000 0000 0000 0000 0000 2-90 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ3CON GPJ3CON[1] GPJ3CON[0] Bit Description 0011 = KP_ROW[3] 0100 = CF_DATA[10] 0101 = MHL_D17 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[2] [7:4] 0000 = Input 0001 = Output 0010 = MSM_DATA[9] 0011 = KP_ROW[2] 0100 = CF_DATA[9] 0101 = MHL_D16 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[1] [3:0] 0000 = Input 0001 = Output 0010 = MSM_DATA[8] 0011 = KP_ROW[1] 0100 = CF_DATA[8] 0101 = MHL_D15 0110 ~ 1110 = Reserved 1111 = GPJ3_INT[0] Initial State 0000 0000 2.2.23.2 Port Group GPJ3 Control Register (GPJ3DAT, R/W, Address = 0xE020_02A4) GPJ3DAT GPJ3DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.23.3 Port Group GPJ3 Control Register (GPJ3PUD, R/W, Address = 0xE020_02A8) GPJ3PUD GPJ3PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2-91 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.23.4 Port Group GPJ3 Control Register (GPJ3DRV, R/W, Address = 0xE020_02AC) GPJ3DRV GPJ3DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.23.5 Port Group GPJ3 Control Register (GPJ3CONPDN, R/W, Address = 0xE020_02B0) GPJ3CONPDN GPJ3[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.23.6 Port Group GPJ3 Control Register (GPJ3PUDPDN, R/W, Address = 0xE020_02B4) GPJ3PUDPDN GPJ3[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-92 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.24 PORT GROUP GPJ4 CONTROL REGISTER There are six control registers, namely, GPJ4CON, GPJ4DAT, GPJ4PUD, GPJ4DRV, GPJ4CONPDN and GPJ4PUDPDN in the Port Group GPJ4 Control Registers. 2.2.24.1 Port Group GPJ4 Control Register (GPJ4CON, R/W, Address = 0xE020_02C0) GPJ4CON GPJ4CON[4] GPJ4CON[3] GPJ4CON[2] GPJ4CON[1] GPJ4CON[0] Bit [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = MSM_ADVN 0011 = KP_ROW[13] 0100 = SROM_ADDR_16to22[6] 0101 = MHL_DE 0110 ~ 1110 = Reserved 1111 = GPJ4_INT[4] 0000 = Input 0001 = Output 0010 = MSM_IRQn 0011 = KP_ROW[12] 0100 = CF_IOWN 0101 = MHL_VSYNC 0110 ~ 1110 = Reserved 1111 = GPJ4_INT[3] 0000 = Input 0001 = Output 0010 = MSM_Rn 0011 = KP_ROW[11] 0100 = CF_IORN 0101 = MHL_IDCK 0110 ~ 1110 = Reserved 1111 = GPJ4_INT[2] 0000 = Input 0001 = Output 0010 = MSM_WEn 0011 = KP_ROW[10] 0100 = CF_CSn[1] 0101 = MHL_HSYNC 0110 ~ 1110 = Reserved 1111 = GPJ4_INT[1] 0000 = Input 0001 = Output 0010 = MSM_CSn 0011 = KP_ROW[9] 0100 = CF_CSn[0] 0101 = MHL_D23 0110 ~ 1110 = Reserved 1111 = GPJ4_INT[0] Initial State 0000 0000 0000 0000 0000 2-93 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.24.2 Port Group GPJ4 Control Register (GPJ4DAT, R/W, Address = 0xE020_02C4) GPJ4DAT GPJ4DAT[4:0] Bit Description [4:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.24.3 Port Group GPJ4 Control Register (GPJ4PUD, R/W, Address = 0xE020_02C8) GPJ4PUD GPJ4PUD[n] Bit [2n+1:2n] n=0~4 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0155 2.2.24.4 Port Group GPJ4 Control Register (GPJ4DRV, R/W, Address = 0xE020_02CC) GPJ4DRV GPJ4DRV[n] Bit [2n+1:2n] n=0~4 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2.2.24.5 Port Group GPJ4 Control Register (GPJ4CONPDN, R/W, Address = 0xE020_02D0) GPJ4CONPDN GPJ4[n] Bit [2n+1:2n] n=0~4 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.24.6 Port Group GPJ4 Control Register (GPJ4PUDPDN, R/W, Address = 0xE020_02D4) GPJ4PUDPDN GPJ4[n] Bit [2n+1:2n] n=0~4 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-94 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.25 PORT GROUP MP0_1 CONTROL REGISTER There are six control registers, namely, MP0_1CON, MP0_1DAT, MP0_1PUD, MP0_1DRV, MP0_1CONPDN and MP0_1PUDPDN in the Port Group MP0_1 Control Registers. 2.2.25.1 Port Group MP0_1 Control Register (MP0_1CON, R/W, Address = 0xE020_02E0) MP0_1CON MP0_1CON[7] MP0_1CON[6] MP0_1CON[5] MP0_1CON[4] MP0_1CON[3] MP0_1CON[2] MP0_1CON[1] MP0_1CON[0] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = EBI_WEn 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_OEn 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[5] 0011 = NFCSn[3] 0100 = Reserved 0101 = ONANDXL_CSn[1] 0110 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[4] 0011 = NFCSn[2] 0100 = Reserved 0101 = ONANDXL_CSn[0] 0110 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[3] 0011 = NFCSn[1] 0100 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[2] 0011 = NFCSn[0] 0100 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[1] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_CSn[0] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0101 0101 0011 0011 0010 0010 2-95 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.25.2 Port Group MP0_1 Control Register (MP0_1DAT, R/W, Address = 0xE020_02E4) MP0_1DAT MP0_1DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.25.3 Port Group MP0_1 Control Register (MP0_1PUD, R/W, Address = 0xE020_02E8) MP0_1PUD MP0_1PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.25.4 Port Group MP0_1 Control Register (MP0_1DRV, R/W, Address = 0xE020_02EC) MP0_1DRV MP0_1DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.25.5 Port Group MP0_1 Control Register (MP0_1CONPDN, R/W, Address = 0xE020_02F0) MP0_1CONPDN MP0_1[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.25.6 Port Group MP0_1 Control Register (MP0_1PUDPDN, R/W, Address = 0xE020_02F4) MP0_1PUDPDN MP0_1[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-96 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.26 PORT GROUP MP0_2 CONTROL REGISTER There are six control registers, namely, MP0_2CON, MP0_2DAT, MP0_2PUD, MP0_2DRV, MP0_2CONPDN and MP0_2PUDPDN in the Port Group MP0_2 Control Registers. 2.2.26.1 Port Group MP0_2 Control Register (MP0_2CON, R/W, Address = 0xE020_0300) MP0_2CON MP0_2CON[3] MP0_2CON[2] MP0_2CON[1] MP0_2CON[0] Bit [15:12] [11:8] [7:4] [3:0] Description 0000 = Input 0001 = Output 0010 = EBI_DATA_RDn 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = SROM_WAITn 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_BEn[1] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_BEn[0] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0010 0010 2.2.26.2 Port Group MP0_2 Control Register (MP0_2DAT, R/W, Address = 0xE020_0304) MP0_2DAT MP0_2DAT[3:0] Bit Description [3:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2-97 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.26.3 Port Group MP0_2 Control Register (MP0_2PUD, R/W, Address = 0xE020_0308) MP0_2PUD MP0_2PUD[n] Bit [2n+1:2n] n=0~3 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.26.4 Port Group MP0_2 Control Register (MP0_2DRV, R/W, Address = 0xE020_030C) MP0_2DRV MP0_2DRV[n] Bit [2n+1:2n] n=0~3 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x00AA 2.2.26.5 Port Group MP0_2 Control Register (MP0_2CONPDN, R/W, Address = 0xE020_0310) MP0_2CONPDN MP0_2[n] Bit [2n+1:2n] n=0~3 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.26.6 Port Group MP0_2 Control Register (MP0_2PUDPDN, R/W, Address = 0xE020_0314) MP0_2PUDPDN MP0_2[n] Bit [2n+1:2n] n=0~3 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-98 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.27 PORT GROUP MP0_3 CONTROL REGISTER There are six control registers, namely, MP0_3CON, MP0_3DAT, MP0_3PUD, MP0_3DRV, MP0_3CONPDN and MP0_3PUDPDN in the Port Group MP0_3 Control Registers. 2.2.27.1 Port Group MP0_3 Control Register (MP0_3CON, R/W, Address = 0xE020_0320) MP0_3CON MP0_3CON[7] MP0_3CON[6] MP0_3CON[5] MP0_3CON[4] MP0_3CON[3] MP0_3CON[2] MP0_3CON[1] Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] Description 0000 = Input 0001 = Output 0010 = NF_RnB[3] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_RnB[2] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_RnB[1] 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_INT[1] 0110 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_RnB[0] 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_INT[0] 0110 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_FREn 0010 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_FWEn 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_RPn 0110 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = NF_ALE Initial State 0010 0010 0101 0101 0010 0101 0101 2-99 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT MP0_3CON MP0_3CON[0] Bit Description 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_SMCLK 0110 ~ 1110 = Reserved 1111 = Reserved [3:0] 0000 = Input 0001 = Output 0010 = NF_CLE 0011 = Reserved 0100 = Reserved 0101 = ONANDXL_ADDRVALID 0110 ~ 1110 = Reserved 1111 = Reserved Initial State 0101 2.2.27.2 Port Group MP0_3 Control Register (MP0_3DAT, R/W, Address = 0xE020_0324) MP0_3DAT MP0_3DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.27.3 Port Group MP0_3 Control Register (MP0_3PUD, R/W, Address = 0xE020_0328) MP0_3PUD MP0_3PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.27.4 Port Group MP0_3 Control Register (MP0_3DRV, R/W, Address = 0xE020_032C) MP0_3DRV MP0_3DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-100 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.27.5 Port Group MP0_3 Control Register (MP0_3CONPDN, R/W, Address = 0xE020_0330) MP0_3CONPDN MP0_3[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.27.6 Port Group MP0_3 Control Register (MP0_3PUDPDN, R/W, Address = 0xE020_0334) MP0_3PUDPDN MP0_3[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-101 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.28 PORT GROUP MP0_4 CONTROL REGISTER There are six control registers, namely, MP0_4CON, MP0_4DAT, MP0_4PUD, MP0_4DRV, MP0_4CONPDN and MP0_4PUDPDN in the Port Group MP0_4 Control Registers. 2.2.28.1 Port Group MP0_4 Control Register (MP0_4CON, R/W, Address = 0xE020_0340) MP0_4CON MP0_4CON[0] MP0_4CON[1] MP0_4CON[2] MP0_4CON[3] MP0_4CON[4] MP0_4CON[5] MP0_4CON[6] MP0_4CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] Description 0000 = Input 0001 = Output 0010 = EBI_ADDR[0] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[1] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[2] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[3] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[4] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[5] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[6] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[7] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0010 0010 0010 0010 0010 0010 2-102 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.28.2 Port Group MP0_4 Control Register (MP0_4DAT, R/W, Address = 0xE020_0344) MP0_4DAT MP0_4DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.28.3 Port Group MP0_4 Control Register (MP0_4PUD, R/W, Address = 0xE020_0348) MP0_4PUD MP0_4PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.28.4 Port Group MP0_4 Control Register (MP0_4DRV, R/W, Address = 0xE020_034C) MP0_4DRV MP0_4DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.28.5 Port Group MP0_4 Control Register (MP0_4CONPDN, R/W, Address = 0xE020_0350) MP0_4CONPDN MP0_4[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.28.6 Port Group MP0_4 Control Register (MP0_4PUDPDN, R/W, Address = 0xE020_0354) MP0_4PUDPDN MP0_4[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-103 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.29 PORT GROUP MP0_5 CONTROL REGISTER There are six control registers, namely, MP0_5CON, MP0_5DAT, MP0_5PUD, MP0_5DRV, MP0_5CONPDN and MP0_5PUDPDN in the Port Group MP0_5 Control Registers. 2.2.29.1 Port Group MP0_5 Control Register (MP0_5CON, R/W, Address = 0xE020_0360) MP0_5CON MP0_5CON[0] MP0_5CON[1] MP0_5CON[2] MP0_5CON[3] MP0_5CON[4] MP0_5CON[5] MP0_5CON[6] MP0_5CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] Description 0000 = Input 0001 = Output 0010 = EBI_ADDR[8] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[9] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[10] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[11] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[12] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[13] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[14] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_ADDR[15] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0010 0010 0010 0010 0010 0010 2-104 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.29.2 Port Group MP0_5 Control Register (MP0_5DAT, R/W, Address = 0xE020_0364) MP0_5DAT MP0_5DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.29.3 Port Group MP0_5 Control Register (MP0_5PUD, R/W, Address = 0xE020_0368) MP0_5PUD MP0_5PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.29.4 Port Group MP0_5 Control Register (MP0_5DRV, R/W, Address = 0xE020_036C) MP0_5DRV MP0_5DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.29.5 Port Group MP0_5 Control Register (MP0_5CONPDN, R/W, Address = 0xE020_0370) MP0_5CONPDN MP0_5[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.29.6 Port Group MP0_5 Control Register (MP0_5PUDPDN, R/W, Address = 0xE020_0374) MP0_5PUDPDN MP0_5[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-105 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.30 PORT GROUP MP0_6 CONTROL REGISTER There are six control registers, namely, MP0_6CON, MP0_6DAT, MP0_6PUD, MP0_6DRV, MP0_6CONPDN and MP0_6PUDPDN in the Port Group MP0_6 Control Registers. 2.2.30.1 Port Group MP0_6 Control Register (MP0_6CON, R/W, Address = 0xE020_0380) MP0_6CON MP0_6CON[0] MP0_6CON[1] MP0_6CON[2] MP0_6CON[3] MP0_6CON[4] MP0_6CON[5] MP0_6CON[6] MP0_6CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] Description 0000 = Input 0001 = Output 0010 = EBI_DATA[0] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[1] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[2] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[3] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[4] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[5] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[6] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[7] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0010 0010 0010 0010 0010 0010 2-106 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.30.2 Port Group MP0_6 Control Register (MP0_6DAT, R/W, Address = 0xE020_0384) MP0_6DAT MP0_6DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.30.3 Port Group MP0_6 Control Register (MP0_6PUD, R/W, Address = 0xE020_0388) MP0_6PUD MP0_6PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.30.4 Port Group MP0_6 Control Register (MP0_6DRV, S/W, Address = 0xE020_038C) MP0_6DRV MP0_6DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.30.5 Port Group MP0_6 Control Register (MP0_6CONPDN, S/W, Address = 0xE020_0390) MP0_6CONPDN MP0_6[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.30.6 Port Group MP0_6 Control Register (MP0_6PUDPDN, S/W, Address = 0xE020_0394) MP0_6PUDPDN MP0_6[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-107 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.31 PORT GROUP MP0_7 CONTROL REGISTER There are six control registers, namely, MP0_7CON, MP0_7DAT, MP0_7PUD, MP0_7DRV, MP0_7CONPDN and MP0_7PUDPDN in the Port Group MP0_7 Control Registers. 2.2.31.1 Port Group MP0_7 Control Register (MP0_7CON, R/W, Address = 0xE020_03A0) MP0_7CON MP0_7CON[0] MP0_7CON[1] MP0_7CON[2] MP0_7CON[3] MP0_7CON[4] MP0_7CON[5] MP0_7CON[6] MP0_7CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] Description 0000 = Input 0001 = Output 0010 = EBI_DATA[8] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[9] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[10] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[11] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[12] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[13] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[14] 0011 ~ 1110 = Reserved 1111 = Reserved 0000 = Input 0001 = Output 0010 = EBI_DATA[15] 0011 ~ 1110 = Reserved 1111 = Reserved Initial State 0010 0010 0010 0010 0010 0010 0010 0010 2-108 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.31.2 Port Group MP0_7 Control Register (MP0_7DAT, R/W, Address = 0xE020_03A4) MP0_7DAT MP0_7DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.31.3 Port Group MP0_7 Control Register (MP0_7PUD, R/W, Address = 0xE020_03A8) MP0_7PUD MP0_7PUD[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x0000 2.2.31.4 Port Group MP0_7 Control Register (MP0_7DRV, R/W, Address = 0xE020_03AC) MP0_7DRV MP0_7DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.31.5 Port Group MP0_7 Control Register (MP0_7CONPDN, R/W, Address = 0xE020_03B0) MP0_7CONPDN MP0_7[n] Bit [2n+1:2n] n=0~7 00 = Output 0 01 = Output 1 10 = Input 11 = Previous state Description Initial State 0x00 2.2.31.6 Port Group MP0_7 Control Register (MP0_7PUDPDN, R/W, Address = 0xE020_03B4) MP0_7PUDPDN MP0_7[n] Bit [2n+1:2n] n=0~7 Description 00 = Pull-up/down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x00 2-109 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.32 PORT GROUP MP1_0 CONTROL REGISTER There are six control registers, namely, MP1_0CON, MP1_0DAT, MP1_0PUD, MP1_0DRV, MP1_0CONPDN and MP1_0PUDPDN in the Port Group MP1_0 Control Registers. • MP1_0CON, R/W, Address = 0xE020_03C0 • MP1_0DAT, R/W, Address = 0xE020_03C4 • MP1_0PUD, R/W, Address = 0xE020_03C8 • MP1_0DRV, R/W, Address = 0xE020_03CC • MP1_0CONPDN, R/W, Address = 0xE020_03D0 • MP1_0PUDPDN, R/W, Address = 0xE020_03D4 MP1_0DRV MP1_0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.33 PORT GROUP MP1_1 CONTROL REGISTER There are six control registers, namely, MP1_1CON, MP1_1DAT, MP1_1PUD, MP1_1DRV, MP1_1CONPDN and MP1_1PUDPDN in the Port Group MP1_1 Control Registers. • MP1_1CON, R/W, Address = 0xE020_03E0 • MP1_1DAT, R/W, Address = 0xE020_03E4 • MP1_1PUD, R/W, Address = 0xE020_03E8 • MP1_1DRV, R/W, Address = 0xE020_03EC • MP1_1CONPDN, R/W, Address = 0xE020_03F0 • MP1_1PUDPDN, R/W, Address = 0xE020_03F4 MP1_1DRV MP1_1DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-110 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.34 PORT GROUP MP1_2 CONTROL REGISTER There are six control registers, namely, MP1_2CON, MP1_2DAT, MP1_2PUD, MP1_2DRV, MP1_2CONPDN and MP1_2PUDPDN in the Port Group MP1_2 Control Registers. • MP1_2CON, R/W, Address = 0xE020_0400 • MP1_2DAT, R/W, Address = 0xE020_0404 • MP1_2PUD, R/W, Address = 0xE020_0408 • MP1_2DRV, R/W, Address = 0xE020_040C • MP1_2CONPDN, R/W, Address = 0xE020_0410 • MP1_2PUDPDN, R/W, Address = 0xE020_0414 MP1_2DRV MP1_2DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.35 PORT GROUP MP1_3 CONTROL REGISTER There are six control registers, namely, MP1_3CON, MP1_3DAT, MP1_3PUD, MP1_3DRV, MP1_3CONPDN and MP1_3PUDPDN in the Port Group MP1_3 Control Registers. • MP1_3CON, R/W, Address = 0xE020_0420 • MP1_3DAT, R/W, Address = 0xE020_0424 • MP1_3PUD, R/W, Address = 0xE020_0428 • MP1_3DRV, R/W, Address = 0xE020_042C • MP1_3CONPDN, R/W, Address = 0xE020_0430 • MP1_3PUDPDN, R/W, Address = 0xE020_0434 MP1_3DRV MP1_3DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-111 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.36 PORT GROUP MP1_4 CONTROL REGISTER There are six control registers, namely, MP1_4CON, MP1_4DAT, MP1_4PUD, MP1_4DRV, MP1_4CONPDN and MP1_4PUDPDN in the Port Group MP1_4 Control Registers. • MP1_4CON, R/W, Address = 0xE020_0440 • MP1_4DAT, R/W, Address = 0xE020_0444 • MP1_4PUD, R/W, Address = 0xE020_0448 • MP1_4DRV, R/W, Address = 0xE020_044C • MP1_4CONPDN, R/W, Address = 0xE020_0450 • MP1_4PUDPDN, R/W, Address = 0xE020_0454 MP1_4DRV MP1_4DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.37 PORT GROUP MP1_5 CONTROL REGISTER There are six control registers, namely, MP1_5CON, MP1_5DAT, MP1_5PUD, MP1_5DRV, MP1_5CONPDN and MP1_5PUDPDN in the Port Group MP1_5 Control Registers. • MP1_5CON, R/W, Address = 0xE020_0460 • MP1_5DAT, R/W, Address = 0xE020_0464 • MP1_5PUD, R/W, Address = 0xE020_0468 • MP1_5DRV, R/W, Address = 0xE020_046C • MP1_5CONPDN, R/W, Address = 0xE020_0470 • MP1_5PUDPDN, R/W, Address = 0xE020_0474 MP1_5DRV MP1_5DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-112 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.38 PORT GROUP MP1_6 CONTROL REGISTER There are six control registers, namely, MP1_6CON, MP1_6DAT, MP1_6PUD, MP1_6DRV, MP1_6CONPDN and MP1_6PUDPDN in the Port Group MP1_6 Control Registers. • MP1_6CON, R/W, Address = 0xE020_0480 • MP1_6DAT, R/W, Address = 0xE020_0484 • MP1_6PUD, R/W, Address = 0xE020_0488 • MP1_6DRV, R/W, Address = 0xE020_048C • MP1_6CONPDN, R/W, Address = 0xE020_0490 • MP1_6PUDPDN, R/W, Address = 0xE020_0494 MP1_6DRV MP1_6DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.39 PORT GROUP MP1_7 CONTROL REGISTER There are six control registers, namely, MP1_7CON, MP1_7DAT, MP1_7PUD, MP1_7DRV, MP1_7CONPDN and MP1_7PUDPDN in the Port Group MP1_7 Control Registers. • MP1_7CON, R/W, Address = 0xE020_04A0 • MP1_7DAT, R/W, Address = 0xE020_04A4 • MP1_7PUD, R/W, Address = 0xE020_04A8 • MP1_7DRV, R/W, Address = 0xE020_04AC • MP1_7CONPDN, R/W, Address = 0xE020_04B0 • MP1_7PUDPDN, R/W, Address = 0xE020_04B4 MP1_7DRV MP1_7DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-113 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.40 PORT GROUP MP1_8 CONTROL REGISTER There are six control registers, namely, MP1_8CON, MP1_8DAT, MP1_8PUD, MP1_8DRV, MP1_8CONPDN and MP1_8PUDPDN in the Port Group MP1_8 Control Registers. • MP1_8CON, R/W, Address = 0xE020_04C0 • MP1_8DAT, R/W, Address = 0xE020_04C4 • MP1_8PUD, R/W, Address = 0xE020_04C8 • MP1_8DRV, R/W, Address = 0xE020_04CC • MP1_8CONPDN, R/W, Address = 0xE020_04D0 • MP1_8PUDPDN, R/W, Address = 0xE020_04D4 MP1_8DRV MP1_8DRV[n] Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x2AAA 2.2.41 PORT GROUP MP2_0 CONTROL REGISTER There are six control registers, namely, MP2_0CON, MP2_0DAT, MP2_0PUD, MP2_0DRV, MP2_0CONPDN and MP2_0PUDPDN in the Port Group MP2_0 Control Registers. • MP2_0CON, R/W, Address = 0xE020_04E0 • MP2_0DAT, R/W, Address = 0xE020_04E4 • MP2_0PUD, R/W, Address = 0xE020_04E8 • MP2_0DRV, R/W, Address = 0xE020_04EC • MP2_0CONPDN, R/W, Address = 0xE020_04F0 • MP2_0PUDPDN, R/W, Address = 0xE020_04F4 MP2_0DRV MP2_0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-114 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.42 PORT GROUP MP2_1 CONTROL REGISTER There are six control registers, namely, MP2_1CON, MP2_1DAT, MP2_1PUD, MP2_1DRV, MP2_1CONPDN and MP2_1PUDPDN in the Port Group MP2_1 Control Registers. • MP2_1CON, R/W, Address = 0xE020_0500 • MP2_1DAT, R/W, Address = 0xE020_0504 • MP2_1PUD, R/W, Address = 0xE020_0508 • MP2_1DRV, R/W, Address = 0xE020_050C • MP2_1CONPDN, R/W, Address = 0xE020_0510 • MP2_1PUDPDN, R/W, Address = 0xE020_0514 MP2_1DRV MP2_1DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.43 PORT GROUP MP2_2 CONTROL REGISTER There are six control registers, namely, MP2_2CON, MP2_2DAT, MP2_2PUD, MP2_2DRV, MP2_2CONPDN and MP2_2PUDPDN in the Port Group MP2_2 Control Registers. • MP2_2CON, R/W, Address = 0xE020_0520 • MP2_2DAT, R/W, Address = 0xE020_0524 • MP2_2PUD, R/W, Address = 0xE020_0528 • MP2_2DRV, R/W, Address = 0xE020_052C • MP2_2CONPDN, R/W, Address = 0xE020_0530 • MP2_2PUDPDN, R/W, Address = 0xE020_0534 MP2_2DRV MP2_2DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-115 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.44 PORT GROUP MP2_3 CONTROL REGISTER There are six control registers, namely, MP2_3CON, MP2_3DAT, MP2_3PUD, MP2_3DRV, MP2_3CONPDN and MP2_3PUDPDN in the Port Group MP2_3 Control Registers. • MP2_3CON, R/W, Address = 0xE020_0540 • MP2_3DAT, R/W, Address = 0xE020_0544 • MP2_3PUD, R/W, Address = 0xE020_0548 • MP2_3DRV, R/W, Address = 0xE020_054C • MP2_3CONPDN, R/W, Address = 0xE020_0550 • MP2_3PUDPDN, R/W, Address = 0xE020_0554 MP2_3DRV MP2_3DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.45 PORT GROUP MP2_4 CONTROL REGISTER There are six control registers, namely, MP2_4CON, MP2_4DAT, MP2_4PUD, MP2_4DRV, MP2_4CONPDN and MP2_4PUDPDN in the Port Group MP2_4 Control Registers. • MP2_4CON, R/W, Address = 0xE020_0560 • MP2_4DAT, R/W, Address = 0xE020_0564 • MP2_4PUD, R/W, Address = 0xE020_0568 • MP2_4DRV, R/W, Address = 0xE020_056C • MP2_4CONPDN, R/W, Address = 0xE020_0570 • MP2_4PUDPDN, R/W, Address = 0xE020_0574 MP2_4DRV MP2_4DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-116 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.46 PORT GROUP MP2_5 CONTROL REGISTER There are six control registers, namely, MP2_5CON, MP2_5DAT, MP2_5PUD, MP2_5DRV, MP2_5CONPDN and MP2_5PUDPDN in the Port Group MP2_5 Control Registers. • MP2_5CON, R/W, Address = 0xE020_0580 • MP2_5DAT, R/W, Address = 0xE020_0584 • MP2_5PUD, R/W, Address = 0xE020_0588 • MP2_5DRV, R/W, Address = 0xE020_058C • MP2_5CONPDN, R/W, Address = 0xE020_0590 • MP2_5PUDPDN, R/W, Address = 0xE020_0594 MP2_5DRV MP2_5DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.47 PORT GROUP MP2_6 CONTROL REGISTER There are six control registers, namely, MP2_6CON, MP2_6DAT, MP2_6PUD, MP2_6DRV, MP2_6CONPDN and MP2_6PUDPDN in the Port Group MP2_6 Control Registers. • MP2_6CON, R/W, Address = 0xE020_05A0 • MP2_6DAT, R/W, Address = 0xE020_05A4 • MP2_6PUD, R/W, Address = 0xE020_05A8 • MP2_6DRV, R/W, Address = 0xE020_05AC • MP2_6CONPDN, R/W, Address = 0xE020_05B0 • MP2_6PUDPDN, R/W, Address = 0xE020_05B4 MP2_6DRV MP2_6DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2-117 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.48 PORT GROUP MP2_7 CONTROL REGISTER There are six control registers, namely, MP2_7CON, MP2_7DAT, MP2_7PUD, MP2_7DRV, MP2_7CONPDN and MP2_7PUDPDN in the Port Group MP2_7 Control Registers. • MP2_7CON, R/W, Address = 0xE020_05C0 • MP2_7DAT, R/W, Address = 0xE020_05C4 • MP2_7PUD, R/W, Address = 0xE020_05C8 • MP2_7DRV, R/W, Address = 0xE020_05CC • MP2_7CONPDN, R/W, Address = 0xE020_05D0 • MP2_7PUDPDN, R/W, Address = 0xE020_05D4 MP2_7DRV MP2_7DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0xAAAA 2.2.49 PORT GROUP MP2_8 CONTROL REGISTER There are six control registers, namely, MP2_8CON, MP2_8DAT, MP2_8PUD, MP2_8DRV, MP2_8CONPDN and MP2_8PUDPDN in the Port Group MP2_8 Control Registers. • MP2_8CON, R/W, Address = 0xE020_05E0 • MP2_8DAT, R/W, Address = 0xE020_05E4 • MP2_8PUD, R/W, Address = 0xE020_05E8 • MP2_8DRV, R/W, Address = 0xE020_05EC • MP2_8CONPDN, R/W, Address = 0xE020_05F0 • MP2_8PUDPDN, R/W, Address = 0xE020_05F4 MP2_8DRV MP2_8DRV[n Bit [2n+1:2n] n=0~6 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x2AAA 2-118 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.50 PORT GROUP ETC0 CONTROL REGISTER There are two control registers, namely, ETC0PUD and ETC0DRV. ETC0 ports are dedicated as shown in table below: ETC0 ETC0[0] ETC0[1] ETC0[2] ETC0[3] ETC0[4] ETC0[5] Pin Name XjTRSTn XjTMS XjTCK XjTDI XjTDI XjDBGSEL Description JTAG TAP Controller Reset JTAG TAP Controller Mode Select JTAG TAP Controller Clock JTAG TAP Controller Data Input JTAG TAP Controller Data Input JTAG selection(0: CORTEXA8 Core JTAG, 1: Peripherals JTAG) 2.2.50.1 Port Group ETC0 Control Register (ETC0PUD, R/W, Address = 0xE020_0608) ETC0PUD ETC0PUD ETC0PUD[m] Bit [2n+1:2n] n=4~5 [2m+1:2m] m=0~3 Description 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Reserved (fixed) ETC0PUD[0] : Pull-down ETC0PUD[1] : Pull-up ETC0PUD[2] : Pull-down ETC0PUD[3] : Pull-up 2.2.50.2 Port Group ETC0 Control Register (ETC0DRV, R/W, Address = 0xE020_060C) ETC0DRV ETC0DRV[n] Bit [2n+1:2n] n=0~5 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0 0 0 0 0 0 Initial State 0x00 0x00 Initial State 0x0000 2-119 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.51 PORT GROUP ETC1 CONTROL REGISTER There are two control registers, namely, ETC1PUD and ETC1DRV. ETC1 ports are dedicated as shown in table below: ETC1 ETC1[0] ETC1[1] ETC1[2] ETC1[3] ETC1[4] ETC1[5] Pin Name XOM[0] XOM[1] XOM[2] XOM[3] XOM[4] XOM[5] Description Operating Mode control signal 0 Operating Mode control signal 1 Operating Mode control signal 2 Operating Mode control signal 3 Operating Mode control signal 4 Operating Mode control signal 5 ETC1[6] ETC1[7] XDDR2_SEL XPWRRGTON Selection DDR type (LPDDR1/2 or DDR2) Power Regulator enable 2.2.51.1 Port Group ETC1 Control Register (ETC1PUD, R/W, Address = 0xE020_0628) ETC1PUD ETC1PUD[n] ETC1PUD[6] ETC1PUD[7] Bit [2n+1:2n] n=0~5 [13:12] [15:14] Description Reserved(fixed) ETC1PUD[0] : Disable ETC1PUD[1] : Disable ETC1PUD[2] : Disable ETC1PUD[3] : Disable ETC1PUD[4] : Disable ETC1PUD[5] : Disable 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Reserved (fixed) ETC1PUD[7] : Disable Initial State 0 0 0 0 0 0 0 0 Initial State 0x000 0x0 0x0 2-120 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.51.2 Port Group ETC1 Control Register (ETC1DRV, R/W, Address = 0xE020_062C) ETC1DRV ETC1DRV[n] ETC1DRV[6] ETC1DRV[7] Bit [2n+1:2n] n=0~5 [13:12] [15:14] Description Reserved(fixed) ETC1DRV[0] : 01 (3x) ETC1DRV[1] : 01 (3x) ETC1DRV[2] : 01 (3x) ETC1DRV[3] : 01 (3x) ETC1DRV[4] : 01 (3x) ETC1DRV[5] : 01 (3x) 00 = 1x 10 = 2x 01 = 3x 11 = 4x Reserved(fixed) ETC1DRV[7] : 11 (4x) Initial State - 0x0 - 2-121 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.52 PORT GROUP ETC2 CONTROL REGISTER There are two control registers, namely, ETC2PUD and ETC2DRV. ETC2 ports are dedicated as shown in table below: ETC2 ETC2[0] ETC2[1] ETC2[2] ETC2[3] ETC2[4] ETC2[5] ETC2[6] ETC2[7] Pin Name XnRESET CLKOUT XnRSTOUT XnWRESET RTC_CLKOUT Description System Reset Clock out signal For External device reset control System Warm Reset RTC Clock out XuotgDRVVBUS USB OTG charge pump enable XuhostPWREN USB HOST charge pump enable XuhostOVERCUR USB HOST oevercurrent flag 2.2.52.1 Port Group ETC2 Control Register (ETC2PUD, R/W, Address = 0xE020_0648) ETC2PUD ETC2PUD[n] ETC2PUD[m] Bit [2n+1:2n] n=0~4 [2m+1:2m] m=5~7 Description Reserved(fixed) ETC2PUD[0] : Disable ETC2PUD[1] : Disable ETC2PUD[2] : Disable ETC2PUD[3] : Pull-up ETC2PUD[4] : Disable 00 = Pull-up/ down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0 0 0 0 0 0 0 0 Initial State 0x00 0x00 2-122 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.52.2 Port Group ETC2 Control Register (ETC2DRV, R/W, Address = 0xE020_064C) ETC2DRV ETC2DRV[0] ETC2DRV[1] ETC2DRV[n] ETC2DRV[m] Bit [1:0] [3:2] [2n+1:2n] n=2~4 [2m+1:2m] m=7~5 Description Reserved(fixed) ETC2DRV[0] : 01 (3x) 00 = 1x 10 = 2x 01 = 3x 11 = 4x Reserved(fixed) ETC2DRV[2] : 11 (4x) ETC2DRV[3] : 01 (3x) ETC2DRV[4] : 10 (2x) 00 = 1x 10 = 2x 01 = 3x 11 = 4x Initial State 00 - 0x0 2-123 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.53 PORT GROUP ETC3 IS RESERVED 2.2.54 PORT GROUP ETC4 There is no registers. ETC4 ports are dedicated as shown in table below: ETC4 ETC4[0] ETC4[1] ETC4[2] ETC4[3] ETC4[4] ETC4[5] Pin Name XrtcXTI XrtcXTO XXTI XXTO XusbXTI XusbXTO Description 32 KHz crystal input for RTC 32 KHz crystal output for RTC Crystal input for internal OSC circuit Crystal output for internal OSC circuit Crystal input for internal USB circuit Crystal output for internal USB circuit Initial State 0 0 0 0 0 0 2-124 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55 GPIO INTERRUPT CONTROL REGISTERS GPIO Interrupt comprise of 22 groups, namely, GPA0, GPA1, GPB, GPC0, GPC1, GPD0, GPD1, GPE0, GPE1, GPF0, GPF1, GPF2, GPF3, GPG0, GPG1, GPG2, GPG3, GPJ0, GPJ1, GPJ2, GPJ3 and GPJ4. In interrupt function, it is important to understand the filter operation. S5PV210 uses two types of filters to detect interrupt, namely, delay filter and digital filter. Delay filter uses delay cell. If clock is not serviced, select the delay filter in alive area. Delay filter enables to detect interrupt after 35ns from the time when the interrupt occurs. Digital filter means that all interrupt counts are based on clock. Therefore, this filter can be used in clock-supported area.(both off area and alive area) When you select digital filter set the filtering width. Digital filter can detect interrupt per every clock count as many as filtering width. Filtering width is 6-bit in alive area and is 7-bit in off area. When you use interrupt function, set either delay or digital filter enabled in order to detect interrupt. If filter is disabled, there is strong probability that system detects all interrupt from successive interrupts (Some interrupt detection will be missed). To detect all interrupts stably, you had better set filter enable. GPIO Interrupt cannot use for wake-up source. For wake-up interrupt source, you can use External interrupt. The following table shows the list of GPIO Interrupt control registers. Register GPA0_INT_CON GPA1_INT_CON GPB_INT_CON GPC0_INT_CON GPC1_INT_CON GPD0_INT_CON GPD1_INT_CON GPE0_INT_CON Address 0xE020_0700 0xE020_0704 0xE020_0708 0xE020_070C 0xE020_0710 0xE020_0714 0xE020_0718 0xE020_071C R/W Description R/W GPIO Interrupt GPA0_INT Configuration Register R/W GPIO Interrupt GPA1_INT Configuration Register R/W GPIO Interrupt GPB_INT Configuration Register R/W GPIO Interrupt GPC0_INT Configuration Register R/W GPIO Interrupt GPC1_INT Configuration Register R/W GPIO Interrupt GPD0_INT Configuration Register R/W GPIO Interrupt GPD1_INT Configuration Register R/W GPIO Interrupt GPE0_INT Configuration Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-125 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPE1_INT_CON GPF0_INT_CON GPF1_INT_CON GPF2_INT_CON GPF3_INT_CON GPG0_INT_CON GPG1_INT_CON GPG2_INT_CON GPG3_INT_CON GPJ0_INT_CON GPJ1_INT_CON GPJ2_INT_CON GPJ3_INT_CON GPJ4_INT_CON GPA0_INT_FLTCON0 GPA0_INT_FLTCON1 GPA1_INT_FLTCON0 GPA1_INT_FLTCON1 GPB_INT_FLTCON0 GPB_INT_FLTCON1 GPC0_INT_FLTCON0 Address 0xE020_0720 0xE020_0724 0xE020_0728 0xE020_072C 0xE020_0730 0xE020_0734 0xE020_0738 0xE020_073C 0xE020_0740 0xE020_0744 0xE020_0748 0xE020_074C 0xE020_0750 0xE020_0754 0xE020_0800 0xE020_0804 0xE020_0808 0xE020_080C 0xE020_0810 0xE020_0814 0xE020_0818 R/W Register Description R/W GPIO Interrupt GPE1_INT Configuration Register R/W GPIO Interrupt GPF0_INT Configuration Register R/W GPIO Interrupt GPF1_INT Configuration Register R/W GPIO Interrupt GPF2_INT Configuration Register R/W GPIO Interrupt GPF3_INT Configuration Register R/W GPIO Interrupt GPG0_INT Configuration Register R/W GPIO Interrupt GPG1_INT Configuration Register R/W GPIO Interrupt GPG2_INT Configuration Register R/W GPIO Interrupt GPG3_INT Configuration Register R/W GPIO Interrupt GPJ0_INT Configuration Register R/W GPIO Interrupt GPJ1_INT Configuration Register R/W GPIO Interrupt GPJ2_INT Configuration Register R/W GPIO Interrupt GPJ3_INT Configuration Register R/W GPIO Interrupt GPJ4_INT Configuration Register R/W GPIO Interrupt GPA0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPA0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPA1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPA1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPB_INT Filter Configuration Register 0 R/W GPIO Interrupt GPB_INT Filter Configuration Register 1 R/W GPIO Interrupt GPC0_INT Filter Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-126 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPC0_INT_FLTCON1 GPC1_INT_FLTCON0 GPC1_INT_FLTCON1 GPD0_INT_FLTCON0 GPD0_INT_FLTCON1 GPD1_INT_FLTCON0 GPD1_INT_FLTCON1 GPE0_INT_FLTCON0 GPE0_INT_FLTCON1 GPE1_INT_FLTCON0 GPE1_INT_FLTCON1 GPF0_INT_FLTCON0 GPF0_INT_FLTCON1 GPF1_INT_FLTCON0 GPF1_INT_FLTCON1 GPF2_INT_FLTCON0 GPF2_INT_FLTCON1 GPF3_INT_FLTCON0 GPF3_INT_FLTCON1 GPG0_INT_FLTCON0 GPG0_INT_FLTCON1 Address 0xE020_081C 0xE020_0820 0xE020_0824 0xE020_0828 0xE020_082C 0xE020_0830 0xE020_0834 0xE020_0838 0xE020_083C 0xE020_0840 0xE020_0844 0xE020_0848 0xE020_084C 0xE020_0850 0xE020_0854 0xE020_0858 0xE020_085C 0xE020_0860 0xE020_0864 0xE020_0868 0xE020_086C R/W Description Configuration Register 0 R/W GPIO Interrupt GPC0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPC1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPC1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPD0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPD0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPD1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPD1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPE0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPE0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPE1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPE1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPF0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPF0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPF1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPF1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPF2_INT Filter Configuration Register 0 R/W GPIO Interrupt GPF2_INT Filter Configuration Register 1 R/W GPIO Interrupt GPF3_INT Filter Configuration Register 0 R/W GPIO Interrupt GPF3_INT Filter Configuration Register 1 R/W GPIO Interrupt GPG0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPG0_INT Filter Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-127 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPG1_INT_FLTCON0 GPG1_INT_FLTCON1 GPG2_INT_FLTCON0 GPG2_INT_FLTCON1 GPG3_INT_FLTCON0 GPG3_INT_FLTCON1 GPJ0_INT_FLTCON0 GPJ0_INT_FLTCON1 GPJ1_INT_FLTCON0 GPJ1_INT_FLTCON1 GPJ2_INT_FLTCON0 GPJ2_INT_FLTCON1 GPJ3_INT_FLTCON0 GPJ3_INT_FLTCON1 GPJ4_INT_FLTCON0 GPJ4_INT_FLTCON1 GPA0_INT_MASK GPA1_INT_MASK GPB_INT_MASK GPC0_INT_MASK GPC1_INT_MASK GPD0_INT_MASK GPD1_INT_MASK GPE0_INT_MASK Address 0xE020_0870 0xE020_0874 0xE020_0878 0xE020_087C 0xE020_0880 0xE020_0884 0xE020_0888 0xE020_088C 0xE020_0890 0xE020_0894 0xE020_0898 0xE020_089C 0xE020_08A0 0xE020_08A4 0xE020_08A8 0xE020_08AC 0xE020_0900 0xE020_0904 0xE020_0908 0xE020_090C 0xE020_0910 0xE020_0914 0xE020_0918 0xE020_091C R/W Description Configuration Register 1 R/W GPIO Interrupt GPG1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPG1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPG2_INT Filter Configuration Register 0 R/W GPIO Interrupt GPG2_INT Filter Configuration Register 1 R/W GPIO Interrupt GPG3_INT Filter Configuration Register 0 R/W GPIO Interrupt GPG3_INT Filter Configuration Register 1 R/W GPIO Interrupt GPJ0_INT Filter Configuration Register 0 R/W GPIO Interrupt GPJ0_INT Filter Configuration Register 1 R/W GPIO Interrupt GPJ1_INT Filter Configuration Register 0 R/W GPIO Interrupt GPJ1_INT Filter Configuration Register 1 R/W GPIO Interrupt GPJ2_INT Filter Configuration Register 0 R/W GPIO Interrupt GPJ2_INT Filter Configuration Register 1 R/W GPIO Interrupt GPJ3_INT Filter Configuration Register 0 R/W GPIO Interrupt GPJ3_INT Filter Configuration Register 1 R/W GPIO Interrupt GPJ4_INT Filter Configuration Register 0 R/W GPIO Interrupt GPJ4_INT Filter Configuration Register 1 R/W GPIO Interrupt GPA0_INT Mask Register R/W GPIO Interrupt GPA1_INT Mask Register R/W GPIO Interrupt GPB_INT Mask Register R/W GPIO Interrupt GPC0_INT Mask Register R/W GPIO Interrupt GPC1_INT Mask Register R/W GPIO Interrupt GPD0_INT Mask Register R/W GPIO Interrupt GPD1_INT Mask Register R/W GPIO Interrupt GPE0_INT Mask Register Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x000000FF 0x0000000F 0x000000FF 0x0000001F 0x0000001F 0x0000000F 0x0000003F 0x000000FF 2-128 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPE1_INT_MASK GPF0_INT_MASK GPF1_INT_MASK GPF2_INT_MASK GPF3_INT_MASK GPG0_INT_MASK GPG1_INT_MASK GPG2_INT_MASK GPG3_INT_MASK GPJ0_INT_MASK GPJ1_INT_MASK GPJ2_INT_MASK GPJ3_INT_MASK GPJ4_INT_MASK GPA0_INT_PEND GPA1_INT_PEND GPB_INT_PEND GPC0_INT_PEND GPC1_INT_PEND GPD0_INT_PEND GPD1_INT_PEND GPE0_INT_PEND GPE1_INT_PEND GPF0_INT_PEND GPF1_INT_PEND GPF2_INT_PEND GPF3_INT_PEND Address 0xE020_0920 0xE020_0924 0xE020_0928 0xE020_092C 0xE020_0930 0xE020_0934 0xE020_0938 0xE020_093C 0xE020_0940 0xE020_0944 0xE020_0948 0xE020_094C 0xE020_0950 0xE020_0954 0xE020_0A00 0xE020_0A04 0xE020_0A08 0xE020_0A0C 0xE020_0A10 0xE020_0A14 0xE020_0A18 0xE020_0A1C 0xE020_0A20 0xE020_0A24 0xE020_0A28 0xE020_0A2C 0xE020_0A30 R/W Description R/W GPIO Interrupt GPE1_INT Mask Register R/W GPIO Interrupt GPF0_INT Mask Register R/W GPIO Interrupt GPF1_INT Mask Register R/W GPIO Interrupt GPF2_INT Mask Register R/W GPIO Interrupt GPF3_INT Mask Register R/W GPIO Interrupt GPG0_INT Mask Register R/W GPIO Interrupt GPG1_INT Mask Register R/W GPIO Interrupt GPG2_INT Mask Register R/W GPIO Interrupt GPG3_INT Mask Register R/W GPIO Interrupt GPJ0_INT Mask Register R/W GPIO Interrupt GPJ1_INT Mask Register R/W GPIO Interrupt GPJ2_INT Mask Register R/W GPIO Interrupt GPJ3_INT Mask Register R/W GPIO Interrupt GPJ4_INT Mask Register R/W GPIO Interrupt GPA0_INT Pending Register R/W GPIO Interrupt GPA1_INT Pending Register R/W GPIO Interrupt GPB_INT Pending Register R/W GPIO Interrupt GPC0_INT Pending Register R/W GPIO Interrupt GPC1_INT Pending Register R/W GPIO Interrupt GPD0_INT Pending Register R/W GPIO Interrupt GPD1_INT Pending Register R/W GPIO Interrupt GPE0_INT Pending Register R/W GPIO Interrupt GPE1_INT Pending Register R/W GPIO Interrupt GPF0_INT Pending Register R/W GPIO Interrupt GPF1_INT Pending Register R/W GPIO Interrupt GPF2_INT Pending Register R/W GPIO Interrupt GPF3_INT Pending Register Reset Value 0x0000001F 0x000000FF 0x000000FF 0x000000FF 0x0000003F 0x0000007F 0x0000007F 0x0000007F 0x0000007F 0x000000FF 0x0000003F 0x000000FF 0x000000FF 0x0000001F 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 2-129 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPG0_INT_PEND Address 0xE020_0A34 GPG1_INT_PEND 0xE020_0A38 GPG2_INT_PEND 0xE020_0A3C GPG3_INT_PEND 0xE020_0A40 GPJ0_INT_PEND 0xE020_0A44 GPJ1_INT_PEND 0xE020_0A48 GPJ2_INT_PEND 0xE020_0A4C GPJ3_INT_PEND 0xE020_0A50 GPJ4_INT_PEND 0xE020_0A54 GPIO_INT_GRPPRI 0xE020_0B00 GPIO_INT_PRIORITY GPIO_INT_SERVICE GPIO_INT_SERVICE_P END GPIO_INT_GRPFIXPRI 0xE020_0B04 0xE020_0B08 0xE020_0B0C 0xE020_0B10 GPA0_INT_FIXPRI 0xE020_0B14 GPA1_INT_FIXPRI 0xE020_0B18 GPB_INT_FIXPRI 0xE020_0B1C GPC0_INT_FIXPRI 0xE020_0B20 GPC1_INT_FIXPRI 0xE020_0B24 GPD0_INT_FIXPRI 0xE020_0B28 GPD1_INT_FIXPRI 0xE020_0B2C GPE0_INT_FIXPRI 0xE020_0B30 R/W Description R/W GPIO Interrupt GPG0_INT Pending Register R/W GPIO Interrupt GPG1_INT Pending Register R/W GPIO Interrupt GPG2_INT Pending Register R/W GPIO Interrupt GPG3_INT Pending Register R/W GPIO Interrupt GPJ0_INT Pending Register R/W GPIO Interrupt GPJ1_INT Pending Register R/W GPIO Interrupt GPJ2_INT Pending Register R/W GPIO Interrupt GPJ3_INT Pending Register R/W GPIO Interrupt GPJ4_INT Pending Register R/W GPIO Interrupt Group Priority Control Register R/W GPIO Interrupt Priority Control Register R Current Service Register R Current Service Pending Register R/W GPIO Interrupt Group Fixed Priority Control Register R/W GPIO Interrupt 1 Fixed Priority Control Register R/W GPIO Interrupt 2 Fixed Priority Control Register R/W GPIO Interrupt 3 Fixed Priority Control Register R/W GPIO Interrupt 4 Fixed Priority Control Register R/W GPIO Interrupt 5 Fixed Priority Control Register R/W GPIO Interrupt 6 Fixed Priority Control Register R/W GPIO Interrupt 7 Fixed Priority Control Register R/W GPIO Interrupt 8 Fixed Priority Control Register Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 2-130 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT Register GPE1_INT_FIXPRI GPF0_INT_FIXPRI GPF1_INT_FIXPRI GPF2_INT_FIXPRI GPF3_INT_FIXPRI GPG0_INT_FIXPRI GPG1_INT_FIXPRI GPG2_INT_FIXPRI GPG3_INT_FIXPRI GPJ0_INT_FIXPRI GPJ1_INT_FIXPRI GPJ2_INT_FIXPRI GPJ3_INT_FIXPRI GPJ4_INT_FIXPRI Address 0xE020_0B34 0xE020_0B38 0xE020_0B3C 0xE020_0B40 0xE020_0B44 0xE020_0B48 0xE020_0B4C 0xE020_0B50 0xE020_0B54 0xE020_0B58 0xE020_0B5C 0xE020_0B60 0xE020_0B64 0xE020_0B68 R/W Description R/W GPIO Interrupt 9 Fixed Priority Control Register R/W GPIO Interrupt 10 Fixed Priority Control Register R/W GPIO Interrupt 11 Fixed Priority Control Register R/W GPIO Interrupt 12 Fixed Priority Control Register R/W GPIO Interrupt 13 Fixed Priority Control Register R/W GPIO Interrupt 14 Fixed Priority Control Register R/W GPIO Interrupt 15 Fixed Priority Control Register R/W GPIO Interrupt 16 Fixed Priority Control Register R/W GPIO Interrupt 17 Fixed Priority Control Register R/W GPIO Interrupt 18 Fixed Priority Control Register R/W GPIO Interrupt 19 Fixed Priority Control Register R/W GPIO Interrupt 20 Fixed Priority Control Register R/W GPIO Interrupt 21 Fixed Priority Control Register R/W GPIO Interrupt 22 Fixed Priority Control Register Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 2-131 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.1 GPIO Interrupt Control Registers (GPA0_INT_CON, R/W, Address = 0xE020_0700) GPA0_INT_CON Reserved GPA0_INT_CON[7] Reserved GPA0_INT_CON[6] Reserved GPA0_INT_CON[5] Reserved GPA0_INT_CON[4] Reserved GPA0_INT_CON[3] Reserved GPA0_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPA0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA0_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-132 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPA0_INT_CON Reserved GPA0_INT_CON[1] Reserved GPA0_INT_CON[0] Bit Description 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPA0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPA0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-133 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.2 GPIO Interrupt Control Registers (GPA1_INT_CON, R/W, Address = 0xE020_0704) GPA1_INT_CON Reserved Reserved GPA1_INT_CON[3] Reserved GPA1_INT_CON[2] Reserved GPA1_INT_CON[1] Reserved GPA1_INT_CON[0] Bit [31:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPA1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPA1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 2-134 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.3 GPIO Interrupt Control Registers (GPB_INT_CON, R/W, Address = 0xE020_0708) GPB_INT_CON Reserved GPB_INT_CON[7] Reserved GPB_INT_CON[6] Reserved GPB_INT_CON[5] Reserved GPB_INT_CON[4] Reserved GPB_INT_CON[3] Reserved GPB_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPB_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPB_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPB_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPB_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPB_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPB_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-135 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPB_INT_CON Reserved GPB_INT_CON[1] Reserved GPB_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPB_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPB_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-136 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.4 GPIO Interrupt Control Registers (GPC0_INT_CON, R/W, Address = 0xE020_070C) GPC0_INT_CON Reserved Reserved GPC0_INT_CON[4] Reserved GPC0_INT_CON[3] Reserved GPC0_INT_CON[2] Reserved GPC0_INT_CON[1] Reserved GPC0_INT_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPC0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 2-137 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.5 GPIO Interrupt Control Registers (GPC1_INT_CON, R/W, Address = 0xE020_0710) GPC1_INT_CON Reserved Reserved GPC1_INT_CON[4] Reserved GPC1_INT_CON[3] Reserved GPC1_INT_CON[2] Reserved GPC1_INT_CON[1] Reserved GPC1_INT_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPC1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPC1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 2-138 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.6 GPIO Interrupt Control Registers (GPD0_INT_CON, R/W, Address = 0xE020_0714) GPD0_INT_CON Reserved Reserved GPD0_INT_CON[3] Reserved GPD0_INT_CON[2] Reserved GPD0_INT_CON[1] Reserved GPD0_INT_CON[0] Bit [31:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPD0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 2-139 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.7 GPIO Interrupt Control Registers (GPD1_INT_CON, R/W, Address = 0xE020_0718) GPD1_INT_CON Reserved Reserved GPD1_INT_CON[5] Reserved GPD1_INT_CON[4] Reserved GPD1_INT_CON[3] Reserved GPD1_INT_CON[2] Reserved GPD1_INT_CON[1] Reserved GPD1_INT_CON[0] Bit [31:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPD1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPD1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-140 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.8 GPIO Interrupt Control Registers (GPE0_INT_CON, R/W, Address = 0xE020_071C) GPE0_INT_CON Bit Description Reserved GPE0_INT_CON[7] Reserved [31] Reserved [30:28] Sets the signaling method of GPE0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [27] Reserved GPE0_INT_CON[6] Reserved GPE0_INT_CON[5] Reserved [26:24] Sets the signaling method of GPE0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [23] Reserved [22:20] Sets the signaling method of GPE0_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [19] Reserved GPE0_INT_CON[4] Reserved GPE0_INT_CON[3] Reserved GPE0_INT_CON[2] [18:16] Sets the signaling method of GPE0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [15] Reserved [14:12] Sets the signaling method of GPE0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [11] Reserved [10:8] Sets the signaling method of GPE0_INT[2] 000 = Low level 001 = High level Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-141 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPE0_INT_CON Reserved GPE0_INT_CON[1] Reserved GPE0_INT_CON[0] Bit Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPE0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPE0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-142 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.9 GPIO Interrupt Control Registers (GPE1_INT_CON, R/W, Address = 0xE020_0720) GPE1_INT_CON Reserved Reserved GPE1_INT_CON[4] Reserved GPE1_INT_CON[3] Reserved GPE1_INT_CON[2] Reserved GPE1_INT_CON[1] Reserved GPE1_INT_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPE1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPE1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPE1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPE1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPE1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 2-143 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.10 GPIO Interrupt Control Registers (GPF0_INT_CON, R/W, Address = 0xE020_0724) GPF0_INT_CON Reserved GPF0_INT_CON[7] Reserved GPF0_INT_CON[6] Reserved GPF0_INT_CON[5] Reserved GPF0_INT_CON[4] Reserved GPF0_INT_CON[3] Reserved GPF0_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPF0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF0_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-144 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF0_INT_CON Reserved GPF0_INT_CON[1] Reserved GPF0_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPF0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPF0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-145 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.11 GPIO Interrupt Control Registers (GPF1_INT_CON, R/W, Address = 0xE020_0728) GPF1_INT_CON Reserved GPF1_INT_CON[7] Reserved GPF1_INT_CON[6] Reserved GPF1_INT_CON[5] Reserved GPF1_INT_CON[4] Reserved GPF1_INT_CON[3] Reserved GPF1_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPF1_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF1_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-146 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF1_INT_CON Reserved GPF1_INT_CON[1] Reserved GPF1_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPF1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPF1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-147 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.12 GPIO Interrupt Control Registers (GPF2_INT_CON, R/W, Address = 0xE020_072C) GPF2_INT_CON Reserved GPF2_INT_CON[7] Reserved GPF2_INT_CON[6] Reserved GPF2_INT_CON[5] Reserved GPF2_INT_CON[4] Reserved GPF2_INT_CON[3] Reserved GPF2_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPF2_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF2_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF2_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF2_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF2_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF2_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-148 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPF2_INT_CON Reserved GPF2_INT_CON[1] Reserved GPF2_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPF2_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPF2_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-149 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.13 GPIO Interrupt Control Registers (GPF3_INT_CON, R/W, Address = 0xE020_0730) GPF3_INT_CON Reserved Reserved GPF3_INT_CON[5] Reserved GPF3_INT_CON[4] Reserved GPF3_INT_CON[3] Reserved GPF3_INT_CON[2] Reserved GPF3_INT_CON[1] Reserved GPF3_INT_CON[0] Bit [31:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPF3_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF3_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF3_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF3_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF3_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPF3_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-150 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.14 GPIO Interrupt Control Registers (GPG0_INT_CON, R/W, Address = 0xE020_0734) GPG0_INT_CON Reserved Reserved GPG0_INT_CON[6] Reserved GPG0_INT_CON[5] Reserved GPG0_INT_CON[4] Reserved GPG0_INT_CON[3] Reserved GPG0_INT_CON[2] Reserved GPG0_INT_CON[1] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Description Reserved Reserved Sets the signaling method of GPG0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG0_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG0_INT[1] 000 = Low level 001 = High level Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-151 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPG0_INT_CON Reserved GPG0_INT_CON[0] Bit Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPG0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 2-152 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.15 GPIO Interrupt Control Registers (GPG1_INT_CON, R/W, Address = 0xE020_0738) GPG1_INT_CON Reserved Reserved GPG1_INT_CON[6] Reserved GPG1_INT_CON[5] Reserved GPG1_INT_CON[4] Reserved GPG1_INT_CON[3] Reserved GPG1_INT_CON[2] Reserved GPG1_INT_CON[1] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Description Reserved Reserved Sets the signaling method of GPG1_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG1_INT[1] 000 = Low level 001 = High level Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-153 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPG1_INT_CON Reserved GPG1_INT_CON[0] Bit Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPG1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 2-154 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.16 GPIO Interrupt Control Registers (GPG2_INT_CON, R/W, Address = 0xE020_073C) GPG2_INT_CON Reserved Reserved GPG2_INT_CON[6] Reserved GPG2_INT_CON[5] Reserved GPG2_INT_CON[4] Reserved GPG2_INT_CON[3] Reserved GPG2_INT_CON[2] Reserved GPG2_INT_CON[1] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Description Reserved Reserved Sets the signaling method of GPG2_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG2_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG2_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG2_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG2_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG2_INT[1] 000 = Low level 001 = High level Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-155 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPG2_INT_CON Reserved GPG2_INT_CON[0] Bit Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPG2_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 2-156 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.17 GPIO Interrupt Control Registers (GPG3_INT_CON, R/W, Address = 0xE020_0740) GPG3_INT_CON Reserved Reserved GPG3_INT_CON[6] Reserved GPG3_INT_CON[5] Reserved GPG3_INT_CON[4] Reserved GPG3_INT_CON[3] Reserved GPG3_INT_CON[2] Reserved GPG3_INT_CON[1] Bit [31:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] Description Reserved Reserved Sets the signaling method of GPG3_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG3_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG3_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG3_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG3_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPG3_INT[1] 000 = Low level 001 = High level Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-157 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPG3_INT_CON Reserved GPG3_INT_CON[0] Bit Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPG3_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 2-158 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.18 GPIO Interrupt Control Registers (GPJ0_INT_CON, R/W, Address = 0xE020_0744) GPJ0_INT_CON Reserved GPJ0_INT_CON[7] Reserved GPJ0_INT_CON[6] Reserved GPJ0_INT_CON[5] Reserved GPJ0_INT_CON[4] Reserved GPJ0_INT_CON[3] Reserved GPJ0_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPJ0_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ0_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ0_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ0_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ0_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ0_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-159 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ0_INT_CON Reserved GPJ0_INT_CON[1] Reserved GPJ0_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPJ0_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPJ0_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-160 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.19 GPIO Interrupt Control Registers (GPJ1_INT_CON, R/W, Address = 0xE020_0748) GPJ1_INT_CON Reserved Reserved GPJ1_INT_CON[5] Reserved GPJ1_INT_CON[4] Reserved GPJ1_INT_CON[3] Reserved GPJ1_INT_CON[2] Reserved GPJ1_INT_CON[1] Reserved GPJ1_INT_CON[0] Bit [31:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPJ1_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ1_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ1_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ1_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ1_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ1_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 0 000 2-161 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.20 GPIO Interrupt Control Registers (GPJ2_INT_CON, R/W, Address = 0xE020_074C) GPJ2_INT_CON Reserved GPJ2_INT_CON[7] Reserved GPJ2_INT_CON[6] Reserved GPJ2_INT_CON[5] Reserved GPJ2_INT_CON[4] Reserved GPJ2_INT_CON[3] Reserved GPJ2_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPJ2_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ2_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ2_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ2_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ2_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ2_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-162 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ2_INT_CON Reserved GPJ2_INT_CON[1] Reserved GPJ2_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPJ2_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPJ2_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-163 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.21 GPIO Interrupt Control Registers (GPJ3_INT_CON, R/W, Address = 0xE020_0750) GPJ3_INT_CON Reserved GPJ3_INT_CON[7] Reserved GPJ3_INT_CON[6] Reserved GPJ3_INT_CON[5] Reserved GPJ3_INT_CON[4] Reserved GPJ3_INT_CON[3] Reserved GPJ3_INT_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of GPJ3_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ3_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ3_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ3_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ3_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ3_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-164 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPJ3_INT_CON Reserved GPJ3_INT_CON[1] Reserved GPJ3_INT_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of GPJ3_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of GPJ3_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-165 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.22 GPIO Interrupt Control Registers (GPJ4_INT_CON, R/W, Address = 0xE020_0754) GPJ4_INT_CON Reserved Reserved GPJ4_INT_CON[4] Reserved GPJ4_INT_CON[3] Reserved GPJ4_INT_CON[2] Reserved GPJ4_INT_CON[1] Reserved GPJ4_INT_CON[0] Bit [31:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Reserved Sets the signaling method of GPJ4_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ4_INT[3] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ4_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ4_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of GPJ4_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 0 000 0 000 0 000 0 000 0 000 2-166 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.23 GPIO Interrupt Control Registers (GPA0_INT_FLTCON0, R/W, Address = 0xE020_0800) GPA0_INT_FLTCON0 FLTEN1[3] FLTWIDTH1[3] FLTEN1[2] FLTWIDTH1[2] FLTEN1[1] FLTWIDTH1[1] FLTEN1[0] FLTWIDTH1[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPA0_INT[3] 0 = Disables 1 = Enables Filtering width of GPA0_INT[3] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[2] 0 = Disables 1 = Enables Filtering width of GPA0_INT[2] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[1] 0 = Disables 1 = Enables Filtering width of GPA0_INT[1] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[0] 0 = Disables 1 = Enables Filtering width of GPA0_INT[0] This value is valid when FLTSEL1is 1. Initial State 0 0 0 0 0 0 0 0 2-167 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.24 GPIO Interrupt Control Registers (GPA0_INT_FLTCON1, R/W, Address = 0xE020_0804) GPA0_INT_FLTCON1 FLTEN1[7] FLTWIDTH1[7] FLTEN1[6] FLTWIDTH1[6] FLTEN1[5] FLTWIDTH1[5] FLTEN1[4] FLTWIDTH1[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPA0_INT[7] 0 = Disables 1 = Enables Filtering width of GPA0_INT[7] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[6] 0 = Disables 1 = Enables Filtering width of GPA0_INT[6] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[5] 0 = Disables 1 = Enables Filtering width of GPA0_INT[5] This value is valid when FLTSEL1is 1. Filter Enable for GPA0_INT[4] 0 = Disables 1 = Enables Filtering width of GPA0_INT[4] This value is valid when FLTSEL1is 1. Initial State 0 0 0 0 0 0 0 0 2-168 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.25 GPIO Interrupt Control Registers (GPA1_INT_FLTCON0, R/W, Address = 0xE020_0808) GPA1_INT_FLTCON0 FLTEN2[3] FLTWIDTH2[3] FLTEN2[2] FLTWIDTH2[2] FLTEN2[1] FLTWIDTH2[1] FLTEN2[0] FLTWIDTH2[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPA1_INT[3] 0 = Disables 1 = Enables Filtering width of GPA1_INT[3] This value is valid when FLTSEL2is 1. Filter Enable for GPA1_INT[2] 0 = Disables 1 = Enables Filtering width of GPA1_INT[2] This value is valid when FLTSEL2is 1. Filter Enable for GPA1_INT[1] 0 = Disables 1 = Enables Filtering width of GPA1_INT[1] This value is valid when FLTSEL2is 1. Filter Enable for GPA1_INT[0] 0 = Disables 1 = Enables Filtering width of GPA1_INT[0] This value is valid when FLTSEL2is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.26 GPIO Interrupt Control Registers (GPA1_INT_FLTCON1, R/W, Address = 0xE020_080C) GPA1_INT_FLTCON1 Reserved Bit [31:0] Reserved Description Initial State 0 2-169 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.27 GPIO Interrupt Control Registers (GPB_INT_FLTCON0, R/W, Address = 0xE020_0810) GPB_INT_FLTCON0 FLTEN3[3] FLTWIDTH3[3] FLTEN3[2] FLTWIDTH3[2] FLTEN3[1] FLTWIDTH3[1] FLTEN3[0] FLTWIDTH3[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPB_INT[3] 0 = Disables 1 = Enables Filtering width of GPB_INT[3] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[2] 0 = Disables 1 = Enables Filtering width of GPB_INT[2] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[1] 0 = Disables 1 = Enables Filtering width of GPB_INT[1] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[0] 0 = Disables 1 = Enables Filtering width of GPB_INT[0] This value is valid when FLTSEL3 is 1. Initial State 0 0 0 0 0 0 0 0 2-170 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.28 GPIO Interrupt Control Registers (GPB_INT_FLTCON1, R/W, Address = 0xE020_0814) GPB_INT_FLTCON1 FLTEN3[7] FLTWIDTH3[7] FLTEN3[6] FLTWIDTH3[6] FLTEN3[5] FLTWIDTH3[5] FLTEN3[4] FLTWIDTH3[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPB_INT[7] 0 = Disables 1 = Enables Filtering width of GPB_INT[7] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[6] 0 = Disables 1 = Enables Filtering width of GPB_INT[6] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[5] 0 = Disables 1 = Enables Filtering width of GPB_INT[5] This value is valid when FLTSEL3 is 1. Filter Enable for GPB_INT[4] 0 = Disables 1 = Enables Filtering width of GPB_INT[4] This value is valid when FLTSEL3 is 1. Initial State 0 0 0 0 0 0 0 0 2-171 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.29 GPIO Interrupt Control Registers (GPC0_INT_FLTCON0, R/W, Address = 0xE020_0818) GPC0_INT_FLTCON0 FLTEN4[3] FLTWIDTH4[3] FLTEN4[2] FLTWIDTH4[2] FLTEN4[1] FLTWIDTH4[1] FLTEN4[0] FLTWIDTH4[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPC0_INT[3] 0 = Disables 1 = Enables Filtering width of GPC0_INT[3] This value is valid when FLTSEL4 is 1. Filter Enable for GPC0_INT[2] 0 = Disables 1 = Enables Filtering width of GPC0_INT[2] This value is valid when FLTSEL4 is 1. Filter Enable for GPC0_INT[1] 0 = Disables 1 = Enables Filtering width of GPC0_INT[1] This value is valid when FLTSEL4 is 1. Filter Enable for GPC0_INT[0] 0 = Disables 1 = Enables Filtering width of GPC0_INT[0] This value is valid when FLTSEL4 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.30 GPIO Interrupt Control Registers (GPC0_INT_FLTCON1, R/W, Address = 0xE020_081C) GPC0_INT_FLTCON1 Reserved FLTEN4[4] FLTWIDTH4[4] Bit [31:8] [7] [6:0] Description Reserved Filter Enable for GPC0_INT[4] 0 = Disables 1 = Enables Filtering width of GPC0_INT[4] This value is valid when FLTSEL4 is 1. Initial State 0 0 0 2-172 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.31 GPIO Interrupt Control Registers (GPC1_INT_FLTCON0, R/W, Address = 0xE020_0820) GPC1_INT_FLTCON0 FLTEN5[3] FLTWIDTH5[3] FLTEN5[2] FLTWIDTH5[2] FLTEN5[1] FLTWIDTH5[1] FLTEN5[0] FLTWIDTH5[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPC1_INT[3] 0 = Disables 1 = Enables Filtering width of GPC1_INT[3] This value is valid when FLTSEL5 is 1. Filter Enable for GPC1_INT[2] 0 = Disables 1 = Enables Filtering width of GPC1_INT[2] This value is valid when FLTSEL5 is 1. Filter Enable for GPC1_INT[1] 0 = Disables 1 = Enables Filtering width of GPC1_INT[1] This value is valid when FLTSEL5 is 1. Filter Enable for GPC1_INT[0] 0 = Disables 1 = Enables Filtering width of GPC1_INT[0] This value is valid when FLTSEL5 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.32 GPIO Interrupt Control Registers (GPC1_INT_FLTCON1, R/W, Address = 0xE020_0824) GPC1_INT_FLTCON1 Reserved FLTEN5[4] FLTWIDTH5[4] Bit [31:8] [7] [6:0] Description Reserved Filter Enable for GPC1_INT[4] 0 = Disables 1 = Enables Filtering width of GPC1_INT[4] This value is valid when FLTSEL5 is 1. Initial State 0 0 0 2-173 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.33 GPIO Interrupt Control Registers (GPD0_INT_FLTCON0, R/W, Address = 0xE020_0828) GPD0_INT_FLTCON0 FLTEN6[3] FLTWIDTH6[3] FLTEN6[2] FLTWIDTH6[2] FLTEN6[1] FLTWIDTH6[1] FLTEN6[0] FLTWIDTH6[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPD0_INT[3] 0 = Disables 1 = Enables Filtering width of GPD0_INT[3] This value is valid when FLTSEL6 is 1. Filter Enable for GPD0_INT[2] 0 = Disables 1 = Enables Filtering width of GPD0_INT[2] This value is valid when FLTSEL6 is 1. Filter Enable for GPD0_INT[1] 0 = Disables 1 = Enables Filtering width of GPD0_INT[1] This value is valid when FLTSEL6 is 1. Filter Enable for GPD0_INT[0] 0 = Disables 1 = Enables Filtering width of GPD0_INT[0] This value is valid when FLTSEL6 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.34 GPIO Interrupt Control Registers (GPD0_INT_FLTCON1, R/W, Address = 0xE020_082C) GPD0_INT_FLTCON1 Reserved Bit [31:0] Reserved Description Initial State 0 2-174 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.35 GPIO Interrupt Control Registers (GPD1_INT_FLTCON0, R/W, Address = 0xE020_0830) GPD1_INT_FLTCON0 FLTEN7[3] FLTWIDTH7[3] FLTEN7[2] FLTWIDTH7[2] FLTEN7[1] FLTWIDTH7[1] FLTEN7[0] FLTWIDTH7[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPD1_INT[3] 0 = Disables 1 = Enables Filtering width of GPD1_INT[3] This value is valid when FLTSEL7 is 1. Filter Enable for GPD1_INT[2] 0 = Disables 1 = Enables Filtering width of GPD1_INT[2] This value is valid when FLTSEL7 is 1. Filter Enable for GPD1_INT[1] 0 = Disables 1 = Enables Filtering width of GPD1_INT[1] This value is valid when FLTSEL7 is 1. Filter Enable for GPD1_INT[0] 0 = Disables 1 = Enables Filtering width of GPD1_INT[0] This value is valid when FLTSEL7 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.36 GPIO Interrupt Control Registers (GPD1_INT_FLTCON1, R/W, Address = 0xE020_0834) GPD1_INT_FLTCON1 Reserved FLTEN7[5] FLTWIDTH7[5] FLTEN7[4] FLTWIDTH7[4] Bit [31:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPD1_INT[5] 0 = Disables 1 = Enables Filtering width of GPD1_INT[5] This value is valid when FLTSEL7is 1. Filter Enable for GPD1_INT[4] 0 = Disables 1 = Enables Filtering width of GPD1_INT[4] This value is valid when FLTSEL7 is 1. Initial State 0 0 0 0 0 2-175 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.37 GPIO Interrupt Control Registers (GPE0_INT_FLTCON0, R/W, Address = 0xE020_0838) GPE0_INT_FLTCON0 FLTEN8[3] FLTWIDTH8[3] FLTEN8[2] FLTWIDTH8[2] FLTEN8[1] FLTWIDTH8[1] FLTEN8[0] FLTWIDTH8[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPE0_INT[3] 0 = Disables 1 = Enables Filtering width of GPE0_INT[3] This value is valid when FLTSEL8 is 1. Filter Enable for GPE0_INT[2] 0 = Disables 1 = Enables Filtering width of GPE0_INT[2] This value is valid when FLTSEL8 is 1. Filter Enable for GPE0_INT[1] 0 = Disables 1 = Enables Filtering width of GPE0_INT[1] This value is valid when FLTSEL8 is 1. Filter Enable for GPE0_INT[0] 0 = Disables 1 = Enables Filtering width of GPE0_INT[0] This value is valid when FLTSEL8 is 1. Initial State 0 0 0 0 0 0 0 0 2-176 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.38 GPIO Interrupt Control Registers (GPE0_INT_FLTCON1, R/W, Address = 0xE020_083C) GPE0_INT_FLTCON1 FLTEN8[7] FLTWIDTH8[7] FLTEN8[6] FLTWIDTH8[6] FLTEN8[5] FLTWIDTH8[5] FLTEN8[4] FLTWIDTH8[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPE0_INT[7] 0 = Disables 1 = Enables Filtering width of GPE0_INT[7] This value is valid when FLTSEL8 is 1. Filter Enable for GPE0_INT[6] 0 = Disables 1 = Enables Filtering width of GPE0_INT[6] This value is valid when FLTSEL8 is 1. Filter Enable for GPE0_INT[5] 0 = Disables 1 = Enables Filtering width of GPE0_INT[5] This value is valid when FLTSEL8is 1. Filter Enable for GPE0_INT[4] 0 = Disables 1 = Enables Filtering width of GPE0_INT[4] This value is valid when FLTSEL8 is 1. Initial State 0 0 0 0 0 0 0 0 2-177 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.39 GPIO Interrupt Control Registers (GPE1_INT_FLTCON0, R/W, Address = 0xE020_0840) GPE1_INT_FLTCON0 FLTEN9[3] FLTWIDTH9[3] FLTEN9[2] FLTWIDTH9[2] FLTEN9[1] FLTWIDTH9[1] FLTEN9[0] FLTWIDTH9[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPE1_INT[3] 0 = Disables 1 = Enables Filtering width of GPE1_INT[3] This value is valid when FLTSEL9 is 1. Filter Enable for GPE1_INT[2] 0 = Disables 1 = Enables Filtering width of GPE1_INT[2] This value is valid when FLTSEL9 is 1. Filter Enable for GPE1_INT[1] 0 = Disables 1 = Enables Filtering width of GPE1_INT[1] This value is valid when FLTSEL9 is 1. Filter Enable for GPE1_INT[0] 0 = Disables 1 = Enables Filtering width of GPE1_INT[0] This value is valid when FLTSEL9 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.40 GPIO Interrupt Control Registers (GPE1_INT_FLTCON1, R/W, Address = 0xE020_0844) GPE1_INT_FLTCON1 Reserved FLTEN9[4] FLTWIDTH9[4] Bit [31:8] [7] [6:0] Description Reserved Filter Enable for GPE1_INT[4] 0 = Disables 1 = Enables Filtering width of GPE1_INT[4] This value is valid when FLTSEL9 is 1. Initial State 0 0 0 2-178 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.41 GPIO Interrupt Control Registers (GPF0_INT_FLTCON0, R/W, Address = 0xE020_0848) GPF0_INT_FLTCON0 FLTEN10[3] FLTWIDTH10[3] FLTEN10[2] FLTWIDTH10[2] FLTEN10[1] FLTWIDTH10[1] FLTEN10[0] FLTWIDTH10[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF0_INT[3] 0 = Disables 1 = Enables Filtering width of GPF0_INT[3] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[2] 0 = Disables 1 = Enables Filtering width of GPF0_INT[2] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[1] 0 = Disables 1 = Enables Filtering width of GPF0_INT[1] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[0] 0 = Disables 1 = Enables Filtering width of GPF0_INT[0] This value is valid when FLTSEL10 is 1. Initial State 0 0 0 0 0 0 0 0 2-179 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.42 GPIO Interrupt Control Registers (GPF0_INT_FLTCON1, R/W, Address = 0xE020_084C) GPF0_INT_FLTCON1 FLTEN10[7] FLTWIDTH10[7] FLTEN10[6] FLTWIDTH10[6] FLTEN10[5] FLTWIDTH10[5] FLTEN10[4] FLTWIDTH10[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF0_INT[7] 0 = Disables 1 = Enables Filtering width of GPF0_INT[7] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[6] 0 = Disables 1 = Enables Filtering width of GPF0_INT[6] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[5] 0 = Disables 1 = Enables Filtering width of GPF0_INT[5] This value is valid when FLTSEL10 is 1. Filter Enable for GPF0_INT[4] 0 = Disables 1 = Enables Filtering width of GPF0_INT[4] This value is valid when FLTSEL10is 1. Initial State 0 0 0 0 0 0 0 0 2-180 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.43 GPIO Interrupt Control Registers (GPF1_INT_FLTCON0, R/W, Address = 0xE020_0850) GPF1_INT_FLTCON0 FLTEN11[3] FLTWIDTH11[3] FLTEN11[2] FLTWIDTH11[2] FLTEN11[1] FLTWIDTH11[1] FLTEN11[0] FLTWIDTH11[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF1_INT[3] 0 = Disables 1 = Enables Filtering width of GPF1_INT[3] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[2] 0 = Disables 1 = Enables Filtering width of GPF1_INT[2] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[1] 0 = Disables 1 = Enables Filtering width of GPF1_INT[1] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[0] 0 = Disables 1 = Enables Filtering width of GPF1_INT[0] This value is valid when FLTSEL11 is 1. Initial State 0 0 0 0 0 0 0 0 2-181 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.44 GPIO Interrupt Control Registers (GPF1_INT_FLTCON1, R/W, Address = 0xE020_0854) GPF1_INT_FLTCON1 FLTEN11[7] FLTWIDTH11[7] FLTEN11[6] FLTWIDTH11[6] FLTEN11[5] FLTWIDTH11[5] FLTEN11[4] FLTWIDTH11[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF1_INT[7] 0 = Disables 1 = Enables Filtering width of GPF1_INT[7] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[6] 0 = Disables 1 = Enables Filtering width of GPF1_INT[6] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[5] 0 = Disables 1 = Enables Filtering width of GPF1_INT[5] This value is valid when FLTSEL11 is 1. Filter Enable for GPF1_INT[4] 0 = Disables 1 = Enables Filtering width of GPF1_INT[4] This value is valid when FLTSEL11 is 1. Initial State 0 0 0 0 0 0 0 0 2-182 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.45 GPIO Interrupt Control Registers (GPF2_INT_FLTCON0, R/W, Address = 0xE020_0858) GPF2_INT_FLTCON0 FLTEN12[3] FLTWIDTH12[3] FLTEN12[2] FLTWIDTH12[2] FLTEN12[1] FLTWIDTH12[1] FLTEN12[0] FLTWIDTH12[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF2_INT[3] 0 = Disables 1 = Enables Filtering width of GPF2_INT[3] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[2] 0 = Disables 1 = Enables Filtering width of GPF2_INT[2] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[1] 0 = Disables 1 = Enables Filtering width of GPF2_INT[1] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[0] 0 = Disables 1 = Enables Filtering width of GPF2_INT[0] This value is valid when FLTSEL12 is 1. Initial State 0 0 0 0 0 0 0 0 2-183 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.46 GPIO Interrupt Control Registers (GPF2_INT_FLTCON1, R/W, Address = 0xE020_085C) GPF2_INT_FLTCON1 FLTEN12[7] FLTWIDTH12[7] FLTEN12[6] FLTWIDTH12[6] FLTEN12[5] FLTWIDTH12[5] FLTEN12[4] FLTWIDTH12[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF2_INT[7] 0 = Disables 1 = Enables Filtering width of GPF2_INT[7] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[6] 0 = Disables 1 = Enables Filtering width of GPF2_INT[6] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[5] 0 = Disables 1 = Enables Filtering width of GPF2_INT[5] This value is valid when FLTSEL12 is 1. Filter Enable for GPF2_INT[4] 0 = Disables 1 = Enables Filtering width of GPF2_INT[4] This value is valid when FLTSEL12 is 1. Initial State 0 0 0 0 0 0 0 0 2-184 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.47 GPIO Interrupt Control Registers (GPF3_INT_FLTCON0, R/W, Address = 0xE020_0860) GPF3_INT_FLTCON0 FLTEN13[3] FLTWIDTH13[3] FLTEN13[2] FLTWIDTH13[2] FLTEN13[1] FLTWIDTH13[1] FLTEN13[0] FLTWIDTH13[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPF3_INT[3] 0 = Disables 1 = Enables Filtering width of GPF3_INT[3] This value is valid when FLTSEL13 is 1. Filter Enable for GPF3_INT[2] 0 = Disables 1 = Enables Filtering width of GPF3_INT[2] This value is valid when FLTSEL13is 1. Filter Enable for GPF3_INT[1] 0 = Disables 1 = Enables Filtering width of GPF3_INT[1] This value is valid when FLTSEL13 is 1. Filter Enable for GPF3_INT[0] 0 = Disables 1 = Enables Filtering width of GPF3_INT[0] This value is valid when FLTSEL13 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.48 GPIO Interrupt Control Registers (GPF3_INT_FLTCON1, R/W, Address = 0xE020_0864) GPF3_INT_FLTCON1 Reserved FLTEN13[5] FLTWIDTH13[5] FLTEN13[4] FLTWIDTH13[4] Bit [31:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPF3_INT[5] 0 = Disables 1 = Enables Filtering width of GPF3_INT[5] This value is valid when FLTSEL13 is 1. Filter Enable for GPF3_INT[4] 0 = Disables 1 = Enables Filtering width of GPF3_INT[4] This value is valid when FLTSEL13 is 1. Initial State 0 0 0 0 0 2-185 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.49 GPIO Interrupt Control Registers (GPG0_INT_FLTCON0, R/W, Address = 0xE020_0868) GPG0_INT_FLTCON0 FLTEN14[3] FLTWIDTH14[3] FLTEN14[2] FLTWIDTH14[2] FLTEN14[1] FLTWIDTH14[1] FLTEN14[0] FLTWIDTH14[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPG0_INT[3] 0 = Disables 1 = Enables Filtering width of GPG0_INT[3] This value is valid when FLTSEL14 is 1. Filter Enable for GPG0_INT[2] 0 = Disables 1 = Enables Filtering width of GPG0_INT[2] This value is valid when FLTSEL14 is 1. Filter Enable for GPG0_INT[1] 0 = Disables 1 = Enables Filtering width of GPG0_INT[1] This value is valid when FLTSEL14 is 1. Filter Enable for GPG0_INT[0] 0 = Disables 1 = Enables Filtering width of GPG0_INT[0] This value is valid when FLTSEL14 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.50 GPIO Interrupt Control Registers (GPG0_INT_FLTCON1, R/W, Address = 0xE020_086C) GPG0_INT_FLTCON1 Reserved FLTEN14[6] FLTWIDTH14[6] FLTEN14[5] FLTWIDTH14[5] FLTEN14[4] FLTWIDTH14[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPG0_INT[6] 0 = Disables 1 = Enables Filtering width of GPG0_INT[6] This value is valid when FLTSEL14 is 1. Filter Enable for GPG0_INT[5] 0 = Disables 1 = Enables Filtering width of GPG0_INT[5] This value is valid when FLTSEL14 is 1. Filter Enable for GPG0_INT[4] 0 = Disables 1 = Enables Filtering width of GPG0_INT[4] This value is valid when FLTSEL14 is 1. Initial State 0 0 0 0 0 0 0 2-186 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.51 GPIO Interrupt Control Registers (GPG1_INT_FLTCON0, R/W, Address = 0xE020_0870) GPG1_INT_FLTCON0 FLTEN15[3] FLTWIDTH15[3] FLTEN15[2] FLTWIDTH15[2] FLTEN15[1] FLTWIDTH15[1] FLTEN15[0] FLTWIDTH15[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPG1_INT[3] 0 = Disables 1 = Enables Filtering width of GPG1_INT[3] This value is valid when FLTSEL15 is 1. Filter Enable for GPG1_INT[2] 0 = Disables 1 = Enables Filtering width of GPG1_INT[2] This value is valid when FLTSEL15 is 1. Filter Enable for GPG1_INT[1] 0 = Disables 1 = Enables Filtering width of GPG1_INT[1] This value is valid when FLTSEL15 is 1. Filter Enable for GPG1_INT[0] 0 = Disables 1 = Enables Filtering width of GPG1_INT[0] This value is valid when FLTSEL15is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.52 GPIO Interrupt Control Registers (GPG1_INT_FLTCON1, R/W, Address = 0xE020_0874) GPG1_INT_FLTCON1 Reserved FLTEN15[6] FLTWIDTH15[6] FLTEN15[5] FLTWIDTH15[5] FLTEN15[4] FLTWIDTH15[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPG1_INT[6] 0 = Disables 1 = Enables Filtering width of GPG1_INT[6] This value is valid when FLTSEL15 is 1. Filter Enable for GPG1_INT[5] 0 = Disables 1 = Enables Filtering width of GPG1_INT[5] This value is valid when FLTSEL15 is 1. Filter Enable for GPG1_INT[4] 0 = Disables 1 = Enables Filtering width of GPG1_INT[4] This value is valid when FLTSEL15 is 1. Initial State 0 0 0 0 0 0 0 2-187 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.53 GPIO Interrupt Control Registers (GPG2_INT_FLTCON0, R/W, Address = 0xE020_0878) GPG2_INT_FLTCON0 FLTEN16[3] FLTWIDTH16[3] FLTEN16[2] FLTWIDTH16[2] FLTEN16[1] FLTWIDTH16[1] FLTEN16[0] FLTWIDTH16[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPG2_INT[3] 0 = Disables 1 = Enables Filtering width of GPG2_INT[3] This value is valid when FLTSEL16 is 1. Filter Enable for GPG2_INT[2] 0 = Disables 1 = Enables Filtering width of GPG2_INT[2] This value is valid when FLTSEL16 is 1. Filter Enable for GPG2_INT[1] 0 = Disables 1 = Enables Filtering width of GPG2_INT[1] This value is valid when FLTSEL16 is 1. Filter Enable for GPG2_INT[0] 0 = Disables 1 = Enables Filtering width of GPG2_INT[0] This value is valid when FLTSEL16 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.54 GPIO Interrupt Control Registers (GPG2_INT_FLTCON1, R/W, Address = 0xE020_087C) GPG2_INT_FLTCON1 Reserved FLTEN16[6] FLTWIDTH16[6] FLTEN16[5] FLTWIDTH16[5] FLTEN16[4] FLTWIDTH16[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPG2_INT[6] 0 = Disables 1 = Enables Filtering width of GPG2_INT[6] This value is valid when FLTSEL16 is 1. Filter Enable for GPG2_INT[5] 0 = Disables 1 = Enables Filtering width of GPG2_INT[5] This value is valid when FLTSEL16 is 1. Filter Enable for GPG2_INT[4] 0 = Disables 1 = Enables Filtering width of GPG2_INT[4] This value is valid when FLTSEL16 is 1. Initial State 0 0 0 0 0 0 0 2-188 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.55 GPIO Interrupt Control Registers (GPG3_INT_FLTCON0, R/W, Address = 0xE020_0880) GPG3_INT_FLTCON0 FLTEN17[3] FLTWIDTH17[3] FLTEN17[2] FLTWIDTH17[2] FLTEN17[1] FLTWIDTH17[1] FLTEN17[0] FLTWIDTH17[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPG3_INT[3] 0 = Disables 1 = Enables Filtering width of GPG3_INT[3] This value is valid when FLTSEL17 is 1. Filter Enable for GPG3_INT[2] 0 = Disables 1 = Enables Filtering width of GPG3_INT[2] This value is valid when FLTSEL17 is 1. Filter Enable for GPG3_INT[1] 0 = Disables 1 = Enables Filtering width of GPG3_INT[1] This value is valid when FLTSEL17 is 1. Filter Enable for GPG3_INT[0] 0 = Disables 1 = Enables Filtering width of GPG3_INT[0] This value is valid when FLTSEL17 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.56 GPIO Interrupt Control Registers (GPG3_INT_FLTCON1, R/W, Address = 0xE020_0884) GPG3_INT_FLTCON1 Reserved FLTEN17[6] FLTWIDTH17[6] FLTEN17[5] FLTWIDTH17[5] FLTEN17[4] FLTWIDTH17[4] Bit [31:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPG3_INT[6] 0 = Disables 1 = Enables Filtering width of GPG3_INT[6] This value is valid when FLTSEL17 is 1. Filter Enable for GPG3_INT[5] 0 = Disables 1 = Enables Filtering width of GPG3_INT[5] This value is valid when FLTSEL17 is 1. Filter Enable for GPG3_INT[4] 0 = Disables 1 = Enables Filtering width of GPG3_INT[4] This value is valid when FLTSEL17 is 1. Initial State 0 0 0 0 0 0 0 2-189 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.57 GPIO Interrupt Control Registers (GPJ0_INT_FLTCON0, R/W, Address = 0xE020_0888) GPJ0_INT_FLTCON0 FLTEN18[3] FLTWIDTH18[3] FLTEN18[2] FLTWIDTH18[2] FLTEN18[1] FLTWIDTH18[1] FLTEN18[0] FLTWIDTH18[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ0_INT[3] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[3] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[2] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[2] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[1] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[1] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[0] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[0] This value is valid when FLTSEL18 is 1. Initial State 0 0 0 0 0 0 0 0 2-190 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.58 GPIO Interrupt Control Registers (GPJ0_INT_FLTCON1, R/W, Address = 0xE020_088C) GPJ0_INT_FLTCON1 FLTEN18[7] FLTWIDTH18[7] FLTEN18[6] FLTWIDTH18[6] FLTEN18[5] FLTWIDTH18[5] FLTEN18[4] FLTWIDTH18[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ0_INT[7] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[7] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[6] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[6] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[5] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[5] This value is valid when FLTSEL18 is 1. Filter Enable for GPJ0_INT[4] 0 = Disables 1 = Enables Filtering width of GPJ0_INT[4] This value is valid when FLTSEL18 is 1. Initial State 0 0 0 0 0 0 0 0 2-191 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.59 GPIO Interrupt Control Registers (GPJ1_INT_FLTCON0, R/W, Address = 0xE020_0890) GPJ1_INT_FLTCON0 FLTEN19[3] FLTWIDTH19[3] FLTEN19[2] FLTWIDTH19[2] FLTEN19[1] FLTWIDTH19[1] FLTEN19[0] FLTWIDTH19[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ1_INT[3] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[3] This value is valid when FLTSEL19 is 1. Filter Enable for GPJ1_INT[2] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[2] This value is valid when FLTSEL19 is 1. Filter Enable for GPJ1_INT[1] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[1] This value is valid when FLTSEL19 is 1. Filter Enable for GPJ1_INT[0] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[0] This value is valid when FLTSEL19 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.60 GPIO Interrupt Control Registers (GPJ1_INT_FLTCON1, R/W, Address = 0xE020_0894) GPJ1_INT_FLTCON1 Reserved FLTEN19[5] FLTWIDTH19[5] FLTEN19[4] FLTWIDTH19[4] Bit [31:16] [15] [14:8] [7] [6:0] Description Reserved Filter Enable for GPJ1_INT[5] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[5] This value is valid when FLTSEL19 is 1. Filter Enable for GPJ1_INT[4] 0 = Disables 1 = Enables Filtering width of GPJ1_INT[4] This value is valid when FLTSEL19 is 1. Initial State 0 0 000 0 000 2-192 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.61 GPIO Interrupt Control Registers (GPJ2_INT_FLTCON0, R/W, Address = 0xE020_0898) GPJ2_INT_FLTCON0 FLTEN20[3] FLTWIDTH20[3] FLTEN20[2] FLTWIDTH20[2] FLTEN20[1] FLTWIDTH20[1] FLTEN20[0] FLTWIDTH20[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ2_INT[3] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[3] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[2] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[2] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[1] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[1] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[0] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[0] This value is valid when FLTSEL20 is 1. Initial State 0 0 0 0 0 0 0 0 2-193 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.62 GPIO Interrupt Control Registers (GPJ2_INT_FLTCON1, R/W, Address = 0xE020_089C) GPJ2_INT_FLTCON1 FLTEN20[7] FLTWIDTH20[7] FLTEN20[6] FLTWIDTH20[6] FLTEN20[5] FLTWIDTH20[5] FLTEN20[4] FLTWIDTH20[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ2_INT[7] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[7] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[6] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[6] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[5] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[5] This value is valid when FLTSEL20 is 1. Filter Enable for GPJ2_INT[4] 0 = Disables 1 = Enables Filtering width of GPJ2_INT[4] This value is valid when FLTSEL20 is 1. Initial State 0 0 0 0 0 0 0 0 2-194 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.63 GPIO Interrupt Control Registers (GPJ3_INT_FLTCON0, R/W, Address = 0xE020_08A0) GPJ3_INT_FLTCON0 FLTEN21[3] FLTWIDTH21[3] FLTEN21[2] FLTWIDTH21[2] FLTEN21[1] FLTWIDTH21[1] FLTEN21[0] FLTWIDTH21[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ3_INT[3] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[3] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[2] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[2] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[1] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[1] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[0] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[0] This value is valid when FLTSEL21 is 1. Initial State 0 0 0 0 0 0 0 0 2-195 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.64 GPIO Interrupt Control Registers (GPJ3_INT_FLTCON1, R/W, Address = 0xE020_08A4) GPJ3_INT_FLTCON1 FLTEN21[7] FLTWIDTH21[7] FLTEN21[6] FLTWIDTH21[6] FLTEN21[5] FLTWIDTH21[5] FLTEN21[4] FLTWIDTH21[4] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ3_INT[7] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[7] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[6] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[6] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[5] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[5] This value is valid when FLTSEL21 is 1. Filter Enable for GPJ3_INT[4] 0 = Disables 1 = Enables Filtering width of GPJ3_INT[4] This value is valid when FLTSEL21 is 1. Initial State 0 0 0 0 0 0 0 0 2-196 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.65 GPIO Interrupt Control Registers (GPJ4_INT_FLTCON0, R/W, Address = 0xE020_08A8) GPJ4_INT_FLTCON0 FLTEN22[3] FLTWIDTH22[3] FLTEN22[2] FLTWIDTH22[2] FLTEN22[1] FLTWIDTH22[1] FLTEN22[0] FLTWIDTH22[0] Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Description Filter Enable for GPJ4_INT[3] 0 = Disables 1 = Enables Filtering width of GPJ4_INT[3] This value is valid when FLTSEL22 is 1. Filter Enable for GPJ4_INT[2] 0 = Disables 1 = Enables Filtering width of GPJ4_INT[2] This value is valid when FLTSEL22 is 1. Filter Enable for GPJ4_INT[1] 0 = Disables 1 = Enables Filtering width of GPJ4_INT[1] This value is valid when FLTSEL22 is 1. Filter Enable for GPJ4_INT[0] 0 = Disables 1 = Enables Filtering width of GPJ4_INT[0] This value is valid when FLTSEL22 is 1. Initial State 0 0 0 0 0 0 0 0 2.2.55.66 GPIO Interrupt Control Registers (GPJ4_INT_FLTCON1, R/W, Address = 0xE020_08AC) GPJ4_INT_FLTCON1 Reserved FLTEN22[4] FLTWIDTH22[4] Bit [31:8] [7] [6:0] Description Reserved Filter Enable for GPJ4_INT[4] 0 = Disables 1 = Enables Filtering width of GPJ4_INT[4] This value is valid when FLTSEL22 is 1. Initial State 0 0 0 2-197 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.67 GPIO Interrupt Control Registers (GPA0_INT_MASK, R/W, Address = 0xE020_0900) GPA0_INT_MASK Reserved GPA0_INT_MASK[7] GPA0_INT_MASK[6] GPA0_INT_MASK[5] GPA0_INT_MASK[4] GPA0_INT_MASK[3] GPA0_INT_MASK[2] GPA0_INT_MASK[1] GPA0_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 2.2.55.68 GPIO Interrupt Control Registers (GPA1_INT_MASK, R/W, Address = 0xE020_0904) GPA1_INT_MASK Reserved GPA1_INT_MASK[3] GPA1_INT_MASK[2] GPA1_INT_MASK[1] GPA1_INT_MASK[0] Bit [31:4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 2-198 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.69 GPIO Interrupt Control Registers (GPB_INT_MASK, R/W, Address = 0xE020_0908) GPB_INT_MASK Reserved GPB_INT_MASK[7] GPB_INT_MASK[6] GPB_INT_MASK[5] GPB_INT_MASK[4] GPB_INT_MASK[3] GPB_INT_MASK[2] GPB_INT_MASK[1] GPB_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 2-199 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.70 GPIO Interrupt Control Registers (GPC0_INT_MASK, R/W, Address = 0xE020_090C) GPC0_INT_MASK Reserved GPC0_INT_MASK[4] GPC0_INT_MASK[3] GPC0_INT_MASK[2] GPC0_INT_MASK[1] GPC0_INT_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 2.2.55.71 GPIO Interrupt Control Registers (GPC1_INT_MASK, R/W, Address = 0xE020_0910) GPC1_INT_MASK Reserved GPC1_INT_MASK[4] GPC1_INT_MASK[3] GPC1_INT_MASK[2] GPC1_INT_MASK[1] GPC1_INT_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 2-200 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.72 GPIO Interrupt Control Registers (GPD0_INT_MASK, R/W, Address = 0xE020_0914) GPD0_INT_MASK Reserved GPD0_INT_MASK[3] GPD0_INT_MASK[2] GPD0_INT_MASK[1] GPD0_INT_MASK[0] Bit [31:4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 2.2.55.73 GPIO Interrupt Control Registers (GPD1_INT_MASK, R/W, Address = 0xE020_0918) GPD1_INT_MASK Reserved GPD1_INT_MASK[5] GPD1_INT_MASK[4] GPD1_INT_MASK[3] GPD1_INT_MASK[2] GPD1_INT_MASK[1] GPD1_INT_MASK[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 2-201 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.74 GPIO Interrupt Control Registers (GPE0_INT_MASK, R/W, Address = 0xE020_091C) GPE0_INT_MASK Reserved GPE0_INT_MASK[7] GPE0_INT_MASK[6] GPE0_INT_MASK[5] GPE0_INT_MASK[4] GPE0_INT_MASK[3] GPE0_INT_MASK[2] GPE0_INT_MASK[1] GPE0_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2.2.55.75 GPIO Interrupt Control Registers (GPE1_INT_MASK, R/W, Address = 0xE020_0920) GPE1_INT_MASK Reserved GPE1_INT_MASK[4] GPE1_INT_MASK[3] GPE1_INT_MASK[2] GPE1_INT_MASK[1] GPE1_INT_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 2-202 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.76 GPIO Interrupt Control Registers (GPF0_INT_MASK, R/W, Address = 0xE020_0924) GPF0_INT_MASK Reserved GPF0_INT_MASK[7] GPF0_INT_MASK[6] GPF0_INT_MASK[5] GPF0_INT_MASK[4] GPF0_INT_MASK[3] GPF0_INT_MASK[2] GPF0_INT_MASK[1] GPF0_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2.2.55.77 GPIO Interrupt Control Registers (GPF1_INT_MASK, R/W, Address = 0xE020_0928) GPF1_INT_MASK Reserved GPF1_INT_MASK[7] GPF1_INT_MASK[6] GPF1_INT_MASK[5] GPF1_INT_MASK[4] GPF1_INT_MASK[3] GPF1_INT_MASK[2] GPF1_INT_MASK[1] GPF1_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2-203 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.78 GPIO Interrupt Control Registers (GPF2_INT_MASK, R/W, Address = 0xE020_092C) GPF2_INT_MASK Reserved GPF2_INT_MASK[7] GPF2_INT_MASK[6] GPF2_INT_MASK[5] GPF2_INT_MASK[4] GPF2_INT_MASK[3] GPF2_INT_MASK[2] GPF2_INT_MASK[1] GPF2_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enable Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2.2.55.79 GPIO Interrupt Control Registers (GPF3_INT_MASK, R/W, Address = 0xE020_0930) GPF3_INT_MASK Reserved GPF3_INT_MASK[5] GPF3_INT_MASK[4] GPF3_INT_MASK[3] GPF3_INT_MASK[2] GPF3_INT_MASK[1] GPF3_INT_MASK[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 2-204 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.80 GPIO Interrupt Control Registers (GPG0_INT_MASK, R/W, Address = 0xE020_0934) GPG0_INT_MASK Reserved GPG0_INT_MASK[6] GPG0_INT_MASK[5] GPG0_INT_MASK[4] GPG0_INT_MASK[3] GPG0_INT_MASK[2] GPG0_INT_MASK[1] GPG0_INT_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 2.2.55.81 GPIO Interrupt Control Registers (GPG1_INT_MASK, R/W, Address = 0xE020_0938) GPG1_INT_MASK Reserved GPG1_INT_MASK[6] GPG1_INT_MASK[5] GPG1_INT_MASK[4] GPG1_INT_MASK[3] GPG1_INT_MASK[2] GPG1_INT_MASK[1] GPG1_INT_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 2-205 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.82 GPIO Interrupt Control Registers (GPG2_INT_MASK, R/W, Address = 0xE020_093C) GPG2_INT_MASK Reserved GPG2_INT_MASK[6] GPG2_INT_MASK[5] GPG2_INT_MASK[4] GPG2_INT_MASK[3] GPG2_INT_MASK[2] GPG2_INT_MASK[1] GPG2_INT_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 2.2.55.83 GPIO Interrupt Control Registers (GPG3_INT_MASK, R/W, Address = 0xE020_0940) GPG3_INT_MASK Reserved GPG3_INT_MASK[6] GPG3_INT_MASK[5] GPG3_INT_MASK[4] GPG3_INT_MASK[3] GPG3_INT_MASK[2] GPG3_INT_MASK[1] GPG3_INT_MASK[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 2-206 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.84 GPIO Interrupt Control Registers (GPJ0_INT_MASK, R/W, Address = 0xE020_0944) GPJ0_INT_MASK Reserved GPJ0_INT_MASK[7] GPJ0_INT_MASK[6] GPJ0_INT_MASK[5] GPJ0_INT_MASK[4] GPJ0_INT_MASK[3] GPJ0_INT_MASK[2] GPJ0_INT_MASK[1] GPJ0_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 2.2.55.85 GPIO Interrupt Control Registers (GPJ1_INT_MASK, R/W, Address = 0xE020_0948) GPJ1_INT_MASK Reserved GPJ1_INT_MASK[5] GPJ1_INT_MASK[4] GPJ1_INT_MASK[3] GPJ1_INT_MASK[2] GPJ1_INT_MASK[1] GPJ1_INT_MASK[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 2-207 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.86 GPIO Interrupt Control Registers (GPJ2_INT_MASK, R/W, Address = 0xE020_094C) GPJ2_INT_MASK Reserved GPJ2_INT_MASK[7] GPJ2_INT_MASK[6] GPJ2_INT_MASK[5] GPJ2_INT_MASK[4] GPJ2_INT_MASK[3] GPJ2_INT_MASK[2] GPJ2_INT_MASK[1] GPJ2_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2.2.55.87 GPIO Interrupt Control Registers (GPJ3_INT_MASK, R/W, Address = 0xE020_0950) GPJ3_INT_MASK Reserved GPJ3_INT_MASK[7] GPJ3_INT_MASK[6] GPJ3_INT_MASK[5] GPJ3_INT_MASK[4] GPJ3_INT_MASK[3] GPJ3_INT_MASK[2] GPJ3_INT_MASK[1] GPJ3_INT_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2-208 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.88 GPIO Interrupt Control Registers (GPJ4_INT_MASK, R/W, Address = 0xE020_0954) GPJ4_INT_MASK Reserved GPJ4_INT_MASK[4] GPJ4_INT_MASK[3] GPJ4_INT_MASK[2] GPJ4_INT_MASK[1] GPJ4_INT_MASK[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 2-209 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.89 GPIO Interrupt Control Registers (GPA0_INT_PEND, R/W, Address = 0xE020_0A00) GPA0_INT_PEND Reserved GPA0_INT_PEND[7] GPA0_INT_PEND[6] GPA0_INT_PEND[5] GPA0_INT_PEND[4] GPA0_INT_PEND[3] GPA0_INT_PEND[2] GPA0_INT_PEND[1] GPA0_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.90 GPIO Interrupt Control Registers (GPA1_INT_PEND, R/W, Address = 0xE020_0A04) GPA1_INT_PEND Reserved GPA1_INT_PEND[3] GPA1_INT_PEND[2] GPA1_INT_PEND[1] GPA1_INT_PEND[0] Bit [31:4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 2-210 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.91 GPIO Interrupt Control Registers (GPB_INT_PEND, R/W, Address = 0xE020_0A08) GPB_INT_PEND Reserved GPB_INT_PEND[7] GPB_INT_PEND[6] GPB_INT_PEND[5] GPB_INT_PEND[4] GPB_INT_PEND[3] GPB_INT_PEND[2] GPB_INT_PEND[1] GPB_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2-211 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.92 GPIO Interrupt Control Registers (GPC0_INT_PEND, R/W, Address = 0xE020_0A0C) GPC0_INT_PEND Reserved GPC0_INT_PEND[4] GPC0_INT_PEND[3] GPC0_INT_PEND[2] GPC0_INT_PEND[1] GPC0_INT_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 2.2.55.93 GPIO Interrupt Control Registers (GPC1_INT_PEND, R/W, Address = 0xE020_0A10) GPC1_INT_PEND Reserved GPC1_INT_PEND[4] GPC1_INT_PEND[3] GPC1_INT_PEND[2] GPC1_INT_PEND[1] GPC1_INT_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 2-212 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.94 GPIO Interrupt Control Registers (GPD0_INT_PEND, R/W, Address = 0xE020_0A14) GPD0_INT_PEND Reserved GPD0_INT_PEND[3] GPD0_INT_PEND[2] GPD0_INT_PEND[1] GPD0_INT_PEND[0] Bit [31:4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 2.2.55.95 GPIO Interrupt Control Registers (GPD1_INT_PEND, R/W, Address = 0xE020_0A18) GPD1_INT_PEND Reserved GPD1_INT_PEND[5] GPD1_INT_PEND[4] GPD1_INT_PEND[3] GPD1_INT_PEND[2] GPD1_INT_PEND[1] GPD1_INT_PEND[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 2-213 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.96 GPIO Interrupt Control Registers (GPE0_INT_PEND, R/W, Address = 0xE020_0A1C) GPE0_INT_PEND Reserved GPE0_INT_PEND[7] GPE0_INT_PEND[6] GPE0_INT_PEND[5] GPE0_INT_PEND[4] GPE0_INT_PEND[3] GPE0_INT_PEND[2] GPE0_INT_PEND[1] GPE0_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.97 GPIO Interrupt Control Registers (GPE1_INT_PEND, R/W, Address = 0xE020_0A20) GPE1_INT_PEND Reserved GPE1_INT_PEND[4] GPE1_INT_PEND[3] GPE1_INT_PEND[2] GPE1_INT_PEND[1] GPE1_INT_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 2-214 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.98 GPIO Interrupt Control Registers (GPF0_INT_PEND, R/W, Address = 0xE020_0A24) GPF0_INT_PEND Reserved GPF0_INT_PEND[7] GPF0_INT_PEND[6] GPF0_INT_PEND[5] GPF0_INT_PEND[4] GPF0_INT_PEND[3] GPF0_INT_PEND[2] GPF0_INT_PEND[1] GPF0_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.99 GPIO Interrupt Control Registers (GPF1_INT_PEND, R/W, Address = 0xE020_0A28) GPF1_INT_PEND Reserved GPF1_INT_PEND[7] GPF1_INT_PEND[6] GPF1_INT_PEND[5] GPF1_INT_PEND[4] GPF1_INT_PEND[3] GPF1_INT_PEND[2] GPF1_INT_PEND[1] GPF1_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 215 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.100 GPIO Interrupt Control Registers (GPF2_INT_PEND, R/W, Address = 0xE020_0A2C) GPF2_INT_PEND Reserved GPF2_INT_PEND[7] GPF2_INT_PEND[6] GPF2_INT_PEND[5] GPF2_INT_PEND[4] GPF2_INT_PEND[3] GPF2_INT_PEND[2] GPF2_INT_PEND[1] GPF2_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.101 GPIO Interrupt Control Registers (GPF3_INT_PEND, R/W, Address = 0xE020_0A30) GPF3_INT_PEND Reserved GPF3_INT_PEND[5] GPF3_INT_PEND[4] GPF3_INT_PEND[3] GPF3_INT_PEND[2] GPF3_INT_PEND[1] GPF3_INT_PEND[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 216 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.102 GPIO Interrupt Control Registers (GPG0_INT_PEND, R/W, Address = 0xE020_0A34) GPG0_INT_PEND Reserved GPG0_INT_PEND[6] GPG0_INT_PEND[5] GPG0_INT_PEND[4] GPG0_INT_PEND[3] GPG0_INT_PEND[2] GPG0_INT_PEND[1] GPG0_INT_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 2.2.55.103 GPIO Interrupt Control Registers (GPG1_INT_PEND, R/W, Address = 0xE020_0A38) GPG1_INT_PEND Reserved GPG1_INT_PEND[6] GPG1_INT_PEND[5] GPG1_INT_PEND[4] GPG1_INT_PEND[3] GPG1_INT_PEND[2] GPG1_INT_PEND[1] GPG1_INT_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 217 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.104 GPIO Interrupt Control Registers (GPG2_INT_PEND, R/W, Address = 0xE020_0A3C) GPG2_INT_PEND Reserved GPG2_INT_PEND[6] GPG2_INT_PEND[5] GPG2_INT_PEND[4] GPG2_INT_PEND[3] GPG2_INT_PEND[2] GPG2_INT_PEND[1] GPG2_INT_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 2.2.55.105 GPIO Interrupt Control Registers (GPG3_INT_PEND, R/W, Address = 0xE020_0A40) GPG3_INT_PEND Reserved GPG3_INT_PEND[6] GPG3_INT_PEND[5] GPG3_INT_PEND[4] GPG3_INT_PEND[3] GPG3_INT_PEND[2] GPG3_INT_PEND[1] GPG3_INT_PEND[0] Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 2-218 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.106 GPIO Interrupt Control Registers (GPJ0_INT_PEND, R/W, Address = 0xE020_0A44) GPJ0_INT_PEND Reserved GPJ0_INT_PEND[7] GPJ0_INT_PEND[6] GPJ0_INT_PEND[5] GPJ0_INT_PEND[4] GPJ0_INT_PEND[3] GPJ0_INT_PEND[2] GPJ0_INT_PEND[1] GPJ0_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.107 GPIO Interrupt Control Registers (GPJ1_INT_PEND, R/W, Address = 0xE020_0A48) GPJ1_INT_PEND Reserved GPJ1_INT_PEND[5] GPJ1_INT_PEND[4] GPJ1_INT_PEND[3] GPJ1_INT_PEND[2] GPJ1_INT_PEND[1] GPJ1_INT_PEND[0] Bit [31:6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 2-219 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.108 GPIO Interrupt Control Registers (GPJ2_INT_PEND, R/W, Address = 0xE020_0A4C) GPJ2_INT_PEND Reserved GPJ2_INT_PEND[7] GPJ2_INT_PEND[6] GPJ2_INT_PEND[5] GPJ2_INT_PEND[4] GPJ2_INT_PEND[3] GPJ2_INT_PEND[2] GPJ2_INT_PEND[1] GPJ2_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.55.109 GPIO Interrupt Control Registers (GPJ3_INT_PEND, R/W, Address = 0xE020_0A50) GPJ3_INT_PEND Reserved GPJ3_INT_PEND[7] GPJ3_INT_PEND[6] GPJ3_INT_PEND[5] GPJ3_INT_PEND[4] GPJ3_INT_PEND[3] GPJ3_INT_PEND[2] GPJ3_INT_PEND[1] GPJ3_INT_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2-220 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.110 GPIO Interrupt Control Registers (GPJ4_INT_PEND, R/W, Address = 0xE020_0A54) GPJ4_INT_PEND Reserved GPJ4_INT_PEND[4] GPJ4_INT_PEND[3] GPJ4_INT_PEND[2] GPJ4_INT_PEND[1] GPJ4_INT_PEND[0] Bit [31:5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 2-221 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.111 GPIO Interrupt Control Registers (GPIO_INT_GRPPRI, R/W, Address = 0xE020_0B00) GPIO_INT_GRPPRI Reserved GPIO_INT_GRPPRI Bit [31:1] [0] Description Reserved GPIO Interrupt groups priority rotate enable 0 = Not rotate (Fixed) Initial State 0 0 2.2.55.112 GPIO Interrupt Control Registers (GPIO_INT_PRIORITY, R/W, Address = 0xE020_0B04) GPIO_INT_PRIORITY Reserved GPJ4_INT_PRI GPJ3_INT_PRI GPJ2_INT_PRI GPJ1_INT_PRI GPJ0_INT_PRI GPG3_INT_PRI GPG2_INT_PRI GPG1_INT_PRI GPG0_INT_PRI GPF3_INT_PRI GPF2_INT_PRI GPF1_INT_PRI GPF0_INT_PRI GPE1_INT_PRI GPE0_INT_PRI GPD1_INT_PRI GPD0_INT_PRI Bit [31:22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] Description Reserved GPJ4_INT priority rotate enable 0 = Not rotate(Fixed) GPJ3_INT priority rotate enable 0 = Not rotate(Fixed) GPJ2_INT priority rotate enable 0 = Not rotate(Fixed) GPJ1_INT priority rotate enable 0 = Not rotate(Fixed) GPJ0_INT priority rotate enable 0 = Not rotate(Fixed) GPG3_INT priority rotate enable 0 = Not rotate(Fixed) GPG2_INT priority rotate enable 0 = Not rotate(Fixed) GPG1_INT priority rotate enable 0 = Not rotate(Fixed) GPG0_INT priority rotate enable 0 = Not rotate(Fixed) GPF3_INT priority rotate enable 0 = Not rotate(Fixed) GPF2_INT priority rotate enable 0 = Not rotate(Fixed) GPF1_INT priority rotate enable 0 = Not rotate(Fixed) GPF0_INT priority rotate enable 0 = Not rotate(Fixed) GPE1_INT priority rotate enable 0 = Not rotate(Fixed) GPE0_INT priority rotate enable 0 = Not rotate(Fixed) GPD1_INT priority rotate enable 0 = Not rotate(Fixed) GPD0_INT priority rotate enable 0 = Not rotate(Fixed) Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2-222 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPIO_INT_PRIORITY GPC1_INT_PRI GPC0_INT_PRI GPB_INT_PRI GPA1_INT_PRI GPA0_INT_PRI Bit Description [4] GPC1_INT priority rotate enable 0 = Not rotate(Fixed) [3] GPC0_INT priority rotate enable 0 = Not rotate(Fixed) [2] GPB_INT priority rotate enable 0 = Not rotate(Fixed) [1] GPA1_INT priority rotate enable 0 = Not rotate(Fixed) [0] GPA0_INT priority rotate enable 0 = Not rotate(Fixed) Initial State 0 0 0 0 0 2-223 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.113 GPIO Interrupt Control Registers (GPIO_INT_SERVICE, R/W, Address = 0xE020_0B08) GPIO_INT_SERVICE Reserved SVC_Group_Num SVC_Num Bit [31:8] [7:3] [2:0] Description Reserved GPIO Interrupt Service group number (GPA0_INT ~ GPJ4_INT) Non_INT: 00000 == 0x0 GPA0_INT: 00001 == 0x1 GPA1_INT: 00010 == 0x2 GPB_INT: 00011 == 0x3 GPC0_INT: 00100 == 0x4 GPC1_INT: 00101 == 0x5 GPD0_INT: 00110 == 0x6 GPD1_INT: 00111 == 0x7 GPE0_INT: 01000 == 0x8 GPE1_INT: 01001 == 0x9 GPF0_INT: 01010 == 0xA GPF1_INT: 01011 == 0xB GPF2_INT: 01100 == 0xC GPF3_INT: 01101 == 0xD GPG0_INT: 01110 == 0xE GPG1_INT: 01111 == 0xF GPG2_INT: 10000 == 0x10 GPG3_INT: 10001 == 0x11 GPJ0_INT: 10010 == 0x12 GPJ1_INT: 10011 == 0x13 GPJ2_INT: 10100 == 0x14 GPJ3_INT: 10101 = 0x15 GPJ4_INT: 10110 = 0x16 Interrupt number to be serviced Initial State 0 0 0 2-224 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.114 GPIO Interrupt Control Registers (GPIO_INT_SERVICE_PEND, R/W, Address = 0xE020_0B0C) GPIO_INT_SERVICE_PEND Reserved SVC_PEND_Num Bit [31:8] [7:0] Description Reserved GPIO Interrupt Service Interrupt number (0 = Not occur , 1 = Occur interrupt) (0 ~ 7bit) 0bit: 0000_0001 == 0x1 1bit: 0000_0010 == 0x2 2bit: 0000_0100 == 0x4 3bit: 0000_1000 == 0x8 4bit: 0001_0000 == 0x10 5bit: 0010_0000 == 0x20 6bit: 0100_0000 == 0x40 7bit: 1000_0000 == 0x80 Initial State 0 0 2-225 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.115 GPIO Interrupt Control Registers (GPIO_INT_GRPFIXPRI, R/W, Address = 0xE020_0B10) GPIO_INT_GRPFIXPRI Reserved Highest_GRP_NUM Bit [31:5] [4:0] Description Reserved Group number of the highest priority when fixed group priority mode: (GPA0_INT ~ GPJ4_INT) Non_INT: 00000 == 0x0 GPA0_INT: 00001 == 0x1 GPA1_INT: 00010 == 0x2 GPB_INT: 00011 == 0x3 GPC0_INT: 00100 == 0x4 GPC1_INT: 00101 == 0x5 GPD0_INT: 00110 == 0x6 GPD1_INT: 00111 == 0x7 GPE0_INT: 01000 == 0x8 GPE1_INT: 01001 == 0x9 GPF0_INT: 01010 == 0xA GPF1_INT: 01011 == 0xB GPF2_INT: 01100 == 0xC GPF3_INT: 01101 == 0xD GPG0_INT: 01110 == 0xE GPG1_INT: 01111 == 0xF GPG2_INT: 10000 == 0x10 GPG3_INT: 10001 == 0x11 GPJ0_INT: 10010 == 0x12 GPJ1_INT: 10011 == 0x13 GPJ2_INT: 10100 == 0x14 GPJ3_INT: 10101 = 0x15 GPJ4_INT: 10110 = 0x16 *For Example, if GPC0_INT is highest priority, next priority group is GPC1_INT, not GPA0_INT. Initial State 0 0 2.2.55.116 GPIO Interrupt Control Registers (GPA0_INT_FIXPRI, R/W, Address = 0xE020_0B14) GPA0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPA0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-226 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.117 GPIO Interrupt Control Registers (GPA1_INT_FIXPRI, R/W, Address = 0xE020_0B18) GPA1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPA1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.118 GPIO Interrupt Control Registers (GPB_INT_FIXPRI, R/W, Address = 0xE020_0B1C) GPB_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPB_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-227 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.119 GPIO Interrupt Control Registers (GPC0_INT_FIXPRI, R/W, Address = 0xE020_0B20) GPC0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPC0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.120 GPIO Interrupt Control Registers (GPC1_INT_FIXPRI, R/W, Address = 0xE020_0B24) GPC1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPC1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.121 GPIO Interrupt Control Registers (GPD0_INT_FIXPRI, R/W, Address = 0xE020_0B28) GPD0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPD0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-228 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.122 GPIO Interrupt Control Registers (GPD1_INT_FIXPRI, R/W, Address = 0xE020_0B2C) GPD1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPD1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.123 GPIO Interrupt Control Registers (GPE0_INT_FIXPRI, R/W, Address = 0xE020_0B30) GPE0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPE0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.124 GPIO Interrupt Control Registers (GPE1_INT_FIXPRI, R/W, Address = 0xE020_0B34) GPE1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPE1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-229 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.125 GPIO Interrupt Control Registers (GPF0_INT_FIXPRI, R/W, Address = 0xE020_0B38) GPF0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPF0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.126 GPIO Interrupt Control Registers (GPF1_INT_FIXPRI, R/W, Address = 0xE020_0B3C) GPF1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPF1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.127 GPIO Interrupt Control Registers (GPF2_INT_FIXPRI, R/W, Address = 0xE020_0B40) GPF2_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPF2_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-230 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.128 GPIO Interrupt Control Registers (GPF3_INT_FIXPRI, R/W, Address = 0xE020_0B44) GPF3_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPF3_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.129 GPIO Interrupt Control Registers (GPG0_INT_FIXPRI, R/W, Address = 0xE020_0B48) GPG0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPG0_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.130 GPIO Interrupt Control Registers (GPG1_INT_FIXPRI, R/W, Address = 0xE020_0B4C) GPG1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPG1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-231 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.131 GPIO Interrupt Control Registers (GPG2_INT_FIXPRI, R/W, Address = 0xE020_0B50) GPG2_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPG2_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.132 GPIO Interrupt Control Registers (GPG3_INT_FIXPRI, R/W, Address = 0xE020_0B54) GPG3_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPG3_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.133 GPIO Interrupt Control Registers (GPJ0_INT_FIXPRI, R/W, Address = 0xE020_0B58) GPJ0_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Initial State Reserved 0 Interrupt number of the highest priority in GPJ0_INT when fixed 0 priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. 2-232 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.55.134 GPIO Interrupt Control Registers (GPJ1_INT_FIXPRI, R/W, Address = 0xE020_0B5C) GPJ1_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPJ1_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.135 GPIO Interrupt Control Registers (GPJ2_INT_FIXPRI, R/W, Address = 0xE020_0B60) GPJ2_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPJ2_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.136 GPIO Interrupt Control Registers (GPJ3_INT_FIXPRI, R/W, Address = 0xE020_0B64) GPJ3_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPJ3_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2.2.55.137 GPIO Interrupt Control Registers (GPJ4_INT_FIXPRI, R/W, Address = 0xE020_0B68) GPJ4_INT_FIXPRI Reserved Highest_EINT_NUM Bit [31:3] [2:0] Description Reserved Interrupt number of the highest priority in GPJ4_INT when fixed priority mode: 0~7 *For Example, if #3 is high priority, next priority interrupt is #4, not #0. Initial State 0 0 2-233 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.56 PORT GROUP GPH0 CONTROL REGISTER There are four control registers including GPH0CON, GPH0DAT, GPH0PUD and GPH0DRV in the Port Group GPH0 Control Registers. Group GPH0 is in alive area 2.2.56.1 Port Group GPH0 Control Register (GPH0CON, R/W, Address = 0xE020_0C00) GPH0CON GPH0CON[0] GPH0CON[1] GPH0CON[2] GPH0CON[3] GPH0CON[4] GPH0CON[5] GPH0CON[6] GPH0CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[0] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[1] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[2] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[3] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[4] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[5] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[6] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[7] Description Initial State 0000 0000 0000 0000 0000 0000 0000 0000 2-234 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.56.2 Port Group GPH0 Control Register (GPH0DAT, R/W, Address = 0xE020_0C04) GPH0DAT GPH0DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.56.3 Port Group GPH0 Control Register (GPH0PUD, R/W, Address = 0xE020_0C08) GPH0PUD GPH0PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.56.4 Port Group GPH0 Control Register (GPH0DRV, R/W, Address = 0xE020_0C0C) GPH0DRV GPH0DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2-235 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.57 PORT GROUP GPH1 CONTROL REGISTER There are four control registers including GPH1CON, GPH1DAT, GPH1PUD and GPH1DRV in the Port Group GPH1 Control Registers Group GPH1 is in alive area 2.2.57.1 Port Group GPH1 Control Register (GPH1CON, R/W, Address = 0xE020_0C20) GPH1CON GPH1CON[0] GPH1CON[1] GPH1CON[2] GPH1CON[3] GPH1CON[4] GPH1CON[5] GPH1CON[6] GPH1CON[7] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] Description 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[8] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[9] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[10] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[11] 0000 = Input 0001 = Output 0010 ~ 0011 = Reserved 0100 = HDMI_CEC 0100 ~ 1110 = Reserved 1111 = EXT_INT[12] 0000 = Input 0001 = Output 0010 ~ 0011 = Reserved 0100 = HDMI_HPD 0100 ~ 1110 = Reserved 1111 = EXT_INT[13] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[14] 0000 = Input 0001 = Output 0010 ~ 1110 = Reserved 1111 = EXT_INT[15] Initial State 0000 0000 0000 0000 0000 0000 0000 0000 2-236 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.57.2 Port Group GPH1 Control Register (GPH1DAT, R/W, Address = 0xE020_0C24) GPH1DAT GPH1DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.57.3 Port Group GPH1 Control Register (GPH1PUD, R/W, Address = 0xE020_0C28) GPH1PUD GPH1PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.57.4 Port Group GPH1 Control Register (GPH1DRV, R/W, Address = 0xE020_0C2C) GPH1DRV GPH1DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x0000 2-237 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.58 PORT GROUP GPH2 CONTROL REGISTER There are four control registers, namely, GPH2CON, GPH2DAT, GPH2PUD and GPH2DRV in the Port Group GPH2 Control Registers. Group GPH2 is in alive area. 2.2.58.1 Port Group GPH2 Control Register (GPH2CON, R/W, Address = 0xE020_0C40) GPH2CON GPH2CON[0] GPH2CON[1] GPH2CON[2] GPH2CON[3] GPH2CON[4] GPH2CON[5] GPH2CON[6] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] Description 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[0] 0011 ~ 1110 = Reserved 1111 = EXT_INT[16] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[1] 0011 ~ 1110 = Reserved 1111 = EXT_INT[17] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[2] 0011 ~ 1110 = Reserved 1111 = EXT_INT[18] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[3] 0011 ~ 1110 = Reserved 1111 = EXT_INT[19] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[4] 0011 ~ 1110 = Reserved 1111 = EXT_INT[20] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[5] 0011 ~ 1110 = Reserved 1111 = EXT_INT[21] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[6] 0011 ~ 1110 = Reserved Initial State 0000 0000 0000 0000 0000 0000 0000 2-238 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPH2CON GPH2CON[7] Bit [31:28] Description 1111 = EXT_INT[22] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_COL[7] 0011 ~ 1110 = Reserved 1111 = EXT_INT[23] Initial State 0000 2.2.58.2 Port Group GPH2 Control Register (GPH2DAT, R/W, Address = 0xE020_0C44) GPH2DAT GPH2DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.58.3 Port Group GPH2 Control Register (GPH2PUD, R/W, Address = 0xE020_0C48) GPH2PUD GPH2PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.58.4 Port Group GPH2 Control Register (GPH2DRV, R/W, Address = 0xE020_0C4C) GPH2DRV GPH2DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x00 2-239 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.59 PORT GROUP GPH3 CONTROL REGISTER There are four control registers, namely, GPH3CON, GPH3DAT, GPH3PUD and GPH3DRV in the Port Group GPH3 Control Registers. Group GPH3 is alive area 2.2.59.1 Port Group GPH3 Control Register (GPH3CON, R/W, Address = 0xE020_0C60) GPH3CON GPH3CON[0] GPH3CON[1] GPH3CON[2] GPH3CON[3] GPH3CON[4] GPH3CON[5] GPH3CON[6] Bit [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] Description 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[0] 0011 ~ 1110 = Reserved 1111 = EXT_INT[24] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[1] 0011 ~ 1110 = Reserved 1111 = EXT_INT[25] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[2] 0011 ~ 1110 = Reserved 1111 = EXT_INT[26] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[3] 0011 ~ 1110 = Reserved 1111 = EXT_INT[27] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[4] 0011 ~ 1110 = Reserved 1111 = EXT_INT[28] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[5] 0011 ~ 1110 = Reserved 1111 = EXT_INT[29] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[6] 0011 ~ 1110 = Reserved Initial State 0000 0000 0000 0000 0000 0000 0000 2-240 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT GPH3CON GPH3CON[7] Bit [31:28] Description 1111 = EXT_INT[30] 0000 = Input 0001 = Output 0010 = Reserved 0011 = KP_ROW[7] 0011 ~ 1110 = Reserved 1111 = EXT_INT[31] Initial State 0000 2.2.59.2 Port Group GPH3 Control Register (GPH3DAT, R/W, Address = 0xE020_0C64) GPH3DAT GPH3DAT[7:0] Bit Description [7:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. Initial State 0x00 2.2.59.3 Port Group GPH3 Control Register (GPH3PUD, R/W, Address = 0xE020_0C68) GPH3PUD GPH3PUD[n] Bit Description [2n+1:2n] n=0~7 00 = Pull-up/down disabled 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved Initial State 0x5555 2.2.59.4 Port Group GPH3 Control Register (GPH3DRV, R/W, Address = 0xE020_0C6C) GPH3DRV GPH3DRV[n] Bit [2n+1:2n] n=0~7 00 = 1x 10 = 2x 01 = 3x 11 = 4x Description Initial State 0x00 2-241 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60 EXTERNAL INTERRUPT CONTROL REGISTERS External Interrupt consists of 32 bits. EXT_INT[31:0] are used for wake-up source in Power down mode. In idle mode, all interrupts can be wake-up source; the other groups of external interrupts also can be the wake-up sources. EXT_INT[0] can be used PS_HOLD_CONTROL. For more information on PS_HOLD_CONTROL Register, refer to Chapter 02.04. PMU. The table below lists the external interrupt control registers. 2.2.60.1 External Interrupt Control Registers (EXT_INT_0_CON, R/W, Address = 0xE020_0E00) EXT_INT_0_CON Reserved EXT_INT_0_CON[7] Reserved EXT_INT_0_CON[6] Reserved EXT_INT_0_CON[5] Reserved EXT_INT_0_CON[4] Reserved EXT_INT_0_CON[3] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] Description Reserved Sets the signaling method of EXT_INT[7] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[6] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[5] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[4] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[3] 000 = Low level 001 = High level Initial State 0 000 0 000 0 000 0 000 0 000 2-242 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT EXT_INT_0_CON Reserved EXT_INT_0_CON[2] Reserved EXT_INT_0_CON[1] Reserved EXT_INT_0_CON[0] Bit [11] [10:8] [7] [6:4] [3] [2:0] Description 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[2] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[1] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[0] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 0 000 2-243 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.2 External Interrupt Control Registers (EXT_INT_1_CON, R/W, Address = 0xE020_0E04) EXT_INT_1_CON Reserved EXT_INT_1_CON[7] Reserved EXT_INT_1_CON[6] Reserved EXT_INT_1_CON[5] Reserved EXT_INT_1_CON[4] Reserved EXT_INT_1_CON[3] Reserved EXT_INT_1_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of EXT_INT[15] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[14] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[13] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[12] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[11] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[10] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-244 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT EXT_INT_1_CON Reserved EXT_INT_1_CON[1] Reserved EXT_INT_1_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of EXT_INT[9] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of EXT_INT[8] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-245 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.3 External Interrupt Control Registers (EXT_INT_2_CON, R/W, Address = 0xE020_0E08) EXT_INT_2_CON Reserved EXT_INT_2_CON[7] Reserved EXT_INT_2_CON[6] Reserved EXT_INT_2_CON[5] Reserved EXT_INT_2_CON[4] Reserved EXT_INT_2_CON[3] Reserved EXT_INT_2_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of EXT_INT[23] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[22] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[21] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[20] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[19] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[18] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-246 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT EXT_INT_2_CON Reserved EXT_INT_2_CON[1] Reserved EXT_INT_2_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of EXT_INT[17] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of EXT_INT[16] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-247 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.4 External Interrupt Control Registers (EXT_INT_3_CON, R/W, Address = 0xE020_0E0C) EXT_INT_3_CON Reserved EXT_INT_3_CON[7] Reserved EXT_INT_3_CON[6] Reserved EXT_INT_3_CON[5] Reserved EXT_INT_3_CON[4] Reserved EXT_INT_3_CON[3] Reserved EXT_INT_3_CON[2] Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] Description Reserved Sets the signaling method of EXT_INT[31] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[30] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[29] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[28] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[27] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Reserved Sets the signaling method of EXT_INT[26] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered Initial State 0 000 0 000 0 000 0 000 0 000 0 000 2-248 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT EXT_INT_3_CON Reserved EXT_INT_3_CON[1] Reserved EXT_INT_3_CON[0] Bit Description 100 = Both edge triggered 101 ~ 111 = Reserved [7] Reserved [6:4] Sets the signaling method of EXT_INT[25] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved [3] Reserved [2:0] Sets the signaling method of EXT_INT[24] 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered 100 = Both edge triggered 101 ~ 111 = Reserved Initial State 0 000 0 000 2-249 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.5 External Interrupt Control Registers (EXT_INT_0_FLTCON0, R/W, Address = 0xE020_0E80) EXT_INT_0_FLTCON0 FLTEN_0[3] FLTSEL_0[3] FLTWIDTH_0[3] FLTEN_0[2] FLTSEL_0[2] FLTWIDTH_0[2] FLTEN_0[1] FLTSEL_0[1] FLTWIDTH_0[1] FLTEN_0[0] FLTSEL_0[0] FLTWIDTH_0[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[3] 0 = Disables 1 = Enables Filter Selection for EXT_INT[3] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[3] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[2] 0 = Disables 1 = Enables Filter Selection for EXT_INT[2] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[2] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[1] 0 = Disables 1 = Enables Filter Selection for EXT_INT[1] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[1] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[0] 0 = Disables 1 = Enables Filter Selection for EXT_INT[0] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[0] This value is valid when FLTSEL30 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-250 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.6 External Interrupt Control Registers (EXT_INT_0_FLTCON1, R/W, Address = 0xE020_0E84) EXT_INT_0_FLTCON1 FLTEN_0[7] FLTSEL_0[7] FLTWIDTH_0[7] FLTEN_0[6] FLTSEL_0[6] FLTWIDTH_0[6] FLTEN_0[5] FLTSEL_0[5] FLTWIDTH_0[5] FLTEN_0[4] FLTSEL_0[4] FLTWIDTH_0[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[7] 0 = Disables 1 = Enables Filter Selection for EXT_INT[7] 0 = Delay filter 1 = Digital filter(clock count) Filtering width of EXT_INT[7] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[6] 0 = Disables 1 = Enables Filter Selection for EXT_INT[6] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[6] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[5] 0 = Disables 1 = Enables Filter Selection for EXT_INT[5] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[5] This value is valid when FLTSEL30 is 1. Filter Enable for EXT_INT[4] 0 = Disables 1 = Enables Filter Selection for EXT_INT[4] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[4] This value is valid when FLTSEL30 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-251 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.7 External Interrupt Control Registers (EXT_INT_1_FLTCON0, R/W, Address = 0xE020_0E88) EXT_INT_1_FLTCON0 FLTEN_1[3] FLTSEL_1[3] FLTWIDTH_1[3] FLTEN_1[2] FLTSEL_1[2] FLTWIDTH_1[2] FLTEN_1[1] FLTSEL_1[1] FLTWIDTH_1[1] FLTEN_1[0] FLTSEL_1[0] FLTWIDTH_1[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[11] 0 = Disables 1 = Enables Filter Selection for EXT_INT[11] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[11] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[10] 0 = Disables 1 = Enables Filter Selection for EXT_INT[10] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[10] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[9] 0 = Disables 1 = Enables Filter Selection for EXT_INT[9] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[9] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[8] 0 = Disables 1 = Enables Filter Selection for EXT_INT[8] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[8] This value is valid when FLTSEL31 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-252 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.8 External Interrupt Control Registers (EXT_INT_1_FLTCON1, R/W, Address = 0xE020_0E8C) EXT_INT_1_FLTCON1 FLTEN_1[7] FLTSEL_1[7] FLTWIDTH_1[7] FLTEN_1[6] FLTSEL_1[6] FLTWIDTH_1[6] FLTEN_1[5] FLTSEL_1[5] FLTWIDTH_1[5] FLTEN_1[4] FLTSEL_1[4] FLTWIDTH_1[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[15] 0 = Disables 1 = Enables Filter Selection for EXT_INT[15] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[15] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[14] 0 = Disables 1 = Enables Filter Selection for EXT_INT[14] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[14] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[13] 0 = Disables 1 = Enables Filter Selection for EXT_INT[13] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[13] This value is valid when FLTSEL31 is 1. Filter Enable for EXT_INT[12] 0 = Disables 1 = Enables Filter Selection for EXT_INT[12] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[12] This value is valid when FLTSEL31 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-253 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.9 External Interrupt Control Registers (EXT_INT_2_FLTCON0, R/W, Address = 0xE020_0E90) EXT_INT_2_FLTCON0 FLTEN_2[3] FLTSEL_2[3] FLTWIDTH_2[3] FLTEN_2[2] FLTSEL_2[2] FLTWIDTH_2[2] FLTEN_2[1] FLTSEL_2[1] FLTWIDTH_2[1] FLTEN_2[0] FLTSEL_2[0] FLTWIDTH_2[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[19] 0 = Disables 1 = Enables Filter Selection for EXT_INT[19] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[19] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[18] 0 = Disables 1 = Enables Filter Selection for EXT_INT[18] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[18] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[17] 0 = Disables 1 = Enables Filter Selection for EXT_INT[17] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[17] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[16] 0 = Disables 1 = Enables Filter Selection for EXT_INT[16] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[16] This value is valid when FLTSEL32 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-254 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.10 External Interrupt Control Registers (EXT_INT_2_FLTCON1, R/W, Address = 0xE020_0E94) EXT_INT_2_FLTCON1 FLTEN_2[7] FLTSEL_2[7] FLTWIDTH_2[7] FLTEN_2[6] FLTSEL_2[6] FLTWIDTH_2[6] FLTEN_2[5] FLTSEL_2[5] FLTWIDTH_2[5] FLTEN_2[4] FLTSEL_2[4] FLTWIDTH_2[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[23] 0 = Disables 1 = Enables Filter Selection for EXT_INT[23] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[23] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[22] 0 = Disables 1 = Enables Filter Selection for EXT_INT[22] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[22] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[21] 0 = Disables 1 = Enables Filter Selection for EXT_INT[21] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[21] This value is valid when FLTSEL32 is 1. Filter Enable for EXT_INT[20] 0 = Disables 1 = Enables Filter Selection for EXT_INT[20] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[20] This value is valid when FLTSEL32is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-255 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.11 External Interrupt Control Registers (EXT_INT_3_FLTCON0, R/W, Address = 0xE020_0E98) EXT_INT_3_FLTCON0 FLTEN_3[3] FLTSEL_3[3] FLTWIDTH_3[3] FLTEN_3[2] FLTSEL_3[2] FLTWIDTH_3[2] FLTEN_3[1] FLTSEL_3[1] FLTWIDTH_3[1] FLTEN_3[0] FLTSEL_3[0] FLTWIDTH_3[0] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[27] 0 = Disables 1 = Enables Filter Selection for EXT_INT[27] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[27] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[26] 0 = Disables 1 = Enables Filter Selection for EXT_INT[26] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[26] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[25] 0 = Disables 1 = Enables Filter Selection for EXT_INT[25] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[25] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[24] 0 = Disables 1 = Enables Filter Selection for EXT_INT[24] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[24] This value is valid when FLTSEL33 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-256 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.12 External Interrupt Control Registers (EXT_INT_3_FLTCON1, R/W, Address = 0xE020_0E9C) EXT_INT_3_FLTCON1 FLTEN_3[7] FLTSEL_3[7] FLTWIDTH_3[7] FLTEN_3[6] FLTSEL_3[6] FLTWIDTH_3[6] FLTEN_3[5] FLTSEL_3[5] FLTWIDTH_3[5] FLTEN_3[4] FLTSEL_3[4] FLTWIDTH_3[4] Bit [31] [30] [29:24] [23] [22] [21:16] [15] [14] [13:8] [7] [6] [5:0] Description Filter Enable for EXT_INT[31] 0 = Disables 1 = Enables Filter Selection for EXT_INT[31] 0 = Delay filter 1 = Digital filter(clock count) Filtering width of EXT_INT[31] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[30] 0 = Disables 1 = Enables Filter Selection for EXT_INT[30] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[30] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[29] 0 = Disables 1 = Enables Filter Selection for EXT_INT[29] 0 = Delay filter 1 = Digital filter (clock count) Filtering width of EXT_INT[29] This value is valid when FLTSEL33 is 1. Filter Enable for EXT_INT[28] 0 = Disables 1 = Enables Filter Selection for EXT_INT[28] 0 = Delay filter 1 = Digital filter(clock count) Filtering width of EXT_INT[28] This value is valid when FLTSEL33 is 1. Initial State 1 0 0 1 0 0 1 0 0 1 0 0 2-257 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.13 External Interrupt Control Registers (EXT_INT_0_MASK, R/W, Address = 0xE020_0F00) EXT_INT_0_MASK Reserved EXT_INT_0_MASK[7] EXT_INT_0_MASK[6] EXT_INT_0_MASK[5] EXT_INT_0_MASK[4] EXT_INT_0_MASK[3] EXT_INT_0_MASK[2] EXT_INT_0_MASK[1] EXT_INT_0_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2.2.60.14 External Interrupt Control Registers (EXT_INT_1_MASK, R/W, Address = 0xE020_0F04) EXT_INT_1_MASK Reserved EXT_INT_1_MASK[7] EXT_INT_1_MASK[6] EXT_INT_1_MASK[5] EXT_INT_1_MASK[4] EXT_INT_1_MASK[3] EXT_INT_1_MASK[2] EXT_INT_1_MASK[1] EXT_INT_1_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Description Initial State 0 1 1 1 1 1 1 1 1 2-258 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.15 External Interrupt Control Registers (EXT_INT_2_MASK, R/W, Address = 0xE020_0F08) EXT_INT_2_MASK Reserved EXT_INT_2_MASK[7] EXT_INT_2_MASK[6] EXT_INT_2_MASK[5] EXT_INT_2_MASK[4] EXT_INT_2_MASK[3] EXT_INT_2_MASK[2] EXT_INT_2_MASK[1] EXT_INT_2_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 2.2.60.16 External Interrupt Control Registers (EXT_INT_3_MASK, R/W, Address = 0xE020_0F0C) EXT_INT_3_MASK Reserved EXT_INT_3_MASK[7] EXT_INT_3_MASK[6] EXT_INT_3_MASK[5] EXT_INT_3_MASK[4] EXT_INT_3_MASK[3] EXT_INT_3_MASK[2] EXT_INT_3_MASK[1] EXT_INT_3_MASK[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked 0 = Enables Interrupt 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 2-259 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.17 External Interrupt Control Registers (EXT_INT_0_PEND, R/W, Address = 0xE020_0F40) EXT_INT_0_PEND Reserved EXT_INT_0_PEND[7] EXT_INT_0_PEND[6] EXT_INT_0_PEND[5] EXT_INT_0_PEND[4] EXT_INT_0_PEND[3] EXT_INT_0_PEND[2] EXT_INT_0_PEND[1] EXT_INT_0_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.60.18 External Interrupt Control Registers (EXT_INT_1_PEND, R/W, Address = 0xE020_0F44) EXT_INT_1_PEND Reserved EXT_INT_1_PEND[7] EXT_INT_1_PEND[6] EXT_INT_1_PEND[5] EXT_INT_1_PEND[4] EXT_INT_1_PEND[3] EXT_INT_1_PEND[2] EXT_INT_1_PEND[1] EXT_INT_1_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2-260 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.60.19 External Interrupt Control Registers (EXT_INT_2_PEND, R/W, Address = 0xE020_0F48) EXT_INT_2_PEND Reserved EXT_INT_2_PEND[7] EXT_INT_2_PEND[6] EXT_INT_2_PEND[5] EXT_INT_2_PEND[4] EXT_INT_2_PEND[3] EXT_INT_2_PEND[2] EXT_INT_2_PEND[1] EXT_INT_2_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2.2.60.20 External Interrupt Control Registers (EXT_INT_3_PEND, R/W, Address = 0xE020_0F4C) EXT_INT_3_PEND Reserved EXT_INT_3_PEND[7] EXT_INT_3_PEND[6] EXT_INT_3_PEND[5] EXT_INT_3_PEND[4] EXT_INT_3_PEND[3] EXT_INT_3_PEND[2] EXT_INT_3_PEND[1] EXT_INT_3_PEND[0] Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt 0 = Not occur 1 = Occur interrupt Description Initial State 0 0 0 0 0 0 0 0 0 2-261 S5PV210_UM 2 1BGENERAL PURPOSE INPUT/ OUTPUT 2.2.61 EXTERN PIN CONFIGURATION REGISTERS IN POWER DOWN MODE This registers keep their values during power down mode 2.2.61.1 Extern Pin Configuration Registers in Power down Mode (PDNEN, R/W, Address = 0xE020_0F80) PDNEN Reserved PDNEN_CFG PDNEN Bit Description Initial State [7:2] Reserved 0 [1] 0 = Automatically by power down mode 0 1 = by PDNEN bit [0] Power down mode pad state enable register. 0 1 = PADs Controlled by Power Down mode control registers 0 = PADs Controlled by normal mode This bit is set to '1' automaticially when system enters into Power down mode and can be cleared by writing '0' to this bit or cold reset. After wake up from Power down mode, this bit maintains value '1' until writing '0' 2-262 S5PV210_UM 3 2BCLOCK CONTROLLER 3 CLOCK CONTROLLER This chapter describes the clock management unit (CMU) supported by S5PV210. The system controller (SYSCON) manages CMU and power management unit (PMU) in S5PV210. 3.1 CLOCK DOMAINS S5PV210 consists of three clock domains, namely, main system (MSYS), display system (DSYS), and peripheral system (PSYS), as shown in Figure 3-1. • MSYS domain comprises Cortex A8 processor, DRAM memory controllers (DMC0 and DMC1), 3D, internal SRAM (IRAM, and IROM), INTC, and configuration interface (SPERI). Cortex A8 supports only synchronous mode, and therefore it must operate synchronously with 200MHz AXI buses. • DSYS domain comprises display related modules, including FIMC, FIMD, JPEG, and multimedia IPs (all other IPs mentioned in X, L, and T blocks), as shown in Figure 3-1. • PSYS domain is used for security, I/O peripherals, and low power audio play. Each bus system operates at 200 MHz (maximum), 166 MHz, and 133 MHz, respectively. There are asynchronous bus bridges (BRG) between two different domains. Figure 3-1 S5PV210 Clock Domains 3-1 S5PV210_UM 3 2BCLOCK CONTROLLER 3.2 CLOCK DECLARATION Figure 3-2 shows the classification of clocks in S5PV210. The top-level clocks in S5PV210 include: • Clocks from clock pads, that is, XRTCXTI, XXTI, XUSBXTI, and XHDMIXTI. • Clocks from CMU (for instance, ARMCLK, HCLK, PCLK, and so on.) • Clocks from USB OTG PHY • Clocks from GPIO pads 3.2.1 CLOCKS FROM CLOCK PADS The following clocks are provided by clock pads. However, you can disable crystal clock pads. • XRTCXTI: Specifies a clock from 32.768 KHz crystal pad with XRTCXTI and XRTCXTO pins. RTC uses this clock as the source of a real-time clock. • XXTI: Specifies a clock from crystal pad with XXTI and XXTO pins. When USB PHY is not used in commercial set, CMU and PLL use this clock to generate other clocks to modules (APLL, MPLL, VPLL, and EPLL.). The input frequency ranges from 12 ~ 50 MHz. • XUSBXTI: Specifies a clock from a crystal pad with XUSBXTI and XUSBXTO pins. This clock is supplied to APLL, MPLL, VPLL, ELL, and USB PHY. For more information on USB PHY clock, refer to Chapter 8.4 " USB 2.0 HOST Controller " and 8.5 " USB2.0 HS OTG ". • XHDMIXTI: Specifies a clock from 27MHz crystal pad with XHDMIXTI and XHDMIXTO pins. VPLL or HDMI PHY generates 54MHz clock for TV encoder. Figure 3-2 S5PV210 Top-Level Clocks 3-2 S5PV210_UM 3 2BCLOCK CONTROLLER • XXTI and XXTO use wide-range OSC pads. • XUSBXTI and XUSBXTO use wide range OSC pads. • XHDMIXTI and XHDMIXTO use wide range OSC pads. • XRTCXTI and XRTCXTO use OSC pads for RTC. • ARMCLK specifies clock for Cortex A8 (up to 800 MHz @ 1.1V, 1 GHz @ 1.2V). • HCLK_MSYS specifies AXI clock for MSYS clock domain, as shown in Figure 3-1. • PCLK_MSYS specifies APB clock for MSYS clock domain, as shown in Figure 3-1. The maximum operating frequency is up to 100MHz. • HCLK_DSYS specifies AXI/AHB clock for DSYS clock domain, as shown in Figure 3-1. • PCLK_DSYS specifies APB clock for DSYS clock domain, as shown in Figure 3-1. The maximum operating frequency is up to 83 MHz. • HCLK_PSYS specifies AXI/AHB clock for PSYS clock domain, as shown in Figure 3-1. • PCLK_PSYS specifies APB clock for PSYS clock domain, as shown in Figure 3-1. The maximum operating frequency is up to 66 MHz. • Special clocks specify all the clocks except bus clock and processor core clock. 3.2.2 CLOCKS FROM CMU CMU generates internal clocks with intermediate frequencies using clocks from the clock pads (that is, XRTCXTI, XXTI, XUSBXTI, and XHDMIXTI), four PLLs (that is, APLL, MPLL, EPLL, and VPLL), and USB_OTG PHY clock. Some of these clocks can be selected, pre-scaled, and provided to the corresponding modules. It is recommended to use 24MHz input clock source for APLL, MPLL, and EPLL, and 27MHz input clock source for VPLL. To generate internal clocks, the following components are used. • APLL uses SRCLK as input to generate 30MHz ~ 1GHz. • MPLL uses SRCLK as input to generate 50MHz ~ 2GHz. • EPLL uses SRCLK as input to generate 10MHz ~ 600MHz. • VPLL uses SRCLK as input to generate 10MHz ~ 600MHz. This PLL generates 54MHz video clock. • USB OTG PHY uses XUSBXTI to generate 30MHz and 48MHz. In typical S5PV210 applications, • Cortex A8 and MSYS clock domain uses APLL (that is, ARMCLK, HCLK_MSYS, and PCLK_MSYS). • DSYS and PSYS clock domain (that is, HCLK_DSYS, HCLK_PSYS, PCLK_DSYS, and PCLK_PSYS) and other peripheral clocks (that is, audio IPs, SPI, and so on) use MPLL and EPLL. • Video clocks uses VPLL. Clock controller allows bypassing of PLLs for slow clock. It also connects/ disconnects the clock from each block (clock gating) using software, resulting in power reduction. 3-3 S5PV210_UM 3 2BCLOCK CONTROLLER 3.3 CLOCK RELATIONSHIP Clocks have the following relationship: • MSYS clock domain − freq(ARMCLK) − freq(HCLK_MSYS) − freq(PCLK_MSYS) − freq(HCLK_IMEM) = freq(APLLCLK) / n, where n = 1 ~ 8 = freq(ARMCLK) / n, where n = 1 ~ 8 = freq(HCLK_MSYS) / n, where n = 1 ~ 8 = freq(HCLK_MSYS) / 2 • DSYS clock domain − freq(PCLK_DSYS) = freq(HCLK_DSYS) / n, where n = 1 ~ 8 • PSYS clock domain − freq(PCLK_PSYS) − freq(SCLK_ONENAND) − freq(SCLK_ONENANPSYS) = freq(HCLK_PSYS) / n, where n = 1 ~ 8 = freq(HCLK_PSYS) / n, where n = 1 ~ 8 = freq(SCLK_ONENAND) / 2 Values for the high-performance operation: • freq(ARMCLK) • freq(HCLK_MSYS) • freq(HCLK_IMEM) • freq(PCLK_MSYS) • freq(HCLKSECSS) • freq(HCLK_DSYS) • freq(PCLK_DSYS) • freq(HCLK_PSYS) • freq(PCLK_PSYS) • freq(SCLK_ONENAND) = 800 MHz = 200 MHz = 100 MHz = 100 MHz = 83 MHz = 166 MHz = 83 MHz = 133 MHz = 66 MHz = 133 MHz, 166 MHz 3-4 S5PV210_UM 3 2BCLOCK CONTROLLER • PLL − APLL can drive MSYS domain and DSYS domain. It can generate up to 1 GHz, 49:51 duty ratio. − MPLL can drive MSYS domain and DSYS domain. It supplies clock, up to 2 GHz and 40:60 duty ratio. − EPLL is mainly used to generate audio clock. − VPLL is mainly used to generate video system operating clock, 54 MHz. − Typically, APLL drives MSYS domain and MPLL drives DSYS domain. 3.3.1 RECOMMENDED PLL PMS VALUE FOR APLL Table 3-1 APLL PMS Value FIN (MHz) 24 24 Target FOUT (MHz) 800 1000 FVCO P M S AFC_ENB AFC (MHz) 6 200 1 0 6 250 1 0 0 1600.000 0 2000.000 FOUT (MHz) 800.000 1000.000 3-5 S5PV210_UM 3 2BCLOCK CONTROLLER 3.3.2 RECOMMENDED PLL PMS VALUE FOR MPLL FIN (MHz) 24 24 24 24 24 Table 3-2 MPLL PMS Value Target FOUT VSEL P M S (MHz) 133 0 6 266 3 166 0 6 332 3 266 0 6 266 2 333 0 6 333 2 667 0 12 667 1 FVCO (MHz) 1064.000 1328.000 1064.000 1332.000 1334.000 FOUT (MHz) 133.000 166.000 266.000 333.000 667.000 3.3.3 RECOMMENDED PLL PMS VALUE FOR EPLL FIN (MHz) 24 24 24 24 24 24 24 24 24 24 24 24 24 Target FOUT (MHz) 48.0000 96.0000 144.0000 192.0000 288.0000 84.0000 50.0000 80.0000 32.7680 49.1520 67.7376 73.7280 45.1584 Table 3-3 EPLL PMS Value VSEL P M S K 0 3 48 3 0 0 3 48 2 0 1 3 72 2 0 0 3 48 1 0 1 3 72 1 0 0 3 42 2 0 0 3 50 3 0 1 3 80 3 0 1 3 65 4 35127 0 3 49 3 9961 1 3 67 3 48339 1 3 73 3 47710 0 3 45 3 10381 FVCO (MHz) 384.000 384.000 576.000 384.000 576.000 336.000 400.000 640.000 524.28796 393.21594 541.90076 589.82397 361.26721 FOUT (MHz) 48.000 96.000 144.000 192.000 288.000 84.000 50.000 80.000 32.76800 49.15199 67.73759 73.72800 45.15840 3-6 S5PV210_UM 3 2BCLOCK CONTROLLER 3.3.4 RECOMMENDED PLL PMS VALUE FOR VPLL FIN (MHz) 27 24 Table 3-4 VPLL PMS Value Target FOUT VSEL P M S (MHz) 54.0000 0 6 96 3 108.000 0 6 96 2 74.2500 1 6 132 3 148.5000 1 6 132 2 222.7500 0 6 99 1 397.0000 0 3 44 0 371.2500 0 4 55 0 445.5000 0 6 99 0 74.1758 1 6 132 3 148.3516 1 6 132 2 222.5275 0 6 99 1 296.7033 1 6 132 1 370.8791 0 11 151 0 445.0549 0 6 99 0 519.2308 1 9 173 0 54.000 0 6 108 3 108.000 0 6 108 2 74.250 1 8 198 3 148.500 1 8 198 2 222.750 0 16 297 1 397.000 0 24 397 0 371.250 0 24 371 0 445.500 0 16 297 0 74.176 1 18 445 3 148.352 1 18 445 2 222.528 0 22 408 1 296.703 1 18 445 1 370.879 0 22 340 0 445.055 0 22 408 0 519.231 1 22 476 0 27.027 0 6 108 4 27.000 0 6 108 4 FVCO (MHz) 432.000 432.000 594.000 594.000 445.500 396.000 371.250 445.500 594.000 594.000 445.500 594.000 370.636 445.500 519.000 432.000 432.000 594.000 594.000 445.500 397.000 371.000 445.500 593.333 593.333 445.091 593.333 370.909 445.091 519.273 432.000 432.000 FOUT (MHz) 54.000 108.000 74.250 148.500 222.750 396.000 371.250 445.500 74.250 148.500 222.750 297.000 370.636 445.500 519.000 54.000 108.000 74.250 148.500 222.750 397.000 371.000 445.500 74.167 148.333 222.545 296.667 370.909 445.091 519.273 27.000 27.000 3-7 S5PV210_UM 3 2BCLOCK CONTROLLER 3.4 CLOCK GENERATION Figure 3-3 shows block diagram of the clock generation logic. An external crystal clock is connected to the oscillation amplifier. The PLL converts low input frequency to high-frequency clock required by S5PV210. The clock generator block also includes a built-in logic to stabilize the clock frequency after each system reset, since clock takes time before stabilizing. Figure 3-3 also shows two types of clock mux. Clock mux in grey color represents glitch-free clock mux, which is free of glitches if clock selection is changed. Clock mux in white color represents non-glitch-free clock mux, which can suffer from glitches when changing clock sources. Care must be taken in using each of clock muxes. For glitch-free mux, it should be guaranteed that both of clock sources are running when clock selection is changed from one to the other. If that's not the case, clock changing is not finished fully and resulting clock output can have unknown states. For non-glitch-free clock mux, it is possible to have a glitch when clock selections are changed. To prevent the glitch signals, it is recommended to disable output of non-glitch-free muxes before trying to change clock sources. After clock changing is completed, users can re-enable output of the non-glitch-free clock mux so that there will be no glitches resulting from clock changes. Masking output of non-glitch-free muxes are handled by clock source control registers. Clock dividers shown in Figure 3-3 indicates possible dividing value in parentheses. Those diving values can be decided by clock divider registers on run-time. Some clock dividers can only have one dividing value and user cannot change them and does not have corresponding fields in clock divider registers. 3-8 S5PV210_UM 3 2BCLOCK CONTROLLER SCLK VPLL SCLK_ HDMIPHY XXTI XusbXTI SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL XXTI XusbXTI SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL XXTI XusbXTI SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL XXTI PCMCDCLK 0 SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL I2 SCDCLK 1 PCMCDCLK 1 SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL I2 SCDCLK 2 PCMCDCLK 2 SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL XXTI XusbXTI SCLK _ HDMI 27M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLK M PLL SCLKE PLL SCLKV PLL DIV TBLK ( 1 ~ 16 ) MUX DAC 0 SCLK _ DAC/ TVENC 1 MUXMIXER 0 SCLK _ MIXER 0 1 1 SCLK _ HDMI MUX HDMI SCLK _ PIXEL MUXCAM 0,1 DIV CAM0,1 (1~16) MOUTCAM 0,1 SCLK _ CAM 0, 1( PAD) MUXFIMD MOUT FIMD DIV FIMD (1~16) SCLK_ FIMD MUX MMC0~3 DIV MMC 0~3 (1~16) MOUT MMC 0~3 SCLK _ MMC 0 ~ 3 MUXAUDIO 0 DIV AUDIO 0 MOUT AUDIO 0 (1~16) SCLK _ AUDIO0 MUXAUDIO 1 DIV AUDIO 1 (1~16) MOUT AUDIO 1 SCLK _ AUDIO1 MUXAUDIO 2 DIV AUDIO 2 MOUT AUDIO 2 (1~16) SCLK _ AUDIO2 SCLKA 2M SCLK MPLL SCLK E PLL SCLK V PLL SCLK A2 M SCLK MPLL SCLKE PLL SCLKV PLL SCLKA 2M SCLK MPLL SCLK E PLL SCLK V PLL XXTI XusbXTI SCLK _ HDMI 27 M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLKM PLL SCLKE PLL SCLKV PLL XXTI XusbXTI SCLK _ HDMI 27 M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLKM PLL SCLK E PLL SCLK V PLL XXTI XusbXTI SCLK _ HDMI 27 M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLKM PLL SCLK E PLL SCLK V PLL XXTI XusbXTI SCLK _ HDMI 27 M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLKM PLL SCLK E PLL SCLK V PLL XXTI XusbXTI SCLK _ HDMI 27 M SCLK _ USBPHY 0 SCLK _ USBPHY 1 SCLK _ HDMIPHY SCLKM PLL SCLK E PLL SCLK V PLL SCLK _ AUDIO 0 SCLK _ AUDIO 1 SCLK _ AUDIO 2 MUX MFC MOUT MFC DIV MFC ( 1 ~ 16) MUXG 3D MOUTG3 D DIVG3 D (1 ~ 16) MUX G2 D MOUT G2 D DIVG2 D ( 1 ~ 16) MUXCSIS MOUT CSIS DIV CSIS (1 ~ 16) MUX SPI0~2 MOUTSPI 0~2 DIV SPI 0 ~ 2 ( 1 ~ 16) MUXPWI MOUTPWI DIV PWI ( 1 ~ 16) MUX UART 0~3 DIVUART 0~3 MOUT UART 0~3 ( 1~ 16) MUX PWM MOUT PWM DIV PWM ( 1 ~ 16) SCLK _ MFC SCLK _G 3D SCLK _G2 D SCLK _ CSIS SCLK _SPI0~ 2 SCLK _ PWI SCLK _ UART0 ~ 3 SCLK _ PWM MUX SPDIF SCLK _ SPDIF MUXFIMC _ LCLK DIVFIMC_LCLK (1~16) MOUTFIMC _ LCLK SCLK_ FIMC_ LCLK Figure 3-3 S5PV210 Clock Generation Circuit 1 3-9 S5PV210_UM 3 2BCLOCK CONTROLLER Clock Domain MSYS Table 3-5 Maximum Operating Frequency for Each Sub-block Max. Freq. Module 200 MHz Cortex-A8, MFC, 3D TZIC0, TZIC1, TZIC2, TZIC3, VIC0, VIC1, VIC2, VIC3 DMC0, DMC1 AXI_MSYS, AXI_MSFR, AXI_MEM 100 MHz IRAM, IROM, TZPC0 DSYS PSYS 166 MHz 83 MHz 133 MHz 66MHz FIMC0, FIMC1, FIMC2, FIMD, DSIM, CSIS, JPEG, Rotator, VP, MIXER, TVENC, HDMI, MDMA, G2D DSIM, CSIS, I2C_HDMI_PHY, I2C_HDMI_DDC CSSYS, SECJTAG, HOST I/F, MODEM I/F CFCON, NFCON, SROMC, ONE NANDxl PDMA0, PDMA1 SECSS HSMMC0, HSMM1, HSMMC2 USB OTG, USB HOST SYSCON, GPIO, CHIPID, APC, IEC, TZPC1, SPI0, SPI1, I2S1, I2S2, PCM0, PCM1, AC97, SPDIF, I2C0, I2C2, KEYIF, TSADC, PWM, ST, WDT, RTC, UART 3-10 S5PV210_UM 3 2BCLOCK CONTROLLER 3.5 CLOCK CONFIGURATION PROCEDURE Rules to follow when the clock configuration changes: • All inputs of a glitch-free mux must run. • When a PLL is power-off, you should not select the output of PLL. Basic SFR configuration flows: Turn on a PLL (A,M,E,V)PLL_CON[31] = 1; wait_lock_time; (A, M, E, V)PLL_SEL = 1; // Power on a PLL (Refer to (A, M, E, V) PLL_CON SFR) // Wait until the PLL is locked // Select the PLL output clock instead of input reference clock, after PLL output clock is stabilized. (Refer to 0, 4, 8, 12th bit of CLK_SRC0 SFR) Turn “OFF” a PLL (A,M,E,V)PLL_SEL = 0; (A,M,E,V)PLL_CON[31] = 0; // De-select the output of a PLL // Power “OFF” the PLL Change PLL’s PMS values Set PMS values; // Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V) PLL_CON SFR) Change the system clock divider values CLK_DIV0 [31:0] = target value0; Change the divider values for special clocks CLK_DIV1 [31:0] = target value1; CLK_DIV2 [31:0] = target value2; 3.5.1 CLOCK GATING S5PV210 can disable the clock operation of each IP if it is not required. This reduces dynamic power. 3-11 S5PV210_UM 3 2BCLOCK CONTROLLER 3.6 SPECIAL CLOCK DESCRIPTION 3.6.1 SPECIAL CLOCK TABLE Name SCLK_ONENAND SCLK_G3D SCLK_MFC SCLK_CAM0,1 SCLK_FIMD SCLK_TVENC SCLK_DAC SCLK_MIXER SCLK_HDMI SCLK_PIXEL SCLK_SPDIF SCLK_MMC0,1,2 SCLK_USB_OHCI SCLK_USB_PHY SCLK_AUDIO0,1,2 SCLK_PWI SCLK_SRCLK SCLK_SPI0,1,2 SCLK_UART0,1,2,3 Table 3-6 Special Clocks in S5PV210 Description ONE NAND operating clock G3D core operating clock MFC core operating clock Reference clock for external CAM device FIMD operating clock TVENC/ DAC clock DAC clock MIXER clock HDMI LINK clock HDMI PIXEL clock SPDIF operating clock HSMMC operating clock USB OTG clock USB OTG clock AUDIO operating clock (PCM, I2S) IEM APC operating clock KEY I/F or TSADC filter clock SPI operating clock UART operating clock Range ~166 MHz (SCLK_ONENAND) ~200 MHz ~200 MHz CAM spec 54 MHz 54 MHz 48MHz 30MHz (A, M)PLL Source (A, M, E, V)PLL (A, M, E, V)PLL All possible clock sources All possible clock sources VPLL, HDMI PHY output VPLL, HDMI PHY output VPLL, HDMI PHY output All possible clock sources All possible clock sources SCLK_AUDIO0~2 All possible clock sources USB PHY USB PHY All possible clock sources All possible clock sources XXTI, XUSBXTI All possible clock sources All possible clock sources All possible clock sources include XXTI, XUSBXTI, SCLK_HDMI27M, SCLK_USBPHY, SCLK_HDMIPHY, SCLKMPLL, SCLKEPLL, and SCLKVPLL. XXTI and XUSBXTI mean external crystal and USB 48 MHz crystal, respectively. APLL and MPLL mean output clock of APLL and MPLL, respectively. 3-12 S5PV210_UM 3 2BCLOCK CONTROLLER SCLK_USBPHY means USB PHY 48 MHz output clock. SCLK_HDMI27M means HDMI PHY (27 MHz reference clock) output. SCLK_HDMIPHY means HDMI PHY (PIXEL_CLKO) output clock. SCLKMPLL, SCLKEPLL, and SCLKVPLL mean output clock of MPLL, EPLL, and EPLL, respectively. Name IOCLK_CFCON IOCLK_AC97 IOCLK_I2S0,1,2 IOCLK_PCM0,1,2 IOCLK_SPDIF0,1,2 IOCLK_PWM Table 3-7 I/O Clocks in S5PV210 I/O PAD Type Description CFCON I/O clock to receive data IN Muxed AC97 bit clock IN Muxed I2S CODEC clock IN Muxed PCM CODEC clock IN Muxed SPDIF input clock IN Muxed PWM input clock 3-13 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7 REGISTER DESCRIPTION System controller controls PLL, clock generator, the power management unit (PMU), and other system dependent units. This section describes how to control these parts using Special Functional Register (SFR) within the system controller. Do not change any reserved area. Changing value of Reserved area can lead to undefined behavior. 3.7.1 REGISTER MAP Register APLL_LOCK Reserved MPLL_LOCK Reserved EPLL_LOCK Reserved VPLL_LOCK Reserved APLL_CON0 APLL_CON1 MPLL_CON Reserved EPLL_CON0 EPLL_CON1 Reserved VPLL_CON Reserved CLK_SRC0 CLK_SRC1 CLK_SRC2 CLK_SRC3 CLK_SRC4 CLK_SRC5 CLK_SRC6 Reserved CLK_SRC_MASK0 Address 0xE010_0000 0xE010_0004 0xE010_0008 0xE010_000C 0xE010_0010 0xE010_0014~ 0xE010_001C 0xE010_0020 0xE010_0024~ 0xE010_00FC 0xE010_0100 0xE010_0104 0xE010_0108 0xE010_010C 0xE010_0110 0xE010_0114 0xE010_0118~ 0xE010_011C 0xE010_0120 0xE010_0124~ 0xE010_01FC 0xE010_0200 0xE010_0204 0xE010_0208 0xE010_020C 0xE010_0210 0xE010_0214 0xE010_0218 0xE010_021C~ 0xE010_027C 0xE010_0280 R/W Description R/W Control PLL locking period for APLL. - Reserved R/W Control PLL locking period for MPLL. - Reserved R/W Control PLL locking period for EPLL. - Reserved R/W Control PLL locking period for VPLL. - Reserved R/W Control PLL output frequency for APLL. R/W Control PLL AFC (Adaptive Frequency Calibrator) R/W Control PLL output frequency for MPLL. - Reserved R/W Control PLL output frequency for EPLL. R/W Control PLL output frequency for EPLL. - Reserved R/W Control PLL output frequency for VPLL. - Reserved R/W Select clock source 0 (Main) R/W Select clock source 1 (Multimedia) R/W Select clock source 2 (Multimedia) R/W Select clock source 3 (Multimedia) R/W Select clock source 4 (Connectivity) R/W Select clock source 5 (Connectivity) R/W Select clock source 6 (Audio) - Reserved R/W Clock source mask 0 Reset Value 0x0000_0FFF 0x0000_0FFF 0x0000_0FFF - 0x0000_0FFF - 0x00C8_0301 0x0000_0000 0x014D_0301 - 0x0885_0302 0x0000_0000 - 0x006C_0303 - 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 0xFFFF_FFFF 3-14 S5PV210_UM 3 2BCLOCK CONTROLLER Register CLK_SRC_MASK1 Reserved CLK_DIV0 CLK_DIV1 CLK_DIV2 CLK_DIV3 CLK_DIV4 CLK_DIV5 CLK_DIV6 CLK_DIV7 Reserved CLK_GATE_IP0 CLK_GATE_IP1 CLK_GATE_IP2 CLK_GATE_IP3 CLK_GATE_IP4 Reserved CLK_GATE_BLOCK CLK_GATE_IP5 Reserved CLK_OUT Reserved CLK_DIV_STAT0 CLK_DIV_STAT1 Reserved CLK_MUX_STAT0 CLK_MUX_STAT1 Reserved SWRESET Reserved Address 0xE010_0284 0xE010_0288~ 0xE010_02FC 0xE010_0300 0xE010_0304 0xE010_0308 0xE010_030C 0xE010_0310 0xE010_0314 0xE010_0318 0xE010_031C 0xE010_0320~ 0xE010_045C 0xE010_0460 0xE010_0464 0xE010_0468 0xE010_046C 0xE010_0470 0xE010_0474~ 0xE010_047C 0xE010_0480 0xE010_0484 0xE010_0488~ 0xE010_04FC 0xE010_0500 0xE010_0504~ 0xE010_0FFC 0xE010_1000 0xE010_1004 0xE010_1008~ 0xE010_10FC 0xE010_1100 0xE010_1104 0xE010_1108~ 0xE010_1FFC 0xE010_2000 0xE010_2004~ 0xE010_2FFC R/W Description R/W Clock source mask 1 - Reserved R/W Set clock divider ratio 0 (System Clocks) R/W Set clock divider ratio 1 (Multimedia) R/W Set clock divider ratio 2 (Multimedia) R/W Set clock divider ratio 3 (Multimedia) R/W Set clock divider ratio 4 (Connectivity) R/W Set clock divider ratio 5 (Connectivity) R/W Set clock divider ratio 6 (Audio & Others) R/W Set clock divider ratio 7 (IEM_IEC) - Reserved R/W Control IP clock gating R/W Control IP clock gating R/W Control IP clock gating R/W Control IP clock gating R/W Control IP clock gating - Reserved R/W Control block clock gating R/W Control IP clock gating - Reserved R/W Select clock output - Reserved R Clock divider status (CLK_DIV0~3) R Clock divider status 1 (CLK_DIV4~5) - Reserved R Clock MUX status 0 R Clock MUX status 1 - Reserved R/W Generate software reset - Reserved Reset Value 0xFFFF_FFFF - 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF - 0xFFFF_FFFF 0xFFFF_FFFF - 0x0000_0000 - 0x0000_0000 0x0000_0000 - 0x1111_1111 0x0001_0000 - 0x0000_0000 - 3-15 S5PV210_UM 3 2BCLOCK CONTROLLER Register DCGIDX_MAP0 DCGIDX_MAP1 DCGIDX_MAP2 Reserved DCGPERF_MAP0 DCGPERF_MAP1 Reserved DVCIDX_MAP Reserved FREQ_CPU FREQ_DPM Reserved DVSEMCLK_EN MAXPERF Reserved APLL_CON0_L8 APLL_CON0_L7 APLL_CON0_L6 APLL_CON0_L5 APLL_CON0_L4 APLL_CON0_L3 APLL_CON0_L2 APLL_CON0_L1 Reserved CLKDIV_IEM_L8 CLKDIV_IEM_L7 CLKDIV_IEM_L6 CLKDIV_IEM_L5 CLKDIV_IEM_L4 Address 0xE010_3000 0xE010_3004 0xE010_3008 0xE010_300C~ 0xE010_301C 0xE010_3020 0xE010_3024 0xE010_3028~ 0xE010_303C 0xE010_3040 0xE010_3044~ 0xE010_305C 0xE010_3060 0xE010_3064 0xE010_3068~ 0xE010_307C 0xE010_3080 0xE010_3084 0xE010_3088~ 0xE010_30FC 0xE010_3100 0xE010_3104 0xE010_3108 0xE010_310C 0xE010_3110 0xE010_3114 0xE010_3118 0xE010_311C 0xE010_3120~ 0xE010_31FC 0xE010_3200 0xE010_3204 0xE010_3208 0xE010_320C 0xE010_3210 R/W Description R/W DCG index map 0 R/W DCG index map 1 R/W DCG index map 2 - Reserved R/W DCG performance map 0 R/W DCG performance map 1 - Reserved R/W DVC index map - Reserved R/W Maximum frequence of CPU R/W Frequency of DPM accumulators - Reserved R/W DVS emulation clock enable R/W MAX performance enable - Reserved R/W APLL control (performance level-8) R/W APLL control (performance level-7) R/W APLL control (performance level-6) R/W APLL control (performance level-5) R/W APLL control (performance level-4) R/W APLL control (performance level-3) R/W APLL control (performance level-2) R/W APLL control (performance level-1) - Reserved R/W Clock divider for IEM (performance level8) R/W Clock divider for IEM (performance level7) R/W Clock divider for IEM (performance level6) R/W Clock divider for IEM (performance level5) R/W Clock divider for IEM (performance level- Reset Value 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF - 0xFFFF_FFFF 0xFFFF_FFFF - 0x00FF_FFFF - 0x0000_0000 0x0000_0000 - 0x0000_0000 0x0000_0000 - 0x00C8_0301 0x00C8_0301 0x00C8_0301 0x00C8_0301 0x00C8_0301 0x00C8_0301 0x00C8_0301 0x00C8_0301 - 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 3-16 S5PV210_UM 3 2BCLOCK CONTROLLER Register Address CLKDIV_IEM_L3 0xE010_3214 CLKDIV_IEM_L2 0xE010_3218 CLKDIV_IEM_L1 0xE010_321C Reserved APLL_CON1_L8 APLL_CON1_L7 APLL_CON1_L6 APLL_CON1_L5 APLL_CON1_L4 APLL_CON1_L3 APLL_CON1_L2 APLL_CON1_L1 Reserved DISPLAY_CONTROL AUDIO_ENDIAN 0xE010_3220~ 0xE010_32FC 0xE010_3300 0xE010_3304 0xE010_3308 0xE010_330C 0xE010_3310 0xE010_3314 0xE010_3318 0xE010_331C 0xE010_3320~ 0xE010_7004 0xE010_7008 0xE010_700C R/W 4) Description R/W Clock divider for IEM (performance level3) R/W Clock divider for IEM (performance level2) R/W Clock divider for IEM (performance level1) - Reserved R/W Control PLL AFC (performance level-1) R/W Control PLL AFC (performance level-7) R/W Control PLL AFC (performance level-6) R/W Control PLL AFC (performance level-5) R/W Control PLL AFC (performance level-4) R/W Control PLL AFC (performance level-3) R/W Control PLL AFC (performance level-2) R/W Control PLL AFC (performance level-1) - Reserved R/W Display output path selection. R/W Endian selection for audio subsystem Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 - 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 0x0000_0000 0x0000_0000 SFRs consist of several parts. The SFRs with address 0xE010_0XXX controls clock-related logics. They control the output frequency of three PLLs, clock source selection, clock divider ratio, and clock gating. The SFRs with address 0xE010_2XXX controls SW reset. The SFRs with address 0xE010_3XXX controls IEM block. The SFRs with address 0xE010_6XXX controls S5PV210 system. The SFRs withe address 0xE010_7XXX include miscellaneous registers. The SFRs with address 0xE010_8XXX controls the power management block. 3-17 S5PV210_UM 3 2BCLOCK CONTROLLER S5PV210 has four internal PLLs, namely, APLL, MPLL, EPLL, and VPLL. The four internal PLLs are controlled by the following eight special registers: 3.7.2 PLL CONTROL REGISTERS 3.7.2.1 PLL Control Registers (APLL_LOCK / MPLL_LOCK / EPLL_LOCK / VPLL_LOCK) • (APLL_LOCK, R/W, Address = 0xE010_0000) • (MPLL_LOCK, R/W, Address = 0xE010_0008) • (EPLL_LOCK, R/W, Address = 0xE010_0010) • (VPLL_LOCK, R/W, Address = 0xE010_0020) A PLL requires locking period when input frequency is changed or frequency division (multiplication) values are changed. PLL_LOCK register specifies this locking period, which is based on PLL’s source clock. During this period, output will be masked ‘0’. APLL_LOCK / MPLL_LOCK / EPLL_LOCK / VPLL_LOCK Reserved PLL_LOCKTIME Bit Description [31:16] Reserved [15:0] Required period to generate a stable clock output Initial State 0x0000 0x0FFF 3-18 S5PV210_UM 3 2BCLOCK CONTROLLER PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates output after PLL locking period. The MDIV, PDIV, and SDIV values control the output frequency of PLL. The PLL also generates the output frequency when MDIV, PDIV, and VSEL are changed. However, the PLL locking period is not applied if only SDIV is changed. PLL Control Registers (APLL_CON0/APLL_CON1, R/W, Address = 0xE010_0100/0xE010_0104) APLL_CON0 ENABLE Reserved LOCKED Reserved MDIV Reserved PDIV Reserved SDIV Bit [31] [30] [29] [28:26] [25:16] [15:14] [13:8] [7:3] [2:0] Description PLL enable control (0: disable, 1: enable) Reserved PLL locking indication 0 = Unlocked 1 = Locked Read Only Reserved PLL M divide value Reserved PLL P divide value Reserved PLL S divide value Initial State 0 0 0 0x0 0xC8 0 0x3 0 0x1 The reset value of APLL_CON0 generates 800 MHz output clock, if the input clock frequency is 24 MHz. Equation to calculate the output frequency: FOUT = MDIV X FIN / (PDIV × 2SDIV-1) where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions : PDIV: 1 ≤ PDIV ≤ 63 MDIV: 64 ≤ MDIV ≤ 1023 SDIV: 1 ≤ SDIV ≤ 5 Fref (=FIN / PDIV): 1MHz ≤ Fref ≤ 12MHz FVCO (=2 × MDIV × FIN / PDIV): 1000MHz ≤ FVCO ≤ 2060MHz Refer to 3.3.1 Recommended PLL PMS Value for APLL for recommended PMS values. Caution: APLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop, sleep mode. APLL will be automatically turned off while entering those low-power modes. 3-19 S5PV210_UM 3 2BCLOCK CONTROLLER APLL_CON1 AFC_ENB Reserved AFC Bit [31] [30:5] [4:0] Description Decides whether AFC is enabled or not. Active low. AFC selects adaptive frequency curve of VCO for wide range, high phase noise (or jitter) and fast lock time. (LOW: AFC is enabled, HIGH: AFC is disabled) Users should refer to 3.3.1 on whether to use AFC for a given P/M/S values. Reserved AFC value Users should refer to 3.3.1 on the recommended AFC value for a given scenario. Initial State 0x0 0x0 0x0 3-20 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.2.2 PLL Control Registers (MPLL_CON, R/W, Address = 0xE010_0108) MPLL_CON ENABLE Reserved LOCKED Reserved VSEL Reserved MDIV Reserved PDIV Reserved SDIV Bit Description [31] PLL enable control (0: disable, 1: enable) [30] Reserved [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only [28] Reserved [27] VCO frequency range selection [26] Reserved [25:16] PLL M divide value [15:14] Reserved [13:8] PLL P divide value [7:3] Reserved [2:0] PLL S divide value Initial State 0 0 0 0 0x0 0 0x14D 0 0x3 0 0x1 The reset value of APLL_CON0 and MPLL_CON generates 800 MHz and 667 MHz output clock respectively, if the input clock frequency is 24 MHz. Equation to calculate the output frequency: FOUT = MDIV X FIN / (PDIV X 2SDIV) where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions : PDIV: 1 ≤ PDIV ≤ 63 MDIV: 16 ≤ MDIV ≤ 511 SDIV: 0 ≤ SDIV ≤ 5 Fref (=FIN / PDIV): 1MHz ≤ Fref ≤ 10MHz FVCO (=MDIV X FIN / PDIV): 1000MHz ≤ FVCO ≤ 1400MHz when VSEL=LOW. 1400MHz ≤ FVCO ≤ 2000MHz when VSEL=HIGH. FOUT: 32MHz ≤ FOUT ≤ 2000MHz Refer to 3.3.2 Recommended PLL PMS Value for MPLL for recommended PMS values. Caution: MPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop, sleep mode. MPLL will be automatically turned off while entering those low-power modes. 3-21 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.2.3 PLL Control Registers (EPLL_CON0/ EPLL_CON1, R/W, Address = 0xE010_0110/0xE010_0114) EPLL_CON0 ENABLE Reserved LOCKED Bit Description [31] PLL enable control (0: disable, 1: enable) [30] Reserved [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only Initial State 0x0 0x0 0x0 Reserved [28] Reserved 0x0 VSEL [27] VCO frequency range selection 0x1 Reserved MDIV Reserved PDIV Reserved SDIV [26:25] Reserved [24:16] PLL M divide value [15:14] Reserved [13:8] PLL P divide value [7:3] Reserved [2:0] PLL S divide value 0x0 0x85 0x0 0x3 0x0 0x2 EPLL_CON1 Reserved K Bit Description [31:16] Reserved [15:0] PLL K value. K value is used to fine-tune M divider value to meet FOUT requirement exactly. For this purpose, MDIV+K/65536 is used for M divider value. Also called as DSM (Delta-Sigma Modulator). Initial State 0x0 0x0 The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively, if the input clock frequency is 24 MHz. Equation to calculate the output frequency: FOUT = (MDIV+K/65536) X FIN / (PDIV X 2SDIV) where, MDIV, PDIV, SDIV for PLLs must meet the following conditions : PDIV: 1 ≤ PDIV ≤ 63 MDIV: 16 ≤ MDIV ≤ 511 SDIV: 0 ≤ SDIV ≤ 5 K: 0 ≤ SDIV ≤ 65535 Fref (=FIN / PDIV): 4MHz ≤ Fref ≤ 30MHz FVCO (=MDIV X FIN / PDIV): 330MHz ≤ FVCO ≤ 460MHz when VSEL=LOW. 3-22 S5PV210_UM 3 2BCLOCK CONTROLLER 460MHz ≤ FVCO ≤ 660MHz when VSEL=HIGH. FOUT: 12MHz ≤ FOUT ≤ 660MHz Refer to 3.3.3 Recommended PLL PMS Value for EPLL for recommended PMS values. Caution: EPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop, sleep mode. EPLL will be automatically turned off while entering those low-power modes. 3-23 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.2.4 PLL Control Registers (VPLL_CON, R/W, Address = 0xE010_0120) VPLL_CON ENABLE Reserved LOCKED Reserved VSEL Bit Description [31] PLL enable control (0: disable, 1: enable) [30] Reserved [29] PLL locking indication 0 = Unlocked 1 = Locked Read Only [28] Reserved [27] VCO frequency range selection Initial State 0 0 0 0 0x0 Reserved MDIV Reserved PDIV Reserved SDIV [26:25] Do not change [24:16] PLL M divide value [15:14] Reserved [13:8] PLL P divide value [7:3] Reserved [2:0] PLL S divide value 0 0x6C 0 0x3 0 0x3 The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively, if the input clock frequency is 24 MHz. Equation to calculate the output frequency: FOUT = MDIV X FIN / (PDIV X 2SDIV) where, MDIV, PDIV, SDIV for PLLs must meet the following conditions : PDIV: 1 ≤ PDIV ≤ 63 MDIV: 16 ≤ MDIV ≤ 511 SDIV: 0 ≤ SDIV ≤ 5 Fref (=FIN / PDIV): 2MHz ≤ Fref ≤ 6MHz FVCO (=MDIV X FIN / PDIV): 330MHz ≤ FVCO ≤ 460MHz when VSEL=LOW. 460MHz ≤ FVCO ≤ 660MHz when VSEL=HIGH. FOUT : 12MHz ≤ FOUT ≤ 660MHz Refer to 3.3.4 Recommended PLL PMS Value for VPLL for recommended PMS values. Caution: VPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop, sleep mode. VPLL will be automatically turned off while entering those low-power modes. 3-24 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3 CLOCK SOURCE CONTROL REGISTERS S5PV210 has many clock sources, which include four PLL outputs, the external oscillator, the external clock, and other clock sources from GPIO. CLK_SRCn registers control the source clock of each clock divider. 3.7.3.1 Clock Source Control Registers (CLK_SRC0, R/W, Address = 0xE010_0200) CLK_SRC0 Reserved ONENAND_SEL Reserved MUX_PSYS_SEL Reserved MUX_DSYS_SEL Reserved MUX_MSYS_SEL Reserved VPLL_SEL Reserved EPLL_SEL Reserved MPLL_SEL Reserved APLL_SEL Bit [31:29] [28] [27:25] [24] [23:21] [20] [19:17] [16] [15:13] [12] [11:9] [8] [7:5] [4] [3:1] [0] Description Reserved Control MUXFLASH (0:HCLK_PSYS, 1:HCLK_DSYS) Reserved Control MUX_PSYS (0:SCLKMPLL, 1:SCLKA2M) Reserved Control MUX_DSYS (0:SCLKMPLL, 1:SCLKA2M) Reserved Control MUX_MSYS (0:SCLKAPLL, 1:SCLKMPLL) Reserved Control MUXVPLL (0: FINVPLL, 1: FOUTVPLL) Reserved Control MUXEPLL (0:FINPLL, 1:FOUTEPLL) Reserved Control MUXMPLL (0:FINPLL, 1:FOUTMPLL) Reserved Control MUXAPLL (0:FINPLL, 1:FOUTAPLL) Initial State 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 3-25 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.2 Clock Source Control Registers (CLK_SRC1, R/W, Address = 0xE010_0204) CLK_SRC1 Reserved VPLLSRC_SEL CSIS_SEL FIMD_SEL CAM1_SEL CAM0_SEL Reserved DAC_SEL Reserved MIXER_SEL Reserved HDMI_SEL Bit [31:29] [28] [27:24] [23:20] [19:16] [15:12] [11:9] [8] [7:5] [4] [3:1] [0] Description Reserved Control MUXVPLLSRC, which is the source clock of VPLL (0: Oscillator clock, 1: HDMI reference clock) Control MUXCSIS, which is the source clock of CSIS (0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXFIMD, which is the source clock of FIMD (0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXCAM1, which is the source clock of CAM0 (0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXCAM0, which is the source clock of CAM0 (0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Reserved Control MUXDAC, which is the source clock of TVENC and DAC (0:SCLKVPLL, 1: SCLK_HDMIPHY) Reserved Control MUXMIXER, which is the source clock of MIXER (0:SCLK_DAC, 1: SCLK_HDMI) Reserved Control MUXHDMI, which is the source clock of HDMI link (0:SCLK_PIXEL, 1: SCLK_HDMIPHY) Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 3-26 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.3 Clock Source Control Registers (CLK_SRC2, R/W, Address = 0xE010_0208) CLK_SRC2 Reserved G2D_SEL Reserved MFC_SEL Reserved G3D_SEL Bit [31:10] [9:8] [7:6] [5:4] [3:2] [1:0] Description Reserved Control MUXG2D, which is the source clock of G2D core (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) Reserved Control MUXMFC, which is the source clock of MFC core (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) Reserved Control MUXG3D, which is the source clock of G3D core (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) Initial State 0x0 0x0 0x0 0x0 0x0 0x0 3-27 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.4 Clock Source Control Registers (CLK_SRC3, R/W, Address = 0xE010_020C) CLK_SRC3 Reserved FIMC_LCLK_SEL F1 F0 Reserved Bit [31:24] [23:20] [19:16] [15:12] [11:0] Description Reserved Control MUXFIMC_LCLK, which is the source clock of FIMC2 local clock (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Should have same value as FIMC_LCLK_SEL Should have same value as FIMC_LCLK_SEL Reserved Initial State 0x00 0x0 0x0 0x0 0x0 3-28 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.5 Clock Source Control Registers (CLK_SRC4, R/W, Address = 0xE010_0210) CLK_SRC4 UART3_SEL UART2_SEL UART1_SEL UART0_SEL MMC3_SEL MMC2_SEL MMC1_SEL MMC0_SEL Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description Control MUXUART3, which is the source clock of UART3 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXUART2, which is the source clock of UART2 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXUART1, which is the source clock of UART1 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXUART0, which is the source clock of UART0 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXMMC3, which is the source clock of MMC3 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXMMC2, which is the source clock of MMC2 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXMMC1, which is the source clock of MMC1 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXMMC0, which is the source clock of MMC0 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 3-29 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.6 Clock Source Control Registers (CLK_SRC5, R/W, Address = 0xE010_0214) CLK_SRC5 Reserved PWM_SEL Reserved SPI1_SEL SPI0_SEL Bit [31:16] [15:12] [11:8] [7:4] [3:0] Description Reserved Control MUXPWM, which is the source clock of PWM (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Reserved Control MUXSPI1, which is the source clock of SPI1 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXSPI0, which is the source clock of SPI0 (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Initial State 0x0 0x0 0x0 0x0 0x0 3-30 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.7 Clock Source Control Registers (CLK_SRC6, R/W, Address = 0xE010_0218) CLK_SRC6 Reserved DMC0_SEL PWI_SEL Reserved HPM_SEL Reserved SPDIF_SEL AUDIO2_SEL AUDIO1_SEL AUDIO0_SEL Bit [31:26] [25:24] [23:20] [19:17] [16] [15:14] [13:12] [11:8] [7:4] [3:0] Description Reserved Control MUXDMC0, which is the source clock of DMC0 (00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL, 11:SCLKVPLL) Control MUXPWI, which is the source clock of PWI (0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Reserved Control MUXHPM, which is the source clock of HPM (0: SCLKAPLL, 1: SCLKMPLL) Reserved Control MUXSPDIF, which is the source clock of SPDIF (00:SCLK_AUDIO0, 01:SCLK_AUDIO1, 1x:SCLK_AUDIO2) Control MUXAUDIO2, which is the source clock of AUDIO2 (0000: I2SCDCLK2, 0001: PCMCDCLK2, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPHY1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: rerved) Control MUXAUDIO1, which is the source clock of AUDIO1 (0000: I2SCDCLK1, 0001: PCMCDCLK1, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPHY1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000: SCLKVPLL, OTHERS: reserved) Control MUXAUDIO0, which is the source clock of AUDIO0 (0000: XXTI, 0001: PCMCDCLK0, 0010: SCLK_HDMI27M, 0011: SCLK_USBPHY0, 0100: SCLK_USBPHY1, 0101: SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 100: SCLKVPLL, OTHERS: reserved) Initial State 0x00 0x0 0x0 0 0x0 0x0 0x0 0x0 0x0 0x0 3-31 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.8 Clock Source Control Registers (CLK_SRC_MASK0, R/W, Address = 0xE010_0280) CLK_SRC_MASK0 Reserved PWI_MASK Reserved SPDIF_MASK AUDIO2_MASK AUDIO1_MASK AUDIO0_MASK Reserved PWM_MASK Reserved SPI1_MASK SPI0_MASK UART3_MASK UART2_MASK UART1_MASK UART0_MASK MMC3_MASK MMC2_MASK MMC1_MASK MMC0_MASK FINVPLL_MASK CSIS_MASK FIMD_MASK CAM1_MASK CAM0_MASK DAC_MASK MIXER_MASK HDMI_MASK Bit [31:30] [29] [28] [27] [26] [25] [24] [23:20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Mask output clock of MUXPWI (0: disable, 1: enable) Reserved Mask output clock of MUXSPDIF (0: disable, 1: enable) Mask output clock of MUXAUDIO2 (0: disable, 1: enable) Mask output clock of MUXAUDIO1 (0: disable, 1: enable) Mask output clock of MUXAUDIO0 (0: disable, 1: enable) Reserved Mask output clock of MUXPWM (0: disable, 1: enable) Reserved Mask output clock of MUXSPI1 (0: disable, 1: enable) Mask output clock of MUXSPI0 (0: disable, 1: enable) Mask output clock of MUXUART3 (0: disable, 1: enable) Mask output clock of MUXUART2 (0: disable, 1: enable) Mask output clock of MUXUART1 (0: disable, 1: enable) Mask output clock of MUXUART0 (0: disable, 1: enable) Mask output clock of MUXMMC3 (0: disable, 1: enable) Mask output clock of MUXMMC2 (0: disable, 1: enable) Mask output clock of MUXMMC1 (0: disable, 1: enable) Mask output clock of MUXMMC0 (0: disable, 1: enable) Mask output clock of MUXVPLLSRC (0: disable, 1: enable) Mask output clock of MUXCSIS (0: disable, 1: enable) Mask output clock of MUXFIMD (0: disable, 1: enable) Mask output clock of MUXCAM1 (0: disable, 1: enable) Mask output clock of MUXCAM0 (0: disable, 1: enable) Mask output clock of MUXDAC (0: disable, 1: enable) Mask output clock of MUXMIXER (0: disable, 1: enable) Mask output clock of MUXHDMI (0: disable, 1: enable) Initial State 0x3 1 1 1 1 1 1 0xF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3-32 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.3.9 Clock Source Control Registers (CLK_SRC_MASK1, Address = R/W, 0xE010_0284) CLK_SRC_MASK1 Reserved FIMC_LCLK_MASK F1 F0 Reserved Bit [31:7] [4] [3] [2] [1:0] Description Reserved Mask output clock of MUXFIMC_LCLK (0: disable, 1: enable) Should have same value as FIMC_LCLK_MASK Should have same value as FIMC_LCLK_MASK Reserved Initial State 0x7FF_FFFF 1 1 1 0x3 3-33 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.4 CLOCK DIVIDER CONTROL REGISTER S5PV210 has several clock dividers to support various operating clock frequency. The clock divider ratio can be controlled by CLK_DIV0, CLK_DIV1, 2, 3, 4, and 5. There are operating frequency limitations. The maximum operating frequency of SCLKAPLL, SCLKMPLL, SCLKA2M, HCLK_MSYS, and PCLK_MSYS are 800 MHz, 667 MHz, 400 MHz, 200 MHz, and 100 MHz, respectively. These operating clock conditions must be met through CLK_DIVX configuration. Divider for internal memory shown as DIVIMEM in Figure 3-3 does not have corresponding fields in clock divider control registers since the divider value is fixed to two. Whenever clock divider control register is changed, it is recommended to check clock divider status registers before using the new clock output. This guarantees corresponding divider finishes changing to a new dividing value before it's output is used by other modules. 3.7.4.1 Clock Divider Control Register (CLK_DIV0, R/W, Address = 0xE010_0300) CLK_DIV0 Reserved PCLK_PSYS_RATIO HCLK_PSYS_RATIO Reserved PCLK_DSYS_RATIO HCLK_DSYS_RATIO Reserved PCLK_MSYS_RATIO Reserved HCLK_MSYS_RATIO Reserved A2M_RATIO Reserved APLL_RATIO Bit [31] [30:28] [27:24] [23] [22:20] [19:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved DIVPCLKP clock divider ratio, PCLK_PSYS = HCLK_PSYS / (PCLK_PSYS_RATIO + 1) DIVHCLKP clock divider ratio, HCLK_PSYS = MOUT_PSYS / (HCLK_PSYS_RATIO + 1) Reserved DIVPCLKD clock divider ratio, PCLK_DSYS = HCLK_DSYS / (PCLK_DSYS_RATIO + 1) DIVHCLKD clock divider ratio, HCLK_DSYS = MOUT_DSYS / (HCLK_DSYS_RATIO + 1) Reserved DIVPCLKM clock divider ratio, PCLK_MSYS = HCLK_MSYS / (PCLK_MSYS_RATIO + 1) Reserved DIVHCLKM clock divider ratio, HCLK_MSYS = ARMCLK / (HCLK_MSYS_RATIO + 1) Reserved DIVA2M clock divider ratio, SCLKA2M = SCLKAPLL / (A2M_RATIO + 1) Reserved DIVAPLL clock divider ratio, ARMCLK = MOUT_MSYS / (APLL_RATIO + 1) Initial State 0 0x0 0x0 0 0x0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 3-34 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.4.2 Clock Divider Control Register (CLK_DIV1, R/W, Address = 0xE010_0304) CLK_DIV1 CSIS_RATIO Reserved FIMD_RATIO CAM1_RATIO CAM0_RATIO Reserved TBLK_RATIO Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:4] [3:0] Description DIVCSIS clock divider ratio, SCLK_CSIS = MOUTCSIS / (CSIS_RATIO + 1) Reserved DIVFIMD clock divider ratio, SCLK_FIMD = MOUTFIMD / (FIMD_RATIO + 1) DIVCAM1 clock divider ratio, SCLK_CAM1 = MOUTCAM1 / (CAM1_RATIO + 1) DIVCAM0 clock divider ratio, SCLK_CAM0 = MOUTCAM0 / (CAM0_RATIO + 1) Reserved DIVTBLK clock divider ratio, SCLK_PIXEL= SCLKVPLL/ (TBLK_RATIO + 1) 3.7.4.3 Clock Divider Control Register (CLK_DIV2, R/W, Address = 0xE010_0308) CLK_DIV2 Reserved G2D_RATIO MFC_RATIO G3D_RATIO Bit [31:12] [11:8] [7:4] [3:0] Description Reserved DIVG2D clock divider ratio, SCLKG2D= MOUTG2D / (G2D_RATIO + 1) DIVMFC clock divider ratio, SCLKMFC= MOUTMFC / (MFC_RATIO + 1) DIVG3D clock divider ratio, SCLKG3D= MOUTG3D / (G3D_RATIO + 1) Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Initial State 0x00_0000 0x0 0x0 0x0 3-35 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.4.4 Clock Divider Control Register (CLK_DIV3, R/W, Address = 0xE010_030C) CLK_DIV3 Reserved FIMC_LCLK_RATIO F1 F0 Reserved Bit [31:24] [23:20] [19:16] [15:12] [11:0] Description Reserved DIVFIMC_LCLK clock divider ratio, SCLKFIMC_LCLK= MOUTFIMC_LCLK / (FIMC_LCLK_RATIO + 1) Should have same value as FIMC_LCLK_RATIO Should have same value as FIMC_LCLK_RATIO Reserved Initial State 0x00 0x0 0x0 0x0 0 3.7.4.5 Clock Divider Control Register (CLK_DIV4, R/W, Address = 0xE010_0310) CLK_DIV4 UART3_RATIO UART2_RATIO UART1_RATIO UART0_RATIO MMC3_RATIO MMC2_RATIO MMC1_RATIO MMC0_RATIO Bit [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] Description DIVUART3 clock divider ratio, SCLK_UART3 = MOUTUART3 / (UART3_RATIO + 1) DIVUART2 clock divider ratio, SCLK_UART2 = MOUTUART2 / (UART2_RATIO + 1) DIVUART1 clock divider ratio, SCLK_UART1 = MOUTUART1 / (UART1_RATIO + 1) DIVUART0 clock divider ratio, SCLK_UART0 = MOUTUART0 / (UART0_RATIO + 1) DIVMMC3 clock divider ratio, SCLK_MMC3 = MOUTMMC3 / (MMC3_RATIO + 1) DIVMMC2 clock divider ratio, SCLK_MMC2 = MOUTMMC2 / (MMC2_RATIO + 1) DIVMMC1 clock divider ratio, SCLK_MMC1 = MOUTMMC1 / (MMC1_RATIO + 1) DIVMMC0 clock divider ratio, SCLK_MMC0 = MOUTMMC0 / (MMC0_RATIO + 1) Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 3-36 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.4.6 Clock Divider Control Register (CLK_DIV5, R/W, Address = 0xE010_0314) CLK_DIV5 Reserved PWM_RATIO Reserved SPI1_RATIO SPI0_RATIO Bit Description [31:12] Reserved [15:12] DIVPWM clock divider ratio, SCLK_PWM = MOUTPWM / (PWM_RATIO + 1) [11:8] Reserved [7:4] DIVSPI1 clock divider ratio, SCLK_SPI1 = MOUTSPI1 / (SPI1_RATIO + 1) [3:0] DIVSPI0 clock divider ratio, SCLK_SPI0 = MOUTSPI0 / (SPI0_RATIO + 1) Initial State 0x0 0x0 0x0 0x0 0x0 3.7.4.7 Clock Divider Control Register (CLK_DIV6, R/W, Address = 0xE010_0318) CLK_DIV6 DMC0_RATIO PWI_RATIO Reserved HPM_RATIO Reserved COPY_RATIO Reserved ONENAND_RATIO AUDIO2_RATIO AUDIO1_RATIO AUDIO0_RATIO Bit [31:28] [27:24] [23] [22:20] [19] [18:16] [15] [14:12] [11:8] [7:4] [3:0] Description DIVDMC0 clock divider ratio, SCLK_DMC0 = MOUTDMC0 / (DMC0_RATIO + 1) DIVPWI clock divider ratio, SCLK_PWI = MOUTPWI / (PWI_RATIO + 1) Reserved DIVHPM clock divider ratio, SCLK_HPM = DOUTCOPY / (IEM_RATIO + 1) Reserved DIVCOPY clock divider ratio, DOUTCOPY = MOUTHPM / (COPY_RATIO + 1) Reserved DIVFLASH clock divider ratio, SCLK_ONENAND = MOUTFLASH / (ONENAND_RATIO + 1) DIVAUDIO2 clock divider ratio, SCLK_AUDIO2 = MOUTAUDIO2 / (AUDIO2_RATIO + 1) DIVAUDIO1 clock divider ratio, SCLK_AUDIO1 = MOUTAUDIO1 / (AUDIO1_RATIO + 1) DIVAUDIO0 clock divider ratio, SCLK_AUDIO0 = MOUTAUDIO0 / (AUDIO0_RATIO + 1) Initial State 0x0 0x0 0 0x0 0 0x0 0x0 0x0 0x0 0x0 0x0 3-37 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.4.8 Clock Divider Control Register (CLK_DIV7, R/W, Address = 0xE010_031C) CLK_DIV7 Reserved DPM_RATIO Reserved DVSEM_RATIO Bit Description [31:15] Reserved [14:8] CLK_DPM clock divider ratio. Source of DIVDPM clock divider is PCLK for IEM_IEC. DPM_RATIO decides how often DPM channel increments for IEM_IEC. Refer to Figure 3-3. [7] Reserved [6:0] CLK_DVSEM clock divider ratio Source of DIVDVSEM clock divider is PCLK for IEM_IEC. DVSEM_RATIO decides how often PWM frame time slot is advanced when IEM_IEC is in DVS emulation mode. It should be guaranteed DIVDVSEM clock runs at 1MHz. Refer to Figure 3-3. Initial State 0x0 0x0 0 0x0 3-38 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5 CLOCK GATING CONTROL REGISTER There are two types of clock gating control registers for disable/enable operation, namely: • Clock gating control register by block • Clock gating register for by IP The above two registers are ANDed together to generate a final clock gating enable signal. As a result, if either of the two register field is turned OFF, the resulting clock is stopped. 3.7.5.1 Clock Gating Control Register (CLK_GATE_SCLK, R/W, Address = 0xE010_0444) CLK_GATE_SCLK Reserved SCLK_FIMC_LCLK Bit [31:6] [5] Reserved [4:0] Description Reserved Gating special clock for FIMC local clock (0: mask, 1: pass) Should be one for all bit Gated Clock Name Reserved SCLK_FIMC_LCLK Reserved Initial State 0x3FF_FFFF 1 0x1F 3.7.5.2 Clock Gating Control Register (CLK_GATE_IP0, R/W, Address = 0xE010_0460) CLK_GATE_IP0 CLK_CSIS Bit Description [31] Gating all clocks for CSIS Reserved CLK_ROTATOR CLK_JPEG Reserved CLK_FIMC2 [30] Reserved [29] Gating all clocks for ROTATOR (0: mask, 1: pass) [28] Gating all clocks for JPEG (0: mask, 1: pass) [27] Reserved [26] Gating all clocks for FIMC2 (0: mask, 1: pass) CLK_FIMC1 CLK_FIMC0 Reserved CLK_MFC Reserved CLK_G2D [25] Gating all clocks for FIMC1 (0: mask, 1: pass) [24] Gating all clocks for FIMC0 (0: mask, 1: pass) [23:17] Reserved [16] Gating all clocks for MFC (0: mask, 1: pass) [15:13] Reserved [12] Gating all clocks for G2D Gated Clock Name PCLK_CSIS SCLK_CSIS Reserved ACLK_ROTATOR ACLK_JPEG Reserved ACLK_FIMC2 SCLK_FIMC_LCLK SCLK_CAM0, 1 ACLK_FIMC1 SCLK_CAM0, 1 ACLK_FIMC0 SCLK_CAM0, 1 Reserved PCLK_MFC SCLK_MFC Reserved ACLK_G2D SCLK_G2D Initial State 1 1 1 1 1 1 1 1 0x7F 1 0x7 0x1 3-39 S5PV210_UM CLK_GATE_IP0 Bit Description Reserved CLK_G3D Reserved CLK_IMEM CLK_PDMA1 CLK_PDMA0 CLK_MDMA CLK_DMC1 CLK_DMC0 [11:9] [8] [7:6] [5] [4] [3] [2] [1] [0] Reserved Gating all clocks for G3D (0: mask, 1: pass) Reserved Gating all clocks for IMEM (0: mask, 1: pass) Gating all clocks for PDMA1 (0: mask, 1: pass) Gating all clocks for PDMA0 (0: mask, 1: pass) Gating all clocks for MDMA (0: mask, 1: pass) Gating all clocks for DMC1 (0: mask, 1: pass) Gating all clocks for DMC0 (0: mask, 1: pass) 3 2BCLOCK CONTROLLER Gated Clock Name PCLK_G2D Reserved ACLK_G3D SCLK_G3D Reserved ACLK_IMEM Initial State 0x7 1 0x3 1 ACLK_PDMA1 1 PCLK_PDMA1 ACLK_PDMA0 1 PCLK_PDMA0 ACLK_MDMA 1 PCLK_MDMA ACLK_DMC1 1 PCLK_DMC1 SCLK_DMC0 1 ACLK_DMC0 PCLK_DMC0 3-40 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.3 Clock Gating Control Register (CLK_GATE_IP1, R/W, Address = 0xE010_0464) CLK_GATE_IP1 Reserved CLK_NFCON Reserved CLK_SROMC CLK_CFCON CLK_NANDXL Reserved CLK_USBHOST CLK_USBOTG Reserved CLK_HDMI CLK_TVENC Bit [31:29] Reserved Description [28] Gating all clocks for NFCON (0: mask, 1: pass) [27] Reserved [26] Gating all clocks for SROM (0: mask, 1: pass) [25] Gating all clocks for CFCON (0: mask, 1:pass) [24] Gating all clocks for One NAND-XL (0:mask, 1:pass) [23:18] Reserved [17] Gating all clocks for USB HOST (0: mask, 1: pass) [16] Gating all clocks for USB OTG (0: mask, 1: pass) [15:12] Reserved [11] Gating all clocks for HDMI link (0: mask, 1: pass) [10] Gating all clocks for TVENC (0: mask, 1: pass) CLK_MIXER CLK_VP Reserved CLK_DSIM Reserved CLK_FIMD [9] Gating all clocks for MIXER (0: mask, 1: pass) [8] Gating all clocks for VP (0: mask, 1: pass) [7:3] Reserved [2] Gating all clocks for DSIM (0: mask, 1: pass) [1] Reserved [0] Gating all clocks for FIMD (0: mask, 1: pass) Gated Clock Name ACLK_NFCON ACLK_SROMC ACLK_CFCON ACLK_NANDXL SCLK_NANDXL ACLK_USBHOST ACLK_USBOTG PCLK_HDMI SCLK_HDMI ACLK_TVENC SCLK_TVENC SCLK_DAC ACLK_MIXER SCLK_MIXER ACLK_VP PCLK_DSIM ACLK_FIMD SCLK_FIMD Initial State 0x7 1 1 1 1 1 0x3F 1 1 0xF 1 1 1 1 0x1F 1 1 1 3-41 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.4 Clock Gating Control Register (CLK_GATE_IP2, R/W, Address = 0xE010_0468) CLK_GATE_IP2 CLK_TZIC3 CLK_TZIC2 CLK_TZIC1 CLK_TZIC0 CLK_VIC3 CLK_VIC2 CLK_VIC1 CLK_VIC0 Reserved CLK_TSI CLK_HSMMC3 CLK_HSMMC2 CLK_HSMMC1 CLK_HSMMC0 Reserved CLK_SECJTAG CLK_HOSTIF CLK_MODEM CLK_CORESIGHT Bit [31] [30] [29] [28] [27] [26] [25] [24] [23:21] [20] [19] [18] [17] [16] [15:12] [11] [10] [9] [8] Description Gating all clocks for TZIC3 (0: mask, 1: pass) Gating all clocks for TZIC2 (0: mask, 1: pass) Gating all clocks for TZIC1 (0: mask, 1: pass) Gating all clocks for TZIC0 (0: mask, 1: pass) Gating all clocks for VIC3 (0: mask, 1: pass) Gating all clocks for VIC2 (0: mask, 1: pass) Gating all clocks for VIC1 (0: mask, 1: pass) Gating all clocks for VIC0 (0: mask, 1: pass) Reserved Gating all clocks for TSI (0: mask, 1: pass) Gating all clocks for HSMMC3 (0: mask, 1: pass) Gating all clocks for HSMMC2 (0: mask, 1: pass) Gating all clocks for HSMMC1 (0: mask, 1: pass) Gating all clocks for HSMMC0 (0: mask, 1: pass) Reserved Gating all clocks for SECJTAG (0: mask, 1: pass) Gating all clocks for HOST I/F (0: mask, 1: pass) Gating all clocks for MODEM I/F (0: mask, 1: pass) Gating all clocks for CORESIGHT (0: mask, 1: pass) Gated Clock Name ACLK_TZIC3 ACLK_TZIC2 ACLK_TZIC1 ACLK_TZIC0 ACLK_VIC3 ACLK_VIC2 ACLK_VIC1 ACLK_VIC0 ACLK_TSI ACLK_HSMMC3 SCLK_MMC3 ACLK_HSMMC2 SCLK_MMC2 ACLK_HSMMC1 SCLK_MMC1 ACLK_HSMMC0 SCLK_MMC0 PCLK_SECJTAG ACLK_HOSTIF ACLK_MODEM ACLK_CSSYS PCLK_CSSYS Initial State 1 1 1 1 1 1 1 1 0x7 1 1 1 1 1 0xF 1 1 1 1 3-42 S5PV210_UM 3 2BCLOCK CONTROLLER CLK_GATE_IP2 Reserved CLK_SDM CLK_SECSS Bit Description [7:2] Reserved [1] Gating all clocks for SDM (0: mask, 1: pass) [0] Gating all clocks for SECSS (0: mask, 1: pass) Gated Clock Name ACLK_SDM PCLK_SDM ACLK_SECSS Initial State 0x3F 1 1 Caution: Is should be guaranteed that S/W does not access IPs whose clock is gated. This can cause system failure. 3-43 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.5 Clock Gating Control Register (CLK_GATE_IP3, R/W, Address = 0xE010_046C) CLK_GATE_IP3 Reserved CLK_PCM2 CLK_PCM1 CLK_PCM0 CLK_SYSCON CLK_GPIO Reserved CLK_TSADC CLK_PWM CLK_WDT CLK_KEYIF CLK_UART3 CLK_UART2 CLK_UART1 CLK_UART0 CLK_SYSTIMER CLK_RTC Reserved CLK_SPI1 Bit Description [31] Reserved [30] Gating all clocks for PCM2 (0: mask, 1: pass) [29] Gating all clocks for PCM1 (0: mask, 1: pass) (DO NOT mask when I2S1 or SPDIF is used) [28] Gating all clocks for PCM0 (0: mask, 1: pass) (DO NOT mask when I2S0 or SPDIF is used) [27] Gating all clocks for SYSCON (0: mask, 1: pass) [26] Gating all clocks for GPIO (0: mask, 1: pass) [25] Reserved [24] Gating all clocks for TSADC (0: mask, 1: pass) [23] Gating all clocks for PWM (0: mask, 1: pass) [22] Gating all clocks for WDT (0: mask, 1: pass) [21] Gating all clocks for KEYIF (0: mask, 1: pass) [20] Gating all clocks for UART3 (0: mask, 1: pass) [19] Gating all clocks for UART2 (0: mask, 1: pass) [18] Gating all clocks for UART1 (0: mask, 1: pass) [17] Gating all clocks for UART0 (0: mask, 1: pass) [16] Gating all clocks for System Timer (0: mask, 1: pass) [15] Gating all clocks for RTC (0: mask, 1: pass) [14] Reserved [13] Gating all clocks for SPI1 (0: mask, 1: pass) Gated Clock Name - PCLK_PCM2 SCLK_AUDIO2 PCLK_PCM1 SCLK_AUDIO1 PCLK_PCM0 SCLK_AUDIO0 PCLK_SYSCON PCLK_GPIO PCLK_TSADC PCLK_PWM SCLK_PWM PCLK_WDT PCLK_KEYIF PCLK_UART3 SCLK_UART3 PCLK_UART2 SCLK_UART2 PCLK_UART1 SCLK_UART1 PCLK_UART0 SCLK_UART0 PCLK_ST PCLK_RTC PCLK_SPI1 SCLK_SPI1 Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3-44 S5PV210_UM 3 2BCLOCK CONTROLLER CLK_GATE_IP3 Bit Description Gated Clock Name CLK_SPI0 [12] Gating all clocks for SPI0 (0: mask, 1: pass) PCLK_SPI0 SCLK_SPI0 CLK_I2C_HDMI_PHY [11] Gating all clocks for I2C_HDMI_PHY PCLK_I2C_HDMI_PHY (0: mask, 1: pass) CLK_I2C_HDMI_DDC [10] Gating all clocks for I2C_HDMI_DDC PCLK_I2C_HDMI_DDC (0: mask, 1: pass) CLK_I2C2 [9] Gating all clocks for I2C2 (0: mask, 1: pass) PCLK_I2C2 Reserved [8] Reserved CLK_I2C0 [7] Gating all clocks for I2C0 (0: mask, 1: pass) PCLK_I2C0 CLK_I2S2 [6] Gating all clocks for I2S2 (0: mask, 1: pass) (DO NOT mask when SPDIF is used) PCLK_I2S2 SCLK_AUDIO2 CLK_I2S1 [5] Gating all clocks for I2S1 (0: mask, 1: pass) (DO NOT mask when PCM1 or SPDIF is used) PCLK_I2S1 SCLK_AUDIO1 CLK_I2S0 [4] Gating all clocks for I2S0 (0: mask, 1: pass) (DO NOT mask when PCM0 or SPDIF is used) SCLK_AUDIO0 Reserved [3:2] Reserved CLK_AC97 [1] Gating all clocks for AC97 (0: mask, 1: pass) PCLK_AC97 CLK_SPDIF [0] Gating all clocks for SPDIF (0: mask, 1: pass) PCLK_SPDIF SCLK_SPDIF SCLK_AUDIO0 SCLK_AUDIO1 SCLK_AUDIO2 Initial State 1 1 1 1 1 1 1 1 1 0x3 1 1 3-45 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.6 Clock Gating Control Register (CLK_GATE_IP4, R/W, Address = 0xE010_0470) CLK_GATE_IP4 Reserved CLK_TZPC3 CLK_TZPC2 CLK_TZPC1 CLK_TZPC0 Reserved CLK_SECKEY CLK_IEM_APC CLK_IEM_IEC Bit [31:9] [8] [7] [6] [5] [4] [3] [2] [1] Description Reserved Gating all clocks for TZPC3 (0: mask, 1: pass) Gating all clocks for TZPC2 (0: mask, 1: pass) Gating all clocks for TZPC1 (0: mask, 1: pass) Gating all clocks for TZPC0 (0: mask, 1: pass) Reserved Gating all clocks for SECKEY (0: mask, 1: pass) Gating all clocks for IEM APC (0: mask, 1: pass) Gating all clocks for IEM IEC (0: mask, 1: pass) CLK_CHIP_ID [0] Gating all clocks for CHIP ID (0: mask, 1: pass) Gated Clock Name PCLK_TZPC3 PCLK_TZPC2 PCLK_TZPC1 PCLK_TZPC0 PCLK_SECKEY PCLK_IEM_APC SCLK_PWI PCLK_IEM_IEC SCLK_PWI SCLK_HPM PCLK_CHIP_ID Initial State 0x7F_FFFF 1 1 1 1 1 1 1 1 1 3-46 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.7 Clock Gating Control Register (CLK_GATE_BLOCK, R/W, Address = 0xE010_0480) CLK_GATE_BLOCK Bit Description Reserved [31:11] Reserved CLK_INTC [10] Gating all clocks for block-INTC (VIC0,1,2, TZIC0,1,2) (0: mask, 1: pass) CLK_HSMMC [9] Gating all clocks for blockHSMMC (HSMMC0,1,2,3) (0: mask, 1: pass) CLK_DEBUG [8] Gating all clocks for block-DEBUG (MODEM I/F, HOST I/F, CSSYS, SECJTAG) (0: mask, 1: pass) CLK_SECURITY CLK_MEMORY [7] Gating all clocks for blockSECURITY (Security Subsystem) (0: mask, 1: pass) [6] Gating all clocks for blockMEMORY (OneNAND XL, CFCON, SROMC, OneNAND, EBI) (0: mask, 1: pass) CLK_USB [5] Gating all clocks for block-USB (USB OTG) (0: mask, 1: pass) Gated Clock Name ACLK_VIC0,1,2,3 ACLK_TZIC0,1,2,3 ACLK_AHB_ISFR ACLK_HSMMC0,1,2,3 ACLK_TSI ACLK_AHB_CSFR ACLK_AHB_CSYS SCLK_HSMMC0,1,2,3 ACLK_CSSYS ACLK_MODEM ACLK_HOSTIF ACLK_AHB_GSFR ACLK_AHB_GSYS PCLK_CSSYS PCLK_SECJTAG ACLK_SECSS ACLK_AHB_ESYS0,1 ACLK_AHB_ESFR ACLK_ONENANDXL ACLK_CFCON ACLK_SROMC ACLK_NFCON ACLK_AHB_SSFR ACLK_AHB_SSYS ACLK_AHB_SMEM SCLK_NANDXL SCLK_ONENAND SCLK_EBI ACLK_USBOTG ACLK_USBHOST ACLK_AHB_USFR ACLK_AHB_USYS Initial State 0x1F_FFFF 1 1 1 1 1 1 3-47 S5PV210_UM 3 2BCLOCK CONTROLLER CLK_GATE_BLOCK Bit Description CLK_TV [4] Gating all clocks for block-TV (VP, MIXER, TVENC) (0: mask, 1: pass) CLK_LCD [3] Gating all clocks for block-LCD (FIMD, G2D) (0: mask, 1: pass) Gated Clock Name ACLK_VP ACLK_MIXER ACLK_TVENC ACLK_AHB_TSFR ACLK_AXI_TSYS PCLK_HDMI PCLK_AXI_TSYS SCLK_MIXER SCLK_TVENC SCLK_DAC SCLK_PIXEL ACLK_FIMD ACLK_AHB_LSFR ACLK_AXI_LSYS PCLK_DSIM PCLK_AXI_LSYS SCLK_FIMD SCLK_FIMC_LCLK1 ACLK_G2D SCLK_G2D Initial State 1 1 1 SCLK_FIMC_LCLK will be automatically turned OFF when any of block clock CLK_LCD and CLK_IMG is turned OFF. 3-48 S5PV210_UM 3 2BCLOCK CONTROLLER CLK_GATE_BLOCK Bit Description CLK_IMG [2] Gating all clocks for block-IMG (FIMC0,1,2, JPEG, ROTATOR) (0: mask, 1: pass) CLK_MFC CLK_G3D [1] Gating all clocks for block-MFC (MFC) (0: mask, 1: pass) [0] Gating all clocks for block-G3D (G3D) (0: mask, 1: pass) Gated Clock Name ACLK_FIMC0,1,2 ACLK_JPEG ACLK_ROTATOR ACLK_AHB_XSFR ACLK_AXI_XSYS PCLK_CSIS PCLK_AXI_XSYS SCLK_CAM0,1 SCLK_CSIS SCLK_FIMC_LCLK PCLK_MFC SCLK_MFC ACLK_G3D SCLK_G3D Initial State 1 1 1 3-49 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.8 Clock Gating Control Register (CLK_GATE_IP5, R/W, Address = 0xE010_0484) CLK_GATE_IP5 Reserved CLK_JPEG Reserved Bit Description [31:30] Should be one for all bit [29] Gating all clocks for JPEG (0: mask, 1: pass) [28:0] Should be one for all bit Gated Clock Name ACLK_JPEG Initial State 0x3 1 0x1FFFFFFF 3-50 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.5.9 Clock Gating Exceptions Some clock gating cells have exceptional conditions for gating clocks. This section summarizes this. SCLK_AUDIO0 is gated when all of the following register fields are cleared to LOW. This guarantees SCLK_AUDIO0 is running when any of the load is running. • CLK_GATE_IP3[0] for SPDIF • CLK_GATE_IP3[4] for I2S0 • CLK_GATE_IP3[28] for PCM0 SCLK_AUDIO1 is gated when all of the following register fields are cleared to LOW. This guarantees SCLK_AUDIO1 is running when any of the load is running. • CLK_GATE_IP3[0] for SPDIF • CLK_GATE_IP3[5] for I2S1 • CLK_GATE_IP3[29] for PCM1 SCLK_AUDIO2 is gated when all of the following register fields are cleared to LOW. This guarantees SCLK_AUDIO2 is running when any of the load is running. • CLK_GATE_IP3[0] for SPDIF • CLK_GATE_IP3[6] for I2S2 • CLK_GATE_IP3[30] for PCM2 3-51 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.6 CLOCK OUTPUT CONFIGURATION REGISTER Internal clocks can be monitored through XCLKOUT PAD. CLK_OUT register selects an internal clock among PLL outputs, USBPHY output, HDMIPHY output, RTC, TICK, system bus clocks, ARMCLK, HPM clock and external OSCs. It also divides the selected clock. This is just for debugging. Do not supply this to other components as clock. 3.7.6.1 Clock Output Configuration Register (CLK_OUT, R/W, Address = 0xE010_0500) CLK_OUT Reserved DIVVAL Reserved CLKSEL DCLKCMP DCLKDIV Bit Description [31:24] Reserved [23:20] Divide ratio (Divide ratio = DIVVAL + 1) [19:17] Reserved [16:12] 00000 = FOUTAPLL/4 00001 = FOUTMPLL/2 00010 = FOUTEPLL 00011 = FOUTVPLL 00100 = SCLK_USBPHY0 00101 = SCLK_USBPHY1 00110 = SCLK_HDMIPHY 00111 = RTC 01000 = RTC_TICK_SRC 01001 = HCLK_MSYS 01010 = PCLK_MSYS 01011 = HCLK_DSYS 01100 = PCLK_DSYS 01101 = HCLK_PSYS 01110 = PCLK_PSYS 01111 = ARMCLK/4 10000 = SCLK_HPM 10001 = XXTI 10010 = XUSBXTI 10011 = DCLK DCLKCMP, DCLKDIV, DCLKSEL, and DCLKEN fields define DCLK. [11:8] This field changes the clock duty of DCLK. Thus, it must be smaller than DCLKDIV. It is valid only when CLKSEL is DOUT. If the DCLKDIV is n, low level duration is (n+1). High level duration is ((DCLKDIV + 1) - (n+1)) [7:4] DCLK divide value DCLK frequency = source clock / (DCLKDIV + 1) Initial State 0x000 0x0 0x000 0x0 0x0 0x0 3-52 S5PV210_UM 3 2BCLOCK CONTROLLER CLK_OUT DCLKSEL DCLKEN Bit Description [3:1] Select DCLK source clock (000: XXTI, 001: XUSBXTI, 010: SCLK_HDMI27M, 011: SCLK_USBPHY0, 100: SCLK_USBPH1, 101: SCLK_HDMIPHY, 110: FOUTMPLL/2, 111: SCLKEPLL) [0] Enable DCLK (0:disable, 1:enable) Initial State 0 0 CLKOUT frequency = CLKIN (selected by CLKSEL) frequency / (DIVVAL+1) Figure 3-4 CLKOUT Waveform with DCLK Divider 3-53 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.7 CLOCK DIVIDER STATUS SFRS 3.7.7.1 Clock Divider Status SFRs (CLK_DIV_STAT0, R, Address = 0xE010_1000) CLK_DIV_STAT0 DIV_UART3 DIV_UART2 DIV_UART1 DIV_UART0 DIV_MMC3 DIV_MMC2 DIV_MMC1 DIV_MMC0 Reserved DIV_FIMC_LCLK Reserved DIV_MFC DIV_G3D DIV_CSIS Reserved DIV_FIMD DIV_CAM1 DIV_CAM0 DIV_FIMC Reserved DIV_TBLK DIV_PCLK_PSYS DIV_HCLK_PSYS DIV_PCLK_DSYS DIV_HCLK_DSYS DIV_PCLK_MSYS DIV_HCLK_MSYS DIV_A2M DIV_APLL Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21:18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description DIVUART3 status (0: stable, 1: divider is changing) DIVUART2 status (0: stable, 1: divider is changing) DIVUART1 status (0: stable, 1: divider is changing) DIVUART0 status (0: stable, 1: divider is changing) DIVMMC3 status (0: stable, 1: divider is changing) DIVMMC2 status (0: stable, 1: divider is changing) DIVMMC1 status (0: stable, 1: divider is changing) DIVMMC0 status (0: stable, 1: divider is changing) Reserved DIVFIMC_LCLK status (0: stable, 1: divider is changing) Reserved DIVMFC status (0: stable, 1: divider is changing) DIVG3D status (0: stable, 1: divider is changing) DIVCSIS status (0: stable, 1: divider is changing) Reserved DIVFIMD status (0: stable, 1: divider is changing) DIVCAM1 status (0: stable, 1: divider is changing) DIVCAM0 status (0: stable, 1: divider is changing) DIVFIMC status (0: stable, 1: divider is changing) Reserved DIVTBLK status (0: stable, 1: divider is changing) DIVPCLKP status (0: stable, 1: divider is changing) DIVHCLKP status (0: stable, 1: divider is changing) DIVPCLKD status (0: stable, 1: divider is changing) DIVHCLKD status (0: stable, 1: divider is changing) DIVPCLKM status (0: stable, 1: divider is changing) DIVHCLKM status (0: stable, 1: divider is changing) DIVA2M status (0: stable, 1: divider is changing) DIVAPLL status (0: stable, 1: divider is changing) Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3-54 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.7.2 Clock Divider Status SFRs (CLK_DIV_STAT1, R, Address = 0xE010_1004) CLK_DIV_STAT1 Reserved DIV_G2D Reserved DIV_DPM DIV_DVSEM DIV_DMC0 DIV_PWI DIV_HPM DIV_COPY DIV_ONENAND DIV_AUDIO2 DIV_AUDIO1 DIV_AUDIO0 Reserved DIV_PWM Reserved DIV_SPI1 DIV_SPI0 Bit [31:21] [20] [19:18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Description Reserved DIVG2D status (0: stable, 1: divider is changing) Reserved DIVDPM status (0: stable, 1: divider is changing) DIVDVSEM status (0: stable, 1: divider is changing) DIVDMC0 status (0: stable, 1: divider is changing) DIVPWI status (0: stable, 1: divider is changing) DIVHPM status (0: stable, 1: divider is changing) DIVCOPY status (0: stable, 1: divider is changing) DIVFLASH status (0: stable, 1: divider is changing) DIVAUDIO2 status (0: stable, 1: divider is changing) DIVAUDIO1 status (0: stable, 1: divider is changing) DIVAUDIO0 status (0: stable, 1: divider is changing) Reserved DIVPWM status (0: stable, 1: divider is changing) Reserved DIVSPI1 status (0: stable, 1: divider is changing) DIVSPI0 status (0: stable, 1: divider is changing) Initial State 0x0 0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3-55 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.8 CLOCK MUX STATUS SFRS 3.7.8.1 Clock MUX Status SFRs (CLK_MUX_STAT0, R, Address = 0xE010_1100) Clock MUX status registers show the status of glitch-free MUX logic. When CLK_SRCx SFR has been changed, it takes several clock cycles. Therefore, S/W should check the status of glitch-free MUX if the SFR values are applied. CLK_MUX_STAT0 Reserved ONENAND_SEL Reserved MUX_PSYS_SEL Reserved MUX_DSYS_SEL Reserved MUX_MSYS_SEL Reserved VPLL_SEL Reserved EPLL_SEL Reserved MPLL_SEL Reserved APLL_SEL Bit [31] [30:28] [27] [26:24] [23] [22:20] [19] [18:16] [15] [14:12] [11] [10:8] [7] [6:4] [3] [2:0] Description Reserved Selection signal status of MUXFLASH (001:HCLK_PSYS, 010:HCLK_DSYS, 1xx: On changing) Reserved Selection signal status of MUX_PSYS (001:SCLKMPLL, 010:SCLKA2M, 1xx: On changing) Reserved Selection signal status of MUX_DSYS (001:SCLKMPLL, 010:SCLKA2M, 1xx: On changing) Reserved Selection signal status of MUX_MSYS (001:SCLKAPLL, 010:SCLKMPLL, 1xx: On changing) Reserved Selection signal status of MUXVPLL (001: FINVPLL, 010: FOUTVPLL, 1xx: On changing) Reserved Selection signal status of MUXEPLL (001:FINPLL, 010:FOUTEPLL, 1xx: On changing) Reserved Selection signal status of MUXMPLL (001:FINPLL, 010:FOUTMPLL, 1xx: On changing) Reserved Selection signal status of MUXAPLL (001:FINPLL, 010:FOUTAPLL, 1xx: On changing) Initial State 0 0x1 0 0x1 0 0x1 0 0x1 0 0x1 0 0x1 0 0x1 0 0x1 3-56 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.8.2 Clock MUX Status SFRs (CLK_MUX_STAT1, R, Address = 0xE010_1104) CLK_MUX_STAT1 DMC0_SEL G2D_SEL Reserved HPM_SEL Reserved MFC_SEL G3D_SEL Bit [31:28] [27:24] [23:19] [18:16] [15:8] [7:4] [3:0] Description Selection signal status of MUXDMC0 (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) Selection signal status of MUXG2D (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) Reserved Selection signal status of MUXHPM (001: SCLKAPLL, 010: SCLKMPLL, 1xx: On changing) Reserved Selection signal status of MUXMFC (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) Selection signal status of MUXG3D (00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL, 011x:SCLKVPLL, 1xxx: On changing) Initial State 0x0 0x0 0x0 0x1 0x0 0x0 0x0 3-57 S5PV210_UM 3.7.9 OTHER SFRS 3.7.9.1 Other SFRs (SWRESET, R/W, Address = 0xE010_2000) SWRESET Reserved SWRESET Bit [31:1] [0] Description Reserved Software reset (0: no effect, 1: reset) 3 2BCLOCK CONTROLLER Initial State 0x0 0 3.7.10 IEM CONTROL SFRS 3.7.10.1 IEM Control SFRs (DCGIDX_MAP0, R/W, Address = 0xE010_3000) DCGIDX_MAP0 DCGIDX_MAP0 Bit Description [31:0] IEC configuration for DCG index map[31:0] Initial State 0xFFFF_FFFF 3.7.10.2 IEM Control SFRs (DCGIDX_MAP1, R/W, Address = 0xE010_3004) DCGIDX_MAP1 DCGIDX_MAP1 Bit Description [31:0] IEC configuration for DCG index map[63:32] Initial State 0xFFFF_FFFF 3.7.10.3 IEM Control SFRs (DCGIDX_MAP2, R/W, Address = 0xE010_3008) DCGIDX_MAP2 DCGIDX_MAP2 Bit Description [31:0] IEC configuration for DCG index map[95:64] DCGIDX_MAP0~3 are mapped to IECCFGDCGIDXMAP[95:0] of IEM_IEC input port. Initial State 0xFFFF_FFFF 3-58 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.10.4 IEM Control SFRs (DCGPERF_MAP0, R/W, Address = 0xE010_3020) DCGPERF_MAP0 DCGPERF_MAP0 Bit Description [31:0] DCG performance map[31:0] Initial State 0xFFFF_FFFF 3.7.10.5 IEM Control SFRs (DCGPERF_MAP1, R/W, Address = 0xE010_3024) DCGPERF_MAP1 DCGPERF_MAP1 Bit Description [31:0] DCG performance map[63:32] DCGPERF_MAP0~1 are mapped to IECCFGDCGPERFMAP[63:0] of IEM_IEC input port. Initial State 0xFFFF_FFFF 3.7.10.6 IEM Control SFRs (DVCIDX_MAP_MAP0, R/W, Address = 0xE010_3040) DVCIDX_MAP Reserved DCGPERF_MAP0 Bit [31:24] [23:0] Description Reserved IEC configuration for DVC index map[23:0] DVCIDX_MAP is mapped to IECCFGDVCIDXMAP[23:0] of IEM_IEC input port. Initial State 0x00 0xFF_FFFF 3-59 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.10.7 IEM Control SFRs (FREQ_CPU, R/W, Address = 0xE010_3060) FREQ_CPU Reserved FREQ_CPU Bit Description [31:24] Reserved [23:0] Maximum frequency of CPU in kHz Initial State 0x00 0x00_0000 The register is related to IECCFGFREQCPU[23:0] of IEM_IEC input port. FREQ_CPU[23:0] is the maximum processor of frequency in KHz, and gives the clock frequency of the processor in KHz. Examples values are shown in the following table. FREQ_CPU[23:0] 0x00_4E20 0x03_A980 0x00_03E8 Verilog Expression 24’MSYS20_000 24’PSYS40_000 24’MSYS01_000 Processor Frequency 200,000KHz = 20MHz 240,000KHz = 240MHz 1,000KHz = 1MHz 3.7.10.8 IEM Control SFRs (FREQ_DPM, R/W, Address = 0xE010_3064) FREQ_DPM Reserved FREQ_DPM Bit [31:24] [23:0] Description Reserved Maximum frequency of DPM accumulators Initial State 0x00 0x00_0000 The register is related to IECCFGFREQDPM[23:0] of IEM_IEC input port. FREQ_DPM[23:0] is the DPM frequency in KHz, and gives the rate that the DPM is accumulating in KHz. Examples values are shown in the following table. FREQ_DPM[23:0] 0x00_4E20 0x00_2710 0x00_03E8 Verilog Expression 24’MSYS20_000 24’MSYS10_000 24’MSYS01_000 Processor Frequency 200,000KHz = 20MHz 100,000KHz = 10MHz 1,000KHz = 1MHz 3-60 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.10.9 IEM Control SFRs (DVSEMCLK_EN, R/W, Address = 0xE010_3080) DVSEMCLK_EN Reserved DVSEMCLK_EN Bit [31:1] [0] Description Reserved DVS emulation clock enable Initial State 0x0000_0000 0 The register is related to IECDVSEMCLKEN of IEM_IEC input port. DVSEMCLK_EN means the enable for advancing the PWM frame time slots when in DVS emulation mode. The signal must be pulsed at a frequency of 1 MHz. 3.7.10.10 IEM Control SFRs (MAXPERF, R/W, Address = 0xE010_3084) MAXPERF Reserved MAXPERF_EN Bit [31:1] [0] Description Reserved MAX performance enable (0: disable, 1: enable) Initial State 0x0000_0000 0 3-61 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.10.11 IEM Control SFRs • APLL_CON0_L8, R/W, Address = 0xE010_3100 • APLL_CON0_L7, R/W, Address = 0xE010_3104 • APLL_CON0_L6, R/W, Address = 0xE010_3108 • APLL_CON0_L5, R/W, Address = 0xE010_310C • APLL_CON0_L4, R/W, Address = 0xE010_3110 • APLL_CON0_L3, R/W, Address = 0xE010_3114 • APLL_CON0_L2, R/W, Address = 0xE010_3118 • APLL_CON0_L1, R/W, Address = 0xE010_311C • APLL_CON1_L8, R/W, Address = 0xE010_3300 • APLL_CON1_L7, R/W, Address = 0xE010_3304 • APLL_CON1_L6, R/W, Address = 0xE010_3308 • APLL_CON1_L5, R/W, Address = 0xE010_330C • APLL_CON1_L4, R/W, Address = 0xE010_3310 • APLL_CON1_L3, R/W, Address = 0xE010_3314 • APLL_CON1_L2, R/W, Address = 0xE010_3318 • APLL_CON1_L1, R/W, Address = 0xE010_331C APLL_CON0_L1 ~ 8 Reserved MDIV Reserved PDIV Reserved SDIV Bit [31:26] [25:16] [15:14] [13:8] [7:3] [2:0] Reserved APLL M divide value Reserved APLL P divide value Reserved APLL S divide value Description Initial State 0x00 0x0C8 0 0x3 0 0x1 Each register of APLL_CON0_L1 ~ 7 configures P/M/S/VCO_FREQ values for ARM PLL at IEM performance level-1 to 8. APLL_CON1_L1 ~ 8 AFC_ENB Reserved AFC Bit [31] [30:5] [4:0] Description Decides whether AFC is enabled or not. Active low. AFC selects adaptive frequency curve of VCO for wide range, high phase noise (or jitter) and fast lock time. (LOW: AFC is enabled, HIGH: AFC is disabled) Reserved AFC value Initial State 0x0 0x0 0x0 3-62 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.10.12 IEM Control SFRs • CLKDIV_IEM_L8, R/W, 0xE010_3200 • CLKDIV_IEM_L7, R/W, 0xE010_3204 • CLKDIV_IEM_L6, R/W, 0xE010_3208 • CLKDIV_IEM_L5, R/W, 0xE010_320C • CLKDIV_IEM_L4, R/W, 0xE010_3210 • CLKDIV_IEM_L3, R/W, 0xE010_3214 • CLKDIV_IEM_L2, R/W, 0xE010_3218 • CLKDIV_IEM_L1, R/W, 0xE010_321C CLKDIV_IEM_L1 ~ 8 Reserved HPM_RATIO Reserved COPY_RATIO Reserved HCLK_MSYS_RATIO Reserved APLL_RATIO Bit [31:23] [22:20] [19] [18:16] [15:11] [10:8] [7:3] [2:0] Description Reserved DIVIEM clock divider ratio, DIVIEM = DIVCOPY / RATIO (RATIO = IEM_RATIO + 1) Reserved DIVCOPY clock divider ratio, DIVCOPY = MUXIEM / RATIO (RATIO = COPY_RATIO + 1) Reserved DIVHCLKM clock divider ratio, HCLK_MSYS = ARMCLK / RATIO (RATIO = HCLK_MSYS_RATIO + 1) Reserved DIVAPLL clock divider ratio, ARMCLK = MUX_MSYS / RATIO (RATIO = APLL_RATIO + 1) Initial State 0x000 0x0 0 0x0 0x00 0x0 0x0 0x0 Each register of CLKDIV_IEM_L1~8 configures clock divider values for ARM and HPM clocks at IEM performance level-1 to 8. 3-63 S5PV210_UM 3 2BCLOCK CONTROLLER 3.7.11 MISCELLANEOUS SFRS 3.7.11.1 Miscellaneous SFRs (DISPLAY_CONTROL, R/W, Address = 0xE010_7008) DISPLAY_CONTROL Reserved DISPLAY_PATH_SEL Bit [31:2] [1:0] Description Reserved Display path selection 00: RGB=--- I80=FIMD ITU=FIMD 01: RGB=--- I80=--- ITU=FIMD 10: RGB=FIMD I80=FIMD ITU=FIMD 11: RGB=FIMD I80=FIMD ITU=FIMD 3.7.11.2 Miscellaneous SFRs (AUDIO_ENDIAN, R/W, Address = 0xE010_700C) AUDIO_ENDIAN Reserved RP_R_ENDIAN RP_W_ENDIAN ARM_R_ENDIAN ARM_W_ENDIAN Bit [31:4] [3] [2] [1] [0] Description Reserved Endian selection for RP read channel (0: little endian, 1: big endian) Endian selection for RP write channel channel (0: little endian, 1: big endian) Endian selection for ARM read channel channel (0: little endian, 1: big endian) Endian selection for ARM write channel channel (0: little endian, 1: big endian) Initial State 0x0000_0000 0 Initial State 0x0000_0000 0 0 0 0 3-64 S5PV210_UM 4 3BPOWER MANAGEMENT 4 POWER MANAGEMENT This chapter describes the Power Management Unit (PMU) in S5PV210. SYSCON manages clock management unit (CMU) and PMU in S5PV210. 4.1 OVERVIEW OF PMU Mobile application processors such as the S5PV210 should consume less power, since mobile products have a small battery with limited power capacity. The purpose of PMU is to provide various methods in S5PV210 to consume less power under specific application scenarios. The power management scheme in S5PV210 provides six system power modes, namely, Normal, Idle, Deep-idle, Stop, Deep-stop, and Sleep modes. The description of each power mode is given as follows: • Normal: In this mode, the CPU core is running, that is, the software is running. • Idle: In this mode, the CPU core is idle, that is, the CPU core clock is disabled but the remaining parts of the S5PV210 are running. • Deep-idle: In this mode, the CPU core is power-gated, that is, the CPU core power is supplied, but is powered off by the internal power switch. The remaining parts of the chip remain the same as those in the Normal mode, or become power-gated (except Audio power domain for application of low power MP3 playback). • Stop: In this mode, the S5PV210 is clock-gated (except RTC module). Therefore, application programming stops and waits for wakeup event to resume its operation. Also, the CPU core clock is disabled. (Note: The power-gated block in Normal mode is still power-gated in Stop mode.) • Deep-stop: In this mode, the CPU core and remaining parts of the chip are power-gated (except TOP, RTC, and ALIVE modules). The TOP module can be power-gated or powered-on. • Sleep: In this mode, the internal power (1.1V) of the S5PV210 is externally turned off using regulator or power management IC (PMIC). Therefore, the internal power to S5PV210 is powered “off” except ALIVE block. (Note: RTC power to RTC and external power to I/O pad is still "on". If wakeup event occurs, S5PV210 is initialized by wakeup reset, as though power-on reset was asserted.) ‘Deep’ means CPU core is power-gated. Therefore, leakage power of CPU core is minimized in Deep-idle and Deep-stop power modes. The above description about power mode is given in view of internal digital logic. For more information on nondigital logic, refer to 4.5 "Cortex-A8 Power Mode", 4.7 "External Power Control", and 4.8 "Internal memory control". PMU controls the power mode of SRAM and PLL. However, the power mode of analog IP (except SRAM and PLL) should be controlled by its corresponding control module. In addition to the PMU, clock controller (CLKCON) also controls the PLL. 4-1 S5PV210_UM 4 3BPOWER MANAGEMENT 4.2 FUNCTIONAL DESCRIPTION OF PMU The total power consumption consists of static and dynamic power consumptions. Static power is consumed when power to a circuit is supplied and there is no active operation in the circuit. On the other hand, dynamic power is consumed when the signal to a circuit is changing and there are some active operations in the circuit. The static power consumption is due to leakage current in the process, while dynamic power consumption is due to the transition of gate state. The dynamic power consumption depends on the operating voltage, operating frequency, and toggling ratios of the logic gate. Various power-saving techniques have been developed, and some of them are shown and compared in Table 4-1. Power saving techniques Frequency scaling Clock gating Power gating Power off Table 4-1 Comparison of Power Saving Techniques Result Clock Reduce dynamic power Minimize dynamic power Minimize leakage power Enable Disable Disable Nearly zero power Disable Power Supplied Supplied External power supplied, while internally gated Externally off State Retention Normal F/F Retention F/F Keep state Keep state Lose state Keep state Lose state Frequency scaling means that the frequency of clock to a specific module is lowered when the module is not required to run fast. Dynamic power can be reduced by frequency scaling. Clock gating means that the clock to a specific Intellectual Property (IP) module is disabled using clock gating cells in SYSCON. To control these clock gating cells, set registers CLK_GATE_IP0-4 and CLK_GATE_BLOCK in SYSCON. Clock gating technique is also applied in synthesis phase of chip development flow, where gate-level netlist is generated from RTL code by synthesis tool. The clock gating cells inserted by synthesis tool are controlled not by software, but by hardware automatically. When clock gating is applied, power to logic gate is still supplied. Therefore, the states of Normal Flip-Flop (F/F) and Retention F/F are kept. Retention F/F is developed to keep its state, even though power is not supplied due to power gating. Power gating means that a current path to a specific power domain (a group of IP modules) is internally disconnected using switch cells in that power domain. Therefore, power to that domain is not supplied. The switch cell can be located between real power and virtual power (HEADER), or between real ground and virtual ground (FOOTER). To control the switch cells, set registers NORMAL_CFG, IDLE_CFG, and STOP_CFG in SYSCON. Note that external power to S5PV210 is not "OFF". When power gating is applied, the states of normal F/Fs are lost, but the states of retention F/Fs are kept. Therefore, there can be two power-gating techniques, as listed below: • Power gating without state retention − Normal F/F is used. • Wakeup reset is required. Power gating with state retention − Retention F/F is used. 4-2 S5PV210_UM 4 3BPOWER MANAGEMENT Power “OFF” means that the power to S5PV210 is externally “OFF” using regulator or Power Management IC (PMIC). In S5PV210, SYSCON generates power control signal to regulator or PMIC. When power “OFF” is applied, the states of normal F/Fs and retention F/Fs are lost. Therefore, if you want to save some important data, you should move the data to external memory and restore it when wakeup event occurs. To reduce the dynamic power consumption, S5PV210 uses clock gating and frequency scaling. Clocks in S5PV210 can be disabled in module-by-module basis. Clock frequency can be lowered when the system is not required to operate at the maximum frequency. To reduce power consumption further in the system level, S5PV210 makes the DRAM enter into self-refresh mode and deep power-down mode (refer to Chapter 5.1, "DRAM Controller"). To reduce the static current, S5PV210 supports block-based power gating. In specific applications, a certain group of modules are not required to run, and therefore do not need to be powered "ON". For example, MP3 playback, Multi-Format Codec (MFC), Video modules (Camera interface, JPEG, Video processor, Mixer, and so on), and 3D graphics core, do not need to operate and can be power-gated for minimum static power consumption. S5PV210 internal modules are grouped into 11 power domains based on their functions, as shown in Table 4-2 S5PV210 Power Domains of Internal Logic and eight power domains except System Timer, ALIVE and RTC can be powergated by turning “OFF” the Current Cut-off Switch (CCS), which connects the current path between real VDD and virtual VDD. Table 4-2 S5PV210 Power Domains of Internal Logic Power Domain Included Modules Power Gating Methods 1 CPU Cortex-A8, L1/L2 Cache, ETM, NEON PMOS (inside CPU) 2 MFC MFC PMOS (header) 3 G3D G3D PMOS (header) 4 Audio Sub-system Audio related modules: I2S channel 0 only, Audio buffer RAM PMOS (header) 5 LCD LCD controller, DSIM, G2D PMOS (header) 6 TV VP, MIXER, TV Encoder, HDMI PMOS (header) 7 CAM Camera, CSIS, JPEG, Rotator PMOS (header) 8 System Timer System Timer PMOS but, switch is not off (always on) Clock Management Unit, GPIO (OFF), Bus components, VIC, TZIC, Internal memory (IROM and IRAM), NAND controller, OneNAND controller, CF controller, SRAM controller, Peripheral DMA, Memory DMA, CoreSight, 9 TOP Secure JTAG, Modem interface, Security sub-system, PMOS (header) TSI, HSMMC, USB HOST, USB OTG, DRAM controller, CHIPID, IEM_IEC, Security key, SPDIF, PCM, SPI, KEYIF, TSADC, I2C, I2S channel 1 and 2, AC97, PCM, System timer, Watchdog timer, UART 10 ALIVE Power Management Unit, GPIO (ALIVE), Wakeup logic NO 11 RTC RTC NO 4-3 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3 SYSTEM POWER MODE 4.3.1 OVERVIEW According to the power saving schemes and features explained in Section 4.3 , S5PV210 provides six power modes, namely, NORMAL, IDLE, DEEP-IDLE, STOP, DEEP-STOP, and SLEEP. Power modes are summarized in Table 4-3. In NORMAL mode, use module-based clock gating, block-based power gating, and frequency scaling to reduce power consumption. To reduce dynamic power consumption, clock gating disables clock input to specific module according to the operating scenario. Clock gating can be done in module-by-module basis. To reduce static power consumption of a block or power domain (a group of modules), power gating disconnects a leakage current path. Power gating can be done in block-by-block basis. Frequency scaling lowers the operating frequency to reduce dynamic power consumption. In IDLE mode, the CPU clock is disabled internally by entering Standby mode of Cortex-A8. CPU performs WFI instruction to enter Standby mode. In this mode, Cortex-A8 core is not running, therefore dynamic power of CPU is reduced. The remaining parts of the chip keep their states in NORMAL mode, that is, clock-gated modules are still clock-gated and power-gated blocks are still power-gated. In DEEP-IDLE mode, Cortex-A8 core is power-gated rather than clock-gated. In DEEP-IDLE mode, the leakage power of CPU core is minimized. There are three options in DEEP-IDLE mode. The first option is that the remaining parts of the chip keep their operations in NORMAL mode. The second option is that the remaining parts of the chip keep their states in NORMAL mode. The third option is that for low-power MP3 playback, that is, TOP and SUB blocks are also power-gated, but only Audio block is still power on. These three options can be selected by setting TOP_LOGIC field of IDLE_CFG register in SYSCON, that is, TOP domain can either be power-on or power-gated by setting TOP_LOGIC field of IDLE_CFG register before entry into IDLE mode. • TOP_LOGIC = 2’b01: TOP block and sub-blocks keep their states in NORMAL mode. Audio block is running the operation. • TOP_LOGIC = 2’b10: TOP block, sub-blocks, and Audio block is running the operation. ‘DEEP’ means that Cortex-A8 Core is power-gated. In STOP mode, the clock to modules (except RTC module), PLLs, and unnecessary oscillators are selectively disabled in order to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into Standby mode. In DEEP-STOP mode, Cortex-A8 Core is power-gated rather than clock-gated as in STOP mode, and the remaining parts of the chip are power-gated (except TOP, RTC, and ALIVE modules). However, TOP domain can either be power-on or power-gated. To do so, set TOP_LOGIC field of STOP_CFG register before entry into DEEP-STOP mode. Cortex-A8 L2 cache can be powered “ON” for memory retention or power-gated to save power. • TOP_LOGIC = 2’b01, TOP block is power-gated. • TOP_LOGIC = 2’b10, TOP block is power “ON”. 4-4 S5PV210_UM 4 3BPOWER MANAGEMENT Table 4-3 Power Mode Summary Power Mode NORMAL IDLE DEEP-IDLE STOP DEEP-STOP SLEEP CortexA8 Core L2 Cache Run with IEM1) Run with IEM Standby Power on Power gating Retention/ Power gating Standby Power on Power gating Retention/ Power gating Power off Power off SUB2) Power on/ Clock gating/ Power gating KEEP power state in NORMAL mode KEEP power state in NORMAL mode/ Power gating5) Clock gating/ Power gating Power gating Power off Logic Audio block3) Power on/ Clock gating KEEP power state in NORMAL mode KEEP power state in NORMAL mode Clock gating Power gating Power off TOP4) Power on/ Clock gating KEEP power state in NORMAL mode KEEP power state in NORMAL mode/ Power gating5) Clock gating Power on/ Power gating Power off ALIVE Power on PLL Selectively Disabled Selectively Disabled Disabled Power off OSC Selectively Disabled Selectively Disabled Selectively Disabled Selectively Disabled I/O Power on Power on Power on internal power16) off/ alive power17) on Typical Wakeup time6) OSC enabled OSC disabled < 1us7) N.A < 1us N.A < 1us8) or < 400us9) N.A < 350us10) < 1.35 ms13) < 350us10) or 400us11) < 1.35ms13) or 1.4ms14) < 6.1ms12) < 7.4 ms15) IEM refers to Intelligent Energy Management introduced by ARM. IEM is explained in detail separately in IEM related TRM. SUB refers to power domain of Row 2, 3, 5, 6, 7, and 8 in Table 4-2. Audio block refers to power domain of Row 4 in Table 4-2. TOP refers to power domain of Row 10 in Table 4-2. 4-5 S5PV210_UM 4 3BPOWER MANAGEMENT There is second option in DEEP-IDLE mode for low-power MP3 playback, i.e., TOP block and SUB block is power-gated, but Audio block is still power ”ON”. This time is measured from wakeup event assertion to ARM reset de-assertion or ARM clock supply. That is, ARM runs the next instruction this time after wakeup event is asserted. Restored time is not included. Those saved data in external memory should be restored after this time. All values are measured assuming 12 MHz clock as main OSC. Wake-up time in this case refers to time to power-up a power domain. For TOP block ”ON”, 1us for ARM clock supply For TOP block ”OFF”, max 300us for PLL+ 100us for ARM reset de-assertion Maximum 300us for PLL + 50 us for ARM clock supply For TOP block ”OFF”, maximum 300us for PLL + 100 us for ARM reset de-assertion 6ms for regulator ”ON” + 100us for ARM reset de-assertion 1ms for OSC+ max 300us for PLL + 50 us for ARM clock supply For TOP block ”OFF”, 1ms for OSC + max 300us for PLL + 100 us for ARM reset de-assertion 6ms for regulator ”ON” + 1ms for OSC + 100us for ARM reset de-assertion Internal power is connected to all internal logic except CPU, ALIVE, and RTC module, as shown in Table 4-2. Alive power is connected to ALIVE module in Table 4-2. In SLEEP mode, power for all blocks except ALIVE block is not supplied since regulator or PMIC turn “OFF” the external power source, and all PLLs and unnecessary oscillators are disabled. Static power consumption is very small in SLEEP mode. The only leakage power source is due to power supplied to ALIVE block. Hardware disables the PLL in STOP and SLEEP mode, and OSCs are selectively disabled by setting OSC_EN field of STOP_CFG and SLEEP_CFG register in SYSCON. 4-6 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3.2 NORMAL MODE In NORMAL mode, clock gating, power gating, and frequency scaling can be used for power saving. Clock gating can be done on the basis of module-by-module. In other words, you can decide which modules to turn on or off. To disable the clock of one or more modules, set the corresponding bits in clock gating control registers CLK_GATE_IP0-4 and CLK_GATE_BLOCK in SYSCON module. Changing these bits (except some bits related AXI modules) will enable/ disable the clock to corresponding modules immediately. Some bits related to AXI modules will disable the clock input after some time, but will enable the clock input almost immediately. The delay to disable the clock input is due to handshaking procedure of Low power interface. If you want to disable the AXI module, set the bit related to that module to 1’b0, then SYSCON asserts CSYSREQ to 1’b0 to request the AXI module to enter the low power state. If the module asserts CSYSACK to 1’b0, then SYSCON will disable the clock to that module. NOTE: Use Standby mode to disable CPU clock internally. The Standby mode is one of the power modes of ARM Cortex-A8. The clock to CPU is disabled to reduce switching current in ARM Cortex-A8. When S5PV210 enters IDLE mode, CPU clock is disabled using Standby mode, where application program is not running until wakeup event occurs. Frequency scaling is done in PLL-by-PLL basis. Change the PLL P/M/S values to lower the operating frequency of the modules. Changing a P/M/S value results in PLL lock operation, which takes maximum 100us time. S5PV210 stops its operation during the PLL lock period, since the PLL output clock is masked. For more information on how to change P/M/S value and related clock divider value, refer to Chapter 2.10, "Clock Strategy". Power gating is done on the basis of block-by-block. Set the corresponding bits in NORMAL_CFG register to perform power gating in one or more blocks. The IP blocks that can be power-gated in NORMAL mode are MFC, G3D, IMG sub-system, LCD sub-system, and TV sub-system (Refer to Table 4-2). Power gating of a block will disconnect the current path to the logic gates. The power domain can also be powered “ON” by setting the corresponding bit in NORMAL_CFG register. Change the multiple bits in the NORMAL_CFG registers to power “ON” or power-gate multiple power domains at the same time. However, you should not initiate power “ON” (or power-gate) before power gating (or power on) is complete. Power gating status of each power domain is found in the BLK_PWR_STAT register. BLK_PWR_STAT is not updated until the power-up or power-down process is completed. NORMAL_CFG and BLK_PWR_STAT will have different values while the power-up or power-down procedure is in progress, and will have the same value after the power state change is completed. Look up BLK_PWR_STAT register value to know whether power gating is complete or not. The power gating does not preserve the state of normal flip-flops in the power-down domain. A power domain (except TOP domain) has only normal F/Fs and is not implemented with retention F/Fs. Therefore, a power domain (except TOP domain) namely sub-domain does not preserve the state of F/Fs when the sub-domain is power-gated. When a sub-domain is powered up again, a wakeup reset is asserted for the modules in the subdomain. However, top domain has retention F/Fs instead of normal F/Fs, therefore top domain keeps the state of F/Fs when the top domain is power-gated. When top domain is powered up again, a wakeup reset is not asserted for the modules in the top domain. The power-up takes time to stabilize the internal logic gates and memory after power is supplied again. The power-up time is required because a simultaneous power-up of all logic gates and memories is not allowed since it will drain a large amount of current in a very short period and cause system malfunction consequently. 4-7 S5PV210_UM 4 3BPOWER MANAGEMENT There are two wakeup techniques. First technique is applied to TOP domain and System Timer domain, whereas the other is applied to SUB domains (except System Timer domain). The first technique is as follows: The logic gates in TOP and System Timer domains are turned “ON” in two steps, and then memories are turned “ON” one-by-one in memory group. Two steps means that about 10% of all switches are supplied power first, and the remaining 90% switches are supplied power after some time. The power-up time is composed of the logic power-up time and the memory power-up time. These are determined by the oscillator frequency, number of memories and count values given in the OSC_FREQ registers. The count value depends on the size of the logic gates and number of memories. System Timer domain has no memory, and therefore memory power-up time is not necessary. The second technique is as follows: The logic gates and memory in SUB domains (except System Timer domain) are turned “ON” at the same time. However, to prevent wakeup noise from occurring, the power to switches is supplied in two steps similar with first technique. About 10% switches are supplied power first, and remaining 90% switches are supplied power after some time. 4-8 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3.3 IDLE MODE If Cortex-A8 is not required to operate, the clock for Cortex-A8 can be disabled internally. This saves the dynamic power consumption. To disable clock to Cortex-A8, execute a Wait-For-Interrupt instruction. The remaining parts of the chip (except state of Cortex-A8 core) keep their operating states in NORMAL, that is, the running modules are still running, clock-gated modules are still clock-gated, and power-gated modules are still power-gated. To enter the IDLE mode, 1. Set CFG_STANDBYWFI field of PWR_CFG to 2’b00. 2. Execute Wait-For-Interrupt instruction (WFI). To exit the IDLE mode, wake up sources (For more information, refer to Section 4.6 "Wakeup Sources"). 4.3.4 DEEP-IDLE MODE If Cortex-A8 is not required to operate and to reduce CPU power, the power to Cortex-A8 core can be gated internally. This saves the static leakage consumption. To save the static leakage consumption, set the register IDLE_CFG in SYSCON, and execute a Wait-For-Interrupt instruction. There are three options in DEEP-IDLE mode, namely: 1. The remaining parts of the chip keep their operations in NORMAL mode. 2. The remaining parts of the chip keep their states in NORMAL mode. 3. For low power MP3 playback, TOP block and SUB block is also power-gated, but only Audio block is still power "ON". To select the above options, set TOP_LOGIC field of IDLE_CFG register in SYSCON, that is, TOP domain can either be power-on or power-gated by the setting of TOP_LOGIC field of IDLE_CFG register, before entry into IDLE mode. • TOP_LOGIC = 2’b01: TOP block and sub-blocks keep their states in NORMAL mode. Audio block is running the operation. • TOP_LOGIC = 2’b10: TOP block, sub-blocks, and Audio block is running the operation. 4-9 S5PV210_UM 4 3BPOWER MANAGEMENT To enter the DEEP-IDLE mode, 1. Make sure all PLLs are running before entering low-power mode. This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register. This step is required only when TOP_LOGIC field is set to 2'b01. 2. Set CFG_DIDLE field of IDLE_CFG to 2’b1. 3. Set other fields of IDLE_CFG based on the users' requirements. 4. Set CFG_STANDBYWFI field of PWR_CFG to 2’b01. 5. Set SYSCON_INT_DISABLE field of OTHERS to 1’b1 6. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after calling wfi instruction, this indicates wfi instruction is ignored by the processor and user should call wfi instruction again. The SYSCON performs the following sequence to enter DEEP-IDLE mode (TOP_LOGIC = 2’b01). 1. Complete all active bus transactions. 2. Complete all active memory controller transactions. 3. Allow external DRAM to enter self-refresh mode (to preserve DRAM contents). 4. Mask clock input using internal signal in SYSCON. 5. Disable all PLLs except for EPLL. 6. Selectively disable OSCs except 32.768 KHz. To exit the DEEP-IDLE mode, wake up sources (For more information, refer to Section 4.6 ). Then SYSCON performs the following sequence to exit from DEEP-IDLE mode (TOP_LOGIC = 2’b01). 1. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms). 2. Unmask clock input to clock-on blocks. 3. Enable the PLLs and wait for locking (about 300us). 4. Let DRAMs exit from self-refresh mode. 4-10 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3.5 STOP MODE In STOP mode, clock to modules (except RTC module), PLLs, and unnecessary oscillators are selectively disabled to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into Standby mode. Therefore, current application program that is running in NORMAL mode stops in STOP mode and waits for wakeup event to resume. To enter the STOP mode, 1. Make sure all PLLs are running before entering low-power mode. This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register. 2. Cut power off for all sub-blocks (LCD, CAM, TV, 3D, MFC) and verifies it is finised. 3. Set ARM_LOGIC field of STOP_CFG register to 2’b10. Set TOP_LOGIC field of STOP_CFG register to 2'b10. 4. Set other fields of STOP_CFG based on the users' requirements. 5. Set CFG_STANDBYWFI field of PWR_CFG to 2’b10. 6. Set SYSCON_INT_DISABLE field of OTHERS to 1’b1 7. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after calling wfi instruction, this indicates wfi instruction is ignored by the processor and user should call wfi instruction again. The SYSCON performs the following sequence to enter STOP mode. 1. Complete all active bus transactions. 2. Complete all active memory controller transactions. 3. Allow external DRAM to enter self-refresh mode (to preserve DRAM contents). 4. Mask clock input using internal signal in SYSCON. 5. Disable all PLLs. 6. Selectively disable OSCs except 32.768KHz. In the above procedure, to finish all active bus transactions, SYSCON asserts CSYSREQs for AXI interface components (AXI masters). If SYSCON confirms that all CSYSACKs and CACTIVEs from all AXI masters become low, then it will check that CSYSACK and CACTIVE from external memory controller become low after it asserts CSYSREQ to external memory controller to low. Then it confirms that CSYSACK and CACTIVE from external memory controller become low and proceeds to next step. 4-11 S5PV210_UM 4 3BPOWER MANAGEMENT To exit STOP mode, wake up sources (For more information, refer to Section 4.6 "Wakeup Sources"). Then SYSCON performs the following sequence to exit from STOP mode. 1. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms). 2. Enable the PLLs and wait for locking (about 300us). 3. Unmask clock input to clock-on blocks. 4. Let DRAMs exit from self-refresh mode. OSC stabilization time is determined by the external clock frequency and counter value specified in the OSC_STABLE register. PLL locking time is set in PLL_LOCK registers. 4-12 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3.6 DEEP-STOP MODE In DEEP-STOP mode, Cortex-A8 Core is power-gated rather than clock-gated, and the remaining parts of the chip are power-gated (except RTC module). However, TOP domain can either be power-on or power-gated by setting TOP_LOGIC field of STOP_CFG register before entry into DEEP-STOP mode. Cortex-A8 L2 cache can be powered on for memory retention or power-gated to save power. • TOP_LOGIC = 2’b01, TOP block is power-gated. • TOP_LOGIC = 2’b10, TOP block is power ”ON”. To enter the DEEP-STOP mode, 1. Make sure all PLLs are running before entering low-power mode. This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register. 2. Cut power off for all sub-blocks (LCD, CAM, TV, 3D, MFC) and verifies it is finised. 3. Set ARM_LOGIC field of STOP_CFG register to 2’b00. 4. Set other fields of STOP_CFG based on the users' requirements. 5. Set CFG_STANDBYWFI field of PWR_CFG to 2’b10 6. Set SYSCON_INT_DISABLE field of OTHERS to 1’b1 7. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after calling wfi instruction, this indicates wfi instruction is ignored by the processor and user should call wfi instruction again. The SYSCON performs the following sequence to enter DEEP-STOP mode. 1. Complete all active bus transactions. 2. Complete all active memory controller transactions. 3. Allow external DRAM to enter self-refresh mode (to preserve DRAM contents). 4. Mask clock input using internal signal in SYSCON. 5. Disable all PLLs. 6. Selectively disable OSCs except 32.768KHz. To exit the DEEP-STOP mode, wake up sources (For more information, refer to Section 4.6 "Wakeup Sources"). Then SYSCON performs the following sequence to exit from DEEP-STOP mode. 1. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms). 2. Enable the PLLs and wait for locking (about 300us). 3. Unmask clock input to clock-on blocks. 4-13 S5PV210_UM 4. Let DRAMs exit from self-refresh mode. 4 3BPOWER MANAGEMENT 4-14 S5PV210_UM 4 3BPOWER MANAGEMENT 4.3.7 SLEEP MODE In SLEEP mode, all power domains are powered down (except ALIVE and RTC), all PLLs are disabled, and the oscillators (except RTC) are selectively disabled. To enter the SLEEP mode, 1. Set SLEEP_CFG based on the users' requirements. 2. Set CFG_STANDBYWFI field of PWR_CFG to 2’b11. 3. Set SYSCON_INT_DISABLE field of OTHERS to 1’b1 4. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after calling wfi instruction, this indicates wfi instruction is ignored by the processor and user should call wfi instruction again. Then the SYSCON performs the following sequence to enter SLEEP mode. 1. Complete all active bus transactions. 2. Complete all active memory controller transactions. 3. Allow the external DRAM enter self-refresh mode (to preserve DRAM contents). 4. Disable all PLLs. 5. Selectively disable OSCs except 32.768 KHz. 6. XPWRRGTON becomes low to power off external voltage regulator. To exit the SLEEP mode, wake up sources referred in section Wakeup Sources. Then the SYSCON performs the following sequence to exit from SLEEP mode. 1. Assert wake-up reset to low. 2. XPWRRGTON becomes high to power on external voltage regulator. 3. Wait for voltage regulator to be stable (around 6ms). 4. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms.) 5. Power up all power domains except power domains, which was power-down state before entering the SLEEP Mode. 6. Release wake-up reset. Since all modules are powered “OFF” and their states are not preserved in SLEEP mode, you must save and restore necessary state information before and after SLEEP mode. An example procedure of state saving and recovery is described in Section 4.5.3 "State Save and Restore" on page 4-24. 4-15 S5PV210_UM 4 3BPOWER MANAGEMENT Caution: Executing wfi instruction is a mandatory step when entering low-power mode. To make sure the processor does not ignore wfi instruction, it is recommended to make a loop statement around the wfi instruction. The loop repeatedly calls wfi instruciton until SYSCON_INT_DISABLE field of OTHERS register to become LOW, which indicates low-power mode entering sequence is completed. 4-16 S5PV210_UM 4.4 SYSTEM POWER MODE TRANSITION Figure 4-1 shows the state transition diagram of power mode. 4 3BPOWER MANAGEMENT IDLE System Reset ARM command NORMAL IDLE wake-up sources ARM cIoDmLEmawsnoadukrec-eusp DEEPIDLE STOP ARM command STOP wake-up sources ARM command SLEEP wake-up sources ARM command SsToOurPcewsake-up DEEPSTOP SLEEP Figure 4-1 State Transition Diagram of Power Mode The wakeup sources described in Figure 4-1 are summarized in Table 4-4. The detail operation is shown Figure 4-2. 4-17 S5PV210_UM 4 3BPOWER MANAGEMENT NORMAL Write SFR PWR_MODE / STANDBYWFI Wait CLKST OPACK / STANDBYWFI DIS_ AR MC LK Mask ARMCLK IDLE I DLE/ STOP Reset ARM EN_ AR MCLK Unmask ARMCLK TOP _IDL E STOP_ BU S Disable BUS operation STOP_ DR AM D-IDLE & Request DRAM LOGIC =RET power-down STOP_ A LLCLK0 STOP_ ALLCLK1 Disable all clocks except for EPLL Disable all clocks RU N_ B US Enable BUS operation Operation e n ab le/ dis ab le sequece RU N_ D RAM Enable DRAM RU N_ A LLCLK D-IDLE & LOGIC=ON D-IDLE & LOGIC=ON Enable all clocks SYSCLK Change SYSCLK PLLCLK Change PLL FOUT SLEEP PWD N_ SUB Power down sub -blocks DIS_ AR MIO Clamping Cortex-A8 PWU P_SUB Power up sub-blocks EN_ AR MIO Enable Cortex-A8 I/ O SLEEP PWD N_ SRA M PMU_TOP_GAT E.v PWU P_SRA M Disable SRAM Enable SRAM STOP & PWD N_ A RM Power down Cortex-A8 LOGIC=RET EN _FF_ RET (D-I DLE|D-STOP)& LOGIC=ON LOGIC=ON Enable F F retention PWU P_A RM Power up Cortex-A8 (D- IDL E|D-S TOP) & LOGIC=ON DIS_ FF_RET STOP & LOGIC=RET Disable F F ret ention STOP& LOGIC=ON TOP_GATED STOP| D-STOP|SLEEP ALIVE_GPIO Change GPIO D-IDLE & selection LOGIC= RETEN_PAD_RET Enable PAD ret ention EN _PA D_ GATE Enable PAD gating (CPGI) EN _ISO_ EN SLEEP Disable isolation cells (ISO _EN) PWR_OFF Power OFF DIS_ SC Disable footer cells (SCPRE, SCALL) S LEEP D-IDLE/ D-STOP /STOP D-IDLE & LOGIC=ON D-IDLE & L OGIC= ONNO RMA L_G PIO Change GPIO selection S/W DIS_ PAD _RET Disable PAD e n ab le/ dis ab le ret ent io n sequece DIS_ PAD _GA TE Disable PAD gating (D-)STOP & (D-)STOP ) & (CPGI) LOGIC=ON L OGIC=ONDIS_ ISO _EN E nab le isolation cells ( ISO_E N) EN_ SC PRE/A LL Enable all footer cells (SCPRE, SCALL) OSC_ STABLE OSC stable D- IDL E & LOGIC=RET Figure 4-2 PWR _STA BLE Power stable Internal Operation During Power Mode Transition 4-18 S5PV210_UM 4 3BPOWER MANAGEMENT 4.4.1 TRANSITION ENTERING/ EXITING CONDITION Table 4-4 shows the Power Saving mode state and Entering or Exiting condition. As you can see, the entering conditions are set by the main ARM CPU. Power Mode General Clock Gating IDLE DEEP-IDLE (TOP block on) DEEP-IDLE (TOP block off) (DEEP) STOP SLEEP Table 4-4 Power Saving Mode Entering/Exiting Condition Enter Exit Use S/W to set the Clock-disable Bit for each Use S/W to clear the Clock-disable Bit for IP block each IP block Set CFG_STANDBYWFI field of PWR_CFG to 2’b00. 1) All interrupt sources2 Execute Wait-For-Interrupt instruction (WFI). 1) External Interrupt1 Set CFG_DIDLE field of IDLE_CFG to 0x1. 2) RTC Alarm Set TOP_LOGIC field of IDLE_CFG to 0x2. 3) RTC TICK Set other fields of IDLE_CFG for users’ need. 4) Key Pad Press event Set CFG_STANDBYWFI field of PWR_CFG to 2’b01. 5) MMC0~3 Set SYSCON_INT_DISABLE field of OTHERS 6) Touch Screen Pen-down event to 1’b1 7) I2S in audio sub-block wake-up event Execute Wait-For-Interrupt instruction (WFI). 8) System Timer event 9) CEC wake-up event 1) External Interrupt1 Set CFG_DIDLE field of IDLE_CFG to 0x1. 2) RTC Alarm Set TOP_LOGIC field of IDLE_CFG to 0x1. 3) RTC TICK Set other fields of IDLE_CFG for users’ need. 4) Key Pad Press event Set CFG_STANDBYWFI field of PWR_CFG to 5) MMC0~3 2’b01. 6) Touch Screen Pen-down event Set SYSCON_INT_DISABLE field of OTHERS 7) I2S in audio sub-block wake-up event to 1’b1 8) System Timer event Execute WFI. 9) CEC wake-up event 10) System Timer event Set ARM_LOGIC field of STOP_CFG register. 1) External Interrupt1 (0x2 for STOP and 0x0 for DEEP-STOP) 2) RTC Alarm Set other fields of STOP_CFG for users’ need. 3) RTC TICK Set CFG_STANDBYWFI field of PWR_CFG to 4) Key Pad Press event 2’b10. 5) MMC0~3 Set SYSCON_INT_DISABLE field of OTHERS 6) Touch Screen Pen-down event to 1’b1 7) System Timer event Execute WFI. 8) CEC wake-up event Set SLEEP_CFG for users’ need. 1) External Interrupt1 Set CFG_STANDBYWFI field of PWR_CFG to 2) RTC Alarm 2’b11. 3) RTC TICK Set SYSCON_INT_DISABLE field of OTHERS to 1’b1 4) Key Pad Press event Execute WFI. 5) CEC wake-up event 4-19 S5PV210_UM 4 3BPOWER MANAGEMENT 1. External Interrupt includes OneDRAM Interrupt 2. Depends on their interrupt mask bits. Power mode exit condition is met when one of various wakeup sources occurs. For more information on wakeup sources, refer to 4.6 "Wakeup Sources". 4-20 S5PV210_UM 4 3BPOWER MANAGEMENT 4.5 CORTEX-A8 POWER MODE 4.5.1 OVERVIEW Cortex-A8 has its own four power modes, namely, RUN, STANDBY, L2RETENTION, and POWER-OFF. In each power mode, power control of Cortex-A8 is done as follows: • In RUN mode, Core logic of Cortex-A8 is powered "ON" and clocked. The L2 cache of Cortex-A8 is power-on. • In STANDBY mode, Core logic of Cortex-A8 is powered "ON" and only wake-up logic is clocked. The L2 cache of Cortex-A8 is power-on. • In L2RETENTION mode, Core logic of Cortex-A8 is power-gated and L2 cache of Cortex-A8 enters retention mode for data retention. Therefore, the data of L2 cache can be kept in this mode. • In POWER-OFF mode, all components of Cortex-A8 (that is, Core logic, L2 cache, ETM, and NEON) are all power-gated. 4.5.2 CORTEX-A8 POWER MODE TRANSITION For information on entry to and exit from STANDBY mode in IDLE mode, refer to 4.3.3 "IDLE Mode". For information on entry to and exit from L2RETENTION and POWER-OFF in DEEP-IDLE mode, refer to 4.3.4 "DEEP-IDLE Mode". In IDLE and STOP mode, Cortex-A8 enters STANDBY mode. In DEEP-IDLE and DEEP-STOP mode, Cortex-A8 enters L2RETENTION or POWER-OFF mode depending on the selection of L2 retention mode, that is, IDLE_CFG[27:26] for DEEP-IDLE mode, and STOP_CFG[27:26] for DEEP-STOP mode. In SLEEP mode, Cortex-A8 automatically enters POWER-OFF mode. Before entry into SLEEP mode, state of Cortex-A8 must be saved in external memory. Figure 4-3 shows the state transition diagram of Cortex-A8 power mode, and the relationship between System power mode and Cortex-A8 power mode transition is summarized in Table 4-5. STANDBY, L2RETENTION, and POWER-OFF modes transition from RUN mode can be done in NORMAL system power mode. STANDBY mode of Cortex-A8 can exist in IDLE and STOP system power modes. L2RETENTION mode of Cortex-A8 can exist in DEEP-IDLE and DEEP-STOP system power mode. POWER-OFF mode of Cortex-A8 can exist in DEEP-IDLE, DEEP-STOP, and SLEEP system power mode. RUN mode transitions from STANDBY, L2RETENTION, and POWER-OFF can be done by wakeup sources. In IDLE mode, internal interrupts, external interrupts, and RTC alarm can be wakeup sources. In DEEP-IDLE mode, external interrupts, wakeup event, and RTC alarm can be wakeup sources. In STOP, and DEEP-STOP, external interrupts, wakeup event, and RTC alarm can be wakeup sources. 4-21 S5PV210_UM 4 3BPOWER MANAGEMENT DEEP - IDLE, DEEP - STOP NORMAL DEEP - IDLE, DEEP - STOP, SLEEP WFI instruction L2RE TE NTION RUN WFI instruction POWER - OFF Wakeup event Wakeup event WFI instruction Wakeupevent STANDBY IDLE, STOP power mode Cortex - A8 power Figure 4-3 Cortex-A8 Power Mode Transition Diagram 4-22 S5PV210_UM 4 3BPOWER MANAGEMENT Cortex-A8 power mode transition NORMAL Cortex-A8 Core RUN Æ STANDBY RUN Æ L2RETENTION RUN Æ POWER-OFF STANDBY Æ RUN L2RETENTION Æ RUN POWER-OFF Æ RUN N.A: Not Available By WFI command By register setting and WFI command (SYSCON) By register setting and WFI command (SYSCON) N.A N.A N.A Table 4-5 Cortex-A8 Power Control System Power Mode IDLE DEEP-IDLE STOP Run with IEM1) Standby Power gating Standby N.A Standby DEEP-STOP SLEEP Standby Power gating N.A. N.A. N.A. L2RETENTION N.A. L2RETENTION N.A. N.A. POWER-OFF N.A. POWER-OFF POWEROFF Wakeup by interrupt N.A. N.A. N.A Wakeup by interrupt Wakeup by interrupt Wakeup by interrupt N.A N.A. N.A. Wakeup by interrupt Wakeup by interrupt N.A. N.A. Wakeup by interrupt 4-23 S5PV210_UM 4 3BPOWER MANAGEMENT 4.5.3 STATE SAVE AND RESTORE The current state of power-gated modules will be lost when their power turns ”OFF”. Therefore, before the modules are power-gated, their state should be saved, and restored after wakeup reset is asserted. In case of Cortex-A8, in DEEP-IDLE, DEEP-STOP, and SLEEP mode, the state of Cortex-A8 core will be lost, therefore the current states must be saved. Cortex-A8 will start running from the reset handler as it does when hardware reset occurs. To continue execution from the point where it entered SLEEP mode, users must save and restore the current states before and after those modes. An example of state save and restore is described below. Before entering SLEEP mode, 1. Save the status of necessary modules. 2. Save resume address, MMU (Memory Management Unit), and registers for each Cortex-A8 mode (SVC, FIQ, IRQ, ABT, etc.). 3. Create and save checksum for security. 4. Flush cache if L2 cache is power-gated. After wake-up, 1. Proceed to normal system initialization sequence including PLL locking. 2. Look up the RST_STAT register to check if it is the wake-up from SLEEP mode. 3. Let external DRAM exit from self-refresh mode. 4. Restore all registers and MMU information. 5. Jump to the saved resume address to resume execution. The SYSCON has eight 32-bit SFRs, namely, INFORM0-6 for quick saving and recovery of the state information, or you can save information to external DRAM. 4-24 S5PV210_UM 4 3BPOWER MANAGEMENT 4.6 WAKEUP SOURCES Table 4-6 Relationship Among Power Mode Wakeup Sources Power Mode IDLE DEEP-IDLE DEEP-IDLE (2) (1) STOP or DEEPSTOP SLEEP Wakeup Sources All interrupt sources I2S (in audio block) MMC0, MM1, MMC2, MMC3 TSADC System Timer External interrupt sources (EINT) RTC Alarm RTC TICK KEYIF HDMI CEC NOTE: 1. If TOP block on 2. If TOP block off 4.6.1 EXTERNAL INTERRUPTS External interrupts are the common wake-up source of IDLE (including DEEP-IDLE), STOP (including DEEPSTOP), and SLEEP modes. The logic for external interrupt configuration such as polarity, edge/level sensitivity, and masking resides in the GPIO. It can be modified through GPIO register setting before entering power down modes. The external interrupt handling logic holds the external interrupt information until Cortex-A8 clears the information. It allows Cortex-A8 to handle the external interrupt after wake-up. 4.6.2 RTC ALARM The Real Time Clock (RTC) has 32-bit counter to wake up the system after specified time. If the timer alarm triggers, the SYSCON wakes up the system and sets the RTL_ALARM field of WAKEUP_STAT register to 1. After the wake-up, Cortex-A8 can refer the WAKEUP_STAT register to find out the cause of wake up. 4.6.3 SYSTEM TIMER System Timer is newly introduced module in S5PV210. It supplements PWM timer, which suffers from accumulation of time deviation when operated in variable tick mode. On the contrary, System Timer is free from such deviation and can be a preferrable choice for variable tick generation. In DEEP-IDLE, STOP, and DEEP-STOP mode, there can be no system clock when TOP block is power-gated. Therefore, RTC is used to generate timing tick instead of PWM timer, but by using this clock, timing count is not controlled to meet exact 1ms OS time tick since RTC clock does not have high resolution. On the other hand, System timer has the function to generate interrupts at various interval, and do not require manual setting. Thus, it does not wake up the chip too often, and provides accurate 1ms timing ticks. It uses an external crystal clock, RTC clock and the generated clock from SYSCON as clock input. For System Timer to operate in DEEP-IDLE, STOP, and DEEP-STOP mode, power to System Timer is not gated. The wakeup event from System Timer will wake up S5PV210 from DEEP-IDLE, STOP, and DEEP-STOP mode. 4-25 S5PV210_UM 4 3BPOWER MANAGEMENT 4.7 EXTERNAL POWER CONTROL Table 4-7 shows the external power control summary. Table 4-7 S5PV210 External Power Control Block Controlled by NORMAL IDLE/ DEEP-IDLE (1) DEEP-IDLE (2) / STOP / DEEP-STOP SLEEP 1 USB OTG PHY USB OTG link Run / IDLE / Suspend Keep operation or power state in NORMAL Suspend Should be externally powered-off. 2 HDMI PHY HDMI link Run / Power-down Keep operation or power state in NORMAL Power-down Should be externally powered-off. 3 MIPI D-PHY MIPI link Run / LP / ULPS Keep operation or power state in NORMAL LP / ULPS Should be externally powered-off. 4 PLL SYSCON Run / Power-down Keep operation or power state in NORMAL Power-down Should be externally powered-off. Run / Keep operation Should be 5 DAC TV Encoder logic or power state Power-down externally Power-down in NORMAL powered-off. 6 TSADC TSADC logic Run / Power-down Keep operation or power state in NORMAL Standby / Power-down Power-down / Power-off 7 Digital I/O SYSCON Power-on Power-on Power-on Power-on NOTE: 1. TOP block on 2. TOP block off 4-26 S5PV210_UM 4 3BPOWER MANAGEMENT 4.7.1 USB OTG PHY USB OTG PHY has three power modes, namely, Run, IDLE, and Suspend mode. • In Run mode, USB OTG PHY sends and receives data normally. • In IDLE mode, there is no data transaction to and from USB OTG PHY. However, the clock is still supplied to USB OTG PHY. • In Suspend mode, USB OTG PHY clock is “OFF” to save power. In NORMAL mode, all the three power modes can be used. If USB OTG PHY is in use, then it is in Run mode when there is data transaction, and in IDLE mode when there is no data transaction. The USB OTG link performs the change between these two modes. If USB OTG PHY is not in use, then it can enter into Suspend mode. Set register in USB OTG for Entry to, and Exit from Suspend mode. In IDLE mode and DEEP-IDLE mode where TOP block is ”ON”, USB OTG PHY keeps its operation or power state in NORMAL. Before entry to DEEP-IDLE mode where TOP block is ”OFF”, STOP, DEEP-STOP, and SLEEP mode, it is recommended that USB OTG PHY enter into Suspend mode. 4.7.2 HDMI PHY HDMI PHY has two power modes, namely, Run and Power-down mode • In Run mode, HDMI PHY sends and receives data normally. • In Power-down mode, all power to HDMI PHY is “OFF” internally. In NORMAL mode, both the power modes can be used. If you want to use HDMI PHY, then set it in the Run mode. Otherwise, it can enter into Power-down mode to save static power by setting register in HDMI link. I2C I/F can control the mode transition from normal mode to powerdown mode. The hardware signal, PWR_OFF, is not used for this purpose. In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, HDMI PHY keeps its operation or power state in NORMAL. Before entry to DEEP-IDLE mode where TOP block is ”OFF”, STOP, DEEP-STOP, and SLEEP mode, it is recommended that HDMI PHY enter into Power-down mode. 4-27 S5PV210_UM 4 3BPOWER MANAGEMENT 4.7.3 MIPI D-PHY MIPI D-PHY has three power modes, namely, Run, LP, and ULPS mode • In Run mode, MIPI D-PHY sends and receives data normally. • In LP and ULPS mode, all power MIPI D-PHY is off internally. In NORMAL mode, all three power modes can be used. If you want to use MIPI D-PHY, then you should set it in the Run mode. Otherwise, it can enter into LP or ULPS mode to save static power by setting register in MIPI link. In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, MIPI D-PHY keeps its operation or power state in NORMAL. Before entry to DEEP-IDLE mode where TOP block is ”OFF”, STOP, and DEEP-STOP mode, it is recommended that MIPI D-PHY enter into LP or ULPS mode. Before entry to SLEEP, it is recommended that MIPI D-PHY enter into ULPS mode. For more details about LP and ULPS mode, refer to MIPI D-PHY user’s manual. 4.7.4 PLL PLL has two power modes, namely, Run and Power-down mode • In Run mode, PLL sends and receives data normally. (Iop = max. 2mA@4502A, max. 1mA@4500B) • In Power-down mode, all power to PLL is “OFF” internally. (Ipd = max 80uA) In NORMAL mode, both power modes can be used. If you want to use PLL, then you should set it in the Run mode. Otherwise, it can enter into Power-down mode to save static power by setting register (APLLCON, MPLLCON, EPLLCON, VPLLCON) in SYSCON. In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, PLL keeps its operation or power state in NORMAL. In DEEP-IDLE mode where TOP block is “OFF”, APLL, MPLL, and VPLL are powered down automatically by SYSCON. Note that EPLL is still powered on in this mode to provide proper operating clock to Audio sub-block. In STOP and SLEEP mode, all PLLs are powered down automatically by SYSCON. 4-28 S5PV210_UM 4 3BPOWER MANAGEMENT 4.7.4.1 Status of PLL after Wake-Up Event When the S5PV210 wakes up from STOP mode or SLEEP mode by an External Interrupt, a RTC alarm wakeup and other wakeup events, the PLL is turned “ON” automatically. However, the clock supply scheme is quite different. The initial-state of the S5PV210 after wake-up from the SLEEP mode is almost the same as the PowerOn-Reset state except that the contents of the external DRAM is preserved. On the other hand, the S5PV210 automatically recovers the previous working state after wake-up from the STOP mode. The following Table 4-8 shows the states of PLLs and internal clocks after wake-ups from the power-saving modes. Mode before wake-up IDLE DEEP-IDLE STOP DEEP-STOP SLEEP Table 4-8 The Status of MPLL and SYSCLK After Wake-Up MPLL on/off after wake up unchanged off → on off → on off → on off → off SYSCLK after wake up and before the lock time PLL Output PLL Output PLL reference clock PLL reference clock PLL reference clock SYSCLK after the lock time by internal logic PLL Output PLL Output PLL Output PLL Output PLL reference clock 4.7.5 DAC DAC has two power modes, namely, Run and Power-down mode • In Run mode, DAC sends and receives data normally. (Iop = min. 19mA, typ. 23mA, max. 27mA) • In Power-down mode, all power to DAC is off internally. (Ipd = max. 100uA) In NORMAL mode, both power modes can be used. If DAC is in use, then it is in Run mode. Otherwise, it can enter into Power-down mode to save static power by setting register in TVOUT logic. In IDLE mode, and DEEP-IDLE mode where TOP block is on, DAC keeps its operation or power state in NORMAL. Before entry to DEEP-IDLE mode where TOP block is ”OFF”, STOP and SLEEP mode, it is recommended that DAC enter into Power-down mode. 4-29 S5PV210_UM 4 3BPOWER MANAGEMENT 4.7.6 ADC I/O In DEEP-IDLE mode where TOP block is off, and DEEP-STOP mode where TOP block is off, the output port of normal I/O keeps its driving value before entering DEEP-IDLE/ DEEP-STOP mode. Normal I/O has output retention function, and it uses latch to keep its driving value. The retention control signal to input port (RTO, CPGI) of normal I/O is generated by SYSCON when entering DEEP-IDLE/ DEEP-STOP mode. RTO is first asserted to 1’b0 to latch the output value, and then CPGI is asserted to 1’b0 to prevent leakage path from power-off block. Finally, power-gating signal (nSCPRE, nSCALL) is asserted to 1’b0 to power off the block. RTO is 3.3V signal, and becomes 3.3V via level-shifter. Alive I/O also keeps its driving value from power-off region before entering DEEP-IDLE/DEEP-STOP mode. SYSCON generates the retention control signal (CPGI). In SLEEP mode, internal power to normal I/O is ”OFF”, and I/O power to normal I/O is still ”ON”. SYSCON generates the retention control signal (RTO and CPGI) while entering SLEEP mode. Alive I/O changes its output path from Normal path (power-off region) to ALIVE path (ALIVE module). RTO is asserted to 1’b0 to latch the output value. ALIVE module drives output value of alive I/O in SLEEP mode. Read value from alive I/O goes to ALIVE module. This read values acts as wakeup source in SLEEP mode. 4.7.7 POR Power-On-Reset (POR) uses alive power. Thus, there is no power-down mode. The maximum current is up-to 10uA. 4-30 S5PV210_UM 4 3BPOWER MANAGEMENT 4.8 INTERNAL MEMORY CONTROL Table 4-9 shows the internal memory power control summary. Table 4-9 S5PV210 Internal Memory Control Block Controlled by NORMAL IDLE/ DEEP-IDLE(1) DEEP-IDLE(2) / STOP / DEEP-STOP 1 SRAM SYSCON Run / Keep operation Stand-by or power state Retention / Stand-by in NORMAL Power-down 2 ROM SYSCON Run / Stand-by / Keep operation or power state Stand-by / Power-down in NORMAL Power-down SLEEP (Power off) (Power off) 4.8.1 SRAM SRAM in TOP block has four power modes, namely, Run, Stand-by, Retention, and Power-down mode. • In Run mode, read and write access to SRAM can be performed normally. • In Stand-by mode, SRAM chip select is deactivated, so that there is no read and write access. • In Retention mode, power is provided to only core of SRAM, and power to peripheral circuitry is ”OFF” internally. • In Power-down mode, all power to core and peripheral circuitry is ”OFF”. In NORMAL mode, run, or stand-by mode can be used. Run mode is used when there is read and write access, while stand-by mode is used when there is no read and write access. The change between these two modes can be done by module that has SRAM. In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, SRAM keeps its operation or power state in NORMAL. In DEEP-IDLE mode where TOP block is ”OFF”, SRAM in TOP module can enter stand-by, retention, or powerdown mode. Before entering this mode, you must set the TOP_MEMORY field IDLE_CFG in SYSCON. In STOP mode and DEEP-STOP mode, stand-by, retention, and power-down mode can be entered. Before entry to STOP mode, you must set the TOP_MEMORY field of STOP_CFG register in SYSCON to determine which power mode SRAM will enter during STOP mode. In SLEEP mode, power to SRAM is off, so the data in SRAM will be lost. Power mode in SLEEP mode has no meaning. 4-31 S5PV210_UM 4 3BPOWER MANAGEMENT 4.8.2 ROM ROM has three power modes, namely, Run, Stand-by, and Power-down mode. • In Run mode, read access to ROM can be performed normally. • In Stand-by mode, chip selection to ROM is deactivated, so that there is no read access. • In Power-down mode, all power to core and peripheral circuitry is off internally. In NORMAL mode, all three power modes can be used. When ROM is in use, two power modes are available. Run mode is used when there is read access, while Standby mode is used when there is no read access. The decision to move from one mode to another is made by the internal ROM controller. If ROM is not in use, then it can enter into Power-down mode. Set the IROM field of NORMAL_CFG register in SYSCON for Entry to, and exit from Power-down mode. In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, ROM keeps its operation or power state in NORMAL. In DEEP-IDLE mode where TOP block is ”OFF”, STOP mode and DEEP-STOP mode, ROM can have two power states. If IROM bit of NORMAL_CFG is 1’b1, then ROM keeps stand-by mode. Otherwise, ROM keeps power down mode. In SLEEP mode, power to ROM is ”OFF”, so the data in ROM will be lost. Power mode in SLEEP mode has no meaning. 4-32 S5PV210_UM 4 3BPOWER MANAGEMENT 4.9 RESET CONTROL 4.9.1 RESET TYPES S5PV210 has four types of resets and reset generator can place the system into one of five reset states. There are five reset states, namely: • Hardware Reset - The hardware reset is generated when XnRESET is driven to low. It is an uncompromised, ungated, and total reset that is used to drive S5PV210 to a known initial state. • Watchdog Reset - Reset signal by watchdog timer • Software Reset - Reset signal by setting special control register • Warm reset - Reset signal by XnWRESET pin. • Wakeup Reset - Reset signal generated when a module that has normal F/Fs is powered down, and the module is powered up again by wakeup events; but in sleep mode, wakeup reset is generated to all modules that were powered off regardless of normal F/F or retention F/F. Five resets have the following priorities: Hardware Reset > Watchdog Reset > Warm Reset > Software Reset > Wakeup Reset 4.9.2 HARDWARE RESET Hardware reset is asserted when the XnRESET pin is driven to low, and all units in the system (except RTC function module) are reset to known states. During the hardware reset, the following actions take place: • All internal registers and Cortex-A8 go into their pre-defined reset state. • All pins get their reset state. • The XnRSTOUT pin is asserted when XnRESET is driven. Hardware reset is asserted when an external source drives the XnRESET input pin low. XnRESET is nonmaskable, and therefore is always applicable. Upon assertion of XnRESET, S5PV210 enters into reset state regardless of the previous state. For hardware reset to be asserted actually, XnRESET must be held long enough to allow internal stabilization and propagation of the reset state. Caution: Power regulator for system must be stable prior to the deassertion of XnRESET. If power regulator for system is not stable, it damages to S5PV210 and its operation is not guaranteed. 4-33 S5PV210_UM 4 3BPOWER MANAGEMENT Figure 4-4 shows the clock behaviour during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds after the power supply supplies enough power-level to the S5PV210. Internal PLLs are disabled after power-on reset is asserted. XnRESET signal should be released after the fully settle-down of the power supply-level. For the proper system operation, the S5PV210 requires a hazard-free system clock (SYSCLK, ARMCLK, HCLK and PCLK) when the system reset is released (XnRESET). However, since PLLs are disabled, Fin (the direct external oscillator clock) is fed directly to SYSCLK instead of the MPLL_CLK (PLL output) before the S/W configures the MPLLCON register to enable the operation of PLLs. If new P/M/S values are required, the S/W configures P/M/S field first, and the PLL_EN field later. The PLL begins the lockup sequence toward the new frequency only after the S/W configures the PLL with a new frequency-value. SYSCLK is configured to be PLL output (MPLL_CLK) immediately after lock time. The user should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the power-up sequence. The S5PV210 assumes that the crystal oscillation is settled during the power-supply settle-down period. However, to ensure the proper operation during wake-up from the STOP mode, the S5PV210 explicitly adds the crystal oscillator settle-down time (the wait-time can be programmed using the OSC_STABLE registers) after wake-up from the STOP mode. S5PV210 has four PLLs, namely, APLL, MPLL, EPLL, and VPLL. • APLL: used to generate ARM clock • MPLL: used to generate system bus clock and several special clocks • EPLL: used to generate several special clocks • VPLL: used to generate Video clocks. Usually, generates 54 MHz. 1.1V VDDALIVE 0.6V VDDINT/ 1.1V VDDARM 3.3V/2.5V/1.8V VDDIO XPWRRGTON XnRESET (internal) RESETn XXTI >0ns >0ns OSC _STABLE Power-on transition max (OSC_STABLE, PWR_STABLE) NORMAL mode SLEEP mode Wake-up from SLEEP NORMAL mode >0ns >0ns Power-off transition Figure 4-4 Power-ON/OFF Reset Sequence 4-34 S5PV210_UM 4 3BPOWER MANAGEMENT 4.9.2.1 Watchdog Reset Watchdog reset is asserted when software fails to prevent the watchdog timer from timing out. In watchdog reset all units in S5PV210 (except some blocks listed in Table 4-10) are reset to their predefined reset states. The behavior after Watchdog reset is asserted, is the same as Hardware reset case. (Refer to 4.9 "Reset Control") During the watchdog reset, the following actions occur: • All units (except some blocks listed in Table 4-10) go into their pre-defined reset state. • All pins get their reset state. • The XnRSTOUT pin is asserted during watchdog reset. Watchdog reset can be activated in NORMAL and IDLE (DEEP-IDLE) mode because watchdog timer can expire with clock. Watchdog reset is asserted when watchdog timer and reset are enabled (WTCON[5] = 1, WTCON[0]=1) and watchdog timer is expired. Watchdog reset is asserted then, the following sequence occurs: 1. WDT generate time-out signal. 2. SYSCON invokes reset signals and initialize internal IPs. 3. The reset including nRSTOUT will be asserted until the reset counter, RST_STABLE, is expired. 4.9.2.2 Software Reset Software reset is asserted when CPU write “1” to SWRESET register in NORMAL mode. During the software reset, the following actions occur: • All units (except some blocks listed in Table 4-10) go into their pre-defined reset state. • All pins get their reset state. • The XnRSTOUT pin is asserted during software reset. When Software reset is asserted the following sequence occurs. 1. SYSCON requests bus controller to finish current transactions. 2. Bus controller send acknowledge to SYSCON after completed bus transactions. 3. SYSCON request memory controller to enter into self refresh mode. 4. SYSCON wait for self refresh acknowledge from memory controller. 5. Internal reset signals and XnRSTOUT are asserted and reset counter is activated. 6. Reset counter is expired, then internal reset signals and XnRSTOUT are deasserted. 4-35 S5PV210_UM 4 3BPOWER MANAGEMENT 4.9.2.3 Warm Reset Warm reset is asserted when XnWRESET is asserted to ‘0’. During the warm reset, the following actions occur: • All units (except some blocks listed in Table 4-10) go into their pre-defined reset state. • All pins get their reset state. • The XnRSTOUT pin is asserted during software reset. When warm reset is asserted the following sequence occurs. 1. SYSCON requests bus controller to finish current transactions. 2. Bus controller send acknowledge to SYSCON after completed bus transactions. 3. SYSCON request memory controller to enter into self refresh mode. 4. SYSCON wait for self refresh acknowledge from memory controller. 5. Internal reset signals and XnRSTOUT are asserted and reset counter is activated. 6. Reset counter is expired, then internal reset signals and XnRSTOUT are deasserted. 4.9.2.4 Wakeup Reset Wakeup reset is asserted when a module that has normal F/Fs is powered down, and the module is powered up again by wakeup events. Note that if the module has only retention F/Fs, wakeup reset is not asserted. However, in sleep mode, wakeup reset is generated to all modules that were powered off regardless of normal F/F or retention F/F. Therefore, wakeup reset can be asserted in NORMAL, DEEP-IDLE, DEEP-STOP, and SLEEP mode. In NORMAL mode, when a sub-domain is powered down, and the sub-domain is powered up again, wakeup reset is asserted to the sub-domain. In DEEP-IDLE and DEEP-STOP mode, wakeup reset is asserted to Cortex-A8, since Cortex-A8 is powered up again when wakeup event occurs in these power modes. Wakeup reset is also asserted to a sub-block that becomes power on after exiting from DEEP-IDLE and DEEP-STOP mode. Finally, wakeup reset is asserted when the system is waked up from sleep mode by wakeup event. Register initialization due to various resets, is shown in Table 4-10. 4-36 S5PV210_UM 4 3BPOWER MANAGEMENT Table 4-10 Register Initialization Due to Various Resets ALIVE Power On Reset XnRESET Watchdog Software Reset Warm Reset Wakeup from SLEEP Block Register SYSCON (PMU) INFORM4~7, OM_STAT X XXO SYSCON (PMU) RST_STAT, PS_HOLD_CONTROL X XOO OSC_CON, PWR_CFG, EINT_WAKEUP_MASK, WAKEUP_MASK, PWR_MODE, NORMAL_CFG, IDLE_CFG, STOP_CFG, STOP_MEM_CFG, SLEEP_CFG, OSC_FREQ, OSC_STABLE, SYSCON (PMU) PWR_STABLE, MTC_STABLE, CLAMP_STABLE, X OOO WAKEUP_STAT, BLK_PWR_STAT, OTHERS, HDMI_CONTROL, USB_PHY_CONTROL, MIPI_DPHY_CONTROL, ADC_CONTROL, DAC_CONTROL, INFORM0~6 RTC RTCCON, TICCNT, RTCALM, ALMSEC, ALMMIN, ALMHOUR, ALMDAY, ALMMON, ALMYEAR, X OOO RTCRST Others - O OOO 4-37 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10 REGISTER DESCRIPTION Do not change any reserved area. Changing value of Reserved area can lead to undefined behavior. 4.10.1 REGISTER MAP Register OSC_CON Reserved RST_STAT Reserved PWR_CFG EINT_WAKEUP_MASK WAKEUP_MASK PWR_MODE NORMAL_CFG Reserved IDLE_CFG Reserved STOP_CFG STOP_MEM_CFG Reserved SLEEP_CFG Reserved OSC_FREQ OSC_STABLE PWR_STABLE Reserved MTC_STABLE CLAMP_STABLE Address R/W Description Reset Value 0xE010_8000 R/W Crystal oscillator control register 0x0000_0003 0xE010_8004 ~ 0xE010_9FFC Reserved 0x0000_0000 0xE010_A000 R Reset status register 0x0000_0001 0xE010_A004 ~ R/W Reserved 0xE010_BFFC 0x0000_0000 0xE010_C000 R/W Configure power manager 0x0000_0000 0xE010_C004 R/W Configure EINT(external interrupt) mask 0x0000_0000 0xE010_C008 R/W Configure wakeup source mask 0x0000_0000 0xE010_C00C R/W Secondary entering method to power down mode 0x0000_0000 0xE010_C010 R/W Configure power manager at NORMAL 0xFFFF_FFBF mode 0xE010_C014 ~ 0xE010_C01C Reserved 0x0000_0000 0xE010_C020 R/W Configure power manager at IDLE mode 0x6000_0000 0xE010_C024 ~ 0xE010_C02C Reserved 0x0000_0000 0xE010_C030 R/W Configure power manager at STOP mode 0x9600_0000 0xE010_C034 R/W Configure memory power at STOP mode 0x0000_00FF 0xE010_C038 ~ 0xE010_C03C Reserved 0x0000_0000 0xE010_C040 R/W Configure power manager at SLEEP mode 0x0000_0000 0xE010_C044 ~ 0xE010_C0FC Reserved 0x0000_0000 0xE010_C100 R/W Oscillator frequency scale counter 0x0000_000F 0xE010_C104 R/W Oscillator pad stable counter 0x0000_FFFF 0xE010_C108 R/W Power stable counter 0x0000_FFFF 0xE010_C10C Reserved 0x0000_0000 0xE010_C110 R/W MTC stable counter 0xFFFF_FFFF 0xE010_C114 R/W Cortex-A8 CLAMP stable counter 0x03FF_03FF 4-38 S5PV210_UM 4 3BPOWER MANAGEMENT Register Address R/W Description Reserved 0xE010_C118 ~ 0xE010_C1FC Reserved WAKEUP_STAT 0xE010_C200 R/W Wakeup status registers BLK_PWR_STAT 0xE010_C204 R Block power status register Reserved 0xE010_C208 ~ 0xE010_DFFC Reserved OTHERS 0xE010_E000 R/W Others control register Reserved 0xE010_E00C ~ 0xE010_E0FC R/W Reserved OM_STAT 0xE010_E100 R OM status register Reserved 0xE010_E104 ~ 0xE010_E7FC Reserved Reserved 0xE010_E800 R/W Reserved HDMI_CONTROL 0xE010_E804 R/W HDMI control register Reserved 0xE010_E808 Reserved USB_PHY_CONTROL 0xE010_E80C R/W USB PHY control register DAC_CONTROL 0xE010_E810 R/W DAC control register MIPI_DPHY_CONTROL 0xE010_E814 R/W MIPI DPHY control register ADC_CONTROL 0xE010_E818 R/W TS-ADC control register PS_HOLD_CONTROL 0xE010_E81C R/W PS_HOLD control register Reserved 0xE010_E81C ~ 0xE010_EFFC Reserved INFORM0 0xE010_F000 R/W Information register0 INFORM1 0xE010_F004 R/W Information register1 INFORM2 0xE010_F008 R/W Information register2 INFORM3 0xE010_F00C R/W Information register3 INFORM4 0xE010_F010 R/W Information register4 INFORM5 0xE010_F014 R/W Information register5 INFORM6 0xE010_F018 R/W Information register6 Reserved 0xE010_F020 ~ 0xE010_FFFC Reserved Reset Value 0x0000_0000 0x0000_0000 0x0000_00BF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0001 0x0096_0000 0x0000_0000 0x0000_0000 0x0000_0001 0x0000_0000 0x0000_0000 0x0000_5200 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 PMU SFRs consists of four parts. The first part, OSC_CON, controls the operation of external oscillators. The second part, RST_STAT, shows the reset status. Before entering into low power mode, S/W must set appropriate values for the third part. The final part has system control registers and user specific information registers. 4-39 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.2 CLOCK CONTROL REGISTER Clock control register enables and disables all oscillators for S5PV210. OSC_CON register control all oscillators for S5PV210. Each oscillator can be controlled independently. When oscillator pad is disabled, oscillation stops and no clock is generated further. 4.10.2.1 Clock Control Register (OSC_CON, R/W, Address = 0xE010_8000) OSC_CON Reserved OSCUSB_EN OSC_EN Bit [31:2] [1] [0] Description Reserved Control X-tal oscillator pad for USB (0: disable, 1: enable) Control X-tal oscillator pad for main oscillator (0: disable, 1: enable) Initial State 0x0000_0000 1 1 4-40 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.3 RESET CONTROL REGISTER 4.10.3.1 Reset Control Register (RST_STAT, R/W, Address = 0xE010_A000) RST_STAT Reserved DIDLE_WAKEUP DSTOP_WAKEUP Reserved SLEEP_WAKEUP Reserved SWRESET nWDTRESET nWRESET nRESET Bit [31:20] [19] [18] [17] [16] [15:4] [3] [2] [1] [0] Description Reserved ARM reset from DEEP-IDLE ARM reset from DEEP-STOP Reserved Reset by SLEEP mode wake-up Reserved Software reset by SWRESET Watch dog timer reset by WDTRST Warm reset by XnWRESET External reset by XnRESET Initial State 0x000 0 0 0 0 0x000 0 0 0 1 4-41 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4 POWER MANAGEMENT REGISTER 4.10.4.1 Power Management Register (PWR_CFG, R/W, Address = 0xE010_C000) PWR_CFG Reserved CFG_STANDBYWFI Reserved Bit Description [31:10] Reserved [9:8] Configure Cortex-A8 STANDBYWFI Determines what action is taken when the STANDBYWFI signal is activated by the Cortex-A8 00 = Ignore 01 = Enter IDLE mode 10 = Enter STOP mode 11 = Enter SLEEP mode [7:0] Reserved Initial State 0x00_0000 0x0 0x00 4.10.4.2 Power Management Register (EINT_WAKEUP_MASK, R/W, Address = 0xE010_C004) EINT_WAKEUP_MASK EINT_WAKEUP_MASK Bit [31:0] Description External interrupt wake-up mask EINT[31:0] . The field affects on NORMAL mode. Therefore, this field must clear when EINT is used as a normal external interrupt source. 0 = Use as a wake-up source 1 = Disable Initial State 0x0000_0000 4-42 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.3 Power Management Register (WAKEUP_MASK, R/W, Address = 0xE010_C008) WAKEUP_MASK Reserved CEC ST I2S MMC3 MMC2 MMC1 MMC0 Reserved Reserved Reserved KEY TS1 TS0 RTC_TICK RTC_ALARM Reserved Bit [31:16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Wake-up mask for HDMI-CEC (0: pass, 1: mask) Wake-up mask for system timer (0: pass, 1: mask) Wake-up mask for I2S within Audio sub-system (0: pass, 1: mask) Wake-up mask for MMC3 (0: pass, 1: mask) Wake-up mask for MMC2 (0: pass, 1: mask) Wake-up mask for MMC1 (0: pass, 1: mask) Wake-up mask for MMC0 (0: pass, 1: mask) Reserved Reserved Reserved Wake-up mask for KEY I/F (0: pass, 1: mask) Wake-up mask for TSADC1 (0: pass, 1: mask) Wake-up mask for TSADC0 (0: pass, 1: mask) Wake-up mask for RTC-TICK (0: pass, 1: mask) Wake-up mask for RTC-Alarm (0: pass, 1: mask) Reserved Initial State 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.10.4.4 Power Mode Register (PWR_MODE, R/W, Address = 0xE010_C00C) PWR_MODE Reserved SLEEP Reserved Bit [31:3] [2] [1:0] Description Reserved Go to SLEEP mode when this field is set. (automatically clear). Reserved Initial State 0x0000 0 0 NOTE: Before setting this register, you should set CFG_STANBYWFI[9:8] bits of PWR_CFG register to '00:ignore'. 4-43 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.5 Power Management Register (NORMAL_CFG, R/W, Address = 0xE010_C010) NORMAL_CFG Reserved IROM Reserved AUDIO Reserved CAM TV LCD G3D MFC Reserved Bit [31:21] [20] [19:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Power gating control for I-ROM (0: LP mode (OFF), 1: Active mode (ON)) Reserved Power gating control for Audio sub-block (0: LP mode (OFF), 1: Active mode (ON)) Reserved Power gating control for X-block (0: LP mode (OFF), 1: Active mode (ON)) Power gating control for T-block (0: LP mode (OFF), 1: Active mode (ON)) Power gating control for L-block (0: LP mode (OFF), 1: Active mode (ON)) Power gating control for G3D block (0: LP mode (OFF), 1: Active mode (ON)) Power gating control for F-block (0: LP mode (OFF), 1: Active mode (ON)) Reserved Initial State 0x7FF 1 0xFFF 1 1 1 1 1 1 1 1 Warning: Don't access SFR of modules whose block power is gated. Warning: When block power is turned on, be sure to keep the clock running for the corresponding modules. 4-44 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.6 Power Management Register (IDLE_CFG, R/W, Address = 0xE010_C020) IDLE_CFG TOP_LOGIC TOP_MEMORY ARM_L2CACHE Reserved CFG_DIDLE Bit [31:30] [29:28] [27:26] [25:1] [0] Description Configure TOP logic state 01 = Retention 10 = ON Other: Reserved Configure TOP memory state 01 = Retention 10 = ON Other: Reserved Configure ARM L2 cache state in DEEP-IDLE mode 00 = OFF 01 = Retention Other: Reserved Reserved Configure DEEP-IDLE setting for Cortex-A8 core 0 = No DEEP (Cortex-A8 core power on) 1 = DEEP (Cortex-A8 core power off) Initial State 0x1 0x1 0x0 0x000_0000 0 4-45 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.7 Power Management Register (STOP_CFG, R/W, Address = 0xE010_C030) STOP_CFG TOP_LOGIC TOP_MEMORY ARM_L2CACHE ARM_LOGIC Reserved OSCUSB_EN OSC_EN Bit Description [31:30] Configure TOP logic state 01 = Retention 10 = ON Other: Reserved. Writing reserved values to registers can lead to unexpected behavior. When ARM_LOGIC is set to 2'b10 (STOP mode), this field should be 2'b10. [29:28] Configure TOP memory state (DO NOT CHANGE) 01 = OFF/ Retention (According to STOP_MFM_CFG) Other: Reserved [27:26] Configure ARM L2 cache state in STOP mode. When ARM_LOGIC is ON, L2CACHE is always ON regardless of this field setting. 00 = OFF 01 = Retention Other: Reserved [25:24] Configure ARM logic state in STOP/D-STOP mode 00 = OFF (D-STOP mode) 10 = ON (STOP mode) Other: Reserved [23:2] Reserved [1] Control USB X-tal Oscillator pad in STOP mode (0: disable, 1: enable) [0] Control X-tal Oscillator pad in STOP mode (0: disable, 1: enable) Initial State 0x2 0x1 0x1 0x2 0x00_0000 0 0 4-46 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.8 Power Management Register (STOP_MEM_CFG, R/W, Address = 0xE010_C034) STOP_MEM_CFG Reserved ONENAND MODEMIF Reserved USBOTG HSMMC CSSYS SECSS IRAM Reserved Bit [31:9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Memory retention control for ONENAND I/F (0: OFF, 1: Retention) Memory retention control for MODEM I/F (0: OFF, 1: Retention) Reserved Memory retention control for USB-OTG (0: OFF, 1: Retention) Memory retention control for HSMMC (0: OFF, 1: Retention) Memory retention control for CoreSight (0: OFF, 1: Retention) Memory retention control for security sub-system (0: OFF, 1: Retention) Memory retention control for internal RAM This field should be 0x1. Reserved Initial State 0x00_0000 1 1 1 1 1 1 1 0x1 0x0 4-47 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.9 Power Management Register (SLEEP_CFG, R/W, Address = 0xE010_C040) SLEEP_CFG Reserved OSCUSB_EN OSC_EN Bit [31:2] [1] [0] Description Reserved Control USB X-tal Oscillator pad in SLEEP mode (0: disable, 1: enable) Control X-tal oscillator pad in SLEEP mode (0: Disable, 1: Enable) Initial State 0x0000_0000 0 0 4-48 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.10 Power Management Register (OSC_FREQ, R/W, Address = 0xE010_C100) OSC_FREQ Reserved OSC_FREQ_VALUE Bit [31:4] [3:0] Description Reserved Oscillator frequency scale counter ( OSC_FREQ_VALUE / oscillator_frequency > 200ns) Initial State 0x000_0000 0xF 4.10.4.11 Power Management Register (OSC_STABLE, R/W, Address = 0xE010_C104) OSC_STABLE Reserved OSC_CNT_VALUE Bit Description [31:20] Reserved [19:0] 20-bit oscillator stable counter value. It sets required period of time for oscillator to be stabilized. Whenever oscillator is turned on, corresponding counter increments from zero until it gets 16 times as big as this field value. The reference clock for the counter is external oscillator clock input. Initial State 0x000 0x0_FFFF 4.10.4.12 Power Management Register (PWR_STABLE, R/W, Address = 0xE010_C108) PWR_STABLE Reserved PWR_CNT_VALUE Bit [31:20] [19:0] Description Reserved 20-bit power stable counter value. It sets required period of time for external power regulator to be stabilized. Whenever external power regulator is turned on, corresponding counter increments from zero until it gets 16 times as big as this field value. The reference clock for the counter is external oscillator clock input. Initial State 0x000 0x0_FFFF 4.10.4.13 Power Management Register (MTC_STABLE, R/W, Address = 0xE010_C110) MTC_STABLE AUDIO Reserved CAM TV LCD G3D MFC TOP Bit Description [31:28] Memory power stabilization counter for Audio sub-block [27:24] Reserved [23:20] Memory power stabilization counter for CAM-block [19:16] Memory power stabilization counter for TV-block [15:12] Memory power stabilization counter for LCD-block [11:8] Memory power stabilization counter for G3D block [7:4] Memory power stabilization counter for MFC-block [3:0] Memory power stabilization counter for TOP block Initial State 0xF 0x0 0xF 0xF 0xF 0xF 0xF 0xF 4-49 S5PV210_UM 4 3BPOWER MANAGEMENT MTC_STABLE counter indicates time required for power supplies to be stabilized when sub-block power is turned “ON”. Unless commented, use the default values. 4-50 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.14 Power Management Register (CLAMP_STABLE, R/W, Address = 0xE010_C114) CLAMP_STABLE Reserved CLAMP_OFF_VALUE Reserved CLAMP_ON_VALUE Bit [31:26] [25:16] [15:10] [9:0] Description Reserved Clamp OFF counter value Reserved Clamp ON counter value Initial State 0x00 0x3FF 0x00 0x3FF CLAMP_STABLE counter indicates time required for power supplies to be stabilized when Cortex processor power is turned “ON” or turned “OFF”. Unless commented, use the default values. 4.10.4.15 Power Management Register (WAKEUP_STAT, Address = R/W, 0xE010_C200) WAKEUP_STAT Reserved CEC ST I2S MMC3 MMC2 MMC1 MMC0 Reserved Reserved Reserved KEY TS0 TS1 RTC_TICK RTC_ALARM EINT Bit [31:16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Wake-up by HDMI-CEC. This is cleared by writing 1. Wake-up by system timer. This is cleared by writing 1. Wake-up by I2S within Audio sub-system. This is cleared by writing 1. Wake-up by MMC3. This is cleared by writing 1. Wake-up by MMC2. This is cleared by writing 1. Wake-up by MMC1. This is cleared by writing 1. Wake-up by MMC2. This is cleared by writing 1. Reserved Reserved Reserved Wake-up by KEY I/F. This is cleared by writing 1. Wake-up by TSADC1. This is cleared by writing 1. Wake-up by TSADC0. This is cleared by writing 1. Wake-up by RTC-TICK. This is cleared by writing 1. Wake-up by RTC-Alarm. This is cleared by writing 1. Wake-up by EINT. This is cleared by writing 1. Initial State 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4-51 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.4.16 Power Management Register (BLK_PWR_STAT, R, 0xE010_C204) BLK_PWR_STAT Reserved AUDIO Reserved CAM TV LCD G3D MFC TOP Bit [31:8] [7] [6] [5] [4] [3] [2] [1] [0] Description Reserved Audio block power ready (0: OFF, 1: ON) Reserved X-block power ready (0: OFF, 1: ON) T-block power ready (0: OFF, 1: ON) L-block power ready (0: OFF, 1: ON) G3D block power ready (0: OFF, 1: ON) F-block power ready (0: OFF, 1: ON) TOP power ready (0: OFF, 1: ON) Initial State 0x0 1 0 1 1 1 1 1 1 4-52 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.5 MISC REGISTER 4.10.5.1 MISC Register (OTHERS, R/W, Address = 0xE010_E000) OTHERS RELEASE_RET_GPIO Bit Description [31] RELEASE_RET_GPIO is retention control signal to normal I/O pad. If you want to disable RELEASE_RET_GPIO, set to 1. After RELEASE_RET_GPIO becomes OFF, this bit will be cleared to 0. Usage1: Wakeup from IDLE, DEEP-IDLE, STOP, or DEEP-STOP with top-level logic ON -> No need to set this register field. Usage2: Wakeup from DEEP-IDLE, STOP, or DEEPSTOP with top-level logic OFF. -> Set HIGH on this register field to that corresponding PAD starts to work. Usage3: Wakeup from SLEEP. -> First restore GPIO configuration options to those values before entering SLEEP mode. And then set HIGH on this register field to that corresponding PAD starts to work. 0 = Auto clear 1 = RELEASE_RET_GPIO Initial State 0 For more information on list of PADs belonging to normal I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. RELEASE_RET_CF_IO [30] RELEASE_RET_CF_IO_IO is retention control signal 0 to CF I/O pad. If you want to disable RELEASE_RET_CF_IO_IO, set to 1. After RELEASE_RET_CF_IO_IO becomes OFF, this bit will be cleared to 0. Usage1: Wakeup from IDLE, DEEP-IDLE, STOP, or DEEP-STOP with top-level logic ON -> No need to set this register field. Usage2: Wakeup from DEEP-IDLE, STOP, or DEEPSTOP with top-level logic OFF. -> Set HIGH on this register field to that corresponding PAD starts to work. Usage3: Wakeup from SLEEP. -> First restore GPIO configuration options to those values before entering SLEEP mode. And then set HIGH on this register field to that corresponding PAD starts to work. 0 = Auto clear 1 = RELEASE_RET_CF_IO_IO 4-53 S5PV210_UM 4 3BPOWER MANAGEMENT OTHERS Bit Description Initial State For more information on list of PADs belonging to MMC I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. RELEASE_RET_MMC_IO [29] RELEASE_RET_MMC_IO is retention control signal to 0 MMC I/O pad. If you want to disable RELEASE_RET_MMC_IO, set to 1. After RELEASE_RET_MMC_IO becomes OFF, this bit will be cleared to 0. Usage1: Wakeup from IDLE, DEEP-IDLE, STOP, or DEEP-STOP with top-level logic ON -> No need to set this register field. Usage2: Wakeup from DEEP-IDLE, STOP, or DEEPSTOP with top-level logic OFF. -> Set HIGH on this register field to that corresponding PAD starts to work. Usage3: Wakeup from SLEEP. -> First restore GPIO configuration options to those values before entering SLEEP mode. And then set HIGH on this register field to that corresponding PAD starts to work. 0 = Auto clear 1 = RELEASE_RET_MMC_IO For more information on list of PADs belonging to MMC I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. RELEASE_RET_UART_IO [28] RELEASE_RET_UART_IO is retention control signal 0 to UART I/O pad. If you want to disable RELEASE_RET_UART_IO, set to 1. After RELEASE_RET_UART_IO becomes OFF, this bit will be cleared to 0. Usage1: Wakeup from IDLE, DEEP-IDLE, STOP, or DEEP-STOP with top-level logic ON -> No need to set this register field. Usage2: Wakeup from DEEP-IDLE, STOP, or DEEPSTOP with top-level logic OFF. -> Set HIGH on this register field to that corresponding PAD starts to work. Usage3: Wakeup from SLEEP. -> First restore GPIO configuration options to those values before entering SLEEP mode. And then set HIGH on this register field to that corresponding PAD starts to work. 0 = Auto clear 4-54 S5PV210_UM 4 3BPOWER MANAGEMENT OTHERS Reserved ARM_PRESETn_TYPE Reserved CLKOUT Reserved CLEAR_DBGACK SYSCON_INT_DISABLE Bit Description 1 = RELEASE_RET_UART_IO For more information on list of PADs belonging to UART I/O pad, refer to Section 4.2 PIN SUMMARY of GPIO manual. [27:18] Reserved [17] ARM_PRESETn type selection 0 = Asserted when software reset is generated. 1 = Not asserted when software reset is generated. [16:10] Reserved [9:8] Control the XCLKOUT signal output. This bit is prior to CLK_OUT register value. When this bit is ‘10’ or ‘11’, XCLKOUT output selected clock is not only normal mode but also Top block off status and sleep mode. 00 = Clock out signal from SYSCON (by CLK_OUT SFR of CMU) 01 = Reserved 10 = XXTI (Main X-tal input) 11 = XUSBXTI (USB X-tal input) [7:2] Reserved [1] Clear DBGACK signal when this field has value 1. Cortex-A8 asserts DBGACK signal to indicate the system has entered DEBUG state. If DBGACK is asserted, this state is stored in PMU until software clears it using this field. [0] Disables new interrupt to reach processor core. Active HIGH. Setting this field to HIGH is a mandatory step when entering low-power mode. This field is automatically cleared when low-power mode entering sequence is completed. Initial State 0x000 0 0x00 0x0 0x00 0 0 4.10.5.2 MISC Register (OM_STAT, R, Address = 0xE010_E100) OM_STAT Reserved OM Bit [31:6] [5:0] Description Reserved Operation mode value Initial State 0x000_0000 0x00 4-55 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.5.3 MISC Register (HDMI_CONTROL, R/W, Address = 0xE010_E804) HDMI_CONTROL Reserved DIV_RATIO Reserved ENABLE Bit Description [31:26] Reserved [25:16] Clock divider ratio for HDMI [15:1] Reserved [0] HDMI PHY enable (0: disable, 1: enable) Initial State 0x00 0x96 0x0000 0 4.10.5.4 MISC Register (USB_PHY_CONTROL, R/W, Address = 0xE010_E80C) USB_PHY_CONTROL Reserved ENABLE1 ENABLE0 Bit [31:2] [1] [0] Description Reserved USB PHY1 Enable selection (0: disable, 1: enable) USB PHY0 Enable selection (0: disable, 1: enable) 4.10.5.5 MISC Register (DAC_CONTROL, R/W, Address = 0xE010_E810) DAC_CONTROL Reserved ENABLE Bit [31:1] [0] Description Reserved DAC IP enable selection. This bit must be set to 1 at the system initialization step before data access from/to DAC begins. Caution: If DAC is not used in your system, do not touch this field. (0: disable, 1: enable) Initial State 0x0000_0000 0 0 Initial State 0x0000_0000 0 4.10.5.6 MISC Register (MIPI_DPHY_CONTROL, R/W, Address = 0xE010_E814) MIPI_DPHY_CONTROL Reserved M_RESETN S_RESETN ENABLE Bit [31:1] [2] [1] [0] Description Reserved Isolate/Connect MIPI_PHY Master Logic from/to Link 0 : Isolate MIPI D-PHY Master Logic from DSI Link 1: Connect MIPI D-PHY Master Logic to DSI Link Isolate/Connect MIPI_PHY Slave Logic from/to Link 0 : Isolate MIPI D-PHY Slave Logic from CSI Link 1: Connect MIPI D-PHY Slave Logic to CSI Link MIPI_DPHY enable selection. This bit must be set to 1 at the system initialization step before data access from/to MIPI_DPHY begins. Caution: If MIPI_DPHY is not used in your system, do not touch this bit. (0: disable, 1: enable) Initial State 0x0000_0000 0 0 0 4-56 S5PV210_UM 4 3BPOWER MANAGEMENT 4.10.5.7 MISC Register (ADC_CONTROL, R/W, Address = 0xE010_E818) ADC_CONTROL Reserved DISABLE Bit [31:1] [0] Description Reserved TS-ADC enable control (0: disable, 1: enable) Initial State 0x0000_0000 1 4.10.5.8 MISC Register (PS_HOLD_CONTROL, R/W, Address = 0xE010_E81C) PS_HOLD_CONTROL Reserved Reserved DIR DATA Reserved PS_HOLD_OUT_EN Bit Description [31:12] Reserved [11:10] Reserved [9] Direction (0: input, 1: output) [8] Driving value (0:low, 1:high) [7:1] Reserved [0] XEINT[0] pad is controlled by this register values and values of control registers for XEINT[0] of GPIO chapter is ignored when this field is ‘1’. (0: disable, 1: enable) Initial State 0x00005 0 1 0 0x00 0 PS_HOLD (muxed with XEINT[0]) pin value is kept up in any power mode. This register is in alive region and reset by XnRESET or power off only. 4.10.5.9 MISC Register • INFORM0, R/W, 0xE010_F000 • INFORM1, R/W, 0xE010_F004 • INFORM2, R/W, 0xE010_F008 • INFORM3, R/W, 0xE010_F00C • INFORM4, R/W, 0xE010_F010 • INFORM5, R/W, 0xE010_F014 • INFORM6, R/W, 0xE010_F018 INFORMn INFORM Bit [31:0] Description User defined information register. INFORM0~3 registers are cleared by asserting XnRESET pin. INFORM4~6 registers are cleared by power off only. Initial State 0x0000_0000 4-57 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5 INTELLIGENT ENERGY MANAGEMENT 5.1 OVERVIEW OF INTELLIGENT ENERGY MANAGEMENT The Intelligent Energy Management (IEM) solution is designed primarily for battery-powered equipment, where the major requirement is to have long battery life. The IEM solution is ideal for portable applications, for example, smartphones, feature phones, Personal Digital Assistants (PDA), hand held games consoles and portable media players. Figure 5-1 shows a high-level block diagram of a complete IEM solution. System - on - Chip (SoC) Hardware Performance Monitor ARM processor HPM clock ARM Core clock Clock Management Unit Applications OS Performance Power Management Unit Advanced Power Controller Vdd Communication Interface Power Supply Unit Off - chip Intelligent Energy Manager Software Intelligent Energy Controller Figure 5-1 Intelligent Energy Manager Solution An IEM system consists of the following components: • An operating system (OS) modified to co-operate with the IEM software (An IEM-enabled OS). • The IEM software, ported to the platform that you are using. • Performance scaling hardware and appropriate drivers for that hardware. 5-1 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT The above listed components, which are part of the IEM system, co-operate with each other to optimize power consumption, without compromising on performance or responsiveness. Work flow of IEM system: • When the IEM software starts, software registers some kernel hooks with the OS. • The OS uses these kernel hooks to invoke the IEM software. It does so whenever a system event occurs that might influence the optimum performance level. • The IEM software records information about the events that occur, and the related tasks. • The policies that are a part of the IEM software analyze this information to determine the optimum performance level. • Whenever the optimum performance level changes, the IEM software uses the performance scaling hardware to set the new level. 5.1.1 KEY FEATURES OF INTELLIGENT ENERGY MANAGEMENT The key features of IEM include: • Up to eight energy level control • Up to eight frequency level control • Up to eight voltage level control • Supports low power mode 5-2 S5PV210_UM 5.1.2 BLOCK DIAGRAM 5 4BINTELLIGENT ENERGY MANAGEMENT AMBA APB Bus Maximum performance request Acknowledge Configuration Information Target Frequency Index Current Frequency Index Clock Management Unit Intelligent Energy Controller Target Frequency Index Current Frequency Index Target Voltage Index Current Voltage Index Power Request Power Management Unit Target Voltage Index Current Voltage Index Advanced Power Controller Power request ARM Core clock HPM clock Hardware Performance Monitor Interrupts Interrupts To and from the PSU Figure 5-2 IEM Block Diagram 5-3 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2 FUNCTIONAL DESCRIPTION OF INTELLIGENT ENERGY MANAGEMENT To support IEM, S5PV210 includes special IPs, namely: • Intelligent Energy Controller • Power Management Unit supporting IEM • Clock Management Unit (CMU) supporting Dynamic Clock Generation − Clock Management Unit in System Controller acts as Dynamic Clock Generator • Advanced Power Controller (APC1) supporting Dynamic Voltage Control − APC1 acts as Dynamic Voltage Controller • Power Supply Unit supporting Dynamic Voltage Scaling − Power Supply Unit is the only off-chip component. • Hardware Performance Monitor (HPM) − This is optional and required only for a closed loop system Figure 5-2 shows the on-chip IEM components required for a complete solution of IEM and how each component are connected. 5.2.1 IEM SYSTEM COMPONENTS 5.2.1.1 Intelligent Energy Controller The Intelligent Energy Controller (IEC) from ARM is designed to reuse in a wide variety of AMBA based designs and has a standard APB slave interface to program the registers. The IEC provides an Applications Programming Interface (API) for the IEM software. The IEC connects via defined interfaces to SoC-specific components such as the APC1. The IEC uses prediction performance level requests from the IEM software. The performance setting is communicated to the IEC in order to control the System-on-Chip specific and product platform scaling hardware and to achieve desired system performance. Battery life is extended by lowering the operating frequency and voltage of SoC components, such as the processor, and consequently reducing energy consumption. The IEC provides an abstracted view of the SoC-specific performance scaling hardware. It is responsible for translating the performance prediction made by the IEM software (0-100% of maximum performance) to an appropriate performance point at which the system runs and then controlling the scaling hardware to achieve operation at that target point. To achieve this, IEC sends a target performance request to the CMU and APC1. The IEC also measures the work done in the system to ensure that the software deadlines are not missed. Additionally, the IEC supports a maximum performance hardware request feature. The IEC is designed to map to an implementation-defined set of index levels. You must configure the IEC to define the CMU frequencies and APC1 voltage levels that can be selected. These frequencies and voltages depend on the capabilities of the dynamic or adaptive power supply technology to support multiple operating performance points. The IEC interfaces to the CMU and APC1 blocks via PMU through a thermometer encoded interface protocol, which indicates to the IEC the current performance level. This protocol is specified to support interfacing across asynchronous clock domains between high-speed PLL and clock-generator and low-speed voltage scaling hardware. The IEC provides an encoded performance index to S5PV210’s CMU and APC1 blocks. 5-4 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT The IEC also includes a Design for Test (DFT) interface. This enables easier control over the scaling hardware during production testing of the SoC device. The IEC is an AMBA compliant, SoC peripheral that is developed, tested, and licensed by ARM Limited. The IEC features are as follows: • AMBA APB compliant. • Defined interfaces between the IEC and CMU/APC1 via PMU that is necessary for a complete energy management solution. • An abstract interface to the underlying system-specific clock multiplexing and dynamic voltage or power control. This is through mapping to an implementation-defined set of index levels: − That correspond with the CMU frequencies that can be selected, and − That enables the voltage steps for the corresponding dynamic or adaptive power supply technology and consequently supports multiple operating performance points. • An encoded interface protocol that provides a performance index to S5PV210x’s CMU and APC1 blocks. • Dynamic Voltage Scaling (DVS) emulation support enables a run fast then idle mode of operation. • An API interface for efficient control and monitoring: − Implementation-independent fractional performance setting interface to support performance prediction algorithms without hard-coded frequencies. − Implementation-independent interrogation of performance-level quantization mapping levels to enable performance prediction software to adapt to the processor clock frequencies provided. − SoC-specific configuration interrogation, consisting of processor and IEC clock frequencies in kHz, and performance level mapping provided by the S5PV210x’s CMU. • Supports maximum performance signaling for real time subsystems that enables: − The maximum performance level to be requested regardless of the current programmed target performance level. − You to decide the events that activate this mode. • Monitoring for IEM-specific algorithms, through a multi-channel interface designed to support automatic accumulation of system metrics. • Supports synchronization handshaking with synchronous and asynchronous bridges to control entry and exit from maximum performance mode. • Test registers for use in block and system level integration testing. • System level integration testing using externally applied integration vectors. • Debug mode to test clock generation with maximum voltage. • ID support registers to port software driver compliance. 5-5 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.1.2 DFT interface to control the target index outputs during SoC DFT. Advanced Power Controller S5PV210 uses Advanced Power Controller (APC1) from National Semiconductor for Dynamic Voltage Control. The APC1 is an advanced power controller designed for reuse in the AMBA-based designs with a standard APB slave interface to program registers. Based on the requested performance requirements from the CMU, the APC1 dynamically controls the EMU to provide sufficient voltage level to the SoC in order to achieve the performance level. This is the minimum voltage for the best power saving. APC1 uses a thermometer-encoded interface to receive target performance level requirements, and to send out current performance level updates indicating voltage readiness. Together with the HPM, the APC1 tracks the system timing in real time, and sends voltage commands to the EMU to request the adjustment of voltage level. The flowchart in Figure 5-3 shows how the adaptive voltage control is processed to find optimum voltage level. Figure 5-3 PowerWise Performance Tracking and Voltage Adjustment If you require the open-loop Dynamic Voltage Scaling (DVS) voltage control you can use a built-in voltage table to request the EMU voltage level corresponding to the target performance level. The APC1 is an AMBA APB-based SoC peripheral. The features are as follows: • AMBA APB interface to program the registers • PowerWise Interface™ (PWI) Rev 1.0 compliant master to control an external PWI-compliant power supply • Supports the closed-loop AVS voltage control in conjunction with the HPM • Voltage table to support the open-loop DVS 5-6 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT • Supports thermometer-encoded interface for a target performance level request and a current performance level update • Parameterized design supports up to eight performance levels • Supports sleep mode (retention level) power-down • Revision identification register to port software driver compliance • DFT-ready for SCAN-based ATPG. The APC1 receives the required target performance request from the IEC via PMU. This performance request is then translated to a voltage level that is communicated to the PSU through an interface such as the. The ARM and National Semiconductor jointly developed PWI to provide a high-speed and low-power control interface between an IEM-enabled SoC and an external power supply unit. For an open loop system, the APC1 can either: • Wait a programmed time that is dependent on the response time of the PSU, before signaling to the CMU that the target performance can be achieved • Interrogate the PSU through the PWI for a VDD_OK signal indication. If the PSU provides intermediate stable voltage level indication, then the APC1 can also determine this via the PWI. 5.2.1.3 Hardware Performance Monitor The Hardware Performance Monitor (HPM) is designed for reuse and easy implementation. Although it is a separate entity in physical partition, the HPM is an integral part of the APC1 for an AVS power management system. The HPM is not a memory mapped device. An HPM is required for closed loop control, but not for an open loop control system. The HPM tracks the system delay. The output of the HPM is a function of voltage level and the HPM clock. As shown in Figure 5-3, the HPM is embedded in the ARM Core voltage domain that is AVS controlled. It receives the clock from the CMU, and outputs are connected to the APC1. It translates voltage level into system delay information. APC1 uses the system delay information to determine the optimum voltage level for the target performance requirement. To be short, the CMU supplies the target frequency required by the IEM software for that voltage domain, and the HPM informs the APC1 when this target frequency is detected. The HPM design is structurally coded in the synthesizable RTL to facilitate ease of place and route. This is required to optimize the accuracy of the system delay tracking. The HPM features are as follows: • Configurable for a different target frequency • Low power consumption overhead • Low area overhead • DFT-ready for SCAN based ATPG 5-7 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.1.4 Power Management Unit The Power Management Unit (PMU) in S5PV210X supports IEM features. The PMU provides configuration information to IEC, for example: • Fractional index map, indicating the fractional levels supported • Performance map, providing the mapping of the performance levels onto the clock frequencies supported by the CMU • Maximum processor performance. 5.2.1.5 Clock Management Unit In S5PV210X, Clock Management Unit (CMU) in System Controller supports Dynamic Clock Generation. The CMU receives target performance requests from the IEC, via Power Management Unit (PMU). It generates the necessary clocks for the CPU, for example: • Processor clock • Peripheral clocks • AMBA clock. Additionally, for a more efficient design, the CMU must be capable to generate the different performance levels as indicated by the IEC. The CMU can also be a memory mapped AMBA peripheral and can contain both control and status registers. The design of the CMU must meet the requirements set by the IEC and the Advanced Power Controller (APC1). These constraints are necessary to ensure optimum and correct performance of the Hardware Performance Monitor (HPM). 5.2.1.6 Power Supply Unit Supporting Dynamic Voltage Scaling The Power Supply Unit (PSU) is the only off-chip component. The PSU provides the requested voltage to the SoC. It interfaces to the DVC through an interface such as the PWI. It ensures that the voltage targets specified by the DVC are provided to the SoC. 5-8 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.2 IEM SYSTEM OPERATION Loading and starting the software At an appropriate stage of system boot-up, the OS loads and initializes the modules that contain the IEM software: • On most platforms, the module loader automatically runs the initialization code for a module (if any) • Else, the OS (or a driver) must call the initialization codlmee itself. This initialization code performs most of the set up for the IEM software. For example: • The code in the IEM HAL sets up and configures the performance scaling hardware • The code in the control component loads the Comms driver that it uses to communicate with the IEM kernel. The OS then configures the IEM kernel by issuing commands to the control component. The control component encodes these commands as messages, and uses the Comms driver to send them to the IEM kernel. These control messages: • Start the policies, so that they are ready to use • Optionally: − Configure the IEM activities that are traced − Enables tracing. Finally, the OS issues a command to start the IEM kernel. When the IEM kernel receives the corresponding control message, it: 1. Allocates memory for the event queue, and initializes it. 2. Allocates memory for the IEM blocks, and initializes them. 3. Registers the kernel hooks that the OS calls whenever a system event occurs. 5-9 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.2.1 Handling System Events When an event occurs that might influence the optimum performance level, the OS calls the appropriate kernel hook in the IEM kernel: • The New Task hook is called whenever a new task is created. This hook generates a New Task system event for the new task that has just been created. • The Exit hook is called whenever a task is about to exit. This hook generates a Task Exit system event for the exiting task. • The Task Switch hook is called whenever the OS switches from one task to another. This hook generates two system events: − A Task Schedule Out system event for the previous task that has just been switched out − A Task Schedule In system event for the next task that is being switched in. • The User Input hook is called whenever a task receives user input. This hook generates a User Input system event for the task that is receiving input. When a kernel hook generates an system event, it determines whether any event handlers recognize the system event. If so, it: • Creates a structure describing the system event • Ensures that there is an IEM block describing the corresponding task • Runs the fast event handlers to process the system event. The kernel hook then determines whether any standard event handlers recognize the system event. If so, the kernel hook adds the event to the event queue, for subsequent processing by the standard event handlers. The kernel hook finally ensures that, if there are any system events in the event queue, the standard event handlers run within a given period. 5-10 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.2.2 Running the Fast Event Handlers The fast event handlers are run from the kernel hooks whenever a system event occurs. For each policy, the IEM kernel determines whether its fast event handler recognizes the system event. If so, the IEM kernel runs the fast event handler, passing it pointers to the IEM kernel data structures that include: • The system event structure describing the event • The IEM block describing the task that triggered the system event. The fast event handler then processes the event. Typical uses of the fast event handler include: • Recognizing a task that requires an immediate change in performance level, and requesting that performance level. The fast event handler might recognize: − A specific task, such as a movie player − A type of task, such as real-time tasks, or tasks that are receiving user input. If necessary, the fast event handler can get further information about the task by making calls to the OS layer API. • Storing policy-specific information about the current state of the task or the system, for later processing by the standard event handler of the same policy. The fast event handler might get this information by making calls to the IEM HAL or OS layer APIs. It typically stores this information in arrays of memory that are allocated by the initialization function of the policy. When the fast event handlers have been run, the IEM kernel then combines any performance requests that the fast event handlers are making, and sets the resulting performance level using the IEM HAL. 5-11 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.2.2.3 Running the Standard Event Handlers The standard event handlers are run periodically by the IEM kernel. When the IEM kernel determines that it must run the standard event handlers, there are typically a number of outstanding system events in the event queue, that have not yet been processed by the standard event handlers. Starting with the oldest event, the IEM kernel processes each event in turn by enabling pre-emption, and then running the standard event handlers. The standard event handlers are run in a very similar way to the fast event handlers. For each policy, the IEM kernel determines whether its standard event handler recognizes the system event. If so, the IEM kernel runs the standard event handler, passing it pointers to the IEM kernel data structures that include: • The system event structure describing the event • The IEM block describing the task that triggered the system event. The standard event handler then processes the event, analyzing the data in the IEM kernel data structures and any data that was stored by the fast event handler to determine the optimum performance level. The analysis that the standard event handler performs is usually very different to that performed by the fast event handler of the same policy. This is because the standard event handler is working on historical data. Also, the standard event handler is pre-emptable, and so can spend longer analyzing the data without impacting system responsiveness. It can therefore use more complex algorithms, such as decaying weighted averages. When the final outstanding event in the queue is processed, the standard event handlers can request a performance level. The IEM kernel then combines any performance requests that the standard event handlers are making, and sets the resulting performance level using the IEM HAL. 5-12 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.3 IEM IMPLEMENTATION AND DRIVER SETTING 5.3.1 DEFINITION OF PERFORMANCE The maximum frequency of APLL is 2GHz. The expected frequency range of ARM Core is from 166MHz to 800MHz. AXI_MSYS bus, which is connected to ARM Core, works at 166MHz. In S5PV210X, CMU only uses clock divider to change performance. If you want to use PLL clock change, you should change PLL setting. With this specification, we should consider about number of the frequency levels as well as the resolution of each frequency level. There are divider values for ARM Core clock, AXI_MSYS bus AXI clock and HPM clock when PLL output is 1600MHz as shown in table below. Table 5-1 Example Divider Values for 1600MHz PLL Output PLL Output (MHz) 1600 ARM Core Clock Frequency (MHz) 800.0 533.3 400.0 320.0 266.7 228.6 200.0 177.8 160.0 HPM Clock Frequency (MHz) 100.0 66.7 50.0 40.0 33.3 28.6 25.0 22.2 20.0 AXI Bus Clock Frequency (MHz) 160.0 ARM Clock Ratio (fPLL/fARM) 2 3 4 5 6 7 8 9 10 HPM Clock Ratio (fARM/fHPM) 8 AXI Bus Clock Ratio (fPLL/fAXI) 10 Performance mapping (%) 100.0 66.7 50.0 40.0 33.3 28.6 25.0 22.2 20.0 There are divider values for ARM Core clock, AXI_MSYS bus AXI clock and HPM clock when PLL output is 833MHz as shown table below. PLL Output (MHz) 833 Table 5-2 Example Divider Values for 833MHz PLL Output ARM Core Clock Frequency (MHz) 833.0 416.5 277.7 208.3 166.6 HPM Clock Frequency (MHz) 104.1 52.1 34.7 26.0 20.8 AXI Bus Clock Frequency (MHz) 166.6 ARM Clock Ratio (fPLL/fARM) 2 3 4 5 6 HPM Clock Ratio (fARM/fHPM) 8 AXI Bus Clock Ratio (fPLL/fAXI) 5 Performance mapping (%) 100.0 50.0 33.3 25.0 20.0 If you want to add more performance level above 50%, you should put PLL change scheme to CMU. 5-13 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.3.2 HPM STRUCTURE AND CLOSED-LOOP BEHAVIOR When IEM works with closed-loop, HPM and APC1 work as shown in Figure 5-4 and Figure 5-5. closedloop_vdd[6:0] hpm_targetclk_c creset0 sample_en pre_delay_in delayline_end hpm_delay_code HPM 0_0110 RCC table APC_PL1_CALCODE APC_PL2_CALCODE APC_PL3_CALCODE APC_PL4_CALCODE APC_PL5_CALCODE APC_PL6_CALCODE APC_PL7_CALCODE APC_PL8_CALCODE A Minimum (A+B, 1_1111) B APC_PREOFFSET 0 1 integral_reg[20:0] ([20:14]=closedloop_vdd) tgained_slack[22:0] The faster, the higher integral = integral_reg + integral rst_filterq | ((integral > 22’h1F_C000) & (gained_slack > 0) & (integral > 0)) 21’h1F_C000 ((integral ≤ APC_MINVDD_LIMIT) & gained_slack < 0) | (integral < 0) integral_reg[20:14] = APC_MINVDD_LIMIT A A==0 filter_en integral[20:0] Sign B extender sd_saturation A A-B gained_slack[15:0] Shifter slack_reg [5:0] Sign extender ext_slack[15:0] A (A[5:2] == 4’hF) sd_low | (A[5:2] == 4’h0) loop_gain APC_SS_GAIN_EN & APC_GAIN_SEL vdd_stable APC_SAT_GAIN_EN & sd_saturation & step_upward APC_IGAIN3 APC_UP_GAIN_EN & step_upward APC_IGAIN2 APC_LOW_GAIN_EN & sd_low APC_IGAIN4 vdd_stable step_upward Default APC_IGAIN1 Figure 5-4 IEM Closed-Loop Voltage Generation Flow in HPM and APC1 5-14 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT apc_target_index[7:0] apc_target_index_prv clkdivcnt[5:0] clock_div || (apc_target_index != apc_target_index_prv) 6’h00 default clkdivcnt +1 clkdivcnt == APC_SLK_SMP clock_div APC_UNSHT_NOISE[5:4] 00 step_dir_int = 0 < precnt = step_upward = 0 {APC_VDDCHKD[7:0], cnt = Integral = 0 01 10 APC_VDDCHK[3:0] mresult = 0 11 > step_dir_int = 1 APC_VDDCHK[7:4]} noise_limit_int 5’h00 5’h04 5’h10 5’h1F precnt down to 0 clock_div cnt down to 0 Accumulate slack to integral except overflow is expected clock_div noise_limit_int Voltage meet condition (double check, then mresult = 1) = 1) Below reference, but less than noise_limit_int step_upward • Integral is positive (Voltage under-supplied) • Integral is less than or equal to noise_limit_int[4:0] 2) Above reference perf_lvl_zero & mresult = vdd_stable • Integral is negative (Voltage over-supplied) Undershoot condition • Absolute value of Integral is less than APC_OVSHT_LMT[7:0] 1) Positive slack (Voltage under-supplied) Low_VDD_timeout : Too much time taken to increase voltage 2) Slack is higher than APC_UNSHT_NOISE[3:0] step_upward = 1 when Integral is positive and step_int_dir == 1 3) Above occurs more than 10 times Figure 5-5 IEM Closed-Loop Control Flow in APC1 HPM Delay 5-15 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT Critical path delay of ARM Core in S5PV210X is about 1.70ns in the worst condition. Delay of NOR2X1 cell is about 0.04609ns. One delay tap has four NOR2X1 cells and each delay tap gives 0.184ns delay. Delay tap structure is as shown in Figure 5-6. Figure 5-6 HPM Delay Tap structure in S5PV210 HPM has a predelay module that includes 32 delay tap-like delay elements and a delayline module that includes 32 delay taps. To correlate with ARM core, 14-th tap should be selected with setting predelay_sel[2:0] of HPM 3’b000 when HPM clock ratio is equal to 1. 5-16 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.3.2.1 Calibration Code for Closed-loop In closed-loop mode, Calibration codes are used to control voltage level, while voltage values in open-loop mode. Calibration code stands for critical path delay of ARM core. In S5PV210X, 14-th tap output of HPM has the nearly same delay to the critical path of ARM core (when HPM clock ratio is equal to 1), which can be encoded to the delay code 5’hE. 5.3.3 INITIALIZATION SEQUENCE 1. Initialize the index map & all other IEM & APC mapping values. 2. If IEM will use ‘overdrive’ level, then programs ‘Max performance mapping index value’ in IECDPCCR register with proper values ( smaller than 3’b111) 3. Enables voltage scaling feature in the APC by setting ‘APC_VDD_UD’ bit in APC_CONTROL register as “1” 4. If IEM will use closed loop mode, then programs ‘APC_HPM_EN’ bit & ‘APC_LOOP_MODE’ bit in APC_CONTROL register as “1” 5. Start IEM HW by setting ‘iem_enable’ bit in IEM_CONTROL register in power management unit as “1” 6. Start IEM control by setting “iec_enable” bit in IECDPCCR register as “1” 7. Now, the system is under the IEM control. 5-17 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.4 I/O DESCRIPTION Signal IEM_SCLK IEM_SPWI I/O Bidirectional Bidirectional Description PWI clock PWI serial data Pad IEM_SCLK IEM_SPWI Type dedicated dedicated NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals. 5-18 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5 REGISTER DESCRIPTION 5.5.1 REGISTER MAP Register IEC IECDPCCR IECDVSEMSTR IECDPCTGTPERF IECDPCCRNTPERF Address 0xE080_0000 0xE080_0004 0xE080_0008 0xE080_000C IECIMSC IECRIS IECMIS IECICR IECCFGCPUFREQ IECDPMFREQ IECCFGDCGIDXMAP00 IECCFGDCGIDXMAP32 IECCFGDCGIDXMAP64 IECCFGDVCIDXMAP IECCFGDCGPERFMAP0 IECCFGDCGPERFMAP4 IECDPMCR IECDPM2RATE IECDPM3RATE IECDPMILO IECDPM1H1 IECDPM2LO IECDPM2HI IECDPM3LO IECDPM3HI IECITCR IECITIP1 0xE080_0010 0xE080_0014 0xE080_0018 0xE080_001C 0xE080_0020 0xE080_0024 0xE080_0040 0xE080_0044 0xE080_0048 0xE080_004C 0xE080_0060 0xE080_0064 0xE080_0100 0xE080_0108 0xE080_010C 0xE080_0180 0xE080_0184 0xE080_0188 0xE080_018C 0xE080_0190 0xE080_0194 0xE080_0F00 0xE080_0F10 IECITIP2 0xE080_0F14 IECITIP3 0xE080_0F18 IECITOP1 0xE080_0F20 R/W Description R/W DPC Control Register R/W DVS Emulation Slot Time Register W DPC Target Performance Register R DPC Current Performance Register R/W Interrupt Mask Set and Clear Register R Raw Interrupt Status Register R Masked Interrupt Status Register W Interrupt Clear Register R Configured CPU Frequency Register R DPM Frequency Register R Configuration Fractional Index Map0 R Configuration Fractional Index Map32 R Configuration Fractional Index Map64 R Configuration DVC Index Map Register R Configuration Performance Map 0 R Configuration Performance Map 4 R/W DPM Command Register R/W DPM Channel 2 Rate Register R/W DPM Channel 3 Rate Register R DPM Channel 1 Low Register R DPM Channel 1 High Register R DPM Channel 2 Low Register R DPM Channel 2 High Register R DPM Channel 3 Low Register R DPM Channel 3 High Register R/W Integration Test Control Register R/W Integration Test Input Read or Set Register 1 R/W Integration Test Input Read or Set Register 2 R/W Integration Test Input Read or Set Register 3 R/W Integration Test Output Read or Set Reset Value 0x000000E0 0x63 0x80 System Dependent 0x3 0x0 0x0 0x0 From PMU From PMU From PMU From PMU From PMU From PMU From PMU From PMU 0x000 0x80 0x80 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0 0x00 0x0 0x00 0x0 5-19 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT Register IECITOP2 IECITOP3 IECITCR IECPeriphID4 IECPeriphID5 IECPeriphID6 IECPeriphID7 IECPeriphID0 IECPeriphID1 IECPeriphID2 IECPeriphID3 IECID0 IECID1 IECID2 IECID3 APC APC_PWICMD APC_PWIDATAWR APC_PWIDATARD APC_CONTROL APC_STATUS APC_MINVDD_LIMIT APC_VDDCHK APC_VDDCHKD APC_PREDLYSEL APC_IMASK APC_ISTATUS APC_ICLEAR APC_UNSH_NOISE APC_WKUP_DLY APC_SLK_SMP APC_CLKDIV_PWICLK APC_OVSHT_LMT APC_CLP_CTRL Address 0xE080_0F24 0xE080_0F28 0xE080_0F00 0xE080_0FD0 0xE080_0FD4 0xE080_0FD8 0xE080_0FDC 0xE080_0FE0 0xE080_0FE4 0xE080_0FE8 0xE080_0FEC 0xE080_0FF0 0xE080_0FF4 0xE080_0FF8 0xE080_0FFC R/W Description Register 1 R/W Integration Test Output Read or Set Register 2 R/W Integration Test Output Read or Set Register 3 R/W Integration Test Control Register R Peripheral Identification Register 4 R Peripheral Identification Register 5 R Peripheral Identification Register 6 R Peripheral Identification Register 7 R Peripheral Identification Register 0 R Peripheral Identification Register 1 R Peripheral Identification Register 2 R Peripheral Identification Register 3 R IEC Identification Register 0 R IEC Identification Register 1 R IEC Identification Register 2 R IEC Identification Register 3 0xE070_0000 0xE070_0004 0xE070_0008 0xE070_0010 0xE070_0014 0xE070_0018 0xE070_001C 0xE070_0020 0xE070_0024 0xE070_0028 0xE070_002C 0xE070_0030 0xE070_0034 0xE070_0038 0xE070_003C 0xE070_0040 0xE070_0050 0xE070_0054 R/W PWI Command Register R/W PWI Write Data Register R PWI Read Data Register R/W APC Control Register R APC Status Register R/W Minimum Limit Register R/W VDD Check Register R/W VDD Delay Time Register R/W VDD Pre-delay Select Register R/W APC Interrupt Mask Register R APC Interrupt Status Register W APC Interrupt Clear Register R/W APC Undershoot Threshold and Noise Limit Register R/W Wakeup Delay Register R/W Slack Sample Count Register R/W PWI Clock Division Register R/W APC Overshoot Limit Register R/W APC Closed-loop Control Reset Value 0x00 0x00 0x0 0x03 0x08 Reserved Reserved 0x50 0x17 0x04 0x08 0x0D 0xF0 0x05 0xB1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 5-20 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT Register APC_SS_SRATE APC_IGAIN4 APC_IGAIN1 APC_IGAIN2 APC_IGAIN3 APC_ITSTCTRL APC_ITSTIP1 APC_ITSTIP2 APC_ITSTOP1 APC_ITSTOP2 APC_PL1_CALCODE APC_PL2_CALCODE APC_PL3_CALCODE APC_PL4_CALCODE APC_PL5_CALCODE APC_PL6_CALCODE APC_PL7_CALCODE APC_PL8_CALCODE APC_PL1_COREVDD APC_PL2_COREVDD APC_PL3_COREVDD APC_PL4_COREVDD APC_PL5_COREVDD APC_PL6_COREVDD APC_PL7_COREVDD APC_PL8_COREVDD APC_RET_VDD APC_ITSTOP3 APC_DBG_DLYCODE APC_REV Address 0xE070_0058 0xE070_005C 0xE070_0060 0xE070_0064 0xE070_0068 0xE070_006C 0xE070_0070 0xE070_0074 0xE070_0078 0xE070_007C 0xE070_0080 0xE070_0084 0xE070_0088 0xE070_008C 0xE070_0090 0xE070_0094 0xE070_0098 0xE070_009C 0xE070_00A0 0xE070_00A4 0xE070_00A8 0xE070_00AC 0xE070_00B0 0xE070_00B4 0xE070_00B8 0xE070_00BC 0xE070_00C0 0xE070_00C4 0xE070_00E0 0xE070_00FC R/W Description R/W APC Steady State Slew Rate Register R/W Integrator’s Gain 4 Register R/W Integrator’s Gain 1 Register R/W Integrator’s Gain 2 Register R/W Integrator’s Gain 3 Register R/W Integration Test Control Register R/W Integration Test Input Read or Set Register 1 R/W Integration Test Input Read or Set Register 2 R/W Integration Test Output Read or Set Register 1 R/W Integration Test Output Read or Set Register 2 R/W Calibration Code 1 Register R/W Calibration Code 2 Register R/W Calibration Code 3 Register R/W Calibration Code 4 Register R/W Calibration Code 5 Register R/W Calibration Code 6 Register R/W Calibration Code 7 Register R/W Calibration Code 8 Register R/W Open-loop VDD Core Register 1 R/W Open-loop VDD Core Register 2 R/W Open-loop VDD Core Register 3 R/W Open-loop VDD Core Register 4 R/W Open-loop VDD Core Register 5 R/W Open-loop VDD Core Register 6 R/W Open-loop VDD Core Register 7 R/W Open-loop VDD Core Register 8 R/W Retention VDD Register R/W Integration Test Output Read or Set Register 3 R Debug Performance Register R Revision Number Register NOTE: All registers of IEM interface are accessible by word unit with STR/LDR instructions. Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x7F 0x00 0x00 0x00 0x01 5-21 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2 IEC RELATED REGISTERS 5.5.2.1 DPC Control Register (IECDPCCR, R/W, Address = 0xE080_0000) IECDPCCR Reserved Max Performance mapping index value Synchronous Mode Handshaking Enable IEC Software Debug Emulation IEC Max Perf Enable IEC PWM DVS En IEC Enable Bit [31:8] [7:5] [4] [3] [2] [1] [0] Description Reserved, read undefined, do not modify. When IECMAXPERF goes high, the IEC requests maximum performance level which is decided by this register value. The reset value is 3’b111 which is literally max performance. However, if 3’b111 performance level needs overdrive, it is not desirable to overdrive SoC on every interrupt (MAXPERF case). In that case, software programs this register as lower value than the value needs overdrive. Enable/disable the use of the synchronous mode handshaking control signals. 0 = Synchronous mode handshaking disabled, also the reset value 1 = Synchronous mode handshaking enabled. When this bit is set, the synchronous mode handshaking signals are used to control entry and exit from the maximum performance mode. When this bit is cleared, the handshaking signals are not used. Control to debug performance scaling. 0 = IEC performance scaling software debug disabled, also the reset value 1 = IEC performance scaling software debug enabled. When this bit is seta, the performance level driven out of the IECTGTDVCIDX is set to maximum regardless of the software request. The performance level changes are only visible on IECTGTDCGIDX. Enable/disable maximum performance mode override. 0 = IEC maximum performance mode disabled, also the reset value 1 = IEC maximum performance mode enabled. When this bit is set, the maximum performance mode is enabled and therefore whenever IECMAXPERF goes high, the IEC requests maximum performance level regardless of the current software request. Enable/disable the IEC PWM DVS mode. 0 = IEC PWM DVS mode disabled, also the reset value 1 = IEC PWM DVS mode enabled. When this bit is set, the IEC requests power through the IECPWRREQ output. The target performance index outputs are set to either maximum or minimum depending on the PWM state. Controls enabling and disabling of the IEC. 0 = IEC Disabled, also the reset value 1 = IEC Enabled When this bit is set, the IEC is enabled for performance scaling. When the bit is cleared, the IEC always requests maximum performance. Initial State 0 0x7 0 0 0 0 0 5-22 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.2 DVS Emulation Slot Time Register (IECDVSEMSTR, R/W, Address = 0xE080_0004) IECDVSEMSTR Reserved Slot time Bit [31:10] [9:0] Description Reserved, read undefined, do not modify. The time in μs for each slot of a PWM frame. This is reset to 0x63. For example, if you want each time slot to be 100μs in length, then the slot time bits must be programmed with 0x63. Similarly, if you want each time slot to be 200μs in length, then the slot time bits must be programmed with 0xC7a. Initial State 0 0x63 5.5.2.3 DPC Target Performance Register (IECDPCTGTPERF, W, Address = 0xE080_0008) IECDPCTGTPERF Reserved IECDPCTGTPERF Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Sets the target fractional performance level. At system reset, the value 0x80 (100%). Initial State 0 0x80 5.5.2.4 DPC Current Performance Register (IECDPCCRNTPERF, R, Address = 0xE080_000C) IECDPCCRNTPERF Reserved IECDPCCRNTPERF Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Returns the current performance level as indicated to the IEC by the DCG on the IECCRNTDCGIDX inputs. Initial State 0 System Dependent 5.5.2.5 Interrupt Mask Set and Clear Register (IECIMSC, R/W, Address = 0xE080_0010) IECIMSC Reserved CPU Sleep Interrupt Mask (CSIM) CPU Wake-up Interrupt Mask (CWIM) Bit [31:2] [1] [0] Description Reserved, read undefined, do not modify. On a read, the current mask of the CSIM is returned. On a write of 1, the mask of CSIM interrupt is set. A write of 0 clears the mask. The reset value is 1. On a read, the current mask of the CWIM is returned. On a write of 1, the mask of CWIM interrupt is set. A write of 0 clears the mask. The reset value is 1. Initial State 0 1 1 5-23 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.6 Raw Interrupt Status Register (IECRIS, R, Address = 0xE080_0014) IECRIS Reserved CPU Sleep Interrupt Status (CSRIS) CPU Wake-up Interrupt Status (CWRIS) Bit [31:2] [1] [0] Description Reserved, read undefined, do not modify. Returns the raw interrupt state prior to masking of the IECCPUSLPINT interrupt. The reset value is 0. Returns the raw interrupt state prior to masking of the IECCPUWUINT interrupt. The reset value is 0. Initial State 0 0 0 5.5.2.7 Interrupt Masked Interrupt Status Register (IECMIS, R, Address = 0xE080_0018) IECMIS Reserved Bit Description [31:2] Reserved, read undefined, do not modify. Initial State 0 CPU Sleep Masked [1] Gives the masked interrupt state (after masking) of the 0 Interrupt Status (CSMIS) IECCPUSLPINT interrupt. The reset value is 0. CPU Wake-up Masked [0] Gives the masked interrupt state (after masking) of the 0 Interrupt Status (CWMIS) IECCPUWUINT interrupt. The reset value is 0. 5.5.2.8 Interrupt Clear Register (IECICR, W, Address = 0xE080_001C) IECICR Reserved CPU Sleep Interrupt Clear (CSIC) CPU Wake-up Interrupt Clear (CWIC) Bit [31:2] [1] [0] Description Reserved, read undefined, do not modify. Clears the IECCPUSLPINT interrupt. The reset value is 0. Clears the IECCPUWUINT interrupt. The reset value is 0. Initial State 0 0 0 5.5.2.9 Configured CPU Frequency Register (IECCFGCPUFREQ, R, Address = 0xE080_0020) IECCFGCPUFREQ Reserved Configured CPU Frequency (CFGCPUF) Bit [31:24] [23:0] Description Reserved, read undefined, do not modify. The configured CPU frequency in kHz. Initial State 0 From PMU 5-24 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.10 DPM Frequency Register (IECDPMFREQ, R, Address = 0xE080_0024) IECDPMFREQ Reserved DPM Frequency (DPMF) Bit Description [31:24] Reserved, read undefined, do not modify. [23:0] The DPM frequency in kHz. Initial State 0 From PMU 5.5.2.11 Configuration Fractional Index Map00 Register (IECCFGDCGIDXMAP00, R, Address = 0xE080_0040) IECCFGDCGIDXMAP00 IECCFGDCGIDXMAP00 Bit Description [31:0] State of IECCFGDCGIDXMAP [31:0] Initial State From PMU 5.5.2.12 Configuration Fractional Index Map32 Register (IECCFGDCGIDXMAP32, R, Address = 0xE080_0044) IECCFGDCGIDXMAP32 IECCFGDCGIDXMAP32 Bit Description [31:0] State of IECCFGDCGIDXMAP [63:32] Initial State From PMU 5.5.2.13 Configuration Fractional Index Map32 Register (IECCFGDCGIDXMAP64, R, Address = 0xE080_0048) IECCFGDCGIDXMAP64 IECCFGDCGIDXMAP64 Bit Description [31:0] State of IECCFGDCGIDXMAP [95:64] Initial State From PMU 5.5.2.14 Configuration DVC Index Map Register (IECCFRDVCIDXMAP, R, Address = 0xE080_004C) IECCFGDVCIDXMAP IECCFGDVCIDXMAP Bit [31:24] [23:0] Description Reserved, read undefined, do not modify. State of IECCFGDVCIDXMAP [23:0] Initial State 0 From PMU 5.5.2.15 Configuration Performance Map Register0 (IECCFGDCGPERFMAP0, R, Address = 0xE080_0060) IECCFGDCGPERFMAP0 IECCFGDCGPERFMAP0 Bit Description [31:0] State of IECCFGDCGPERFMAP [31:0] Initial State From PMU 5.5.2.16 Configuration Performance Map Register4 (IECCFGDCGPERFMAP4, R, Address = 0xE080_0064) IECCFGDCGPERFMAP4 IECCFGDCGPERFMAP4 Bit Description [31:0] State of IECCFGDCGPERFMAP [63:32] Initial State From PMU 5-25 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.17 DPM Command Register (IECDPMCR, R/W, Address = 0xE080_0100) IECDPMCR Reserved DPMCH3CMD DPMCH2CMD DPMCH1CMD Bit [31:12] [11:8] [7:4] [3:0] Description Reserved, read undefined, do not modify. DPM Channel 3 command. DPM Channel 2 command. DPM Channel 1 command. Initial State 0 0 0 0 DPMCHxCMD b’0000 b’0001 b’0010 Command Freeze Reset Accumulate Description The channel is frozen and stops accumulating. This is also the reset value. The channel is reset to zero. The channel starts accumulating. Initial State 0 0 0 5.5.2.18 DPM Channel Rate Registers (IECDPM2RATE, R/W, Address = 0xE080_0108) IECDPM2RATE IECDPM2RATE Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. The fractional rate that DPM channel 2 counts. The reset value of this register is 0x80, that is, 100%. Initial State 0 0x80 5.5.2.19 DPM Channel Rate Registers (IECDPM3RATE, R/W, Address = 0xE080_010C) IECDPM3RATE IECDPM3RATE Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. The fractional rate that DPM channel 3 counts. The reset value of this register is 0x80, that is, 100%. Initial State 0 0x80 5.5.2.20 DPM Channel Registers (IECDPM1LO, R, Address = 0xE080_0180) IECDPM1LO IECDPM1LO Bit [31:0] Description Low 32-bit of DPM channel 1. The reset value is 0x00000000. Initial State 0x00000000. 5.5.2.21 DPM Channel Registers (IECDPM1HI, R, Address = 0xE080_0184) IECDPM1HI IECDPM1HI Bit [31:0] Description High 32-bit of DPM channel 1. The reset value is 0x00000000. Initial State 0x00000000 5-26 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.22 DPM Channel Registers (IECDPM2LO, R, Address = 0xE080_0188) IECDPM2LO IECDPM2LO Bit [31:0] Description Low 32-bit of DPM channel 2. The reset value is 0x00000000. 5.5.2.23 DPM Channel Registers (IECDPM2HI, R, Address = 0xE080_018C) IECDPM2HI IECDPM2HI Bit [31:0] Description High 32-bits of DPM channel 2. The reset value is 0x00000000. 5.5.2.24 DPM Channel Registers (IECDPM3LO, R, Address = 0xE080_0190) IECDPM3LO IECDPM3LO Bit [31:0] Description Low 32-bits of DPM channel 3. The reset value is 0x00000000. 5.5.2.25 DPM Channel Registers (IECDPM3HI, R, Address = 0xE080_0194) IECDPM3HI IECDPM3HI Bit [31:0] Description High 32-bits of DPM channel 3. The reset value is 0x00000000. Initial State 0x00000000 Initial State 0x00000000 Initial State 0x00000000. Initial State 0x00000000 5-27 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.26 IEC Integration Test Control Register (IECITCR, R/W, Address = 0xE080_0F00) IECITCR DPM Counter Test DVS Emulation Slot Counter Test ITEN Bit [31:3] [2] [1] [0] Description Reserved. Unpredictable when read. Should be written as zero. Enable or disable test mode for all DPM counters. 0 = DPM counter test mode disabled, also the reset value. 1 = DPM counter test mode enabled. When this bit is set, the 64-bit DPM counters are split up into eight separate 8-bit counters, each accumulate by the CPU or programmed rate. This reduces the testing time required to ensure that all bits of the counters toggle correctly. Enable or disable test mode for the bus V slotcounter. 0 = DVS emulation slot counter test mode disabled, also reset value. 1 = DVS emulation slot counter test mode enabled. When this bit is set, the 10-bit DVS emulation slot timing counter is split up into two 5-bit counters, each decrement separately. This reduces the testing time required to ensure that all bits of the counters toggle correctly. Integration test enable. When this bit is set to 1, the IEC is put into integration test mode. When 0, the IEC is in normal operating mode. The reset value is 0. Initial State 0 0 0 0 5-28 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.27 IEC Integration Test Input Read or Set Registers (IECITIP1, R/W, Address = 0xE080_0F10) IECITIP1 IECSYNCMODEACK IECDPMCLKEN IECDVSEMCLKEN IECCPUWFIACK IECMAXPERF Bit [31:5] [4] [3] [2] [1] [0] Description Reserved. Unpredictable when read. Should be written as zero. Intra-chip input. Writes to this bit, set the value to be driven onto the input IECSYNCMODEACK, in the integration test mode. Reads return the value of the IECSYNCMODEACK input at the output of the test multiplexer. The reset value is 0. Intra-chip input. Writes to this bit, set the value to be driven onto the input IECDPMCLKEN, in the integration test mode. Reads return the value of the IECDPMCLKEN input at the output of the test multiplexer. The reset value is 0. Intra-chip input. Writes to this bit set the value to be driven onto the input IECDVSEMCLKEN, in the integration test mode. Reads return the value of the IECDVSEMCLKEN input at the output of the test multiplexer. The reset value is 0. Intra-chip input. Writes to this bit set the value to be driven onto the input IECCPUWFIACK, in the integration test mode. Reads return the value of the IECCPUWFIACK input at the output of the test multiplexer. The reset value is 0. Intra-chip input. Writes to this bit set the value to be driven onto the input IECMAXPERF, in the integration test mode. Reads return the value of the IECMAXPERF input at the output of the test multiplexer. The reset value is 0. Initial State 0 0 0 0 0 0 5-29 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.28 IEC Integration Test Input Read or Set Registers (IECITIP1, R/W, Address = 0xE080_0F14) IECITIP2 IECCRNTDCGIDX Bit Description [31:8] Reserved, read undefined, do not modify. [7:0] Intra-chip input. Writes to these bits set the value to be driven onto the inputs IECCRNTDCGIDX[7:0], in the integration test mode. Reads return the value of the IECCRNTDCGIDX[7:0] inputs at the output of the test multiplexer. The reset value is 0x00. Initial State 0 0x00 5.5.2.29 IEC Integration Test Input Read or Set Registers (IECITIP1, R/W, Address = 0xE080_0F18) IECITIP3 IECCRNTDVGIDX Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Intra-chip input. Writes to these bits set the value to be driven onto the inputs IECCRNTDVCIDX[7:0], in the integration test mode. Reads return the value of theIECCRNTDVCIDX[7:0] inputs at the output of the test multiplexer. The reset value is 0x00. Initial State 0 0x00 5.5.2.30 Integration Test Output Read or Set Registers (IECITOP1, R/W, Address = 0xE080_0F20) IECITOP1 IECSYNCMODEREQ IECPWRREQ IECCPUSLPINT IECCPUWUINT Bit [31:4] [3] [2] [1] [0] Description Reserved, read undefined, do not modify. Intra-chip output. Writes to this bit set the value to be driven onto the IECSYNCMODEREQ output in integration test mode. Reads return the value of IECSYNCMODEREQ at the output of the test multiplexer. The reset value is 0. Intra-chip output. Writes to this bit set the value to be driven onto the IECPWRREQ output in integration test mode. Reads return the value of IECPWRREQ at the output of the test multiplexer. The reset value is 0. Intra-chip output. Writes to this bit set the value to be driven onto the IECCPUSLPINT output in integration test mode. Reads return the value of IECCPUSLPINT at the output of the test multiplexer. The reset value is 0. Intra-chip output. Writes to this bit set the value to be driven onto the IECCPUWUINT output in integration test mode. Reads return the value of IECCPUWUINT at the output of the test multiplexer. The reset value is 0. Initial State 0 0 0 0 0 5-30 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.31 Integration Test Output Read or Set Registers (IECITOP2, R/W, Address = 0xE080_0F24) IECITOP2 Reserved IECTGTDCGIDX Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Intra-chip outputs. Writes to these bits set the value to be driven onto the IECTGTDCGIDX [7:0] outputs in integration test mode. Reads return the value of IECTGTDCGIDX[7:0] at the output of the test multiplexer. The reset value is 0x00. Initial State 0 0x00 5.5.2.32 Integration Test Output Read or Set Registers (IECITOP3, R/W, Address = 0xE080_0F28) IECITOP3 Reserved IECTGTDVCIDX Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Intra-chip outputs. Writes to these bits set the value to be driven onto the IECTGTDVCIDX[7:0] outputs in integration test mode. Reads return the value of IECTGTDVCIDX[7:0] at the output of the test multiplexer. The reset value is 0x00. Initial State 0 0x00 5.5.2.33 Peripheral Identification Register 0 (IECPeriphID0, R, Address = 0xE080_0FE0) IECPeriphID0 Reserved Partnumber0 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0x50 Initial State X 0x50 5.5.2.34 Peripheral Identification Register 1 (IECPeriphID1, R, Address = 0xE080_0FE4) IECPeriphID1 Reserved Partnumber1 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0x07 Initial State X 0x07 5.5.2.35 Peripheral Identification Register 2 (IECPeriphID2, R, Address = 0xE080_0FE8) IECPeriphID2 Reserved Revision Designer1 Bit [31:8] [7:4] [3:0] Description Reserved, read undefined, do not modify. These bits read back as 0x0 These bits read back as 0x04 Initial State X 0x0 0x04 5-31 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.36 Peripheral Identification Register 3 (IECPeriphID3, R, Address = 0xE080_0FEC) IECPeriphID3 Reserved Configuration 1 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Number of DPC levels. These bits read back as 0x08. Initial State X 0x08 5.5.2.37 Peripheral Identification Register 4 (IECPeriphID4, R, Address = 0xE080_0FD0) IECPeriphID4 Reserved Reserved Configuration 2 Bit [31:8] [7:3] [2:0] Description Reserved, read undefined, do not modify. Reserved Number of DPM channels. These bits are read back as 0x3. Initial State X X 0x3 5.5.2.38 Peripheral Identification Register 5 (IECPeriphID5, R, Address = 0xE080_0FD4) IECPeriphID5 Reserved Configuration 3 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. Number of DVS slots in a frame. These bits read back as 0x08. Initial State X 0x08 5.5.2.39 Peripheral Identification Register 6 (IECPeriphID6, R, Address = 0xE080_0FD8) IECPeriphID6 Reserved Configuration 4 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits are all reserved Initial State X Reserved 5.5.2.40 Peripheral Identification Register 7 (IECPeriphID7, R, Address = 0xE080_0FDC) IECPeriphID7 Reserved Configuration 5 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits are all reserved Initial State X Reserved 5-32 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.2.41 IEC Identification Register 0 (IECID0, R, Address = 0xE080_0FF0) IECID0 IECID0 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0x0D 5.5.2.42 IEC Identification Register 1 (IECID1, R, Address = 0xE080_0FF4) IECID1 IECID1 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0xF0 5.5.2.43 IEC Identification Register 2 (IECID2, R, Address = 0xE080_0FF8) IECID2 IECID2 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0x05 5.5.2.44 IEC Identification Register 3 (IECID3, R, Address = 0xE080_0FFC) IECID3 IECID3 Bit [31:8] [7:0] Description Reserved, read undefined, do not modify. These bits read back as 0xB1 Initial State X 0x0D Initial State X 0xF0 Initial State X 0x05 Initial State X 0xB1 5-33 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3 APC1 RELATED REGISTERS 5.5.3.1 PWI Command Register (APC_PWICMD, R/W, Address = 0xE070_0000) APC_PWICMD PWI Slave Register Address PWI Slave Command Bit Description [7:4] PWI slave Register address of the read and write register. [3:0] PWI slave command: 4’b0000 = Reset 4’b0001 = Authenticate 4’b0010 = Register read 4’b0011 = Register write 4’b0100 = Wakeup 4’b0101 = Sleep 4’b0110 = Shutdown 4’b1001 = Synchronize. Unused command patterns result in a No Operation (NOP) at the PWI interface. Initial State 0x0 0x0 5.5.3.2 PWI Write Data Register (APC_PWIDATAWR, R/W, Address = 0xE070_0004) APC_PWIDATAWR PWI Slave Write Data Bit Description [7:0] Data is written to the PWI slave. Initial State 0x00 5.5.3.3 PWI Read Data Register (APC_PWIDATARD, R, Address = 0xE070_0008) APC_PWIDATARD PWI Slave Read Data Bit Description [7:0] Data is read from the PWI slave. Initial State 0x00 5-34 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.4 APC Control Register (APC_CONTROL, R/W, Address = 0xE070_0010) APC_CONTROL Bit Description Initial State APC_HPM_AUTH_SET [7] HPM is set to the ring oscillator mode for a random PC 0 used in the authentication sequence. APC_PWRSV_EN [6] Enables the power save mode. On setting this bit: 0 * the apc_refclk_req signal is deasserted when the apc_refclk_c clock signal is not required * the CMU can gate off the clock signal to save the power when the apc_refclk_req signal is deasserted. APC_MULTICAL_EN [5] Enables the multiple RCC mode. Default, the APC1 is in 0 the single RCC mode. APC_HPM_EN [4] Enables the HPM. Default, the HPM is disabled and the 0 PC is zero. APC_PWRDN_EN [3] Enables the PWI sleep and wakeup command 0 functions. Default, this feature is disabled. APC_PLL_STATE_DETECT [2] Enable bit for disabling closed loop mode when pll is 0 unstable. APC_LOOP_MODE [1] Enable bit for the closed-loop or the open-loop mode: 0 * defaults to the open-loop mode * setting this bit enables the closed-loop mode. The voltage scaling in the open-loop or the closed-loop mode is enabled only after setting the APC_VDD_UD bit of the APC_CONTROL Register. APC_VDD_UD [0] Enables voltage scaling feature in the APC1: 0 * defaults to the fixed voltage mode and the core voltage is set to the maximum value * for the closed-loop and the open-loop modes this bit must be enabled. 5.5.3.5 APC Status Register (APC_STATUS, R, Address = 0xE070_0014) APC_STATUS Reserved AUTH_DONE PWI_BUSY POWERWISE _VERIFIED VDDOK Bit Description [7:4] Read undefined. [3] Authentication procedure is completed. [2] Bit is set on initiating a PWI command and is cleared when the command sequence is completed. [1] Bit is set on a successful PowerWise capable power supply authentication. [0] Vdd level is suitable for the current target frequency. This bit is set in the closed-loop mode. Initial State 0 0 0 0 0 5-35 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.6 Minimum Limit Register (APC_MINVDD_LIMIT, R/W, Address = 0xE070_0018) APC_MINVDD_LIMIT Reserved Minimum core voltage Bit Description [7] Read undefined. Write as zero. [6:0] Minimum SoC operating core voltage. Initial State 0 0x00 5.5.3.7 VDD Check Register (APC_VDDCHK, R/W, Address = 0xE070_001C) APC_VDDCHK vddchkd[3:0] vddchk[3:0] Bit Description [7:4] The upper nibble of this register holds the four LSBs of the 12-bit vddchkd counter. [3:0] Evaluation time period during the integration of the slack in the closed Initial State 0x0 0x0 5.5.3.8 VDD Delay Time Register (APC_VDDCHKD, R/W, Address = 0xE070_0020) APC_VDDCHKD vddchkd[11:4] Bit Description [7:0] Holds the upper eight bits of the 12-bit vddchkd counter. Initial State 0x00 5.5.3.9 VDD Pre-delay Select Register (APC_PREDYSEL, R/W, Address = 0xE070_0024) APC_PREDYSEL Reserved Pre-delay Bit Description [7:3] Read undefined. Write as zero. [2:0] Selects the predelay value for the HPM. Initial State 0 0x7 5.5.3.10 APC Interrupt Mask Register (APC_IMASK, R/W, Address = 0xE070_0028) APC_IMASK Reserved APB Write Discard PWI Transaction Done Error Detected in PWI No PWI Slave Response Output Voltage Clamped Low VDD Timeout Undershoot Interrupt Bit Description [7] Read undefined. Write as zero. [6] The APB write is discarded. [5] The PWI transaction is completed. [4] Error is detected in the PWI response frame. [3] No response frame detected on the PWI interface. [2] The output voltage is clamped to the minimum voltage limit or to the zero voltage. [1] Vdd has not reached the optimum voltage in the closedloop mode for the voltage upward slew within the hardware defined time period. [0] Undershoot interrupt. Initial State 0 0 0 0 0 0 0 0 5-36 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.11 APC Interrupt Status Register (APC_ISTATUS, R, Address = 0xE070_002C) APC_ISTATUS Reserved APB Write Discard PWI Transaction Done Error Detected in PWI No PWI Slave Response Output Voltage Clamped Low VDD Timeout Undershoot Interrupt Bit Description [7] Read undefined. [6] When the PWI command is active in the APC1, the new PWI commands issued by the host are discarded. This discarded status is reflected in this bit. [5] Bit is set when the APC1 completes the host issued PWI command. Software has to check this bit as well as the APC_STATUS.PWI_BUSY bit to confirm the completion of the command. [4] Bit is set on an error response from the PWI slave for the host issued as well as the APC1 issued PWI commands. [3] Bit is set for no response from the PWI slave for the host issued as well as the APC1 issued commands. [2] This bit is set when the output voltage is clamped to the minimum limit or to the zero voltage. [1] During upward voltage slew, this bit is set in the closedloop mode indicating that the dynamic compensator is not able to increase the voltage to the required level for the new higher performance level within the maximum time period set by the hardware. [0] In the closed-loop AVS operation for a performance level change after reaching the optimum voltage the APC1 asserts an interrupt if the voltage correction continues and results in a slack error (+ve) which is more than the undershoot_limit value programmed in the APC_UNSHT_NOISE Register for nine consecutive samples. Initial State 0 0 0 0 0 0 0 0 5.5.3.12 APC Interrupt Clear Register (APC_ICLEAR, W, Address = 0xE070_0030) APC_ICLEAR Reserved APB Write Discard PWI Transaction Done Error Detected in PWI No PWI Slave Response Output Voltage Clamped Low VDD Timeout Undershoot Interrupt Bit Description [7] Undefined. Write as zero. [6] The APB write is discarded. [5] The PWI transaction is completed. [4] Error is detected in PWI response frame. [3] No response frame is detected on PWI interface. [2] The output voltage is clamped to minimum limit or zero voltage. [1] In the closed-loop mode, Vdd has not reached the target voltage in the programmed time period for the upward voltage slew. [0] Undershoot interrupt. Initial State 0 0 0 0 0 0 0 0 5-37 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.13 APC Undershoot Threshold and Noise Limit Register (APC_UNSHT_NOISE, R/W, Address = 0xE070_0034) APC_UNSHT_NOISE Reserved Noise Limit for VDDOK Undershoot Threshold Level Bit Description [7:6] Read undefined. Write as zero. [5:4] Noise limit for the VDDOK generation due to the power supply regulation errors. Provides the acceptable integrated eHPM (+ve) below the RCC value for updating the performance level in the closed-loop mode. APC_UNSHT_NOISE[5:4] Minimum Accumulated eHPM 00 0 01 4 10 16 11 31 [3:0] This is the threshold level for the detection of voltage undershoot interrupt on the voltage slew. The value programmed is the amount of eHPM (+ve) allowed after reaching the optimum core voltage for the safe SoC operation. Initial State 0 0x0 0x0 5.5.3.14 Wakeup Delay Register (APC_WKUP_DLY, R/W, Address = 0xE070_0038) APC_WKUP_DLY Wakeup Delay Bit Description [7:0] Count for the wakeup delay. Initial State 0x00 5.5.3.15 Slack Sample Count Register (APC_SLK_SMP, R/W, Address = 0xE070_003C) APC_SLK_SMP Reserved Slack Sample Count Bit Description [7:6] Read undefined. Write as zero. [5:0] The time period for each count in the vddchkd and the vddchk counters during the performance level change: * set to 0x1D for 2μs when theapc_refclk_c clock is 15MHZ * set to 0x3B for 2μs when the apc_refclk_c clock is 30MHZ. Initial State 0 0x00 5-38 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.16 PWI Clock Division Register (APC_CLKDIV_PWICLK, R/W, Address = 0xE070_0040) APC_CLKDIV_PWICLK Reserved Programmable Clock Division Bit [7:4] [3:0] Description Read undefined. Write as zero. Programmable division to theapc_refclk_c clock frequency for the PWI clock. The clock division is equal to 2 * (APC_CLKDIV_PWICLK + 1). Initial State 0 0x0 5.5.3.17 APC Overshoot Limit Register (APC_OVSHT_LMT, R/W, Address = 0xE070_0050) APC_OVSHT_LMT overshoot limit Bit Description [7:0] Overshoot limit during the voltage slew in the closed-loop mode. Initial State 0x00 5.5.3.18 APC Closed-loop Control Register (APC_CLP_CTRL, R/W, Address = 0xE070_0054) APC_CLP_CTRL Reserved APC_SS_GAIN_EN APC_UP_GAIN_EN APC_LOW_GAIN_EN APC_SAT_GAIN_EN Bit Description Initial State [7:4] Undefined. Write as zero. 0 [3] Enables steady state gain term. 0 [2] Enables the APC_GAIN2 term for the dynamic 0 compensator. This gain term is selected during voltage upward slew. [1] Enables the APC_GAIN4 term for the dynamic 0 compensator. This gain term is selected when the slack or eHPM value is between +3 to -3. [0] Enables the APC_GAIN3 term for the dynamic 0 compensator. This gain term is selected when the PC value is saturated and the voltage is stepping up. This gain term has higher priority over the gain term 2. 5.5.3.19 APC Steady State Slew Rate Register (APC_SS_SRATE, R/W, Address = 0xE070_0058) APC_SS_SRATE Reserved APC_SS_SMP_RATE APC_GAIN_SEL Bit Description [7:4] Read undefined. [3:2] 00 Sample the eHPM every 32 apc_refclk_c cycles. 01 Sample the eHPM every 16 apc_refclk_c cycles. 10 Sample the eHPM every 8 apc_refclk_c cycles. 11 Sample the eHPM every apc_refclk_c cycle. [1:0] 00 Gain term value of 0 in steady state mode. 01 Gain term value of 1 in steady state mode. 10 Gain term value of 2 in steady state mode. 11 Gain term value of 3 in steady state mode. Initial State 0 0x0 0x0 5-39 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.20 Integrator’s Gain Registers (APC_IGAIN1, R/W, Address = 0xE070_0060) APC_IGAIN1 Reserved Gain 1 Bit Description [7:4] Read undefined. Write as zero. [3:0] Default gain term for the dynamic compensator. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations. Initial State 0 0x0 5.5.3.21 Integrator’s Gain Registers (APC_IGAIN2, R/W, Address = 0xE070_0064) APC_IGAIN2 Reserved Gain 2 Bit Description [7:4] Read undefined. Write as zero. [3:0] Gain term for the upward voltage slew when enabled in the APC_CLP_CTRL Register. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations. Initial State 0 0x0 5.5.3.22 Integrator’s Gain Registers (APC_IGAIN3, R/W, Address = 0xE070_0068) APC_IGAIN3 Reserved Gain 3 Bit [7:4] [3:0] Description Read undefined. Write as zero. Dynamic compensator uses this gain term for the saturated HPM output when enabled. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations. Initial State 0 0x0 5.5.3.23 Integrator’s Gain Registers (APC_IGAIN4, R/W, Address = 0xE070_006C) APC_IGAIN4 Reserved Gain 4 Bit Description [7:4] Read undefined. Write as zero. [3:0] Selected by the dynamic compensator when enabled in the APC_CL_CTRL Register for the low slack values. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations. Initial State 0 0x0 5-40 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.24 Integration Test Control Register (APC_ITSTCTRL, R/W, Address = 0xE070_006C) APC_ITSTCTRL Bit Description Reserved [7:2] Undefined. Write as zero. IT_OPEN [1] Integration test output enable. The reset value is zero. 1 = APC1 is in integration test mode. 0 = APC1 is in normal mode. This control bit also drives the apc_hpm_it_en output signal. When this signal is asserted, the HPM is set to the integration test mode. In this mode the primary inputs are directly connected to the primary outputs. IT_IPEN [0] Integration test input enable. The reset value is zero. 1 = APC1 is in integration test mode. 0 = APC1 is in normal mode. Initial State 0 0 0 5.5.3.25 Integration Test Input Read or Set Registers (APC_ITSTIP1, R/W, Address = 0xE070_0070) APC_ITSTIP1 Reserved HPM_DELAY _CODE[4:0] APC_SYNC _FROM_HPM APC_CLAMP _ACK Bit Description [7] Undefined. Write as zero. [6:2] In integration test mode: • write drives the hpm_delay_code inputs to the design • read returns the register content. In normal mode: • write updates the register • read returns the data from the hpm_delay_code primary inputs. [1] In integration test mode: • write drives the apc_sync_from_hpm input to the design • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_sync_from_hpm primary input. [0] In integration test mode: • write drives the apc_clamp_ack input to the design • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_clamp_ack primary input. Initial State 0 0x00 0 0 5-41 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.26 Integration Test Input Read or Set Registers (APC_ITSTIP2, R/W, Address = 0xE070_0074) APC_ITSTIP2 Reserved APC_TARGET_INDEX Bit [7:N] [N-1:0] Description Read undefined. Write as zero. In integration test mode: • write drives the apc_target_index inputs to the design • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_target_index primary inputs. Initial State 0 0x00 5-42 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.27 Integration Test Output Read or Set Registers (APC_ITSTOP1, R/W, Address = 0xE070_0078) APC_ITSTOP1 Bit Description APC_PREDELAY _SEL[2:0] [7:5] In integration test mode: • write drives the apc_predelay_selprimary outputs • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_predelay_sel signals of the design. APC_HPM_EN [4] In integration test mode: • write drives the apc_hpm_enprimary output • read returns the register content. In normal mode: • write updates the register • read returns the data from theapc_hpm_en signal of the design. APC_CLAMP_REQ [3] In integration test mode: • write drives the apc_clamp_reqprimary output • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_clamp_req signal of the design. APC_INTERRUPT [2] In integration test mode: • write drives the apc_interruptprimary output • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_interrupt signal of the design. APC_SYNC_TO_HPM [1] In integration test mode: • write drives the apc_sync_to_hpmprimary output • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_sync_to_hpm signal of the design. APC_REFCLK_REQ [0] In integration test mode: • write drives the apc_refclk_reqprimary output • read returns the register content. In normal mode: • write updates the register • read returns the data from theapc_refclk_req signal of the design. Initial State 0x0 0 0 0 0 0 5-43 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.28 Integration Test Output Read or Set Registers (APC_ITSTOP2, R/W, Address = 0xE070_007C) APC_ITSTOP2 Reserved APC_CURRENT_INDEX Bit [7:N] [N-1:0] Description Read undefined. Write as zero. In integration test mode: • write drives the apc_current_index primary outputs • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_current_index signals of the design. Initial State 0 0x00 5.5.3.29 Integration Test Output Read or Set Registers (APC_ITSTOP3, R/W, Address = 0xE070_00C4) APC_ITSTOP3 Reserved APC_HPM_AUTH_SET Bit Description [7:1] Read undefined. Write as zero. [0] In integration test mode: • write drives the apc_hpm_auth_set primary output • read returns the register content. In normal mode: • write updates the register • read returns the data from the apc_hpm_auth_set signal of the design. Initial State 0 0 5-44 S5PV210_UM 5 4BINTELLIGENT ENERGY MANAGEMENT 5.5.3.30 Voltage Information Registers APC1 has two types of voltage information registers. Ones are for closed-loop control, and the others are for open-loop control. Registers for closed-loop control give delay information, while registers for open-loop control give direct voltage information. There is a register containing the retention voltage level for the performance level zero. • Calibration Code Registers (APC_PL1_CALCODE, R/W, Address = 0xE070_0080) • Calibration Code Registers (APC_PL2_CALCODE, R/W, Address = 0xE070_0084) • Calibration Code Registers (APC_PL3_CALCODE, R/W, Address = 0xE070_0088) • Calibration Code Registers (APC_PL4_CALCODE, R/W, Address = 0xE070_008C) • Calibration Code Registers (APC_PL5_CALCODE, R/W, Address = 0xE070_0090) • Calibration Code Registers (APC_PL6_CALCODE, R/W, Address = 0xE070_0094) • Calibration Code Registers (APC_PL7_CALCODE, R/W, Address = 0xE070_0098) • Calibration Code Registers (APC_PL8_CALCODE, R/W, Address = 0xE070_009C) The Calibration Code Registers are eight, 5-bit registers. Their names are APC_PL1_CALCODE ~ APC_PL8_CALCODE. They give delay information target for closed-loop operation. APC_PL*_CALCODE Reserved Reference Calibrated Code 1 Bit Description [7:5] Read undefined. Write as zero. [4:0] The RCC for performance level * Initial State X 0x1F • Open-loop VDD Core Registers (APC_PL1_COREVDD, R/W, Address = 0xE070_00A0) • Open-loop VDD Core Registers (APC_PL2_COREVDD, R/W, Address = 0xE070_00A4) • Open-loop VDD Core Registers (APC_PL3_COREVDD, R/W, Address = 0xE070_00A8) • Open-loop VDD Core Registers (APC_PL4_COREVDD, R/W, Address = 0xE070_00AC) • Open-loop VDD Core Registers (APC_PL5_COREVDD, R/W, Address = 0xE070_00B0) • Open-loop VDD Core Registers (APC_PL6_COREVDD, R/W, Address = 0xE070_00B4) • Open-loop VDD Core Registers (APC_PL7_COREVDD, R/W, Address = 0xE070_00B8) • Open-loop VDD Core Registers (APC_PL8_COREVDD, R/W, Address = 0xE070_00BC) The Open-loop VDD Core Registers are eight, 7-bit registers. Their names are APC_PL1_COREVDD ~ APC_PL8_COREVDD. They give direct voltage information for open-loop operation. APC_PL*_COREVDD Reserved OL_VDD1 Bit Description Initial State [7] Read undefined. Write as zero. X [6:0] The voltage value for the performance level * in the open-loop mode. 0x7F 5-45 S5PV210_UM 1 5.5.3.31 Retention VDD Registers (APC_RET_VDD, R/W, Address = 0xE070_00C0) APC_RET_VDD Reserved Retention VDD Bit Description [7] Read undefined. Write as zero. [6:0] The retention voltage level for performance level zero. Initial State 0 0x00 5.5.3.32 Debug Performance Registers (APC_DBG_DLYCODE, R, Address = 0xE070_00E0) APC_DBG_DLYCODE Reserved Performance Code Bit Description [7:5] Read undefined. [4:0] The PC of the HPM. Initial State 0 0x00 5.5.3.33 Revision Number Registers (APC_REV, R, Address = 0xE070_00FC) APC_REV Revision Number Bit Description [7:0] Holds the APC1 revision number. Initial State 0x01 5-46 S5PV210_UM 6 5BBOOTING SEQUENCE 6 BOOTING SEQUENCE 6.1 OVERVIEW OF BOOTING SEQUENCE S5PV210 consists of 64KB ROM and 96KB SRAM as internal memory. For booting, internal 64KB ROM and internal 96KB SRAM regions can be used. S5PV210 boots from internal ROM to enable secure booting, which ensures that the image cannot be altered by unauthorized users. To select secure booting or normal booting, S5PV210 should use e-fuse information. This information cannot be altered after being programmed. The booting device can be chosen from following list: • General NAND Flash memory • OneNAND memory • SD/ MMC memory (such as MoviNAND and iNAND) • eMMC memory • eSSD memory • UART and USB devices At system reset, the program counter starts from the iROM codes in internal ROM region. However, the system reset may be asserted not only on booting time, but also on wakeup from low power modes. Therefore, the iROM code must execute appropriate process according to the reset status (refer to Table 6-1). The boot loader is largely composed of iROM, first and second boot loaders. The characteristics of these boot loaders are: • iROM code: Contains small and simple code, which is platform-independent and stored in internal memory • First boot loader: Contains small and simple code, which is platform-independent and stored in external memory device. Related to secure booting. • Second boot loader: Contains complex code, which is platform-specific and stored in external memory device. If you select secure booting, iROM code and first boot loader provide integrity checking function (that is it uses public key algorithm) to verify loaded image. There are 160 e-fuse bits of secure boot key, and they are used to authenticate loaded public key before the iROM’s integrity check. For more information on secure booting, refer to Chapter. 6-1 S5PV210_UM Figure 6-1 shows the block diagram of booting time operation. 6 5BBOOTING SEQUENCE Figure 6-1 Block Diagram of Booting Time Operation • The iROM code is placed in internal 64KB ROM. It initializes basic system functions such as clock, stack, and heap. • The iROM loads the first boot loader image from a specific booting device to internal 96KB SRAM. The booting device is selected by Operating Mode (OM) pins. According to the secure boot key values, the iROM code may do an integrity check on the first boot loader image. • The first boot loader loads the second boot loader then may check the integrity of the second boot loader according the secure boot key values. • The second boot loader initializes system clock, UART, and DRAM controller. After initializing DRAM controller, it loads OS image from the booting device to DRAM. According to the secure boot key values, the second boot loader can do an integrity check on the OS image. • After the booting completes, the second boot loader jumps to the operating system. The iROM code reads the OM pins to find the booting device. The OM register provides the OM pin and other information required for booting. For more information on OM register, refer to Chapter 02.01, "Chip ID". The OM pin decides the booting devices such as OneNAND, NAND, MoviNAND, eSSD and iNAND. It also decides the device options such as bit width, wait cycles, page sizes, and ECC modes. NOTE: USB booting is provided for system debugging and flash reprogramming, not for normal booting. Hence, it is selected by toggling OM[5:4] pin to “2’b10” without considering other OM pin values. The iROM code in internal 64KB ROM is named BL0. And the first boot loader is named BL1 6-2 S5PV210_UM 6 5BBOOTING SEQUENCE 6.2 SCENARIO DESCRIPTION 6.2.1 RESET STATUS There are several scenarios for system reset such as hardware reset, watchdog reset, software reset, and wake up from power down modes. For each scenario, the mandatory functions are summarized in Table 6-1 Table 6-1 Functions Needed for Various Reset Status Basic Initialization in iROM PLL Setting in iROM First Boot / Second Boot Loader Loading DRAM Setting in Second Boot Loader OS Loading Restore Previous State Hardware Reset O O O O O X Watchdog Reset O O O O Wake up from SLEEP O O O O SW reset O O O O Wake up from DEEP_STOP O Wake up from DEEP_IDLE O X X (note) X X X (note) X NOTE: When the contents of SRAM are preserved by retention option. O X X O O X X O X O At the time of hardware reset and watchdog reset, the system should boot fully with the first boot loader and the second boot loader and loading of OS image. The new reset status is classified as reset group0. Since the contents of DRAM memory are preserved in the SLEEP mode, it does not require loading the OS image to DRAM. However, SoC internal power is not supplied to internal logic during SLEEP mode and all contents in internal SRAM are not preserved. Therefore, the first boot loader and the second boot loader should be loaded again. This reset status is classified as reset group1. At the time of software reset, The loading of boot loader is executed. Although top block’s power is gated in DEEP_STOP and DEEP_IDLE modes, the internal SRAM can be reserved, so that the re-loading of boot loader is not required. In case of non-retention of SRAM in DEEP_STOP and DEEP_IDLE modes, the first boot loader should be loaded again. These software reset that wake up from DEEP_STOP and DEEP_IDLE statuses are classified as reset group2. If system enters into all power down modes, the current system status should be saved to safe memory region such as DRAM, so that the system continues processing seamlessly after waking up from power down modes. Finally, the restoring previous state function is required on wake up from SLEEP, DEEP_STOP, and DEEP_IDLE modes. 6-3 S5PV210_UM 6.2.2 BOOTING SEQUENCE EXAMPLE Figure 6-2 shows the flow chart related to total booting code sequence. 6 5BBOOTING SEQUENCE Figure 6-2 Total Booting Code Sequence Flow Chart 6-4 S5PV210_UM 6 5BBOOTING SEQUENCE Program code starts from internal ROM(iROM) and moves to internal SRAM(iRAM). Finally, program executes on DRAM. The booting sequence in internal ROM is as follows: 1. Disable the watchdog timer. 2. Initialize the instruction cache controller. 3. Initialize the stack and heap region. 4. Check secure key. 5. Set Clock divider, lock time, PLL (MPS value), and source clock. 6. Check OM pin and load the first boot loader (The size of boot loader depends on S/W) from specific device (block number 0) to iRAM. 7. If secure booting is successful, execute integrity check 8. If integrity check passes, then jump to the first boot loader in iRAM (0xD002_0010) The booting sequence in internal SRAM is as follows: 1. Load the second boot loader from boot device to iRAM. 2. If secure booting is successful, execute integrity check. 3. If integrity check passes, then jump to the second boot loader in iRAM (The jumping address depends on user's software) 4. If integrity check fails, then stop the first boot loader. 5. The second boot loader Initializes the DRAM controller. 6. Load the OS image from specific device (block number 1) to DRAM. 7. Jump to OS code in DRAM (0x2000_0000 or 0x4000_0000) The booting sequence in DRAM is as follows: 1. If S5PV210 is powered on from SLEEP, DEEP_STOP, or DEEP_IDLE modes, then restore the previous state. 2. Jump to OS code. 6-5 S5PV210_UM 6 5BBOOTING SEQUENCE 6.2.3 FIXED PLL AND CLOCK SETTING To speed up first boot loader’s operation, the first boot loader initializes the PLL with fixed value. Fixed PLL setting is as follows: • APLL: M=200, P=6, S=1 FOUT = (MDIV X FIN )/ (PDIV X 2(SDIV-1))) = 800MHz • MPLL: M=667, P=12, S=1 FOUT = (MDIV X FIN) / (PDIV X 2SDIV) = 667MHz • EPLL: M=80, P=3, S=3, K=0 FOUT = ((MDIV+KDIV) X FIN) / (PDIV X 2SDIV) = 80MHz Table 6-2 shows the system clock frequencies for various external crystals after initialization of the PLL by first boot loader. Table 6-2 First Boot Loader's Clock Speed at 24 MHz External Crystal ARMCLK ACLK200 HCLK200 PCLK100 HCLK100 HCLK166 PCLK83 SCLK_FIMC HCLK133 400 133 133 66 66 133 66 133 133 6-6 S5PV210_UM 6 5BBOOTING SEQUENCE 6.2.4 OM PIN CONFIGURATION Table 6-3 shows the booting option that can be set by OM pins. Table 6-3 OM Pin Setting for Various Booting Option OM[5] 1'b0 OM[4] 1'b0 OM[3] 1'b0 1'b1 OM[2] 1'b0 1'b1 1'b0 1'b1 OM[1] 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 OM[0] 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 OM[5] Boot Mode OM[4] I-ROM OM[3] OM[2] OM[1] eSSD NAND 2 KB, 5cycle (NAND 8-bit ECC) NAND 4 KB, 5cycle (NAND 8-bit ECC) NAND 4 KB, 5cycle (NAND 16-bit ECC) OnenandMux(Audi) OnenandDemux(Audi) SD/MMC eMMC(4-bit) OM[0] X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) 1'b0 1'b1 1'b1 1'b0 1'b0 1'b1 1'b1 1'b1 1'b0 1'b0 1'b0 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 1'b0 1'b0 1'b0 1'b1 1'b0 1'b0 1'b1 1'b1 1'b0 1'b0 1'b0 1'b1 1'b1 1'b0 1'b1 1'b1 NAND 2 KB, 5cycle (16-bit bus, 4-bit ECC) NAND 2 KB, 4cycle (NAND 8-bit ECC) iROM NOR boot eMMC(8-bit) I-ROM First boot UART ->USB eSSD NAND 2 KB, 5cycle NAND 4 KB, 5cycle NAND 16-bit ECC (NAND 4 KB, 5cycle) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) 1'b1 1'b0 1'b0 1'b0 OnenandMux(Audi) X-TAL 6-7 S5PV210_UM 6 5BBOOTING SEQUENCE OM[5] OM[4] OM[3] OM[2] OM[1] OM[0] OM[5] 1'b1 1'b0 1'b1 1'b1 1'b0 1'b0 1'b1 1'b1 1'b0 1'b1 1'b1 OM[4] OM[3] OM[2] OM[1] OnenandDemux(Audi) SD/MMC eMMC(4-bit) OM[0] X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) X-TAL X-TAL(USB) NOTE: The first boot loader tries to negotiate UART first. If it fails, then it tries to drive the USB device. Hence, you have to disconnect the UART device if you want to boot using USB device. The hardware logic decides address mapping, and the software routine decides other booting options. The value of OM pin can be read from OM register, which is described in Chapter 2.1. 6-8 S5PV210_UM 6 5BBOOTING SEQUENCE 6.2.5 SECURE BOOTING The basic criterion for security system is "The ‘root of trust’ has to be hardware. You cannot request a software system to ‘validate’ itself.” In S5PV210, the root of trust is implemented by iROM code in internal ROM. Therefore it cannot be modified by unauthorized users. The hardware design proves the integrity of iROM code. On the other hand, the first boot loader, the second boot loader and OS images are stored in external memory devices. Therefore, the iROM code (that has already been proved as secure) should verify the integrity of first boot loader. If the integrity check passes on first boot loader, the first boot loader is included in trust region. Then, first boot loader verifies the integrity of the second boot loader, the second boot loader verifies the integrity of the OS image. Figure 6-3 shows the secure booting diagram. The secure booting sequence is as follows: The iROM code 1. Checks the integrity of RSA public key using E-fuse RSA key hash value. 2. Loads the first boot loader to iRAM. 3. Checks the integrity of first boot loader using trusted RSA public key. The first boot loader 1. Loads security software to iRAM. 2. Checks the integrity of software using trusted RSA public key. 3. Loads second boot loader to iRAM. 4. Checks the integrity of second boot loader using trusted RSA public key. The second boot loader 1. Loads security software to iRAM. 2. Checks the integrity of software using trusted RSA public key. 3. Loads OS kernel and applications to DRAM. 4. Checks the integrity of OS kernel and application using trusted RSA public key 6-9 S5PV210_UM 6 5BBOOTING SEQUENCE Figure 6-3 Secure Booting Diagram 6-10 Section 3 BUS Table of Contents 1 Bus Configuration ......................................................................................1-2 1.1 Overview of Bus Configuration ................................................................................................................ 1-2 1.1.1 AXI Interconnect ............................................................................................................................... 1-2 1.2 Register Description................................................................................................................................. 1-6 1.2.1 Register Map .................................................................................................................................... 1-6 1.2.2 Synchronizer Configuration Register (ASYNC_CONFIG0~10, R/W)............................................... 1-7 2 Coresight.....................................................................................................2-1 2.1 Coresight System Overview..................................................................................................................... 2-1 2.1.1 About Coresight Systems Generals ................................................................................................. 2-1 2.1.2 Key Features of Coresight................................................................................................................ 2-2 2.2 Debug Access Port .................................................................................................................................. 2-7 2.2.1 About Debug Access Port ................................................................................................................ 2-7 2.3 ETB .......................................................................................................................................................... 2-9 2.3.1 About the ETB .................................................................................................................................. 2-9 2.3.2 About the ECT ................................................................................................................................ 2-10 3 Access Controller (TZPC)..........................................................................3-1 3.1 Overview of Access Controller (TZPC).................................................................................................... 3-1 3.1.1 Key Features of Access Controller (TZPC) ...................................................................................... 3-1 3.1.2 Block Diagram of Access Controller (TZPC) .................................................................................... 3-1 3.2 Functional Description ............................................................................................................................. 3-2 3.3 TZPC Configuration ................................................................................................................................. 3-3 3.4 Register DiscripTion................................................................................................................................. 3-5 3.4.1 Register Map .................................................................................................................................... 3-5 List of Figures Figure Number Title Page Number Figure 1-1 Figure 1-2 Figure 1-3 Example of ProgQoS Control for 2-1 Interconnect ........................................................................... 1-3 Example Operation of RR Arbitration Scheme ................................................................................. 1-4 Example Operation of LRG Arbitration Scheme............................................................................... 1-5 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 DAP Connections Inside a SoC Cross Triggering ............................................................................ 2-3 S5PV210 Coresight Structure........................................................................................................... 2-4 Debugger Register Map of S5PV210 ............................................................................................... 2-5 Structure of the Coresight DAP Components................................................................................... 2-8 ETB Block Diagram ECT (CTI + CTM) ............................................................................................. 2-9 Coresight CTI and CTM Block Diagram ......................................................................................... 2-10 Figure 3-1 Block Diagram of Access Controller (TZPC) .................................................................................... 3-1 List of Tables Table Number Title Page Number Table 2-1 Authentication Signal Rule................................................................................................................. 2-6 Table 3-1 Table 3-2 Table 3-3 TZPC Table........................................................................................................................................ 3-3 TZPC Transfer Attribute..................................................................................................................... 3-4 TZPC Registers.................................................................................................................................. 3-5 S5PV210_UM 1 BUS CONFIGURATION 1 BUS CONFIGURATION 1.1 OVERVIEW OF BUS CONFIGURATION This chapter describes the bus configuration in S5PV210. 1.1.1 AXI INTERCONNECT S5PV210 consists of 12 high-performance AXI interconnect. The role of AXI interconnect is to interconnect bus masters to bus slaves. 1.1.1.1 Key Features of AXI Interconnect The key features of AXI interconnect include: • Quality of Service The Quality of Service (QoS) scheme tracks the number of outstanding transactions. When a specified number is reached, it permits transactions from specified masters only. This scheme only provides support for slaves that have a combined acceptance capability such as the Dynamic Memory Controller (DMC). The QoS scheme has no effect until the AXI interconnect matrix calculates the following: At a particular Master Interface (MI), there are a number of outstanding transactions equal to the value stored in QoS tidemark. It then accepts transactions only from slave ports specified in the QoS access control. This restriction remains until the number of outstanding transactions is again less than the value stored in QoS tidemark. Figure 1-1 shows the implementation for an interconnect supporting two masters and one slave. 1-2 S5PV210_UM 1 BUS CONFIGURATION Figure 1-1 Example of ProgQoS Control for 2-1 Interconnect • Arbitration scheme In the AXI interconnect, you can configure each MI separately to contain an arbitration scheme. This scheme is further classified as: − Non-programmable RR scheme − Programmable RR scheme − Programmable LRG scheme The AW and AR channels have separate arbiters, and can be programmed (if applicable) and interrogated separately through APB programming interface. However, both AW and AR channels are configured identically. If these channels are arbitrated separately, MI can permit simultaneous read and write transactions from different SIs. The arbitration policy is decided by the values of SFRs. An arbitration decision taken in the current cycle does not affect the current cycle. If no SIs are active, the arbiter adopts default arbitration, that is, the highest priority SI. If default arbitration occurs and the highest priority SI becomes active in the same cycle as (or before) any other SI, then this does not constitute a grant to an active SI and the arbitration scheme does not change its state. If a QoS provision is active, only a subset of SI is permitted to win arbitration. There is no guarantee that the default arbitration is among these. In these circumstances, no transaction is permitted to use the default arbitration, and arbitration must occur whenever there is an active SI. 1-3 S5PV210_UM 1 BUS CONFIGURATION 1.1.1.2 Round-robin (RR) Scheme In the RR scheme, you can select the following design time: • Number of used slots • SI to which these slots are allocated • Order of slots There must be at least one slot per connected SI and up to 32 slots. By allocating multiple slots for a SI, you can allocate access to the slave on average, in proportion to the number of slots. If the slots are appropriately ordered, this can also reduce the maximum time before a grant is guaranteed. The SI associated with a slot can be interrogated by APB programming interface, but it cannot be changed. Whenever arbitration is granted to an active SI, the slots are rotated so that the slot in the highest priority position becomes the lowest and all other slots move to a higher priority, but maintain their relative order, as shown in Figure 1-2. This means that if an SI is the highest priority active SI, but is not the highest priority interface, then it continues to win the arbitration until it becomes the highest priority interface, and then the lowest priority interface subsequently. Figure 1-2 Example Operation of RR Arbitration Scheme Since the arbitration value is registered, the arbitration decision made in this cycle is used in the next cycle. This means that if SI (that currently holds the arbitration) has the highest priority active SI in this cycle, it wins the arbitration again--regardless of whether or not it is active in the next cycle, as shown by the status of M3 in stages A, B, and C in Figure 1-2. 1-4 S5PV210_UM 1 BUS CONFIGURATION 1.1.1.3 Least Recently Granted Scheme In the Least Recently Granted (LRG) scheme, each connected SI has a single slot associated with it, but each interface also has a priority value. This priority value, whose post-reset value can be configured at design time, programmed, or interrogated through the APB programming interface, can make the arbiter behave as: • Pure LRG scheme • Fixed priority encoder • Combination of the two All masters with the same priority form a priority group. As a result of arbitration, a master can move within its priority group but cannot leave its group, and no new masters can join the group. Arbitration is granted to the highest priority group from which a member is trying to win access and within that group to the highest master at that time. When master wins arbitration, it is relegated to the bottom of its group to ensure that it does not prevent other masters in its group from accessing the slave. If you configure all master priorities to different levels, the arbiter implements a fixed priority scheme. This occurs because in this case, each master is in a group of its own, and therefore, masters maintain their ordering. If all master priorities are the same, then an LRG scheme is implemented. The reason all master priorities behave as LRG is because the process of relegating the master that was last granted access to the bottom of its group results in the masters being ordered from the LRG master at the top to the Most Recently Granted (MRG) at the bottom. The LRG and fixed priority modes concurrently exist when the master priority values are set with a combination of identical and unique values. You can mix priority groups that contain one member with priority groups that contain more than one member in an arbitrary manner. The arbiter places no restriction on the number of groups or their membership. Figure 1-3 shows the movement of masters within their priority groups. Figure 1-3 Example Operation of LRG Arbitration Scheme 1-5 S5PV210_UM 1.2 REGISTER DESCRIPTION 1 BUS CONFIGURATION 1.2.1 REGISTER MAP Register ASYNC_CONFIG0 ASYNC_CONFIG1 ASYNC_CONFIG2 ASYNC_CONFIG3 ASYNC_CONFIG4 ASYNC_CONFIG5 ASYNC_CONFIG6 ASYNC_CONFIG7 ASYNC_CONFIG8 ASYNC_CONFIG9 ASYNC_CONFIG10 Address 0xE0F0_0000 0xE1F0_0000 0xF180_0000 0xF190_0000 0xF1A0_0000 0xF1B0_0000 0xF1C0_0000 0xF1D0_0000 0xF1E0_0000 0xF1F0_0000 0xFAF0_0000 R/W Description R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register R/W Synchronizer configuration register Reset Value 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 0x0000_0001 1-6 S5PV210_UM 1 BUS CONFIGURATION 1.2.2 SYNCHRONIZER CONFIGURATION REGISTER (ASYNC_CONFIG0~10, R/W) ASYNC_CONFIG0~10 Reserved HALF_SYNC_SEL Bit [31:1] [0] Description Reserved Use half synchronizer for asynchronous clock domain crossing. Initial State 0x0 0x1 HALF_SYNC_SEL field of ASYNC_CONFIG0~10 registers decides whether to use half or full synchronization for synchronizer, which separates two different clock domains. Setting this field to HIGH selects half synchronizer, which has better performance over full synchronizer. On the contrary, full synchronizer has a better MTBF (Mean Time Between Failure) resulting from crossing clock domains. It is recommended to use full synchronization for stable operation. 1-7 S5PV210_UM 2 CORESIGHT 2 CORESIGHT 2.1 CORESIGHT SYSTEM OVERVIEW 2.1.1 ABOUT CORESIGHT SYSTEMS GENERALS CoreSight systems provide the entire infrastructure required to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design. There are historically three main ways of debugging an ARM processor based SoC: • Conventional JTAG debug. This is invasive debug with the core halted using: − Breakpoints and watchpoints to halt the core on specific activity − A debug connection to examine and modify registers and memory and provide single-step execution. • Conventional monitor debug. This is invasive debug with the core running using a debug monitor that resides in memory. • Trace. This is non-invasive debug with the core running at full speed using: − Collection of information on instruction execution and data transfers − Delivery off-chip in real-time − Tools to merge data with source code on a development workstation for later analysis. 2-1 S5PV210_UM 2 CORESIGHT 2.1.2 KEY FEATURES OF CORESIGHT 2.1.2.1 Debug Access You gain debug access in CoreSight systems through the Debug Access Port (DAP) that provides: • Real-time access to physical memory without halting the core and without any target resident code • Debug control and access to all status registers The same mechanism provides fast access to download code at the start of the debug session. This is faster than the traditional JTAG mechanism that uses the ARM core to write data to memory. You can still use the ARM core to write data to virtual memory and to ease migration when the debugger does not support this approach. Figure 2-1 shows an example system with debug components and a DAP in a SoC design. The DAP provides the following advantages for multi-core SoC designs: • There is no requirement to run at the lowest common speed. A slow or powered down component has no effect on access to other components. This means that power management has minimal impact on debug. • The number of devices in the system does not affect the access speed. You have direct access to individual devices. • You can add third party debug components with the Advanced Microcontroller Bus Architecture (AMBA) debug bus interface, AMBA 3 Advanced Peripheral Bus (APB), which provides internal and external access to the component. • More than one core can control debug functionality, rather than restricting this to the core being debugged. One core can debug another. In particular this enables a multi-core SoC when used as a single core platform to have complex on-chip debug and analysis features. You could use this, for example, during application development. 2-2 S5PV210_UM 2 CORESIGHT Figure 2-1 DAP Connections Inside a SoC Cross Triggering The Embedded Cross Trigger (ECT), comprising of the Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM), provides a standard interconnect mechanism to pass debug or profiling events around the SoC. The ECT provides a standard mechanism to connect different signal types. A set of standard triggers for cores are predefined and you can add triggers for third party cores. The ECT enables tool developers to supply a standard control dialog so that software programmers can connect trigger events. 2.1.2.2 Trace The CoreSight Design Kit provides components that support a standard infrastructure for the capture and transmission of trace data, combination of multiple data streams by funneling together, and then output of data to a trace port or storing in an on-chip buffer. 2-3 S5PV210_UM 2 CORESIGHT 2.1.2.3 Coresight System in S5PV210 S5PV210 is single processor system with CortexA8 core. Its main bus system is based on AMBA3 AXI interconnects. It does not support Serial Wire debug port protocol. Figure 2-2 shows configuration of debugging system. Figure 2-2 S5PV210 Coresight Structure 2-4 S5PV210_UM 2 CORESIGHT Although Coresight’s registers can be accessed through system APB bus as well as JTAG port, the address map of those registers are observed differently. While the memory map for JTAG port is same as shows in Figure 2-2, the memory map for system view is same as the memory map for JTAG port + system register offset. The debugger register map of S5PV210 is summarized in Figure 2-3. System view 0xE0D0_8000 0xE0D0_7000 0xE0D0_6000 0xE0D0_5000 0xE0D0_4000 0xE0D0_3000 0xE0D0_2000 0xE0D0_1000 0xE0D0_0000 SecureJTAG CortexA8 CTI CortexA8 embedded trace mactocell CortexA8 Debug Coresight FUNNEL Reserved Coresight CTI Coresight ETB ROM table Debugger view 0x0000_8000 or 0x8000_8000 0x0000_7000 or 0x8000_7000 0x0000_6000 or 0x8000_6000 0x0000_5000 or 0x8000_5000 0x0000_4000 or 0x8000_4000 0x0000_3000 or 0x8000_3000 0x0000_2000 or 0x8000_2000 0x0000_1000 or 0x8000_1000 0x0000_0000 or 0x8000_0000 Figure 2-3 Debugger Register Map of S5PV210 2.1.2.4 Authentication for Secure JTAG Operation S5PV210 supports Secure JTAG by using authentication signal of cortexA8 and coresight system. To set the secure JTAG mode can program Secure JTAG key e-fuse bit. • [79:0]: Secure JTAG hash key • [80]: Secure JTAG lock on - 0: non-protection, 1: protected by Secure JTAG Before authentication, the debugger should access Secure JTAG module mapped in debugger register map. If Secure JTAG lock on bit is programmed as “1”, the authentication signals such as DBGEN, NIDEN, SPIDEN, and SPNIDEN are all “0” before passing authentication. 2-5 S5PV210_UM 2 CORESIGHT By writing the passwords in predefined sequence, the authentication can be done. After authentication, the authentication signals are selectively asserted as defined in Table 2-1. Mode JTAG unplugged non-protected mode secure invasive JTAG and authenticated as secure invasive JTAG and authenticated as secure non-invasive JTAG and authenticated as non-secure invasive JTAG and authenticated as non-secure non-invasive JTAG and nonauthenticated Table 2-1 Authentication Signal Rule JTAG Detect JTAG lock on Access Level DBGEN NIDEN 0 X X 0 0 SPIDEN SPNIDEN 0 0 1 0 X 1 1 1 1 1 1 4 1 1 1 1 1 1 3 1 1 0 1 1 1 2 1 1 0 0 1 1 1 0 1 0 0 1 1 0 0 0 0 0 The authentication sequence script and the hash key generation program will be provided to the customer. 2-6 S5PV210_UM 2 CORESIGHT 2.2 DEBUG ACCESS PORT 2.2.1 ABOUT DEBUG ACCESS PORT The Debug Access Port (DAP) is an implementation of ARM Debug Interface version 5 (ADIv5) comprising a number of components supplied in a single configuration. All the supplied components fit into the various architectural components for Debug Ports (DPs), which are used to access the DAP from an external debugger and Access Ports (APs), to access on-chip system resources. The debug port and access ports together are referred to as DAP. The DAP provides real-time access to the debugger without halting the core to: • AMBA system memory and peripheral registers • All debug configuration registers. The DAP also provides debugger access to JTAG scan chains of system components, for example non-CoreSight compliant processors. Figure 2-4 shows the top-level view of the functional blocks of the DAP. The DAP enables debug access to the complete SoC using a number of master ports. Access to the CoreSight Debug Advanced Peripheral Bus (APB) is enabled through the APB Access Port (APBAP) and APB Multiplexer (APB-MUX), and system access through the Advanced High-performance Bus Access Port (AHB-AP). The DAP comprises of following interface blocks: • External debug access using the JTAG Debug Port. − External JTAG access using the JTAG Debug Port (JTAG-DP). • System access using: − AHB-AP − APB-AP − JTAG-AP − DAPBUS exported interface. • An APB multiplexer enables system access to CoreSight components connected to the Debug APB. • The ROM table provides a list of memory locations of CoreSight components connected to the Debug APB. This is visible from both tools and system access. There are three access ports supplied in the DAP, and it is possible to connect a fourth access port externally. The supplied access ports within this release are: • AHB-AP for connection to the main system bus • APB-AP to enable direct connection to the dedicated Debug Bus • JTAG-AP to control up to eight scan chains. 2-7 S5PV210_UM 2 CORESIGHT Figure 2-4 Structure of the Coresight DAP Components 2-8 S5PV210_UM 2 CORESIGHT 2.3 ETB 2.3.1 ABOUT THE ETB The ETB provides on-chip storage of trace data using 32-bit RAM. Figure 2-5 shows the main ETB blocks. The ETB accepts trace data from CoreSight trace source components through an AMBA Trace Bus (ATB). The ETB contains the following blocks: • Formatter - Inserts source ID signals into the data packet stream so that trace data can be re-associated with its trace source after the data is read back out of the ETB. • Control - Control registers for trace capture and flushing. • APB interface - Read, write, and data pointers provide access to ETB registers. In addition, the APB interface supports wait states through the use of a PREADYDBG signal output by the ETB. The APB interface is synchronous to the ATB domain. • Register bank - Contains the management, control, and status registers for triggers, flushing behavior, and external control. • Trace RAM interface - Controls reads and writes to the Trace RAM. • Memory BIST interface - Provides test access to the Trace RAM. Figure 2-5 ETB Block Diagram ECT (CTI + CTM) 2-9 S5PV210_UM 2 CORESIGHT 2.3.2 ABOUT THE ECT The ECT provides an interface to the debug system as shown in Figure 2-6. This enables an ARM subsystem to interact, that is cross trigger, with each other. The debug system enables debug support for multiple cores, together with cross triggering between the cores and their respective internal embedded trace macrocells. The main function of the ECT (CTI and CTM) is to pass debug events from one processor to another. For example, the ECT can communicate debug state information from one core to another, so that program execution on both processors can be stopped at the same time if required. • Cross Trigger Interface (CTI) The CTI combines and maps the trigger requests, and broadcasts them to all other interfaces on the ECT as channel events. When the CTI receives a channel event it maps this onto a trigger output. This enables subsystems to cross trigger with each other. The receiving and transmitting of triggers is performed through the trigger interface. • Cross Trigger Matrix (CTM) This block controls the distribution of channel events. It provides Channel Interfaces (CIs) for connection to either CTIs or CTMs. This enables multiple CTIs to be linked together. Figure 2-6 Coresight CTI and CTM Block Diagram 2-10 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3 ACCESS CONTROLLER (TZPC) 3.1 OVERVIEW OF ACCESS CONTROLLER (TZPC) The TrustZone Protection Controller (TZPC) is an AMBA-compliant, tested, and licensed by ARM Limited. The TZPC provides a software interface to the protection bits in a secure system in a TrustZone design. It provides system flexibility that enables to configure different areas of memory as secure or non-secure. The S5PV210 comprises of four TZPC. 3.1.1 KEY FEATURES OF ACCESS CONTROLLER (TZPC) Protection bits: This enables you to program maximum 32 areas of memory as secure or non-secure Secure region bits: This enables you to split an area of internal RAM into both secure and non-secure regions The Access Controller includes AMBA APB system interface 3.1.2 BLOCK DIAGRAM OF ACCESS CONTROLLER (TZPC) APB bus TZPC APB interface Registers TZPCR0SIZE TZPCDECPROT0 TZPCDECPROT1 TZPCDECPROT2 TZPCDECPROT3 Figure 3-1 Block Diagram of Access Controller (TZPC) 3-1 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.2 FUNCTIONAL DESCRIPTION The TZPC provides a software interface to set up memory areas as secure or non-secure. The two ways to set up memory area as secure or non-secure is as follows: • Programmable protection bits that can be allocated to memory area as determined by the external decoder. • Programmable region size value for use by an AXI TrustZone Memory Adapter (TZMA). You can use this to split the RAM into two regions: − One secure − One non-secure This enables the best use of memory and other system resources. It is assumed that the specific secure and nonsecure requirements for an application are determined during: • Boot-up • OS or secure kernel port development work This means that the secure and non-secure memory partitioning is not expected to change dynamically during normal software operation because it is fixed at compile time and is only configured once during system boot-up. Ensure that this boot-up is always made in secure-state to guarantee full security protection. 3-2 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.3 TZPC CONFIGURATION Table 3-1 TZPC Table Register Bit [0] [1] [2] [3] TZPCDECPROT0 [4] [5] [6] [7] [0] [1] [2] [3] TZPCDECPROT1 [4] [5] [6] [7] [0] [1] [2] [3] TZPCDECPROT2 [4] [5] [6] [7] [0] [1] [2] [3] TZPCDECPROT3 [4] [5] [6] [7] TZPCR0SIZE TZPC0 Module Name DMC0 DMC1 INTC* MFC G3D SDM IntMEM TZPC1 Module Name XBLOCK* TBLOCK* HDMI_LINK MDMA - DSIM CSIS I2C_HDMI_PHY I2C_HDMI_DDC LBLOCK* MDNIE - TZPC2 Module Name CHIPID SYSCON GPIO - IEM_APC IEM_IEC PDMA0 PDMA1 CORESIGHT SPDIF PCM1 SPI0 SPI1 SPI2 KEYIF TSADC I2C0(general) I2C(PMIC) I2S1 AC97 PCM0 PWM ST WDT RTC UART SBLOCK* CBLOCK* - TZPC3 Module Name HDMI_CEC UBLOCK* GBLOCK* AUDIO(I2S0)** I2S2 PCM2 - - 3-3 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) * XBLOCK, TBLOCK, UBLOCK, GBLOCK, LBLOCK, SBLOCK, CBLOCK and INTC Refer to Figure 3-1 of Section 2-3.S5PV210_CMU. ** AUDIO includes I2S0. If non-secure master accesses to secure slave area, DECERR occurs. Master Attribute Secure Master Table 3-2 TZPC Transfer Attribute Transfer Attribute Secure Transfer Secure Transfer Non-Secure Transfer Non-Secure Transfer Slave/Area Attribute Secure Slave / Area Non-Secure Slave / Area Secure Slave / Area Non-Secure Slave / Area Response OK OK DECERR OK 3-4 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.4 REGISTER DISCRIPTION 3.4.1 REGISTER MAP Register TZPC0 TZPCR0SIZE TZPCDECPROT0Stat TZPCDECPROT0Set TZPCDECPROT0Clr TZPCDECPROT1Stat TZPCDECPROT1Set TZPCDECPROT1Clr TZPCDECPROT2Stat TZPCDECPROT2Set TZPCDECPROT2Clr TZPCDECPROT3Stat TZPCDECPROT3Set TZPCDECPROT3Clr TZPCPERIPHID0 TZPCPERIPHID1 TZPCPERIPHID2 TZPCPERIPHID3 TZPCPCELLID0 TZPCPCELLID1 TZPCPCELLID2 TZPCPCELLID3 TZPC1 Table 3-3 TZPC Registers Address R/W Description 0xF150_0000 0xF150_0800 0xF150_0804 0xF150_0808 0xF150_080C 0xF150_0810 0xF150_0814 0xF150_0818 0xF150_081C 0xF150_0820 0xF150_0824 0xF150_0828 0xF150_082C 0xF150_0FE0 0xF150_0FE4 0xF150_0FE8 0xF150_0FEC 0xF150_0FF0 0xF150_0FF4 0xF150_0FF8 0xF150_0FFC R/W Specifies the Secure RAM Region Size Register R Specifies the Decode Protection 0 Status Register W Specifies the Decode Protection 0 Set Register W Specifies the Decode Protection 0 Clear Register R Specifies the Decode Protection 1 Status Register W Specifies the Decode Protection 1 Set Register W Specifies the Decode Protection 1 Clear Register R Specifies the Decode Protection 2 Status Register W Specifies the Decode Protection 2 Set Register W Specifies the Decode Protection 2 Clear Register R Not used W Not used W Not used R Specifies the TZPC Peripheral Identification Register 0 R Specifies the TZPC Peripheral Identification Register 1 R Specifies the TZPC Peripheral Identification Register 2 R Not used R Specifies the TZPC Identification Register 0 R Specifies the TZPC Identification Register 1 R Specifies the TZPC Identification Register 2 R Not used Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000070 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 3-5 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) Register TZPCR0SIZE TZPCDECPROT0Stat TZPCDECPROT0Set TZPCDECPROT0Clr TZPCDECPROT1Stat TZPCDECPROT1Set TZPCDECPROT1Clr TZPCDECPROT2Stat TZPCDECPROT2Set TZPCDECPROT2Clr TZPCDECPROT3Stat TZPCDECPROT3Set TZPCDECPROT3Clr TZPCPERIPHID0 TZPCPERIPHID1 TZPCPERIPHID2 TZPCPERIPHID3 TZPCPCELLID0 TZPCPCELLID1 TZPCPCELLID2 TZPCPCELLID3 TZPC2 TZPCR0SIZE TZPCDECPROT0Stat TZPCDECPROT0Set TZPCDECPROT0Clr Address 0xFAD0_0000 0xFAD0_0800 0xFAD0_0804 0xFAD0_0808 0xFAD0_080C 0xFAD0_0810 0xFAD0_0814 0xFAD0_0818 0xFAD0_081C 0xFAD0_0820 0xFAD0_0824 0xFAD0_0828 0xFAD0_082C 0xFAD0_0FE0 0xFAD0_0FE4 0xFAD0_0FE8 0xFAD0_0FEC 0xFAD0_0FF0 0xFAD0_0FF4 0xFAD0_0FF8 0xFAD0_0FFC 0xE060_0000 0xE060_0800 0xE060_0804 0xE060_0808 R/W Description R/W Not used R Specifies the Decode Protection 0 Status Register W Specifies the Decode Protection 0 Set Register W Specifies the Decode Protection 0 Clear Register R Specifies the Decode Protection 1 Status Register W Specifies the Decode Protection 1 Set Register W Specifies the Decode Protection 1 Clear Register R Specifies the Decode Protection 2 Status Register W Specifies the Decode Protection 2 Set Register W Specifies the Decode Protection 2 Clear Register R Not used W Not used W Not used R Specifies the TZPC Peripheral Identification Register 0 R Specifies the TZPC Peripheral Identification Register 1 R Specifies the TZPC Peripheral Identification Register 2 R Not used R Specifies the TZPC Identification Register 0 R Specifies the TZPC Identification Register 1 R Specifies the TZPC Identification Register 2 R Not used R/W Not used R Specifies the Decode Protection 0 Status Register W Specifies the Decode Protection 0 Set Register W Specifies the Decode Protection 0 Clear Register Reset Value 0x00000200 0x00000000 - - 0x00000000 - - 0x00000000 - - 0x00000000 - 0x00000070 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 0x00000200 0x00000000 - - 3-6 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) Register TZPCDECPROT1Stat TZPCDECPROT1Set TZPCDECPROT1Clr TZPCDECPROT2Stat TZPCDECPROT2Set TZPCDECPROT2Clr TZPCDECPROT3Stat TZPCDECPROT3Set TZPCDECPROT3Clr TZPCPERIPHID0 TZPCPERIPHID1 TZPCPERIPHID2 TZPCPERIPHID3 TZPCPCELLID0 TZPCPCELLID1 TZPCPCELLID2 TZPCPCELLID3 TZPC3 TZPCR0SIZE TZPCDECPROT0Stat TZPCDECPROT0Set TZPCDECPROT0Clr TZPCDECPROT1Stat TZPCDECPROT1Set TZPCDECPROT1Clr Address 0xE060_080C 0xE060_0810 0xE060_0814 0xE060_0818 0xE060_081C 0xE060_0820 0xE060_0824 0xE060_0828 0xE060_082C 0xE060_0FE0 0xE060_0FE4 0xE060_0FE8 0xE060_0FEC 0xE060_0FF0 0xE060_0FF4 0xE060_0FF8 0xE060_0FFC 0xE1C0_0000 0xE1C0_0800 0xE1C0_0804 0xE1C0_0808 0xE1C0_080C 0xE1C0_0810 0xE1C0_0814 R/W Description R Specifies the Decode Protection 1 Status Register W Specifies the Decode Protection 1 Set Register W Specifies the Decode Protection 1 Clear Register R Specifies the Decode Protection 2 Status Register W Specifies the Decode Protection 2 Set Register W Specifies the Decode Protection 2 Clear Register R Specifies the Decode Protection 3 Status Register W Specifies the Decode Protection 3 Set Register W Specifies the Decode Protection 3 Clear Register R Specifies the TZPC Peripheral Identification Register 0 R Specifies the TZPC Peripheral Identification Register 1 R Specifies the TZPC Peripheral Identification Register 2 R Specifies the TZPC Peripheral Identification Register 3 R Specifies the TZPC Identification Register 0 R Specifies the TZPC Identification Register 1 R Specifies the TZPC Identification Register 2 R Specifies the TZPC Identification Register 3 R/W Not used R Specifies the Decode Protection 0 Status Register W Specifies the Decode Protection 0 Set Register W Specifies the Decode Protection 0 Clear Register R Not used W Not used W Not used Reset Value 0x00000000 0x00000000 0x00000000 0x00000070 0x00000018 0x00000000 0x00000004 0x0000000D 0x000000F0 0x00000005 0x000000B1 0x00000200 0x00000000 0x00000000 - 3-7 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) Register TZPCDECPROT2Stat TZPCDECPROT2Set TZPCDECPROT2Clr TZPCDECPROT3Stat TZPCDECPROT3Set TZPCDECPROT3Clr TZPCPERIPHID0 TZPCPERIPHID1 TZPCPERIPHID2 TZPCPERIPHID3 TZPCPCELLID0 TZPCPCELLID1 TZPCPCELLID2 TZPCPCELLID3 Address 0xE1C0_0818 0xE1C0_081C 0xE1C0_0820 0xE1C0_0824 0xE1C0_0828 0xE1C0_082C 0xE1C0_0FE0 0xE1C0_0FE4 0xE1C0_0FE8 0xE1C0_0FEC 0xE1C0_0FF0 0xE1C0_0FF4 0xE1C0_0FF8 0xE1C0_0FFC R/W Description R Not used W Not used W Not used R Not used W Not used W Not used R Specifies the TZPC Peripheral Identification Register 0 R Not used R Not used R Not used R Specifies the TZPC Identification Register 0 R Not used R Not used R Not used Reset Value 0x00000000 0x00000000 0x00000070 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 3-8 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.1 Secure RAM Region Size Register (TZPCR0SIZE(TZPC0), RW, Address = 0xF150_0000) TZPCR0SIZE Reserved R0Size Bit [31:6] [5:0] Description Read undefined. Write as zero. Secure RAM region size in 4KB steps. 0x00000000 = no secure region 0x00000001 = 4KB secure region 0x00000002 = 8KB secure region … 0x0000001F = 128KB secure region 0x00000020 or above sets the entire RAM to secure regardless of size Initial State 0 0x0 3.4.1.2 Decode Protection 0-3 Status Registers • TZPCDECPROTxSTAT(TZPC0), R, Address = 0xF150_0800, 0xF150_080C, 0xF150_0818 • TZPCDECPROTxSTAT(TZPC1), R, Address = 0xFAD0_0800, 0xFAD0_080C, 0xFAD0_0818 • TZPCDECPROTxSTAT(TZPC2), R, Address = 0xE060_0800, 0xE060_080C, 0xE060_0818 • TZPCDECPROTxSTAT(TZPC3), R, Address = 0xE1C0_0800, 0xE1C0_080C, 0xE1C0_0818 TXPCDECPROTxStat Reserved DECPROTxStat Bit [31:8] [7:0] Description Read undefined. Show the status of the decode protection output: 0 = Decode region corresponding to the bit is secure 1 = Decode region corresponding to the bit is non-secure There is one bit of the register for each protection output, eight outputs are implemented as standard. Initial State 0 0x000 3-9 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.3 Decode Protection 0-2 Set Registers • TZPCDECPROTxSet(TZPC0), W, Address = 0xF150_0804, 0xF150_0810, 0xF150_081C • TZPCDECPROTxSet(TZPC1), W, Address = 0xFAD0_0804, 0xFAD0_0810, 0xFAD0_081C • TZPCDECPROTxSet(TZPC2), W, Address = 0xE060_0804, 0xE060_0810, 0xE060_081C • TZPCDECPROTxSet(TZPC3), W, Address = 0xE1C0_0804, 0xE1C0_0810, 0xE1C0_081C TXPCDECPROTxSet Reserved DECPROTxSet Bit [31:8] [7:0] Description Write as zero. Sets the corresponding decode protection output: 0 = No effect 1 = Set decode region to non-secure There is one bit of the register for each protection output, eight outputs are implemented as standard. Initial State - 3.4.1.4 Decode Protection 0-2 Clear Registers • TZPCDECPROTxClr(TZPC0), W, Address = 0xF150_0808, 0xF150_081C, 0xF150_0820 • TZPCDECPROTxClr(TZPC1), W, Address = 0xFAD0_0808, 0xFAD0_081C, 0xFAD0_0820 • TZPCDECPROTxClr(TZPC2), W, Address = 0xE060_0808, 0xE060_081C, 0xE060_0820 • TZPCDECPROTxClr(TZPC3), W, Address = 0xE1C0_0808, 0xE1C0_081C, 0xE1C0_0820 TXPCDECPROTxClr Reserved DECPROTxClr Bit [31:8] [7:0] Description Write as zero. Clears the corresponding decode protection output: 0 = No effect 1 = Set decode region to secure There is one bit of the register for each protection output, eight outputs are implemented as standard. Initial State 3-10 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.5 TZPC Peripheral Identification Register 0 (TZPCPERIPHID0, R, Address = 0xF150_0FE0, 0xFAD0_0FE0, 0xE060_0FE0, 0xE1C0_0FE0) TZPCPERIPHID0 Reserved Partnumber0 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x70 Initial State 0 0x70 3.4.1.6 TZPC Peripheral Identification Register 1 (TZPCPERIPHID1, R, Address = 0xF150_0FE4, 0xFAD0_0FE4, 0xE060_0FE4, 0xE1C0_0FE4) TZPCPERIPHID1 Reserved Designer0 Partnumber1 Bit [31:8] [7:4] [3:0] Description Read undefined These bits read back as 0x1 These bits read back as 0x8 Initial State 0 0x1 0x8 3.4.1.7 TZPC Peripheral Identification Register 2 (TZPCPERIPHID2, R, Address = 0xF150_0FE8, 0xFAD0_0FE8, 0xE060_0FE8, 0xE1C0_0FE8) TZPCPERIPHID2 Reserved Revision Designer1 Bit [31:8] [7:4] [3:0] Description Read undefined These bits read back as the revision number which can be 0-15 These bits read back as 0x4 Initial State 0 0x0 0x4 3.4.1.8 TZPC Peripheral Identification Register 3 (TZPCPERIPHID3, R, Address = 0xF150_0FEC, 0xFAD0_0FEC, 0xE060_0FEC, 0xE1C0_0FEC) TZPCPERIPHID3 Reserved Configuration Bit [31:8] [7:0] Description Read undefined These bits read back as 0x00 Initial State 0 0x0 3-11 S5PV210_UM 3 ACCESS CONTROLLER (TZPC) 3.4.1.9 Identification Register 0 (TZPCPCELLID0, R, Address = 0xF150_0FF0, 0xFAD0_0FF0, 0xE060_0FF0, 0xE1C0_0FF0) TZPCPCELLID0 Reserved TZPCPCELLID0 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x0D Initial State 0 0x0D 3.4.1.10 Identification Register 1 (TZPCPCELLID1, R, Address = 0xF150_0FF4, 0xFAD0_0FF4, 0xE060_0FF4, 0xE1C0_0FF4) TZPCPCELLID1 Reserved TZPCPCELLID1 Bit [31:8] [7:0] Description Read undefined These bits read back as 0xF0 Initial State 0 0xF0 3.4.1.11 Identification RegisteR 2 (TZPCPCELLID2, R, Address = 0xF150_0FF8, 0xFAD0_0FF8, 0xE060_0FF8, 0xE1C0_0FF8) TZPCPCELLID2 Reserved TZPCPCELLID2 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x05 Initial State 0 0x05 3.4.1.12 Identification RegisteR 3 (TZPCPCELLID3, R, Address = 0xF150_0FFC, 0xFAD0_0FFC, 0xE060_0FFC, 0xE1C0_0FFC) TZPCPCELLID3 Reserved TZPCPCELLID3 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x00 Initial State 0 0x00 3-12 Section 4 INTERRUPT Table of Contents 1 Vectored Interrupt Controller ....................................................................1-2 1.1 Overview of Vectored Interrupt Controller ............................................................................................... 1-2 1.1.1 Key Features of Vectored Interrupt Controller.................................................................................. 1-2 1.2 Nterrupt Source........................................................................................................................................ 1-3 1.3 Functional Description ............................................................................................................................. 1-7 1.4 Register Description................................................................................................................................. 1-8 1.4.1 Register Map .................................................................................................................................... 1-8 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1 VECTORED INTERRUPT CONTROLLER 1.1 OVERVIEW OF VECTORED INTERRUPT CONTROLLER The interrupt controller in S5PV210 is composed of four Vectored Interrupt Controller (VIC), ARM PrimeCell PL192 and four TrustZone Interrupt Controller (TZIC), SP890. Three TZIC’s and three VIC’s are daisy-chained to support up to 93 interrupt sources. The TZIC provides a software interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ interrupt and masks the interrupt source(s) from the interrupt controller on the non-secure side of the system (VIC). Use the latter to generate nIRQ signal. To generate nFIQ from the non-secure interrupt sources, the TZIC0 takes the nNSFIQIN signal from the nonsecure interrupt controller. 1.1.1 KEY FEATURES OF VECTORED INTERRUPT CONTROLLER • Supports 93 vectored IRQ interrupts • Fixed hardware interrupts priority levels • Programmable interrupt priority levels • Supports Hardware interrupt priority level masking • Programmable interrupt priority level masking • Generates IRQ and FIQ • Generates Software interrupt • Test registers • Raw interrupt status • Interrupt request status • Supports Privileged mode for restricted access I 1-2 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.2 NTERRUPT SOURCE The S5PV210 supports interrupt sources as shown in the Table below. Module VIC3 Multimedia, Audio, Security, Etc., VIC2 VIC port no 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 No INT Request 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 PENDN1 (TSADC) 105 ADC1 (TSADC) 104 103 102 101 100 TSI 99 CEC 98 MMC3 97 96 95 SDM_FIQ (security) Remark 1-3 S5PV210_UM Module Multimedia, Audio, Security, Etc., VIC1 ARM, power, memory, 1 VECTORED INTERRUPT CONTROLLER VIC port no 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 No INT Request 94 SDM_IRQ (security) 93 PCM2 92 IntFeedCtrl_SSS 91 IntHash_SSS 90 89 KEYPAD 88 PENDN (TSADC) 87 ADC (TSADC) 86 SPDIF 85 PCM1 84 PCM0 83 AC97 82 81 I2S1 80 I2S0 79 TVENC 78 MFC 77 I2C_HDMI_DDC 76 HDMI 75 Mixer 74 3D 73 2D 72 JPEG 71 FIMC2 70 FIMC1 69 FIMC0 68 ROTATOR 67 66 LCD[2] 65 LCD[1] 64 LCD[0] 63 ONENAND_AUDI 62 MIPI_DSI 61 MIPI_CSI 60 HSMMC2 59 HSMMC1 Remark 1-4 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Module Connectivity, Storage VIC port no 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIC0 31 System, 30 DMA, 29 Timer 28 27 No INT Request 58 HSMMC0 57 MODEMIF 56 OTG (usb) 55 UHOST (usb) 54 53 52 I2C_HDMI_PHY 51 I2C2 50 AUDIO_SS 49 48 SPI1 47 SPI0 46 I2C0 45 UART3 44 UART2 43 UART1 42 UART0 41 CFC 40 NFC 39 38 IEM_IEC 37 IEM_APC 36 CORTEX4 (nCTIIRQ) 35 CORTEX3 (nDMAEXTERIRQ) 34 CORTEX2 (nDMAIRQ) 33 CORTEX1 (nDMASIRQ) 32 CORTEX0 (nPMUIRQ) 31 FIMC3 30 GPIOINT 29 RTC_TIC 28 RTC_ALARM 27 WDT Remark All other GPIO interrupt mux 1-5 S5PV210_UM Module 1 VECTORED INTERRUPT CONTROLLER VIC port no 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No INT Request 26 System Timer 25 TIMER4 24 TIMER3 23 TIMER2 22 TIMER1 21 TIMER0 20 PDMA1 19 PDMA0 18 MDMA 17 16 EINT 16_31 15 EINT15 14 EINT14 13 EINT13 12 EINT12 11 EINT11 10 EINT10 9 EINT9 8 EINT8 7 EINT7 6 EINT6 5 EINT5 4 EINT4 3 EINT3 2 EINT2 1 EINT1 0 EINT0 Remark EXT_INT[16] ~ [31] EXT_INT[15] EXT_INT[14] EXT_INT[13] EXT_INT[12] EXT_INT[11] EXT_INT[10] EXT_INT[9] EXT_INT[8] EXT_INT[7] EXT_INT[6] EXT_INT[5] EXT_INT[4] EXT_INT[3] EXT_INT[2] EXT_INT[1] EXT_INT[0] 1-6 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.3 FUNCTIONAL DESCRIPTION When user clears interrupt pending, user must write 0 to all the VICADDRESS registers (VIC0ADDRESS, VIC1ADDRESS, VIC2ADDRESS, and VIC3ADDRESS). 1-7 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4 REGISTER DESCRIPTION 1.4.1 REGISTER MAP Register VIC0IRQSTATUS VIC0FIQSTATUS VIC0RAWINTR VIC0INTSELECT VIC0INTENABLE VIC0INTENCLEAR VIC0SOFTINT VIC0SOFTINTCLEAR VIC0PROTECTION VIC0SWPRIORITYMASK VIC0PRIORITYDAISY VIC0VECTADDR0 VIC0VECTADDR1 VIC0VECTADDR2 VIC0VECTADDR3 VIC0VECTADDR4 VIC0VECTADDR5 VIC0VECTADDR6 VIC0VECTADDR7 VIC0VECTADDR8 VIC0VECTADDR9 VIC0VECTADDR10 VIC0VECTADDR11 VIC0VECTADDR12 VIC0VECTADDR13 VIC0VECTADDR14 VIC0VECTADDR15 VIC0VECTADDR16 VIC0VECTADDR17 VIC0VECTADDR18 Address 0xF200_0000 0xF200_0004 0xF200_0008 0xF200_000C 0xF200_0010 0xF200_0014 0xF200_0018 0xF200_001C 0xF200_0020 0xF200_0024 0xF200_0028 0xF200_0100 0xF200_0104 0xF200_0108 0xF200_010C 0xF200_0110 0xF200_0114 0xF200_0118 0xF200_011C 0xF200_0120 0xF200_0124 0xF200_0128 0xF200_012C 0xF200_0130 0xF200_0134 0xF200_0138 0xF200_013C 0xF200_0140 0xF200_0144 0xF200_0148 R/W Description Reset Value R Specifies the IRQ Status Register 0x00000000 R Specifies the FIQ Status Register 0x00000000 R Specifies the Raw Interrupt Status - Register R/W Specifies the Interrupt Select Register 0x00000000 R/W Specifies the Interrupt Enable Register 0x00000000 W Specifies the Interrupt Enable Clear - Register R/W Specifies the Software Interrupt Register 0x00000000 W Specifies the Software Interrupt Clear - Register R/W Specifies the Protection Enable Register 0x0 R/W Software Priority Mask Register 0xFFFF R/W Specifies the Vector Priority Register for 0xF Daisy Chain R/W Specifies the Vector Address 0 Register 0x00000000 R/W Specifies the Vector Address 1 Register 0x00000000 R/W Specifies the Vector Address 2 Register 0x00000000 R/W Specifies the Vector Address 3 Register 0x00000000 R/W Specifies the Vector Address 4 Register 0x00000000 R/W Specifies the Vector Address 5 Register 0x00000000 R/W Specifies the Vector Address 6 Register 0x00000000 R/W Specifies the Vector Address 7 Register 0x00000000 R/W Specifies the Vector Address 8 Register 0x00000000 R/W Specifies the Vector Address 9 Register 0x00000000 R/W Specifies the Vector Address 10 Register 0x00000000 R/W Specifies the Vector Address 11 Register 0x00000000 R/W Specifies the Vector Address 12 Register 0x00000000 R/W Specifies the Vector Address 13 Register 0x00000000 R/W Specifies the Vector Address 14 Register 0x00000000 R/W Specifies the Vector Address 15 Register 0x00000000 R/W Specifies the Vector Address 16 Register 0x00000000 R/W Specifies the Vector Address 17 Register 0x00000000 R/W Specifies the Vector Address 18 Register 0x00000000 1-8 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC0VECTADDR19 VIC0VECTADDR20 VIC0VECTADDR21 VIC0VECTADDR22 VIC0VECTADDR23 VIC0VECTADDR24 VIC0VECTADDR25 VIC0VECTADDR26 VIC0VECTADDR27 VIC0VECTADDR28 VIC0VECTADDR29 VIC0VECTADDR30 VIC0VECTADDR31 VIC0VECPRIORITY0 VIC0VECTPRIORITY1 VIC0VECTPRIORITY2 VIC0VECTPRIORITY3 VIC0VECTPRIORITY4 VIC0VECTPRIORITY5 VIC0VECTPRIORITY6 VIC0VECTPRIORITY7 VIC0VECTPRIORITY8 VIC0VECTPRIORITY9 VIC0VECTPRIORITY10 VIC0VECTPRIORITY11 VIC0VECTPRIORITY12 VIC0VECTPRIORITY13 VIC0VECTPRIORITY14 VIC0VECTPRIORITY15 VIC0VECTPRIORITY16 VIC0VECTPRIORITY17 VIC0VECTPRIORITY18 VIC0VECTPRIORITY19 VIC0VECTPRIORITY20 VIC0VECTPRIORITY21 VIC0VECTPRIORITY22 Address 0xF200_014C 0xF200_0150 0xF200_0154 0xF200_0158 0xF200_015C 0xF200_0160 0xF200_0164 0xF200_0168 0xF200_016C 0xF200_0170 0xF200_0174 0xF200_0178 0xF200_017C 0xF200_0200 0xF200_0204 0xF200_0208 0xF200_020C 0xF200_0210 0xF200_0214 0xF200_0218 0xF200_021C 0xF200_0220 0xF200_0224 0xF200_0228 0xF200_022C 0xF200_0230 0xF200_0234 0xF200_0238 0xF200_023C 0xF200_0240 0xF200_0244 0xF200_0248 0xF200_024C 0xF200_0250 0xF200_0254 0xF200_0258 R/W Description R/W Specifies the Vector Address 19 Register R/W Specifies the Vector Address 20 Register R/W Specifies the Vector Address 21 Register R/W Specifies the Vector Address 22 Register R/W Specifies the Vector Address 23 Register R/W Specifies the Vector Address 24 Register R/W Specifies the Vector Address 25 Register R/W Specifies the Vector Address 26 Register R/W Specifies the Vector Address 27 Register R/W Specifies the Vector Address 28 Register R/W Specifies the Vector Address 29 Register R/W Specifies the Vector Address 30 Register R/W Specifies the Vector Address 31 Register R/W Specifies the Vector Priority 0 Register R/W Specifies the Vector Priority 1 Register R/W Specifies the Vector Priority 2 Register R/W Specifies the Vector Priority 3 Register R/W Specifies the Vector Priority 4 Register R/W Specifies the Vector Priority 5 Register R/W Specifies the Vector Priority 6 Register R/W Specifies the Vector Priority 7 Register R/W Specifies the Vector Priority 8 Register R/W Specifies the Vector Priority 9 Register R/W Specifies the Vector Priority 10 Register R/W Specifies the Vector Priority 11 Register R/W Specifies the Vector Priority 12 Register R/W Specifies the Vector Priority 13 Register R/W Specifies the Vector Priority 14 Register R/W Specifies the Vector Priority 15 Register R/W Specifies the Vector Priority 16 Register R/W Specifies the Vector Priority 17 Register R/W Specifies the Vector Priority 18 Register R/W Specifies the Vector Priority 19 Register R/W Specifies the Vector Priority 20 Register R/W Specifies the Vector Priority 21 Register R/W Specifies the Vector Priority 22 Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 1-9 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC0VECTPRIORITY23 VIC0VECTPRIORITY24 VIC0VECTPRIORITY25 VIC0VECTPRIORITY26 VIC0VECTPRIORITY27 VIC0VECTPRIORITY28 VIC0VECTPRIORITY29 VIC0VECTPRIORITY30 VIC0VECTPRIORITY31 VIC0ADDRESS VIC0PERIPHID0 VIC0PERIPHID1 VIC0PERIPHID2 VIC0PERIPHID3 VIC0PCELLID0 VIC0PCELLID1 VIC0PCELLID2 VIC0PCELLID3 VIC1IRQSTATUS VIC1FIQSTATUS VIC1RAWINTR VIC1INTSELECT VIC1INTENABLE VIC1INTENCLEAR VIC1SOFTINT VIC1SOFTINTCLEAR VIC1PROTECTION VIC1SWPRIORITYMASK Address 0xF200_025C 0xF200_0260 0xF200_0264 0xF200_0268 0xF200_026C 0xF200_0270 0xF200_0274 0xF200_0278 0xF200_027C 0xF200_0F00 0xF200_0FE0 0xF200_0FE4 0xF200_0FE8 0xF200_0FEC 0xF200_0FF0 0xF200_0FF4 0xF200_0FF8 0xF200_0FFC 0xF210_0000 0xF210_0004 0xF210_0008 0xF210_000C 0xF210_0010 0xF210_0014 0xF210_0018 0xF210_001C 0xF210_0020 0xF210_0024 R/W Description R/W Specifies the Vector Priority 23 Register R/W Specifies the Vector Priority 24 Register R/W Specifies the Vector Priority 25 Register R/W Specifies the Vector Priority 26 Register R/W Specifies the Vector Priority 27 Register R/W Specifies the Vector Priority 28 Register R/W Specifies the Vector Priority 29 Register R/W Specifies the Vector Priority 30 Register R/W Specifies the Vector Priority 31 Register R/W Specifies the Vector Address Register R Specifies the Peripheral Identification Register bit 7:0 R Specifies the Peripheral Identification Register bit 15:9 R Specifies the Peripheral Identification Register bit 23:16 R Specifies the Peripheral Identification Register bit 31:24 R Specifies the PrimeCell Identification Register bit 7:0 R Specifies the PrimeCell Identification Register bit 15:9 R Specifies the PrimeCell Identification Register bit 23:16 R Specifies the PrimeCell Identification Register bit 31:24 R Specifies the IRQ Status Register R Specifies the FIQ Status Register R Specifies the Raw Interrupt Status Register R/W Specifies the Interrupt Select Register R/W Specifies the Interrupt Enable Register W Specifies the Interrupt Enable Clear Register R/W Specifies the Software Interrupt Register W Specifies the Software Interrupt Clear Register R/W Specifies the Protection Enable Register R/W Specifies the Software Priority Mask Register Reset Value 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0x00000000 0x92 0x11 0x04 0x00 0x0D 0xF0 0x05 0xB1 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 - 0x0 0xFFFF 1-10 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC1PRIORITYDAISY VIC1VECTADDR0 VIC1VECTADDR1 VIC1VECTADDR2 VIC1VECTADDR3 VIC1VECTADDR4 VIC1VECTADDR5 VIC1VECTADDR6 VIC1VECTADDR7 VIC1VECTADDR8 VIC1VECTADDR9 VIC1VECTADDR10 VIC1VECTADDR11 VIC1VECTADDR12 VIC1VECTADDR13 VIC1VECTADDR14 VIC1VECTADDR15 VIC1VECTADDR16 VIC1VECTADDR17 VIC1VECTADDR18 VIC1VECTADDR19 VIC1VECTADDR20 VIC1VECTADDR21 VIC1VECTADDR22 VIC1VECTADDR23 VIC1VECTADDR24 VIC1VECTADDR25 VIC1VECTADDR26 VIC1VECTADDR27 VIC1VECTADDR28 VIC1VECTADDR29 VIC1VECTADDR30 VIC1VECTADDR31 VIC1VECPRIORITY0 VIC1VECTPRIORITY1 Address 0xF210_0028 0xF210_0100 0xF210_0104 0xF210_0108 0xF210_010C 0xF210_0110 0xF210_0114 0xF210_0118 0xF210_011C 0xF210_0120 0xF210_0124 0xF210_0128 0xF210_012C 0xF210_0130 0xF210_0134 0xF210_0138 0xF210_013C 0xF210_0140 0xF210_0144 0xF210_0148 0xF210_014C 0xF210_0150 0xF210_0154 0xF210_0158 0xF210_015C 0xF210_0160 0xF210_0164 0xF210_0168 0xF210_016C 0xF210_0170 0xF210_0174 0xF210_0178 0xF210_017C 0xF210_0200 0xF210_0204 R/W Description R/W Specifies the Vector Priority Register for Daisy Chain R/W Specifies the Vector Address 0 Register R/W Specifies the Vector Address 1 Register R/W Specifies the Vector Address 2 Register R/W Specifies the Vector Address 3 Register R/W Specifies the Vector Address 4 Register R/W Specifies the Vector Address 5 Register R/W Specifies the Vector Address 6 Register R/W Specifies the Vector Address 7 Register R/W Specifies the Vector Address 8 Register R/W Specifies the Vector Address 9 Register R/W Specifies the Vector Address 10 Register R/W Specifies the Vector Address 11 Register R/W Specifies the Vector Address 12 Register R/W Specifies the Vector Address 13 Register R/W Specifies the Vector Address 14 Register R/W Specifies the Vector Address 15 Register R/W Specifies the Vector Address 16 Register R/W Specifies the Vector Address 17 Register R/W Specifies the Vector Address 18 Register R/W Specifies the Vector Address 19 Register R/W Specifies the Vector Address 20 Register R/W Specifies the Vector Address 21 Register R/W Specifies the Vector Address 22 Register R/W Specifies the Vector Address 23 Register R/W Specifies the Vector Address 24 Register R/W Specifies the Vector Address 25 Register R/W Specifies the Vector Address 26 Register R/W Specifies the Vector Address 27 Register R/W Specifies the Vector Address 28 Register R/W Specifies the Vector Address 29 Register R/W Specifies the Vector Address 30 Register R/W Specifies the Vector Address 31 Register R/W Specifies the Vector Priority 0 Register R/W Specifies the Vector Priority 1 Register Reset Value 0xF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xF 0xF 1-11 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC1VECTPRIORITY2 VIC1VECTPRIORITY3 VIC1VECTPRIORITY4 VIC1VECTPRIORITY5 VIC1VECTPRIORITY6 VIC1VECTPRIORITY7 VIC1VECTPRIORITY8 VIC1VECTPRIORITY9 VIC1VECTPRIORITY10 VIC1VECTPRIORITY11 VIC1VECTPRIORITY12 VIC1VECTPRIORITY13 VIC1VECTPRIORITY14 VIC1VECTPRIORITY15 VIC1VECTPRIORITY16 VIC1VECTPRIORITY17 VIC1VECTPRIORITY18 VIC1VECTPRIORITY19 VIC1VECTPRIORITY20 VIC1VECTPRIORITY21 VIC1VECTPRIORITY22 VIC1VECTPRIORITY23 VIC1VECTPRIORITY24 VIC1VECTPRIORITY25 VIC1VECTPRIORITY26 VIC1VECTPRIORITY27 VIC1VECTPRIORITY28 VIC1VECTPRIORITY29 VIC1VECTPRIORITY30 VIC1VECTPRIORITY31 VIC1ADDRESS VIC1PERIPHID0 VIC1PERIPHID1 VIC1PERIPHID2 Address 0xF210_0208 0xF210_020C 0xF210_0210 0xF210_0214 0xF210_0218 0xF210_021C 0xF210_0220 0xF210_0224 0xF210_0228 0xF210_022C 0xF210_0230 0xF210_0234 0xF210_0238 0xF210_023C 0xF210_0240 0xF210_0244 0xF210_0248 0xF210_024C 0xF210_0250 0xF210_0254 0xF210_0258 0xF210_025C 0xF210_0260 0xF210_0264 0xF210_0268 0xF210_026C 0xF210_0270 0xF210_0274 0xF210_0278 0xF210_027C 0xF210_0F00 0xF210_0FE0 0xF210_0FE4 0xF210_0FE8 R/W Description R/W Specifies the Vector Priority 2 Register R/W Specifies the Vector Priority 3 Register R/W Specifies the Vector Priority 4 Register R/W Specifies the Vector Priority 5 Register R/W Specifies the Vector Priority 6 Register R/W Specifies the Vector Priority 7 Register R/W Specifies the Vector Priority 8 Register R/W Specifies the Vector Priority 9 Register R/W Specifies the Vector Priority 10 Register R/W Specifies the Vector Priority 11 Register R/W Specifies the Vector Priority 12 Register R/W Specifies the Vector Priority 13 Register R/W Specifies the Vector Priority 14 Register R/W Specifies the Vector Priority 15 Register R/W Specifies the Vector Priority 16 Register R/W Specifies the Vector Priority 17 Register R/W Specifies the Vector Priority 18 Register R/W Specifies the Vector Priority 19 Register R/W Specifies the Vector Priority 20 Register R/W Specifies the Vector Priority 21 Register R/W Specifies the Vector Priority 22 Register R/W Specifies the Vector Priority 23 Register R/W Specifies the Vector Priority 24 Register R/W Specifies the Vector Priority 25 Register R/W Specifies the Vector Priority 26 Register R/W Specifies the Vector Priority 27 Register R/W Specifies the Vector Priority 28 Register R/W Specifies the Vector Priority 29 Register R/W Specifies the Vector Priority 30 Register R/W Specifies the Vector Priority 31 Register R/W Specifies the Vector Address Register R Specifies the Peripheral Identification Register bit 7:0 R Specifies the Peripheral Identification Register bit 15:9 R Specifies the Peripheral Identification Register bit 23:16 Reset Value 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0x00000000 0x92 0x11 0x04 1-12 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC1PERIPHID3 VIC1PCELLID0 VIC1PCELLID1 VIC1PCELLID2 VIC1PCELLID3 VIC2IRQSTATUS VIC2FIQSTATUS VIC2RAWINTR VIC2INTSELECT VIC2INTENABLE VIC2INTENCLEAR VIC2SOFTINT VIC2SOFTINTCLEAR VIC2PROTECTION VIC2SWPRIORITYMASK VIC2PRIORITYDAISY VIC2VECTADDR0 VIC2VECTADDR1 VIC2VECTADDR2 VIC2VECTADDR3 VIC2VECTADDR4 VIC2VECTADDR5 VIC2VECTADDR6 VIC2VECTADDR7 VIC2VECTADDR8 VIC2VECTADDR9 VIC2VECTADDR10 VIC2VECTADDR11 VIC2VECTADDR12 Address 0xF210_0FEC 0xF210_0FF0 0xF210_0FF4 0xF210_0FF8 0xF210_0FFC 0xF220_0000 0xF220_0004 0xF220_0008 0xF220_000C 0xF220_0010 0xF220_0014 0xF220_0018 0xF220_001C 0xF220_0020 0xF220_0024 0xF220_0028 0xF220_0100 0xF220_0104 0xF220_0108 0xF220_010C 0xF220_0110 0xF220_0114 0xF220_0118 0xF220_011C 0xF220_0120 0xF220_0124 0xF220_0128 0xF220_012C 0xF220_0130 R/W Description R Specifies the Peripheral Identification Register bit 31:24 R Specifies the PrimeCell Identification Register bit 7:0 R Specifies the PrimeCell Identification Register bit 15:9 R Specifies the PrimeCell Identification Register bit 23:16 R Specifies the PrimeCell Identification Register bit 31:24 R Specifies the IRQ Status Register R Specifies the FIQ Status Register R Specifies the Raw Interrupt Status Register R/W Specifies the Interrupt Select Register R/W Specifies the Interrupt Enable Register W Specifies the Interrupt Enable Clear Register R/W Specifies the Software Interrupt Register W Specifies the Software Interrupt Clear Register R/W Specifies the Protection Enable Register R/W Specifies the Software Priority Mask Register R/W Specifies the Vector Priority Register for Daisy Chain R/W Specifies the Vector Address 0 Register R/W Specifies the Vector Address 1 Register R/W Specifies the Vector Address 2 Register R/W Specifies the Vector Address 3 Register R/W Specifies the Vector Address 4 Register R/W Specifies the Vector Address 5 Register R/W Specifies the Vector Address 6 Register R/W Specifies the Vector Address 7 Register R/W Specifies the Vector Address 8 Register R/W Specifies the Vector Address 9 Register R/W Specifies the Vector Address 10 Register R/W Specifies the Vector Address 11 Register R/W Specifies the Vector Address 12 Register Reset Value 0x00 0x0D 0xF0 0x05 0xB1 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 - 0x0 0xFFFF 0xF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 1-13 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC2VECTADDR13 VIC2VECTADDR14 VIC2VECTADDR15 VIC2VECTADDR16 VIC2VECTADDR17 VIC2VECTADDR18 VIC2VECTADDR19 VIC2VECTADDR20 VIC2VECTADDR21 VIC2VECTADDR22 VIC2VECTADDR23 VIC2VECTADDR24 VIC2VECTADDR25 VIC2VECTADDR26 VIC2VECTADDR27 VIC2VECTADDR28 VIC2VECTADDR29 VIC2VECTADDR30 VIC2VECTADDR31 VIC2VECPRIORITY0 VIC2VECTPRIORITY1 VIC2VECTPRIORITY2 VIC2VECTPRIORITY3 VIC2VECTPRIORITY4 VIC2VECTPRIORITY5 VIC2VECTPRIORITY6 VIC2VECTPRIORITY7 VIC2VECTPRIORITY8 VIC2VECTPRIORITY9 VIC2VECTPRIORITY10 VIC2VECTPRIORITY11 VIC2VECTPRIORITY12 VIC2VECTPRIORITY13 VIC2VECTPRIORITY14 VIC2VECTPRIORITY15 VIC2VECTPRIORITY16 Address 0xF220_0134 0xF220_0138 0xF220_013C 0xF220_0140 0xF220_0144 0xF220_0148 0xF220_014C 0xF220_0150 0xF220_0154 0xF220_0158 0xF220_015C 0xF220_0160 0xF220_0164 0xF220_0168 0xF220_016C 0xF220_0170 0xF220_0174 0xF220_0178 0xF220_017C 0xF220_0200 0xF220_0204 0xF220_0208 0xF220_020C 0xF220_0210 0xF220_0214 0xF220_0218 0xF220_021C 0xF220_0220 0xF220_0224 0xF220_0228 0xF220_022C 0xF220_0230 0xF220_0234 0xF220_0238 0xF220_023C 0xF220_0240 R/W Description R/W Specifies the Vector Address 13 Register R/W Specifies the Vector Address 14 Register R/W Specifies the Vector Address 15 Register R/W Specifies the Vector Address 16 Register R/W Specifies the Vector Address 17 Register R/W Specifies the Vector Address 18 Register R/W Specifies the Vector Address 19 Register R/W Specifies the Vector Address 20 Register R/W Specifies the Vector Address 21 Register R/W Specifies the Vector Address 22 Register R/W Specifies the Vector Address 23 Register R/W Specifies the Vector Address 24 Register R/W Specifies the Vector Address 25 Register R/W Specifies the Vector Address 26 Register R/W Specifies the Vector Address 27 Register R/W Specifies the Vector Address 28 Register R/W Specifies the Vector Address 29 Register R/W Specifies the Vector Address 30 Register R/W Specifies the Vector Address 31 Register R/W Specifies the Vector Priority 0 Register R/W Specifies the Vector Priority 1 Register R/W Specifies the Vector Priority 2 Register R/W Specifies the Vector Priority 3 Register R/W Specifies the Vector Priority 4 Register R/W Specifies the Vector Priority 5 Register R/W Specifies the Vector Priority 6 Register R/W Specifies the Vector Priority 7 Register R/W Specifies the Vector Priority 8 Register R/W Specifies the Vector Priority 9 Register R/W Specifies the Vector Priority 10 Register R/W Specifies the Vector Priority 11 Register R/W Specifies the Vector Priority 12 Register R/W Specifies the Vector Priority 13 Register R/W Specifies the Vector Priority 14 Register R/W Specifies the Vector Priority 15 Register R/W Specifies the Vector Priority 16 Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 1-14 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC2VECTPRIORITY17 VIC2VECTPRIORITY18 VIC2VECTPRIORITY19 VIC2VECTPRIORITY20 VIC2VECTPRIORITY21 VIC2VECTPRIORITY22 VIC2VECTPRIORITY23 VIC2VECTPRIORITY24 VIC2VECTPRIORITY25 VIC2VECTPRIORITY26 VIC2VECTPRIORITY27 VIC2VECTPRIORITY28 VIC2VECTPRIORITY29 VIC2VECTPRIORITY30 VIC2VECTPRIORITY31 VIC2ADDRESS VIC2PERIPHID0 VIC2PERIPHID1 VIC2PERIPHID2 VIC2PERIPHID3 VIC2PCELLID0 VIC2PCELLID1 VIC2PCELLID2 VIC2PCELLID3 VIC3IRQSTATUS VIC3FIQSTATUS VIC3RAWINTR VIC3INTSELECT VIC3INTENABLE VIC3INTENCLEAR Address R/W Description 0xF220_0244 R/W Specifies the Vector Priority 17 Register 0xF220_0248 R/W Specifies the Vector Priority 18 Register 0xF220_024C R/W Specifies the Vector Priority 19 Register 0xF220_0250 R/W Specifies the Vector Priority 20 Register 0xF220_0254 R/W Specifies the Vector Priority 21 Register 0xF220_0258 R/W Specifies the Vector Priority 22 Register 0xF220_025C R/W Specifies the Vector Priority 23 Register 0xF220_0260 R/W Specifies the Vector Priority 24 Register 0xF220_0264 R/W Specifies the Vector Priority 25 Register 0xF220_0268 R/W Specifies the Vector Priority 26 Register 0xF220_026C R/W Specifies the Vector Priority 27 Register 0xF220_0270 R/W Specifies the Vector Priority 28 Register 0xF220_0274 R/W Specifies the Vector Priority 29 Register 0xF220_0278 R/W Specifies the Vector Priority 30 Register 0xF220_027C R/W Specifies the Vector Priority 31 Register 0xF220_0F00 R/W Specifies the Vector Address Register 0xF220_0FE0 R Specifies the Peripheral Identification Register bit 7:0 0xF220_0FE4 R Specifies the Peripheral Identification Register bit 15:9 0xF220_0FE8 R Specifies the Peripheral Identification Register bit 23:16 0xF220_0FEC R Specifies the Peripheral Identification Register bit 31:24 0xF220_0FF0 R Specifies the PrimeCell Identification Register bit 7:0 0xF220_0FF4 R Specifies the PrimeCell Identification Register bit 15:9 0xF220_0FF8 R Specifies the PrimeCell Identification Register bit 23:16 0xF220_0FFC R Specifies the PrimeCell Identification Register bit 31:24 0xF230_0000 R Specifies the IRQ Status Register 0xF230_0004 R Specifies the FIQ Status Register 0xF230_0008 R Specifies the Raw Interrupt Status Register 0xF230_000C R/W Specifies the Interrupt Select Register 0xF230_0010 R/W Specifies the Interrupt Enable Register 0xF230_0014 W Specifies the Interrupt Enable Clear Reset Value 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0x00000000 0x92 0x11 0x04 0x00 0x0D 0xF0 0x05 0xB1 0x00000000 0x00000000 - 0x00000000 0x00000000 - 1-15 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC3SOFTINT VIC3SOFTINTCLEAR VIC3PROTECTION VIC3SWPRIORITYMASK VIC3PRIORITYDAISY VIC3VECTADDR0 VIC3VECTADDR1 VIC3VECTADDR2 VIC3VECTADDR3 VIC3VECTADDR4 VIC3VECTADDR5 VIC3VECTADDR6 VIC3VECTADDR7 VIC3VECTADDR8 VIC3VECTADDR9 VIC3VECTADDR10 VIC3VECTADDR11 VIC3VECTADDR12 VIC3VECTADDR13 VIC3VECTADDR14 VIC3VECTADDR15 VIC3VECTADDR16 VIC3VECTADDR17 VIC3VECTADDR18 VIC3VECTADDR19 VIC3VECTADDR20 VIC3VECTADDR21 VIC3VECTADDR22 VIC3VECTADDR23 VIC3VECTADDR24 VIC3VECTADDR25 VIC3VECTADDR26 VIC3VECTADDR27 Address 0xF230_0018 0xF230_001C 0xF230_0020 0xF230_0024 0xF230_0028 0xF230_0100 0xF230_0104 0xF230_0108 0xF230_010C 0xF230_0110 0xF230_0114 0xF230_0118 0xF230_011C 0xF230_0120 0xF230_0124 0xF230_0128 0xF230_012C 0xF230_0130 0xF230_0134 0xF230_0138 0xF230_013C 0xF230_0140 0xF230_0144 0xF230_0148 0xF230_014C 0xF230_0150 0xF230_0154 0xF230_0158 0xF230_015C 0xF230_0160 0xF230_0164 0xF230_0168 0xF230_016C R/W Register Description Reset Value R/W Specifies the Software Interrupt Register 0x00000000 W Specifies the Software Interrupt Clear - Register R/W Specifies the Protection Enable Register 0x0 R/W Specifies the Software Priority Mask Register 0xFFFF R/W Specifies the Vector Priority Register for 0xF Daisy Chain R/W Specifies the Vector Address 0 Register 0x00000000 R/W Specifies the Vector Address 1 Register 0x00000000 R/W Specifies the Vector Address 2 Register 0x00000000 R/W Specifies the Vector Address 3 Register 0x00000000 R/W Specifies the Vector Address 4 Register 0x00000000 R/W Specifies the Vector Address 5 Register 0x00000000 R/W Specifies the Vector Address 6 Register 0x00000000 R/W Specifies the Vector Address 7 Register 0x00000000 R/W Specifies the Vector Address 8 Register 0x00000000 R/W Specifies the Vector Address 9 Register 0x00000000 R/W Specifies the Vector Address 10 Register 0x00000000 R/W Specifies the Vector Address 11 Register 0x00000000 R/W Specifies the Vector Address 12 Register 0x00000000 R/W Specifies the Vector Address 13 Register 0x00000000 R/W Specifies the Vector Address 14 Register 0x00000000 R/W Specifies the Vector Address 15 Register 0x00000000 R/W Specifies the Vector Address 16 Register 0x00000000 R/W Specifies the Vector Address 17 Register 0x00000000 R/W Specifies the Vector Address 18 Register 0x00000000 R/W Specifies the Vector Address 19 Register 0x00000000 R/W Specifies the Vector Address 20 Register 0x00000000 R/W Specifies the Vector Address 21 Register 0x00000000 R/W Specifies the Vector Address 22 Register 0x00000000 R/W Specifies the Vector Address 23 Register 0x00000000 R/W Specifies the Vector Address 24 Register 0x00000000 R/W Specifies the Vector Address 25 Register 0x00000000 R/W Specifies the Vector Address 26 Register 0x00000000 R/W Specifies the Vector Address 27 Register 0x00000000 1-16 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER Register VIC3VECTADDR28 VIC3VECTADDR29 VIC3VECTADDR30 VIC3VECTADDR31 VIC3VECPRIORITY0 VIC3VECTPRIORITY1 VIC3VECTPRIORITY2 VIC3VECTPRIORITY3 VIC3VECTPRIORITY4 VIC3VECTPRIORITY5 VIC3VECTPRIORITY6 VIC3VECTPRIORITY7 VIC3VECTPRIORITY8 VIC3VECTPRIORITY9 VIC3VECTPRIORITY10 VIC3VECTPRIORITY11 VIC3VECTPRIORITY12 VIC3VECTPRIORITY13 VIC3VECTPRIORITY14 VIC3VECTPRIORITY15 VIC3VECTPRIORITY16 VIC3VECTPRIORITY17 VIC3VECTPRIORITY18 VIC3VECTPRIORITY19 VIC3VECTPRIORITY20 VIC3VECTPRIORITY21 VIC3VECTPRIORITY22 VIC3VECTPRIORITY23 VIC3VECTPRIORITY24 VIC3VECTPRIORITY25 VIC3VECTPRIORITY26 VIC3VECTPRIORITY27 VIC3VECTPRIORITY28 VIC3VECTPRIORITY29 VIC3VECTPRIORITY30 VIC3VECTPRIORITY31 Address 0xF230_0170 0xF230_0174 0xF230_0178 0xF230_017C 0xF230_0200 0xF230_0204 0xF230_0208 0xF230_020C 0xF230_0210 0xF230_0214 0xF230_0218 0xF230_021C 0xF230_0220 0xF230_0224 0xF230_0228 0xF230_022C 0xF230_0230 0xF230_0234 0xF230_0238 0xF230_023C 0xF230_0240 0xF230_0244 0xF230_0248 0xF230_024C 0xF230_0250 0xF230_0254 0xF230_0258 0xF230_025C 0xF230_0260 0xF230_0264 0xF230_0268 0xF230_026C 0xF230_0270 0xF230_0274 0xF230_0278 0xF230_027C R/W Description R/W Specifies the Vector Address 28 Register R/W Specifies the Vector Address 29 Register R/W Specifies the Vector Address 30 Register R/W Specifies the Vector Address 31 Register R/W Specifies the Vector Priority 0 Register R/W Specifies the Vector Priority 1 Register R/W Specifies the Vector Priority 2 Register R/W Specifies the Vector Priority 3 Register R/W Specifies the Vector Priority 4 Register R/W Specifies the Vector Priority 5 Register R/W Specifies the Vector Priority 6 Register R/W Specifies the Vector Priority 7 Register R/W Specifies the Vector Priority 8 Register R/W Specifies the Vector Priority 9 Register R/W Specifies the Vector Priority 10 Register R/W Specifies the Vector Priority 11 Register R/W Specifies the Vector Priority 12 Register R/W Specifies the Vector Priority 13 Register R/W Specifies the Vector Priority 14 Register R/W Specifies the Vector Priority 15 Register R/W Specifies the Vector Priority 16 Register R/W Specifies the Vector Priority 17 Register R/W Specifies the Vector Priority 18 Register R/W Specifies the Vector Priority 19 Register R/W Specifies the Vector Priority 20 Register R/W Specifies the Vector Priority 21 Register R/W Specifies the Vector Priority 22 Register R/W Specifies the Vector Priority 23 Register R/W Specifies the Vector Priority 24 Register R/W Specifies the Vector Priority 25 Register R/W Specifies the Vector Priority 26 Register R/W Specifies the Vector Priority 27 Register R/W Specifies the Vector Priority 28 Register R/W Specifies the Vector Priority 29 Register R/W Specifies the Vector Priority 30 Register R/W Specifies the Vector Priority 31 Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 1-17 S5PV210_UM Register VIC3ADDRESS VIC3PERIPHID0 VIC3PERIPHID1 VIC3PERIPHID2 VIC3PERIPHID3 VIC3PCELLID0 VIC3PCELLID1 VIC3PCELLID2 VIC3PCELLID3 TZIC0FIQStatus TZIC0RawIntr TZIC0IntSelect TZIC0FIQEnable TZIC0FIQENClear TZIC0FIQBypass TZIC0Protection TZIC0Lock TZIC0LockStatus TZIC0PeriphID0 TZIC0PeriphID1 TZIC0PeriphID2 TZIC0PeriphID3 TZIC0PCellID0 TZIC0PCellID1 TZIC0PCellID2 TZIC0PCellID3 TZIC1FIQStatus TZIC1RawIntr 1 VECTORED INTERRUPT CONTROLLER Address R/W Description 0xF230_0F00 R/W Specifies the Vector Address Register 0xF230_0FE0 R Specifies the Peripheral Identification Register bit 7:0 0xF230_0FE4 R Specifies the Peripheral Identification Register bit 15:9 0xF230_0FE8 R Specifies the Peripheral Identification Register bit 23:16 0xF230_0FEC R Specifies the Peripheral Identification Register bit 31:24 0xF230_0FF0 R Specifies the PrimeCell Identification Register bit 7:0 0xF230_0FF4 R Specifies the PrimeCell Identification Register bit 15:9 0xF230_0FF8 R Specifies the PrimeCell Identification Register bit 23:16 0xF230_0FFC R Specifies the PrimeCell Identification Register bit 31:24 0xF280_0000 R Specifies the FIQ Status Register 0xF280_0004 R Specifies the Raw Interrupt Status Register 0xF280_0008 R/W Specifies the Interrupt Select Register 0xF280_000C R/W Specifies the FIQ Enable Register 0xF280_0010 W Specifies the FIQ Enable Clear Register 0xF280_0014 R/W Specifies the FIQ Bypass Register 0xF280_0018 R/W Specifies the Protection Register 0xF280_001C W Specifies the Lock Enable Register 0xF280_0020 R Specifies the Lock Status Register 0xF280_0FE0 R Specifies the Peripheral Identification Registers 0xF280_0FE4 R 0xF280_0FE8 R 0xF280_0FEC R 0xF280_0FF0 R Specifies the Identification Registers 0xF280_0FF4 R 0xF280_0FF8 R 0xF280_0FFC R 0xF290_0000 R Specifies the FIQ Status Register 0xF290_0004 R Specifies the Raw Interrupt Status Register Reset Value 0x00000000 0x92 0x11 0x04 0x00 0x0D 0xF0 0x05 0xB1 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000090 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 0x00000000 - 1-18 S5PV210_UM Register TZIC1IntSelect TZIC1FIQEnable TZIC1FIQENClear TZIC1FIQBypass TZIC1Protection TZIC1Lock TZIC1LockStatus TZIC1PeriphID0 TZIC1PeriphID1 TZIC1PeriphID2 TZIC1PeriphID3 TZIC1PCellID0 TZIC1PCellID1 TZIC1PCellID2 TZIC1PCellID3 TZIC2FIQStatus TZIC2RawIntr TZIC2IntSelect TZIC2FIQEnable TZIC2FIQENClear TZIC2FIQBypass TZIC2Protection TZIC2Lock TZIC2LockStatus TZIC2PeriphID0 TZIC2PeriphID1 TZIC2PeriphID2 TZIC2PeriphID3 TZIC2PCellID0 TZIC2PCellID1 TZIC2PCellID2 TZIC2PCellID3 TZIC3FIQStatus TZIC3RawIntr 1 VECTORED INTERRUPT CONTROLLER Address R/W Description 0xF290_0008 R/W Specifies the Interrupt Select Register 0xF290_000C R/W Specifies the FIQ Enable Register 0xF290_0010 W Specifies the FIQ Enable Clear Register 0xF290_0014 R/W Specifies the FIQ Bypass Register 0xF290_0018 R/W Specifies the Protection Register 0xF290_001C W Specifies the Lock Enable Register 0xF290_0020 R Specifies the Lock Status Register 0xF290_0FE0 R Specifies the Peripheral Identification Registers 0xF290_0FE4 R 0xF290_0FE8 R 0xF290_0FEC R 0xF290_0FF0 R Specifies the Identification Registers 0xF290_0FF4 R 0xF290_0FF8 R 0xF290_0FFC R 0xF2A0_0000 R Specifies the FIQ Status Register 0xF2A0_0004 R Specifies the Raw Interrupt Status Register 0xF2A0_0008 R/W Specifies the Interrupt Select Register 0xF2A0_000C R/W Specifies the FIQ Enable Register 0xF2A0_0010 W Specifies the FIQ Enable Clear Register 0xF2A0_0014 R/W Specifies the FIQ Bypass Register 0xF2A0_0018 R/W Specifies the Protection Register 0xF2A0_001C W Specifies the Lock Enable Register 0xF2A0_0020 R Specifies the Lock Status Register 0xF2A0_0FE0 R Specifies the Peripheral Identification Registers 0xF2A0_0FE4 R 0xF2A0_0FE8 R 0xF2A0_0FEC R 0xF2A0_0FF0 R Specifies the Identification Registers 0xF2A0_0FF4 R 0xF2A0_0FF8 R 0xF2A0_0FFC R 0xF2B0_0000 R Specifies the FIQ Status Register 0xF2B0_0004 R Specifies the Raw Interrupt Status Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000090 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000090 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 0x00000000 - 1-19 S5PV210_UM Register TZIC3IntSelect TZIC3FIQEnable TZIC3FIQENClear TZIC3FIQBypass TZIC3Protection TZIC3Lock TZIC3LockStatus TZIC3PeriphID0 TZIC3PeriphID1 TZIC3PeriphID2 TZIC3PeriphID3 TZIC3PCellID0 TZIC3PCellID1 TZIC3PCellID2 TZIC3PCellID3 1 VECTORED INTERRUPT CONTROLLER Address R/W Register Description 0xF2B0_0008 R/W Specifies the Interrupt Select Register 0xF2B0_000C R/W Specifies the FIQ Enable Register 0xF2B0_0010 W Specifies the FIQ Enable Clear Register 0xF2B0_0014 R/W Specifies the FIQ Bypass Register 0xF2B0_0018 R/W Specifies the Protection Register 0xF2B0_001C W Specifies the Lock Enable Register 0xF2B0_0020 R Specifies the Lock Status Register 0xF2B0_0FE0 R Specifies the Peripheral Identification Registers 0xF2B0_0FE4 R 0xF2B0_0FE8 R 0xF2B0_0FEC R 0xF2B0_0FF0 R Specifies the Identification Registers 0xF2B0_0FF4 R 0xF2B0_0FF8 R 0xF2B0_0FFC R Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x00000090 0x00000018 0x00000004 0x00000000 0x0000000D 0x000000F0 0x00000005 0x000000B1 1-20 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.1 IRQ Status Register (VICIRQSTATUS, R, Address=0xF200_0000, 0xF210_0000, 0xF220_0000, 0XF230_0000) VICIRQSTATUS IRQStatus Bit [31:0] Description Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = Interrupt is inactive 1 = Interrupt is active. There is one bit of the register for each interrupt source. Initial State 0x00000000 1.4.1.2 FIQ Status Register (VICFIQSTATUS, R, Address=0xF200_0004, 0xF210_0004, 0xF220_0004, 0xF230_0004) VICFIQSTATUS FIQStatus Bit [31:0] Description Shows the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = Interrupt is inactive 1 = Interrupt is active. There is one bit of the register for each interrupt source. Initial State 0x00000000 1.4.1.3 Raw Interrupt Status Register (VICRAWINTR, R, Address=0xF200_0008, 0xF210_0008, 0xF220_0008, 0xF230_0008) VICRAWINTR RawInterrupt Bit [31:0] Description Shows the status of the FIQ interrupts before masking by the VICINTENABLE and VICINTSELECT Registers: 0 = Interrupt is inactive before masking 1 = Interrupt is active before masking Because this register provides a direct view of the raw interrupt inputs, the reset value is unknown. There is one bit of the register for each interrupt source. Initial State - 1.4.1.4 Interrupt Select Register (VICINTSELECT, R/W, Address=0xF200_000C, 0xF210_000C, 0xF220_000C, 0xF230_000C) VICINTSELECT IntSelect Bit [31:0] Description Selects interrupt type for interrupt request: 0 = IRQ interrupt 1 = FIQ interrupt There is one bit of the register for each interrupt source. Initial State 0x00000000 1-21 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.5 Interrupt Enable Register (VICINTENABLE, R/W, Address=0xF200_0010, 0xF210_0010, 0xF220_0010, 0xF230_0010) VICINTENABLE IntEnable Bit Description [31:0] Enables the interrupt request lines, which allows the interrupts to reach the processor. Read: 0 = Disables Interrupt 1 = Enables Interrupt Use this register to enable interrupt. The VICINTENCLEAR Register must be used to disable the interrupt enable. Write: 0 = No effect 1 = Enables Interrupt. On reset, all interrupts are disabled. There is one bit of the register for each interrupt source. Initial State 0x00000000 1.4.1.6 Interrupt Enable Clear (VICINTENCLEAR, W, Address=0xF200_0014, 0xF210_0014, 0xF220_0014, 0xF230_0014) VICINTENCLEAR IntEnable Clear Bit [31:0] Description Clears corresponding bits in the VICINTENABLE Register: 0 = No effect 1 = Disables Interrupt in VICINTENABLE Register. There is one bit of the register for each interrupt source. Initial State - 1.4.1.7 Software Interrupt Register (VICSOFTINT, R/W, Address=0xF200_0018, 0xF210_0018, 0xF220_0018, 0xF230_0018) VICSOFTINT SoftInt Bit [31:0] Description Setting a bit HIGH generates a software interrupt for the selected source before interrupt masking. Read: 0 = Software interrupt inactive 1 = Software interrupt active Write: 0 = No effect 1 = Enables Software interrupt There is one bit of the register for each interrupt source. Initial State 0x00000000 1-22 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.8 Software Interrupt Clear Register (VICSOFTINTCLEAR, W, Address=0xF200_001C, 0xF210_001C, 0xF220_001C, 0xF230_001C) VICSOFTINTCLEAR SoftIntClear Bit [31:0] Description Clears corresponding bits in the VICSOFTINT Register: 0 = No effect 1 = Disables Software interrupt in the VICSOFTINT Register. There is one bit of the register for each interrupt source. Initial State - 1.4.1.9 Protection Enable Register (VICPROTECTION, R/W, Address=0xF200_0020, 0xF210_0020, 0xF220_0020, 0xF230_0020) VICPROTECTION Reserved Protection Bit [31:1] [0] Description Reserved, read as 0, do not modify. Enables or disables protected register access: 0 = Disables Protection mode 1 = Enables Protection mode. If enabled, only privileged mode accesses (reads and writes) can access the interrupt controller registers, that is, if HPROT[1] is set HIGH for the current transfer. If disabled, both user mode and privileged mode can access the registers. This register can only be accessed in privileged mode, even if protection mode is disabled. Initial State 0x0 0x0 1.4.1.10 Vector Address Register (VICADDRESS, R/W, Address=0xF200_0F00, 0xF210_0F00, 0xF220_0F00, 0xF230_0F00) VICADDRESS VectAddr Bit [31:0] Description Contains the address of the currently active ISR, with reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced. A read must be performed while there is an active interrupt. A write of any value to this register clears the current interrupt. A write must only be performed at the end of an interrupt service routine. Initial State 0x00000000 1-23 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.11 Software Priority Mask Register (VICSWPRIORITYMASK, R/W, Address=0xF200_0024, 0xF210_0024, 0xF220_0024, 0xF230_0024) VICSWPRIORITYMASK Bit Description Reserved [31:16] Reserved, read as 0, do not modify SWPriorityMask [15:0] Controls software masking of the 16 interrupt priority levels: 0 = Interrupt priority level is masked 1 = Interrupt priority level is not masked Each bit of the register is applied to each of the 16 interrupt priority levels. Initial State 0x0 0xFFFF 1.4.1.12 Vector Address Registers (VICVECTADDR[0-31], R/W, Address=0xF200_0100~017C, 0xF210_0100~017C, 0xF220_0100~017C, 0xF230_0100~017C) VICVECTADDR[0-31] VectorAddr 0-31 Bit Description [31:0] Contains ISR vector addresses. Initial State 0x00000000 1.4.1.13 Vector Priority Registers (VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY, R/W, Address=0xF200_0200~027C, 0xF210_0200~027C, 0xF220_0200~027C, 0xF230_0200~027C) VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Reserved VectPriority Bit Description Initial State [31:4] Reserved, read as 0, do not modify. 0x0 [3:0] Selects vectored interrupt priority level. You can select 0xF any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0-15. 1.4.1.14 VICPERIPHID0 Register (VICPERIPHID0, R, Address=0xF200_0FE0, 0xF210_0FE0, 0xF220_0FE0, 0xF230_0FE0) VICPERIPHID0 Partnumber0 Bit [31:8] [7:0] Description Reserved, read as 0, do not modify. These bits read back as 0x92 Initial State 0x0 0x92 1-24 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.15 VICPERIPHID1 Register (VICPERIPHID1, R, Address=0xF200_0FE4, 0xF210_0FE4, 0xF220_0FE4, 0xF230_0FE4) VICPERIPHID1 Designer0 Partnumber1 Bit [31:8] [7:4] [3:0] Description Reserved, read as 0, do not modify. These bits read back as 0x1. These bits read back as 0x1. Initial State 0x0 0x1 0x1 1.4.1.16 VICPERIPHID2 Register (VICPERIPHID2, R, Address=0xF200_0FE8, 0xF210_0FE8, 0xF220_0FE8, 0xF230_0FE8) VICPERIPHID2 Revision Designer1 Bit [31:8] [7:4] [3:0] Description Reserved, read as 0, do not modify. These bits read back as the revision number, which can be between 0 and 15. These bits read back as 0x4. Initial State 0x0 0x0 0x4 1.4.1.17 VICPERIPHID3 Register (VICPERIPHID3, R, Address=0xF200_0FEC, 0xF210_0FEC, 0xF220_0FEC, 0xF230_0FEC) VICPERIPHID3 Configuration Configuration Bit [31:8] [7:2] [1:0] Description Reserved, read as 0, do not modify. These bits read back as 0x0. Indicates the number of interrupts supported: 00 = 32 (default) 01 = 64 10 = 128 11 = 256 Initial State 0x0 0x0 0x0 1.4.1.18 VICPCELLID0 Register (VICPCELLID0, R, Address=0xF200_0FF0, 0xF210_0FF0, 0xF220_0FF0, 0xF230_0FF0) VICPCELLID0 VICPCellID0 Bit [31:8] [7:0] Description Reserved, read as 0, do not modify. These bits read back as 0x0D. Initial State 0x0 0x0D 1-25 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.19 VICPCELLID1 Register (VICPCELLID1, R, Address=0xF200_0FF4, 0xF210_0FF4, 0xF220_0FF4, 0xF230_0FF4) VICPCELLID1 VICPCellID1 Bit [31:8] [7:0] Description Reserved, read as 0, do not modify. These bits read back as 0xF0. Initial State 0x0 0xF0 1.4.1.20 VICPCELLID2 Register (VICPCELLID2, R, Address=0xF200_0FF8, 0xF210_0FF8, 0xF220_0FF8, 0xF230_0FF8) VICPCELLID2 VICPCellID2 Bit [31:8] [7:0] Description Reserved, read as 0, do not modify. These bits read back as 0x05. Initial State 0x0 0x05 1.4.1.21 VICPCELLID3 Register (VICPCELLID3, R, Address=0xF200_0FFC, 0xF210_0FFC, 0xF220_0FFC, 0xF230_0FFC) VICPCELLID3 VICPCellID3 Bit [31:8] [7:0] Description Reserved, read as 0, do not modify. These bits read back as 0xB1. Initial State 0x0 0xB1 1.4.1.22 FIQ Status Register (TZICFIQStatus, R, Address=0xF280_0000, 0xF290_0000, 0xF2A0_0000, 0xF2B0_0000) TZICFIQStatus FIQStatus Bit [31:0] Description Shows the status of the interrupts after masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers. A HIGH bit indicates that the interrupt is active, and generates an nFIQ interrupt to the processor. Initial State 0x00000000 1.4.1.23 Raw Interrupt Status Register (TZICRawIntr, R, Address=0xF280_0004, 0xF290_0004, 0xF2A0_0004, 0xF2B0_0004) TZICRawIntr RawIntr Bit [31:0] Description Shows the status of the interrupts before masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers. A HIGH bit indicates that the interrupt is active before masking. Initial State - 1-26 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.24 Interrupt select register (TZICIntSelect, R/W, Address=0xF280_0008, 0xF290_0008, 0xF2A0_0008, 0xF2B0_0008) TZICRawIntr IntSelect Bit [31:0] Description Selects whether the interrupt source generates an FIQ interrupt or passes straight through to TZICIRQOUT. 0 = Interrupt passes through to TZICIRQOUT 1 = Interrupt is available for FIQ generation Initial State 0x00000000 1.4.1.25 FIQ Enable Register (TZICFIQEnable, R/W, Address=0xF280_000C, 0xF290_000C, 0xF2A0_000C, 0xF2B0_000C) TZICFIQEnable FIQEnable Bit [31:0] Description Enables the FIQ-selected interrupt lines, allowing the interrupts to reach the processor. Read: 0 = Disables Interrupt 1 = Enables Interrupt. To enable the interrupt use this register. You must use the TZICFIQEnClear Register to disable the interrupt enable. Write: 0 = No effect 1 = Enables Interrupt. If Reset it disables all interrupts. There is 1 bit of the register for each interrupt source. Initial State 0x00000000 1.4.1.26 FIQ Enable Clear Register (TZICFIQENClear, W, Address=0xF280_0010, 0xF290_0010, 0xF2A0_0010, 0xF2B0_0010) TZICFIQENClear FIQEnClear Bit [31:0] Description Clears bits in the TZICFIQEnable Register. Writing a HIGH clears the corresponding bit in the TZICFIQEnable Register. Writing a LOW has no effect. Initial State - 1.4.1.27 FIQ Bypass Register (TZICFIQBypass, R/W, Address=0xF280_0014, 0xF290_0014, 0xF2A0_0014, 0xF2B0_0014) TZICFIQBypass FIQBypass Bit [31:1] [0] Description Read undefined. Write as 0. Enables nNSFIQIN to route directly to nFIQ. 0 = No Bypass 1 = Bypass. Initial State 0x0 0x0 1-27 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.28 Protection Register (TZICProtection, R/W, Address=0xF280_0018, 0xF290_0018, 0xF2A0_0018, 0xF2B0_0018) TZICProtection Protection Bit [31:1] [0] Description Read undefined. Write as 0. Enables or disables protected register access: 0 = Disables Protection mode 1 = Enables Protection mode. If enabled, you can only make privileged mode access (reads and writes) to the TZIC. This register is accessed in privileged mode, even if protection mode is disabled. Initial State 0x0 0x0 1.4.1.29 Lock Enable Register (TZICLock, W, Address=0xF280_001C, 0xF290_001C, 0xF2A0_001C, 0xF2B0_001C) TZICLock Lock Bit [31:0] Description To enable access to the other registers in the TZIC, you must write the correct access code of 0x0ACCE550 to this register. To disable access to the other TZIC registers, you must write any other value except 0x0ACCE550 to this register. Initial State - 1.4.1.30 Lock Status Register (TZICLockStatus, R, Address=0xF280_0020, 0xF290_0020, 0xF2A0_0020, 0xF2B0_0020) TZICLockStatus Locked Bit [31:1] [0] Description Read undefined. Shows the locked status of the TZIC: 0 = Access to the TZIC is not locked 1 = Access to the TZIC is locked Use TZICLock Register to unlock the access Initial State 0x0 0x1 1.4.1.31 Peripheral Identification Register (TZICPeriphID0, R, Address=0xF280_0FE0, 0xF290_0FE0, 0xF2A0_0FE0, 0xF2B0_0FE0) TZICPeriphID0 Partnumber0 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x90 Initial State 0x0 0x90 1-28 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.32 Peripheral Identification Register (TZICPeriphID1, R, Address=0xF280_0FE4, 0xF290_0FE4, 0xF2A0_0FE4, 0xF2B0_0FE4) TZICPeriphID1 Designer0 Partnumber1 Bit [31:8] [7:4] [3:0] Description Read undefined These bits read back as 0x1 These bits read back as 0x8 Initial State 0x0 0x1 0x8 1.4.1.33 Peripheral Identification Register (TZICPeriphID2, R, Address=0xF280_0FE8, 0xF290_0FE8, 0xF2A0_0FE8, 0xF2B0_0FE8) TZICPeriphlD2 Revision Designer1 Bit [31:8] [7:4] [3:0] Description Read undefined These bits read back as the revision number and can be between 0 and 15 These bits read back as 0x4 Initial State 0x0 0x0 0x4 1.4.1.34 Peripheral Identification Register (TZICPeriphID3, R, Address=0xF280_0FEC, 0xF290_0FEC, 0xF2A0_0FEC, 0xF2B0_0FEC) TZICPeriphID3 Configuration Bit [31:8] [7:0] Description Read undefined These bits read back as 0x00 Initial State 0x0 0x0 1.4.1.35 Identification Register (TZICPCellID0, R, Address=0xF280_0FF0, 0xF290_0FF0, 0xF2A0_0FF0, 0xF2B0_0FF0) TZICPCellID0 TZICPCellID0 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x0D Initial State 0x0 0x0D 1.4.1.36 Identification Register (TZICPCellID1, R, Address=0xF280_0FF4, 0xF290_0FF4, 0xF2A0_0FF4, 0xF2B0_0FF4) TZICPCellID1 TZICPCellID1 Bit [31:8] [7:0] Description Read undefined These bits read back as 0xF0 Initial State 0x0 0xF0 1-29 S5PV210_UM 1 VECTORED INTERRUPT CONTROLLER 1.4.1.37 Identification Register (TZICPCellID2, R, Address=0xF280_0FF8, 0xF290_0FF8, 0xF2A0_0FF8, 0xF2B0_0FF8) TZICPCellID2 TZICPCellID2 Bit [31:8] [7:0] Description Read undefined These bits read back as 0x05 Initial State 0x0 0x05 1.4.1.38 Identification Register (TZICPCellID3 Register, R, Address=0xF280_0FFC, 0xF290_0FFC, 0xF2A0_0FFC, 0xF2B0_0FFC) TZICPCellID3 TZICPCellID3 Bit [31:8] [7:0] Description Read undefined These bits read back as 0xB1 Initial State 0x0 0xB1 1-30 Section 5 MEMORY Table of Contents 1 DRAM Controller ........................................................................................1-1 1.1 Overview of DRAM Controller.................................................................................................................. 1-1 1.1.1 Introduction of DRAM Controller....................................................................................................... 1-1 1.1.2 Key Features of DRAM Controller .................................................................................................... 1-1 1.1.3 Supports Clock frequency up to 200MHz Block Diagram ................................................................ 1-2 1.2 Functional Description ............................................................................................................................. 1-3 1.2.1 Initialization ....................................................................................................................................... 1-3 1.2.2 Address Mapping.............................................................................................................................. 1-6 1.2.3 Low Power Operation ....................................................................................................................... 1-8 1.2.4 Precharge Policy............................................................................................................................... 1-9 1.2.5 Quality of Service............................................................................................................................ 1-11 1.2.6 Read Data Capture......................................................................................................................... 1-14 1.3 I/O Description ....................................................................................................................................... 1-19 1.3.1 PAD Mux for Address Configuration............................................................................................... 1-20 1.4 Register Description............................................................................................................................... 1-21 1.4.1 Register Map .................................................................................................................................. 1-21 2 SROM Controller ........................................................................................2-1 2.1 SROM Controller...................................................................................................................................... 2-1 2.1.1 Overview of SROM Controller .......................................................................................................... 2-1 2.1.2 Key Features of SROM Controller.................................................................................................... 2-1 2.1.3 Block Diagram of SROM Controller.................................................................................................. 2-1 2.2 Functional Description ............................................................................................................................. 2-2 2.2.1 nWAIT Pin Operation........................................................................................................................ 2-2 2.2.2 Programmable Access Cycle ........................................................................................................... 2-3 2.3 I/O Description ......................................................................................................................................... 2-4 2.4 Register Description................................................................................................................................. 2-5 2.4.1 Register Map .................................................................................................................................... 2-5 3 OneNAND Controller..................................................................................3-1 3.1 Overview of OneNAND Controller ........................................................................................................... 3-1 3.2 Key Features of OneNAND Controller ..................................................................................................... 3-1 3.3 Controller Usage Expectations ................................................................................................................ 3-2 3.4 Functional Description of OneNAND ....................................................................................................... 3-3 3.4.1 Block Diagram of OneENAND Controller ......................................................................................... 3-3 3.4.2 Clock control ..................................................................................................................................... 3-4 3.4.3 Initialization Protocol......................................................................................................................... 3-4 3.5 Memory Map ............................................................................................................................................ 3-5 3.6 OneNAND Interface ............................................................................................................................... 3-11 3.6.1 Overview of OneNAND Interface.................................................................................................... 3-11 3.6.2 OneNAND Interface Configuration ................................................................................................. 3-12 3.6.3 OneNAND Device Interrupt Handling ............................................................................................. 3-15 3.6.4 DMA Engine Overview ................................................................................................................... 3-18 3.6.5 DMA Operation ............................................................................................................................... 3-19 3.7 I/O Interface ........................................................................................................................................... 3-21 3.8 Register Description............................................................................................................................... 3-22 3.8.1 Register Map .................................................................................................................................. 3-22 3.8.2 OneNAND Interface Register ......................................................................................................... 3-23 3.8.3 DMA Control Registers................................................................................................................... 3-30 3.8.4 Interrupt Controller Registers ......................................................................................................... 3-36 4 NAND Flash Controller ..............................................................................4-1 4.1 Overview of NAND Flash Controller ........................................................................................................ 4-1 4.2 Key Features of NAND Flash Controller.................................................................................................. 4-1 4.2.1 4-1 4.2.2 Block Diagram .................................................................................................................................. 4-2 4.2.3 NAND Flash Memory Timing............................................................................................................ 4-2 4.3 Software Mode ......................................................................................................................................... 4-4 4.3.1 Data Register Configuration ............................................................................................................. 4-4 4.3.2 1-/ 4-/ 8-/ 12-/ 16-bit ECC ................................................................................................................. 4-5 4.3.3 2048 Byte 1-bit ECC Parity Code Assignment Table ....................................................................... 4-6 4.3.4 32 Byte 1-bit ECC Parity Code Assignment Table ........................................................................... 4-6 4.3.5 1-bit ECC Module Features .............................................................................................................. 4-6 4.3.6 1-bit ECC Programming guide.......................................................................................................... 4-7 4.3.7 4-bit ECC Programming guide (ENCODING)................................................................................... 4-8 4.3.8 4-bit ECC Programming guide (DECODING)................................................................................... 4-9 4.3.9 8-bit / 12-bit / 16-Bit ECC Programming guide (ENCODING) ........................................................ 4-10 4.3.10 8/12/16-bit ECC Programming Guide (DECODING).................................................................... 4-11 4.3.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC ............................................................ 4-12 4.3.12 Lock scheme for data protection .................................................................................................. 4-13 4.4 i/O Description........................................................................................................................................ 4-14 4.5 Register Description............................................................................................................................... 4-15 4.5.1 Register Map .................................................................................................................................. 4-15 4.5.2 Nand Flash Interface and 1 / 4-bit ecc registers............................................................................. 4-17 4.5.3 ECC Registers for 8, 12 and 16-bit ecc.......................................................................................... 4-26 5 Compact Flash Controller .........................................................................5-1 5.1 Overview of Compact Flash Controller .................................................................................................... 5-1 5.2 Key Features of Compact Flash Controller.............................................................................................. 5-1 5.3 Block Diagram of Compact Flash Controller............................................................................................ 5-2 5.4 Functional Description ............................................................................................................................. 5-2 5.5 True IDE Mode PIO/ PDMA Timing Diagram .......................................................................................... 5-3 5.5.1 ATA_PIO_TIME Register Setting Example (In case of Data Transfer)............................................ 5-5 5.6 Flowchart for PIO Read / Write ................................................................................................................ 5-6 5.7 True IDE MDMA Mode Timing Diagram .................................................................................................. 5-7 5.7.1 ATA_MDMA_TIME Register Setting Example ................................................................................. 5-8 5.8 True IDE UDMA Mode Timing Diagram .................................................................................................. 5-9 5.8.1 ATA_UDMA_TIME Register Setting Example................................................................................ 5-12 5.9 Transfer State Abort............................................................................................................................... 5-13 5.10 I/O Description ..................................................................................................................................... 5-14 5.11 Register Description............................................................................................................................. 5-15 5.11.1 Register Map ................................................................................................................................ 5-15 5.11.2 ATA Command Register (ATA_COMMAND, R/W, Address = 0xE820_0008) ............................ 5-18 6 External Bus Interface ...............................................................................6-1 6.1 Overview of External bus Interface .......................................................................................................... 6-1 6.2 Key Features of S5PV210 EBI................................................................................................................. 6-1 6.3 Block Diagram of Memory Interface through EBI .................................................................................... 6-2 6.4 Clock Scheme of Memory Controllers and EBI ....................................................................................... 6-3 List of Figures Figure Number Title Page Number Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 1-7 Figure 1-8 Figure 1-9 Figure 1-10 Figure 1-11 Figure 1-12 Figure 1-13 Figure 1-14 Figure 1-15 Overall Block Diagram ...................................................................................................................... 1-2 Linear Address Mapping................................................................................................................... 1-7 Interleaved Address Mapping ........................................................................................................... 1-8 Timing Diagram of Timeout Precharge........................................................................................... 1-10 Adaptive DRAM QoS Scheme Configuration ................................................................................. 1-12 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1) ............................ 1-14 Timing Diagram of Read Data Capture (DDR2, non-zero delay, RL=3, rd_fetch=2) ..................... 1-15 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)........ 1-16 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2). 1-17 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0) 1-18 DLL Lock Procedure....................................................................................................................... 1-34 Board Level Connection Diagram for DQS Cleaning ..................................................................... 1-36 DQS Cleaning for LPDDR if tAC Min ............................................................................................. 1-37 DQS Cleaning for LPDDR if tAC Max ............................................................................................ 1-37 DQS cleaning for DDR2 ................................................................................................................. 1-38 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Block Diagram of SROM Controller .................................................................................................. 2-1 SROM Controller nWAIT Timing Diagram........................................................................................ 2-2 SROM Controller Read Timing Diagram .......................................................................................... 2-3 SROM Controller Write Timing Diagram .......................................................................................... 2-3 Figure 3-1 OneNAND Controller Block Diagram (A: AHB Slave Port, B: AHB Master Port, and C: OneNAND Interface Port) ......................................................................................................................................................... 3-3 Figure 3-2 OneNAND Accesses (OneNAND Controller Address: 0xB0000000 ~ 0xB01FFFFF) by the External AHB Master (ARM Processor) ................................................................................................................. 3-9 Figure 3-3 Control Register Accesses (OneNAND Controller Address: 0xB0600000 ~ 0xB07FFFFF) by the External AHB Master (ARM Processor) ............................................................................................................... 3-10 Figure 3-4 ONENAND_IF_CTRL (OneNAND Interface Control) Register Update Flow ................................. 3-13 Figure 3-5 ONENAND_IF_ASYNC_TIMING_CTRL (OneNAND Interface Async Timing Control) Register Update Flow 3-14 Figure 3-6 OneNAND Device INT Pin Rising Edge Wait Operations with a Polling Method........................... 3-16 Figure 3-7 OneNAND Device INT Pin Rising Edge Wait Operations with an Interrupt-Driven Method ........ 3-16 Figure 3-8 OneNAND Device INT Pin Rising Edge Wait Operation Timing Diagram DMA Engin .................. 3-17 Figure 3-9 Data Transfer between OneNAND and External Memory by the Internal DMA Engine (OneNAND Read/ Write) 3-18 Figure 3-10 Internal DMA Engine Operations with a Polling Method ................................................................ 3-19 Figure 3-11 Internal DMA Engine Operations with an Interrupt-Driven Method ................................................ 3-20 Figure 3-12 ONENAND Interface Synchronous Read Timing ........................................................................... 3-25 Figure 3-13 OneNAND Interface Synchronous Write Timing ............................................................................ 3-25 Figure 3-14 OneNAND Interface Asynchronous Read Timing .......................................................................... 3-28 Figure 3-15 OneNAND Interface Asynchronous Write Timing .......................................................................... 3-28 Figure 4-1 Figure 4-2 Figure 4-3 NAND Flash Controller Block Diagram............................................................................................. 4-2 CLE and ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) .......................................................... 4-2 nWE and nRE Timing (TWRPH0=0, TWRPH1=0) ........................................................................... 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Block Diagram of Compact Flash Controller .................................................................................... 5-2 PIO Mode Waveform ........................................................................................................................ 5-4 Flowchart for Read / Write in PIO Class........................................................................................... 5-6 MDMA Timing Diagram .................................................................................................................... 5-7 UDMA- In Operation (Terminated by Device)................................................................................... 5-9 UDMA - In Operation (Terminated by Host) ................................................................................... 5-10 UDMA - Out Operation (Terminated by Device)............................................................................. 5-10 UDMA - Out Operation (Terminated by Host) ................................................................................ 5-11 Flowchart for Abort in ATA Mode.................................................................................................... 5-13 Figure 6-1 Memory Interface Through EBI......................................................................................................... 6-2 Figure 6-2 Clock Scheme of Memory Controllers and EBI ................................................................................ 6-3 List of Tables Table Number Title Page Number Table 1-1 Table 1-2 Table 1-3 Fast Qos index table ........................................................................................................................ 1-13 Master Transaction ID for DMC0 in S5PV210 ................................................................................. 1-48 Master Transaction ID for DMC1 in S5PV210 ................................................................................. 1-49 Table 3-1 Table 3-2 Table 3-3 nCE[0]) OneNAND Controller Memory Map ................................................................................................... 3-6 OneNAND Chip #0 (nCE[0]) Address Map (If the OneNAND device is Connected to nCE[0])...... 3-7 Flex-OneNAND Chip #0 (nCE[0]) Address Map (If the Flex-OneNAND device is Connected to 3-8 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Timing Parameter Each PIO Mode .................................................................................................... 5-5 MDMA Timing Parameters................................................................................................................. 5-7 Timing Parameter Each UDMA Mode ............................................................................................. 5-11 True-IDE Mode I/O Decoding .......................................................................................................... 5-12 S5PV210_UM 1 DRAM CONTROLLER 1 DRAM CONTROLLER 1.1 OVERVIEW OF DRAM CONTROLLER 1.1.1 INTRODUCTION OF DRAM CONTROLLER The DRAM controller is an Advanced Microcontroller Bus Architecture (AMBAtm) AXI compliant slave to interface external JEDEC DDR-type SDRAM devices. To support high-speed memory devices, the DRAM controller uses a SEC DDR PHY interface. The controller includes an advanced embedded scheduler to utilize memory device efficiently and an optimized pipeline stage to minimize latency. S5PV210 has two independent DRAM Controllers and Ports, namely, DMC0 and DMC1. 1.1.2 KEY FEATURES OF DRAM CONTROLLER • Compatible with JEDEC DDR2, low power DDR and low power DDR2 SDRAM specification • Uses the SEC LPDDR2 PHY interface to support high-speed memory devices • Supports up to two external chip selects and 1/2/4/8 banks per one chip • Supports 128 Mb, 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb density Memory Devices • Supports 16/ 32-bit wide memory data width • Optimized pipeline stage for low latency • Supports QoS scheme to ensure low latency for some applications • Advanced embedded scheduler enables out-of order operations to utilize memory device efficiently • Supports excellent chip/bank interleaving and memory interrupting • Supports AMBA AXI low power channel for systematic power control • Adapts to various low power schemes to reduce the dynamic and static current of memory • Supports outstanding exclusive accesses • Supports bank selective precharge policy 1-1 S5PV210_UM 1.1.3 SUPPORTS CLOCK FREQUENCY UP TO 200MHZ BLOCK DIAGRAM 1 DRAM CONTROLLER Figure 1-1 Overall Block Diagram Figure 1-1 shows the overall block diagram of the controller. The block diagram shows the bus interface block, scheduler block, and memory interface block, which connects and interfaces with the SEC LPDDR2 PHY. The bus interface block saves the bus transactions for memory access that come from the AXI slave port to the command queue. Additionally it saves the write data to the write buffer or sends the read data to the Master via the AXI bus. It also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function registers/ direct commands and an AXI low power channel interface. The Scheduler block uses the memory bank Finite State Machine (FSM) information to arbitrate the bus transactions in the command queues and transforms the commands into a memory command type, which is sent to the Memory interface block. It also controls the write and read data flow between the memory and the AXI bus. The Memory interface block updates each memory bank state according to the memory command coming from the scheduler and sends the bank state back to the scheduler. It creates a memory command depending on the memory latency and sends the command to the SEC LPDDR2 PHY via the PHY interface. 1-2 S5PV210_UM 1 DRAM CONTROLLER 1.2 FUNCTIONAL DESCRIPTION 1.2.1 INITIALIZATION An Initialization procedure consists of PHY DLL initialization, setting controller register and memory initialization. For memory initialization, refer to JEDEC specifications and data sheets of memory devices. There are three different memory types, namely, LPDDR, LPDDR2, and DDR2. According to the memory types, initialization sequences are as follows. 1.2.1.1 LPDDR Initialization sequence for LPDDR memory type: 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic high level. Then apply stable clock. Note: XDDR2SEL should be Low level to hold CKE to high. 2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to activate the PHY DLL. 3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to the correct value according to clock frequency and memory tAC parameters. 4. Set the PhyControl0.ctrl_start bit-field to ‘1’. 5. Set the ConControl. At this moment, an auto refresh counter should be off. 6. Set the MemControl. At this moment, all power down modes should be off. 7. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register. 8. Set the PrechConfig and PwrdnConfig registers. 9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters. 10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers. 11 Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked. 12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, it should not be off for reliable operation. PHY DLL can be off if frequency is low. If off mode is used, set the PhyControl0.ctrl_force bit-field to the correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field for fix delay amount. Clear the PhyControl0.ctrl_dll_on bitfield to turn off PHY DLL. 13. Confirm whether stable clock issues minimum 200us after power on 14. Issue a PALL command using the DirectCmd register. 15. Issue two Auto Refresh commands using the DirectCmd register. 16. Issue a MRS command using the DirectCmd register to program the operating parameters. 1-3 S5PV210_UM 1 DRAM CONTROLLER 17. Issue an EMRS command using the DirectCmd register to program the operating parameters. 18. If there are two external memory chips, perform steps 14~17 for chip1 memory device. 19. Set the ConControl to turn on an auto refresh counter. 20. If power down modes is required, set the MemControl registers. 1.2.1.2 LPDDR2 Initialization sequence for LPDDR2 memory type: 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low. 2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to activate the PHY DLL. 3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters. 4. Set the PhyControl0.ctrl_start bit-field to ‘1’. 5. Set the ConControl. At this moment, an auto refresh counter should be off. 6. Set the MemControl. At this moment, all power down modes should be off. 7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register. 8. Set the PrechConfig and PwrdnConfig registers. 9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters. 10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers. 11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked. 12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL. 13. Set the PhyControl1.fp_resync bit-field to ‘1’ to update DLL information. 14. Confirm that CKE still maintains a logic low level at minimum 100ns after power on. 15. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level. 16. Wait for at least 200us. 1-4 S5PV210_UM 1 DRAM CONTROLLER 17. Issue a MRS command using the DirectCmd register to reset memory device and program the operating parameters. 18. Wait for minimum 1us. 19. Issue a MRR command using the DirectCmd register to poll the DAI bit of the MRStatus register to know whether Device Auto-Initialization is completed or not. 20. If there are two external memory chips, perform steps 15 ~ 19 for chip1 memory device. 21. Set the ConControl to turn on an auto refresh counter. 22. If power down modes is required, set the MemControl registers. 1.2.1.3 DDR2 Initialization sequence for DDR2 memory type: 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low. 2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL. 3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters. 4. Set the PhyControl0.ctrl_start bit-field to ‘1’. 5. Set the ConControl. At this moment, an auto refresh counter should be off. 6. Set the MemControl. At this moment, all power down modes should be off. 7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register. 8. Set the PrechConfig and PwrdnConfig registers. 9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters. 10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers. 11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked. 12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL. 13. Confirm whether stable clock is issued minimum 200us after power on 14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level. 1-5 S5PV210_UM 1 DRAM CONTROLLER 15. Wait for minimum 400ns. 16. Issue a PALL command using the DirectCmd register. 17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters. 18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters. 19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs. 20. Issue a MRS command using the DirectCmd register to reset the memory DLL. 21. Issue a PALL command using the DirectCmd register. 22. Issue two Auto Refresh commands using the DirectCmd register. 23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL. 24. Wait for minimum 200 clock cycles. 25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters. 26. If there are two external memory chips, perform steps 14~25 for chip1 memory device. 27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers. 1.2.2 ADDRESS MAPPING The controller modifies the address of the bus transaction coming from the AXI slave port into a memory address chip select, bank address, row address, column address and memory data width. To map chip select0 of the memory device to a specific area of the address map, the chip_base and chip_mask bit-fields of the MemConfig0 register must be set (Refer to Register Descriptions). If chip1 of the memory device exists, the MemConfig1 register must also be set. Then, the AXI address requested by the AXI Master is divided into AXI base address and AXI offset address. The AXI base address activates the appropriate memory chip select and the AXI offset address is mapped to a memory address according to the bank, row, column number, and data width set by the MemConfig register. There are two ways to map the AXI offset address as shown in Figure 1-2 Linear mapping and Interleaved mapping. 1-6 S5PV210_UM 1.2.2.1 Linear Mapping 1 DRAM CONTROLLER Figure 1-2 Linear Address Mapping As shown in Figure 1-2, the linear mapping method maps the AXI address in the order of bank, row, column and width. Since the bank address does not change for at least one bank size, applications that use linear address mapping have a high possibility to access the same bank. 1-7 S5PV210_UM 1 DRAM CONTROLLER 1.2.2.2 Interleaved Mapping AXI base address bank0.row0 bank1.row0 bank2.row0 bank3.row0 AXI offset address bank0.row1 bank1.row1 25 13 12 11 10 210 bank2.row1 bank3.row1 row bank column width Interleaved mapping : AXI offset address = {row, bank, column, width} bank0.rown bank1.rown bank2.rown bank3.rown row density Figure 1-3 Interleaved Address Mapping As shown in Figure 1-3, the interleaved mapping method maps the AXI address in the order of row, bank, column and width. The difference between the linear mapping method and the interleaved method is that the bank and row order is different. For accesses beyond a row size, interleaved mapping accesses a different bank. Therefore, applications that use interleaved mapping access numerous banks. This improves the performance but increases power consumption. 1.2.3 LOW POWER OPERATION The DRAM controller executes a low power memory operation in five ways, namely: • AXI Low power channel • Dynamic power down • Dynamic self-refresh • Clock stop • Direct command • Each feature is independent of each other and executed at the same time. 1.2.3.1 AXI Low Power Channel The controller has an AXI low power channel interface to communicate with low power management units such as the system controller, which makes the memory device go into self-refresh mode. To request through the AXI low power channel, refer the chip1_empty and chip0_empty bit-fields of ConControl register to check if the command queue is currently empty. 1-8 S5PV210_UM 1 DRAM CONTROLLER 1.2.3.2 Dynamic Power Down The SDRAM device has an active/ precharge power down mode. This mode is entered if CKE becomes LOW. To enter active power down mode minimum one row of a bank must be open. To enter precharge power down mode CKE must be low. If no AXI transaction enters the controller and the command queue becomes empty for a specific number of cycles (PwrdnConfig.dpwrdn_cyc bit-field), the controller changes the memory device’s state to active/ precharge power down automatically. Then, there are two ways to enter the active/ precharge power down state and it is selected by MEMCONTROL.dpwrdn_type bit. 1. Active/ precharge power down mode: Enter power down without considering whether there is a row open or not, 2. Force precharge power down mode: Enter power down after closing all banks. If a new AXI transaction enters the controller, the controller automatically wakes up the memory device from power down state and executes in a normal operation state. 1.2.3.3 Dynamic Self Refresh Similar to the dynamic power down feature (Refer to Section 2.3.2 Dynamic Power Down), if the command queue is empty for a specific amount of cycles (PwrdnConfig.dsref_cyc bit-field), the memory device enters self-refresh mode. Since exiting power down mode requires many cycles, we recommend to choose a greater cycle size for dynamic self-refresh entry than dynamic power down. 1.2.3.4 Clock Stop To reduce the I/O power of the memory device and the controller, it is possible to stop the clock if the LPDDR / LPDDR2 is in idle mode, or self refresh mode and DDR2 is in self refresh mode. If this feature is enabled, the controller automatically executes the clock stop feature. 1.2.3.5 Direct Command Use the direct command feature to send a command to the memory device through the APB3 port. This way, you force the memory device to enter active/ precharge power down, self-refresh or deep power down mode. 1.2.4 PRECHARGE POLICY There are two ways for the controller to decide precharge policy, namely: • Bank selective precharge policy • Timeout precharge 1-9 S5PV210_UM 1 DRAM CONTROLLER 1.2.4.1 Bank Selective Precharge Policy Since applications include different page policy preferences, it is hard for the engineer to decide whether to use open page policy, or close page (auto precharge) policy. Instead of applying the page policy to entire banks, the bank selective precharge policy allows the user to choose a precharge policy for each bank (Refer to PrechConfig.chip1_policy). You can assign certain applications to a bank that uses an open page policy, and other applications to a bank that uses a close page (auto precharge) policy. Open Page Policy: After a READ or WRITE, the accessed row is left open. Close Page (Auto Precharge) Policy: Right after a READ or WRITE command, the controller issues an auto precharge to the bank. 1.2.4.2 Timeout Precharge If a certain bank uses an open page policy, the row is left open after a data access. If this happens and the bank that is left open is not scheduled for a specific number of cycles (PrechConfig.tp_cnt bit-field) the controller automatically issues a precharge command to close the bank. Figure 1-4 Timing Diagram of Timeout Precharge 1-10 S5PV210_UM 1 DRAM CONTROLLER 1.2.5 QUALITY OF SERVICE The Quality of Service (QoS) is defined for the controller to increase the arbitration priority of a master that requires low latency read data. The QoS is determined if the control queue (Refer to Figure 1-1Figure 1-1) receives the command through the AXI bus and the QoS count starts depreciating at this moment. If the count reaches zero, this command becomes the highest priority among the other commands that are in the control queue. There are three types of QoS, namely: • qos_cnt • qos_cnt_f • default_qos 1.2.5.1 qos_cnt There are 16 configurable QoSControls, which have independent qos_masks that masks the ARID/AWID from one bit up to the ARID/AWID width. All 16 QoSControls are either enabled or disabled, 1. If the command is received via the AXI bus, the ARID/AWID is masked by the qos_masks (QoSConfig(n).qos_mask) from the 16 QoSControls that are enabled. 2. The masked results are then compared to the qos_ids (QoSConfig(n).qos_id). If one of the result are equal, the qos_cnt (QoSControl(n).qos_cnt) value is applied to the command and saved in the control queue. 1-11 S5PV210_UM 1 DRAM CONTROLLER 1.2.5.2 qos_cnt_f To service latency sensitive commands faster, an adaptive DRAM QoS scheme called QoS fast can be enabled. This policy cannot be done by the memory controller itself, but the IP has to observe its FIFO level. For read transactions, for example, when the IP’s FIFO is less than 1/4th full, there is no margin of time available between the FIFO and the memory controller. At this moment, if the IP flags the memory controller through it’s qos_fast index path, the qos_cnt_f (QoSControl(index).qos_cnt_f) value that is specified for the IP is applied to the command to give a higher QoS priority over other IP commands. For write transactions, for example, when the IP’s FIFO is more than 3/4th full, there is almost no margin of time available before the FIFO becomes full. At this moment, if the IP flags the memory controller through it’s index path, the qos_cnt_f (QoSControl(index).qos_cnt_f) value that is specified for the IP is applied to the command to give a higher QoS priority over other IP commands. Figure 1-5 shows the adaptive DRAM QoS scheme configuration in SoC. qos_fast index Figure 1-5 Adaptive DRAM QoS Scheme Configuration Each IP is able to flag the memory controller by accessing a one-bit side-band channel. 1-12 S5PV210_UM 1 DRAM CONTROLLER If qos fast (Concontrol.qos_fast_en) is enabled, and the master that sent the command has raised the qos_fast flag of it’s specific channel index, instead of qos_cnt (QoSControl(index).qos_cnt) being applied to the command, the QoS Cycles for fast request (QoSControl(index).qos_cnt_f) is applied. Table 1-1 shows the QoS fast index of each IP. Table 1-1 Fast Qos index table qos_fast index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Master Reserved Reserved Reserved Reserved FIMD window0 FIMD window4 FIMD window1 FIMD window2 FIMD window3 FIMC0 FIMC1 FIMC2 Reserved VP MIXER_GRP0 MIXER_GRP1 1.2.5.3 Default Qos If qos_cnt is not applied to the command, a default QoS counter (Is set to a different value by modifying ConControl.timeout_cnt) is applied to the command. (Default QoS counter is applied to both read and write) 1-13 S5PV210_UM 1 DRAM CONTROLLER 1.2.6 READ DATA CAPTURE A memory device that receives a read command sends the data to the controller after a read latency (i.e. CAS latency). After clearing the DQS, the PHY uses the PHY DLL to phase shift the DQS 90 degrees. Using the shifted DQS, the PHY samples the read data and saves the data into the read data input FIFO, which is located inside the PHY. Then, the controller fetches the data from the PHY while considering the read latency and the read fetch delay, and then sends it to the AXI read channel. The following figures show the read data capture process’s timing diagram for each memory type. Figure 1-6 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1) 1-14 S5PV210_UM 1 DRAM CONTROLLER Figure 1-6 is for DDR2 having an internal DLL. An internal DLL exists which allows it to send the data after an exact amount of read latency. If we assume there are minimal or no board/ PHY input delay, if sampling the negedge (Q1, Q3 sampling), since the data gets saved into the PHY read data input FIFO, the controller sends the read data to the AXI read channel in ‘read latency + 1(read fetch)’ cycles. The read fetch cycle is set using the ConControl.rd_fetch bit-field. Figure 1-7 Timing Diagram of Read Data Capture (DDR2, non-zero delay, RL=3, rd_fetch=2) Figure 1-7 is different from Figure 1-6 because a delay exists. Negedge sampling happens at T5 and T6, which is one cycle slower than T4/T5 shown in Figure 1-4. Therefore, the read fetch cycle should be set to two since the sampled read data is saved slowly into the read input FIFO. 1-15 S5PV210_UM 1 DRAM CONTROLLER To calculate the DDR2 rd_fetch value: rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75), Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x Therefore, rd_fetch must have minimum one value. Figure 1-8 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1) An LPDDR/LPDDR2 does not have an internal DLL. Without an internal DLL as shown in Figure 1-8 the data is sent out after tDQSCK before the read latency is over. Even if we assume zero delay, since tDQSCK becomes relatively large in high frequencies, the read fetch cycle should be set to one. 1-16 S5PV210_UM 1 DRAM CONTROLLER Figure 1-9 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2) If a delay exists as shown in Figure 1-9, a bigger value should be assigned to rd_fetch 1-17 S5PV210_UM 1 DRAM CONTROLLER Figure 1-10 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0) tDQSCK + Delay is relatively small compared to the clock period during low frequencies as shown in Figure 1-10. In this situation, negedge sampling happens before read latency and therefore read fetch is set to zero. To calculate the LPDDR/LPDDR2 rd_fetch value: rd_fetch (LPDDR/LPDDR2) = INT((-1 + Delay + 0.5T + 0.25T)/T) = INT(Delay/T - 0.25), Delay: board delay + PHY input delay, T: clock period, INT(x): the rounded-up integer value of x Therefore, if the value of Delay/T is less than 0.25, rd_fetch is set to zero 1-18 S5PV210_UM 1 DRAM CONTROLLER 1.3 I/O DESCRIPTION Signal I/O Description PAD Type DDR2SEL I Memory Type Selection (0: LPDDR1, 1: DDR2, LPDDR2) XDDR2SEL dedicated SCLK O Memory Clock Xm1SCLK dedicated nSCLK O Memory Negative Clock Xm1nSCLK dedicated RASn O Row Address Selection Xm1RASn dedicated CASn O Column Address Selection Xm1CASn dedicated WEn O Write Enable Xm1WEn dedicated DATA[31:0] I/O Memory Data Bus Xm1DATA[31:0] dedicated DQM[3:0] O Write Masking Per Byte Xm1DQM[3:0] dedicated DQSp[3:0] I/O Data Strobe Signal Per Byte Xm1DQS[3:0] dedicated DQSn[3:0] I/O Data Strobe Negative Signal Per Byte Xm1DQSn[3:0] dedicated ADCT[18:0], CKE O Memory Address, Bank Address, CS, CKE signals * refer to 3.1 table dedicated 1-19 S5PV210_UM 1 DRAM CONTROLLER 1.3.1 PAD MUX FOR ADDRESS CONFIGURATION PAD Name Xm1ADDR[0] Xm1ADDR[1] Xm1ADDR[2] Xm1ADDR[3] Xm1ADDR[4] Xm1ADDR[5] Xm1ADDR[6] Xm1ADDR[7] Xm1ADDR[8] Xm1ADDR[9] Xm1ADDR[10] Xm1ADDR[11] Xm1ADDR[12] Xm1ADDR[13] Xm1ADDR[14] Xm1ADDR[15] Xm1CSn[1] Xm1CSn[0] Xm1CKE[1] Xm1CKE[0] Config. 1 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 BA_0 BA_1 CS_1 CS_0 CKE_1 CKE_0 Config. 2 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 BA_0 BA_1 CS_0 ADDR_14 CKE_0 Config. 3 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 BA_0 BA_1 BA_2 CS_0 CKE_0 Config. 4 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 BA_0 BA_1 BA_2 CS_0 ADDR_14 CKE_0 LPDDR2 CA_0 CA_1 CA_2 CA_3 CA_4 CA_5 CA_6 CA_7 CA_8 CA_9 CS_1 CS_0 CKE_1 CKE_0 NOTE: 1. Address Config. 1 : The Number of Banks (MEMCONFIGn.chip_bank) is set under 4banks and the Number of Row Address Bits(MEMCONFIGn.chip_row) is set under 14bits. 2. Address Config. 2: The Number of Banks (MEMCONFIGn.chip_bank) is set under 4banks and the Number of Row Address Bits(MEMCONFIGn.chip_row) is set 15 bits. 3. Address Config. 3: The Number of Banks (MEMCONFIGn.chip_bank) is set 8 banks and the Number of Row Address Bits(MEMCONFIGn.chip_row) is set under 14 bits 4. Address Config. 4: The Number of Banks (MEMCONFIGn.chip_bank) is set 8 banks and the Number of Row Address Bits(MEMCONFIGn.chip_row) is set 15bits. 5. Address LPDDR2 : The Type of Memory(MEMCONTROL.mem_type) is selected LPDDR2. 1-20 S5PV210_UM 1 DRAM CONTROLLER 1.4 REGISTER DESCRIPTION 1.4.1 REGISTER MAP Register DMC0 CONCONTROL MEMCONTROL MEMCONFIG0 MEMCONFIG1 DIRECTCMD PRECHCONFIG PHYCONTROL0 PHYCONTROL1 RESERVED PWRDNCONFIG TIMINGAREF TIMINGROW TIMINGDATA TIMINGPOWER PHYSTATUS CHIP0STATUS CHIP1STATUS AREFSTATUS MRSTATUS PHYTEST0 PHYTEST1 QOSCONTROL0 QOSCONFIG0 QOSCONTROL1 QOSCONFIG1 QOSCONTROL2 Address R/W Description Reset Value 0xF000_0000 0xF000_0004 0xF000_0008 0xF000_000C 0xF000_0010 0xF000_0014 0xF000_0018 0xF000_001C 0xF000_0020 0xF000_0028 0xF000_0030 0xF000_0034 0xF000_0038 0xF000_003C 0xF000_0040 0xF000_0048 0xF000_004C 0xF000_0050 0xF000_0054 0xF000_0058 0xF000_005C 0xF000_0060 0xF000_0064 0xF000_0068 0xF000_006C 0xF000_0070 R/W Specifies the Controller Control Register 0x0FFF_1350 R/W Specifies the Memory Control Register 0x0020_2100 R/W Specifies the Memory Chip0 Configuration Register 0x20F0_0312 R/W Specifies the Memory Chip1 Configuration Register 0x30F0_0312 R/W Specifies the Memory Direct Command Register 0x0000_0000 R/W Specifies the Precharge Policy Configuration Register 0xFF00_0000 R/W Specifies the PHY Control0 Register 0x0000_0000 R/W Specifies the PHY Control1 Register 0x0000_0040 R Reserved 0x0000_0000 R/W Specifies the Dynamic Power Down Configuration 0xFFFF_00FF Register R/W Specifies the AC Timing Register for SDRAM Auto 0x0000_040E Refresh R/W Specifies the AC Timing Register for SDRAM Row 0x0F23_3286 R/W Specifies the AC Timing Register for SDRAM Data 0x1213_0204 R/W Specifies the AC Timing Register for Power Mode 0x0E1B_0422 of SDRAM R Specifies the PHY Status Register 0x0000_000X R Specifies the Memory Chip0 Status Register 0x0000_0000 R Specifies the Memory Chip1 Status Register 0x0000_0000 R Specifies the Counter Status Register for Auto Refresh 0x0000_FFFF R Specifies the Memory Mode Registers Status Register 0x0000_0000 R/W Specifies the PHY Test Register 0 0x0000_0000 R Specifies the PHY Test Register 1 0x0000_0000 R/W Specifies the Quality of Service Control Register 0 0x0000_0000 R/W Specifies the Quality of Service Configuration Register 0 0x0000_0000 R/W Specifies the Quality of Service Control Register 1 0x0000_0000 R/W Specifies the Quality of Service Configuration Register 1 0x0000_0000 R/W Specifies the Quality of Service Control Register 2 0x0000_0000 1-21 S5PV210_UM 1 DRAM CONTROLLER Register QOSCONFIG2 Address 0xF000_0074 QOSCONTROL3 0xF000_0078 QOSCONFIG3 0xF000_007C QOSCONTROL4 0xF000_0080 QOSCONFIG4 0xF000_0084 QOSCONTROL5 0xF000_0088 QOSCONFIG5 0xF000_008C QOSCONTROL6 0xF000_0090 QOSCONFIG6 0xF000_0094 QOSCONTROL7 0xF000_0098 QOSCONFIG7 0xF000_009C QOSCONTROL8 0xF000_00A0 QOSCONFIG8 0xF000_00A4 QOSCONTROL9 0xF000_00A8 QOSCONFIG9 0xF000_00AC QOSCONTROL10 0xF000_00B0 QOSCONFIG10 0xF000_00B4 QOSCONTROL11 0xF000_00B8 QOSCONFIG11 0xF000_00BC QOSCONTROL12 0xF000_00C0 QOSCONFIG12 0xF000_00C4 QOSCONTROL13 0xF000_00C8 QOSCONFIG13 0xF000_00CC QOSCONTROL14 0xF000_00D0 QOSCONFIG14 0xF000_00D4 QOSCONTROL15 0xF000_00D8 R/W Description R/W Specifies the Quality of Service Configuration Register 2 R/W Specifies the Quality of Service Control Register 3 R/W Specifies the Quality of Service Configuration Register 3 R/W Specifies the Quality of Service Control Register 4 R/W Specifies the Quality of Service Configuration Register 4 R/W Specifies the Quality of Service Control Register 5 R/W Specifies the Quality of Service Configuration Register 5 R/W Specifies the Quality of Service Control Register 6 R/W Specifies the Quality of Service Configuration Register 6 R/W Specifies the Quality of Service Control Register 7 R/W Specifies the Quality of Service Configuration Register 7 R/W Specifies the Quality of Service Control Register 8 R/W Specifies the Quality of Service Configuration Register 8 R/W Specifies the Quality of Service Control Register 9 R/W Specifies the Quality of Service Configuration Register 9 R/W Specifies the Quality of Service Control Register 10 R/W Specifies the Quality of Service Configuration Register 10 R/W Specifies the Quality of Service Control Register 11 R/W Specifies the Quality of Service Configuration Register 11 R/W Specifies the Quality of Service Control Register 12 R/W Specifies the Quality of Service Configuration Register 12 R/W Specifies the Quality of Service Control Register 13 R/W Specifies the Quality of Service Configuration Register 13 R/W Specifies the Quality of Service Control Register 14 R/W Specifies the Quality of Service Configuration Register 14 R/W Specifies the Quality of Service Control Register 15 Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 1-22 S5PV210_UM 1 DRAM CONTROLLER Register QOSCONFIG15 DMC1 CONCONTROL MEMCONTROL MEMCONFIG0 MEMCONFIG1 DIRECTCMD PRECHCONFIG PHYCONTROL0 PHYCONTROL1 RESERVED PWRDNCONFIG TIMINGAREF TIMINGROW TIMINGDATA TIMINGPOWER PHYSTATUS CHIP0STATUS CHIP1STATUS AREFSTATUS MRSTATUS PHYTEST0 PHYTEST1 QOSCONTROL0 QOSCONFIG0 QOSCONTROL1 QOSCONFIG1 QOSCONTROL2 QOSCONFIG2 Address 0xF000_00DC R/W Description R/W Specifies the Quality of Service Configuration Register 15 Reset Value 0x0000_0000 0xF140_0000 0xF140_0004 0xF140_0008 0xF140_000C 0xF140_0010 0xF140_0014 0xF140_0018 0xF140_001C 0xF140_0020 0xF140_0028 0xF140_0030 0xF140_0034 0xF140_0038 0xF140_003C 0xF140_0040 0xF140_0048 0xF140_004C 0xF140_0050 0xF140_0054 0xF140_0058 0xF140_005C 0xF140_0060 0xF140_0064 0xF140_0068 0xF140_006C 0xF140_0070 0xF140_0074 R/W Specifies the Controller Control Register R/W Specifies the Memory Control Register R/W Specifies the Memory Chip0 Configuration Register R/W Specifies the Memory Chip1 Configuration Register R/W Specifies the Memory Direct Command Register R/W Specifies the Precharge Policy Configuration Register R/W Specifies the PHY Control0 Register R/W Specifies the PHY Control1 Register R/W Reserved R/W Specifies the Dynamic Power Down Configuration Register R/W Specifies the AC Timing Register for SDRAM Auto Refresh R/W Specifies the AC Timing Register for SDRAM Row R/W Specifies the AC Timing Register for SDRAM Data R/W Specifies the AC Timing Register for Power Specifies the Mode of SDRAM R Specifies the PHY Status Register R Specifies the Memory Chip0 Status Register R Specifies the Memory Chip1 Status Register R Specifies the Counter Status Register for Auto Refresh R Specifies the Memory Mode Registers Status Register R/W Specifies the PHY Test Register 0 R Specifies the PHY Test Register 1 R/W Specifies the Quality of Service Control Register 0 R/W Specifies the Quality of Service Configuration Register 0 R/W Specifies the Quality of Service Control Register 1 R/W Specifies the Quality of Service Configuration Register 1 R/W Specifies the Quality of Service Control Register 2 R/W Specifies the Quality of Service Configuration Register 2 0x0FFF1350 0x00202100 0x40E00312 0x60E00312 0x00000000 0xFF000000 0x00000000 0x00000040 0x00000000 0xFFFF00FF 0x0000040E 0x0F233286 0x12130204 0x0E1B0422 0x0000000X 0x00000000 0x00000000 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 1-23 S5PV210_UM 1 DRAM CONTROLLER Register QOSCONTROL3 QOSCONFIG3 Address 0xF140_0078 0xF140_007C QOSCONTROL4 0xF140_0080 QOSCONFIG4 0xF140_0084 QOSCONTROL5 0xF140_0088 QOSCONFIG5 0xF140_008C QOSCONTROL6 0xF140_0090 QOSCONFIG6 0xF140_0094 QOSCONTROL7 0xF140_0098 QOSCONFIG7 0xF140_009C QOSCONTROL8 0xF140_00A0 QOSCONFIG8 0xF140_00A4 QOSCONTROL9 0xF140_00A8 QOSCONFIG9 0xF140_00AC QOSCONTROL10 0xF140_00B0 QOSCONFIG10 0xF140_00B4 QOSCONTROL11 0xF140_00B8 QOSCONFIG11 0xF140_00BC QOSCONTROL12 0xF140_00C0 QOSCONFIG12 0xF140_00C4 QOSCONTROL13 0xF140_00C8 QOSCONFIG13 0xF140_00CC QOSCONTROL14 0xF140_00D0 QOSCONFIG14 0xF140_00D4 QOSCONTROL15 0xF140_00D8 QOSCONFIG15 0xF140_00DC R/W Description R/W Specifies the Quality of Service Control Register 3 R/W Specifies the Quality of Service Configuration Register 3 R/W Specifies the Quality of Service Control Register 4 R/W Specifies the Quality of Service Configuration Register 4 R/W Specifies the Quality of Service Control Register 5 R/W Specifies the Quality of Service Configuration Register 5 R/W Specifies the Quality of Service Control Register 6 R/W Specifies the Quality of Service Configuration Register 6 R/W Specifies the Quality of Service Control Register 7 R/W Specifies the Quality of Service Configuration Register 7 R/W Specifies the Quality of Service Control Register 8 R/W Specifies the Quality of Service Configuration Register 8 R/W Specifies the Quality of Service Control Register 9 R/W Specifies the Quality of Service Configuration Register 9 R/W Specifies the Quality of Service Control Register 10 R/W Specifies the Quality of Service Configuration Register 10 R/W Specifies the Quality of Service Control Register 11 R/W Specifies the Quality of Service Configuration Register 11 R/W Specifies the Quality of Service Control Register 12 R/W Specifies the Quality of Service Configuration Register 12 R/W Specifies the Quality of Service Control Register 13 R/W Specifies the Quality of Service Configuration Register 13 R/W Specifies the Quality of Service Control Register 14 R/W Specifies the Quality of Service Configuration Register 14 R/W Specifies the Quality of Service Control Register 15 R/W Specifies the Quality of Service Configuration Register 15 Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 1-24 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.1 Controller Control Register (ConControl, R/W, Address = 0xF000_0000, 0xF140_0000) CONCONTROL Bit Description R/W Reserved timeout_cnt rd_fetch qos_fast_en dq_swap chip1_empty chip0_empty [31:28] Should be zero [27:16] Default Timeout Cycles R/W 0xn = n aclk cycles (aclk: AXI clock) This counter prevents transactions in command queue from starvation. This counter starts if a new AXI transaction comes into a queue. If the counter becomes zero, the corresponding transaction becomes the highest priority command of all the transactions in the command queue. This is a default timeout counter and overridden by the QoS counter if the ARID/AWID matched with the QoS ID comes into the command queue. Refer to “1.2.5 Quality of Service”. [15:12] Read Data Fetch Cycles R/W 0xn = n mclk cycles (mclk: Memory clock) This register is for the unpredictable latency of read data coming from memory devices by tDQSCK variation or the board flying time. The read fetch delay of PHY read FIFO must be controlled by this parameter. The controller will fetch read data from PHY after (read_latency + n) mclk cycles. Refer to “1.2.6 Read Data Capture”. [11] Enables adaptive QoS R/W 0x0 = Disables 0x1 = Enables If enabled, the controller loads QoS counter value from QoSControl.qos_cnt_f instead of QoSControl.qos_cnt if the corresponding input pin qos_fast is turned on. Refer to “1.2.5 Quality of Service”. [10] DQ Swap R/W 0x0 = Disables 0x1 = Enables If enabled, the controller reverses the bit order of memory data pins. (For example, DQ[31] <-> DQ[0], DQ[30] <-> DQ[1]) [9] Command Queue Status of Chip1 R 0x0 = Not Empty 0x1 = Empty There is no AXI transaction corresponding to chip1 memory in the command queue entries [8] Command Queue Status of Chip0 R 0x0 = Not Empty 0x1 = Empty There is no AXI transaction corresponding to chip0 memory in the command queue entries Initial State 0x0 0xFFF 0x1 0x0 0x0 0x1 0x1 1-25 S5PV210_UM 1 DRAM CONTROLLER CONCONTROL drv_en ctc_rtr_gap_en aref_en out_of Reserved Bit Description R/W Initial State [7] PHY Driving R/W 0x0 0x0 = Disables 0x1 = Enables During the high-Z state of the memory bidirectional pins, PHY drives these pins with the zeros or pull down these pins for preventing current leakage. Set PhyControl1.drv_type register to select driving type. [6] Read Cycle Gap for Two Different Chips R/W 0x1 0x0 = Disables 0x1 = Enables To prevent collision between reads from two different memory devices, a one-cycle gap is required. Enable this register to insert the gap automatically for continuous reads from two different memory devices. [5] Auto Refresh Counter 0x0 = Disables 0x1 = Enables Enable this to decrease the auto refresh counter by 1 at the rising edge of the mclk. R/W 0x0 [4] Out of Order Scheduling 0x0 = Disables 0x1 = Enables The embedded scheduler enables out-of order operation to improve SDRAM utilization R/W 0x1 [3:0] Should be zero 0x0 1-26 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.2 Memory Control Register (MemControl, R/W, Address = 0xF000_0004, 0xF140_0004) MEMCONTROL Bit Description R/W Reserved bl num_chip mem_width mem_type add_lat_pall dsref_en tp_en [31:23] Should be zero [22:20] Memory Burst Length R/W 0x0 = Reserved 0x1 = 2 0x2 = 4 0x3 = 8 0x4 = 16 0x5 ~ 0x7 = Reserved In case of DDR2/ LPDDR2, the controller only supports burst length 4. [19:16] Number of Memory chips R/W 0x0 = 1 chip 0x1 = 2 chips 0x2 ~ 0xf = Reserved [15:12] Width of Memory Data Bus R/W 0x0 = Reserved 0x1 = 16-bit 0x2 = 32-bit 0x3 ~ 0xf = Reserved [11:8] Type of Memory R/W 0x0 = Reserved 0x1 = LPDDR 0x2 = LPDDR2 0x3 = Reserved 0x4 = DDR2 0x5 ~ 0xf = Reserved [7:6] Additional Latency for PALL R/W 0x0 = 0 cycle 0x1 = 1 cycle 0x2 = 2 cycle 0x3 = 3 cycle If all banks precharge command is issued, the latency of precharging will be tRP + add_lat_pall [5] Dynamic Self Refresh R/W 0x0 = Disables 0x1 = Enables Refer to “1.2.3.3 . Dynamic Self Refresh” [4] Timeout Precharge R/W 0x0 = Disables 0x1 = Enables If tp_en is enabled, it automatically precharges an open bank after a specified amount of mclk cycles (if no access has been made in between the cycles) in an open page policy. If PrechConfig.tp_cnt bit-field is set, it specifies the amount of Initial State 0x0 0x2 0x0 0x2 0x1 0x0 0x0 0x0 1-27 S5PV210_UM 1 DRAM CONTROLLER MEMCONTROL dpwrdn_type dpwrdn_en clk_stop_en Bit Description mclk cycles to wait until timeout precharge precharges the open bank. Refer to “1.2.4.2 . Timeout Precharge”. [3:2] Type of Dynamic Power Down 0x0 = Active/ Precharge power down 0x1 = Force precharge power down 0x2 ~ 0x3 = Reserved Refer to “1.2.3.2 Dynamic Power Down”. [1] Dynamic Power Down 0x0 = Disable 0x1 = Enable [0] Dynamic Clock Control 0x0 = Always running 0x1 = Stops during idle periods Refer to “1.2.3.4 . Clock Stop”. R/W Initial State R/W 0x0 R/W 0x0 R/W 0x0 1-28 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.3 Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xF000_0008, 0xF140_0008) MEMCONFIG0 chip_base chip_mask chip_map chip_col chip_row chip_bank Bit Description R/W [31:24] AXI Base Address R/W AXI base address [31:24] = chip_base For example, if chip_base = 0x20, then AXI base address of memory chip0 becomes 0x2000_0000. [23:16] AXI Base Address Mask R/W Upper address bit mask to determine AXI offset address of memory chip0. 0 = Corresponding address bit is not to be used for comparison 1 = Corresponding address bit is to be used for comparison For example, if chip_mask = 0xF8, then AXI offset address becomes 0x0000_0000 ~ 0x07FF_FFFF. If AXI base address of memory chip0 is 0x2000_0000, then memory chip0 has an address range of 0x2000_0000 ~ 0x27FF_FFFF. [15:12] Address Mapping Method (AXI to Memory) R/W 0x0 = Linear ({bank, row, column, width}), 0x1 = Interleaved ({row, bank, column, width}), 0x2 = Mixed1 ( if bank(MSB) = 1’b1, {1’b1, bank(except MSB), row, column, width} else {1’b0, row, bank(except MSB), column, width}), 0x3 ~ 0xf = Reserved [11:8] Number of Column Address Bits R/W 0x0 = Reserved 0x1 = 8 bits 0x2 = 9 bits 0x3 = 10 bits 0x4 = 11 bits 0x5 ~ 0xf = Reserved [7:4] Number of Row Address Bits R/W 0x0 = 12 bits 0x1 = 13 bits 0x2 = 14 bits 0x3 = 15 bits 0x4 ~ 0xf = Reserved [3:0] Number of Banks R/W 0x0 = 1 bank 0x1 = 2 banks 0x2 = 4 banks 0x3 = 8 banks 0x4 ~ 0xf = Reserved Initial State DMC0: 0x20 DMC1: 0X40 DMC0: 0xF0 DMC1: 0xE0 0x0 0x3 0x1 0x2 1-29 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.4 Memory Chip1 Configuration Register (MemConfig1, R/W, Address = 0xF000_000C, 0xF140_000C) MEMCONFIG1 chip_base chip_mask chip_map chip_col chip_row chip_bank Bit Description R/W [31:24] AXI Base Address R/W AXI base address [31:24] = chip_base, For example, if chip_base = 0x28, then AXI base address of chip1 becomes 0x2800_0000. [23:16] AXI Base Address Mask R/W Upper address bit mask to determine AXI offset address of memory chip1. 0 = Corresponding address bit is not to be used for comparison 1 = Corresponding address bit is to be used for comparison For example, if chip_mask = 0xF0, then AXI offset address becomes 0x0000_0000 ~ 0x0FFF_FFFF. If AXI base address of memory chip1 is 0x2800_0000, then memory chip1 has an address range of 0x2800_0000 ~ 0x37FF_FFFF. [15:12] Address Mapping Method (AXI to memory) R/W 0x0 = Linear ({bank, row, column, width}), 0x1 = Interleaved ({row, bank, column, width}), 0x2 = Mixed1 ( if bank(MSB) = 1’b1, {1’b1, bank(except MSB), row, column, width} else {1’b0, row, bank(except MSB), column, width}), 0x3 ~ 0xf = Reserved [11:8] Number of Column Address Bits R/W 0x0 = Reserved 0x1 = 8 bits 0x2 = 9 bits 0x3 = 10 bits 0x4 = 11 bits 0x5 ~ 0xf = Reserved [7:4] Number of Row Address Bits R/W 0x0 = 12 bits 0x1 = 13 bits 0x2 = 14 bits 0x3 = 15 bits 0x4 ~ 0xf = Reserved [3:0] Number of Banks R/W 0x0 = 1 bank 0x1 = 2 banks 0x2 = 4 banks 0x3 = 8 banks 0x4 ~ 0xf = Reserved Initial State DMC0: 0x30 DMC1: 0x60 DMC0: 0xF0 DMC1: 0xE0 0x0 0x3 0x1 0x2 1-30 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.5 Memory Direct Command Register (DirectCmd, R/W, Address = 0xF000_0010, 0xF140_0010) DIRECTCMD Reserved cmd_type Reserved cmd_chip cmd_bank cmd_addr Bit Description R/W [31:28] Should be zero. [27:24] Type of Direct Command R/W 0x0 = MRS/EMRS (mode register setting), 0x1 = PALL (all banks precharge), 0x2 = PRE (per bank precharge), 0x3 = DPD (deep power down), 0x4 = REFS (self refresh), 0x5 = REFA (auto refresh), 0x6 = CKEL (active/ precharge power down), 0x7 = NOP (exit from active/ precharge power down or deep power down, 0x8 = REFSX (exit from self refresh) 0x9 = MRR (mode register reading), 0xa ~ 0xf = Reserved If a direct command is issued, AXI masters must not access memory. It is strongly recommended to check the command queue’s state by Concontrol.chip0/1_empty before issuing a direct command You must disable dynamic power down, dynamic self refresh and force precharge function (MemControl register). MRS/EMRS and MRR commands should be issued if all banks are in idle state. If MRS/EMRS and MRR is issued to LPDDR2, the CA pins must be mapped as follows. MA[7:0] = {cmd_addr[1:0], cmd_bank[2:0], cmd_addr[12:10]}, OP[7:0] = cmd_addr[9:2] [23:21] Should be zero. [20] Chip Number to send the direct command to R/W 0 = Chip 0 1 = Chip 1 [18:16] Related Bank Address when issuing a direct command R/W To send a direct command to a chip, additional information such as the bank address is required. This register is used in such situations. [14:0] Related Address Value when issuing a direct command R/W To send a direct command to a chip, additional information such as the address is required. This register is used in such situations. Initial State 0x0 0x0 0x0 0x0 0x0 0x0 1-31 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.6 Precharge Policy Configuration Register (PrechConfig, R/W, Address = 0xF000_0014, 0xF140_0014) PRECHCONFIG Bit Description R/W tp_cnt Reserved chip1_policy chip0_policy [31:24] Timeout Precharge Cycles R/W 0xn = n mclk cycles, If the timeout precharge function (MemControl.tp_en) is enabled and the timeout precharge counter becomes zero, the controller forces the activated memory bank into the precharged state. Refer to “1.2.4.2 . Timeout Precharge”. [23:16] Should be zero [15:8] Memory Chip1 Precharge Bank Selective Policy R/W 0x0 = Open page policy 0x1 = Close page (auto precharge) policy chip1_policy[n], n is the bank number of chip1. Open Page Policy: After a READ or WRITE, the row accessed before is left open. Close Page (Auto Precharge) Policy: Right after a READ or WRITE command, memory devices automatically precharges the bank. This is a bank selective precharge policy. For example, if chip1_policy[2] is 0x0, bank2 of chip1 has an open page policy and if chip1_policy[6] is 0x1, bank6 of chip1 has a close page policy. Refer to “1.2.4.1 Bank Selective Precharge Policy”. [7:0] Memory chip0 Precharge Bank Selective Policy R/W 0x0 = open page policy 0x1 = close page (auto precharge) policy Chip0_policy[n], n is the bank number of chip0. This is for memory chip0. Initial State 0xFF 0x0 0x0 0x0 1-32 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.7 PHY Control0 Register (PhyControl0, R/W, Address = 0xF000_0018, 0xF140_0018) PHYCONTROL0 Bit Description R/W ctrl_force ctrl_inc ctrl_start_point dqs_delay ctrl_dfdqs ctrl_half ctrl_dll_on ctrl_start [31:24] DLL Force Delay R/W This field is used instead of ctrl_lock_value[9:2] from the PHY DLL when ctrl_dll_on is LOW. (i.e. If the DLL is off, this field is used to generate 270' clock and shift DQS by 90'.) [23:16] DLL Delay Increment R/W Increase the amount of start point This value should be 0x10 [15:8] DLL Lock Start Point R/W Initial DLL lock start point. This is the number of delay cells and is the start point where "DLL" start tracing to lock. Calculates Initial delay time by multiplying the unit delay of delay cell and this value. This value should be 0x10 [7:4] Delay Cycles for DQS Cleaning R/W This register is to enable PHY to clean incoming DQS signals delayed by external circumstances. If DQS is coming with read latency plus n mclk cycles, this registers must be set to n mclk cycles. [3] Differential DQS R/W If enabled, PHY generates differential DQS out signals for write command and receives differential DQS input signals for read command. This function is used in case of DDR2/LPDDR2. [2] DLL Low Speed R/W HIGH active signal to activate the low speed mode for DLL. If this bit is set, DLL runs at low speed (80MHz ~ 100MHz) [1] DLL On R/W HIGH active start signal to activate the DLL. This signal should be kept HIGH for normal operation. If this signal becomes LOW, DLL is turned off and ctrl_clock and ctrl_flock become HIGH. This bit should be set before ctrl_start is set to turn on the DLL [0] DLL Start R/W HIGH active start signal to initiate the DLL run and lock. This signal should be kept HIGH during normal operation. If this signal becomes LOW, DLL stops running. To re-run DLL, make this signal HIGH again. In the case of re-running, DLL loses previous lock information. Before ctrl_start is set, make sure that ctrl_dll_on is HIGH. Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 1-33 S5PV210_UM 1 DRAM CONTROLLER rst_n Power up & PLL lock ctrl_start_point ctrl_inc ctrl_start D L L Lo ck St art ctrl_clock DLL Lock Memory Initialization W rite c trl _s ta rt_p o in t v al ue Wri te ctr l_ in c va lu e D LL L oc ke d ctrl_flock ctrl_lock_value ctrl_dll_on ctrl_force R ea d & W rit e DLL on DLL off ctrl_resync R ef res h Pe ri od R ef res h CMD R e fre sh C MD NOTE: PHY DLL Lock Procedure Memory Acess R efre s h CMD Figure 1-11 DLL Lock Procedure Use DLL to compensate Process, Voltage and Temperature (PVT) condition. Therefore DLL should not be turnedoff for reliable operation except for the case of frequency scaling (To lower frequency scaling is permitted) 1-34 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.8 PHY Control1 Register (PhyControl1, R/W, Address = 0xF000_001C, 0xF140_001C) PHYCONTROL1 Bit Description R/W Reserved ctrl_offsetd drv_type ctrl_offsetc ctrl_ref fp_resync ctrl_shiftc [31:23] Should be zero [22:16] This field is for debug purpose. R/W If this field is fixed, field value must not be changed during operation. This value is valid after ctrl_resync becomes HIGH and LOW. offset amount for 270' clock generation ctrl_offsetd[6] = 1 : (tFS : fine step delay) 270' delay amount - ctrl_offsetd[5:0] x tFS ctrl_offsetd[6] = 0 : 270' delay amount + ctrl_offsetd[5:0] x tFS [15] Driving Type of Bidirectional Pins in Idle State 0x0 = Drive all to zeros 0x1 = Pull down all If CAS or read data latency is 2, this register must not set be to 0x0. [14:8] Delay Offset for DQS Cleaning R/W Gate offset amount for DDR. If this field is fixed, this value should not be changed during operation. This value is valid after ctrl_resync becomes HIGH and LOW. ctrl_offsetc[6] = 1 : (tFS : fine step delay) GATEout delay amount - ctrl_offsetc[5:0] x tFS ctrl_offsetc[6] = 0 : GATEout delay amount + ctrl_offsetc[5:0] x tFS [7:4] Reference Count for DLL Lock Confirmation R/W [3] Force DLL Resynchronization R/W [2:0] Phase Delay for DQS Cleaning R/W GATEout signal delay amount for DDR. If this field is fixed, this value should not be changed during operation. This value is valid after ctrl_resync becomes HIGH and LOW. 0x0 = T/128 (2.8125' shift) 0x1 = T/64 (5.625' shift) 0x2 = T/32 (11.25' shift) 0x3 = T/16 (22.5' shift) 0x4 = T/8 (45' shift) 0x5 = T/4 (90' shift) 0x6 = T/2 (180' shift) 0x7 = T (360' shift) Recommended values according to memory type : 0x5 when LPDDR/LPDDR2 @200MHz 0x6 when DDR2 @200MHz Initial State 0x0 0x0 0x0 0x0 0x4 0x0 0x0 1-35 S5PV210_UM Use DQS cleaning to remove high-Z state of DQS. 1 DRAM CONTROLLER Board PKG Bonding I/O Core D Q FF CK ct r l_ g at e C o n tr o l le r PHY IO io _ ck _o u t t D L io _g a t e _ ou t d e la y lin e D i o _g a te _i n to e a ch da t a sli ce IO tA tA IO C IO tE I /O d a t a _ sl ic e de l ay li n e DQS C le a n io _ d q s_ i n tE IO Q D IO FF CK CK tB tC tD GA TEO F ee d -b ac k B A GA TEI M e m ory A DCT/ IO CM D C K /C K IO B tA C tB tC tD DQS IO DQ IO NOTE: DQS Cleaning Scheme Figure 1-12 Board Level Connection Diagram for DQS Cleaning • tA: I/O output delay • tB: Package bonding wire delay • tC: Package board delay • tD: Board trace delay • tE: I/O input delay • tDL: delay line delay • tAC: minimum CK-to-DQS timing of LPDDR/DDR2 memory spec. (LPDDR ≈ 1ns, DDR2 ≈ 0.5tCK) • tFS: Fine step delay in DLL, From PhyStatus0.ctrl_lock_value[9:0], tFS is calculated. − If ctrl_half = 0, tFS = tCK / ctrl_lock_value[9:0]. − If ctrl_half = 1, tFS = tCK*0.5 / ctrl_lock_value[9:0] ctrl_shiftc controls PVT-independent delay amount(tF) and ctrl_offsetc controls PVT-dependent delay amount(tV). 1-36 S5PV210_UM 1 DRAM CONTROLLER Delay line programming value; tDL ≈tAC + 2*(tB+tC+tD). tDL = tF (ctrl_shiftc[2:0]) + tV (ctrl_offsetc[6:0]) If ctrl_shiftc[2:0] is 3'b100, tF is Tperiod/8 ≈ 0.9375ns. (If tCK is 7.5ns) If ctrl_offsetc[6:0] is 7'b00010_00, tV is 0.320ns(40ps * 8) @ worst case (if tFS = 40ps) Therefore tDL = tF + tV = 0.9375ns + 0.320ns = 1.2575ns Figure 1-13 DQS Cleaning for LPDDR if tAC Min Figure 1-14 DQS Cleaning for LPDDR if tAC Max 1-37 S5PV210_UM 1 DRAM CONTROLLER Figure 1-15 DQS cleaning for DDR2 1.4.1.9 Dynamic Power Down Configuration Register (PwrdnConfig, R/W, Address = 0xF000_0028, 0xF140_0028) PWRDNCONFIG Bit Description dsref_cyc Reserved dpwrdn_cyc [31:16] [15:8] [7:0] Number of Cycles for Dynamic Self Refresh Entry 0xn = n aclk cycles, If the command queue is empty for n+1 cycles, the controller forces the memory device into self refresh state. Refer to “1.2.3.3 . Dynamic Self Refresh”. Should be zero Number of Cycles for Dynamic Power Down Entry 0xn = n aclk cycles, If the command queue is empty for n+1 cycles, the controller forces the memory device into active/ precharge power down state. Refer to “1.2.3.2 Dynamic Power Down”. R/W Initial State R/W 0xFFFF 0x0 R/W 0xFF 1-38 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.10 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address = 0xF000_0030, 0xF140_0030) TIMINGAREF Reserved t_refi Bit Description R/W [31:16] Should be zero [15:0] Average Periodic Refresh Interval R/W Should be minimum memory tREFI (all bank) < t_refi * T(mclk), For example, for the all bank refresh period of 7.8us, and an mclk frequency of 133MHz, the following value should be programmed : 7.8 us * 133 MHz = 1038 Initial State 0x0 0x40E 1.4.1.11 AC Timing Register for the Row of memory (TimingRow, R/W, Address = 0xF000_0034, 0xF140_0034) TIMINGROW t_rfc t_rrd t_rp t_rcd t_rc t_ras Bit Description R/W [31:24] Auto refresh to Active / Auto refresh command period, in R/W cycles t_rfc * T(mclk) should be greater than or equal to the minimum value of memory tRFC. [23:20] Active bank A to Active bank B delay, in cycles R/W t_rrd * T(mclk) should be greater than or equal to the minimum value of memory tRRD. [19:16] Precharge command period, in cycles R/W t_rp * T(mclk) should be greater than or equal to the minimum value of memory tRP. [15:12] Active to Read or Write delay, in cycles R/W t_rcd * T(mclk) should be greater than or equal to the minimum value of memory tRCD [11:6] Active to Active period, in cycles R/W t_rc * T(mclk) should be greater than or equal to the minimum value of memory tRC. [5:0] Active to Precharge command period, in cycles R/W t_ras * T(mclk) should be greater than or equal to the minimum value of memory tRAS. Initial State 0xF 0x2 0x3 0x3 0xA 0x6 1-39 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.12 AC Timing Register for the Data of memory (TimingData, R/W, Address = 0xF000_0038, 0xF140_0038) TIMINGDATA t_wtr t_wr t_rtp cl Reserved wl Reserved rl Bit Description R/W [31:28] Internal write to Read command delay, in cycles R/W t_wtr * T(mclk) should be greater than or equal to the minimum value of memory tWTR. t_wtr must be 0x1 in case of JEDEC LPDDR. [27:24] Write recovery time, in cycles R/W t_wr * T(mclk) should be greater than or equal to the minimum value of memory tWR [23:20] Internal read to Precharge command delay, in cycles R/W t_rtp * T(mclk) should be greater than or equal to the minimum value of memory tRTP. t_rtp must be 0x1 in case of JEDEC LPDDR. [19:16] CAS Latency (for LPDDR/DDR/DDR2), in cycles R/W cl should be greater than or equal to the minimum value of memory CL. [15:12] Should be zero [11:8] Write data latency (for only LPDDR2), in cycles R/W wl should be greater than or equal to the minimum value of memory WL [7:4] Should be zero [3:0] Read data latency (for only LPDDR2), in cycles R/W rl should be greater than or equal to the minimum value of memory RL Initial State 0x1 0x2 0x1 0x3 0x0 0x2 0x0 0x4 NOTE: * tDAL (Auto precharge write recovery + precharge time) = t_wr + t_rp (automatically calculated) 1-40 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.13 AC Timing Register for the Power mode of Memory (TimingPower, R/W, Address = 0xF000_003C, 0xF140_003C) TIMINGPOWER Bit Description R/W Reserved t_faw t_xsr t_xp t_cke t_mrd [31:30] Should be zero [29:24] Four Active Window R/W t_faw * T(mclk) should be greater than or equal to the minimum value of memory tFAW [23:16] Self refresh exit power down to next valid command delay, in R/W cycles t_xsr * T(mclk) should be greater than or equal to the minimum value of memory tXSR. In case of DDR/DDR2, this value should be greater than or equal to the minimum value of memory tXSRD. [15:8] Exit power down to next valid command delay, in cycles R/W t_xp * T(mclk) should be greater than or equal to the minimum value of memory tXP [7:4] CKE minimum pulse width (minimum power down mode R/W duration), in cycles t_cke should be greater than or equal to the minimum value of memory tCKE [3:0] Mode Register Set command period, in cycles R/W t_mrd should be greater than or equal to the minimum value of memory tMRD. Initial State 0x0 0xE 0x1B 0x4 0x2 0x2 1-41 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.14 PHY Status Register (PhyStatus, Read Only, Address=0xF000_0040, 0xF140_0040) PHYSTATUS0 Bit Description R/W Reserved [31:14] Should be zero ctrl_lock_value [13:4] Locked Delay R Locked delay line encoding value ctrl_lock_value[9:2]: number of delay cells for coarse lock ctrl_lock_value[1:0]: control value for fine lock Reserved [3] Should be zero ctrl_locked [2] DLL Lock R 0 = Unlocks DLL 1 = Locks DLL ctrl_flock [1] Fine Lock Information R It is indicated that DLL is locked with fine resolution, “phase offset error” is less than 80ps. ctrl_clock [0] Coarse Lock Information R It is indicated that DLL changes step delays of the “delay line” and “phase offset error” is less than 160ps. Initial State 0x0 0x0 0x0 0x0 0xX 0xX 1-42 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.15 Memory Chip0 Status Register (Chip0Status, Read Only, Address = 0xF000_0048, 0xF140_0048) CHIP0STATUS Bit Description bank7_state bank6_state bank5_state bank4_state bank3_state bank2_state bank1_state bank0_state [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] The current state of bank 7 of memory chip0 The current state of bank 6 of memory chip0 The current state of bank 5 of memory chip0 The current state of bank 4 of memory chip0 The current state of bank 3 of memory chip0 The current state of bank 2 of memory chip0 The current state of bank 1 of memory chip0 The current state of bank 0 of memory chip0 0x0 = Idle (precharged) 0x1 = MRS/EMRS 0x2 = Deep power down 0x3 = Self refresh 0x4 = Auto refresh 0x5 = Precharge power down 0x6 = Row active 0x7 = Active power down 0x8 = Write 0x9 = Write with auto precharge 0xA = Read 0xB = Read with auto precharge 0xC = Burst stop 0xD = Precharging 0xE = MRR 0xF = Reserved R/W Initial State R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 1-43 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.16 Memory Chip1 Status Register (Chip1Status, Read Only, Address=0xF000_004C, 0xF140_004C) CHIP1STATUS Bit Description bank7_state bank6_state bank5_state bank4_state bank3_state bank2_state bank1_state bank0_state [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] The current state of bank 7 of SDRAM chip1 The current state of bank 6 of SDRAM chip1 The current state of bank 5 of SDRAM chip1 The current state of bank 4 of SDRAM chip1 The current state of bank 3 of SDRAM chip1 The current state of bank 2 of SDRAM chip1 The current state of bank 1 of SDRAM chip1 The current state of bank 0 of SDRAM chip1 0x0 = Idle (precharged) 0x1 = MRS/EMRS 0x2 = Deep power down 0x3 = Self refresh 0x4 = Auto refresh 0x5 = Precharge power down 0x6 = Row active 0x7 = Active power down 0x8 = Write 0x9 = Write with auto precharge 0xA = Read 0xB = Read with auto precharge 0xC = Burst stop 0xD = Precharging 0xE = MRR 0xF = Reserved R/W Initial State R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 1-44 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.17 Counter Status Register for the Auto Refresh (ArefStatus, R, Address=0xF000_0050, 0xF140_0050) AREFSTATUS Reserved aref_cnt Bit Description [31:16] [15:0] Should be zero Current Value of Auto Refresh Counter Shows the current value of all bank auto refresh counter. This is updated if a new t_refi is programmed into the TimingAref register and decreases by 1 at the rising edge of mclk. An all bank auto refresh command is issued to memory device and this counter is reloaded with TimingAref.t_ref if this becomes zero. R/W Initial State 0x0 R 0xFFFF 1.4.1.18 Memory Mode Registers Status Register (MrStatus, Read Only, Address = 0xF000_0054, 0xF140_0054) MRSTATUS Reserved mr_status Bit Description [31:8] Should be zero [7:0] Mode Registers Status R/W Initial State 0x0 R 0x0 1.4.1.19 PHY Test Register 0 (PhyTest0, R/W, Address = 0xF000_0058, 0xF140_0058) PHYTEST0 ctrl_fb_cnt4 Reserved ctrl_fb_oky Reserved ctrl_fb_err Reserved ctrl_fb_start Bit Description [31:24] [23:21] [20:16] [15:13] [12:8] [7:5] [4:0] Count Value for Control Channel Should be zero ctrl_fb_okay[4] : Error status for control, ctrl_fb_okay[3:0] : Error status for data Should be zero ctrl_fb_err[4] : Error for control, ctrl_fb_err[3:0] : Error for data Should be zero ctrl_fb_start[4] : Start for control, ctrl_fb_start[3:0] : Start for data R/W Initial State R 0x0 0x0 R 0x0 0x0 R 0x0 0x0 R/W 0x0 1-45 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.20 PHY Test Register 1 (PhyTest1, R, Address = 0xF000_005C, 0xF140_005C) PHYTEST1 ctrl_fb_cnt3 ctrl_fb_cnt2 ctrl_fb_cnt1 ctrl_fb_cnt0 Bit Description [31:24] [23:16] [15:8] [7:0] Count value for data3 channel Count value for data2 channel Count value for data1 channels Count value for data0 channel R/W Initial State R 0x0 R 0x0 R 0x0 R 0x0 1.4.1.21 Quality of Service Control Register n (QosControl n, R/W, Address = 0xF000_0060 + 8n (n=0~15, integer), 0xF140_0060 + 8n (n=0~15, integer) QOSCONTROLn Bit Description Reserved qos_cnt qos_cnt_f [31:28] [27:16] [15:4] Should be zero QoS Cycles 0xn = n aclk cycles The matched ARID/AWID uses this value for its timeout counters instead of ConControl.timeout_cnt. QoS cycles for fast request R/W Initial State 0x0 R/W 0x0 R/W 0x0 0xn = n aclk cycles Reserved qos_en When Concontrol.qos_fast_en is enabled and input pin qos_fast[n] bit is 1, this qos_cnt_f value is loaded to the timeout counter. [3:1] Should be zero [0] QoS Enable 0x0 = Disable 0x1 = Enable If this function is enabled, its timeout counter works and the ARID/AWID is masked with QoSConfig.qos_mask and compared with QoSConfig.qos_id 0x0 R/W 0x0 NOTE: If qos fast is enabled, the QoSControl(n) of 4,5,6,7,8,9,10,11,13,14 & 15 are dedicated to each specific IP that is refer to Table 1-1. 1-46 S5PV210_UM 1 DRAM CONTROLLER 1.4.1.22 Quality of Service Configuration Register n (QosConfig n, R/W, Address = 0xF000_0064 + 8n (n=0~15, integer), 0xF140_0064 + 8n (n=0~15, integer) QOSCONFIGn qos_mask qos_id Bit Description R/W [31:16] QoS Mask Bits R/W This is used to mask the incoming ARID/AWID to compare with the qos_id. For example, to have 0b00110XX000 IDs the same QoS, the 4th and 5th bits must be masked. Therefore, qos_mask would be 0b1111100111. [15:0] QoS ID R/W This is used to compare with the masked ARID/AWID to check whether its timeout counter should be used for QoS. After applying the qos_mask to these ARID/AWID, it is compared with qos_id. The qos_id would be 0b001100_0000 using the example above. Comparing the masked ID, if the result is equal to the qos_id, then the QoSControl0.qos_cnt is applied to this ARID/AWID transaction for timeout. Don’t care bits must be assigned zeros. Initial State 0x0 0x0 NOTE: If qos fast is enabled, the QoSConfig(n) of 4,5,6,7,8,9,10,11,13,14 & 15 are dedicated to each specific IP, and it’s qos_id & qos_mask value should be set proper to each IP’s Transaction ID 1-47 S5PV210_UM 1 DRAM CONTROLLER Table 1-2 Master Transaction ID for DMC0 in S5PV210 Transaction Master ARM MFC G3D FIMC0 FIMC1 FIMC2 JPEG ROT FIMD_W0 FIMD_W4 FIMD_W1 FIMD_W2 FIMD_W3 G2D VP MIXER_GRP0 MIXER_GRP1 SSYS GSYS ESYS0 ESYS1 CSYS USYS AUDIO PDMA0 PDMA1 MDMA R/W Transaction ID R/W 14’b000_0000_0xxx_x000 R/W 14’b000_000x_xxx0_0001 R/W 14’b000_000x_xxx1_0001 R/W 14’b00x_xxx0_0000_0010 R/W 14’b00x_xxx0_0100_0010 R/W 14’b00x_xxx0_1000_0010 R/W 14’b000_0000_1100_0010 R/W 14’b000_0001_0000_0010 R/W 14’b000_0000_0001_0010 FIMD window 0 R/W 14’b000_0001_0001_0010 FIMD window 4 R/W 14’b000_0000_0101_0010 FIMD window 1 R/W 14’b000_0001_0101_0010 FIMD window 2 R/W 14’b000_0010_0101_0010 FIMD window 3 R/W 14'b000_xxxx_1001_0010 R/W 14’b000_0xxx_x010_0010 R/W 14’b000_0000_0110_0010 R/W 14’b000_0000_1110_0010 R/W 14’b000_0000_0011_0010 R/W 14’b000_0000_0111_0010 R/W 14’b000_0000_1011_0010 R/W 14’b000_0000_1111_0010 R/W 14’b000_0001_0011_0010 R/W 14’b000_0001_0111_0010 R/W 14’b000_0001_1011_0010 R/W 14’b0xx_xx01_1111_0010 R/W 14’b0xx_xx11_1111_0010 R/W 14’b000_00xx_xx11_1010 Description NOTE: Transaction ID in S5PV210 1-48 S5PV210_UM 1 DRAM CONTROLLER Transaction Master ARM MFC G3D FIMC0 FIMC1 FIMC2 JPEG ROT FIMD_W0 FIMD_W4 FIMD_W1 FIMD_W2 FIMD_W3 G2D VP MIXER_GRP0 MIXER_GRP1 SSYS GSYS ESYS0 ESYS1 CSYS USYS AUDIO PDMA0 PDMA1 MDMA Table 1-3 Master Transaction ID for DMC1 in S5PV210 R/W Transaction ID R/W 14’b000_0000_0xxx_x000 R/W 14’b000_000x_xxx0_1100 R/W 14’b000_000x_xxx1_0100 R/W 14’b00x_xxx0_0000_1011 R/W 14’b00x_xxx0_0100_1011 R/W 14’b00x_xxx0_1000_1011 R/W 14’b000_0000_1100_1011 R/W 14’b000_0001_0000_1011 R/W 14’b000_0000_0001_1011 FIMD window 0 R/W 14’b000_0001_0001_1011 FIMD window 4 R/W 14’b000_0000_0101_1011 FIMD window 1 R/W 14’b000_0001_0101_1011 FIMD window 2 R/W 14’b000_0010_0101_1011 FIMD window 3 R/W 14'b000_xxxx_1001_0011 R/W 14’b000_0xxx_x010_1011 R/W 14’b000_0000_0110_1011 R/W 14’b000_0000_1110_1011 R/W 14’b000_0000_0011_0011 R/W 14’b000_0000_0111_0011 R/W 14’b000_0000_1011_0011 R/W 14’b000_0000_1111_0011 R/W 14’b000_0001_0011_0011 R/W 14’b000_0001_0111_0011 R/W 14’b000_0001_1011_0011 R/W 14’b0xx_xx01_1111_0011 R/W 14’b0xx_xx11_1111_0011 R/W 14’b000_00xx_xx11_1011 Description 1-49 S5PV210_UM 2 SROM CONTROLLER 2 SROM CONTROLLER 2.1 SROM CONTROLLER 2.1.1 OVERVIEW OF SROM CONTROLLER S5PV210 SROM Controller (SROMC) support external 8 / 16-bit NOR Flash/ PROM/ SRAM memory. S5PV210 SROM Controller supports 6-bank memory up to maximum 16Mbyte per bank. 2.1.2 KEY FEATURES OF SROM CONTROLLER • Supports SRAM, various ROMs and NOR flash memory • Supports only 8 or 16-bit data bus (only 16-bit data bus for BANK0) • Address space: Up to 16MB per Bank • Supports 6 banks. • Fixed memory bank start address • External wait to extend the bus cycle • Supports byte and half-word access for external memory 2.1.3 BLOCK DIAGRAM OF SROM CONTROLLER AHB I/F for SROM SFR SROM DECODER AHB I/F for SROM MEM SFR CONTROL & STATE MACHINE SROM I/F SIGNAL GENERATO N SROM MEM I/F DATA PATH Figure 2-1 Block Diagram of SROM Controller 2-1 S5PV210_UM 2.2 FUNCTIONAL DESCRIPTION SROM Controller supports SROM interface for Bank0 to Bank5. 2 SROM CONTROLLER 2.2.1 NWAIT PIN OPERATION If the WAIT signal corresponding to each memory bank is enabled, the external nWAIT pin should prolong the duration of nOE while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high. The nWE signal has the same relation with nOE signal. HCLK ADDR nGCS nOE nWAIT DATA(R) Tacs Tcos tRC Tacc=4 Delayed Sampling nWAIT Figure 2-2 SROM Controller nWAIT Timing Diagram 2-2 S5PV210_UM 2.2.2 PROGRAMMABLE ACCESS CYCLE 2 SROM CONTROLLER HCLK ADDR nGCS nOE DATA(R) Tacs ADDRESS 0 ADDRESS 1 Tcos Tcoh Tacc DATA 0 Tacp DATA 1 Tacs = 2-cycle Tcos = 2-cycle Tacc = 3-cycle Tacp = 2-cycle Tcoh = 2-cycle Tcah = 2-cycle Tcah Figure 2-3 SROM Controller Read Timing Diagram HCLK ADDR nGCS nWE DATA(W) Tacs ADDRESS Tcos DATA Tacs = 2-cycle Tcos = 2-cycle Tacc = 3-cycle Tacc Tcoh Tacp = don’t care Tcoh = 2-cycle Tcah = 2-cycle Tcah Figure 2-4 SROM Controller Write Timing Diagram NOTE: Page mode is only supported on read cycle. 2-3 S5PV210_UM 2 SROM CONTROLLER 2.3 I/O DESCRIPTION Signal nGCS[5:0] ADDR[22:0] nOE nWE nWBE/nBE [1:0] DATA[15:0] nWAIT I/O Output Output Output Output Output In/Out Input Description Bank selection signal SROM Address bus SROM Output Enable SROM Write Enable SROM Byte write Enable / Byte Enable SROM Data bus SROM Wait input Pad Xm0CSn[5:0] Xm0ADDR[22:0] Xm0OEn Xm0WEn Xm0BEn Xm0DATA[15:0] Xm0WAITn Type muxed muxed muxed muxed muxed muxed muxed 2-4 S5PV210_UM 2 SROM CONTROLLER 2.4 REGISTER DESCRIPTION 2.4.1 REGISTER MAP Register SROM_BW SROM_BC0 SROM_BC1 SROM_BC2 SROM_BC3 SROM_BC4 SROM_BC5 Address 0xE800_0000 0xE800_0004 0xE800_0008 0xE800_000C 0xE800_0010 0xE800_0014 0xE800_0018 R/W Description R/W Specifies the SROM Bus width & wait control R/W Specifies the SROM Bank0 control register R/W Specifies the SROM Bank1 control register R/W Specifies the SROM Bank2 control register R/W Specifies the SROM Bank3 control register R/W Specifies the SROM Bank4 control register R/W Specifies the SROM Bank5 control register Reset Value 0x0000_0009 0x000F_0000 0x000F_0000 0x000F_0000 0x000F_0000 0x000F_0000 0x000F_0000 2-5 S5PV210_UM 2 SROM CONTROLLER 2.4.1.1 SROM Bus Width & Wait Control Register (SROM_BW, R/W, Address = 0x0000_0000) SROM_BW Reserved ByteEnable5 WaitEnable5 AddrMode5 DataWidth5 ByteEnable4 WaitEnable4 AddrMode4 DataWidth4 ByteEnable3 WaitEnable3 AddrMode3 Bit [31:24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] Description Reserved nWBE / nBE(for UB/LB) control for Memory Bank5 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] Wait enable control for Memory Bank5 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR Base for Memory Bank5 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth5 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) Data bus width control for Memory Bank5 0 = 8-bit 1 = 16-bit nWBE / nBE(for UB/LB) control for Memory Bank4 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] Wait enable control for Memory Bank4 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR Base for Memory Bank4 0= SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1= SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth4 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) Data bus width control for Memory Bank4 0 = 8-bit 1 = 16-bit nWBE / nBE(for UB/LB) control for Memory Bank3 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] Wait enable control for Memory Bank3 0 = Disables WAIT 1 = Enables WAIT Select SROM ADDR Base for Memory Bank3 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) Initial State 0 0 0 0 0 0 0 0 0 0 0 0 2-6 S5PV210_UM 2 SROM CONTROLLER SROM_BW DataWidth3 ByteEnable2 WaitEnable2 AddrMode2 DataWidth2 ByteEnable1 WaitEnable1 AddrMode1 DataWidth1 ByteEnable0 WaitEnable0 Bit Description 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth3 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) [12] Data bus width control for Memory Bank3 0 = 8-bit 1 = 16-bit [11] nWBE / nBE(for UB/LB) control for Memory Bank2 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] [10] Wait enable control for Memory Bank2 0 = Disables WAIT 1 = Enables WAIT [9] Select SROM ADDR Base for Memory Bank2 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth2 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) [8] Data bus width control for Memory Bank2 0 = 8-bit 1 = 16-bit [7] nWBE / nBE(for UB/LB) control for Memory Bank1 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] [6] Wait enable control for Memory Bank1 0 = Disables WAIT 1 = Enables WAIT [5] Select SROM ADDR Base for Memory Bank1 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth1 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) [4] Data bus width control for Memory Bank1 0 = 8-bit 1 = 16-bit [3] nWBE / nBE(for UB/LB) control for Memory Bank0 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0] [2] Wait enable control for Memory Bank0 0 = Disables WAIT Initial State 0 0 0 0 0 0 0 0 0 1 0 2-7 S5PV210_UM 2 SROM CONTROLLER SROM_BW AddrMode0 DataWidth0 Bit 1 = Enables WAIT Description [1] Select SROM ADDR Base for Memory Bank0 0 = SROM_ADDR is Half-word base address. (SROM_ADDR[22:0] <= HADDR[23:1]) 1 = SROM_ADDR is byte base address (SROM_ADDR[22:0] <= HADDR[22:0]) Note: When DataWidth0 is “0”, SROM_ADDR is byte base address. (Ignored this bit.) [0] Data bus width control for Memory Bank0 1 = 16-bit Note: Only 16bit for bank0, can’t change Initial State 0 1 2-8 S5PV210_UM 2.4.1.2 SROM Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2) • SROM_BC0, R/W, Address = 0xE800_0004 • SROM_BC1, R/W, Address = 0xE800_0008 • SROM_BC2, R/W, Address = 0xE800_000C • SROM_BC3, R/W, Address = 0xE800_0010 • SROM_BC4, R/W, Address = 0xE800_0014 • SROM_BC5, R/W, Address = 0xE800_0018 SROM_BCn Tacs Tcos Reserved Tacc Bit Description [31:28] Adress set-up before nGCS 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks Note: More 1~2 cycles according to bus i/f status [27:24] Chip selection set-up before nOE 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks [23:21] Reserved [20:16] Access cycle 00000 = 1 clock 00001 = 2 clocks 00001 = 3 clocks 00010 = 4 clocks …………. 11100 = 29 clocks 11101 = 30 clocks 11110 = 31 clocks 11111 = 32 clocks 2 SROM CONTROLLER Initial State 0000 0000 000 01111 2-9 S5PV210_UM SROM_BCn Tcoh Tcah Tacp Reserved PMC Bit [15:12] [11:8] [7:4] [3:2] [1:0] Description Chip selection hold on nOE 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks Address holding time after nGCSn 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks Note: More 1~2 cycles according to bus i/f status Page mode access cycle @ Page mode 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks …………. 1100 = 12 clocks 1101 = 13 clocks 1110 = 14 clocks 1111 = 15 clocks Reserved Page mode configuration 00 = Normal (1 data) 01 = 4 data 10 = Reserved 11 = Reserved 2 SROM CONTROLLER Initial State 0000 0000 0000 00 2-10 S5PV210_UM 3 ONENAND CONTROLLER 3 ONENAND CONTROLLER 3.1 OVERVIEW OF ONENAND CONTROLLER S5PV210 supports external 16-bit bus for OneNAND and Flex-OneNAND memory devices. The OneNAND controller supports asynchronous and synchronous read/ write bus operations. It also integrates its own dedicated DMA engine and microsequencer to accelerate the operations of OneNAND memory device. 3.2 KEY FEATURES OF ONENAND CONTROLLER The key features of OneNAND controller include: • Supports data buffering (32-entry read prefetch FIFO and 32-entry posted write FIFO) where necessary, to achieve maximum performance. • Supports asynchronous FIFOs for matching speed between OneNAND flash memory and AHB system bus interface. • Supports both asynchronous and synchronous read/ write of the OneNAND flash memory device. • Programmable burst transfer size of the OneNAND flash memory interface (4, 8, 16, 32, 1024 and continuous). • Supports 16-bit data path to memory and 32-bit data path to the AHB system bus interface. • Supports multiple memory devices in the OneNAND family (OneNAND and Flex-OneNAND) with a single bus interface protocol. • Supports up to two OneNAND devices. All the chip selects are available by default. • Supports the warm reset function of the OneNAND device. The advanced features of OneNAND controller include: • Supports internal dedicated DMA engine to maximize the data transfer speed between OneNAND flash and system memory. 3-1 S5PV210_UM 3 ONENAND CONTROLLER 3.3 CONTROLLER USAGE EXPECTATIONS The OneNAND controller is designed with the following expectations: • Supported transfer types are SINGLE/ INCR4/ INCR8/ INCR16 transactions. • Supported transfer sizes are WORD/ HALFWORD transactions for the OneNAND slave. • Supported transfer sizes are WORD transactions for the register slave. 3-2 S5PV210_UM 3 ONENAND CONTROLLER 3.4 FUNCTIONAL DESCRIPTION OF ONENAND By default, the ARM processor directly accesses OneNAND. In addition, internal DMA engine can access OneNAND. For example, the internal DMA engine transfers data between OneNAND DataRAM and system main memory (like DRAM) without wasting the processing power of ARM processor. These additional hardware resources can be utilized to maximize the performance and minimize the usage of ARM processor for OneNAND read/ write/ copy operation. 3.4.1 BLOCK DIAGRAM OF ONEENAND CONTROLLER Figure 3-1 shows the block diagram of OneNAND controller that comprises one AHB slave port (A), one AHB master port (B), and one OneNAND interface port (C). Figure 3-1 OneNAND Controller Block Diagram (A: AHB Slave Port, B: AHB Master Port, and C: OneNAND Interface Port) 3-3 S5PV210_UM 3 ONENAND CONTROLLER 3.4.2 CLOCK CONTROL The OneNAND controller has three clock source inputs, namely, HCLK, OA_CLK_OUT, and O_CLK_2X. Bus system interface gets AHB bus clock, HCLK. On the other hand, OneNAND controller core gets one controller clock input, O_CLK_2X. It generates OneNAND memory clock output, OA_CLK_OUT, which is supplied to external OneNAND flash memory. The clock frequency of OA_CLK_OUT is half the clock frequency of O_CLK_2X. You can set the frequency ratio in special function register (SFR) of the system controller. For more information about clock ratio setting, refer to Section 2.3, "Clock Controller".To change the clock frequency ratio, perform these steps: 1. Check OneNAND Read Write Busy (ORWB) bit of OneNAND Interface Status (ONENAND_IF_STATUS) register to ensure there are no memory transfers. 2. Switch the clock ratio in the SFR of system controller. 3. Write to the clock ratio register. 4. Start the memory accesses. 3.4.3 INITIALIZATION PROTOCOL 3.4.3.1 Power On After power on, the S5PV210 and OneNAND controller are initialized. Thereafter, OneNAND controller will automatically configure itself to work with the OneNAND flash memory devices. This automatic configuration can be achieved using one of the following: • Mux-type OneNAND or Demux-type OneNAND • Asynchronous read and write mode • Read prefetch disabled 3.4.3.2 Boot Code On initialization, the OneNAND flash device will automatically load boot data in boot buffer. To access this code, one or more reads to the boot address can be issued. This operation will happen asynchronously until both OneNAND devices and OneNAND controller are configured to run in synchronous mode. To configure both OneNAND devices and OneNAND controller, update the OneNAND Interface Control (ONENAND_IF_CTRL) register. 3-4 S5PV210_UM 3 ONENAND CONTROLLER 3.5 MEMORY MAP OneNAND controller occupies 16MB address space in the system address space. The base address of OneNAND controller is configured by 0xB00000000 in S5PV210. OneNAND controller has three AHB slaves, namely: 1. OneNAND interface 2. Control registers The three AHB slaves share 16MB address space. OneNAND controller assigns 2MB address space to each AHB slave. Therefore, total 8MB address space is used to address the four AHB slaves. Other 8MB address space is reserved for future use. For more information about address space, refer to Table 3-1. The OneNAND interface provides eight chip-enable (nCE) signals to support up to eight OneNAND devices. As shown in Table 3-1, 2MB address space is shared by eight OneNAND devices. Figure 3-2 shows the data path when OneNAND device is accessed by the external AHB master (like ARM processor). If AHB address offset from the base address belongs to the bottom 2MB address space, this AHB transaction goes to the OneNAND interface to access the OneNAND device. Each OneNAND device has its own 128KB address space and this 128KB address space is used to address the BootRAM, DataRAM, and registers of the OneNAND device. As shown in Figure 3-2, the ARM processor can access OneNAND device directly through the OneNAND interface. The ARM processor can read or write all OneNAND address area (BootRAM, DataRAM, or registers). If block erase, page program, and page load operations are required, then the following must be set: • OneNAND device address registers − Start Address 1 (device address offset: 0x1E200) − Start Address 2 (device address offset: 0x1E202) − Start Address 8 (device address offset: 0x1E20E) • Start Buffer registers (device address offset: 0x1E400) 3-5 S5PV210_UM 3 ONENAND CONTROLLER The corresponding commands must be issued to the device command register (Command register (device address offset: 0x1E440)). For more information about the OneNAND device memory map, refer to Figure 3-3 that shows the data path when the external AHB master accesses control registers. Table 3-1 OneNAND Controller Memory Map OneNAND Interface Reserved Microsequencer Memory Control Registers Reserved OneNAND Controller Address (Start) 0xB0000000 0xB0020000 0xB0040000 0xB0060000 0xB0080000 0xB00A0000 0xB00C0000 0xB00E0000 0xB0100000 0xB0120000 0xB0140000 0xB0160000 0xB0180000 0xB01A0000 0xB01C0000 0xB01E0000 0xB0200000 0xB0400000 0xB0600000 0xB0800000 OneNAND Controller Address (End) 0xB001FFFF 0xB003FFFF 0xB005FFFF 0xB007FFFF 0xB009FFFF 0xB00BFFFF 0xB00DFFFF 0xB00FFFFF 0xB011FFFF 0xB013FFFF 0xB015FFFF 0xB017FFFF 0xB019FFFF 0xB01BFFFF 0xB01DFFFF 0xB01FFFFF 0xB03FFFFF 0xB05FFFFF 0xB07FFFFF 0xB0FFFFFF Window Size Note 128KB OneNAND nCE[0] (For more information about OneNAND Chip #0 address map, refer to Table 3-3. 128KB Reserved for future use 128KB OneNAND nCE[1] 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 128KB Reserved for future use 2MB Reserved for future use 2MB 8kB SRAM 2MB 8MB 32-bit Registers Reserved for future use 3-6 S5PV210_UM 3 ONENAND CONTROLLER Main area (64KBytes) Spare area (8KBytes) Reserved (24KBytes) Reserved (8KBytes) Reserved (16KBytes) Registers (8KBytes) Table 3-2 OneNAND Chip #0 (nCE[0]) Address Map (If the OneNAND device is Connected to nCE[0]) OneNAND Controller Address (Start) 0xB0000000 0xB0000200 0xB0000400 0xB0000600 0xB0000800 0xB0000A00 0xB0000C00 0xB0000E00 0xB0001000 0xB0001200 0xB0001400 0xB0010000 0xB0010010 0xB0010020 0xB0010030 0xB0010040 0xB0010050 0xB0010060 0xB0010070 0xB0010080 0xB0010090 0xB00100A0 0xB0012000 OneNAND Controller Address (End) Size (Total 128KBytes) Description 0xB00001FE 0xB00003FE 0xB00005FE 0xB00007FE 0xB00009FE 0xB0000BFE 0xB0000DFE 0xB0000FFE 0xB00011FE 0xB00013FE 0xB000FFFE 0xB001000E 0xB001001E 0xB001002E 0xB001003E 0xB001004E 0xB001005E 0xB001006E 0xB001007E 0xB001008E 0xB001009E 0xB0011FFE 0xB0017FFE 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 59K 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 8032B 24KB 1KB 4KB 59K 32B 128B 8032B 24KB BootRAM Main sector0 BootRAM Main sector1 DataRAM Main page0/ sector0 DataRAM Main page0/ sector1 DataRAM Main page0/ sector2 DataRAM Main page0/ sector3 DataRAM Main page1/ sector0 DataRAM Main page1/ sector1 DataRAM Main page1/ sector2 DataRAM Main page1/ sector3 Reserved BootRAM Spare sector0 BootRAM Spare sector1 DataRAM Spare page0/ sector0 DataRAM Spare page0/ sector1 DataRAM Spare page0/ sector2 DataRAM Spare page0/ sector3 DataRAM Spare page1/ sector0 DataRAM Spare page1/ sector1 DataRAM Spare page1/ sector2 DataRAM Spare page1/ sector3 Reserved Reserved 0xB0018000 0xB0019FFE 8KB 8KB Reserved 0xB001A000 0xB001DFFE 16KB 16KB Reserved 0xB001E000 0xB001FFFE 8KB 8KB Registers 3-7 S5PV210_UM 3 ONENAND CONTROLLER Main area (64KBytes) Spare area (8KBytes) Reserved (24KBytes) Reserved (8KBytes) Reserved (16KBytes) Registers (8KBytes) Table 3-3 Flex-OneNAND Chip #0 (nCE[0]) Address Map (If the Flex-OneNAND device is Connected to nCE[0]) OneNAND Controller Address (Start) 0xB0000000 0xB0000200 0xB0000400 0xB0000600 0xB0000800 0xB0000A00 0xB0000C00 0xB0000E00 0xB0001000 0xB0001200 0xB0001400 0xB0010000 0xB0010010 0xB0010020 0xB0010030 0xB0010040 0xB0010050 0xB0010060 0xB0010070 0xB0010080 0xB0010090 0xB00100A0 0xB0012000 OneNAND Controller Address (End) 0xB00001FE 0xB00003FE 0xB00005FE 0xB00007FE 0xB00009FE 0xB0000BFE 0xB0000DFE 0xB0000FFE 0xB00011FE 0xB00013FE 0xB000FFFE 0xB001000E 0xB001001E 0xB001002E 0xB001003E 0xB001004E 0xB001005E 0xB001006E 0xB001007E 0xB001008E 0xB001009E 0xB0011FFE 0xB0017FFE Size (Total 128KBytes) Description 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 59K 16B 16B 16B 16B 16B 16B 16B 16B 16B 16B 8032B 24KB 1KB 4KB 59K 32B 128B 8032B 24KB BootRAM Main sector0 BootRAM Main sector1 DataRAM Main n-th page/ sector0 DataRAM Main n-th page/ sector1 DataRAM Main n-th page/ sector2 DataRAM Main n-th page/ sector3 DataRAM Main n-th page/ sector4 DataRAM Main n-th page/ sector5 DataRAM Main n-th page/ sector6 DataRAM Main n-th page/ sector7 Reserved BootRAM Spare sector0 BootRAM Spare sector1 DataRAM Spare n-th page/ sector0 DataRAM Spare n-th page/ sector1 DataRAM Spare n-th page/ sector2 DataRAM Spare n-th page/ sector3 DataRAM Spare n-th page/ sector4 DataRAM Spare n-th page/ sector5 DataRAM Spare n-th page/ sector6 DataRAM Spare n-th page/ sector7 Reserved Reserved 0xB0018000 0xB0019FFE 8KB 8KB Reserved 0xB001A000 0xB001DFFE 16KB 16KB Reserved 0xB001E000 0xB001FFFE 8KB 8KB Registers 3-8 S5PV210_UM 3 ONENAND CONTROLLER Figure 3-2 OneNAND Accesses (OneNAND Controller Address: 0xB0000000 ~ 0xB01FFFFF) by the External AHB Master (ARM Processor) 3-9 S5PV210_UM 3 ONENAND CONTROLLER Figure 3-3 Control Register Accesses (OneNAND Controller Address: 0xB0600000 ~ 0xB07FFFFF) by the External AHB Master (ARM Processor) 3-10 S5PV210_UM 3 ONENAND CONTROLLER 3.6 ONENAND INTERFACE 3.6.1 OVERVIEW OF ONENAND INTERFACE The OneNAND interface is an AHB slave module that provides an interface for the AHB master to access OneNAND devices on the internal AHB bus of OneNAND controller. For example, 1. The external AHB master can access OneNAND device through the AHB2AHB bridge and OneNAND interface (Figure 3-2) 2. The internal AHB master can access the OneNAND deice through the OneNAND interface (Figure 3-10 and Figure 3-9). The OneNAND interface slave has few AHB transaction constraints. It supports HSIZE of HALFWORD and WORD transactions on the AHB system bus. It also supports HBURST of SINGLE, INCR4, INCR8, and INCR16. This interface outputs HRESP of ERROR at the first data phase of AHB transaction. Both OneNAND and Flex-OneNAND flash memory devices are supported by OneNAND controller. Both mux-type and demux-type OneNAND devices are supported by OneNAND controller. Use SFR to configure the OneNAND device type. Both asynchronous and synchronous read/ write operations are supported by OneNAND controller for OneNAND flash memory devices. This mode of read/ write operations can be configured through the SFR. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register. To connect OneNAND controller with eight OneNAND devices, eight chip enable (CE) signals are provided. Asynchronous FIFOs are used for speed matching between OneNAND flash memory and AHB system bus. The clock frequency relationship between OneNAND device and AHB system bus is fully asynchronous. The OneNAND device supports only 16-bit data bus width. On the other hand, the OneNAND controller supports 32-bit AHB data bus width. While reading data from OneNAND device and writing that data to FIFO, the OneNAND interface automatically resolves the data bus width mismatch. This interface also resolves the data bus width mismatch while reading data from FIFO and writing that data to OneNAND device. 32-entry read prefetch FIFO supports read prefetching. This feature accelerates the sequential read performance of OneNAND BootRAM and DataRAM areas. Use SFR to enable or disable this feature. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register. To accelerate the write performance of the OneNAND DataRAM area, perform posted write. This feature is implemented using the 32-entry posted write FIFOs. Use SFR to configure the strobe signals’ timing for asynchronous read/write operation. For more information, refer to the OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register. Use SFR to configure the burst read write latency (BRWL) for the synchronous read/ write operation with 3, 4, 5, 6, and 7. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register. The OneNAND interface does NOT support the initial read write latency control through the RDY pin of the OneNAND device. The Burst Length (BL) also can be configured to 4-/ 8-/16-/ 32-/ 1024-burst and continuous burst through the SFR. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register. 3-11 S5PV210_UM 3 ONENAND CONTROLLER To reduce the power consumption for OneNAND interface and drive the clock output to OneNAND device, the gated clock output is supported. If this feature is enabled, the OneNAND device clock is toggled only if the OneNAND device is accessed to perform read or write operation. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register. The warm reset operation is supported. For more information, refer to the OneNAND Interface Command (ONENAND_IF_CMD) register. 3.6.2 ONENAND INTERFACE CONFIGURATION There are two configuration registers for the OneNAND Interface, namely: 1. OneNAND Interface Control (OneNAND_IF_CTRL) register 2. OneNAND Interface Asynchronous Timing Control (OneNAND_IF_ASYNC_TIMING_CTRL) register. The OneNAND Interface Control Register (ONENAND_IF_CTRL) register holds configuration bits for following: − MUX : Mux/ Demux select (mux-type or demux-type) − GCE: Gated-clock enable (enable or disable) − RPE: Read prefetch enable (enable or disable) − RM : Read mode (synchronous vs. asynchronous) − BRWL: Burst read write latency (3 clock, … , 7 clock) − BL: Burst length (4-/8-/16-/32-/1024-burst or continuous) − HF: High frequency (enable or disable) − WM : Write mode (synchronous vs. asynchronous) The OneNAND controller requires a correct operation sequence to change the OneNAND Interface Control (ONENAND_IF_CTRL) register value. To update this register the system software must follow the specific sequence illustrated in Figure 3-4. Note that the OneNAND Read Write Busy (ORWB) bit must be checked to confirm that there is no bus transaction in progress on the OneNAND interface before write new configuration to the OneNAND Interface Control (ONENAND_IF_CTRL) register. Also note that the System Configuration 1 registers of all the OneNAND devices must be set by the same configuration value though the OneNAND interface supports multiple (up to eight) OneNAND devices. The OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register holds configuration bits for following: − WHL: nWE signal high length (1 clock, … , 15 clock) − WLL: nWE signal low length (1 clock, … , 15 clock) − OHL: nOE signal high length (1 clock, … , 15 clock) − OLL: nOE signal low length (2 clock, … , 16 clock) The OneNAND controller requires a correct operation sequence to change the OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register value. To update this register the system software must follow the specific sequence illustrated in Figure 3-6. Note that the OneNAND Read Write Busy(ORWB) bit must be checked to confirm that there is no bus transaction in progress on the OneNAND interface before write new configuration to the OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register. 3-12 S5PV210_UM 3 ONENAND CONTROLLER ONENAND_IF_CTRL Reg ister U pdate Start Read ONENAN D_IF_STAT US NO ORWB = 0 ? YES Write New Configu ratio n t o th e “System Con figu rat io n1” Reg ister o f All th e On eNAND Devices Conn ect ed with th e On eN AND Cont ro ller (NOTE) Read One Dummy Half word f ro m an On eNAND Device Write New Con figu rat ion to ONENAND_IF_CT RL On eN AND In terface is Ready to Accep t t he AHB Read/Wit e Requ st to Access t he On eNAND Device ONENAND_IF_CTRL Reg ist er Upd ate Complete Figure 3-4 ONENAND_IF_CTRL (OneNAND Interface Control) Register Update Flow NOTE: This dummy halfword read is necessary to confirm that new configuration value is written to the OneNAND device before updating the ONENAND_IF_CTRL register. We recommend 0x0000 for this dummy read address from OneNAND device. 3-13 S5PV210_UM 3 ONENAND CONTROLLER Figure 3-5 ONENAND_IF_ASYNC_TIMING_CTRL (OneNAND Interface Async Timing Control) Register Update Flow 3-14 S5PV210_UM 3 ONENAND CONTROLLER 3.6.3 ONENAND DEVICE INTERRUPT HANDLING The OneNAND interface provides two mechanisms to check the INT pin status of the OneNAND devices, namely: 1. Polling the INTD (INT Done) bits of the OneNAND Interface Status (ONENAND_IF_STATUS) register 2. Interrupt-driven checking. The OneNAND controller requires that the system software should follow the correct operation sequence to check the INT pin status of the OneNAND device as shown in Figure 3-6 and Figure 3-7. Note that the OneNAND interface detects only the rising edge of the INT pin. Therefore, set the INT Polarity (INTpol) bit of the System Configuration 1 register (device address offset: 0x1E442) of the OneNAND device to 1. Figure 3-8 illustrates the timing diagram of the INT pin of the OneNAND device and related SFR signals. The Figure 3-8 is described below: • T1: New command (ex. load, program or erase) is written to the OneNAND device Command register • T2: OneNAND device INT pin rising edge occurs • T3: The INTD[x] bit of the OneNAND Interface Status (ONENAND_IF_STATUS) register is set to 1. • T4: OSINTD[x] (OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status (INTC_ONENAND_STATUS) register is set to 1 because OMINTD[x] (OneNAND Mask INT Done) bit of the Interrupt Controller OneNAND Mask (INTC_ONENAND_MASK) is deasserted to 0. Simultaneously, ARM_IRQ pin is asserted to high to generate an interrupt to the system • T5: The system software (ex. ISR (Interrupt Service Routine)) writes 1 to the INTC[x] bit of the OneNAND Interface Command (ONENAND_IF_CMD) register to clear the INTD[x] bit of the OneNAND Interface Status (ONENAND_IF_STATUS) register. • T6: The INTD[x] bit of the OneNAND Interface Status (ONENAND_IF_STATUS) register is cleared to 0. T7: The system software (ex. ISR (Interrupt Service Routine)) writes 1 to the OCINTD[x] bit (OneNAND Clear INT Done) of the Interrupt Controller OneNAND Clear (INTC_ONENAND_CLR) register to clear the OSINTD[x] (OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status (INTC_ONENAND_STATUS) register. • T8: The OSINTD[x] (OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status (INTC_ONENAND_STATUS) register is cleared to 0. Simultaneously, ARM_IRQ pin is deasserted to low. 3-15 S5PV210_UM 3 ONENAND CONTROLLER Figure 3-6 OneNAND Device INT Pin Rising Edge Wait Operations with a Polling Method Figure 3-7 OneNAND Device INT Pin Rising Edge Wait Operations with an Interrupt-Driven Method 3-16 S5PV210_UM 3 ONENAND CONTROLLER Figure 3-8 OneNAND Device INT Pin Rising Edge Wait Operation Timing Diagram DMA Engin 3-17 S5PV210_UM 3 ONENAND CONTROLLER 3.6.4 DMA ENGINE OVERVIEW To perform data transfer between internal AHB memory (such as OneNAND device) and external AHB memory (such as SDRAM), the internal dedicated DMA engine is embedded in the OneNAND controller. The DMA engine supports single transfer, 4-/ 8-/ 16-burst transfer with 8-/ 16-/ 32-bit data width on the AHB. In addition, it supports even unaligned transfers. The DMA engine has two AHB master ports. One port can access OneNAND or control registers on the internal AHB. The other port can access SDRAM on the external AHB (AHB backbone), as shown in Figure 3-9. Each port has 32-entry synchronous FIFOs as data buffer, through which two AHB masters of the DMA engine transfer data. This helps to improve the performance of data transfer, because two AHB master ports of DMA engine access the source and destination memories at the same time. Note that a general DMA engine has a single AHB master port, and the memory accesses to the source and destination memories are serialized. Figure 3-9 Data Transfer between OneNAND and External Memory by the Internal DMA Engine (OneNAND Read/ Write) 3-18 S5PV210_UM 3 ONENAND CONTROLLER 3.6.5 DMA OPERATION Set DMA control registers to configure the DMA operation. The DMA engine begins to transfer data after setting the Transfer Run (TR) bit of the DMA Transfer Command (DMA_TRANS_CMD) register to 1. The Transfer Busy (TB) bit of the DMA Transfer Status (DMA_TRANS_STATUS) register is maintained as 1 during the data transfer to indicate that the DMA engine is busy. After the DMA operation has been finished successfully, the Transfer Done (TD) bit of the DMA Transfer Status (DMA_TRANS_STATUS) register is set to 1 to notify the system software that the DMA operation is completed. There are two methods, with which the system software waits for the completion of the DMA operation and determines the DMA engine’s completion status. • DMA operation with a polling method • DMA operation with an interrupt-driven method 3.6.5.1 DMA Operation With a Polling Method The system software polls DMA_TRANS_STATUS register to check the status of the DMA engine. The DMA engine sets the TD bit of the DMA Transfer Status (DMA_TRANS_STATUS) register to 1 when the data transfer is completed. It sets the Transfer Error (TE) bit of the DMA Transfer Status (DMA_TRANS_STATUS) register to 1 when an error occurs during the transfer. Figure 3-10 Internal DMA Engine Operations with a Polling Method 3-19 S5PV210_UM 3 ONENAND CONTROLLER 3.6.5.2 DMA Operation With an Interrupt-driven Method The DMA engine asserts system interrupt signal for the transfer done or the transfer error event YES DMA Start Read INTC_DMA_MASK DMTD = 0 && DMTE = 0 ? NO Write 0 to both DMTD and DMTE bits of INTC_DMA_MASK Write to DMA_SRC_ADDR Write to DMA_SRC_CFG Write to DMA_DST_ADDR Write to DMA_DST_CFG Write to DMA_TRANS_SIZE Write to DMA_TRANS_DIR Write 1 to TR bit of DMA_TRANS_CMD NO ARM_IRQ = 1 ? YES ARM Processor Jumps to the ISR (Interrupt Service Routine) System ISR Start Read INTC_DMA_STATUS DSTD = 1 ? NO YES Write 1 to TDC bit of DMA_TRANS_CMD Write 1 to DCTD bit of INTC_DMA_CLR System ISR Complete DMA Complete DSTE = 1 ? NO Process Interrupt Events Other Than DMA YES System ISR Complete Write 1 to TEC bit of DMA_TRANS_CMD Write 1 to DCTE bit of INTC_DMA_CLR System ISR Complete DMA Complete with Errors Figure 3-11 Internal DMA Engine Operations with an Interrupt-Driven Method 3-20 S5PV210_UM 3 ONENAND CONTROLLER 3.7 I/O INTERFACE Signal ADDR[15:0] DQ[15:0] nCE[1:0] nWE nOE INT[1:0] nAVD nRP CLK I/O Description I/O Address Bus outputs, during memory read/ write address phase Data Bus outputs address during memory read/ write I/O address phase, inputs data during memory read data phase and outputs data during memory write data phase. Chip Selects are activated when the address of a memory is within the address region of each bank. O Xm0CSn[3:2] can be assigned to either SROMC or OneNAND controller by System Controller SFR setting. Active LOW. O Write Enable indicates that the current bus cycle is a write cycle. Active LOW. O Output Enable indicates that the current bus cycle is a read cycle. Active LOW. Interrupt inputs from OneNAND memory Bank 0, 1. I If OneNAND memory is not used, these signals should be tied to zero. Address valid output. In the POP products, address and O data are multiplexed. Xm0ADDRVALID indicate when the bus is used for address. Active LOW. System reset output for OneNAND memory. O Active LOW. O Static memory clock for synchronous static memory devices. PAD Xm0ADDR [15:0] Xm0DATA [15:0] Xm0CSn [5:4] Xm0WEn Xm0OEn Xm0FRnB [5:4] Xm0FCLE Xm0FWEn Xm0FALE NOTE: The INT pin of each OneNAND Device must be pulled up by a 4.7K-ohm external pull-up resistor. Type muxed muxed muxed muxed muxed muxed muxed muxed muxed 3-21 S5PV210_UM 3 ONENAND CONTROLLER 3.8 REGISTER DESCRIPTION 3.8.1 REGISTER MAP Register ONENAND_IF_CTRL Address R/W Description 0xB060_0100 R/W OneNAND Interface Control register ONENAND_IF_CMD 0xB060_0104 W OneNAND Interface Command register ONENAND_IF_ASYNC_TIMI 0xB060_0108 R/W OneNAND Interface Async. Timing NG_CTRL Control register ONENAND_IF_STATUS 0xB060_010C R OneNAND Interface Status Register DMA_SRC_ADDR 0xB060_0400 R/W DMA Source Address Register DMA_SRC_CFG 0xB060_0404 R/W DMA Source Configuration Register DMA_DST_ADDR 0xB060_0408 R/W DMA Destination Address Register DMA_DST_CFG 0xB060_040C R/W DMA Destination Configuration Register DMA_TRANS_SIZE 0xB060_0414 R/W DMA Transfer Size Register DMA_TRANS_CMD 0xB060_0418 W DMA Transfer Command Register DMA_TRANS_STATUS 0xB060_041C R DMA Transfer Status Register DMA_TRANS_DIR 0xB060_0420 R/W DMA Transfer Direction Register INTC_DMA_CLR 0xB060_1004 W Interrupt Controller DMA Clear Register INTC_ONENAND_CLR 0xB060_1008 W Interrupt Controller OneNAND Clear Register INTC_DMA_MASK 0xB060_1024 R/W Interrupt Controller DMA Mask Register INTC_ONENAND_MASK 0xB06_01028 R/W Interrupt Controller OneNAND Mask Register INTC_DMA_PEND 0xB060_1044 R Interrupt Controller DMA Pending Register INTC_ONENAND_PEND 0xB060_1048 R Interrupt Controller OneNAND Pending Register INTC_DMA_STATUS 0xB060_1064 R Interrupt Controller DMA Status Register INTC_ONENAND_STATUS 0xB060_1068 R Interrupt Controller OneNAND Status Register Reset Value 0x80004000 or 0x00004000 0x00000000 0x00003415 0x00FF0000 0x00000000 0x00040002 0x00000000 0x00040002 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01010000 0x000000FF 0x00000000 0x000000FF 0x00000000 0x00000000 3-22 S5PV210_UM 3 ONENAND CONTROLLER 3.8.2 ONENAND INTERFACE REGISTER 3.8.2.1 OneNAND Interface Control Register (ONENAND_IF_CTRL, R/W, Address = 0xB060_0100) ONENAND_ IF_CTRL MUX GCE RPE RM BRWL Bit Description [31] [30:27] [26] [25:18] [17] [16] [15] [14:12] Mux or Demux OneNAND Type Select OneNAND interface supports both Demux and Mux type OneNAND devices. This bit is used to specify whether OneNAND is Demux or Mux type. The value of OM pins determines the reset value of this bit If the OM pins are of Demuxed type OneNAND boot, the reset value of this bit is 1. Otherwise, the reset value is 0. (For more information, refer to Chapter 2.6. Booting Sequence) 0b = Mux type 1b = Demux type Reserved Gated Clock Enable To reduce power consumption, OneNAND interface supports gated clock method. If this bit is set, the OneNAND clock toggles only during OneNAND read/ write execution time. 0b = Disable 1b = Enable Reserved Enables Read Prefetch. This bit is used to enable or disable the read prefetch operation of the OneNAND interface. 0b = Read Prefetch Disable 1b = Read Prefetch Enable OneNAND Interface has its own read prefetch FIFO. This FIFO is implemented as an asynchronous FIFO of 32-bit x 32-depth between AHB and OneNAND clock domains. If the sequential read access is dominant, prefetch next read data in advance to increase the OneNAND read bandwidth. If Read Prefetch Enable (RPE) bit is set to 1 OneNAND interface will start to prefetch read data when it receives AHB read request. If the read prefetch FIFO becomes full during the prefetch operation, the prefetch operation will be stopped immediately. As soon as the read prefetch FIFO is ready to accept the next read data by successive AHB read operation, the prefetch operation will be resumed. If the read prefetch address reaches 1-KByte aligned address during the prefetch operation, the prefetch operation will be stopped. Reserved Read Mode This bit is used to select the OneNAND read mode between synchronous and asynchronous modes. 0b = Asynchronous Read 1b = Synchronous Read Burst Read Write Latency Initial State 1b or 0b 0b 0b 0b 100b 3-23 S5PV210_UM 3 ONENAND CONTROLLER ONENAND_ IF_CTRL BL HF WM - Bit Description [11:9] [8:3] [2] [1] [0] This bit is used to select the burst read/ write latency between 3 clocks and 7 clocks. BRWL (burst read write latency) bits specify the access latency in the burst read/ write transfer for the initial access. Note that these bits are valid only for the synchronous read/ write operation. 000b = Reserved 001b = Reserved 010b = Reserved 011b = 3 CLK 100b = 4 CLK 101b = 5 CLK 110b = 6 CLK 111b = 7 CLK Burst Length These bits are used to select the burst length among 4-burst, 8burst, 16-burst, 32-burst, 1024-burst and continuous-burst. Note that BL (burst length) bits are valid only for the synchronous read/ write operation. 000b = Continuous-Burst 001b = 4-Burst 010b = 8-Burst 011b = 16-Burst 100b = 32-Burst 101b = 1024-Burst 110b = Reserved 111b = Reserved Reserved High Frequency This bit is used to enable or disable the high frequency mode. High frequency (HF) bit must be set when the OneNAND clock frequency is more than 66MHz. 0b = High Frequency Disable (66MHz and under) 1b = High Frequency Enable (Over 66MHz) Write Mode This bit is used to select the OneNAND write mode between synchronous and asynchronous modes. 0b = Asynchronous Write 1b = Synchronous Write Reserved Initial State 000b 0b 0b - 3-24 S5PV210_UM 3 ONENAND CONTROLLER C LK 2x (I nternal) C LK nC E nAVD nOE nWE AD DR DQ R DY Figure 3-12 ONENAND Interface Synchronous Read Timing 1 C lock 1 C lock 3 C locks Valid A ddress BL C locks BR WL C locks 1-st 2- nd 3-r d BL -th W rite D ata Write Data W rite D ata W rite D ata Figure 3-13 OneNAND Interface Synchronous Write Timing 3-25 S5PV210_UM 3 ONENAND CONTROLLER 3.8.2.2 OneNAND Interface Command Register (ONENAND_IF_CMD, W, Address = 0xB060_0104) ONENAND_ IF_CMD - INTC Bit Description [31:18] [17:16] Reserved OneNAND INT Done Clear When this bit is set to 1, the INTD (OneNAND INT done) bit flag of the OneNAND Interface Status Register (ONENAND_IF_STATUS) is cleared to 0. INTC[0] 1b = Device[0] OneNAND Interrupt Done clear 0b = no operation Initial State 00h INTC[1] 1b = Device[1] OneNAND Interrupt Done clear 0b = no operation - [15:2] Reserved - WR [1] Warm Reset 0b For OneNAND warm reset, writing 1 to this bit makes nRP pin of OneNAND device low during 20 CLK. It is mandatory to assert the nRP pin to zero for warm reset during tRP time and the tRP time is more than 200ns. After warm reset, it should wait for tREADY1 to access the OneNAND BootRAM and tREADY2 time is needed to issue the new command. tREADY1 time and tREADY2 time are at least 5us and 500us respectively. 1b = nPR pin low for 20 CLK 0b = no operation - [0] Reserved - 3-26 S5PV210_UM 3 ONENAND CONTROLLER 3.8.2.3 OneNAND Interface Async Timing Control Register (ONENAND_IF_ASYNC_TIMING_CTRL, R/W, Address = 0xB060_0108) ONENAND_IF_ ASYNC_TIMING _CTRL WHL WLL OHL OLL Bit [31:16] [15:12] [11:8] [7:4] [3:0] Description Reserved nWE High Length nWE signal is held to high for WHL clock time at OneNAND asynchronous read/ write execution. 0000b = Reserved (Do NOT Use) 0001b = 1 CLK 0010b = 2 CLK ... ... 1111b = 15 CLK nWE Low Length nWE signal is held to low for WLL clock time at OneNAND asynchronous read/ write execution. 0000b = Reserved (Do NOT Use) 0001b = 1 CLK 0010b = 2 CLK ... ... 1111b = 15 CLK nOE High Length nOE signal is held to high for OHL clock time at OneNAND asynchronous read/ write execution. 0000b = Reserved (Do NOT Use) 0001b = 1 CLK 0010b = 2 CLK ... ... 1111b = 15 CLK nOE Low Length nOE signal is held to low for (OLL+2) clock time at OneNAND asynchronous read/ write execution. 0000b = 2 CLK 0001b = 3 CLK 0010b = 4 CLK ... ... 1110b = 16 CLK 1111b : Reserved (Do NOT Use) Initial State 3h 4h 1h 5h 3-27 S5PV210_UM 3 ONENAND CONTROLLER C LK 2x (I nternal) C LK nC E nAVD nO E nWE AD D R DQ R DY Async. Read D ata Sampling Timing 1 C lock 1 C lock 1 C lock (nOE Low Length + 2) C locks nOE H igh Length Cl oc k s V alid Address tAC C Valid R ead Dat a Figure 3-14 OneNAND Interface Asynchronous Read Timing C LK 2x (I nternal) C LK nC E nAVD nOE nWE AD D R DQ R DY 1 C lock 1 C lock 1 C lock V alid Address nWE Low Lengt h C locks nWE High Length Clocks Valid Write Dat a Figure 3-15 OneNAND Interface Asynchronous Write Timing 3-28 S5PV210_UM 3 ONENAND CONTROLLER 3.8.2.4 OneNAND Interface Status Register (ONENAND_IF_STATUS, R, Address = 0xB060_010C) ONENAND_ IF_STATUS INTD Bit Description [31:24] [23:18] [17:16] Reserved Reserved OneNAND INT Done This status is used to check whether the OneNAND command execution is complete or not. Check whether the OneNAND INT pin’s rising edge has been occurred or not after issuing a command to the OneNAND to notify command execution completion. This bit is set to 1 automatically when OneNAND INT pin’s rising edge is detected and is cleared to 0 when INTC (OneNAND INT Done Clear) bit of OneNAND Interface Command Register (ONENAND_IF_CMD) is set to 1. INTD[0] 1b = Device[0] OneNAND Interrupt Done 0b = No operation Initial State 111111b 11b ORWB INTD[1] 1b = Device[1] OneNAND Interrupt Done 0b = No operation [15:1] Reserved - [0] OneNAND Read Write Busy 0b This status is used to check whether the OneNAND interface is busy or not to read or write data. This bit must be checked to confirm that there is no (For example, posted writes or read prefetch operations) bus transaction in progress on the OneNAND interface before writing new configurations to ONENAND_IF_CTRL and ONENAND_IF_ASYNC_TIMING_CTRL registers. 1b = Busy 0b = Not Busy 3-29 S5PV210_UM 3 ONENAND CONTROLLER 3.8.3 DMA CONTROL REGISTERS 3.8.3.1 DMA Source Address Register (DMA_SRC_ADDR, R/W, Address = 0xB060_0400) DMA_SRC_ADDR SA Bit [31:0] Description Source Address Source address on the AHB for the DMA operation. The start address for the DMA engine to perform read operation. Initial State 00000000h 3.8.3.2 DMA Source Configuration Register (DMA_SRC_CFG, R/W, Address = 0xB060_0404) DMA_SRC_CFG - SBL SAM SDW Bit [31:19] [18:16] [15:9] [8] [7:2] [1:0] Description Reserved Source Burst Length Burst length during the source memory access on the AHB for the DMA operation. This burst length is valid only when the memory address is aligned. The DMA engine requires that the memory address should be the multiple of the HSIZE (data width) x HBURST (burst length) to initiate the burst transfer on the AHB during the DMA transfer. If this address alignment condition is not satisfied, the actual burst length on the AHB will be single until this condition is met. 000b = Single 001b = Reserved 010b = 4-Burst 011b = 8-Burst 100b = 16-Burst 101b = Reserved 110b = Reserved 111b = Reserved Reserved Source Addressing Mode This bit refers to addressing mode during the source memory access on the AHB for the DMA operation. The incremental addressing mode is used for the general DMA operation and the constant mode is used to access repeatedly the specific address like a data register. 0b = Incremental addressing mode 1b = Constant addressing mode Reserved Source Data Width Access size during the source memory access on the AHB for the DMA operation. The data width is valid only if the memory address is aligned. To initiate the AHB transfer, the DMA engine requires that the Initial State - 100b 0b 10b 3-30 S5PV210_UM 3 ONENAND CONTROLLER DMA_SRC_CFG Bit Description memory address should be the multiple of the HSIZE (data width). If this address alignment condition is not satisfied, the actual data width on the AHB during the DMA transfer will be smaller than the access size specified in these bits. 00b = 8-bit (byte) 01b = 16-bit (half word) 10b = 32-bit (word) 11b = Reserved Initial State 3.8.3.3 DMA Destination Address Register (DMA_DST_ADDR, R/W, Address = 0xB060_0408) DMA_DST_ADDR DA Bit [31:0] Description Destination Address Destination address on the AHB for the DMA operation. This address is the start address to which the DMA engine performs write operation. Initial State 00000000h 3-31 S5PV210_UM 3 ONENAND CONTROLLER 3.8.3.4 DMA Destination Configuration Register (DMA_DST_CFG, R/W, Address = 0xB060_040C) DMA_DST_CFG - DBL DAM DDW Bit [31:19] [18:16] [15:9] [8] [7:2] [1:0] Description Reserved Destination Burst Length Burst length during the destination memory access on the AHB for the DMA operation. This burst length is valid only when the memory address is aligned. The DMA engine requires that the memory address should be the multiple of the HSIZE (data width) x HBURST (burst length) to initiate the burst transfer on the AHB during the DMA transfer. If this address alignment condition is not satisfied, the actual burst length on the AHB will be single until this condition is met. 000b = Single 001b = Reserved 010b = 4-Burst 011b = 8-Burst 100b = 16-Burst 101b = Reserved 110b = Reserved 111b = Reserved Reserved Destination Addressing Mode It specifies Addressing mode during the destination memory access on the AHB for the DMA operation. The incremental addressing mode is used for the general DMA operation and the constant mode is used to access repeatedly the specific address like a data register. 0b = Incremental addressing mode 1b = Constant addressing mode Reserved Destination Data Width Access size during the destination memory access on the AHB for the DMA operation. The data width is valid only if the memory address is aligned. To initiate the AHB transfer, the DMA engine requires that the memory address should be the multiple of the HSIZE (data width). If this address alignment condition is not satisfied, the actual data width on the AHB during the DMA transfer will be smaller than the access size specified in these bits. 00b = 8-bit (byte) 01b = 16-bit (half word) 10b = 32-bit (word) 11b = Reserved Initial State - 100b 0b 10b 3-32 S5PV210_UM 3 ONENAND CONTROLLER 3.8.3.5 DMA Transfer Size Register (DMA_TRANS_SIZE, R/W, Address = 0xB060_0414) DMA_TRANS_ SIZE - TS Bit Description [31:24] [23:0] Reserved Transfer Size The number of bytes to be transferred to the AHB by the DMA engine. Transfer size must be less than 16MBytes. If the DMA source or destination address is in the OneNAND interface slave address space, TS (Transfer Size) must be the multiple of 2 because OneNAND interface slave does NOT support BYTE transactions. Initial State 000000h 3.8.3.6 DMA Transfer Command Register (DMA_TRANS_CMD, W, Address = 0xB060_0418) DMA_TRANS_ CMD - TDC TEC TR Bit [31:19] [18] [17] [16] [15:1] [0] Description Reserved Transfer Done Clear When this bit is set to 1, the TD (Transfer Done) bit flag of the DMA Transfer Status Register (DMA_TRANS_STATUS) in the DMA engine is cleared to 0 Reserved Transfer Error Clear When this bit is set to 1, the TE (Transfer Error) bit flag of the DMA Transfer Status Register (DMA_TRANS_STATUS) in the DMA engine is cleared to 0 Reserved Transfer Run When this bit is set to 1, the DMA engine starts to transfer data from the source memory to the destination memory in the AHB Initial State 0b 0b 0b 3-33 S5PV210_UM 3 ONENAND CONTROLLER 3.8.3.7 DMA Transfer Status Register (A_TRANS_STATUS, R, Address = 0xB060_041C) A_TRANS_ STATUS - TD TB TE Bit Description [31:19] [18] [17] [16] Reserved Transfer Done This status is used to check whether the DMA transfer is complete or not. After the DMA transfer is successfully completed, TD bit is set to 1. Transfer Busy This status is used to check whether the DMA transfer is in progress or not Transfer Error This status is used to check whether there has been an error during the DMA transfer. There are three error sources in the DMA engine. Initial State 0b 0b 0b First error source is the response signal (HRESP) from the slave on the AHB. As soon as the DMA engine receives any ERROR response from the slave on the AHB during the DMA transfer, TE bit is set to 1 and the DMA operation stops. Second error sources are the incorrect source/ destination address and transfer direction configurations. The DMA engine has two AHB master ports and these are connected to the external AHB and the internal AHB, respectively. Therefore source and destination address registers cannot be configured to the slaves on the same AHB for the DMA operation. Due to this fact, only following two cases are allowed for source/ destination address register value: 1) source memory is the slave on the external AHB and destination memory is the slave on the internal AHB, 2) source memory is the slave on the internal AHB and destination memory is the slave on the external AHB. If source/ destination address registers are not configured to satisfy this condition, the DMA engine does not perform any data transfer and TE bit is set to 1. Also, if the transfer direction register is not configured correctly according to source/ destination addresses, the DMA engine does not perform any data transfer and TE bit is set to 1. Third error source is the incorrect source/ destination burst length or data width configurations. If any of these four fields (SBL, DBL, SDW, DDW) is configured with reserved value, the DMA engine does not perform any data transfer and TE bit is set to 1. - [15:0] Reserved 0000h 3-34 S5PV210_UM 3 ONENAND CONTROLLER 3.8.3.8 DMA Transfer Direction Register (DMA_TRANS_DIR, R/W, Address = 0xB060_0420) DMA_TRANS_ DIR - TDIR Bit Description [31:1] [0] Reserved Transfer Direction This bit specifies the transfer direction of the DMA operation between the OneNAND controller’s internal AHB memory and the OneNAND controller’s external AHB memory. 0b = OneNAND controller read (Internal AHB memory to external AHB memory) 1b = OneNAND controller write (External AHB memory to internal AHB memory) Initial State 0b 3-35 S5PV210_UM 3 ONENAND CONTROLLER 3.8.4 INTERRUPT CONTROLLER REGISTERS Interrupt controller registers can be classified into following four register types: 1) interrupt pending registers, 2) interrupt status registers, 3) interrupt mask registers, and 4) interrupt clear registers. Each interrupt pending register represents the raw status of the interrupt sources such as DMA transfer done, DMA transfer error, and OneNAND INT pin done. Interrupt pending register is the exact copy of the peripheral device status registers (ONENAND_IF_STATUS, DMA_TRANS_STATUS, and SQC_STATUS). Therefore, if the raw status bit of the peripheral device status register is cleared by writing a clear command to the peripheral device command register (ONENAND_IF_CMD, DMA_TRANS_CMD, and SQC_CMD), the corresponding bit of the interrupt pending register is also cleared automatically. For example, let us consider a DMA operation scenario, in which the DMA engine generates an interrupt and this interrupt is cleared. After DMA transfer is successfully completed, the TD (Transfer Done) bit of DMA Transfer Status Register (DMA_TRANS_STATUS) is set to 1. Simultaneously, the DPTD (DMA Pending Transfer Done) bit of Interrupt Controller DMA Pending Register (INTC_DMA_PEND) is also set to 1. On the other hand, interrupt controller status registers represent the interrupt sources, which actually generate an interrupt after the masking logic. If the DMTD (DMA Mask Transfer Done) bit of Interrupt Controller DMA Mask Register (INTC_DMA_MASK) is 0, the DSTD (DMA Status Transfer Done) bit of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) is set to 1 because this interrupt source is not masked. Now, the ARM_IRQ pin of the OneNAND controller is asserted to 1 and an interrupt is generated by the OneNAND controller. Note that the ARM_IRQ pin is OR-ed value of all the bits of interrupt controller status registers (INTC_SQC_STATUS, INTC_DMA_STATUS, and INTC_ONENAND_STATUS) and that this output is asserted if any bit of theses registers is set to 1. To handle this interrupt in a system, the ISR (interrupt service routine) should perform as follows. The TD (Transfer Done) bit of DMA Transfer Status Register (DMA_TRANS_STATUS) must be cleared to 0 by writing 1 to the TDC (Transfer Done Clear) bit of DMA Transfer Command Register (DMA_TRANS_CMD). And then, the DSTD (DMA Status Transfer Done) bit of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) must be cleared to 0 by writing 1 to the DCTD (DMA Clear Transfer Done) bit of the Interrupt Controller DMA Clear Register (INTC_DMA_CLR). 3.8.4.1 Interrupt Controller DMA Clear Register (INTC_DMA_CLR, W, Address = 0xB060_1004) INTC_DMA_CLR - DCTD DCTE - Bit [31:25] [24] [13:17] [16] [15:0] Description Reserved DMA Clear Transfer Done When this bit is set to 1, the DSTD (DMA status transfer done) bit flag of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) in the interrupt controller is cleared to 0 Reserved DMA Clear Transfer Error When this bit is set to 1, the DPTE (DMA status transfer error) bit flag of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) in the interrupt controller is cleared to 0 Reserved Initial State 0b 0b - 3-36 S5PV210_UM 3 ONENAND CONTROLLER 3.8.4.2 Interrupt Controller OneNAND Clear Register (INTC_ONENAND_CLR, W, Address = 0xB060_1008) INTC_ONENAND _CLR - OCINTD Bit Description Initial State [31:2] Reserved - [1:0] OneNAND Clear INT Done 00b When this bit is set to 1, the corresponding OSINTD (OneNAND status INT done) bit flag of the Interrupt Controller OneNAND Status Register (INTC_ONENAND_STATUS) in the interrupt controller is cleared to 0. Each bit corresponds to each OneNAND chip. For example, writing 1 to OCINTD[0] bit clears OSINTD[0] for OneNAND chip #0. 3.8.4.3 Interrupt Controller DMA Mask Register (INTC_DMA_MASK, R/W, Address = 0xB060_1024) INTC_DMA_MASK - DMTD DMTE - Bit [31:25] [24] [13:17] [16] [15:0] Description Reserved DMA Mask Transfer Done When this bit is set to 1, the DSTD (DMA status transfer done) bit flag of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) in the interrupt controller is disabled to generate an interrupt. Reserved DMA Mask Transfer Error When this bit is set to 1, the DPTE (DMA status transfer error) bit flag of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) in the interrupt controller is disabled to generate an interrupt. Reserved Initial State 1b 1b - 3.8.4.4 Interrupt Controller OneNAND Mask Register (INTC_ONENAND_MASK, R/W, Address = 0xB060_1028) INTC_ONENAND_ MASK - OMINTD Bit Description Initial State [31:2] Reserved - [1:0] OneNAND Mask INT Done 11b When this bit is set to 1, the corresponding OSINTD (OneNAND status INT done) bit flag of the Interrupt Controller OneNAND Status Register (INTC_ONENAND_STATUS) in the interrupt controller is disabled to generate an interrupt. Each bit corresponds to each OneNAND chip. For example, writing a 1 to OMINTD[0] bit disables OSINTD[0] to generate an interrupt for OneNAND chip #0. 3-37 S5PV210_UM 3 ONENAND CONTROLLER 3.8.4.5 Interrupt Controller DMA Pending Register (INTC_DMA_PEND, R, Address = 0xB060_1044) INTC_DMA_PEND - DPTD DPTE - Bit [31:25] [24] [13:17] [16] [15:0] Description Reserved DMA Pending Transfer Done This bit is the exact copy of the TD (transfer done) bit flag of the DMA Status Register (DMA_STATUS) Reserved DMA Pending Transfer Error This bit is the exact copy of the TE (transfer error) bit flag of the DMA status register (DMA_STATUS) Reserved Initial State 0b 0b - 3.8.4.6 Interrupt Controller OneNAND Pending Register (INTC_ONENAND_PEND, R, Address = 0xB060_1048) INTC_ONENAND_ PEND - OPINTD Bit Description [31:8] [7:2] [1:0] Reserved Reserved OneNAND Pending INT Done This bits are the exact copy of the INTD (INT done) bit flag of the OneNAND Interface Status Register (ONENAND_IF_STATUS) Initial State 111111b 11b 3.8.4.7 Interrupt Controller DMA Status Register (INTC_DMA_STATUS, R, Address = 0xB060_1064) INTC_DMA_ STATUS - DSTD DSTE - Bit Description Initial State [31:25] Reserved - [24] DMA Status Transfer Done 0b This bit is logical AND operation result of DPTD (DMA pending transfer done) bit flag of the interrupt controller DMA pending register (INTC_DMA_PEND) and inverse of DMTD (DMA mask transfer done) bit flag of the Interrupt Controller DMA Mask Register (INTC_DMA_MASK) [13:17] Reserved - [16] DMA Status Transfer Error 0b This bit is logical AND operation result of DPTE (DMA pending transfer error) bit flag of the interrupt controller DMA pending register (INTC_DMA_PEND) and inverse of DMTE (DMA mask transfer error) bit flag of the Interrupt Controller DMA Mask Register (INTC_DMA_MASK) [15:0] Reserved - 3-38 S5PV210_UM 3 ONENAND CONTROLLER 3.8.4.8 Interrupt Controller OneNAND Status Register (INTC_ONENAND_STATUS, R, Address = 0xB060_1068) INTC_ONENAND_ STATUS - OSINTD Bit Description Initial State [31:2] Reserved - [1:0] OneNAND Status INT Done 00b This bits are logical AND operation result of OPINTD (OneNAND pending INT done) bit flags of the interrupt controller OneNAND pending register (INTC_ONENAND_PEND) and inverse of OMINTD (OneNAND mask INT done) bit flag of the Interrupt Controller OneNAND Mask Register (INTC_ONENAND_MASK) 3-39 S5PV210_UM 4 NAND FLASH CONTROLLER 4 NAND FLASH CONTROLLER 4.1 OVERVIEW OF NAND FLASH CONTROLLER Owing to the recent increase in the prices of NOR flash memory and the moderately priced DRAM and NAND flash, customers prefer to execute boot code on NAND flash and execute the main code on DRAM. The boot code in S5PV210 can be executed on external NAND flash. It will copy NAND flash data to DRAM. To validate the NAND flash data, S5PV210 comprises of hardware Error Correction Code (ECC). After the NAND flash content is copied to DRAM, main program will be executed on DRAM. 4.2 KEY FEATURES OF NAND FLASH CONTROLLER The key features of NAND flash controller include: • Auto boot: The boot code is transferred to internal SRAM during reset. After the transfer, the boot code will be executed on the SRAM. • NAND flash memory interface: Supports 512Bytes, 2KB, 4KB, and 8KB pages. • Software mode: You can directly access NAND flash memory, for example, this feature can be used in read/ erase/ program NAND flash memory. • Interface: Supports 8-bit NAND flash memory interface bus. • Generates, detects, and indicates hardware ECC (Software correction). • Supports both SLC and MLC NAND flash memories. • ECC: Supports 1-/ 4-/ 8-/ 12-/ 16-bit ECC • SFR interface: Supports byte/ half word/ word access to Data and ECC data registers, and Word access to other registers. 4.2.1 4-1 S5PV210_UM 4.2.2 BLOCK DIAGRAM SYSTEM BUS AHB Slave I/F SFR ECC Gen. Control & State Machine 4 NAND FLASH CONTROLLER NAND FLASH Interface nFCE CLE ALE nRE nWE R/nB I/O0 - I/O7 Figure 4-1 NAND Flash Controller Block Diagram 4.2.3 NAND FLASH MEMORY TIMING HCLK CLE / ALE TACLS TWRPH0 TWRPH1 nWE DATA COMMAND / ADDRESS Figure 4-2 CLE and ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) 4-2 S5PV210_UM 4 NAND FLASH CONTROLLER HCLK nWE / nRE DATA TWRPH0 TWRPH1 DATA Figure 4-3 nWE and nRE Timing (TWRPH0=0, TWRPH1=0) 4-3 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3 SOFTWARE MODE S5PV210 supports only software mode access. Use this mode to access NAND flash memory. The NAND flash controller supports direct access to interface with the NAND flash memory. • Writing to the command register (NFCMMD) specifies the NAND Flash Memory command cycle • Writing to the address register (NFADDR) specifies the NAND Flash Memory address cycle • Writing to the data register (NFDATA) specifies write data to the NAND Flash Memory (write cycle) • Reading from the data register (NFDATA) specifies read data from the NAND Flash Memory (read cycle) • Reading main ECC registers (NFMECCD0/NFMECCD1) and Spare ECC registers (NFSECCD) specify read data from the NAND Flash Memory NOTE: In the software mode, use polling or interrupt to check the RnB status input pin. 4.3.1 DATA REGISTER CONFIGURATION 4.3.1.1 8-bit NAND Flash Memory Interface • A. Word Access Register NFDATA Endian Little Bit [31:24] 4th I/O[ 7:0] Bit [23:16] 3rd I/O[ 7:0] Bit [15:8] 2nd I/O[ 7:0] Bit [7:0] 1st I/O[ 7:0] • B. Half-word Access Register NFDATA Endian Little Bit [31:24] Invalid value Bit [23:16] Invalid value Bit [15:8] 2nd I/O[ 7:0] Bit [7:0] 1st I/O[ 7:0] • C. Byte Access Register NFDATA Endian Little Bit [31:24] Invalid value Bit [23:16] Invalid value Bit [15:8] Invalid value Bit [7:0] 1st I/O[ 7:0] 4-4 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.2 1-/ 4-/ 8-/ 12-/ 16-BIT ECC NAND flash controller supports 1-/ 4-/ 8-/ 12-/ 16-bit ECC. For 1-bit ECC, NAND flash controller comprises ECC modules for main and spare (meta) data. Main data ECC module generates ECC parity code for 2048 bytes (maximum) data/ message length, whereas spare (meta) data ECC module generates ECC Parity code for 32 bytes (maximum). For 4-bit ECC, NAND flash controller comprises of an ECC module. It generates 512 or 24 bytes of ECC parity code. Set MsgLength (NFCONF[25]) to select 512 or 24 bytes message length. For 8-/ 12-/ 16-bit ECC, NAND flash controller comprises ECC modules for each ECC. You can select data/ message length for main and spare (meta) data length. Usually, the length of main data is 512 bytes, and the length of spare (meta) data depends on user application. Since these ECC modules support variable length of main and spare (meta) data, you must set the ECC parity conversion codes to handle free page (For more information on ECC parity conversion codes, refer to the 4.3.11 ). Free page specifies an erased page. The value of erased page is ‘0xff’. Therefore, set the ECC parity conversion codes to generate ‘0xff’ ECC parity codes for all ‘0xff’ data. This allows ECC module to detect errors on a free page. ECC parity codes are described as follows: • 28-bit ECC Parity Code = 22-bit Line parity + 6-bit Column Parity • 10-bit ECC Parity Code = 4-bit Line parity + 6bit Column Parity Each 1-/ 4-/ 8-/ 12-/ 16-bit ECC module guarantees up to 1-/ 4-/ 8-/ 12-/ 16-bit errors, respectively. If the errors cross the number of guaranteed errors, the result cannot be guaranteed. 4.3.3 and 4.3.4 show 1-bit ECC parity code assignment. 4-5 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.3 2048 BYTE 1-BIT ECC PARITY CODE ASSIGNMENT TABLE MECCn_0 MECCn_1 MECCn_2 MECCn_3 DATA7 ~P64 ~P1024 ~P4 1 DATA6 ~P64’ ~P1024’ ~P4’ 1 DATA5 ~P32 ~P512 ~P2 1 DATA4 ~P32’ ~P512’ ~P2’ 1 DATA3 ~P16 ~P256 ~P1 ~P8192 DATA2 ~P16’ ~P256’ ~P1’ ~P8192’ DATA1 ~P8 ~P128 ~P2048 ~P4096 DATA0 ~P8’ ~P128’ ~P2048’ ~P4096’ 4.3.4 32 BYTE 1-BIT ECC PARITY CODE ASSIGNMENT TABLE SECCn_0 SECCn_1 DATA7 ~P2 ~P128 DATA6 ~P2’ ~P128` DATA5 ~P1 ~P64 DATA4 ~P1’ ~P64` DATA3 ~P16 ~P32 DATA2 ~P16’ ~P32` DATA1 ~P8 ~P4 DATA0 ~P8’ ~P4’ 4.3.5 1-BIT ECC MODULE FEATURES The ECC Lock (MainECCLock and SpareECCLock) bit of the control register generates the 1-bit ECC. If ECCLock is low, the hardware ECC modules generate the ECC codes. • 1-bit ECC Register Configuration The following table shows the configuration of 1-bit ECC value read from spare area of external NAND flash memory. The format of ECC read from memory is important to compare the ECC parity code generated by the hardware modules. NOTE: 4-bit/ 8-bit/ 12-bit/ 16-bit ECC decoding scheme is different compared to 1-bit ECC. • NAND Flash Memory Interface Register NFMECCD0 NFMECCD1 Bit [31:24] Not used Not used Bit [23:16] 2nd ECC 4th ECC Bit [15:8] Not used Not used Bit [7:0] 1st ECC 3rd ECC Register NFSECCD Bit [31:24] Not used Bit [23:16] 2nd ECC Bit [15:8] Not used Bit [7:0] 1st ECC 4-6 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.6 1-BIT ECC PROGRAMMING GUIDE 1. To use SLC ECC in software mode, reset the ECCType to ‘0’ (enable SLC ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are unlocked(‘0’). You must reset ECC value. To reset ECC value write the InitMECC (NFCONT[5]) and InitSECC (NFCON[4]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before reading or writing data. MainECCLock (NFCONT[7]) and SpareECCLock(NFCONT[6]) bits control whether ECC Parity code is generated or not. 2. The ECC module generates ECC parity code on register NFMECC0/1 whenever data is read or written. 3. After you complete reading or writing one page (not including spare area data), set the MainECCLock bit to ‘1’ (Lock). ECC Parity code is locked and the value of the ECC status register does not change. 4. To generate spare area ECC parity code, Clear SpareECCLock (NFCONT[6]) bit as ‘0’ (Unlock). 5. The spare area ECC module generates ECC parity code on register NFSECC whenever data is read or written. 6. After you complete reading or writing spare area, set the SpareECCLock bit to ‘1’ (Lock). ECC Parity code is locked and the value of the ECC status register will not be changed. 7. From now on, you can use these values to record to the spare area or check the bit error. 8. For example, to check the bit error of main data area on page read operation, you must move the ECC parity codes (is stored to spare area) to NFMECCD0 and NFMECCD1 after ECC codes for main data area is generated. From this point, the NFECCERR0 and NFECCERR1 have the valid error status values. NOTE: NFSECCD is for ECC in the spare area (Usually, the user will write the ECC value generated from main data area to spare area, of which the value will be the same as NFMECC0/1) which is generated from the main data area. 4-7 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.7 4-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0(512-byte message length) and the ECCType to “10”(enable 4bit ECC). ECC module generates ECC parity code for 512-byte write data. To reset ECC value write the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before writing data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 2. The 4-bit ECC module generates ECC parity code internally whenever data is written. 3. After you finish writing 512-byte data (not including spare area data), the parity codes are automatically updated to NFMECC0 and NFMECC1 registers. If you use 512-byte NAND Flash memory, you can program these values to spare area. However, if you use NAND Flash memory more than 512-byte page, you cannot program immediately. In this case, you have to copy these parity codes to other memory like DRAM. After writing all main data, you can write the copied ECC values to spare area. The parity codes have self-correctable information including parity code itself. 4. To generate spare area ECC parity code, set the MsgLength to 1(24-byte message length) and the ECCType to “10”(enable 4bit ECC). ECC module generates ECC parity code for 24-byte write data. To reset ECC value write the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before writing data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 5. Whenever data is written, the 4-bit ECC module generates ECC parity code internally. 6. When you finish writing 24-byte meta or extra data, the parity codes are automatically updated to NFMECC0 and NFMECC1 registers. You can program these parity codes to spare area. The parity codes have self-correctable information including parity code itself. 4-8 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.8 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and the ECCType to “10” (enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore, to reset ECC value write the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before reading data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 2. Whenever data is read, the 4-bit ECC module generates ECC parity code internally. 3. After you complete reading 512-byte (not including spare area data), you must read parity codes. MLC ECC module needs parity codes to detect whether error bits have occurred or not. Therefore, you must read ECC parity code immediately after reading 512-byte. After ECC parity code is read, 4-bit ECC engine starts searching for error internally. 4-bit ECC error searching engine needs minimum of 155 cycles to find any error. During this time, you can continue reading main data from external NAND Flash memory. Use ECCDecDone(NFSTAT[6]) to check whether ECC decoding is completed or not. 4. When ECCDecDone (NFSTAT[6]) is set (‘1’), NFECCERR0 indicates whether error bit exists or not. If any error exists, refer NFECCERR0/1 and NFMLCBITPT registers to fix. 5. If you have more main data to read, go back to step 1. 6. To check meta data error, set the MsgLength to 1 (24-byte message length) and the ECCType to ‘1’ (enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore, you must reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before reading data. MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not. 7. Whenever data is read, the 4-bit ECC module generates ECC parity code internally. 8. After you complete reading 512-byte (not include spare area data), you must read parity codes. 4-bit ECC module needs parity codes to detect whether error bits have occurred or not. Therefore, ensure to read ECC parity codes immediately after reading 512-byte. After ECC parity code is read, 4-bit ECC engine starts searching for error internally. 4-bit ECC error searching engine needs minimum of 155 cycles to find any error. During this time, you can continue reading main data from external NAND Flash memory. Use ECCDecDone(NFSTAT[6]) to check whether ECC decoding is completed or not. 9. When ECCDecDone (NFSTAT[6]) is set (‘1’), NFECCERR0 indicates whether error bit exists or not. If any error exists, you can fix it by referring to NFECCERR0/1 and NFMLCBITPT registers. 4-9 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.9 8-BIT / 12-BIT / 16-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 8/ 12/ 16-bit ECC in software mode, set the MsgLength(NFECCCONF[25:16]) to 511(512byte message length) and the ECCType to “001/100/101”(enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512 byte write data. Therefore, reset ECC value by writing the InitMECC (NFECCCONT[2]) bit as ‘1’ before writing data, and clear the MainECCLock(NFCONT[7]) bit to ‘0’(Unlock) before writing data. 2. Whenever data is written, the corresponding 8/12/16-bit ECC module generates ECC parity code internally. 3. After you finish writing 512bbyte data (This does not include spare area data), the parity codes are automatically updated to the NFECCPRG0 ~ NFECCPRGECC6 registers. If you use a NAND Flash memory having 512 byte page, you can program these values to spare area. However, if you use a NAND Flash memory more than 512-byte page, you cannot program immediately. In this case, you must copy these ECC parity codes to other memory like DRAM. After writing all main data, you can write the copied ECC values to spare area. The parity codes have self-correctable information including parity code itself. Table below shows the ECC parity size: ECC type 8-bit ECC 12-bit ECC 16-bit ECC Size of ECC Parity Codes 13 byte 20 byte 26 byte 4. To generate spare area ECC parity code for meta data, the steps are same (from 1 ~ 3), except setting the MsgLenght(NFECCCONF[25:16]) to the size that you prefer. When you set InitMECC(NFECCCONT[2]), all ECC parity codes generated for main data are cleared. Therefore, you should copy the ECC parity codes for main data. NOTE: You should set the ECC parity conversion codes to check free page error. For more information about, refer to 4.3.11 4-10 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.10 8/12/16-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 8/ 12/ 16-bit ECC in software mode, set the MsgLength(NFECCCONF[25:16] to 511(512-byte message length) and the ECCType to “001/100/101”(enable 8/12/16-bit ECC, respectively). ECC module generates ECC parity code for 512-byte read data. Therefore, you must reset ECC value by writing the InitMECC (NFECCCONT[2]) bit as ‘1’, and clear the MainECCLock(NFCONT[7]) bit to ‘0’(Unlock) before read data. 2. Whenever data is read, the 8/12/16-bit ECC module generates ECC parity code internally. 3. After you complete reading 512-byte (not including spare area data), ensure to read the corresponding parity codes. ECC module needs parity codes to detect whether error bits have occurred or not. Therefore, you have to read ECC parity code immediately after reading 512-byte. After ECC parity code is read, the 8/12/16-bit ECC engine searches for error internally. 8/12/16-bit ECC search engine needs minimum of 155 cycles to find any errors. DecodeDone(NFECCSTAT[24]) can be used to check whether ECC decoding is completed or not. 4. When DecodeDone (NFECCSTAT[24]) is set (‘1’), ECCError(NFECCSECSTAT[4:0]) indicates whether error bit exists or not. If any error exists, you can fix it by referencing NFECCERL0~NFECCERL7 and NFECCERP0 ~ NFECCERP3 registers. 5. If you have additional main data to read, continue the steps 1 ~ 4. 6. To check spare area data (meta data) error, the sequences are same (steps 1 ~ 4), except setting the MsgLenght(NFECCCONF[25:16]) to the size that you want. NOTE: You should set the ECC parity conversion codes to check free page error. For more information, refer to refer to 4.3.11 . 4-11 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.11 ECC PARITY CONVERSION CODE GUIDE FOR 8/12/16-BIT ECC The ECC parity conversion codes are there to fix errors, which occur when reading a free page. Free page means the page erased. The 8/ 12/ 16-bit ECC modules support variable message size for meta data stored in spare area. Generally, the size of main data (sector) is 512-byte and user should set the corresponding ECC parity conversion codes as shown in Table below. ECC type 8-bit ECC 12-bit ECC 16-bit ECC ECC Parity Conversion Codes Here, 13 byte ECC parity conversion codes Here, 20 byte ECC parity conversion codes Here, 26 byte ECC parity conversion codes The message size for meta data stored spare area can be different depending on user’s needs. Hence, you can change the size of meta data by changing MsgLength(NFECCCONF[25:16]) and change ECC parity conversion codes. Steps to know ECC parity conversion codes according to the size of message length: 1. Clear all ECC parity conversion registers (NFECCCONECC0 ~ NFECCCONECC6) as all zero. 2. Set all registers for page program 3. Reset InitMECC (NFECCCONT[2] bit as ‘1’ 4. Write ‘0xff’ data as much as the size of meta data. 5. After you write data as MsgLength(NFECCCONF[25:16]), the EncodeDone(NFECCSTAT[25]) is set as ‘1’ and generates the corresponding ECC parity codes. 6. Set ECC parity conversion registers as inverted values of ECC parity codes generated. For testing if these ECC parity conversion codes work well, repeat step 3 ~ 5. After you set ECC parity conversion codes, if the generated ECC parity code are all ‘0xff’, then it is working correctly. Constraints to support free page function: − Free page check is for only data area (512-byte) − If there is an error during reading a page erased (free page), then free page engine indicates that the page is not free page. − To detect error(s) on free page, user should set corresponding conversion codes. 4-12 S5PV210_UM 4 NAND FLASH CONTROLLER 4.3.12 LOCK SCHEME FOR DATA PROTECTION NFCON provides a lock scheme to protect data stored in external NAND Flash memories from malicious program. For this scheme, the NFSBLK and NFEBLK registers are used to provide access control methods; only the memory area between NFSBLK and NFEBLK is erasable and programmable, but the read access is available to whole memory area. This lock scheme is only available when you enable LockTight(NFCONT[17]) and LOCK(NFCONT[16]). 1. Unlock mode In unlock mode, user can access whole NAND memory; there are no constraints to access memory. 2. Soft lock mode In soft lock mode, you can access NAND block area between NFSBLK and NFEBLK. When you try to program or erase the locked area, an illegal access error will occur (NFSTAT [5] bit will be set). 3. Lock-tight mode In lock-tight mode, you can access NAND block area between NFSBLK and NFEBLK as soft lock mode. The differences is that you cannot change NFSBLK and NFEBLK registers, and also LOCK(NFCONT[16]) and LockTight(NFCONT[17]) bits. When you try to program or erase the locked area, an illegal access error will occur (NFSTAT[5] bit will be set). The LockTight(NFCONT[17]) bit is only cleared when reset or wake up from sleep mode (It is impossible to clear it by software). The accessibility of NAND area is illustrated in the figure below. NFEBLK + 1 NFEBLK NFSBLK NFSBLK - 1 NAND flash memory Locked area (Read only) Address High Prorammable/ Readable Area Locked area (Read only) NFSBLK NFEBLK Low when Lock-tight =1 or SoftLock=1 When NFSBLK=NFEBLK Locked Area (Read only) NOTE: If the address of NFSBLK and NFEBLK are same, then the erase and program to all NAND memory are not allowed. 4-13 S5PV210_UM 4.4 I/O DESCRIPTION Signal Xm0DATA Xm0FRnB[3:0] Xm0FCLE Xm0FALE Xm0CSn[2:5] Xm0FREn Xm0FWEn I/O Input / Output Input Output Output Output Output Output Description Address / Data Bus Ready and Busy Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable 4 NAND FLASH CONTROLLER Pad Xm0DATA Xm0FRnB Xm0FCLE Xm0FALE Xm0CSn Xm0FREn Xm0FWEn Type muxed muxed muxed muxed muxed muxed muxed 4-14 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5 REGISTER DESCRIPTION 4.5.1 REGISTER MAP Register Address NFCONF 0xB0E0_0000 NFCONT 0xB0E0_0004 NFCMMD 0xB0E0_0008 NFADDR 0xB0E0_000C NFDATA 0xB0E0_0010 NFMECCD0 0xB0E0_0014 NFMECCD1 0xB0E0_0018 NFSECCD 0xB0E0_001C NFSBLK 0xB0E0_0020 NFEBLK 0xB0E0_0024 NFSTAT 0xB0E0_0028 NFECCERR0 0xB0E0_002C NFECCERR1 0xB0E0_0030 NFMECC0 0xB0E0_0034 NFMECC1 0xB0E0_0038 NFSECC 0xB0E0_003C NFMLCBITPT 0xB0E0_0040 8/ 12/ 16-bit ECC Register Map NFECCCONF 0xB0E2_0000 NFECCCONT 0xB0E2_0020 NFECCSTAT 0xB0E2_0030 NFECCSECSTAT 0xB0E2_0040 NFECCPRGECC0 0xB0E2_0090 NFECCPRGECC1 0xB0E2_0094 NFECCPRGECC2 NFECCPRGECC3 NFECCPRGECC4 NFECCPRGECC5 NFECCPRGECC6 NFECCERL0 NFECCERL1 NFECCERL2 0xB0E2_0098 0xB0E2_009C 0xB0E2_00A0 0xB0E2_00A4 0xB0E2_00A8 0xB0E2_00C0 0xB0E2_00C4 0xB0E2_00C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W R R R R R R R R R R R R Description Configuration Register Control Register Command Register Address Register Data Register 1st and 2nd Main ECC Data Register 3rd and 4th Main ECC Data Register Spare ECC Read Register Programmable Start Block Address Register Programmable End Block Address Register NAND Status Registet ECC Error Status0 Register ECC Error Status1 Register Generated ECC Status0 Register Generated ECC Status1 Register Generated Spare Area ECC Status Register 4-bit ECC Error Bit Pattern Register ECC Configuration Register ECC Control Register ECC Status Register ECC Sector Status Register ECC Parity Code0 Register for Page program ECC Parity Code1 Register for Page Program ECC parity code2 register for page program ECC parity code3 register for page program ECC parity code4 register for page program ECC parity code5 register for page program ECC parity code6 register for page program ECC error byte location0 register ECC error byte location1 register ECC error byte location2 register Reset Value 0x0000_1000 0x00C1_00C6 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 0xF080_0F0D 0x0003_FFF2 0x0000_0000 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4-15 S5PV210_UM 4 NAND FLASH CONTROLLER Register NFECCERL3 NFECCERL4 NFECCERL5 NFECCERL6 NFECCERL7 NFECCERP0 NFECCERP1 NFECCERP2 NFECCERP3 NFECCCONECC0 NFECCCONECC1 NFECCCONECC2 NFECCCONECC3 NFECCCONECC4 NFECCCONECC5 NFECCCONECC6 Address R/W Description 0xB0E2_00CC R ECC error byte location3 register 0xB0E2_00D0 R ECC error byte location4 register 0xB0E2_00D4 R ECC error byte location5 register 0xB0E2_00D8 R ECC error byte location6 register 0xB0E2_00DC R ECC error byte location7 register 0xB0E2_00F0 R ECC error bit pattern0 register 0xB0E2_00F4 R ECC error bit pattern1 register 0xB0E2_00F8 R ECC error bit pattern2 register 0xB0E2_00FC R ECC error bit pattern3 register 0xB0E2_0110 R/W ECC parity conversion code0 register 0xB0E2_0114 R/W ECC parity conversion code1 register 0xB0E2_0118 R/W ECC parity conversion code2 register 0xB0E2_011C R/W ECC parity conversion code3 register 0xB0E2_0120 R/W ECC parity conversion code4 register 0xB0E2_0124 R/W ECC parity conversion code5 register 0xB0E2_0128 R/W ECC parity conversion code6 register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4-16 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2 NAND FLASH INTERFACE AND 1 / 4-BIT ECC REGISTERS 4.5.2.1 Nand Flash Configuration Register (NFCONF, R/W, Address = 0xB0E0_0000) NFCONF Reserved MsgLength ECCType0 Reserved TACLS TWRPH0 TWRPH1 MLCFlash PageSize AddrCycle Reserved Bit [31:26] [25] [24:23] [22:16] [15:12] [11:8] [7:4] [3] [2] [1] [0] Description Reserved 0 = 512 byte Message Length 1 = 24 byte Message Length This bit indicates the kind of ECC to use. 00 = 1-bit ECC 10 = 4-bit ECC 01 = 11 = Disable 1-bit and 4-bit ECC Reserved CLE and ALE duration setting value (0~15) Duration = HCLK x TACLS TWRPH0 duration setting value (0~15) Duration = HCLK x ( TWRPH0 + 1 ) Note: You should add additional cycles about 10ns for page read because of additional signal delay on PCB pattern. TWRPH1 duration setting value (0~15) Duration = HCLK x ( TWRPH1 + 1 ) This bit indicates the kind of NAND Flash memory to use. 0 = SLC NAND Flash 1 = MLC NAND Flash This bit indicates the page size of NAND Flash Memory, When MLCFlash is 0, the value of PageSize is as follows: 0 = 2048 Bytes/page 1 = 512 Bytes/page When MLCFlash is 1, the value of PageSize is as follows: 0 = 4096 Bytes/page 1 = 2048 Bytes/page This bit indicates the number of Address cycle of NAND Flash memory. When Page Size is 512 Bytes, 0 = 3 address cycle 1 = 4 address cycle When page size is 2K or 4K, 0 = 4 address cycle 1 = 5 address cycle Reserved Initial State 0 0 0 0000000 0x1 0x0 0x0 0 0 0 0 4-17 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.2 Control Register (NFCONT, R/W, Address = 0xB0E0_0004) NFCONT Reserved Reg_nCE3 Reg_nCE2 Reserved MLCEccDirection LockTight LOCK Reserved EnbMLCEncInt EnbMLCDecInt EnbIllegalAccINT EnbRnBINT RnB_TransMode Bit [31:24] [23] [22] [21:19] [18] [17] [16] [15:14] [13] [12] [11] [10] [9] [8] Description Reserved NAND Flash Memory nRCS[3] signal control 0 = Force nRCS[3] to low (Enable chip select) 1 = Force nRCS[3] to High (Disable chip select) NAND Flash Memory nRCS[2] signal control 0 = Force nRCS[2] to low (Enable chip select) 1 = Force nRCS[2] to High (Disable chip select) Reserved 4-bit, ECC encoding / decoding control 0 = Decoding 4-bit ECC, It is used for page read 1 = Encoding 4-bit ECC, It is be used for page program Lock-tight configuration 0 = Disable lock-tight 1 = Enable lock-tight, If this bit is set to 1, you cannot clear this bit. For more information, refer to the 4.3.12 "Lock scheme for data protection". Soft Lock configuration 0 = Disable lock 1 = Enable lock Software can modify soft lock area any time. For more information, refer to the 4.3.12 ". Reserved 4-bit ECC encoding completion interrupt control 0 = Disable interrupt 1 = Enable interrupt 4-bit ECC decoding completion interrupt control 0 = Disable interrupt 1 = Enable interrupt Reserved Illegal access interrupt control 0 = Disable interrupt 1 = Enable interrupt Illegal access interrupt occurs when CPU tries to program or erase locking area (the area setting in NFSBLK (0xB0E0_0020) to NFEBLK (0xB0E0_0024)-1. RnB status input signal transition interrupt control 0 = Disable RnB interrupt 1 = Enable RnB interrupt RnB transition detection configuration 0 = Detect rising edge 1 = Detect falling edge Initial State 0 1 1 0 0 0 1 00 0 0 0 0 0 0 4-18 S5PV210_UM 4 NAND FLASH CONTROLLER NFCONT MECCLock SECCLock InitMECC InitSECC HW_nCE Reg_nCE1 Reg_nCE0 MODE Bit Description Initial State [7] Lock Main area ECC generation 1 0 = Unlock Main area ECC 1 = Lock Main area ECC Main area ECC status register is NFMECC0/NFMECC1(0xB0E0_0034/0xB0E0_0038), [6] Lock Spare area ECC generation. 1 0 = Unlock Spare ECC 1 = Lock Spare ECC Spare area ECC status register is NFSECC(0xB0E0_003C), [5] 1 = Initialize main area ECC decoder/encoder (write-only) 0 [4] 1 = Initialize spare area ECC decoder/encoder (write-only) 0 [3] Reserved (HW_nCE) 0 [2] NAND Flash Memory nRCS[1] signal control 1 [1] NAND Flash Memory nRCS[0] signal control 1 0 = Force nRCS[0] to low (Enable chip select) 1 = Force nRCS[0] to High (Disable chip select) Note: The setting all nCE[3:0] zero can not be allowed. Only one nCE can be asserted to enable external NAND flash memory. The lower bit has more priority when user set all nCE[3:0] zeros. [0] NAND Flash controller operating mode 0 0 = Disable NAND Flash Controller 1 = Enable NAND Flash Controller 4.5.2.3 Command Register (NFCMMD, R/W, Address = 0xB0E0_0008) NFCMMD Reserved REG_CMMD Bit [31:8] [7:0] Description Reserved NAND Flash memory command value Initial State 0x000000 0x00 4.5.2.4 Address Register (NFADDR, R/W, Address = 0xB0E0_000C) NFADDR Reserved REG_ADDR Bit [31:8] [7:0] Description Reserved NAND Flash memory address value Initial State 0x000000 0x00 4-19 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.5 Data Register (NFDATA, R/W, Address = 0xB0E0_0010) NFDATA NFDATA Bit [31:0] Description NAND Flash read/ program data value for I/O Note: For more information, refer to 4.3.1 Data Register Configuration in page 4-4. Initial State 0x00000000 4.5.2.6 Main Data Area ECC Register (NFMECCD0, R/W, Address = 0xB0E0_0014) NFMECCD0 Reserved ECCData1 (ECC1) Reserved ECCData0 (ECC0) Bit [31:24] [23:16] [15:8] [7:0] Description Reserved 2nd ECC Note: In software mode, read this register when you need to read 2nd ECC value from NAND Flash memory Reserved 1st ECC Note: In software mode, read this register when you need to read 1st ECC value from NAND flash memory. This register has the same read function as NFDATA. NOTE: Only word access is allowed. Initial State 0x00 0x00 0x00 0x00 4.5.2.7 Main Data Area ECC Register (NFMECCD0, R/W, Address = 0xB0E0_0018) NFMECCD1 Reserved ECCData3 (ECC3) Reserved ECCData2 (ECC2) Bit [31:24] [23:16] [15:8] [7:0] Description Reserved 4th ECC Note: In software mode, read this register when you need to read 4th ECC value from NAND Flash memory Reserved 3rd ECC Note: In software mode, read this register when you need to read 3rd ECC value from NAND Flash memory. This register has the same read function as NFDATA. Initial State 0x00 0x00 0x00 0x00 4-20 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.8 Only Word Access is Allowed Spare Area ECC Register (NFSECCD, R/W, Address = 0xB0E0_001C) NFSECCD Reserved SECCData1 Reserved SECCData0 Bit [31:24] [23:16] [15:8] [7:0] Description Reserved 2nd ECC Note: In software mode, read this register when you need to read 2nd ECC value from NAND Flash memory Reserved 1st ECC Note: In software mode, read this register when you need to read 1st ECC value from NAND Flash memory. This register has the same read function as NFDATA. Initial State 0x00 0xFF 0x00 0xFF NOTE: Only word access is allowed. 4.5.2.9 Programmable Start Block Address Register (NFSBLK, R/W, Address = 0xB0E0_0020) NFSBLK Reserved SBLK_ADDR2 SBLK_ADDR1 SBLK_ADDR0 Bit [31:24] [23:16] [15:8] [7:0] Description Reserved The 3rd block address of the block erase operation The 2nd block address of the block erase operation The 1st block address of the block erase operation (Only bit [7:5] are valid) Initial State 0x00 0x00 0x00 0x00 NOTE: Advance Flash’s block Address start from 3-address cycle. So block address register only needs 3-bytes. For more information about lock scheme, refer to the 4.3.12 . 4.5.2.10 Programmable End Block Address Register (NFEBLK, R/W, Address = 0xB0E0_0024) NFEBLK Reserved EBLK_ADDR2 EBLK_ADDR1 EBLK_ADDR0 Bit [31:24] [23:16] [15:8] [7:0] Description Reserved The 3rd block address of the block erase operation The 2nd block address of the block erase operation The 1st block address of the block erase operation (Only bit [7:5] are valid) Initial State 0x00 0x00 0x00 0x00 NOTE: Advance Flash’s block Address start from 3-address cycle. So block address register only needs 3-bytes. For more information about lock scheme, refer to the 4.3.12 . 4-21 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.11 NFCON Status Register (NFSTAT, R/W, Address = 0xB0E0_0028) NFSTAT Flash_RnB_GRP RnB_TransDetect _GRP Reserved Flash_nCE[3:0] (Read-only) MLCEncodeDone MLCDecodeDone IllegalAccess RnB_TransDetect Flash_nCE[1] (Read-only) Flash_nCE[0] (Read-only) Reserved Flash_RnB (Read-only) Bit [31:28] [27:24] [23:12] [11:8] Description The status of RnB[3:0] input pin. 0 = NAND Flash memory busy 1 = NAND Flash memory ready to operate When RnB[3:0] low to high transition occurs, this bit is set and an interrupt is issued if RnB_TransDetect_GRP is enabled. To clear this, write ‘1’. 0 = RnB transition is not detected 1 = RnB transition is detected Transition configuration is set in RnB_TransMode(NFCONT[8]). Reserved The status of nCE[3:0] output pin. Initial State 0xF 0x800 0xF [7] When 4-bit ECC encodng is finished, this bit is set and an 0 interrupt is issued if MLCEncodeDone is enabled. The NFMLCECC0 and NFMLCECC1 have valid values. To clear this, write ‘1’. 1 = 4-bit ECC encoding is completed [6] When 4-bit ECC decoding is finished, this bit is set and an 0 interrupt is issued if MLCDecodeDone is enabled. The NFMLCBITPT, NFMLCL0, and NFMLCEL1 have valid values. To clear this, write ‘1’. 1 = 4-bit ECC decoding is completed [5] Once Soft Lock or Lock-tight is enabled and any illegal access 0 (program, erase) to the memory takes place, then this bit is set. 0 = Illegal access is not detected 1 = Illegal access is detected To clear this value, write 1 to this bit. [4] When RnB[0] low to high transition occurs, this bit is set and an 0 interrupt is issued if RnB_TransDetect is enabled. To clear this, write ‘1’. 0 = RnB transition is not detected 1 = RnB transition is detected Transition configuration is set in RnB_TransMode(NFCONT[8]). [3] The status of nCE[1] output pin 1 [2] The status of nCE[0] output pin 1 [1] Reserved 0 [0] The status of RnB[0] input pin. 1 0 = NAND Flash memory busy 1 = NAND Flash memory ready to operate 4-22 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.12 ECC0/1 Error Status Register (NFECCERR0, R, Address = 0xB0E0_002C) • When ECC Type is 1-bit ECC NFECCERR0 Reserved ECCSDataAddr ECCSBitAddr ECCDataAddr ECCBitAddr ECCSprErrNo ECCMainErrNo Bit Description [31:25] Reserved [24:21] In spare area, Indicates which number data is error [20:18] In spare area, Indicates which bit is error [17:7] In main data area, Indicates which number data is error [6:4] In main data area, Indicates which bit is error [3:2] Indicates whether spare area bit fail error occurred 00 = No Error 01 = 1-bit error(correctable) 10 = Multiple error 11 = ECC area error [1:0] Indicates whether main data area bit fail error occurred 00 = No Error 01 = 1-bit error(correctable) 10 = Multiple error 11 = ECC area error NOTE: The above values are valid only when both ECC register and ECC status register have valid value. Initial State 0x00 0x0 000 0x7FF 111 00 10 • When ECC Type is 4-bit ECC NFECCERR0 MLCECCBusy MLCECCReady MLCFreePage MLCECCError MLCErrLocation2 Reserved MLCErrLocation1 Bit Description [31] Indicates the 4-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy [30] ECC Ready bit [29] Indicates the page data read from NAND flash has all ‘FF’ value. [28:26] 4-bit ECC decoding result 000 = No error 001 = 1-bit error 010 = 2-bit error 011 = 3-bit error 100 = 4-bit error 101 = Uncorrectable 11x = reserved [25:16] Error byte location of 2nd bit error [15:10] Reserved [9:0] Error byte location of 1st bit error NOTE: These values are updated when ECCDecodeDone (NFSTAT[6]) is set (‘1’). Initial State 0 1 0 000 0x000 0x00 0x000 4-23 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.13 ECC0/1 Error Status Register (NFECCERR1, R, Address = 0xB0E0_0030) • When ECC Type is 4-bit ECC NFECCERR1 Reserved MLCErrLocation4 Reserved MLCErrLocation3 Bit [31:26] [25:16] [15:10] [9:0] Description Reserved Error byte location of 4th bit error Reserved Error byte location of 3rd bit error NOTE: These values are updated when ECCDecodeDone (NFSTAT[6]) is set (‘1’). Initial State 0x00 0x00 0x00 0x000 4.5.2.14 Main data area ECC0 status Register (NFMECC0, R, Address = 0xE810_0034) • When ECCType is 1-bit ECC. NFMECC0 MECC3 MECC2 MECC1 MECC0 Bit [31:24] [23:16] [15:8] [7:0] ECC3 for data ECC2 for data ECC1 for data ECC0 for data Description NOTE: The NAND flash controller generate NFMECC0/1 when read or write main area data while the MainECCLock(NFCONT[7]) bit is ‘0’(Unlock). Initial State 0xFF 0xFF 0xFF 0xFF • When ECCType is 4-bit ECC NFMECC0 4th Parity 3rd Parity 2nd Parity 1st Parity Bit [31:24] [23:16] [15:8] [7:0] Description 4th Check Parity generated from main area (512-byte) 3rd Check Parity generated from main area (512-byte) 2nd Check Parity generated from main area (512-byte) 1st Check Parity generated from main area (512-byte) Initial State 0x00 0x00 0x00 0x00 NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is ‘0’(unlock). 4-24 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.2.15 Main data area ECC0 status Register (NFMECC1, R, Address = 0xB0E0_0038) • When ECCType is 4-bit ECC NFMECC1 Reserved 7th Parity 6th Parity 5th Parity Bit [31:24] [23:16] [15:8] [7:0] Description Reserved 7th Check Parity generated from main area (512-byte) 6th Check Parity generated from main area (512-byte) 5th Check Parity generated from main area (512-byte) Initial State 0x00 0x00 0x00 0x00 NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is ‘0’(unlock). 4.5.2.16 Spare Area ECC Status Register (NFSECC, R, Address = 0xB0E0_003C) NFSECC Reserved SECC1 SECC0 Bit [31:16] [15:8] [7:0] Description Reserved Spare area ECC1 Status Spare area ECC0 Status NOTE: The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock(NFCONT[6]) bit is ‘0’(Unlock). Initial State 0xFFFF 0xFF 0xFF 4.5.2.17 MLC 4-bit ECC Error Patten Register (NFMLCBITPT, R, Address = 0xB0E0_0040) NFMLCBITPT 4th Error bit pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern Bit [31:24] [23:16] [15:8] [7:0] 4th Error bit pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern Description Initial State 0x00 0x00 0x00 0x00 4-25 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.3 ECC REGISTERS FOR 8, 12 AND 16-BIT ECC 4.5.3.1 Nand Flash ECC Configuration Register (NFECCCONF, R/W, Address = 0xB0E2_0000) NFECCCONF Reserved Reserved MsgLength Reserved ECCType Bit [31] [28] [25:16] [15:4] [3:0] Description Reserved Reserved The ECC message size. For 512-byte message, you should set 511. Reserved These bits indicate what kind of ECC is used. 000 = Disable 8/ 12/ 16-bit ECC 001 = Reserved 010 = Reserved 011 = 8-bit ECC/512B 100 = 12-bit ECC 101 = 16-bit ECC/512B 110 = Reserved 111 = Reserved Initial State 0 0 0 0x0 4.5.3.2 Nand Flash ECC Control Register (NFECCCONT, R/W, Address = 0xB0E2_0020) NFECCCONT Reserved EnbMLCEncInt EnbMLCDecInt EccDirection Reserved InitMECC Reserved ResetECC Bit [31:26] [25] [24] [16] [15:3] [2] [1] [0] Description Reserved MLC ECC encoding completion interrupt control 0 = Disable interrupt 1 = Enable interrupt MLC ECC decoding completion interrupt control 0 = Disable interrupt 1 = Enable interrupt MLC ECC encoding / decoding control 0 = Decoding, used for page read 1 = Encoding, used for page program Reserved 1 = Initialize main area ECC decoder/ encoder (write-only) Reserved 1 = Reset ECC logic. (Write-only) Initial State 0x00 0 0 0 0x0 0 0 0 4-26 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.3.3 Nand Flash ECC Status Register (NFECCSTAT, R/W, Address = 0xB0E2_0030) NFECCSTAT ECCBusy Reserved EncodeDone DecodeDone Reserved FreePageStat Reserved Bit [31] [30] [25] [24] [23:9] [8] [7:0] Description Indicates the 8-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy Reserved When MLC ECC encoding is finished, this value set and issue interrupt if EncodeDone is enabled. The NFMLCECC0 and NFMLCECC1 have valid values. To clear this, write ‘1’. 1 = MLC ECC encoding is completed When MLC ECC decoding is finished, this value set and issue interrupt if DecodeDone is enabled. The NFMLCBITPT, NFMLCL0 and NFMLCEL1 have valid values. To clear this, write ‘1’. 1 = MLC ECC decoding is completed Reserved It indicates whether the sector is free page or not. Reserved Initial State 0 1 0 0 0x0000 0 0x00 4.5.3.4 Nand Flash ECC Sector Status Register (NFECCSECSTAT, R, Address = 0xB0E2_0040) NFECCSECSTAT ValdErrorStat Bit [31:8] Description Each bit indicates which ERL and ERP is valid or not. Initial State 0x0000_00 ECCErrorNo [4:0] ECC decoding result when page read 00000 = No error 00001 = 1-bit error 00010 = 2-bit error 00011 = 3-bit error .... 01110 = 14-bit error 01111 = 15-bit error 10000 = 16-bit error Note: If 8-bit ECC is used, the valid number of error is until 8. If the number exceeds the supported error number, it means that uncorrectable error occurs. 0x00 4-27 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.3.5 Nand Flash ECC Parity code for Page Program Register (NFECCPRGECC*, R, Address = 0xB0E2_0090 ~ 0xB0E2_00A8) NFECCPRGECC0 4th Parity 3rd Parity 2nd Parity 1st Parity NFECCPRGECC1 8th Parity 7th Parity 6th Parity 5th Parity NFECCPRGECC2 12th Parity 11th Parity 10th Parity 9th Parity NFECCPRGECC3 16th Parity 15th Parity 14th Parity 13th Parity NFECCPRGECC4 20th Parity 19th Parity 18th Parity 17th Parity NFECCPRGECC5 24th Parity 23rd Parity 22th Parity 21th Parity NFECCPRGECC6 Reserved 26th Parity 25th Parity Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:16] [15:8] [7:0] Description 4th Check Parity for page program from main area 3rd Check Parity for page program from main area 2nd Check Parity for page program from main area 1st Check Parity for page program from main area Description 8th Check Parity generated from main area 7th Check Parity generated from main area 6th Check Parity generated from main area 5th Check Parity generated from main area Description 12th Check Parity generated from main area 11th Check Parity generated from main area 10th Check Parity generated from main area 9th Check Parity generated from main area Description 16th Check Parity generated from main area 15th Check Parity generated from main area 14th Check Parity generated from main area 13th Check Parity generated from main area Description 20th Check Parity generated from main area 19th Check Parity generated from main area 18th Check Parity generated from main area 17th Check Parity generated from main area Description 24th Check Parity generated from main area 23rd Check Parity generated from main area 22th Check Parity generated from main area 21th Check Parity generated from main area Description Reserved 26th Check Parity generated from main area 25th Check Parity generated from main area Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State - 0x00 0x00 NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock (NFCON[7]) bit is ‘0’(unlock). 4-28 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.3.6 MLC ECC Error Byte Location Status Register (NFECCERL0~7, R, Address = 0xB0E2_00C0 ~ 0xB0E2_00DC) NFECCERL0 Reserved ErrByteLoc2 Reserved ErrByteLoc1 NFECCERL1 Reserved ErrByteLoc4 Reserved ErrByteLoc3 NFECCERL2 Reserved ErrByteLoc6 Reserved ErrByteLoc5 NFECCERL3 Reserved ErrByteLoc8 Reserved ErrByteLoc7 NFECCERL4 Reserved ErrByteLoc10 Reserved ErrByteLoc9 NFECCERL5 Reserved ErrByteLoc12 Reserved ErrByteLoc11 NFECCERL6 Reserved ErrByteLoc14 Reserved ErrByteLoc13 NFECCERL7 Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit [31:26] [25:16] [15:10] [9:0] Bit Description Reserved Error byte location of 2nd bit error Reserved Error byte location of 1st bit error Description Reserved Error byte location of 4th bit error Reserved Error byte location of 3rd bit error Description Reserved Error byte location of 6th bit error Reserved Error byte location of 5th bit error Description Reserved Error byte location of 8th bit error Reserved Error byte location of 7th bit error Description Reserved Error byte location of 10th bit error Reserved Error byte location of 9th bit error Description Reserved Error byte location of 12th bit error Reserved Error byte location of 11th bit error Description Reserved Error byte location of 14th bit error Reserved Error byte location of 13th bit error Description Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 0x0 0x000 0x0 0x000 Initial State 4-29 S5PV210_UM 4 NAND FLASH CONTROLLER Reserved ErrByteLoc16 Reserved ErrByteLoc15 [31:26] [25:16] [15:10] [9:0] Reserved Error byte location of 16th bit error Reserved Error byte location of 15th bit error NOTE: These values are updated when DecodeDone (NFECCSTAT[24]) is set (‘1’). 0x0 0x000 0x0 0x000 4.5.3.7 MLC ECC Error Patten Register (NFECCERP0~3, R, Address = 0xB0E2_00F0 ~ 0xB0E2_00FC) NFECCERP0 4th ErrBitPattern 3rd ErrBitPattern 2nd ErrBitPattern 1st ErrBitPattern NFECCERP1 8th ErrBitPattern 7th ErrBitPattern 6th ErrBitPattern 5th ErrBitPattern NFECCERP2 12th ErrBitPattern 11th ErrBitPattern 10th ErrBitPattern 9th ErrBitPattern NFECCERP3 16th ErrBitPattern 15th Error bit pattern 14th ErrBitPattern 13th ErrBitPattern Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] 4th Error bit pattern 3rd Error bit pattern 2nd Error bit pattern 1st Error bit pattern 8th Error bit pattern 7th Error bit pattern 6th Error bit pattern 5th Error bit pattern 12th Error bit pattern 11th Error bit pattern 10th Error bit pattern 9th Error bit pattern 16th Error bit pattern 15th Error bit pattern 14th Error bit pattern 13th Error bit pattern Description Description Description Description Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 NOTE: These values are updated when DecodeDone (NFECCSTAT[25]) is set (‘1’). 4-30 S5PV210_UM 4 NAND FLASH CONTROLLER 4.5.3.8 ECC Parity Conversion Register (NFECCCONECC0~6, R/W, Address = 0xB0E2_0110 ~ 0xB0E2_0128) NFECCCONECC0 4th Conversion Code 3rd Conversion Code 2nd Conversion Code 1st Conversion Code NFECCCONECC1 8th Conversion Code 7th Conversion Code 6th Conversion Code 5th Conversion Code NFECCCONECC2 12th Conversion Code 11th Conversion Code 10th Conversion Code 9th Conversion Code NFECCCONECC3 16th Conversion Code 15th Conversion Code 14th Conversion Code 13th Conversion Code NFECCCONECC4 20th Conversion Code 19th Conversion Code 18th Conversion Code 17th Conversion Code NFECCCONECC5 24th Conversion Code 23th Conversion Code 22th Conversion Code 21th Conversion Code NFECCCONECC6 Reserved 26th Conversion Code 25th Conversion Code Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:24] [23:16] [15:8] [7:0] Bit [31:16] [15:8] [7:0] Description 4th ECC Parity conversion code 3rd ECC Parity conversion code 2nd ECC Parity conversion code 1st ECC Parity conversion code Description 8th ECC Parity conversion code 7th ECC Parity conversion code 6th ECC Parity conversion code 5th ECC Parity conversion code Description 12th ECC Parity conversion code 11th ECC Parity conversion code 10th ECC Parity conversion code 9th ECC Parity conversion code Description 16th ECC Parity conversion code 15th ECC Parity conversion code 14th ECC Parity conversion code 13th ECC Parity conversion code Description 20th ECC Parity conversion code 19th ECC Parity conversion code 18th ECC Parity conversion code 17th ECC Parity conversion code Description 24th ECC Parity conversion code 23th ECC Parity conversion code 22th ECC Parity conversion code 21th ECC Parity conversion code Description Reserved 26th ECC Parity conversion code 25th ECC Parity conversion code Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x00 0x00 0x00 0x00 Initial State 0x0000 0x00 0x00 NOTE: For more information about ECC parity conversion codes, refer to the 4.3.11 . 4-31 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5 COMPACT FLASH CONTROLLER 5.1 OVERVIEW OF COMPACT FLASH CONTROLLER A Compact Flash Controller (CFC) connects seamlessly to the AHB Bus as a Bus slave and AHB Master. The CFC subsystem recognizes AHB Bus transactions that target the compact flash card. The Master Interface initiates compact flash card requests to the CFC block requester interface. The Slave interface responds to the requests initiated. To complete the AHB Bus transaction, the CFC drives the appropriate AHB response onto the AHB Bus. The CFC can control the Hard Disk and the Compact Flash that can operate in true IDE mode. 5.2 KEY FEATURES OF COMPACT FLASH CONTROLLER The key features of CFC are as follows: • Supports all ATA PIO from mode 0 to mode 4. • Supports Multi-Word DMA (MDMA) from mode 0 to mode 2. • Supports Ultra DMA (UDMA) from mode 0 to mode 4. • Connects up to two devices. 5-1 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.3 BLOCK DIAGRAM OF COMPACT FLASH CONTROLLER AHB Master AHB Slave FIFO Internal Control Logic ATA Interface ATA Device Interrupt Control ATA Controller Figure 5-1 Block Diagram of Compact Flash Controller 5.4 FUNCTIONAL DESCRIPTION The ATAPI controller is compatible with the ATA/ATAPI-5 standard. This mode allows I/O operations to the task file and data registers. It has access to one FIFO that is 16X32-bit. The ATAPI controller has internal DMA controller for data transfer between ATA device and memory. The ATAPI controller has 32 word-sized (32-bits) Special Function Registers. The ATAPI controller directly accesses the system RAM when it implements MDMA and UDMA data transfer. Therefore, there are three operating modes called PIO, MDMA, and UDMA in the ATA controller. The signal timing depends on the transfer class and its modes. The ATA host controller supports several classes PIO, MDMA, and UDMA. They have various modes according to transfer data rate. The PIO class has five modes. The maximum transfer rate is mode 4. The MDMA has 3 modes, the maximum data rate is 16.7MB/s. The maximum transfer rates supported for the UDMA is mode 4(66MB/s). This ATAPI controller does not supported the ATA special driver(IO PAD) for UDMA. So user has to use the ATA cable which is shorter than 10cm. 5-2 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.5 TRUE IDE MODE PIO/ PDMA TIMING DIAGRAM The PIO transfer protocol supports 8-bit register access in driver and 16-bit PIO data access. If PIO mode 3 or 4 is the currently selected mode of operation, both hosts and devices support ATA_IORDY. The Figure 5-2 defines the relationships between host and device interface signals for data and registers transfer. 5-3 S5PV210_UM 5 COMPACT FLASH CONTROLLER Table 5-1 Table 5-1 describes the timing parameters of PIO modes. The Figure 5-2 shows the timing cycle of the true IDE PIO mode, if ATA controller is in the ATA_TRANS state. The figure indicates various timing parameters. Timing ‘t1’ indicates the time between address valid and IORD/IOWR asserted. Timing ‘t2’ indicates the time for which IORD/ IOWR is asserted. The ATA state transfer in PDMA class follows similar timing. t1 CS 0, CS 1, DA [2:0] t2 DIOR -/ DIOW - t1 teoc WR DD [ 15 :0] or DD [7:0] RD DD [ 15 :0] or DD [7:0] Figure 5-2 PIO Mode Waveform 5-4 S5PV210_UM 5 COMPACT FLASH CONTROLLER Register Transfer t1 t2 tEOC t1+t2+tEOC Data Transfer t1 t2 tEOC t1+t2+tEOC NOTE: unit “ns” Table 5-1 Timing Parameter Each PIO Mode MODE0 (70, --) (290, --) (240, --) (600, --) MODE0 (70, --) (165, --) (365, --) (600, --) MODE1 (50, --) (290, --) (43, --) (383, --) MODE1 (50, --) (125, --) (208, --) (383, --) MODE2 (30, --) (290, --) (10, --) (330, --) MODE2 (30, --) (100, --) (110, --) (240, --) MODE3 (30, --) (80, --) (70, --) (180, --) MODE3 (30, --) (80, --) (70, --) (180, --) MODE4 (25, --) (70, --) (25, --) (120, --) MODE4 (25, --) (70, --) (25, --) (120, --) 5.5.1 ATA_PIO_TIME REGISTER SETTING EXAMPLE (IN CASE OF DATA TRANSFER) The “t1” minimum time is 70ns in the system clock of 100MHz (10ns). It gives 7; “t1” divided by 10ns. This case has no residual, therefore pio_t1[3:0] assigns 6 which is 7 minus 1. If it has residual, assign the quotient at pio_t1[3:0]. • ATA_PIO_TIME (Tpara) = PIO mode (Minimum, Maximum)/ system clock - 1 • tPIO0 (Timing Parameter of PIO Mode 0 in case of Register Transfer) • t1: 70/10 = 7 pio_t1 value = 7- 1 = 6 pio_t1[3:0] • t2: 290/10 = 29 pio_t2 value = 29 - 1 = 28 pio_t2[11 :4] • teoc: 240/10 = 24 pio_teoc value = 24 - 1 = 23 pio_teoc[19:12] : 32’h000_17_1c_6 : 0x6 : 0x1c : 0x17 5-5 S5PV210_UM 5.6 FLOWCHART FOR PIO READ / WRITE 5 COMPACT FLASH CONTROLLER Figure 5-3 Flowchart for Read / Write in PIO Class 5-6 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.7 TRUE IDE MDMA MODE TIMING DIAGRAM The ATAPI MDMA streams data continuously across the ATA interface between the host and the target device. This transfer class allows either the driver or host to pause or terminate the data flow. To support various transfer speed classes, the CPU programs appropriate timing parameters. The ATA_CS0n and CS1n are inactive during MDMA transfer. The ATA Host controller is always the master in the MDMA transfer classes. The MDMA has three transfer modes (Mode 0 ~ 2). The fastest mode is mode 2. The Figure 5-4 defines the relationships between host and device interface signals for data transfer. The Table 5-2 describes the timing parameters of MDMA read and write transfer. tm td tEOC td+tEOC unit: ns Figure 5-4 MDMA Timing Diagram Table 5-2 MDMA Timing Parameters MODE0 (50, --) (215, --) (265, --) (480, --) MODE1 (30, --) (80, --) (70, --) (150, --) MODE2 (25, --) (70, --) (50, --) (120, --) 5-7 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.7.1 ATA_MDMA_TIME REGISTER SETTING EXAMPLE The “td” minimum time is 215ns in the system clock 100MHz (10ns). It gives 21.5; “td” divided by 10ns. This case has residual, assigning quotient (21) to the dma_td[3:0]. If it has no residual, assign the quotient minus 1 at dma_td[3:0]. • tMDMA0 (Timing Parameter of MDMA Mode 0) : 32’h000_1a_15_4 • tm: 50/10 = 5 dma_td value = 5 - 1 = 4 dma_tm[3 :0] • td: 215/10 = 21.5 dma_td value = 21 dma_td[11:4] • teoc: 265/10 = 26.5 dma_teoc value = 26 dma_teoc[19:12] : 0x4 : 0x15 : 0x1a Steps for ATAPI MDMA transfer protocol (To write and read transfer): Steps to Write Protocol: 1. Wait for the driver to activate ATA_DMARQ. 2. Activate ATA_DMACKn, deactivate ATA_CS0n/CS1n, and set time to 0. 3. Activate ATA_DIOWn at time tM. 4. Drive 16-bit data on the lines at time tD. 5. Deactivate ATA_DIOWn after tD. 6. If ATA_DMARQ is still active, repeat step 3 to 6 for another word, and deactivate ATA_DMACKn at time tM. Steps to Read Protocol: 1. Wait for the driver to activate ATA_DMARQ. 2. Activate ATA_DMACKn, deactivate ATA_CS0n/CS1n, and set time to 0. 3. Activate ATA_DIORn at time tM. 4. Deactivate ATA_DIORn and latch 16-bit data lines at time tD. 5. If ATA_DMARQ is still active, repeat step 3 to 5 for another word, and deactivate ATA_DMACKn at time tM. 5-8 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.8 TRUE IDE UDMA MODE TIMING DIAGRAM The Ultra-DMA (UDMA) is a fast DMA protocol which supports six timing modes (mode 0 ~ 5). Mode 5 is the fastest; it operates at 100MHz. This ATAPI host controller supports upto mode 4. It operates at 66MHz. Both host and device driver perform CRC check during UDMA burst transfer. At the end of the burst, the host sends its CRC result to the device. If the CRC result does not match, the driver reports an error in the error register and asserts the ATA_INTRQ signal. The following figures (Figure 5-5, Figure 5-6, Figure 5-7 and Figure 5-8) defines the relationships between host and device interface signals for UDMA data transfer. The timing parameters involved is tACKENV, tRP, tSS, tDVS, and tDVH. • tACKENV indicates the setup and hold times of DMACK (Before assertion or negation) and envelope time (From DMACKn to STOP and HDMARDYn). • tRP indicates Ready-to-pause time. • tSS indicates time from STROBE edge to negation of DMARQ or assertion of STOP. • tDVS is time for which data is valid until STROBE edge. • tDVH is time from STROBE edge until data is invalid. DMARQ DMACK DIOW DIOR CS0,CS1, DA[2:0] IORDY RD DD[15:0 ] or DD[7:0] tACKENV tACKENV tACKENV tACKENV tDVS tDVH CRC Figure 5-5 UDMA- In Operation (Terminated by Device) 5-9 S5PV210_UM 5 COMPACT FLASH CONTROLLER DMARQ DMACK DIOW DIOR CS0,CS1, DA[2:0] IORDY RD DD[15:0 ] or DD[7:0] tRP tACKENV tACKENV tDVS tDVH Figure 5-6 UDMA - In Operation (Terminated by Host) DMARQ DMACK DIOW DIOR CS0,CS1, DA[2:0] IORDY DD[15:0 ] or DD[7:0] tACKENV tACKENV tSS tACKENV tDVS tDVH tDVS tDVH tACKENV Figure 5-7 UDMA - Out Operation (Terminated by Device) 5-10 S5PV210_UM 5 COMPACT FLASH CONTROLLER DMARQ DMACK DIOW DIOR CS0,CS1, DA[2:0] IORDY DD[15:0 ] or DD[7:0] tACKENV tDVS tDVH Figure 5-8 UDMA - Out Operation (Terminated by Host) Table 5-3 Timing Parameter Each UDMA Mode UDMA mode tACKENV tSS tRP UDMA 0 (20, 70) (50, --) (160, --) UDMA 1 (20, 70) (50, --) (125, --) UDMA 2 (20, 70) (50, --) (100, --) UDMA 3 (20, 55) (50, --) (100, --) tDVS (70, --) (48, --) (31, --) (20, --) tDVH tDVS+tDVH (6.2, --) *(50) (120, --) (6.2, --) *(32) (80, --) (6.2, --) *(29) (60, --) (6.2, --) *(25) (45, --) NOTE: unit: ns, *(50) is “(tDVS+tDVH)” – “tDVS” = 120 – 70 = 50 UDMA 4 (20, 55) (50, --) (100, --) (6.7, --) (6.2, --) *(23.3) (30, --) 5-11 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.8.1 ATA_UDMA_TIME REGISTER SETTING EXAMPLE The “tackenv” minimum time is 20ns in the system clock of 100MHz (10ns). It gives 2; “tackenv” divided by 10ns. This case has no residual, therefore the udma_tackenv[3:0] assigns 1 which is 2 minus 1. If it has residual, assign the quotient at udma_tackenv[3:0]. ATA_UDMA_TIME (Tpara) = UDMA mode(min, max) / system clock – 1 tUDMA0(Timing Parameter of UDMA Mode 0) : 32’h04_06_0f_4_1 tackenv: 20/10 = 2 udma_tackenv value = 2 - 1 = 1 udma_tackenv[3 :0] : 0x1 tss: 50/10 = 5 udma_tss value = 5 - 1 = 4 udma_tss[7:4] : 0x4 trp: 160/10 = 16 udma_trp value = 16 -1 = 15 udma_trp[15:8] : 0x0f tdvs: 70/10 = 7 udma_tdvs value = 7 - 1 =6 udma_tdvs[23:16] : 0x06 tdvh: 50/10 = 5 udma_tdvh value = 5 - 1 = 4 udma_tdvh[27:24] : 0x4 (tdvh minimum timing is 6.2ns, but the timing parameter sets 50ns since the tDVS and tDVH summation is 120ns) The Table 5-4 shows True-IDE Mode Control Signaling: Table 5-4 True-IDE Mode I/O Decoding nCE2 nCE1 A2 A1 A0 nDMACK nIORD=0 nIOWR=0 1 0 0 0 0 1 PIO RD data PIO WR data 1 1 X X X 0 DMA RD data DMA WR data 1 0 0 0 1 1 Error Register Feature 1 0 0 1 0 1 Sector Count Sector Count 1 0 0 1 1 1 Sector No. Sector No. 1 0 1 0 0 1 Cylinder Low Cylinder Low 1 0 1 0 1 1 Cylinder High Cylinder High 1 0 1 1 0 1 Select Card/Head Select Card/Head 1 0 1 1 1 1 Status Command 0 1 1 1 0 1 Alt Status Device Control Note 8 or 16 bit 16bit 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 5-12 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.9 TRANSFER STATE ABORT The PIO, PDMA, MDMA or UDMA checks for abort or stop transfer state after completing one full cycle of the finite state machine (FSM). The FSM transition from IDLE state happens if ATA transfer state is in ATA_TRANS. The FSM continues the cycle while the abort is asserted. The transfer in any class stays in IDLE after detecting ATA state in ATA_ABORT. Figure 5-9 Flowchart for Abort in ATA Mode 5-13 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.10 I/O DESCRIPTION Signal CSn0 CSn1 DA[2:0] DD_RD[15:0] DD_WR[15:0] DD_wr_en IORDY INTRQ DMARQ DRESETn DMACKn DIORn (HDMA_RDYn, HSTROBE) DIOWn I/O Description O Device chip selection signal To select the control block registers O Device chip selection signal To select the command block registers O register address signals I Read Data Bus O Write Data Bus O Data Output Enable Strobe I Data transfer wait signal. DMA ready during UDMA write. DMA strobe during UDMA read. I Device Interrupt signal. I The DMA request signal for data transfers between host and device. O Device reset signal from host. O The DMA acknowledge signal that data has been accepted or data is available. O IO Read Enable Strobe. DMA ready during UDMA read. Data strobe during UDMA write O IO Write Enable Strobe Stop during UDMA read. Pad XmsmCSn XmsmWEn XmsmADDR[2:0] XmsmDATA[15:0] XmsmDATA[15:0] XmsmADDR[3] XmsmADDR[4] XmsmADDR[5] XmsmADDR[6] XmsmADDR[7] XmsmRn XmsmIRQn Type muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed muxed 5-14 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11 REGISTER DESCRIPTION 5.11.1 REGISTER MAP Register ATA_CONTROL ATA_STATUS ATA_COMMAND ATA_SWRST ATA_IRQ ATA_IRQ_MASK ATA_CFG Reserved Reserved Reserved ATA_MDMA_TIME ATA_PIO_TIME ATA_UDMA_TIME ATA_XFR_NUM ATA_XFR_CNT ATA_TBUF_BASE ATA_TBUF_SIZE ATA_SBUF_BASE ATA_SBUF_SIZE ATA_CADR_TBUF ATA_CADR_SBUF ATA_PIO_DTR ATA_PIO_FED ATA_PIO_SCR ATA_PIO_LLR ATA_PIO_LMR Address 0xE820_0000 0xE820_0004 0xE820_0008 0xE820_000C 0xE820_0010 0xE820_0014 0xE820_0018 0xE820_001C 0xE820_0020 0xE820_0024 0xE820_0028 0xE820_002C 0xE820_0030 0xE820_0034 0xE820_0038 0xE820_003C 0xE820_0040 0xE820_0044 0xE820_0048 0xE820_004C 0xE820_0050 0xE820_0054 0xE820_0058 0xE820_005C 0xE820_0060 0xE820_0064 R/W Description R/W Specifies the ATA enable and clock down status R Specifies the ATA status R/W Specifies the ATA command R/W Specifies the ATA software reset R/W Specifies the ATA interrupt sources R/W Specifies the ATA interrupt mask R/W Specifies the ATA configuration for ATA interface R/W Reserved R/W Reserved R/W Reserved R/W Specifies the ATA multi-word DMA timing R/W Specifies the ATA PIO timing R/W Specifies the ATA UDMA timing R/W Specifies the ATA transfer number R Specifies the ATA current transfer count R/W Specifies the ATA start address of track buffer R/W Specifies the ATA size of track buffer R/W Specifies the ATA start address of source buffer R/W Specifies the ATA size of source buffer R Specifies the ATA current write address of track buffer R Specifies the ATA current read address of source buffer R/W Specifies the ATA PIO device data register R/W Specifies the ATA PIO device Feature/ Error register R/W Specifies the ATA PIO sector count register R/W Specifies the ATA PIO device LBA low register R/W Specifies the ATA PIO device LBA middle register Reset Value 0x00000002 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x80000000 0x0002c238 0x000272fa 0x080b1a83 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 5-15 S5PV210_UM 5 COMPACT FLASH CONTROLLER Register ATA_PIO_LHR Address 0xE820_0068 ATA_PIO_DVR ATA_PIO_CSD 0xE820_006C 0xE820_0070 ATA_PIO_DAD 0xE820_0074 ATA_PIO_READY ATA_PIO_RDATA 0xE820_0078 0xE820_007C BUS_FIFO_STATUS 0xE820_0080 ATA_FIFO_STATUS 0xE820_0084 R/W Description R/W Specifies the ATA PIO device LBA high register R/W Specifies the ATA PIO device register R/W Specifies the ATA PIO device command/ status register R/W Specifies the ATA PIO device control/ alternate status register R Specifies the ATA PIO data read/ write ready R Specifies the ATA PIO read data from device data register R Specifies the ATA internal AHB FIFO status R Specifies the ATA internal ATA FIFO status Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00000000 5-16 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.1.1 ATA Control Register (ATA_CONTROL, R/W, Address = 0xE820_0000) ATA_CONTROL Reserved clk_down_ready ata_enable Bit [31:2] [1] [0] Description Reserved Status for clock down This bit is asserted in idle state if ATA_CONTROL bit [0] is zero. 0 = Not ready for clock down 1 = Ready for clock down Enables ATA 0 = Disables ATA and preparation for clock down. 1 = Enables ATA. R/W R R R/W Initial State 0x0 0x1 0x0 5.11.1.2 ATA Status Register (ATA_STATUS, R, Address = 0xE820_0004) ATA_STATUS Reserved atadev_cblid atadev_irq atadev_iordy atadev_dmareq xfr_state Bit [31:6] [5] [4] [3] [2] [1:0] Description Reserved ATAPI cable identification ATAPI interrupt signal line ATAPI iordy signal line ATAPI dmareq signal line Transfer state 2’b00 = Idle state 2’b01 = Transfer state 2’b10 = Abort state 2’b11 = Wait for completion state R/W Initial State R 0x0 R 0x0 R 0x0 R 0x1 R 0x0 R 0x0 5-17 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2 ATA COMMAND REGISTER (ATA_COMMAND, R/W, ADDRESS = 0XE820_0008) ATA_COMMAND Bit Description R/W Reserved [31:2] Reserved R xfr_command [1:0] ATA transfer command R/W Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control. The “START” command starts data transfer. The “STOP” command pause transfer temporarily. The “CONTINUE” command is used after “STOP” command or internal state of “pause” if track buffer is full or UDMA hold state. The “ABORT” command terminates current data transfer sequences and make ATA host controller move to idle state. 00 = Stop command 01 = Start command (Available in idle state) 10 = Abort command 11 = Continue command (Available in transfer pause) ** After CPU ABORT commands, make a software reset by ATA_SWRST to clear the leftover values of internal registers. Initial State 0x0 0x0 The STOP command controls the ATA Device side signal but does not control DMA side. Namely, if the FIFO has data after STOP command, DMA operation progresses until the FIFO becomes empty at read operation. In case of write operation, the DMA acts similarly until the FIFO becomes full. Use the ABORT command if the transmitting data has proven useless data or discontinues absurd state by error interrupt from device. At that time, it clears all data in ATA Host controller (register, FIFO) and the transmission state machine goes to IDLE. 5-18 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.1 ATA Software Reset (ATA_SWRST, R/W, Address = 0xE820_000C) ATA_SWRST Reserved ata_swrst Bit [31:1] [0] Description Reserved Software reset for the ATAPI host 0 = No reset 1 = Resets device registers and all registers of ATAPI host controller except CPU interface registers. After software reset, to continue transfer, user must configure all registers of host controller and device registers. R/W Initial State R 0x0 R/W 0x0 5.11.2.2 ATA Interrupt Register (ATA_IRQ, R/W, Address = 0xE820_0010) ATA_IRQ Reserved mdma_hold_int sbuf_empty_int tbuf_full_int atadev_irq_int udma_hold_int xfr_done_int Bit Description R/W Initial State [31:6] Reserved R 0x0 [5] If ATAPI device makes pending in MDMA class. CPU R/W 0x0 clears this interrupt by writing “1”. [4] If source buffer is empty. CPU clears this interrupt by writing “1”. R/W 0x0 [3] If track buffer is half-full. CPU clears this interrupt by writing “1”. R/W 0x0 [2] If ATAPI device generates interrupt. CPU clears this interrupt by writing “1”. R/W 0x0 [1] If ATAPI device makes early termination in UDMA class. R/W 0x0 CPU clears this interrupt by writing “1”. [0] If all data transfers are complete. CPU clears this interrupt by writing “1”. R/W 0x0 5-19 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.3 ATA Interrupt Mask Register (ATA_IRQ_MASK, R/W, Address = 0xE820_0014) ATA_IRQ_MASK Bit Description R/W Reserved [31:6] Reserved R mask_mdma_hold_int [5] 0 = Mask mdma_hold_int; Disable R/W 1 = Unmask mdma_hold_int; Enable mask_sbut_empty_int [4] 0 = Mask sbut_empty_int; Disable R/W 1 = Unmask sbuf_empty_int; Enable mask_tbuf_full_int [3] 0 = Mask tbuf_full_int; Disable R/W 1 = Unmask tbuf_full_int; Enable mask_atadev_irq_int [2] 0 = Mask atadev_irq_int; Disable R/W 1 = Unmask ata_irq_int; Enable mask_udma_hold_int [1] 0 = Mask udma_hold_int; Disable R/W 1 = Unmask udma_hold_int; Enable mask_xfr_done_int [0] 0 = Mask xfr_done_int; Disable R/W 1 = Unmask xfr_done_int; Enable Initial State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5-20 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.4 ATA Configuration Register (ATA_CFG, R/W, Address = 0xE820_0018) ATA_CFG Bit Description R/W Initial State Reserved [31] Reserved (This field should be 0x1) R/W 0x1 Reserved [30:13] Reserved R 0x0 dma_mode [12] Determines whether DMA is normal DMA 0 = Normal DMA mode 1 = Reserved. R/W 0x0 Reserved [11] Reserved R word_swap [10] Determines whether endian is little or big in AHB word R/W 0x0 data. (half word swapping) 0 = Little endian {byte3, byte2, byte1, byte0} 1 = Big endian {byte1, byte0, byte3, byte2} udma_auto_mode [9] Determines whether to continue automatically in case of R/W 0x0 early termination in UDMA mode by Device. This bit shoud not be changed during runtime operation. 0 = Stay in pause state and wait for CPU's action. 1 = Continue automatically Reserved [8] Reserved R 0x0 Reserved [7] Reserved R 0x0 byte_swap [6] Determines whether data endian is little or big in 16-bit R/W 0x0 data. 0 = Little endian ( data[15:8], data[7:0] ) 1 = Big endian ( data[7:0], data[15:8] ) In case of PIO mode; 0 = Big endian 1 = Little endian. atadev_irq_al [5] Device interrupt signal level 0 = Active high 1 = Active low R/W 0x0 dma_dir [4] DMA transfer direction 0 = Host read data from device 1 = Host write data to device R/W 0x0 ata_class [3:2] Selects ATA transfer class 2’b00 = Transfer class is PIO 2’b01 = Transfer class is PIO DMA 2’b10 = Transfer class is Multi-word DMA 2’b11 = Transfer class is UDMA R/W 0x0 ata_iordy_en [1] Determines whether IORDY input extends data transfer. R/W 0x0 0 = Disables IORDY ( ignored ) 1 = Enables IORDY ( can extend ) ata_rst [0] ATAPI device reset by this host. 0 = No reset 1 = Reset R/W 0x0 5-21 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.5 ATA Multi_word DMA Timing (ATA_MDMA_TIME, R/W, Address = 0xE820_0028) ATA_MDMA_TIME Bit Description R/W Reserved [31:20] Reserved R dma_teoc [19:12] DMA timing parameter, Teoc, end of cycle time R/W dma_t2 [11:4] DMA timing parameter, tD, DIOR/DIOWn pulse width R/W dma_t1 [3:0] DMA timing parameter, tM, CS0,1n valid to DIOR/Wn R/W Initial State 0x0 0x2C 0x23 0x8 5.11.2.6 ATA PIO Time (ATA_PIO_TIME, R/W, Address = 0xE820_002C) ATA_PIO_TIME Reserved pio_teoc pio_t2 pio_t1 Bit [31:20] [19:12] [11:4] [3:0] Description Reserved PIO timing parameter, teoc, end of cycle time It shall not have zero value. PIO timing parameter, t2, DIOR/Wn pulse width It cannot have zero value. PIO timing parameter, t1, address valid to DIOR/Wn R/W Initial State R 0x0 R/W 0x27 R/W 0x2f R/W 0xa 5.11.2.7 ATA UDMA Time (ATA_UDMA_TIME, R/W, Address = 0xE820_0030) ATA_UDMA_TIME Bit Description R/W Reserved [31:28] Reserved R udma_tdvh [27:24] UDMA timing parameter tDVH R/W udma_tdvs [23:16] UDMA timing parameter tDVS R/W It cannot have zero value. udma_trp [15:8] UDMA timing parameter tRP R/W udma_tss [7:4] UDMA timing parameter, tSS R/W udma_tackenv [3:0] UDMA timing parameter tENV (envelope time (From R/W DMACKn to STOP and HDMARDYn), tACK (setup and hold time for DMACKn) Initial State 0x0 0x8 0x0b 0x1a 0x8 0x3 5-22 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.8 ATA Transfer Count Number (ATA_XFR_NUM, R/W, Address = 0xE820_0034) ATA_XFR_NUM Bit Description R/W xfr_num [31:1] Data transfer number. R/W To transfer 1-sector (512-byte), you should set 32’h1ff. Reserved [0] Reserved R Initial State 0x00000000 0x0 5.11.2.9 ATA Current Transfer Count (ATA_XFR_CNT, R, Address = 0xE820_0038) ATA_XFR_CNT Bit Description R/W xfr_cnt [31:1] Current remaining transfer counter. This value counts R down from ATA_XFR_NUM. It goes to zero if all pre- defined data are transferred. In case of read transfer, ATA_XFR_NUM decreases by 1(2-byte). In case of write transfer, ATA_XFR_NUM decreases by 16(32-byte), because the AHB burst size is 8. Reserved [0] Reserved R Initial State 0x00000000 0x0 5.11.2.10 Start Address of the Track Buffer (ATA_TBUF_BASE, R/W, Address = 0xE820_003C) ATA_TBUF_BASE track_buffer_base Reserved Bit Description [31:2] Start address of track buffer (4 byte unit) [1:0] Reserved R/W Initial State R/W 0x00000000 R 0x0 5.11.2.11 Size of the Track Buffer (ATA_TBUF_SIZE, R/W, Address = 0xE820_0040) ATA_TBUF_SIZE Bit Description R/W track_buffer_size [31:5] Size of track buffer (32 byte unit) R/W This should be set to “size_of_data_in_bytes – 1”. For example, to transfer 1-sector (512-byte, 32’h200), you should set 32’h1FF ( = 32’h200 – 1). Reserved [4:0] Reserved R Initial State 0x0000000 0x00 5.11.2.12 Start Address of the Source Buffer (ATA_SBUF_BASE, R/W, Address = 0xE820_0044) ATA_SBUF_BASE src_buffer_base Reserved Bit Description [31:2] Start address of source buffer (4byte unit) [1:0] Reserved R/W Initial State R/W 0x00000000 R 0x0 5-23 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.13 Size of Source Buffer (ATA_SBUF_SIZE, R/W, Address = 0xE820_0048) ATA_SBUF_SIZE Bit Description R/W Initial State src_buffer_size [31:5] Size of source buffer (32byte unit) R/W This should be set to “size_of_data_in_bytes – 1”. For example, to transfer 1-sector (512-byte, 32’h200), you should set 32’h1FF ( = 32’h200 – 1). 0x0000000 Reserved [4:0] Reserved R 0x00 5.11.2.14 Current Address of Track Buffer (ATA_CADDR_TBUF, R, Address = 0xE820_004C) ATA_CADDR_TBUF track_buf_cur_adr Reserved Bit Description [31:2] Current address of track buffer [1:0] Reserve R/W Initial State R 0x00000000 R 0x0 5.11.2.15 Current Address of Source Buffer (ATA_CADDR_SBUF, R, Address = 0xE820_0050) ATA_CADDR_SBUF source_buf_cur_adr Reserved Bit [31:2] [1:0] Description Current address of source buffer Reserved R/W Initial State R 0x00000000 R 0x0 5.11.2.16 ATA PIO Data Register (ATA_PIO_DTR, R/W, Address = 0xE820_0054) ATA_PIO_DTR Reserved pio_dev_dtr Bit Description [31:16] Reserved [15:0] 16-bit PIO data register R/W Initial State R 0x0 R/W 0x0000 5.11.2.17 ATA PIO Device Feature/Error Register (ATA_PIO_FED, R/W, Address = 0xE820_0058) ATA_PIO_FED Reserved pio_dev_fed Bit Description R/W Initial State [31:8] Reserved R 0x0 [7:0] 8-bit PIO device feature/ error (command block) register R/W 0x00 5.11.2.18 ATA PIO Device Sector Count Register (ATA_PIO_SCR, R/W, Address = 0xE820_005C) ATA_PIO_SCR Reserved pio_dev_scr Bit [31:8] [7:0] Description Reserved 8-bit PIO device sector count (command block) register R/W Initial State R 0x0 R/W 0x00 5-24 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.19 ATA PIO Device LBA Low Register (ATA_PIO_LLR, R/W, Address = 0xE820_0060) ATA_PIO_LLR Reserved pio_dev_llr Bit [31:8] [7:0] Description Reserved 8-bit PIO device LBA low (command block) register R/W Initial State R 0x0 R/W 0x00 5.11.2.20 ATA PIO Device LBA Middle Register (ATA_PIO_LMR, R/W, Address = 0xE820_0064) ATA_PIO_LMR Reserved pio_dev_lmr Bit [31:8] [7:0] Description Reserved 8-bit PIO device LBA middle (command block) register R/W Initial State R 0x0 R/W 0x00 5.11.2.21 ATA PIO Device LBA High Register (ATA_PIO_LHR, R/W, Address = 0xE820_0068) ATA_PIO_LHR Reserved pio_dev_lhr Bit [31:8] [7:0] Description Reserved 8-bit PIO LBA high (command block) register R/W Initial State R 0x0 R/W 0x00 5.11.2.22 ATA PIO Device Register (ATA_PIO_DVR, R/W, Address = 0xE820_006C) ATA_PIO_DVR Bit Description R/W Reserved [31:8] Reserved R pio_dev_dvr [7:0] 8-bit PIO device (command block) register R/W Initial State 0x0 0x00 5.11.2.23 ATA PIO Device Command Status Register (ATA_PIO_CSD, R/W, Address = 0xE820_0070) ATA_PIO_CSD Reserved pio_dev_csd Bit [31:8] [7:0] Description Reserved 8-bit PIO device command/status (command block) register R/W Initial State R 0x0 R/W 0x00 5.11.2.24 ATA PIO Device Control/Alternate Status Register (ATA_PIO_DAD, R/W, Address = 0xE820_0074) ATA_PIO_DAD Reserved pio_dev_dad Bit [31:8] [7:0] Description Reserved 8-bit PIO device control/ alternate status (control block) register R/W Initial State R 0x0 R/W 0x00 5-25 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.25 ATA PIO Data Ready Register (ATA_PIO_READY, R, Address = 0xE820_0078) ATA_PIO_READY Bit Description R/W Reserved [31:2] Reserved R dev_acc_ready [1] Indicates whether host can start access to device register R 0 = Not ready to start access ATA device register 1 = Ready to start access ATA device register pio_data_ready [0] Indicates whether data is valid in ATA_PIO_DATA R register 0 = No valid data in ATA_PIO_DATA register 1 = Valid data in ATA_PIO_DATA register Initial State 0x0 0x1 0x1 5.11.2.26 ATA PIO Read Data Register (ATA_PIO_RDATA, R, Address = 0xE820_007C) ATA_PIO_RDATA Bit Description R/W Reserved [31:16] Reserved R pio_rdata [15:0] PIO read data register while HOST read from ATA R device register Initial State 0x0 0x0000 5.11.2.27 AHB Bus FIFO Status Register (BUS_FIFO_STATUS, R, Address = 0xE820_0080) BUS_FIFO_STATUS Bit Description Reserved [31:19] Reserved bus_state[2:0] [18:16] 3’b000 = IDLE 3’b001 = BUSYW 3’b010 = PREP 3’b011 = BUSYR 3’b100 = PAUSER 3’b101 = PAUSEW 3’b110 = PAUSER2 Reserved [15:14] Reserved bus_fifo_rdpnt [13:8] Bus FIFO read pointer Reserved [7:6] Reserved bus_fifo_wrpnt [5:0] Bus FIFO write pointer R/W Initial State R 0x0 R 0x00 R 0x0 R 0x00 R 0x0 R 0x00 5-26 S5PV210_UM 5 COMPACT FLASH CONTROLLER 5.11.2.28 ATA FIFO Status Register (ATA_FIFO_STATUS, R, Address = 0xE820_0084) ATA_FIFO_STATUS Bit Description R/W Reserved [31] Reserved R ata_state [30:28] 0 = ATA_IDLE R 1 = ATA_TRANS 2 = ATA_PAUSE 3 = ATA_PAUSE2 4 = ATA_ABORT pio_state [27:26] 2’b00 = IDLE R 2’b01 = T1 2’b10 = T2 2’b11 = TEOC pdma_state [25:24] 2’b00 = IDLE R 2’b01 = T1 2’b10 = T2 2’b11 = TEOC Reserved [23] Reserved R dma_state[1:0] [22:21] 0 = IDLE R 1 = TD 2 = TM 3 = TEOC udma_state[4:0] [20:16] 5’b00000 = IDLE R 5’b00001 = TMI 5’b00010 = CRCS 5’b00011 = CRCH 5’b00100 = END 5’b01000 = STOPW 5’b01001 = ACKW 5’b01010 = NSEQWS 5’b01011 = NSEQWH 5’b01100 = SEQWS 5’b01101 = SEQWH 5’b01110 = TSSW 5’b10000 = STOPR 5’b10001 = ACKR 5’b10010 = NSEQR 5’b10011 = SEQR 5’b10100 = TRPR 5’b10101 = STRPR Reserved [15:0] Reserved R Initial State 0x0 0x0000 0x0 0x0 0x0 0x00 0x00 0x0 5-27 S5PV210_UM 6 EXTERNAL BUS INTERFACE 6 EXTERNAL BUS INTERFACE 6.1 OVERVIEW OF EXTERNAL BUS INTERFACE The External Bus Interface (EBI) is used as a peripheral in S5PV210. It relies on memory controller to release external requests for external bus when the memory contro