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max 10 FPGA(10m80)开发板电路图

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    标    签:MAX10开发板

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    该文档是Altera公司MAX 10 FPGA(10m80)开发板电路图,包括开发板实物图与电路原理图.

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    5 4 REV DATE 1.0 11-Sep-14 Initial Production Release. D 3 REVISION INDEX DESCRIPTION OF CHANGES 2 1 PAGES BY APPROVED 1-8 Scott Lee Eric Kwok D C C B B A A Altera Corporation Designed by Axelsys LLC Title MAX R 10 10M08 Eval Kit Board Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 1 of 8 5 4 3 2 1 5 2 x 20 vias D 4 Arduino I/O 3 Arduino I/O 2 1 2 x 20 vias D High-Speed I/O 4 5 High-Speed I/O 3 C 6 C MAX 10M08 High-Speed I/O 7 8 2 1B 1A High-Speed I/O B B Arduino Power Arduino Analog A Switches & LEDs BLOCK DIAGRAM 5 4 3 A Altera Corporation Title MAX R 10 10M08 Eval Kit Board Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 2 of 8 2 1 5 4 3 VCCA_3.3V VCC_CORE U2-10 D C45 C44 C4 C7 C5 C6 C49 C48 1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VREF_2.5V C12 35 34 107 143 71 2 VCCA1 VCCA2 VCCA3 VCCA4 VCCA5 VCCA6 5 ADC_VREF 3 ANAIN1 VCC_ONE1 VCC_ONE2 VCC_ONE3 VCC_ONE4 VCC_ONE5 VCC_ONE6 VCC_ONE7 VCC_ONE8 VCC_ONE9 VCC_ONE10 73 72 51 37 36 144 115 109 108 1 1uF C R73 4 REFGND C46 0 0.1uF L3 Ferrite Bead GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 PAD 42 53 63 68 83 95 104 116 125 133 137 142 145 C8 C9 C10 C11 0.1uF 0.1uF 0.1uF 1uF VCC_CORE C13 0.1uF C14 0.1uF C15 0.1uF C16 0.1uF 10M08SAE144xxx FPGA 2 1 VBUS_5V NC(SW)2 15 NC(SW)3 16 U1 1 NC(SW)1 VIN 14 C1 4.7uF 2 PGND1 ENABLE 13 D 3 PGND2 VS0 12 R75 0 4 VFB VS1 11 R76 0 5 VSENSE VS2 10 R77 0 6 AGND NC 9 7 VOUT1 8 VOUT2 EP5388QI 3.3V 3.3V TP2 TP3 R1 0.1 VCC_CORE R2 R3 1K 100 DNI 1 D6 Green + C3 47uF/16V RES 0.1 OHM 1/2W 1% 0805 WIDE TP4 TP5 R4 0.1 VCC_IO RES 0.1 OHM 1/2W 1% 0805 WIDE C 2 Enpirion Step-down switching regulator VBUS_5V TP1 3.3V L2 1 TP6 2 VCCA_3.3V 1 C2 L1 0.1uF 600ohm 500mA C50 10uF B VCCA_3.3V U5 1 VIN VOUT 2 VREF_2.5V 2 600ohm 500mA B TP7 TP8 TP9 C47 0.1uF 3 VSS MCP1525 C61 R74 0 1uF Arduino_Vref 4 DNI J1 VCC DD+ ID GND 1 2 3 4 5 TIE AGND & DGND at U1 SKT_MINIUSB_B_RA A 5 USB Power A Altera Corporation Title MAX R 10 10M08 Eval Kit Board POWER SECTION Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 3 of 8 4 3 2 1 1 2 3 11 GND R6 11 GND 5 VBUS_5V 3.3V VCC_IO 5 RESET_N D J2 1 2 3 4 5 6 7 8 NC IOREF ARDUINO_RESET_N VCC3P3 VCC5 GND1 GND2 VCCI2 Arduino_A0 Arduino_A1 Arduino_A2 Arduino_A3 Arduino_A4 Arduino_A5 Arduino_A6 Arduino_A7 PPTC081LFBN-RC J4 1 2 3 4 5 6 7 8 ANALOG_IN0 ANALOG_IN1 ANALOG_IN2 ANALOG_IN3 ANALOG_IN4 ANALOG_IN5 ANALOG_IN6 ANALOG_IN7 PPTC081LFBN-RC C 4 J3 ANALOG_VREF GND ARDUINO_IO13 ARDUINO_IO12 ARDUINO_IO11 ARDUINO_IO10 ARDUINO_IO9 ARDUINO_IO8 1 2 3 4 5 6 7 8 PPTC081LFBN-RC J5 ARDUINO_IO7 ARDUINO_IO6 ARDUINO_IO5 ARDUINO_IO4 ARDUINO_IO3 ARDUINO_IO2 ARDUINO_IO1 ARDUINO_IO0 1 2 3 4 5 6 7 8 PPTC081LFBN-RC 3 2 1 Arduino_Vref 3 Arduino_IO13 5 Arduino_IO12 5 Arduino_IO11 5 Arduino_IO10 5 Arduino_IO9 5 Arduino_IO8 5 Arduino_IO7 5 Arduino_IO6 5 Arduino_IO5 5 Arduino_IO4 5 Arduino_IO3 5 Arduino_IO2 5 Arduino_IO1 5 Arduino_IO0 5 Bank 1A ADC1IN1 ADC1IN2 ADC1IN3 ADC1IN4 R89 R86 R87 100 R88 100 100 100 6 7 8 10 U2-1 DIFFIO_RX_L1N/ADC1IN1 DIFFIO_RX_L1P/ADC1IN2 DIFFIO_RX_L3N/ADC1IN3 DIFFIO_RX_L3P/ADC1IN4 DIFFIO_RX_L5N/ADC1IN5 DIFFIO_RX_L5P/ADC1IN6 DIFFIO_RX_L7N/ADC1IN7 DIFFIO_RX_L7P/ADC1IN8 11 12 13 14 100 R90 ADC1IN5 100 R91 ADC1IN6 100 R92 ADC1IN7 100 R93 ADC1IN8 C56 C55 C54 C53 1nF 1nF 1nF 1nF C57 C58 C59 C60 D VCCIO1A 9 1nF 1nF 1nF 1nF 10M08SAE144xxx FPGA Short-circuit Jumper JU1 JU2 VCCA_3.3V 0 C17 C18 0.1uF 1uF VCC_IO1A 6 63429-202LF 63429-202LF C VCCA_3.3V R10 316 Arduino_A0 R78 C22 316 1nF C51 0.1uF U3A VCC 4 2 3 1IN1OUT 1IN+ 1 ADC1IN1 LM2902DR2 R8 316 Arduino_A1 R79 C19 316 1nF U3B 6 5 2IN2OUT 2IN+ 7 LM2902DR2 ADC1IN2 U3C R7 316 Arduino_A2 9 10 3IN3OUT 3IN+ 8 R80 C21 316 1nF LM2902DR2 ADC1IN3 U3D R9 316 Arduino_A3 13 12 4IN4OUT 4IN+ 14 R81 C20 316 1nF LM2902DR2 ADC1IN4 VCCA_3.3V B B R15 1K 1 1 VCCA_3.3V C52 0.1uF U4A VCC 4 Arduino_A4 R20 316 2 3 1IN1OUT 1IN+ 1 R82 C25 316 1nF LM2902DR2 A ADC1IN5 5 R18 316 Arduino_A5 R83 C23 316 1nF U4B 6 5 2IN2OUT 2IN+ 7 LM2902DR2 ADC1IN6 R16 10K DNI 0.1 Header J7 HEADER 3 Arduino_A6 1 2 3 3 2 R94 10K DNI 2 3 U4C R19 316 9 10 3IN3OUT 3IN+ 8 R84 C26 316 1nF DNI LM2902DR2 ADC1IN7 ANALOG SECTION 4 3 2 0.1 Header J6 HEADER 3 Arduino_A7 U4D R17 316 13 12 4IN4OUT 4IN+ 14 ADC1IN8 R85 C24 316 1nF LM2902DR2 A Altera Corporation Title MAX R 10 10M08 Eval Kit Board Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 4 of 8 1 5 D C B A 5 4 3 2 1 D 3 Arduino_IO11 3 Arduino_IO12 3 Arduino_IO13 U2-5 66 DIFFIO_TX_RX_B25N 69 70 DIFFIO_TX_RX_B27N DIFFIO_TX_RX_B27P Bank 4 DIFFIO_TX_RX_B20P 62 DIFFIO_TX_RX_B23N DIFFIO_TX_RX_B23P 64 65 Arduino_IO8 3 Arduino_IO9 3 Arduino_IO10 3 6 VREFB4N0 61 VREFB4N0 VCCIO4 67 VCC_IO R25 10M08SAE144xxx FPGA 0 VCC_IO4 6 Arduino_IO12 J11 1 2 VBUS_5V C27 C28 0.1uF 1uF C Arduino_IO13 3 4 Arduino_IO11 4 RESET_N 5 6 87227-3 DNI Bank 5 3 Arduino_IO1 3 Arduino_IO3 3 Arduino_IO0 3 Arduino_IO2 3 Arduino_IO4 3 Arduino_IO5 U2-6 75 77 DIFFIO_RX_R1P DIFFIO_RX_R1N 74 76 DIFFIO_RX_R2P DIFFIO_RX_R2N 79 81 DIFFIO_RX_R7P DIFFIO_RX_R7N DIFFIO_RX_R10P DIFFIO_RX_R10N 85 87 DIFFIO_RX_R11P DIFFIO_RX_R11N 84 86 IO_78 78 Arduino_IO6 3 Arduino_IO7 3 VCC_IO B R26 7 VREFB5N0 80 VREFB5N0 VCCIO5 82 0 10M08SAE144xxx FPGA C29 C30 0.1uF 1uF VCC_IO5 7 A Altera Corporation Title MAX R 10 10M08 Eval Kit Board ARDUINO CONNECTION Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 5 of 8 4 3 2 1 5 4 3 2 1 J8 Bank 2 6 VCC_IO3 1 2 3 4 VREFB3N0 U2-3 DIFFIO_B16P 5 6 DIFFIO_B14P D OSC_OUT 26 27 DIFFIO_RX_L18N/CLK0N DIFFIO_RX_L18P/CLK0P DIFFIO_RX_L20N/CLK1N DIFFIO_RX_L20P/CLK1P 28 29 DIFFIO_L20N/CLK1N DIFFIO_L20P/CLK1P BANK 3 DIFFIO_B16N DIFFIO_B12P DIFFIO_B12N 7 8 9 10 11 12 DIFFIO_B14N DIFFIO_B9P DIFFIO_B9N D DIFFIO_RX_L27N/PLL_L_CLKOUTN DIFFIO_RX_L27P/PLL_L_CLKOUTP 32 33 DIFFIO_L27N/PLL_CLKOUTN DIFFIO_L27P/PLL_CLKOUTP DIFFIO_B7P DIFFIO_B7N DIFFIO_B3P 13 14 15 16 17 18 DIFFIO_B5P DIFFIO_B5N DIFFIO_B1P DIFFIO_B3N 19 20 DIFFIO_B1N VREFB2N0 30 VREFB2N0 VCCIO2 31 VCC_IO 6 VCC_IO2 21 22 23 24 VREFB2N0 DIFFIO_L27P/PLL_CLKOUTP 25 26 DIFFIO_L20P/CLK1P 10M08SAE144xxx FPGA DIFFIO_L27N/PLL_CLKOUTN 27 28 DIFFIO_L20N/CLK1N 0 VCC_IO2 6 BANK 2 5 VCC_IO4 5 VREFB4N0 29 30 31 32 33 34 35 36 VCC_IO1B 8 C31 C32 0.1uF 1uF 4 VCC_IO1A 37 38 39 40 VREFB1N0 8 R27 R38 Header2x20 DNI C C DIFFIO_B1N DIFFIO_B1P DIFFIO_B3N DIFFIO_B3P DIFFIO_B5N DIFFIO_B5P DIFFIO_B7N DIFFIO_B7P U2-4 38 39 DIFFIO_TX_RX_B1N DIFFIO_TX_RX_B1P 41 43 DIFFIO_TX_RX_B3N DIFFIO_TX_RX_B3P 44 45 DIFFIO_TX_RX_B5N DIFFIO_TX_RX_B5P 46 47 DIFFIO_TX_RX_B7N DIFFIO_TX_RX_B7P Bank 3 DIFFIO_TX_RX_B9N DIFFIO_TX_RX_B9P 50 52 DIFFIO_TX_RX_B10N 54 DIFFIO_TX_RX_B12N DIFFIO_TX_RX_B12P 55 56 DIFFIO_TX_RX_B14N DIFFIO_TX_RX_B14P 57 58 DIFFIO_TX_RX_B16N DIFFIO_TX_RX_B16P 59 60 DIFFIO_B9N DIFFIO_B9P DIFFIO_B12N DIFFIO_B12P DIFFIO_B14N DIFFIO_B14P DIFFIO_B16N DIFFIO_B16P DIFFIO_L20N/CLK1N DIFFIO_L20P/CLK1P R31 DNI 100 DIFFIO_L27N/PLL_CLKOUTN R34 DNI 100 DIFFIO_L27P/PLL_CLKOUTP VREFB3N0 48 VREFB3N0 B 10M08SAE144xxx FPGA VCCIO3_1 VCCIO3_2 40 49 VCC_IO 0 VCC_IO3 6 BANK 2 C33 C34 0.1uF 1uF DIFFIO_B7N DIFFIO_B7P R29 DNI 100 DIFFIO_B1N DIFFIO_B1P R30 DNI 100 DIFFIO_B9N DIFFIO_B9P R32 DNI 100 DIFFIO_B3N DIFFIO_B3P R33 DNI 100 DIFFIO_B12N DIFFIO_B12P R35 DNI 100 DIFFIO_B5N DIFFIO_B5P R36 DNI 100 DIFFIO_B14N DIFFIO_B14P R37 DNI 100 B DIFFIO_B16N DIFFIO_B16P R39 DNI 100 VCC_CORE BANK 3 C35 X1 0.1uF 1 EN Vcc 4 2 GND Output 3 OSC_OUT CB3LV-3C-50M0000 A A 50MHz OSC Altera Corporation Title MAX R 10 10M08 Eval Kit Board BANK2, BANK3 BREAKOUT Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 6 of 8 5 4 3 2 1 5 4 3 2 1 J9 Bank 6 D U2-7 D DIFFIO_R14P/CLK2P DIFFIO_R14N/CLK2N 88 89 DIFFIO_RX_R14P/CLK2P DIFFIO_RX_R14N/CLK2N DIFFIO_RX_R27P DIFFIO_RX_R27N 99 101 DIFFIO_R27P DIFFIO_R27N 7 VCC_IO6 1 3 DIFFIO_R14P/CLK2P 5 2 VREFB6N0 4 6 DIFFIO_R16P/CLK3P DIFFIO_R16P/CLK3P DIFFIO_R16N/CLK3N 90 91 DIFFIO_RX_R16P/CLK3P DIFFIO_RX_R16N/CLK3N DIFFIO_RX_R28P DIFFIO_RX_R28N 100 102 DIFFIO_R28P DIFFIO_R28N BANK 6 DIFFIO_R14N/CLK2N 7 DIFFIO_R18P 9 DIFFIO_R18N 11 8 DIFFIO_R16N/CLK3N 10 DIFFIO_R26P/DPCLK3 12 DIFFIO_R26N/DPCLK2 DIFFIO_R18P DIFFIO_R18N 92 93 DIFFIO_RX_R18P DIFFIO_RX_R18N DIFFIO_RX_R33P DIFFIO_RX_R33N 105 106 DIFFIO_R33P DIFFIO_R33N DIFFIO_R27P DIFFIO_R27N DIFFIO_R33P 13 14 15 16 17 18 DIFFIO_R28P DIFFIO_R28N DIFFIO_R26P/DPCLK3 96 DIFFIO_R26N/DPCLK2 98 DIFFIO_RX_R26P/DPCLK3 DIFFIO_RX_R26N/DPCLK2 DIFFIO_R33N 7 VCC_IO7 19 20 21 22 23 24 VREFB7N0 VREFB6N0 97 VREFB6N0 VCCIO6_1 VCCIO6_2 94 103 VCC_IO 0 R40 BANK 7 DIFFIO_T1P DIFFIO_T1N 25 26 27 28 29 30 31 32 33 34 DIFFIO_T10P DIFFIO_T10N DIFFIO_T4N DIFFIO_T6P 10M08SAE144xxx FPGA C36 C37 VCC_IO6 7 8 VCC_IO8 8 VREFB8N0 35 36 37 38 39 40 VCC_IO5 5 VREFB5N0 5 0.1uF 1uF C Header2x20 C DNI DIFFIO_R14P/CLK2P DIFFIO_R14N/CLK2N R41 DNI 100 DIFFIO_T1P DIFFIO_T1N R42 DNI 100 Bank 7 U2-8 B DIFFIO_T1P DIFFIO_T1N DIFFIO_T4N 110 111 DIFFIO_RX_T1P DIFFIO_RX_T1N 113 DIFFIO_RX_T4N DIFFIO_RX_T6P 114 DIFFIO_RX_T10P DIFFIO_RX_T10N 118 119 DIFFIO_T6P DIFFIO_T10P DIFFIO_T10N DIFFIO_R16P/CLK3P DIFFIO_R16N/CLK3N R43 DNI 100 DIFFIO_T10P DIFFIO_T10N R44 DNI 100 DIFFIO_R18P R45 DNI 100 BANK 7 DIFFIO_R18N B VREFB7N0 112 VREFB7N0 10M08SAE144xxx FPGA VCCIO7 117 VCC_IO R47 0 C38 C39 0.1uF 1uF VCC_IO7 7 DIFFIO_R26P/DPCLK3 R46 DNI 100 DIFFIO_R26N/DPCLK2 DIFFIO_R27P DIFFIO_R27N R48 DNI 100 DIFFIO_R28P DIFFIO_R28N R49 DNI 100 A 5 DIFFIO_R33P DIFFIO_R33N R50 DNI 100 BANK 6 A Altera Corporation Title MAX R 10 10M08 Eval Kit Board BANK6, BANK7 BREAKOUT Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 7 of 8 4 3 2 1 5 4 3 2 1 VCC_IO8 D 5 RESET_N U2-9 R51 R52 R53 1K 1K 1K Switch 1 RESET_N BOOT_SEL Switch 2 Switch 3 Switch 4 Switch 5 Bank 8 120 121 122 126 124 127 130 131 DIFFIO_RX_T16P DIFFIO_RX_T16N/DEV_CLRN DIFFIO_RX_T22P DIFFIO_RX_T22N/CRC_ERROR DIFFIO_RX_T18P/DEV_OE DIFFIO_RX_T23N BOOT_SEL DIFFIO_RX_T24P/NSTATUS DIFFIO_RX_T19P DIFFIO_RX_T24N/CONF_DONE DIFFIO_RX_T19N DIFFIO_RX_T26P DIFFIO_RX_T20P DIFFIO_RX_T26N DIFFIO_RX_T20N NCONFIG 132 134 135 136 138 140 141 129 LED1 LED2 LED3 LED4 LED5 NCONFIG 7 VREFB8N0 C 123 VREFB8N0 10M08SAE144xxx FPGA VCCIO8_1 VCCIO8_2 139 128 VCC_IO R63 0 C40 C41 0.1uF 1uF VCC_IO8 7 VCC_IO1B VCC_IO1B R54 10K TCK TDO TMS TDI R55 10K R62 1K R56 10K J10 1 2 3 4 5 6 7 8 9 10 70246-1004 JTAGEN USB Blaster Programming Header (uses JTAG mode) VCC_IO8 LED1 LED2 LED3 LED4 LED5 2 1 VCC_IO8 D R57 R58 R59 R60 R61 1K 1K 1K 1K 1K 1 1 1 1 D1 D2 D3 D4 D5 Red Red Red Red Red 2 2 2 2 C Bank 1B U2-2 JTAGEN TMS TCK TDI TDO 15 DIFFIO_RX_L9P/JTAGEN 16 18 DIFFIO_RX_L11N/TMS DIFFIO_RX_L11P/TCK 19 20 DIFFIO_RX_L12N/TDI DIFFIO_RX_L12P/TDO DIFFIO_RX_L14N DIFFIO_RX_L14P 21 22 DIFFIO_RX_L16N DIFFIO_RX_L16P 24 25 B 6 VREFB1N0 17 VREFB1N0 VCCIO1B 23 10M08SAE144xxx FPGA A 5 4 R64 R65 R66 R67 R68 R69 SW3 1K 1K 1K 1K 1K 1K 1 12 Switch 1 2 11 Switch 2 3 10 Switch 3 4 9 Switch 4 5 8 Switch 5 VCC_IO 6 7 BOOT_SEL B R70 0 C42 C43 0.1uF 1uF VCC_IO1B 6 219-6LPST SW2 1 A1 B1 3 2 A2 B2 4 PTS645SM43SMTR92 LFS NCONFIG CONFIGURATION 3 VCC_IO8 SW1 1 A1 B1 3 2 A2 B2 4 R72 1K RESET_N PTS645SM43SMTR92 LFS A Altera Corporation Title MAX R 10 10M08 Eval Kit Board Size Document Number B 150-0991402-A1 Rev 1.0 Date: Thursday, September 11, 2014 Sheet 8 of 8 2 1

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