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    Rev 1.10 Data Sheet S6D05A0 MOBILE DISPLAY DRIVER IC Property of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved Page 1/389 2008-12-29 TRADEMARK & COPYRIGHT INFORMATION Copyright © 2008-2008 Samsung Electronics Co., Ltd. All Rights Reserved. This is proprietary information of Samsung Electronics Co., Ltd. No part of the information contained in this document maybe reproduced or used without the prior consent of Samsung Electronics Co., Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea 446-711 http://www.samsung.com/Products/Semiconductor/DisplayDriverIC Page 2/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 REVISION HISTORY Mobile Display Driver IC Rev.# Date History - Modified Figure 107. Power Up Pattern Diagram. (Modified Note 1) - Added Note2 of Table169. - Modified Sleep-in and DSTB current of Table 16. 1.10 2008-12-29 - Changed Expression. MCU -> MPU - Figure 101. Note is added. (Deep Standby Mode) - 5.3.8. WRID : ID Definition(D4h) description added about read value. - Modified Figure 107. Power Up Pattern Diagram.(Added Automatic boosting area.) - Modified tMFMC of Table21, Table23. (10ns -> 20ns) - Modified tDCYC of Table 25. (29ns -> 40ns) - Modified Chip thickness of 1.5.2 Bump. (200um -> 300um) - Modified miss writing. (RPKP3 -> RPKP03) - Modified miss writing. (BKP220 -> BPKP20) 1.00 2008-11-27 - Modified Table 10.Interface Pad Configuration (VSS -> VDD3/VSS) - Modified Table 115. Instruction code (F7) (PPKP53 -> RPKP53) - Modified EFh. (W -> R/W) - Modified F3h (‘-‘ ->1) - Modified Table 163. HBP[6:0] (Added “Setting disable” area) - Modified 1.5.3 Bump. ( Dimple height 1.5 -> 2.0 ) - Modified Table 16. DC electrical characteristics (Current Consumption). - Modified Table 18. MPU 80 interface AC characteristics(1/2 transfer) - Modified Table 19. MPU 80 interface AC characteristics(3 transfer) - Modified Table 22. Serial interface AC characteristics, When MFIX_SEL=0(4-wire 8bit) - Modified Table 23. Serial interface AC characteristics, When MFIX_SEL=1(4-wire 8bit) - Modified Figure 108. Setup flow of power - Added comment 5.3.17.4 BLK_VCIR Description. - Added comment 5.3.17.5 VCOM_BLK_OFF Description. 0.10 2008-08-22 - Modified Table 140.WINHADDR0[8:0] - Modified Table 141.WINHADDR1[8:0] - Modified Figure 165.MIE window(A Case of 320RGB) - Modified 5.2.28.3. BL Description - Modified 5.3.3.2. BL_MODE_IN_SLP Description - Modified 5.3.13. WRPWD: DSTB and MTP Control Test Key (F0h)'s TEST7-0 description - Modified Table 163.HBP[6:0] - Modified Table 186.NBLK_CON[1:0] - Modified Standby mode to Sleep mode Page 3/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Rev.# Date 0.00 2008-06-24 . Initial Release History Mobile Display Driver IC Page 4/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 LIST OF CONTENTS Mobile Display Driver IC 1 Overview................................................................................................... 20 1.1. Introduction........................................................................................................................................... 20 1.2. Product options .................................................................................................................................... 20 1.3. Features................................................................................................................................................. 21 1.4. Block Diagram ...................................................................................................................................... 23 1.4.1. Module Level .................................................................................................................................... 23 1.4.2. Functional Block Diagram of the IC ................................................................................................. 24 1.5. Pad Information .................................................................................................................................... 25 1.5.1. Configuration of Signal Pads ........................................................................................................... 25 1.5.2. Bump ................................................................................................................................................ 26 1.5.3. Align Key .......................................................................................................................................... 28 1.6. Description of Signal Pads.................................................................................................................. 29 1.6.1. Pads for power supplies................................................................................................................... 29 1.6.2. Signal Pads for Logic Interface ........................................................................................................ 31 1.7. Interface Pad Configuration ................................................................................................................ 35 2 Electrical Specifications.......................................................................... 41 2.1. Absolute Maximum Ratings ................................................................................................................ 41 2.2. DC Electrical Characteristics .............................................................................................................. 42 2.2.1. BASIC Characteristics...................................................................................................................... 42 2.3. AC Characteristics ............................................................................................................................... 45 2.3.1. Parallel Interface Characteristics (80-series MPU) .......................................................................... 45 2.3.2. Serial Interface Characteristics, When MFIX_SEL=0 (3-wire/ 9-bit serial interface) ....................... 48 2.3.3. Serial Interface Characteristics, When MFIX_SEL=1 (3-wire/ 9-bit serial interface) ....................... 49 2.3.4. Serial Interface Characteristics, When MFIX_SEL=0 (4-wire/ 8-bit serial interface) ....................... 50 2.3.5. Serial Interface Characteristics, When MFIX_SEL=1 (4-wire/ 8-bit serial interface) ....................... 52 2.3.6. RGB Interface Characteristics ......................................................................................................... 54 2.3.7. RESX Signal .................................................................................................................................... 56 2.3.8. Measurement Conditions ................................................................................................................. 58 2.4. MDDI DC/AC Characteristics............................................................................................................... 61 3 Interface.................................................................................................... 64 3.1. MPU Interface........................................................................................................................................ 64 3.1.1. Interface Type Selection .................................................................................................................. 64 3.1.2. Pad Description of MPU Interface.................................................................................................... 65 3.1.3. Sequence of MPU Interface............................................................................................................. 67 3.1.4. Sequence of 4-wire/8-bit Serial Interface......................................................................................... 70 3.1.5. Sequence of 3-wire/9-bit Serial Interface......................................................................................... 73 3.1.6. Description of MPU Interface ........................................................................................................... 76 3.2. Display Module Data Color Coding .................................................................................................... 81 3.2.1. Display Data Format for Write.......................................................................................................... 81 3.2.2. Display Data Format for Read ......................................................................................................... 83 3.2.3. 16M Color Mode............................................................................................................................... 88 3.2.4. 262k Color Mode.............................................................................................................................. 94 3.2.5. 65k Color Mode.............................................................................................................................. 101 3.3. RGB Interface...................................................................................................................................... 105 3.3.1. Motion Picture Display ................................................................................................................... 105 3.3.2. 24-bit RGB Interface ...................................................................................................................... 106 3.3.3. 18-bit RGB Interface ...................................................................................................................... 107 Page 5/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 3.3.4. 16-bit RGB Interface ...................................................................................................................... 108 3.3.5. 8-bit RGB Interface ........................................................................................................................ 109 3.3.6. 6-bit RGB Interface ........................................................................................................................ 111 3.4. MDDI .................................................................................................................................................... 113 3.4.1. Introduction to MDDI ...................................................................................................................... 113 3.4.2. Data-STB Encoding ....................................................................................................................... 114 3.4.3. MDDI Data & STB .......................................................................................................................... 115 3.4.4. MDDI Packet .................................................................................................................................. 116 3.4.5. Panel Control ................................................................................................................................. 119 3.4.6. Tearing-less Display....................................................................................................................... 121 3.4.7. Hibernation / Wake-up ................................................................................................................... 123 3.4.8. MDDI Link Wake-up Procedure ..................................................................................................... 124 3.4.9. Client-Initiated Link Wake-up ......................................................................................................... 127 3.4.10. MDDI Operation ........................................................................................................................... 129 4 Functional Description .......................................................................... 132 4.1. Power................................................................................................................................................... 132 4.1.1. Power ON / OFF Sequence ........................................................................................................... 132 4.1.2. Abrupt Power Off............................................................................................................................ 135 4.1.3. Power Levels (APON=1) ................................................................................................................ 136 4.1.4. Power Flow Chart for Different Power Modes (APON=1).............................................................. 137 4.1.5. Power Supply ................................................................................................................................. 138 4.1.6. Pattern Diagrams for Voltage Setting ............................................................................................ 139 4.1.7. Set up Flow of Power ..................................................................................................................... 140 4.1.8. Deep-Standby Sequence ............................................................................................................... 141 4.1.9. Discharge Status of Power Block................................................................................................... 142 4.1.10. Voltage Regulation Function ........................................................................................................ 143 4.2. Source ................................................................................................................................................. 144 4.2.1. Source Driver ................................................................................................................................. 144 4.2.2. Gamma Adjustment Function ........................................................................................................ 144 4.2.3. Gamma Curve................................................................................................................................ 145 4.2.4. Structure of Grayscale Amplifier .................................................................................................... 146 4.2.5. Gamma Adjustment Register ......................................................................................................... 149 4.2.6. Resistor Ladder Network / Selector ............................................................................................... 152 4.2.7. Grayscale Levels............................................................................................................................ 160 4.3. GATE DRIVER ..................................................................................................................................... 190 4.3.1. Gate Driver ..................................................................................................................................... 190 4.4. Oscillator- System Clock Generator................................................................................................. 191 4.4.1. Oscillator Circuit ............................................................................................................................. 191 4.4.2. Frame Frequency Adjusting Function ............................................................................................ 192 4.5. Display Data RAM............................................................................................................................... 193 4.5.1. Address Counter ............................................................................................................................ 193 4.5.2. Memory to Display Address Mapping ............................................................................................ 195 4.5.3. Normal Display On or Partial Mode On.......................................................................................... 196 4.5.4. Command Definition is Independent of the IC Mount Position ...................................................... 197 4.6. Reset .................................................................................................................................................... 202 4.6.1. Registers ........................................................................................................................................ 202 4.6.2. Moduls Input/Output/Bi-direction (I/O) Pads .................................................................................. 205 4.7. Sleep-Out Command and Self-Diagnostic Functions of the Display Module .............................. 206 4.7.1. Register Loading Detection............................................................................................................ 206 4.7.2. Functionality Detection................................................................................................................... 207 4.8. NVM Memory Control ......................................................................................................................... 208 4.8.1. MTP Control ................................................................................................................................... 208 4.9. 8-color Display Mode ......................................................................................................................... 213 4.10. Instruction Setup Flow..................................................................................................................... 214 Page 6/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 4.10.1. Power OFF Sequence.................................................................................................................. 214 4.11. Tearing Effect Output Line .............................................................................................................. 215 4.11.1. Tearing Effect Line Modes ........................................................................................................... 215 4.11.2. Tearing Effect Line Timings ......................................................................................................... 216 4.12. MIE Function ..................................................................................................................................... 219 5 COMMAND ............................................................................................. 221 5.1. Command List..................................................................................................................................... 221 5.1.1. Level 1: Function Command .......................................................................................................... 221 5.1.2. Level 2: Function Command .......................................................................................................... 225 5.2. Description of Level1 Command ...................................................................................................... 237 5.2.1. SWRESET: Software Reset (01h) ................................................................................................. 237 5.2.2. RDDIDIF: Read Display ID (04h) ................................................................................................... 239 5.2.3. RDDST: Read Display Status (09h)............................................................................................... 241 5.2.4. RDDPM: Read Display Power Mode (0Ah) ................................................................................... 243 5.2.5. RDDMADCTL: Read Display MADCTL (0Bh) ............................................................................... 245 5.2.6. RDDCOLMOD: Read Display Pixel Format (0Ch)......................................................................... 247 5.2.7. RDDSM: Read Display Signal Mode (0Eh).................................................................................... 249 5.2.8. RDDSDR: Read Display Self-Diagnostic Result (0Fh) .................................................................. 251 5.2.9. SLPIN: Sleep In (10h) .................................................................................................................... 253 5.2.10. SLPOUT: Sleep Out (11h) ........................................................................................................... 255 5.2.11. PTLON: Partial Display Mode On (12h)....................................................................................... 257 5.2.12. NORON: Normal Display Mode On (13h) .................................................................................... 258 5.2.13. DISPOFF: Display Off (28h) ........................................................................................................ 259 5.2.14. DISPON: Display On (29h) .......................................................................................................... 261 5.2.15. CASET: Column Address Set (2Ah) ............................................................................................ 263 5.2.16. PASET: Page Address Set (2Bh) ................................................................................................ 265 5.2.17. RAMWR: Memory Write (2Ch)..................................................................................................... 267 5.2.18. RAMRD: Memory Read (2Eh) ..................................................................................................... 269 5.2.19. PTLAR: Partial Area (30h) ........................................................................................................... 271 5.2.20. TEOFF: Tearing Effect Line OFF (34h) ....................................................................................... 273 5.2.21. TEON: Tearing Effect Line ON (35h) ........................................................................................... 274 5.2.22. MADCTL: Memory Data Access Control (36h) ............................................................................ 276 5.2.23. IDMOFF: Idle Mode Off (38h) ...................................................................................................... 278 5.2.24. IDMON: Idle Mode On (39h) ........................................................................................................ 279 5.2.25. COLMOD: Interface Pixel Format (3Ah) ...................................................................................... 281 5.2.26. WRDISBV: Write Manual Brightness (51h).................................................................................. 283 5.2.27. RDDISBV : Read Display Brightness (52h) ................................................................................. 285 5.2.28. WRCTRLD: Write BL Control (53h) ............................................................................................. 286 5.2.29. Read BL Control (54h) ................................................................................................................. 288 5.2.30. WRCABC : Write MIE Mode (55h) ............................................................................................... 289 5.2.31. Read MIE Mode (56h).................................................................................................................. 290 5.2.32. WRCABCMB: Write Minimum Brightness (5Eh).......................................................................... 291 5.2.33. Read Minimum Brightness (5Fh) ................................................................................................. 293 5.2.34. MIECTRL1: Write MIE Control 1 (CAh) ....................................................................................... 294 5.2.35. BCMODE: Write BL Control Mode (CBh) .................................................................................... 298 5.2.36. RDID1: Read ID1 Value (DAh) .................................................................................................... 299 5.2.37. RDID2 : Read ID2 Value (DBh) ................................................................................................... 300 5.2.38. RDID3 : Read ID3 Value (DCh) ................................................................................................... 301 5.3. Description of Level2 Command ...................................................................................................... 302 5.3.1. DSTB: Deep Stand by mode Control (B0h) ................................................................................... 302 5.3.2. MIECTL2: Write MIE Control 2 (CCh)............................................................................................ 302 5.3.3. MIE Control3 (CDh) : Write BL Control .......................................................................................... 307 5.3.4. MTPCTL: MTP Control Command (D0h)....................................................................................... 313 5.3.5. WRVCMOC: Set VCOM Offset Control (D1h) ............................................................................... 315 5.3.6. WRVMLOC: Set VCOML Offset Control (D2h).............................................................................. 317 5.3.7. WRGVDOC: Set GVDD Offset Control (D3h)................................................................................ 318 5.3.8. WRID: ID Definition (D4h) .............................................................................................................. 319 Page 7/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.3.9. RDOFFSETC: Read Offset Control (D5h) ..................................................................................... 320 5.3.10. MDDICTL1 : MDDI Control 1 (E0h) ............................................................................................. 321 5.3.11. MDDILIK: MDDI Link Wake-up Start Position (E1h) .................................................................... 322 5.3.12. DCON: Manual Display Control Register (EFh)........................................................................... 323 5.3.13. WRPWD: DSTB and MTP Control Test Key (F0h) ...................................................................... 325 5.3.14. DISCTL: Display Control Register (F2h)...................................................................................... 326 5.3.15. PWRCTL: Power Control Register (F3h) ..................................................................................... 333 5.3.16. VCMCTL : VCOM Control Register (F4h).................................................................................... 341 5.3.17. SRCCTL: Source Output Control Register (F5h)......................................................................... 348 5.3.18. IFCTL : Interface Control Register (F6h) ..................................................................................... 356 5.3.19. RGAMCTL: Positive Gamma Control Register for Red (F7h) ..................................................... 360 5.3.20. RNGAMCTL: Negative Gamma Control Register for Red (F8h) ................................................. 362 5.3.21. GGAMCTL: Positive Gamma Control Register for Green (F9h).................................................. 364 5.3.22. GNGAMCTL: Negative Gamma Control Register for Green (FAh) ............................................. 366 5.3.23. BGAMCTL : Positive Gamma Control Register for Blue (FBh).................................................... 368 5.3.24. BNGAMCTL: Negative Gamma Control Register for Blue(FCh) ................................................. 370 5.3.25. GATECTL: Gate Control Register (FDh) ..................................................................................... 372 6 Appendix ................................................................................................ 376 6.1. Application Circuit ............................................................................................................................. 376 6.2. External Component .......................................................................................................................... 377 6.3. PAD Center Coordinates ................................................................................................................... 378 6.4. Display Module Default Position....................................................................................................... 389 Page 8/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 LIST OF FIGURES Mobile Display Driver IC Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. The interface signal flow of a mobile display panel module................................................ 23 S6D05A0 block diagram...................................................................................................... 24 S6D05A0 pad configuration ................................................................................................ 25 Pad arrangement layout ...................................................................................................... 26 Chip outline.......................................................................................................................... 27 COG align key configuration and coordinate ...................................................................... 28 COG align key arrangement layout ..................................................................................... 28 LCD source driver delay...................................................................................................... 44 MPU 80 interface AC characteristics .................................................................................. 45 3- wire 9bit Serial interface characteristics, When MFIX_SEL=0 ....................................... 48 3- wire 9bit Serial interface characteristics, When MFIX_SEL=1 ....................................... 49 4 wire 8bit Serial interface characteristics, When MFIX_SEL=0......................................... 50 4 wire 8bit Serial interface characteristics, When MFIX_SEL=1......................................... 52 RGB interface characteristics.............................................................................................. 54 Reset input timing................................................................................................................ 56 RESX pulse width................................................................................................................ 57 Measurement condition set-up of MPU interface at a module level.................................... 58 Minimum value measurement of MPU interface ................................................................. 58 Maximum value measurement of MPU interface ................................................................ 59 Measurement condition set-up of SPI at a module level..................................................... 59 Minimum value measurement of SPI .................................................................................. 60 Maximum value measurement of SPI ................................................................................. 60 MDDI receiver, driver electrical diagram ............................................................................. 61 Host enable/disable time and client enable/disable time diagram ...................................... 62 80-series WRX protocol ...................................................................................................... 68 80-series Parallel bus protocol, write to register or display RAM........................................ 68 80-series RDX protocol ....................................................................................................... 69 80-series Parallel bus protocol, read from register or display RAM.................................... 69 4-wire/8-bit Data serial interface write mode, When MFIX_SEL=0..................................... 70 4-wire/8-bit Data serial interface write mode, When MFIX_SEL=1..................................... 71 4-wire/8-bit Data serial interface write mode, When MFIX_SEL=0 (CSX=”H” during transmission) ....................................................................................................................... 71 4-wire/8-bit Data serial interface write mode, When MFIX_SEL=1 (CSX=”H” during transmission) ....................................................................................................................... 71 4-wire/8-bit Data serial interface read 1-byte mode, When MFIX_SEL=0 .......................... 72 4-wire/8-bit Data serial interface read 1-byte mode, When MFIX_SEL=1 .......................... 72 4-wire/8-bit Data serial interface read multi-byte mode, When MFIX_SEL=0 .................... 72 4-wire/8-bit Data serial interface read multi-byte mode, When MFIX_SEL=1 .................... 72 3-wire/9-bit Data serial interface write mode, When MFIX_SEL=0..................................... 73 3-wire/9-bit Data serial interface write mode When, MFIX_SEL=1..................................... 74 3-wire/9-bit Data serial interface write mode When MFIX_SEL=0 (CSX=”H” during transmission ) ...................................................................................................................... 74 3-wire/9-bit Data serial interface write mode, When MFIX_SEL=1 (CSX=”H” during transmission) ....................................................................................................................... 74 3-wire/9-bit Data serial interface read 1-byte mode, When MFIX_SEL=0 .......................... 75 3-wire/9-bit Data serial interface read 1-byte mode, When MFIX_SEL=1 .......................... 75 3-wire/9-bit Data serial interface read multi-byte mode, When MFIX_SEL=0 .................... 75 3-wire/9-bit Data serial interface read multi-byte mode, When MFIX_SEL=1 .................... 75 Parallel interface pause....................................................................................................... 77 Serial interface pause, When MFIX_SEL=0 ....................................................................... 77 Serial interface pause, When MFIX_SEL=1 ....................................................................... 77 Serial bus protocol, write mode – interrupted by RESX, When MFIX_SEL=0 (3-wire 9bit data serial I/F) ...................................................................................................................... 78 Serial bus protocol, write mode – interrupted by RESX, When MFIX_SEL=1 (3-wire 9bit data serial I/F) ...................................................................................................................... 78 Serial bus protocol, write mode – interrupted by CSX, When MFIX_SEL=0 (3-wire 9bit data serial I/F) .............................................................................................................................. 79 Serial bus protocol, write mode – interrupted by CSX, When MFIX_SEL=1 (3-wire 9bit data serial I/F) .............................................................................................................................. 79 Write interrupt recovery (serial interface) ............................................................................ 79 Write interrupt recovery (both serial and parallel interface) ................................................ 80 Image data writing method 1 ............................................................................................... 80 Image data writing method 2 ............................................................................................... 80 Data expand method (65K color mode) .............................................................................. 81 Data expand method (262K color mode) ............................................................................ 82 Case of 16M color mode ..................................................................................................... 83 Case of 262K color mode.................................................................................................... 83 Page 9/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Case of 65K color mode...................................................................................................... 83 Display data read (24bit Interface type) .............................................................................. 84 Display data read (18bit Interface: MDT=00) ...................................................................... 84 Display data read (18bit Interface: MDT=01) ...................................................................... 85 Display data read (16bit Interface : MDT=00) ..................................................................... 85 Display data read (16bit Interface : MDT=01) ..................................................................... 86 Display data read (9bit Interface: MDT=00) ........................................................................ 86 Display data read (8bit Interface type) ................................................................................ 87 RGB interface .................................................................................................................... 105 Bit assignment of GRAM data on 24bit RGB interface ..................................................... 106 Timing diagram of 24bit RGB interface ............................................................................. 106 Bit assignment of GRAM data on 18bit RGB interface(IPM=”100”).................................. 107 Timing diagram of 18bit RGB interface ............................................................................. 107 Bit assignment of GRAM data on 16bit RGB interface(IPM=”100”).................................. 108 Timing diagram of 16bit RGB interface ............................................................................. 108 Bit assignment of GRAM data on 8bit RGB interface ....................................................... 109 Timing diagram of 8bit RGB interface ............................................................................... 109 Transfer synchronization function in 8-bit RGB interface mode........................................ 110 Bit assignment of GRAM data on 6bit RGB interface(IPM=”100”) .................................... 111 Timing diagram of 6bit RGB interface ............................................................................... 111 Transfer synchronization function in 6-bit RGB interface mode........................................ 112 Physical connection of MDDI host and client .................................................................... 113 Data-STB encoding ........................................................................................................... 114 Data / STB generation & recovery circuit .......................................................................... 114 Differential connection between host and client................................................................ 115 MDDI packet structure....................................................................................................... 116 Sub-Frame header packet structure ................................................................................. 117 Register access packet structure ...................................................................................... 117 Video stream packet structure........................................................................................... 117 Filler packet structure ........................................................................................................ 118 Link shutdown packet structure......................................................................................... 118 Writing video data to memory sequence........................................................................... 119 Writing register sequence.................................................................................................. 119 Reading video data from memory sequence .................................................................... 120 Reading register sequence ............................................................................................... 120 Tearing-less display: data write speed is faster than display............................................ 121 Tearing-less display: display speed is faster than data write............................................ 122 MDDI transceiver / receiver state in hibernation ............................................................... 123 Host-Initiated link wake-up sequence ............................................................................... 124 Client-Initiated link wake-up sequence.............................................................................. 125 VSYNC based link wake-up procedure............................................................................. 127 Operating state in MDDI mode.......................................................................................... 130 RESX line is held high or unstable by host at power on ................................................... 133 RESX line is held low by host at power on........................................................................ 134 Status of Driver IC at abrupt power-off.............................................................................. 135 Power-on flowchart for various power modes ................................................................... 137 Configuration of the internal power-supply circuit ............................................................. 138 Power-Up pattern diagram ................................................................................................ 139 Setup flow of power ........................................................................................................... 140 Deep-Standby Sequence .................................................................................................. 141 Voltage regulation function................................................................................................ 143 Block diagram of gamma adjustment function .................................................................. 144 Gamma y = x 2.2 ............................................................................................................ 145 Structure of gray scale amplifier........................................................................................ 146 Structure of resistor ladder network 1. .............................................................................. 147 Structure of resistor ladder network 2. .............................................................................. 148 The operation of adjusting register.................................................................................... 149 Relationship between RAM data and output voltage ........................................................ 188 Relationship between source output and VCOM .............................................................. 189 Application diagram for oscillator circuitry......................................................................... 191 Formula for the frame frequency ....................................................................................... 192 Frame data write direction according to the MADCTL parameters (D5, D6 and D7) ....... 194 Memory to display address mapping ................................................................................ 195 Example for normal display On (D6 = D7 = D4 = ‘0’)........................................................ 196 Partial display on: SR [15:0] = 04h, ER [15:0] = 1DCh, MADCTL .................................... 196 Model of LCD module for the S6D05A0............................................................................ 197 An example of MADCTL(00h) ........................................................................................... 197 Cases of panel position mounted IC ................................................................................. 198 0-Address position and RAM access scan direction(D5=0).............................................. 199 0-Address position and RAM access scan direction(D5=1).............................................. 200 LCD read scan direction and common scan direction ...................................................... 201 Partial area and scan direction.......................................................................................... 201 Page 10/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. Figure 144. Figure 145. Figure 146. Figure 147. Figure 148. Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Figure 164. Figure 165. Figure 166. Figure 167. Figure 168. Figure 169. Figure 170. Figure 171. Figure 172. Figure 173. Figure 174. Figure 175. Figure 176. Figure 177. Figure 178. Figure 179. Figure 180. Figure 181. Figure 182. Figure 183. Figure 184. Figure 185. Figure 186. Figure 187. Figure 188. Flowchart of register loading detection ............................................................................. 206 Flowchart of functionality detection ................................................................................... 207 Flow of MTP load / read .................................................................................................... 208 MTP initialization, erase and program (internal mode using VCI)..................................... 209 MTP initialization, erase and program (internal mode using VCI1)................................... 210 MTP initialization, erase and program (external mode) .................................................... 211 Timing of MTP program..................................................................................................... 212 Timing of MTP load ........................................................................................................... 212 8-color display control. ...................................................................................................... 213 Power OFF sequence ....................................................................................................... 214 Tearing effect output signal consists of V-blanking information only ................................ 215 Tearing effect output signal consists of V-blanking and H-blanking information .............. 215 Tearing effect output signal ............................................................................................... 215 Tearing effect output signal timing .................................................................................... 216 Rise and fall time of TE signal........................................................................................... 216 Method 1 to avoid tearing effect........................................................................................ 217 Panel image refreshment of method 1 .............................................................................. 217 Method 2 to avoid tearing effect........................................................................................ 218 Panel image refreshment of method 2 .............................................................................. 218 Flowchart of MIE function.................................................................................................. 219 Manual brightness ............................................................................................................. 283 Calculation formula............................................................................................................ 283 Example of manual brightness .......................................................................................... 284 Manual dimming function .................................................................................................. 286 Example of minimum brightness ....................................................................................... 291 Power reduction rate ......................................................................................................... 294 Example of RRC................................................................................................................ 294 Image enhancement rate .................................................................................................. 295 Example of IERC ............................................................................................................... 295 Example of MIE on / off dimming transition control........................................................... 296 Saturation enhancement rate ............................................................................................ 297 Example of SERC ............................................................................................................. 297 Example of MIE transition control...................................................................................... 304 MIE window(A Case of 320RGB) ...................................................................................... 306 Transition time of manual dimming function...................................................................... 308 Example of dimming function (DT[2:0] = 000)................................................................... 308 Calculation formula of BC frequency................................................................................. 309 Example of BC frequency selection .................................................................................. 310 Gate clock generation order selection using GS and SM (NL=6’b111011, SCN=5’b00000) . -----------------------------------------------------------------------------------------------------------330 Gate clock generation order selection using GS and SM (NL=6’b100111, SCN=5’b00000) . --------------------------------------------------------------------------------------------------------------330 Set delay from gate output to source output and VCIR signal .......................................... 346 Source/Vcom operating example by releated registers .................................................... 347 Gamma & Source driver offset cancellation method......................................................... 353 4-frame offset cancellation mode ...................................................................................... 354 2-frame offset cancellation mode ...................................................................................... 354 Line & 4-frame offset cancellation mode........................................................................... 354 Line & 2-frame offset cancellation mode........................................................................... 354 Halt offset cancellation mode ............................................................................................ 354 8 Frame offset cancellation mode ..................................................................................... 355 2 Line and 4 Frame offset cancellation mode ................................................................... 355 Data expansion by IMP (example of red color) ................................................................. 356 VSYNC interface (example: 24bit interface) ..................................................................... 357 Motion picture data transfer via VSYNC interface............................................................. 357 Little Endian (When MPU 65K 8bit I/F) ............................................................................. 358 Gate Scan Position Control ............................................................................................... 374 Application circuit .............................................................................................................. 376 Display module default position......................................................................................... 389 Page 11/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 LIST OF TABLES Mobile Display Driver IC Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. List of S6D05A0 options ......................................................................................................... 20 Pads for power supplies (continued) .................................................................................... 30 Signal pads for logic interface ............................................................................................... 31 Signal pads for logic interface(continued) ........................................................................... 32 Signal pads for logic interface(continued) ........................................................................... 33 Pads for source/gate driver output signal ............................................................................ 33 MIE pins .................................................................................................................................... 33 Miscellaneous signal pads ..................................................................................................... 34 Test signal pads....................................................................................................................... 34 Interface pad configuration1 (MPU)....................................................................................... 35 Interface pad configuration2 (SPI 3wire/RGB, When Use SDA for instruction) ................ 36 Interface pad configuration3 (SPI 4wire/RGB, When Use SDA for instruction) ................ 37 Interface pad configuration4 (SPI 3wire/RGB, When Use DB[1:0] for instruction)........... 38 Interface pad configuration5 (SPI 4wire/RGB, When Use DB[1:0] for instruction)........... 39 Absolute maximum ratings .................................................................................................... 41 DC electrical characteristics (Ta = 25°C). ............................................................................. 42 DC characteristics for LCD driver outputs (TYP: VCI=VDD3=3.0V, Ta=25°C) ................... 43 MPU 80 interface AC characteristics(1/2 transfer) ............................................................... 46 MPU 80 interface AC characteristics(3 transfer) .................................................................. 47 Serial interface AC characteristics, When MFIX_SEL=0 (3-wire 9bit) ................................ 48 Serial interface AC characteristics, When MFIX_SEL=1 (3-wire 9bit) ................................ 49 Serial interface AC characteristics, When MFIX_SEL=0(4-wire 8bit) ................................. 50 Serial interface AC characteristics, When MFIX_SEL=1 (4-wire 8bit) ................................ 52 RGB interface AC characteristics (1 transfer) ...................................................................... 54 RGB interface AC characteristics (3 transfer) ...................................................................... 55 Reset input timing When APON=1......................................................................................... 56 Reset input timing When APON=0......................................................................................... 56 RESX pulse............................................................................................................................... 56 Data/Strobe Rx DC characteristics ........................................................................................ 61 Driver electrical DC characteristics ....................................................................................... 61 Receiver AC Characteristics .................................................................................................. 62 Interface type selection........................................................................................................... 64 Interface signal description in case of MPU I/F.................................................................... 65 Interface Signals in case of 4-wire/8-bit Serial Interface. .................................................... 66 Interface Signals in case of 3-wire/9-bit Serial Interface. .................................................... 66 The function of 80-series parallel interface .......................................................................... 67 Bidirectional data bus description of MPU 24bit.................................................................. 76 Page 12/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Display data format for write .................................................................................................. 81 24-bit Parallel interface for 888 1/1 formats (MDT = 00)....................................................... 88 18-bit Parallel interface for 888 2/3 formats (MDT = 00)....................................................... 89 18-bit Parallel interface for 888 1/2 formats (MDT = 01)....................................................... 90 16-bit Parallel interface for 888 2/3 formats (MDT = 00)....................................................... 91 16-bit Parallel interface for 888 1/2 formats (MDT = 01)....................................................... 92 9-bit Parallel interface for 888 1/3 formats (MDT = 00)......................................................... 93 8-bit Parallel interface for 888 1/3 formats (MDT = 00)......................................................... 93 24-bit Parallel interface for 666 1/1 formats (MDT = 00)....................................................... 94 18-bit Parallel interface for 666 1/1 formats (MDT = 00)....................................................... 95 16-bit Parallel Interface for 666 2/3 formats (MDT = 00)....................................................... 96 16-bit Parallel interface for 666 1/2 formats ( MDT = 01 )..................................................... 97 16-bit Parallel interface for 666 1/2 formats ( MDT = 10 )..................................................... 98 16-bit Parallel interface for 666 1/2 formats ( MDT = 11)...................................................... 99 9-bit Parallel interface for 666 1/2 formats (MDT = 00)....................................................... 100 9-bit Parallel interface for 666 1/3 formats (MDT = 01)....................................................... 100 8-bit Parallel interface for 666 1/3 formats (MDT = 00)....................................................... 100 24-bit Parallel interface for 565 1/1 formats (MDT = 00)..................................................... 101 18-bit Parallel interface for 565 1/1 formats (MDT = 00)..................................................... 102 16-bit Parallel interface for 565 1/1 formats (MDT = 00)..................................................... 103 9-bit Parallel interface for 565 1/2 formats (MDT = 00)....................................................... 104 8-bit Parallel interface for 565 1/2 formats (MDT = 00)....................................................... 104 RGB interface mode selection ............................................................................................. 105 COLMOD setting in MDDI ..................................................................................................... 119 MDDI Opreration State .......................................................................................................... 129 Discharge Status of Power Block ........................................................................................ 142 Description of gamma adjustment register ........................................................................ 150 Amplitude adjustment ........................................................................................................... 153 Amplitude adjustment(continued) ....................................................................................... 154 Reference adjustment ........................................................................................................... 155 Reference adjustment(continued) ....................................................................................... 156 Relationship between micro-adjustment register and selected voltage ......................... 157 Relationship between micro-adjustment register and selected voltage(continued)...... 158 Relationship between micro-adjustment register and selected voltage(continued)...... 159 Formulas for calculating gamma adjusting voltage (positive polarity) 1 ........................ 160 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 161 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 162 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 163 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 164 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 165 Page 13/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 166 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 167 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 168 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 169 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 170 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 171 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 172 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 173 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 174 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 175 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 176 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 177 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 178 Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) ... 179 Formulas for calculating gamma adjusting voltage (positive polarity) 2 ........................ 180 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 181 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 182 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 183 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 184 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 185 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 186 Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) ... 187 Control for column and page counter ................................................................................. 193 The default value of the register set .................................................................................... 202 The default value of the register set 1(level II) ................................................................... 204 Reset states of output pads ................................................................................................. 205 Reset states of input pads.................................................................................................... 205 AC characteristics of tearing effect signal (Idle mode off) ............................................... 216 Instruction code..................................................................................................................... 221 Instruction code - (0F ~ 2E) .................................................................................................. 222 Instruction code – (30 ~ 56) .................................................................................................. 223 Instruction code - (5E ~ DC) ................................................................................................. 224 Instruction code – (B0 ~ CD) ................................................................................................ 225 Instruction code – (D0 ~ D5) ................................................................................................. 226 Instruction code – (E0 ~ F2).................................................................................................. 227 Instruction code – (F3 ~ F4).................................................................................................. 228 Instruction code – (F5 ~ F6).................................................................................................. 229 Instruction code – (F7) .......................................................................................................... 230 Instruction code – (F8) .......................................................................................................... 231 Instruction code – (F9) .......................................................................................................... 232 Page 14/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Instruction code – (FA) ......................................................................................................... 233 Instruction code – (FB) ......................................................................................................... 234 Instruction code – (FC) ......................................................................................................... 235 Instruction code – (FD) ......................................................................................................... 236 MANBR [7:0]........................................................................................................................... 283 Example of manual brightness ............................................................................................ 284 BROUT[7:0] ............................................................................................................................ 285 BCTRL..................................................................................................................................... 286 DD ........................................................................................................................................ 286 BL ......................................................................................................................................... 287 MIE_MODE[1:0] ...................................................................................................................... 289 Example of minimum brightness ( Minimum brightness = 20%)...................................... 291 BRMIN[7:0] ............................................................................................................................. 292 RRC[7:0] ................................................................................................................................. 295 IERC[7:0]................................................................................................................................. 296 ONOFF_DIMM_EN.................................................................................................................. 296 SERC[4:0] ............................................................................................................................... 297 BC_MODE[1:0] ....................................................................................................................... 298 CAT[1:0] .................................................................................................................................. 303 CST[1:0] .................................................................................................................................. 303 WINVADDR0[8:0] ................................................................................................................... 304 WINVADDR1[8:0] ................................................................................................................... 305 WINHADDR0[8:0] ................................................................................................................... 305 WINHADDR1[8:0] ................................................................................................................... 306 BL_MODE_IN_SLP ................................................................................................................ 307 State of BC ............................................................................................................................. 307 DT[2:0] .................................................................................................................................... 308 BL_DRV_EN_PAD.................................................................................................................. 309 BL_DIMM_STEP[1:0] ............................................................................................................. 309 BC frequency ......................................................................................................................... 311 Example of BC frequency selection .................................................................................... 312 ID_SEL .................................................................................................................................... 313 MTP_SEL ................................................................................................................................ 313 MTP_MODE ............................................................................................................................ 313 MTP_EX .................................................................................................................................. 314 VCMOC[5:0]............................................................................................................................ 315 VMLOC[4:0] ............................................................................................................................ 317 GVDOC[4:1] ............................................................................................................................ 318 GON......................................................................................................................................... 323 D_CON[1:0]............................................................................................................................. 323 Page 15/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Display Control and Chip Operation, When APON is High, .............................................. 324 NRTN[4:0]/IPRTN[4:0]............................................................................................................ 326 IPINV/IINV/PINV/NINV ............................................................................................................ 328 NVBP[7:0]/IPVBP[7:0]............................................................................................................ 328 NVFP[7:0]/IPVFP[7:0] ............................................................................................................ 329 HBP[6:0].................................................................................................................................. 329 REV ...................................................................................................................................... 330 NCRTN[4:0] / IPCRTN[4:0] .................................................................................................... 331 NDC3[1:0]/ IPDC3[1:0] ........................................................................................................... 334 NDC2[1:0]/ IPDC2[1:0] ........................................................................................................... 335 NDC1[1:0]/ IPDC1[1:0] ........................................................................................................... 335 VC[3:0] .................................................................................................................................... 336 NBT[2:0]/IPBT[2:0] ................................................................................................................. 337 NGVD[6:0]............................................................................................................................... 337 IPGVD[6:0] .............................................................................................................................. 338 NVCM[6:0] (Vref=2.0V, unit =V) ............................................................................................ 341 IPVCM[6:0] (Vref=2.0V, unit =V)............................................................................................ 342 NVML[6:0] (Vref=2.0V, unit =V) .......................................................................................... 343 IPVML[6:0] (Vref=2.0V, unit =V) ............................................................................................ 344 VCIRA[2:0]/ VCIR[2:0]............................................................................................................ 346 SEL_360.................................................................................................................................. 348 GS_EN..................................................................................................................................... 348 IPSDT[2:0]/NSDT[2:0] ............................................................................................................ 349 SAP[3:0].................................................................................................................................. 350 NBLK_VCIR[1:0]/ IPBLK_VCIR[1:0] ..................................................................................... 351 NDISP_CON[1:0] .................................................................................................................... 351 IPDISP_CON [1:0] .................................................................................................................. 351 VCOM_BLK_OFF ................................................................................................................... 352 NBLK_CON[1:0] ..................................................................................................................... 352 IPBLK_CON[1:0] .................................................................................................................... 352 GOCM[2:0] .............................................................................................................................. 353 OCM[1:0]................................................................................................................................. 353 IPM[2:0]................................................................................................................................... 356 Relationship between EPL, ENABLE and RAM access ..................................................... 358 ENDIAN ................................................................................................................................... 358 RIM ........................................................................................................................................ 359 RGB_DIV[3:0] ......................................................................................................................... 359 IPNO[2:0]/ NNO[2:0]............................................................................................................... 372 NL bits and drive duty(When SCN=”00000”) ...................................................................... 373 SCN bits and drive duty ........................................................................................................ 373 Page 16/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 198. External components ............................................................................................................ 377 Table 199. Pad center coordinates [Unit: µm] ....................................................................................... 378 Page 17/389 2008-12-29 Preface About This Data Sheet This document is to provide a complete Datasheet of S6D05A0 IC design. It also provides useful information to those who works on a panel module or a set. IMPORTANT NOTICE Precautions against Light The conductivity of a semiconductor is strongly influenced by electro-magnetic radiation such as visible light, infrared light, ultraviolet light, or gamma radiation. When light is absorbed, electron-hole pairs are generated raising the conductivity of the material, eventually altering the electrical characteristics of the IC. Therefore, if the packages that expose IC’s to external light sources, such as COB, COG, TCP, and COF, are used, effective means to shield the IC from the light coming in all directions – top, bottom, and the sides – must be devised. Full observation of the following precautions is strongly recommended. 1. Make sure that the IC and substrate (board or glass) are protected from a stray light. 2. Always test and inspect products under the environment with no light penetration. Page 18/389 2008-12-29 CHAPTER 1 OVERVIEW 1.1 Introduction 1.2 Product Options 1.3 Features 1.4 Block Diagram 1.5 Pad Information 1.6 Description of signal pads 1.7 Interface Pad Configuration Page 19/389 2008-12-29 1 OVERVIEW 1.1. INTRODUCTION S6D05A0 is a single-chip display driver IC for a TFT-LCD panel. Integrated on this chip are source drivers with built-in memory, gate drivers and power sources. S6D05A0 can support a TFT-LCD panel up to a resolution of 320-RGB x 480-dot or 360-RGB x 480-dot graphics with 16M-color. S6D05A0 also supports various types of peripheral interface such as 80-series MPU interface (8-/9-/16-/18-/24-bits data), and 3-wire 9bit / 4-wire 8bit serial interface. S6D05A0 supports various types of RGB interface (24-/18-/16-/8-/6-bits data), and MDDI. The Integrated on-chip functions that are described in this document include: - Power saving: It reduces the overall power consumed in a TFT-LCD panel module. - Internal GRAM: - Internal DC/DC voltage converter - MIE (Mobile Image Enhancement) functions S6D05A0 features several power saving functions to reduce the overall power consumed in a TFT-LCD panel module: S6D05A0 operates at low voltage and has internal GRAMs that can store 320-RGB x 480-dot or 360-RGB x 480-dot 16M-color image data. In addition, it has an internal DC/DC voltage converter that generates various voltages needed for driving the TFT-LCD panel by using breeder resistors and the voltage followers. S6D05A0 supports 320-RGB or 360-RGB Source Channel and It is possible to switch 320-RGB or 360-RGB Source Channel by setting register, This Spec is based on the assumption that the number of source channels is 320-RGB. 1.2. PRODUCT OPTIONS S6D05A0 offers more than one option in order to meet customer-specific functions from the customers. Table 1 describes its functions. Table 1. List of S6D05A0 options Options Remarks -X01 Reference design of S6D05A0 which supports various Host interfaces Page 20/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.3. FEATURES Mobile Display Driver IC S6D05A0 offers the following key features: z A single-chip TFT-LCD Controller/gate driver/source driver with built-in Graphic RAM z Supported Display panel resolution: 320*R/G/B (H) * 480 (V), 360*R/G/B (H) * 480 (V) z Integrated 4,147,200bit of graphic RAM (GRAM) „ GRAM configuration: 360 x 480 x 24-bits = 4,147,200bits z Supported Interfaces „ 3-wire 9-bit data, 4-wire 8-bit data serial interface (for RGB parallel Interface) „ 8-/9-/16-/18-/24- bit interface with 80-Series MPU (so called 80-Series) „ MDDI z Outputs „ Common electrode output „ Gate outputs „ Source outputs z Color Display mode „ Full color mode (Idle mode off): 16M / 260k / 65k colors „ Reduced color mode (Idle mode on): 8-colors (3-bit binary mode) z Color modes on the display host interface „ 16-bits/Pixel: RGB= (565) using the 4,147k bit frame memory „ 18-bits/Pixel: RGB= (666) using the 4,147k bit frame memory „ 24-bits/Pixel: RGB= (888) using the 4,147k bit frame memory z Display features „ Partial display mode z Driving scheme: line inversion & frame inversion z MIE (Mobile Image Enhancement) functions „ Adaptive luminance/contrast enhancement function. „ Reduce the power consumption of backlight. z On-chip functions „ Voltage Boosters „ Adjustable VCOM voltage source generator „ An oscillator for display clock generation & Timing generation „ Factory default value (Contrast, Module ID, Module version, etc) can be stored inside IC z MTP (Multi-time Programmable) Memory „ MTP initialization & program voltages are generated automatically from the built-in power circuit. „ Each 8-bits for product ID1/ID2/ID3 „ 6-bits for VCM, 5-bits for VML, 4-bits for GVD Offset adjustment „ 1 bit for MTP writing protection z Voltage Supplies Page 21/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 „ 2.3V – 3.3V for VCI, supply voltage for Analog blocks „ 1.65V – 3.3V for VDD3, Supply voltage for I/O z Output voltage levels „ 2.5V to 5.0V for GVDD, Source output voltage „ AVDD1/2, Power supply for driver circuit (Note 1) „ Maximum 6.0V for VCOM, Common electrode output voltage „ 13.75V to 19.25V for VGH, Positive Gate output voltage (Note 2, Note 3) „ -13.75V to - 8.25V for VGL, Negative Gate output voltage (Note 2) z CMOS compatible inputs z COG package z Operating temperature range: -40 to +85 Mobile Display Driver IC Note1. Available AVDD1/2 Min: 4.14V at VCI1 = 2.07V, Max=6V at VCI1 = 3V (AVDD1 is power supply for 2nd/3rd booster circuit, VCOM drifer, VCOMH/GVDD AMP, AVDD2 is power supply for source driver) Note2. |VGH - VGL| Max = 30V Note3. Maximum |VGH| should be lower than or equal to 19.25V in normal operating condition, regardless of VCI1 & BT settings. Note4. Blank display means: For normally white panel, the blank display indicates white display. For normally black panel, the blank display indicates black display Page 22/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.4. BLOCK DIAGRAM 1.4.1. Module Level Mobile Display Driver IC Figure 1 shows the block diagram of a mobile display panel module and related interface signals required by set makers and module makers. Level I interface signals represent the requirements by a set manufacturer that must be complied to by a module manufacturer. Level II interface signals, on the other hand, represent the requirements from the module manufacturer to that, typically, a driver IC manufacturer must comply. Panel Gate Power Driver IC Source Driver Memory Logic Memory Gate Power ETC HOST Interface Flexible PCB Level I Interface signals Level II Interface signals Figure 1. The interface signal flow of a mobile display panel module. There are also Level III signals which are for internal use only for the driver IC itself. These signals may not necessarily be released to the customer since they are designed for a specific manufacturing purpose and are supposed to be hidden features. The reference specifications shown in this document serve only as guidelines to Level I and II interface signals only; the reason being that a specification related to Level I and II considers the parasitic and design requirements within the flexible PCB used by a display module maker. IC specification will offer related information among Level I/II on how each interface signals relates to each other. Page 23/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.4.2. Functional Block Diagram of the IC .. .. .. .. .. .. .. Mobile Display Driver IC .. .. .. .. .. .. .. .. / 256 2/ / 24 Figure 2. S6D05A0 block diagram Page 24/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.5. PAD INFORMATION 1.5.1. Configuration of Signal Pads Mobile Display Driver IC Note: Pattern Surface Figure 3. S6D05A0 pad configuration Page 25/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.5.2. Bump Mobile Display Driver IC S6D05A0 pad dimensions Item Pad No. Size Unit X Y Chip size - 23,920 1,320 Bumped pad top size Input side Output side 45(70) 2 15 2 60 2 105 2 Height 15 3 (in wafer) µm Bumped pad height Tolerance in chip Under 2 Dimple height Under 2.0 Chip thickness - 300 Note1: Scribe lane 80um included in this die size Note2: Wafer thickness can be varies based on the customer’s need. Figure 4. Pad arrangement layout Page 26/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 5. Chip outline Page 27/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.5.3. Align Key Mobile Display Driver IC LEFT UPSIDE COG ALIGN KEY 100um RIGHT UPSIDE COG ALIGN KEY 100um 100um (-11865, 565) 15um 25um 20um 25um 15um 100um (11865, 565) 15um 25um 20um 25um 15um 15um 25um 20um 25um 15um LEFT DOWN SIDE COG ALIGN KEY 100um 15um 25um 20um 25um 15um RIGHT DOWNSIDE COG ALIGN KEY 100um 100um 100um (-11865, -565) (11865, -565) 10um 25um 25um 25um 15um Figure 6. COG align key configuration and coordinate Figure 7. COG align key arrangement layout Page 28/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.6. DESCRIPTION OF SIGNAL PADS 1.6.1. Pads for power supplies Mobile Display Driver IC Name VDD VDDM VDD3 VCI VCI_MDDI AVSS VSSC VSS VSS3 VSS_MDDI AVDD1 AVDD2 VCI1 VGH VGL VCL VGS VREF I/O Description Voltage regulator output for internal memory and logic circuit. Connect an external capacitor O for stabilization. Do not apply any external power to this pad. I Power supply for internal memory. This pad should be connected to VDD pad. P Power supply for I/O block provided from outside P Power supply for analog and voltage booster block. I Power supply for MDDI I/O block. Must be connected to VCI level. P GND for analog circuits. P GND for voltage booster circuits. P GND for logic circuits. P GND for IO block. I GND for MDDI I/O block. Internally generated voltage output pad for 2nd booster and VCOM block. Output voltage of 1st booster circuit ( =2 x VCI1) O Input voltage to 2nd booster and VCOM circuit. This pad needs to an external storage capacitor. Internally generated voltage output pad for source driver block. Output voltage of 1st booster circuit ( =2 x VCI1) O Input voltage to source block. This pad needs to an external storage capacitor. Reference input voltage for 1st booster circuit. O Connect a capacitor for stabilization. VCI1 cannot exceed 3V Positive power output of the 2nd booster circuit. O Gate “ON” level voltage. Connect a capacitor for storage function. Negative power output of the 2nd booster circuit. O Gate “OFF” level voltage. Connect a capacitor for storage function. 3rd booster output voltage. O Power supply for generating VCOML block. Connect a capacitor for storage function. Reference voltage input for grayscale voltage generator. I Connect an external resistor or to system ground. Reference voltage for generating GVDD voltage. O Reference voltage input for VCOMH / VCOML voltage generator. Page 29/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Name GVDDO VCOMH VCOML I/O Description Reference voltage input for grayscale voltage generator. O An internal register can be used to adjust the GVDD voltage. Connect a capacitor for stabilization. High level output voltage of VCOM. O An internal register can be used to adjust the VCOMH voltage. Connect a capacitor for stabilization. Low level output voltage of VCOM. An internal register can be used to adjust the difference voltage between O VCOMH and VCOML. Connect a capacitor for stabilization. Note. As VDDM pad is used to test for memory leakage current, it should be connected VDD pad in normal operation. ‘ Table 2. Pads for power supplies (continued) Symbol I/O Description Power supply pad for the TFT- display common electrode. VCOM O Charge recycling method is used with VCI voltage. Connect this pad to the TFT-display common electrode C11P, C11M C12P, C12M - Connect the charge-pumping capacitor for generating AVDD1 level. C13P, C13M C14P, C14M - Connect the charge-pumping capacitor for generating AVDD2 level. C21P, C21M C22P, C22M - Connect the charge-pumping capacitor for generating VGH, VGL level. C31P, C31M, C32P, C32M - Connect the charge-pumping capacitor for generating VCL level. Page 30/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.6.2. Signal Pads for Logic Interface Mobile Display Driver IC Table 3. Signal pads for logic interface Name I/O Description Differential Data input/output pads for MDDI interface. When the forward link activates, MDP/MDN I/O MDP/MDN receive data from host. When the reverse link activates, MDP/MDN transmit data to host. If MDDI is not used, this pad should be unconnected. Differential Strobe input pads for MDDI interface. These pads always receive strobe data MSP/MSN regardless of link direction. I/O Also these pads are output pads for MDDI failsafe function. If MDDI is not used, this pad should be unconnected. IM[2:0] Selects the interface mode. IM2 IM1 IM0 Interface mode 1 0 0 80 MPU 24-bit Parallel I/F 0 1 1 80 MPU 18-bit Parallel I/F 0 0 0 80 MPU 16-bit Parallel I/F 0 0 1 I 0 1 0 80 MPU 9-bit Parallel I/F 80 MPU 8-bit Parallel I/F 3-wire 9-bit data Serial interface 1 0 1 & RGB Interface 4-wire 8-bit data Serial interface 1 1 0 & RGB Interface 1 1 1 MDDI DB pad DB[23:0] DB[17:0] DB[15:0] DB[8:0] DB[7:0] Refer to DB Description Refer to DB Description Refer to DB Description RESX CSX DCX RDX WRX Active low. This signal is used to reset the device and must be applied to initialize the chip I properly. Chip select signal. Activate MPU interface mode by setting this to ‘low’. This pad can be I permanently connected to “Low” in MPU interface mode only. If not used, connect this pad to either VSS or VDD3. Display Data/Command selection signal in parallel interface DCX=’1’: Display Data or Command parameter. I DCX=’0’: Command Index. If not used, connect this pad to either VSS or VDD3. Read Enable in 80-parallel interface. I If not used, connect this pad to VDD3. Write Enable in 80-parallel interface. I Serial interface clock in Serial Interface If not used, connect this pad to either VSS or VDD3. Page 31/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 4. Signal pads for logic interface(continued) Name I/O Description Data Bus. Interface Mode VFPF IM RIM (Note*) Interface Mode 100 X X 80 MPU 24-bit Parallel I/F 011 X X 80 MPU 18-bit Parallel I/F 000 X X 80 MPU 16-bit Parallel I/F 001 X X 80 MPU 9-bit Parallel I/F 010 X X 80 MPU 8-bit Parallel I/F 3-wire 9-bit data Serial 0 111 Interface & RGB 24-bit I/F 3-wire 9-bit data Serial 0 110 Interface & RGB 18-bit I/F 3-wire 9-bit data Serial 101 0 101 Interface & RGB 16-bit I/F DB[23:0] I/O 1 111 1 110 3-wire 9-bit data Serial Interface & RGB 8-bit I/F 3-wire 9-bit data Serial Interface & RGB 6-bit I/F 4-wire 8-bit data Serial 0 111 Interface & RGB 24-bit I/F 4-wire 8-bit data Serial 0 110 Interface & RGB 18-bit I/F 4-wire 8-bit data Serial 110 0 101 Interface & RGB 16-bit I/F 1 111 4-wire 8-bit data Serial Interface & RGB 8-bit I/F 1 110 4-wire 8-bit data Serial Interface & RGB 6-bit I/F 111 X X MDDI Note1. “X“ denotes “Don’t care" Note2. VFPF = COLMOD[6:4] (Refer to 3Ah Command) Mobile Display Driver IC Description Index Data DB[7:0] DB[7:0] DB[7:0] DB[7:0] DB[7:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] SDA Or DB[1:0] - DB[23:0] DB[17:0] DB[15:0] DB[8:0] DB[7:0] DB[23:0] DB[17:0] DB[15:0] DB[7:0] DB[5:0] DB[23:0] DB[17:0] DB[15:0] DB[7:0] DB[5:0] - SDA Must be connected to VDD3 or VSS level when not used. I/O Serial data bus. If not used, connect this pad to either VDD3 or VSS. Page 32/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 5. Signal pads for logic interface(continued) Name I/O Description When use SDA in Serial I/F for instruction, Connect this pad to VSS. MFIX_SEL When use DB[1:0] in Serial I/F for instruction , If MFIX_SEL is high, DB[1:0] is used to transfer I instruction, If MFIX_SEL is low , DB[1:0] is used to transfer DISPLAY DATA. Refer to the 1.7 INTERFACE PAD CONFIGURATION. Tearing effect output pad to synchronize MPU to frame writing, activated by S/W command. TE O When this pad is not activated, this signal stays low. If not used, leave this pad unconnected. DOTCLK Pixel clock signal in RGB I/F mode. I If not used, connect this pad to either VDD3 or VSS. VSYNC Vertical Sync signal in RGB I/F mode. I If not used, connect this pad to either VDD3 or VSS. HSYNC Horizontal Sync signal in RGB I/F mode. I If not used, connect this pad to either VDD3 or VSS. ENABLE Data Enable signal in RGB I/F mode. I If not used, connect this pad to either VDD3 or VSS. Note. If CSX is connected to VSS in Parallel interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore there should be no influence to the Power Consumption of the display module. When CSX=’1’, there is no influence to the parallel interface. Table 6. Pads for source/gate driver output signal Name I/O S1 to S1080 O Signal pads for Source driver output. G1 to G480 O Signal pads for Gate driver output. Description Table 7. MIE pins Name I/O BC O BC_CTL O Description This pin is used to PWM output for back light control of LED driver. If not used, this pin should be opened. This pin is used to enable the back light LED driver (active high). If not used, this pin should be opened. Page 33/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 8. Miscellaneous signal pads Name I/O Description Output pads used only for test purpose at IC-side. CL1 O In normal operation, leave this pad unconnected. CONTACT1 CONTACT2 CONTACT3 CONTACT4 Contact resistance measurement pad. In normal operation, leave this unconnected. These - pads are at VSS level. When measuring an ohmic resistance of the contact, do not apply any power. Dummy Dummy PAD. These pads are floated. Dummy_ VSS3 Dummy PAD. These pads are at VSS Level. Leave these pads floated. Dummy_ VSS Dummy PAD. These pads are at VSS Level. Leave these pads floated. Dummy_ VGH Dummy PAD. These pads are at VGH Level. Leave these pads floated. Dummy_ VGL Dummy PAD. These pads are at VGL Level. Leave these pads floated. Table 9. Test signal pads. Name I/O Description TMODE [3:0] Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. OSCEX Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. OSCEX_EN Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. OSCOUT Output pads used only for test purpose at IC-side. O During normal operation, leave this pad unconnected. TREGB Input pad used only for test purpose at IC-side. I During normal operation, connect this pad to VSS. TEST_MUX [2:0] Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. TEST_YA [2:0] Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. TEST_XA Input pads used only for test purpose at IC-side. I During normal operation, connect these pads to VSS. Page 34/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 1.7. INTERFACE PAD CONFIGURATION Mobile Display Driver IC Table 10. Interface pad configuration1 (MPU) PIN NAME/ IF MODE 24bit 18bit TMODE[3:0] VSS VSS MFIX_SEL VSS VSS IM[2] VDD3 VSS IM[1] VSS VDD3 IM[0] VSS VDD3 MDP/MDN floating floating MSP/MSN floating floating RESX RESX RESX CSX CSX CSX DCX DCX DCX WRX WRX WRX RDX RDX RDX VSYNC (VSYNC) (VSYNC) HSYNC VDD3/VSS VDD3/VSS ENABLE VDD3/VSS VDD3/VSS DOTCLK VDD3/VSS VDD3/VSS SDA VDD3/VSS VDD3/VSS DB[23:18] DB[23:18] VDD3/VSS DB[17:16] DB[17:16] DB[17:16] DB[15:9] DB[15:9] DB[15:9] DB[8] DB[8] DB[8] DB[7:0] DB[7:0] DB[7:0] 80 MPU 16bit VSS VSS VSS VSS VSS floating floating RESX CSX DCX WRX RDX (VSYNC) VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[15:9] DB[8] DB[7:0] 9bit VSS VSS VSS VSS VDD3 floating floating RESX CSX DCX WRX RDX (VSYNC) VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[8] DB[7:0] 8bit VSS VSS VSS VDD3 VSS floating floating RESX CSX DCX WRX RDX (VSYNC) VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[7:0] MDDI VSS VDD3/VSS VDD3 VDD3 VDD3 MDP/MDN MSP/MSN RESX VDD3/VSS VDD3/VSS VDD3/VSS VDD3 VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS Page 35/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 11. Interface pad configuration2 (SPI 3wire/RGB, When Use SDA for instruction) PIN NAME/ RGB(SPI 3wire) IF MODE 24bit 18bit 16bit 8bit 6bit TMODE[3:0] VSS VSS VSS VSS VSS MFIX_SEL VSS VSS VSS VSS VSS IM[2] VDD3 VDD3 VDD3 VDD3 VDD3 IM[1] VSS VSS VSS VSS VSS IM[0] VDD3 VDD3 VDD3 VDD3 VDD3 MDP/MDN floating floating floating floating floating MSP/MSN floating floating floating floating floating RESX RESX RESX RESX RESX RESX CSX CSX CSX CSX CSX CSX DCX VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS WRX SCL SCL SCL SCL SCL RDX VDD3 VDD3 VDD3 VDD3 VDD3 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK SDA SDA SDA SDA SDA SDA DB[23:18] DB[23:18] VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[17:16] DB[17:16] DB[17:16] VDD3/VSS VDD3/VSS VDD3/VSS DB[15:8] DB[15:8] DB[15:8] DB[15:8] VDD3/VSS VDD3/VSS DB[7:6] DB[7:6] DB[7:6] DB[7:6] DB[7:6] VDD3/VSS DB[5:0] DB[5:0] DB[5:0] DB[5:0] DB[5:0] DB[5:0] Note1. SDA is used to transfer Instruction, and DB[23:0] are used to transfer DISPLAY Data according to the I/F Type. Page 36/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 12. Interface pad configuration3 (SPI 4wire/RGB, When Use SDA for instruction) PIN NAME/ RGB(SPI 4wire) IF MODE 24bit 18bit 16bit 8bit 6bit TMODE[3:0] VSS VSS VSS VSS VSS MFIX_SEL VSS VSS VSS VSS VSS IM[2] VDD3 VDD3 VDD3 VDD3 VDD3 IM[1] VDD3 VDD3 VDD3 VDD3 VDD3 IM[0] VSS VSS VSS VSS VSS MDP/MDN floating floating floating floating floating MSP/MSN floating floating floating floating floating RESX RESX RESX RESX RESX RESX CSX CSX CSX CSX CSX CSX DCX DCX DCX DCX DCX DCX WRX SCL SCL SCL SCL SCL RDX VDD3 VDD3 VDD3 VDD3 VDD3 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK SDA SDA SDA SDA SDA SDA DB[23:18] DB[23:18] VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[17:16] DB[17:16] DB[17:16] VDD3/VSS VDD3/VSS VDD3/VSS DB[15:8] DB[15:8] DB[15:8] DB[15:8] VDD3/VSS VDD3/VSS DB[7:6] DB[7:6] DB[7:6] DB[7:6] DB[7:6] VDD3/VSS DB[5:0] DB[5:0] DB[5:0] DB[5:0] DB[5:0] DB[5:0] Note1. SDA is used to transfer Instruction, and DB[23:0] are used to transfer DISPLAY Data according to the I/F Type. Page 37/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 13. Interface pad configuration4 (SPI 3wire/RGB, When Use DB[1:0] for instruction) PIN NAME/ RGB(SPI 3wire) IF MODE 24bit 18bit 16bit 8bit 6bit TMODE[3:0] VSS VSS VSS VSS VSS MFIX_SEL VSS / VDD3 VSS / VDD3 VSS / VDD3 VSS / VDD3 VSS / VDD3 IM[2] VDD3 VDD3 VDD3 VDD3 VDD3 IM[1] VSS VSS VSS VSS VSS IM[0] VDD3 VDD3 VDD3 VDD3 VDD3 MDP/MDN floating floating floating floating floating MSP/MSN floating floating floating floating floating RESX RESX RESX RESX RESX RESX CSX CSX CSX CSX CSX CSX DCX VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS WRX SCL SCL SCL SCL SCL RDX VDD3 VDD3 VDD3 VDD3 VDD3 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK SDA VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[23:18] DB[23:18] VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[17:16] DB[17:16] DB[17:16] VDD3/VSS VDD3/VSS VDD3/VSS DB[15:8] DB[15:8] DB[15:8] DB[15:8] VDD3/VSS VDD3/VSS DB[7:6] DB[7:6] DB[7:6] DB[7:6] DB[7:6] VDD3/VSS DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[1] DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[0] DB[0] / SDI DB[0] / SDI DB[0] / SDI DB[0] / SDI DB[0] / SDI Note1. When MFIX_SEL is high, DB[0] is used to transfer Instruction, and DB[1] is used to read instruction from IC, When MFIX_SEL is Low, DB[23:0] are used to transfer DISPLAY data according to the I/F Type. Page 38/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 14. Interface pad configuration5 (SPI 4wire/RGB, When Use DB[1:0] for instruction) PIN NAME/ RGB(SPI 4wire) IF MODE 24bit 18bit 16bit 8bit 6bit TMODE[3:0] VSS VSS VSS VSS VSS MFIX_SEL VSS / VDD3 VSS / VDD3 VSS / VDD3 VSS / VDD3 VSS / VDD3 IM[2] VDD3 VDD3 VDD3 VDD3 VDD3 IM[1] VDD3 VDD3 VDD3 VDD3 VDD3 IM[0] VSS VSS VSS VSS VSS MDP/MDN floating floating floating floating floating MSP/MSN floating floating floating floating floating RESX RESX RESX RESX RESX RESX CSX CSX CSX CSX CSX CSX DCX DCX DCX DCX DCX DCX WRX SCL SCL SCL SCL SCL RDX VDD3 VDD3 VDD3 VDD3 VDD3 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK DOTCLK SDA VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[23:18] DB[23:18] VDD3/VSS VDD3/VSS VDD3/VSS VDD3/VSS DB[17:16] DB[17:16] DB[17:16] VDD3/VSS VDD3/VSS VDD3/VSS DB[15:8] DB[15:8] DB[15:8] DB[15:8] VDD3/VSS VDD3/VSS DB[7:6] DB[7:6] DB[7:6] DB[7:6] DB[7:6] VDD3/VSS DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[5:2] DB[1] DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[1] / SDO DB[0] DB[0] / SDI DB[0] / SDI DB[0] / SDI DB[0] / SDI DB[0] / SDI Note1. When MFIX_SEL is high, DB[0] is used to transfer Instruction, and DB[1] is used to read instruction from IC, When MFIX_SEL is Low, DB[23:0] are used to transfer DISPLAY data according to the I/F Type. Page 39/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC CHAPTER 2 ELECTRICAL SPECIFICATION 2.1 Absolute Maximum Ratings 2.2 DC Electrical Characteristics 2.3 AC Characteristics 2.4 MDDI DC/AC Characteristics Page 40/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 2 ELECTRICAL SPECIFICATIONS Mobile Display Driver IC 2.1. ABSOLUTE MAXIMUM RATINGS Table 15. Absolute maximum ratings Item Symbol Rating Unit Supply voltage for logic block VDD - VSS -0.3 to +3.3 V Supply voltage for I/O block VDD3 - VSS -0.3 to +5.0 V Supply voltage for step-up circuit VCI - VSS -0.3 to +5.0 V AVDD – VSS -0.3 to +6.5 V VGH - VSS -0.3 to +22.0 V LCD Supply Voltage range VSS – VGL -0.3 to +22.0 V VSS - VCL -0.3 to +5.0 V |VGH – VGL| -0.3 to +33 V Input Voltage range Vin - 0.3 to VDD3 + 0.5 V Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +110 °C Note1. The absolute maximum rating is the limit value. When the IC is exposed to the operating environment beyond this range, the IC does not assure normal operations and may be damaged permanently, not be able to be recovered. Note2. The operating temperature is the range of device-operating temperature. They do not guarantee chip performance. Caution Stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to maximum rating conditions for extended periods may reduce device reliability. Page 41/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 2.2. DC ELECTRICAL CHARACTERISTICS 2.2.1. BASIC Characteristics Table 16. DC electrical characteristics (Ta = 25°C). Characteristic Symbol CONDITION Power supply for I/O Power supply, for Internal reference LCD driving voltage VDD3 VCI VGH VGL VCL AVDD1 AVDD2 GVDD Logic Input voltage, high VIH Logic Input voltage, low VIL Logic output voltage, high VOH IOH = -0.5mA Logic output voltage, low Leakage current, input Leakage current, output Operating frequency Input voltage to the 1st Booster VOL IIL IOL Fosc VCI1 IOL = 0.5mA VIN = VSS or VDD3 VIN = VSS or VDD3 Frame freq. = 60 Hz Display line = 480 Ta = 25°C MIN 1.65 2.3 13.75 -13.75 -3.0 4.14 4.14 2.5 0.7* VDD3 0 0.8* VDD3 0.0 -1.0 -3.0 0.9*TY P 2.07 TYP - - - - 15 - Mobile Display Driver IC MAX 3.3 3.3 19.25 -8.25 -2.07 6.0 6.0 5.0 Unit V V V V V V V V Note *1 *1 VDD3 V *2 0.3* V *2 VDD3 VDD3 V *3 0.2* V *3 VDD3 1.0 uA *2 3.0 uA *3 1.1*TY P MHz 3.0 V *4 Power efficiency of the 1st Booster ηAVDD Load current= 4mA 90 95 - % Power efficiency of the 2nd Booster ηVGH Load current= 100uA 90 95 - % Power efficiency of the 3rd Booster ηVGL Load current= 100uA 90 95 - % Power efficiency of the 4th Booster ηVCL Load current= 300uA 90 95 - % VCI=3V,VDD3=3V Frame(f)=60Hz Current consumption during normal IVDD3 MPU I/F - operation White pattern MIE function off - 1500 uA - Page 42/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Characteristic Symbol CONDITION MIN TYP MAX Unit Note VCI=3V,VDD3=3V IVCI - Frame(f)=60Hz - 20 mA - Current consumption during Sleep mode IVCI VIN=VDD3, VCI,VSS - IVDD3 VIN=VDD3, VCI,VSS - 5 uA - 25 uA Current consumption during IVCI VIN=VDD3, VCI,VSS - - 5 uA - Deep Standby mode IVDD3 VIN=VDD3, VCI,VSS 5 uA Note1 .VCI1=2.75V Note2. Signals under consideration; CSX, RDX, WRX, DB0 to DB23, RESX, SDA,IM,DCX,VSYNC,HSYNC,ENABLE,DOTCLK, MFIX_SEL, Note3. Signals under consideration; DB0 to DB23, TE, SDA,BC,BC_CTL,TE Note4. Practical VCI1 range is over 2.07V. VCI1 under 2.07V is used only for power-up period. Table 17. DC characteristics for LCD driver outputs (TYP: VCI=VDD3=3.0V, Ta=25°C) Characteristic Symbol Condition MIN TYP MAX Unit Note On resistance of Ronvgh VGH=16.5V - - 3.0 - Gate driver output Ronvgl VGL=-13.5V - - 3.0 - On resistance of Ronp AVDD=5.0V - - 20 - source driver output Ronn AVSS=0V - - 20 - On resistance of Ronpb GVDD=4.5V - - 300 - binary driver Output Ronnb AVSS=0V - - 300 - Output voltage deviation (Mean value) AVDD=5.0V, GVDD=4.5V AVDD-0.8V≤VSO - ∆VO 0.8V 350) Page 106/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.3. 18-bit RGB Interface 3.3.3.1. Bit Assignment Mobile Display Driver IC Figure 71. Bit assignment of GRAM data on 18bit RGB interface(IPM=”100”) 3.3.3.2. Timing Diagram Figure 72. Timing diagram of 18bit RGB interface Note. The number of DOTCLK for 1H period must be bigger than Horizontal Pixel + 30 (ex 320RGB :DOTCLK > 350) Page 107/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.4. 16-bit RGB Interface 3.3.4.1. Bit Assignment Mobile Display Driver IC Figure 73. Bit assignment of GRAM data on 16bit RGB interface(IPM=”100”) 3.3.4.2. Timing Diagram Figure 74. Timing diagram of 16bit RGB interface Note. The number of DOTCLK for 1H period must be bigger than Horizontal Pixel + 30 (ex 320RGB :DOTCLK > 350) Page 108/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.5. 8-bit RGB Interface In order to transfer data on 8bit RGB Interface there should be three transfers. 3.3.5.1. Bit Assignment Mobile Display Driver IC Figure 75. Bit assignment of GRAM data on 8bit RGB interface 3.3.5.2. Timing Diagram Figure 76. Timing diagram of 8bit RGB interface Note1. Three clocks are regarded as one clock for transfer when data is transferred in 8-bit interface. VSYNC, HSYNC, ENABLE, DOTCLK, and DB[7:0] should be transferred in units of three clocks. Note2. The number of DOTCLK for 1H period must be bigger than ((Horizontal Pixel + 30)X3), (ex 320RGB :DOTCLK > 350X3) Page 109/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.5.3. Transfer Synchronization Mobile Display Driver IC Figure 77. Transfer synchronization function in 8-bit RGB interface mode Note. The figure above shows Transfer Synchronization functions for 8bit RGB Interface. S6D05A0 has a transfer counter internally to count 1st, 2nd and 3rd data transfer of 8bit RGB Interface. The transfer counter is reset on the falling edge of VSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected at every VSYNC signal assertion. In this method, when data is consecutively transferred in for displaying motion pictures, the effect of transfer mismatch will be reduced and recovered by normal operation. The display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch occurs and the frame, which is operated, and the next frame are not displayed correctly. Page 110/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.6. 6-bit RGB Interface In order to transfer data on 6bit RGB Interface there should be three transfers. 3.3.6.1. Bit Assignment Mobile Display Driver IC Figure 78. Bit assignment of GRAM data on 6bit RGB interface(IPM=”100”) 3.3.6.2. Timing Diagram VSYNC HSYNC DOTCLK ENABLE DB[5:0] > = 2H Back Porch 1 Frame 1H Front Porch HSYNC DOTCLK ENABLE DB[5:0] > = 6 CLK 1 CLK R G BR G B R G BR G B R G BR G B R G B R G B R G B R G B R G B R G BR G B Figure 79. Timing diagram of 6bit RGB interface Note1. Three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface. VSYNC, HSYNC, ENABLE, DOTCLK, and DB[5:0] should be transferred in units of three clocks. Note2. The number of DOTCLK for 1H period must be bigger than ((Horizontal Pixel + 30)X3), (ex 320RGB :DOTCLK > 350X3) Page 111/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.3.6.3. Transfer Synchronization Mobile Display Driver IC Figure 80. Transfer synchronization function in 6-bit RGB interface mode Note. The figure above shows Transfer Synchronization functions for 6bit RGB Interface. S6D05A0 has a transfer counter internally to count 1st, 2nd and 3rd data transfer of 6bit RGB Interface. The transfer counter is reset on the falling edge of VSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected at every VSYNC signal assertion. In this method, when data is consecutively transferred in for displaying motion pictures, the effect of transfer mismatch will be reduced and recovered by normal operation. The display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch occurs and the frame, which is operated, and the next frame are not displayed correctly. Page 112/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4. MDDI 3.4.1. Introduction to MDDI Mobile Display Driver IC The S6D05A0 supports MDDI, mobile display driver interface. The physical layer of MDDI is based on a high-speed, differential serial interface. Both command and image data transfer can be achieved with MDDI. MDDI host & client are linked by Data and STB line. Through Data line, either command or image data is transferred from MDDI host to MDDI client, and vice versa. Data is transferred by packet unit. Through STB line, strobe signal is transferred. When the link is in “FORWARD direction,” data is transferred from host to client; in “REVERSE direction,” client transfers data to MDDI host. Figure 81. Physical connection of MDDI host and client Page 113/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.2. Data-STB Encoding Mobile Display Driver IC Data is encoded using a DATA-STB method. Data signal is bi-directional over a pair of differential cable while STB signal is unidirectional over a pair of differential cable driven by a host as shown in following Figure. Figure below illustrates how the data sequence “1110001011” is transmitted using DATA-STB encoding. Figure 82. Data-STB encoding The Following figure shows a sample circuit to generate DATA and STB from input data, and then recover the input data from DATA and STB. Figure 83. Data / STB generation & recovery circuit Page 114/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.3. MDDI Data & STB Mobile Display Driver IC The Data (MDP/MDN) and STB (MSP/MSN) signals are always operated in a differential mode to maximize noise immunity. Each differential pair is parallel-terminated with the characteristic impedance of the cable. All parallelterminations are in the client device. Figure below illustrates the configuration of the drivers, receivers, and terminations. The driver of each signal pair has a differential current output. While receiving MDDI packets. The MDDI_DATA and MDDI_STB pairs use a conventional differential receiver with a differential voltage threshold of zero volts. In the hibernation state, the driver outputs are disabled and the parallel termination resistors pull the differential voltage on each signal pair to zero volts. During hibernation, a special receiver on the MDDI_DATA pairs has an offset input differential voltage threshold of positive 125 mV, which causes the hibernation line receiver to interpret the un-driven signal pair as logic-zero level. Figure 84. Differential connection between host and client Page 115/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.4. MDDI Packet Mobile Display Driver IC MDDI transfer data in a packet format. MDDI host can generate and send packets. In S6D05A0, several packet formats are supported. Packets are transferred from MDDI host to client (forward direction); but reverse encapsulation packet is transferred from MDDI client to host (reverse direction). A number of packets, started by sub-frame header packet, construct 1 sub frame. Figure 85. MDDI packet structure Refer to MDDI packet structure, sub-frame header packet is placed in front of a sub-frame, and some sub-frame construct media-frame together. The following table describes 9 types of packets which are supported in S6D05A0. Packet Sub-frame header packet Register access packet Video stream packet Filler packet Reverse link encapsulation packet Round-trip delay measurement packet Client capability packet Client request and status packet Link shutdown packet Function Header of each sub frame Register setting Video data transfer Fill empty packet space Reverse data packet Host->client->host delay check Capability of client check Information about client status End of frame Direction Forward Forward Forward Forward Reverse Forward/Reverse Reverse Reverse Forward Page 116/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Sub-frame header packet Mobile Display Driver IC Figure 86. Sub-Frame header packet structure Register access packet Basis of Register Data List is 4byte unit. Therefore, when write 1parameter, remainders must fill by 0. Video Stream packet Figure 87. Register access packet structure Figure 88. Video stream packet structure Page 117/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Filler packet Mobile Display Driver IC Link shutdown packet Figure 89. Filler packet structure Figure 90. Link shutdown packet structure : fixed value For More information about MDDI packet, refer to VESA MDDI spec. Page 118/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.5. Panel Control Mobile Display Driver IC S6D05A0 supports video stream packet for memory write and register access packet for register write/read. Followings are some examples of memory and register write/read sequence. 3.4.5.1. Writing Video Data to Memory Sequence Figure 91. Writing video data to memory sequence Table 61. COLMOD setting in MDDI Video data format descriptor[11:0] COLMOD[2:0] 1000_1000_1000 111 (16M color) 0110_0110_0110 110 (262k color) 0101_0110_0101 101 (65k color) Note: If user want to transfer 888(24bit) video data, Set COLMOD[2:0]=”111” prior to Video Stream Packet 3.4.5.2. Writing Register Sequence Figure 92. Writing register sequence Page 119/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.5.3. Reading Video Data from Memory Sequence Mobile Display Driver IC In order to read a pixel data from memory(readable one pixel only), the following sequence should be programmed. Memory read command (2EH) is followed by reverse encapsulation packet. DDI transmits video pixel data through encapsulation packet. Please refer to VESA spec for detailed description. Figure 93. Reading video data from memory sequence 3.4.5.4. Reading Register Sequence In order to read registers, the following sequence should be programmed. Register read command is followed by reverse encapsulation packet. DDI transmits register data through encapsulation packet. Please refer to VESA spec for detailed description. Figure 94. Reading register sequence Note: Only Level 1 Registers are readable in MDDI. Page 120/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.6. Tearing-less Display Mobile Display Driver IC In S6D05A0, the matching between data writes timing and written data display timing is important. If timing is mismatched, tearing effect can occur. To avoid display tearing effect, two possible ways are suggested. First case is that data write is slower than speed of displaying written data. In this case, data write speed is not critical, but current consumption in interface will be increased because data transfer time is long. Data write time is selected widely in this case. Other case is that data write is faster than speed of displaying written data. In this case, data update speed is very high so that transfer time is short. So current consumption in interface can be minimized, but it requires fast data transfer. The most important thing is to avoid data scan conflicts with data update. The following figures describe some examples to avoid display tearing phenomenon. A. Display speed is slower than data write. Figure 95. Tearing-less display: data write speed is faster than display Page 121/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 B. Display speed is faster than data write. Mobile Display Driver IC Figure 96. Tearing-less display: display speed is faster than data write Page 122/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.7. Hibernation / Wake-up Mobile Display Driver IC S6D05A0 support hibernation mode to save interface power consumption. MDDI link can enter the hibernation state quickly and wake up from hibernation quickly. This allows the system to force MDDI link into hibernation frequently to save power consumption. During hibernation mode, the hi-speed transmitters and receivers are disabled and the low-speed & low-power receivers are enabled in order to detect wake-up sequence. Figure 97. MDDI transceiver / receiver state in hibernation When the link wakes up from hibernation, the host and client exchange a sequence of pulses. These pulses can be detected using low-speed, low-power receivers that consume only a fraction of the current of the differential receivers required to receive the signals at the maximum link operating speed. Either the client or the host can wake up the link; Host-initiated link wakeup and Client-initiated link wakeup. Page 123/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.8. MDDI Link Wake-up Procedure Mobile Display Driver IC A. Host-initiated Link Wake-up Procedure The simple case of a host-initiated wake-up is described below without contention from the client trying to wake up at the same time. The following sequence of events is illustrated in the following figure. Figure 98. Host-Initiated link wake-up sequence The Detailed descriptions for labeled events are as follows: 1. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power hibernation state. 2. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data to a logic-zero level, and then disables the MDDI_Data output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point 3. 3. The host enters the low-power hibernation state by disabling the MDDI_Data and MDDI_Stb drivers and by placing the host controller into a low-power hibernation state. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. 4. After a while, the host begins the link restart sequence by enabling the MDDI_Data and MDDI_Stb driver outputs. The host drives MDDI_Data to a logic-one level and MDDI_Stb to logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200n sec after MDDI_Data reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. The client first detects the wake-up pulse using a low-power differential receiver having a +125mV input offset voltage. Page 124/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5. The host drivers are fully enabled and MDDI_Data is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consistent with having logic-zero level on MDDI_Data for duration of 150 MDDI_Stb cycles. 6. The host drives MDDI_Data to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data is at logic-zero level for 40 MDDI_Stb cycles. 7. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point 7. The MDDI host generates MDDI_Stb based on the logic level on MDDI_Data so that proper data-strobe encoding commences from point 7. B. Client-initiated Link Wake-up Procedure An example of a typical client-initiated service request event with no contention is illustrated in the following figure. Figure 99. Client-Initiated link wake-up sequence The Detailed descriptions for labeled events are as follows: 1. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power hibernation state. 2. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data to a logic-zero level, and then disables the MDDI_Data output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point 3. 3. The host enters the low-power hibernation state by disabling its MDDI_Data and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. Page 125/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 4. After a while, the client begins the link restart sequence by enabling the MDDI_Stb receiver and also enabling an offset in its MDDI_Stb receiver to guarantee the state of the received version of MDDI_Stb is a logical-zero level in the client before the host enables its MDDI_Stb driver. The client will need to enable the offset in MDDI_Stb immediately before enabling its MDDI_Stb receiver to ensure that the MDDI_Stb receiver in the client is always receiving a valid differential signal and to prevent erroneous received signals from propagating into the client. After that, the client enables its MDDI_Data driver while driving MDDI_Data to a logic-one level. It is allowed for MDDI_Data and MDDI_Stb to be enabled simultaneously if the time to enable the offset and enable the standard MDDI_Stb differential receiver is less than 200n sec. 5. Within 1m sec the host recognizes the service request pulse, and the host begins the link restart sequence by enabling the MDDI_Data and MDDI_Stb driver outputs. The host drives MDDI_Data to a logic-one level and MDDI_Stb to a logical-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200n sec after MDDI_Data reaches a valid logic-one level and MDDI_Stb reaches a valid fully-driven logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. 6. The host begins outputting pulses on MDDI_Stb and shall keep MDDI_Data at a logic-one level for a total duration of 150 MDDI_Stb pulses through point 8. The host generates MDDI_Stb in a manner consistent with sending a logicalzero level on MDDI_Data. When the client recognizes the first pulse on MDDI_Stb it shall disable the offset in its MDDI_Stb receiver. 7. The client continues to drive MDDI_Data to a logic-one level for 70 MDDI_Stb pulses, and the client disables its MDDI_Data driver at point 7. The host continues to drive MDDI_Data to a logic-one level for duration of 80 additional MDDI_Stb pulses, and at point 8 drives MDDI_Data to logic-zero level. 8. The host drives MDDI_Data to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data is at logic-zero level for 40 MDDI_Stb cycles. 9. After asserting MDDI_Data to logic-zero level and driving MDDI_Stb for duration of 50 MDDI_Stb pulses the host begins to transmit data on the forward link at point 9 by sending a Sub-frame Header Packet. The client begins to look for the Sub-frame Header Packet after MDDI_Data is at logic-zero level for 40 MDDI_Stb cycles. Page 126/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.9. Client-Initiated Link Wake-up Mobile Display Driver IC S6D05A0 supports VSYNC based client-initiated link wake-up. As client-initiated wake-up action is executed in hibernation state only, the register setting for wake-up have to be set before link shut-down. A. VSYNC Based Link Wake-up In display-ON state, when the IC finishes displaying all internal GRAM data, data request must be transferred to MDDI host for new video data. As MDDI link is usually in hibernation for reducing interface power consumption, MDDI link wake-up must be done before internal GRAM update. In that case, client initiated link wake-up can be used as data request. When VSYNC based link wake-up register (E0h: VWAKE_EN) is set, client initiated wake-up is executed in synchronization with the vertical-sync signal which generated in S6D05A0. Using VSYNC based link wake-up, tearingless display can be accomplished if interface speed and wake-up time is well known. The following figure shows detailed timing for VSYNC based link wake-up. Figure 100. VSYNC based link wake-up procedure The Detailed descriptions for labeled events are as follows: 1. MDDI host writes to the VSYNC based link wakeup register to enable a wake-up based on internal vertical-sync signal. 2. Link_active goes low when the host puts in the link into hibernation after no more data needs to be sent to the S6D05A0. 3. Frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped around and is now reading from the beginning of the frame buffer. Link wake-up can be set using WKF and WKL (E1h) registers. WKF specifies the number of frame before wake-up; WKL specifies the number of lines before wake-up. Page 127/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4. Client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. Mobile Display Driver IC 5. Link_active goes high after the host brings the link out of hibernation. 6. After link wake-up, client_wakeup signal and the VWAKE_EN register are cleared automatically. Page 128/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 3.4.10. MDDI Operation In MDDI, six operation modes are available. The following table describes six modes. Mobile Display Driver IC Table 62. MDDI Opreration State STATE OSC booster Circuit INIT_ HIBER OFF Disabled WAIT OFF Disabled NORMAL ON Enabled SLEEP OFF Disabled HIBER ON Enabled STOP OFF Disabled Internal Logic status Display OFF /Internal Logic ON MDDI Link hibernation Display OFF /Internal Logic ON MDDI Link in SYNC Display ON /Internal Logic ON MDDI Link in SYNC Display OFF /Internal Logic ON MDDI Link in SYNC Display ON /Internal Logic ON MDDI Link hibernation Display OFF /Internal Logic ON MDDI Link OFF MDDI I/O Wake-up by Hibernation driver ON Host – Initiated standard driver ON - standard driver ON - standard driver ON - Hibernation driver ON Host – Initiated Client –Initiated (VSYNC) Driver All OFF RESET INIT_HIBER: Initial status when external power is connected to the IC. In this state, internal oscillator is OFF, and MDDI link is in hibernation state. As no command or signal is applied to the IC except RESET input and booster circuit is OFF, and internal logic is ON. WAIT: After the wake-up sequence, the IC is in WAIT state. MDDI link is in SYNC, and internal logic is ON, and booster is still OFF because no other register access or video stream packet is transferred to the IC. NORMAL: MDDI link, booster circuit, and internal logic circuit are ON. Register access or Video data transfer is available in NORMAL state. HIBER: When no more video data update is needed, MDDI link is in hibernation so that interface power can be reduced. Internal booster & logic circuits are still operating. MDDI link wakeup will be accomplished when VSYNC wakeup register is set before hibernation SLEEP: This state is set by register access. Booster is OFF, but MDDI link is ON. MDDI link and internal logic have to be in SYNC because the IC must receive commands for power save or normal operation STOP: STOP state is set by MDDI_SLP register access (E0h). In this state, MDDI link, internal oscillator, Boosters are all OFF. But internal logic is still ON. To release STOP state, input reset signal. After reset, status is INIT_HIBER state. Page 129/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC MDDI Link wake-up! Figure 101. Operating state in MDDI mode *note : Deep Standby Mode -> MDDI mode enters “STOP” mode and Logic Power is Off. Page 130/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC CHAPTER 4 FUNCTIONAL DESCRIPTION 4.1 Power 4.2 Source 4.3 Panel Control 4.4 Oscillator –System Clock Generator 4.5 Display Data RAM 4.6 Reset 4.7 Sleep Out 4.8 NVM Memory Control 4.9 8-color Display Mode 4.10 Instruction Setup Flow 4.11 Tearing Effect Output Line 4.12 MIE Function Page 131/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4 FUNCTIONAL DESCRIPTION Mobile Display Driver IC 4.1. POWER 4.1.1. Power ON / OFF Sequence VDD3 and VCI can be applied in any order. VDD3 and VCI can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VCI and VDD3 must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDD3 or VCI can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note. There will be damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between the end of Power On Sequence and before the reception of Sleep Out command. Same is the case between receiving Sleep In command and Power Off Sequence. If RESX line is not held stable by host during Power On Sequence , it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise, function is not guaranteed. The power on/off sequence is illustrated in the next pages. Page 132/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.1.1. Case-1 RESX line is held High or Unstable by Host at Power On Mobile Display Driver IC If RESX line is held high or unstable by the host during Power On, then a Hardware Reset must be applied after both VCI and VDD3 have been applied – otherwise, correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. pwRESX1 is applied to RESX falling in the Sleep Out Mode pwRESX2 is applied to RESX falling in the Sleep In Mode Note : Unless otherwise specified , timings herein show cross point at 50 % of signal / power level . Figure 102. RESX line is held high or unstable by host at power on Page 133/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.1.2. Case-2 RESX line is held Low by Host at Power On Mobile Display Driver IC If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10µsec after both VCI and VDD3 have been applied Figure 103. RESX line is held low by host at power on Page 134/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.2. Abrupt Power Off Mobile Display Driver IC The abrupt power-off represents a situation where, for e.g., a battery is removed without the expected power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an abrupt power-off, the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until “Power-On Sequence” powers it up. Figure 104. Status of Driver IC at abrupt power-off Page 135/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.3. Power Levels (APON=1) Mobile Display Driver IC S6D05A0 supports 6 types of power-consumption modes. Each mode is described as follows: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out In this mode, the display is able to show maximum 16,777,216 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out In this mode, part of the display is used with maximum 16,777,216 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out In this mode, the full display area is used but with 8 colors, 4. Partial Mode On, Idle Mode On, Sleep Out In this mode, part of the display is used but with 8 colors 5. Sleep In Mode In this mode, the booster, internal oscillator and panel driver circuit are stopped. Only the MPU interface and memory work VDD3 power supply. Contents of the memory are safe. 6. Power Off Mode. In this mode, both VCI and VDD3 are removed Note. Transition between modes 1-5 is controllable by MPU commands. Mode 6 is entered only when both Power supplies are removed. Page 136/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.4. Power Flow Chart for Different Power Modes (APON=1) Mobile Display Driver IC Normal display mode = NORON Partial mode on = PTLON Idle mode off = IDMOFF Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN NORON PTLON Sleep out Normal display mode on Idle mode off SLPIN SLPOUT Power on sequence HW reset SW reset Sleep in Normal display mode on Idle mode off NORON PTLON IDMON IDMOFF IDMON IDMOFF Sleep out Normal display mode on Idle mode on SLPIN SLPOUT Sleep in Normal display mode on Idle mode on Sleep out Partial mode on Idle mode off IDMON IDMOFF PTLON NORON Sleep out Partial mode on Idle mode on SLPIN SLPOUT Sleep in Partial mode on Idle mode off IDMON IDMOFF SLPIN SLPOUT Sleep in Partial mode on Idle mode on PTLON NORON Sleep out Sleep in Figure 105. Power-on flowchart for various power modes Note1. There is no abnormal visual effect when there is a change from one power mode to another power mode. There is no limitation, which is not specified by this spec, when there is a change from one power mode to another power mode Page 137/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.5. Power Supply Mobile Display Driver IC The following figure shows a configuration of the voltage generation circuit of S6D05A0. The booster circuit consists of booster circuits 1 to 3. Booster circuit1 doubles input voltage supplied from VCI1 for AVDD1, AVDD2 level. Booster circuit2 makes 2.5, 3 or 3.5 times AVDD1 level for VGH level, and makes -1.5, -2 or -2.5 times AVDD1 level for VGL level. Booster circuit3 reverses the VCI1 level with respect to VSS to generate VCL level. These Booster circuits generate power supplies AVDD1, AVDD2, VGH, VGL, and VCL. AVDD2 is used in power of source block. Reference voltages such as GVDD, VCOMH and VCOML are generated with VREF from the voltage adjustment circuit. Connect VCOM to the TFT panel. Figure 106. Configuration of the internal power-supply circuit Note. Use the 1uF capacitor. Schottky diode between VGL and VSS is positively necessary for making the circuitry latch-up free. The Capacitor between VREF and VSS may be used in the case of occurring fluctuation in VCOM swing level. Page 138/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.6. Pattern Diagrams for Voltage Setting Mobile Display Driver IC The following figure shows a pattern diagram for the voltage setting and an example of waveforms Figure 107. Power-Up pattern diagram Page 139/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.7. Set up Flow of Power Mobile Display Driver IC Apply the power in a sequential way as shown in the following figure. The settling time of the oscillation circuit, booster1/2/3 circuits, and operational amplifier depends on the external resistance or capacitance value. < Power on flow: APON=0> < Power on flow: APON =1> External Power On Sequence 1ms External Power On Sequence More than 5 ms : Settiling time of register default Value Loading More than 10ms :Settling time of the oscillator Reset PWRCTL (RF3H) Sleep Out (R11H) PWRCTL (RF3H) PWRCTL (RF3H) PWRCTL (RF3H) VCMCTL (RF4H) APON=0 Bits for VCI1 setting* VCI1_EN=1,VC[ 0000] Bits for power setting BT[010], DC11-10, DC21-20, DC31-30 GVD6-0 VCOMG, VCM6-0 , VML6-0 PWRCTL (RF3H) APON=1 Sleep- Out (R11H) Internal Oscillator Starts Booster Starts Change Offset Voltage for LCD Panel VCMCTL2 (RF3/4H) IPVCM, IPVML, IPGVD Display Whole blank screen for2 frames At least 10ms : Settling time of the VCI1 At least 10ms : Settling time of the AVDD1 At least 10ms : Settling time of the AVDD2 At least 10ms : Settling time of the VGH At least 10ms : Settling time of the VGL At least 20ms : Settling time of the VCL At least 30ms : Settling time of the internal OP- AMPs SRCCTL (RF5H) PWRCTL (RF3H) PWRCTL ( RF3H) PWRCTL (RF3H) PWRCTL (RF3H) PWRCTL (RF3H) PWRCTL ( RF3H) SAP3-0 Bits for step- up circuit1 operation start PON=1 Bits for step- up circuit1 operation start PON0=1 Bits for step- up circuit 2 operation start PON1=1 VC[ 0010] Bits for step- up circuit 2 operation start PON2=1 Display Memory Contents in accordance with the current command table settings Sleep Out mode Bits for step- up circuit3 operation start PON3=1 BT[2:0],VC[3:0 ] user setting Bits for amplifier circuit operation start AON=1 Sleep Out mode Figure 108. Setup flow of power Note. The VCI1 voltage level is set to the user setting value when a PON3 value is high for latch-up free sequence When PON3 = 0 : VCI1 = 2.07V When PON3 = 1 : VCI1 = User setting value (VC3-0) Power on flow (APON=0): register setting sequence Power on flow (APON=1): auto power sequence. Page 140/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.8. Deep-Standby Sequence Mobile Display Driver IC Figure 109. Deep-Standby Sequence Page 141/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.9. Discharge Status of Power Block Following Table describes The Discharge status of power block Table 63. Discharge Status of Power Block H/W RESET VCOM VSS SOURCE VSS GATE VSS VREF Floating GVDD VSS VCOMH VSS VCOML VSS VCI1 VSS AVDD1,2 VSS VCL VSS VGH VSS VGL VSS S/W RESET VSS VSS VSS Floating VSS VSS VSS VSS VSS VSS VSS VSS Mobile Display Driver IC DSTB VSS VSS VSS Floating VSS VSS VSS VSS VSS VSS VSS VSS Page 142/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.1.10. Voltage Regulation Function Mobile Display Driver IC The S6D05A0 has an internal voltage regulator. By the use of this function, unexpected damages on internal logic circuit can be avoided. Furthermore, low power consumption can also be obtained. Detailed function description and applicable configuration are described in the following diagram. Figure 110. Voltage regulation function Page 143/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2. SOURCE 4.2.1. Source Driver Mobile Display Driver IC The liquid crystal display source driver circuit consists of 1080 drivers (S1 to S1080). Display pattern data is latched when 1080 Channel data has arrived. Then the latched data enables the source drivers to output to expected voltage level. When less than 1080 sources are required, the unused source outputs should be left open. 4.2.2. Gamma Adjustment Function S6D05A0 provides the gamma adjustment function to display 16,777,216 colors simultaneously for each R/G/B color. The gamma adjustment executed by the high/ mid/ low level adjustment registers determines 13 grayscale reference levels. Furthermore, since the high-level adjustment register, mid-level adjustment register and the low-level adjustment register have the positive polarities and negative polarities, you can adjust them to match LCD panel and a gamma for each R/G/B color, respectively.. Figure 111. Block diagram of gamma adjustment function Page 144/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.3. Gamma Curve 4.2.3.1. Gamma Curve Gamma Curve, applies the function. y = x 2.2 Mobile Display Driver IC Figure 112. Gamma y = x 2.2 Page 145/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.4. Structure of Grayscale Amplifier Mobile Display Driver IC The structure of grayscale amplifier is shown as below. The 13 voltage levels (VIN0-VIN12) between GVDD and VGS are determined by the reference adjustment register, the amplitude adjustment resister, the x-axis symmetric adjustment register, the micro-adjustment register and the gray-shift register. Each level is split into 256 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 256 voltage levels ranging from V0 to V255. Figure 113. Structure of gray scale amplifier Page 146/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 114. Structure of resistor ladder network 1. Page 147/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC VINP0 50R 0.5R X 20 Positive Polarity VINP0 VRUP VINP 0 PKP0 [5:0] VRC0 ~ VRC63 64 to1 SEL VINP 1 VRC0~ VRC19 PKP1[5:0] VRC 5 ~ VRC68 64 to1 SEL VINP 2 PKP2[5:0] VRC 8 ~ VRC71 64 to1 SEL VINP 3 PKP3[5:0] 1R x VRC20~ VRC219 200 VRC31 ~ VRC94 64 to1 SEL VINP 4 PKP4[5:0] VRC44 ~ VRC107 64 to1 SEL VINP 5 PKP5[5:0] VRC 50 ~ VRC113 64 to1 SEL VINP 6 PKP6[5:0] VRC130 ~ VRC67 64 to1 SEL VINP 7 PKP7[5:0] VRC156 ~ 64 to1 SEL VRC93 VINP 8 PKP8[5:0] 0.5R x 20 VRC220~ VRC238 VRC225 64 to1 ~ SEL VRC162 VINP 9 PKP7[5:0] VRC234 ~ 64to1 SEL VRC171 VINP10 PKP8[5:0] 50R VINP12 VRDN VRC238 ~ VRC175 64to1 SEL VINP12 VINP11 VINP 12 VINN0 50R 0.5R X 20 Negative Polarity VINN0 VRUP VINN0 PKN0 [5:0] VRC0 ~ VRC63 64 to1 SEL VINN1 VRC0~ VRC19 PKN1[5:0] VRC 5 ~ VRC68 64 to1 SEL VINN2 PKN2[5:0] VRC 8 ~ VRC71 64 to1 SEL VINN3 PKN3[5:0] 1R x VRC20~ VRC219 200 VRC31 ~ VRC94 64 to1 SEL VINN4 PKN4[5:0] VRC44 ~ VRC107 64 to1 SEL VINN5 PKN5[5:0] VRC 50 ~ VRC113 64 to1 SEL VINN6 PKN6[5:0] VRC130 ~ VRC67 64 to1 SEL VINN7 PKN7[5:0] VRC156 ~ 64 to1 SEL VRC93 VINN8 PKN8[5:0] 0.5R x 20 VRC220~ VRC238 VRC225 64 to1 ~ SEL VRC162 VINN9 PKN7[5:0] VRC234 ~ 64to1 SEL VRC171 VINN10 PKN8[5:0] 50R VINP12 VRDN VRC238 ~ VRC175 64to1 SEL VINN12 VINN11 VINN 12 Figure 115. Structure of resistor ladder network 2. Page 148/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.5. Gamma Adjustment Register Mobile Display Driver IC This block has registers to set up the grayscale voltage according to the gamma specification of the LCD panel. These registers can independently set up the positive/negative polarities. There are 4 types of register groups to adjust the amplitude on the grayscale characteristics of the grayscale voltage, and R/G/B gamma adjustment registers are separated. The following figures indicate the operation of each adjustment registers. Figure 116. The operation of adjusting register 4.2.5.1. Reference Adjustment Register The Reference adjustment register is used to adjust the reference of the grayscale voltage. To accomplish the adjustment, it controls the VINP12/VINN12 voltage level by 64 to 1 selector towards the 64-leveled reference voltage generated from the resistor ladder between GVDD and VGS. 4.2.5.2. Amplitude Adjustment Register The Amplitude adjustment register is to adjust the amplitude of the grayscale voltage. To accomplish the adjustment, it controls the VINP0/VINN0 voltage level by 64 to 1 selector towards the 64-leveled reference voltage generated from the resistor ladder between GVDD and VGS. 4.2.5.3. Micro Adjustment Register The Micro adjustment register is employed to make subtle adjustment to the grayscale voltage level. To accomplish the adjustment, it controls each reference voltage level by the 64 to 1 selector towards the 64-leveled reference voltage generated from the resistor ladder. Also, there is an independent register on the positive/negative polarities as well as other adjustment registers. 4.2.5.4. Gray Shirt Register The Gray shift register is employed to make subtle adjustment to the grayscale voltage level. To accomplish the adjustment, it controls 4 point reference voltage level by the switch. Also, there is an independent register on the positive/negative polarities as well as other adjustment registers Page 149/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.5.5. X-axis Symmetric Adjustment Register Mobile Display Driver IC The X-axis symmetric adjustment register is to adjust X-axis symmetric of the grayscale voltage. This register can be detailedly explained with NGF register selection. 1st case; when XSG=0 and NGF=0, Vp+Vn=Vp<0>+Vn<0> and gamma symmetric axis is (Vp<0>+Vn<0>)/2. 2nd case; when XSG=0 and NGF=1, negative gamma voltage can be changed using negative gamma register value and symmetric axis will be changed according to negative gamma voltage. 3rd case; when XSG=1 and NGF=0, Vp=Vn<|255-N|>. 4th case; when XSG=1 and NGF=1, Vp+Vn Vp<0>+Vn<0> but can have similar value in some degree using both positive and negative gamma registers. Table 64. Description of gamma adjustment register Register Positive polarity Negative polarity Set-up contents Reference adjustment Amplitude adjustment OSP[5:0] RFP[5:0] OSN[5:0] RFN[5:0] The voltage of VBOTTOM is selected by the 64 to 1 selector The voltage of VTOP is selected by the 64 to 1 selector X-axis symmetric adjustment Micro adjustment XSG GLP[1:0] GLN[1:0] PKP0[5:0] PKN0[5:0] PKP1[5:0] PKN1[5:0] PKP2[5:0] PKN2[5:0] PKP3[5:0] PKN3[5:0] PKP4[5:0] PKN4[5:0] PKP5[5:0] PKN5[5:0] PKP6[5:0] PKN6[5:0] PKP7[5:0] PKN7[5:0] PKP8[5:0] PKN8[5:0] The voltage of VINP12/VINN12 is selected by the 2 to 1 selector The voltage of VINP0/VINN0 is selected by the 2 to 1 selector The voltage of grayscale number from 1 to 254 is adjusted by the variable resistor The voltage of grayscale number 1 is selected by the 64 to 1 selector The voltage of grayscale number 5 is selected by the 64 to 1 selector The voltage of grayscale number 11 is selected by the 64 to 1 selector The voltage of grayscale number 55 is selected by the 64 to 1 selector The voltage of grayscale number 95 is selected by the 64 to 1 selector The voltage of grayscale number VC (middle voltage between v<127> and V<128>) is selected by the 64 to 1 selector The voltage of grayscale number 160 is selected by the 64 to 1 selector The voltage of grayscale number 200 is selected by the 64 to 1 selector The voltage of grayscale number 244 is selected by the 64 to 1 selector Page 150/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Register Positive polarity Negative polarity Set-up contents PKP9[5:0] PKN9[5:0] The voltage of grayscale number 250 is selected by the 64 to 1 selector PKP10[5:0] PKN10[5:0] The voltage of grayscale number 254 is selected by the 64 to 1 selector The register is used to select one among the grayscale numbers GSRP0[3:0] GSRN0[3:0] 4 to 7 The register is used to select one among the grayscale numbers GSRP1[3:0] GSRN1[3:0] 54 to 57 The register is used to select one among the grayscale numbers GSRP2[3:0] GSRN2[3:0] 199 to 202 The register is used to select one among the grayscale numbers GSRP3[3:0] GSRN3[3:0] 249 to 252 Page 151/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.6. Resistor Ladder Network / Selector Mobile Display Driver IC This block outputs the reference voltage of the grayscale voltage. There are three ladder resistors including the 64 to 1 selector selecting voltage generated by the ladder resistance voltage. Also, there are pins that connect to the external volume resistor. In addition, it allows compensating the dispersion of length between one panel and another. 4.2.6.1. Resistor Ladder Network 1 / Selector There are 2 adjustments that are for the reference / amplitude adjustment (RFP(N)/ OSP(N)) and micro adjustment (PKP(N)). The voltage level is set by the reference / amplitude adjustment registers and micro adjustments as below. Page 152/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 65. Amplitude adjustment Register value RFP(N) [5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Selected voltage VTOP VRH0 VRH1 VRH2 VRH3 VRH4 VRH5 VRH6 VRH7 VRH8 VRH9 VRH10 VRH11 VRH12 VRH13 VRH14 VRH15 VRH16 VRH17 VRH18 VRH19 VRH20 VRH21 VRH22 VRH23 VRH24 VRH25 VRH26 VRH27 VRH28 VRH29 VRH30 VRH31 VRH32 VRH33 VRH34 VRH35 Page 153/389 Mobile Display Driver IC Formula of VTOP (320R/320R) * (GVDD-VGS) + VGS (318R/320R) * (GVDD-VGS) + VGS (316R/320R) * (GVDD-VGS) + VGS (314R/320R) * (GVDD-VGS) + VGS (312R/320R) * (GVDD-VGS) + VGS (310R/320R) * (GVDD-VGS) + VGS (308R/320R) * (GVDD-VGS) + VGS (306R/320R) * (GVDD-VGS) + VGS (304R/320R) * (GVDD-VGS) + VGS (302R/320R) * (GVDD-VGS) + VGS (300R/320R) * (GVDD-VGS) + VGS (298R/320R) * (GVDD-VGS) + VGS (296R/320R) * (GVDD-VGS) + VGS (294R/320R) * (GVDD-VGS) + VGS (292R/320R) * (GVDD-VGS) + VGS (290R/320R) * (GVDD-VGS) + VGS (288R/320R) * (GVDD-VGS) + VGS (286R/320R) * (GVDD-VGS) + VGS (284R/320R) * (GVDD-VGS) + VGS (282R/320R) * (GVDD-VGS) + VGS (280R/320R) * (GVDD-VGS) + VGS (278R/320R) * (GVDD-VGS) + VGS (276R/320R) * (GVDD-VGS) + VGS (274R/320R) * (GVDD-VGS) + VGS (272R/320R) * (GVDD-VGS) + VGS (270R/320R) * (GVDD-VGS) + VGS (268R/320R) * (GVDD-VGS) + VGS (266R/320R) * (GVDD-VGS) + VGS (264R/320R) * (GVDD-VGS) + VGS (262R/320R) * (GVDD-VGS) + VGS (260R/320R) * (GVDD-VGS) + VGS (258R/320R) * (GVDD-VGS) + VGS (256R/320R) * (GVDD-VGS) + VGS (254R/320R) * (GVDD-VGS) + VGS (252R/320R) * (GVDD-VGS) + VGS (250R/320R) * (GVDD-VGS) + VGS 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 66. Amplitude adjustment(continued) Register value RFP(N) [5:0] Selected voltage VTOP 100100 VRH36 100101 VRH37 100110 VRH38 100111 VRH39 101000 VRH40 101001 VRH41 101010 VRH42 101011 VRH43 101100 VRH44 101101 VRH45 101110 VRH46 101111 VRH47 110000 VRH48 110001 VRH49 110010 VRH50 110011 VRH51 110100 VRH52 110101 VRH53 110110 VRH54 110111 VRH55 111000 VRH56 111001 VRH57 111010 VRH58 111011 VRH59 111100 VRH60 111101 VRH61 111110 VRH62 111111 VRH63 Mobile Display Driver IC Formula of VTOP (248R/320R) * (GVDD-VGS) + VGS (246R/320R) * (GVDD-VGS) + VGS (244R/320R) * (GVDD-VGS) + VGS (242R/320R) * (GVDD-VGS) + VGS (240R/320R) * (GVDD-VGS) + VGS (238R/320R) * (GVDD-VGS) + VGS (236R/320R) * (GVDD-VGS) + VGS (234R/320R) * (GVDD-VGS) + VGS (232R/320R) * (GVDD-VGS) + VGS (230R/320R) * (GVDD-VGS) + VGS (228R/320R) * (GVDD-VGS) + VGS (226R/320R) * (GVDD-VGS) + VGS (224R/320R) * (GVDD-VGS) + VGS (222R/320R) * (GVDD-VGS) + VGS (220R/320R) * (GVDD-VGS) + VGS (218R/320R) * (GVDD-VGS) + VGS (216R/320R) * (GVDD-VGS) + VGS (214R/320R) * (GVDD-VGS) + VGS (212R/320R) * (GVDD-VGS) + VGS (210R/320R) * (GVDD-VGS) + VGS (208R/320R) * (GVDD-VGS) + VGS (206R/320R) * (GVDD-VGS) + VGS (204R/320R) * (GVDD-VGS) + VGS (202R/320R) * (GVDD-VGS) + VGS (200R/320R) * (GVDD-VGS) + VGS (198R/320R) * (GVDD-VGS) + VGS (196R/320R) * (GVDD-VGS) + VGS (194R/320R) * (GVDD-VGS) + VGS Page 154/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 67. Reference adjustment Register value OSP(N) [5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Selected voltage VBOTTOM VRL0 VRL1 VRL2 VRL3 VRL4 VRL5 VRL6 VRL7 VRL8 VRL9 VRL10 VRL11 VRL12 VRL13 VRL14 VRL15 VRL16 VRL17 VRL18 VRL19 VRL20 VRL21 VRL22 VRL23 VRL24 VRL25 VRL26 VRL27 VRL28 VRL29 VRL30 VRL31 VRL32 VRL33 VRL34 VRL35 Page 155/389 Mobile Display Driver IC Formula of VBOTTOM (16R/320R) * (GVDD-VGS) + VGS (18R/320R) * (GVDD-VGS) + VGS (20R/320R) * (GVDD-VGS) + VGS (22R/320R) * (GVDD-VGS) + VGS (24R/320R) * (GVDD-VGS) + VGS (26R/320R) * (GVDD-VGS) + VGS (28R/320R) * (GVDD-VGS) + VGS (30R/320R) * (GVDD-VGS) + VGS (32R/320R) * (GVDD-VGS) + VGS (34R/320R) * (GVDD-VGS) + VGS (36R/320R) * (GVDD-VGS) + VGS (38R/320R) * (GVDD-VGS) + VGS (40R/320R) * (GVDD-VGS) + VGS (42R/320R) * (GVDD-VGS) + VGS (44R/320R) * (GVDD-VGS) + VGS (46R/320R) * (GVDD-VGS) + VGS (48R/320R) * (GVDD-VGS) + VGS (50R/320R) * (GVDD-VGS) + VGS (52R/320R) * (GVDD-VGS) + VGS (54R/320R) * (GVDD-VGS) + VGS (56R/320R) * (GVDD-VGS) + VGS (58R/320R) * (GVDD-VGS) + VGS (60R/320R) * (GVDD-VGS) + VGS (62R/320R) * (GVDD-VGS) + VGS (64R/320R) * (GVDD-VGS) + VGS (66R/320R) * (GVDD-VGS) + VGS (68R/320R) * (GVDD-VGS) + VGS (70R/320R) * (GVDD-VGS) + VGS (72R/320R) * (GVDD-VGS) + VGS (74R/320R) * (GVDD-VGS) + VGS (76R/320R) * (GVDD-VGS) + VGS (78R/320R) * (GVDD-VGS) + VGS (80R/320R) * (GVDD-VGS) + VGS (82R/320R) * (GVDD-VGS) + VGS (84R/320R) * (GVDD-VGS) + VGS (86R/320R) * (GVDD-VGS) + VGS 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 68. Reference adjustment(continued) Register value OSP(N) [5:0] Selected voltage VBOTTOM 100100 VRL36 100101 VRL37 100110 VRL38 100111 VRL39 101000 VRL40 101001 VRL41 101010 VRL42 101011 VRL43 101100 VRL44 101101 VRL45 101110 VRL46 101111 VRL47 110000 VRL48 110001 VRL49 110010 VRL50 110011 VRL51 110100 VRL52 110101 VRL53 110110 VRL54 110111 VRL55 111000 VRL56 111001 VRL57 111010 VRL58 111011 VRL59 111100 VRL60 111101 VRL61 111110 VRL62 111111 VRL63 Mobile Display Driver IC Formula of VBOTTOM (88R/320R) * (GVDD-VGS) + VGS (90R/320R) * (GVDD-VGS) + VGS (92R/320R) * (GVDD-VGS) + VGS (94R/320R) * (GVDD-VGS) + VGS (96R/320R) * (GVDD-VGS) + VGS (98R/320R) * (GVDD-VGS) + VGS (100R/320R) * (GVDD-VGS) + VGS (102R/320R) * (GVDD-VGS) + VGS (104R/320R) * (GVDD-VGS) + VGS (106R/320R) * (GVDD-VGS) + VGS (108R/320R) * (GVDD-VGS) + VGS (110R/320R) * (GVDD-VGS) + VGS (112R/320R) * (GVDD-VGS) + VGS (114R/320R) * (GVDD-VGS) + VGS (116R/320R) * (GVDD-VGS) + VGS (118R/320R) * (GVDD-VGS) + VGS (120R/320R) * (GVDD-VGS) + VGS (122R/320R) * (GVDD-VGS) + VGS (124R/320R) * (GVDD-VGS) + VGS (126R/320R) * (GVDD-VGS) + VGS (128R/320R) * (GVDD-VGS) + VGS (130R/320R) * (GVDD-VGS) + VGS (132R/320R) * (GVDD-VGS) + VGS (134R/320R) * (GVDD-VGS) + VGS (136R/320R) * (GVDD-VGS) + VGS (138R/320R) * (GVDD-VGS) + VGS (140R/320R) * (GVDD-VGS) + VGS (142R/320R) * (GVDD-VGS) + VGS Page 156/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.2.6.2. Resistor Ladder Network 2 / Selector Mobile Display Driver IC In the 64-to-1 selector, the voltage level must be selected by the given ladder resistance and the micro-adjustment register and output the nine types of the reference voltage, VIN1 to VIN11. Following figure explains the relationship between the micro-adjustment register and the selected voltage Table 69. Relationship between micro-adjustment register and selected voltage Register value Selected voltage PKP(N) [5:0] VINP (N)1 VINP (N)2 VINP (N)3 VINP (N)4 VINP (N)5 VINP (N)6 VINP (N)7 VINP (N)8 VINP (N)9 000000 VRC0 VRC5 VRC8 VRC41 VRC59 VRC71 VRC146 VRC168 VRC215 000001 VRC1 VRC6 VRC9 VRC42 VRC60 VRC72 VRC145 VRC167 VRC214 000010 VRC2 VRC7 VRC10 VRC43 VRC61 VRC73 VRC144 VRC166 VRC213 000011 VRC3 VRC8 VRC11 VRC44 VRC62 VRC74 VRC143 VRC165 VRC212 000100 VRC4 VRC9 VRC12 VRC45 VRC63 VRC75 VRC142 VRC164 VRC211 000101 VRC5 VRC10 VRC13 VRC46 VRC64 VRC76 VRC141 VRC163 VRC210 000110 VRC6 VRC11 VRC14 VRC47 VRC65 VRC77 VRC140 VRC162 VRC209 000111 VRC7 VRC12 VRC15 VRC48 VRC66 VRC78 VRC139 VRC161 VRC208 001000 VRC8 VRC13 VRC16 VRC49 VRC67 VRC79 VRC138 VRC160 VRC207 001001 VRC9 VRC14 VRC17 VRC50 VRC68 VRC80 VRC137 VRC159 VRC206 001010 VRC10 VRC15 VRC18 VRC51 VRC69 VRC81 VRC136 VRC158 VRC205 001011 VRC11 VRC16 VRC19 VRC52 VRC70 VRC82 VRC135 VRC157 VRC204 001100 VRC12 VRC17 VRC20 VRC53 VRC71 VRC83 VRC134 VRC156 VRC203 001101 VRC13 VRC18 VRC21 VRC54 VRC72 VRC84 VRC133 VRC155 VRC202 001110 VRC14 VRC19 VRC22 VRC55 VRC73 VRC85 VRC132 VRC154 VRC201 001111 VRC15 VRC20 VRC23 VRC56 VRC74 VRC86 VRC131 VRC153 VRC200 010000 VRC16 VRC21 VRC24 VRC57 VRC75 VRC87 VRC130 VRC152 VRC199 010001 VRC17 VRC22 VRC25 VRC58 VRC76 VRC88 VRC129 VRC151 VRC198 010010 VRC18 VRC23 VRC26 VRC59 VRC77 VRC89 VRC128 VRC150 VRC197 010011 VRC19 VRC24 VRC27 VRC60 VRC78 VRC90 VRC127 VRC149 VRC196 010100 VRC20 VRC25 VRC28 VRC61 VRC79 VRC91 VRC126 VRC148 VRC195 010101 VRC21 VRC26 VRC29 VRC62 VRC80 VRC92 VRC125 VRC147 VRC194 010110 VRC22 VRC27 VRC30 VRC63 VRC81 VRC93 VRC124 VRC146 VRC193 010111 VRC23 VRC28 VRC31 VRC64 VRC82 VRC94 VRC123 VRC145 VRC192 011000 VRC24 VRC29 VRC32 VRC65 VRC83 VRC95 VRC122 VRC144 VRC191 011001 VRC25 VRC30 VRC33 VRC66 VRC84 VRC96 VRC121 VRC143 VRC190 011010 VRC26 VRC31 VRC34 VRC67 VRC85 VRC97 VRC120 VRC142 VRC189 VINP (N)10 VRC234 VRC233 VRC232 VRC231 VRC230 VRC229 VRC228 VRC227 VRC226 VRC225 VRC224 VRC223 VRC222 VRC221 VRC220 VRC219 VRC218 VRC217 VRC216 VRC215 VRC214 VRC213 VRC212 VRC211 VRC210 VRC209 VRC208 VINP (N)11 VRC238 VRC237 VRC236 VRC235 VRC234 VRC233 VRC232 VRC231 VRC230 VRC229 VRC228 VRC227 VRC226 VRC225 VRC224 VRC223 VRC222 VRC221 VRC220 VRC219 VRC218 VRC217 VRC216 VRC215 VRC214 VRC213 VRC212 Page 157/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 70. Relationship between micro-adjustment register and selected voltage(continued) Register value Selected voltage PKP(N) [5:0] VINP (N)1 VINP (N)2 VINP (N)3 VINP (N)4 VINP (N)5 VINP (N)6 VINP (N)7 VINP (N)8 VINP (N)9 VINP (N)10 VINP (N)11 011011 VRC27 VRC32 VRC35 VRC68 VRC86 VRC98 VRC119 VRC141 VRC188 VRC207 VRC211 011100 VRC28 VRC33 VRC36 VRC69 VRC87 VRC99 VRC118 VRC140 VRC187 VRC206 VRC210 011101 VRC29 VRC34 VRC37 VRC70 VRC88 VRC100 VRC117 VRC139 VRC186 VRC205 VRC209 011110 VRC30 VRC35 VRC38 VRC71 VRC89 VRC101 VRC116 VRC138 VRC185 VRC204 VRC208 011111 VRC31 VRC36 VRC39 VRC72 VRC90 VRC102 VRC115 VRC137 VRC184 VRC203 VRC207 100000 VRC32 VRC37 VRC40 VRC73 VRC91 VRC103 VRC114 VRC136 VRC183 VRC202 VRC206 100001 VRC33 VRC38 VRC41 VRC74 VRC92 VRC104 VRC113 VRC135 VRC182 VRC201 VRC205 100010 VRC34 VRC39 VRC42 VRC75 VRC93 VRC105 VRC112 VRC134 VRC181 VRC200 VRC204 100011 VRC35 VRC40 VRC43 VRC76 VRC94 VRC106 VRC111 VRC133 VRC180 VRC199 VRC203 100100 VRC36 VRC41 VRC44 VRC77 VRC95 VRC107 VRC110 VRC132 VRC179 VRC198 VRC202 100101 VRC37 VRC42 VRC45 VRC78 VRC96 VRC108 VRC109 VRC131 VRC178 VRC197 VRC201 100110 VRC38 VRC43 VRC46 VRC79 VRC97 VRC109 VRC108 VRC130 VRC177 VRC196 VRC200 100111 VRC39 VRC44 VRC47 VRC80 VRC98 VRC110 VRC107 VRC129 VRC176 VRC195 VRC199 101000 VRC40 VRC45 VRC48 VRC81 VRC99 VRC111 VRC106 VRC128 VRC175 VRC194 VRC198 101001 VRC41 VRC46 VRC49 VRC82 VRC100 VRC112 VRC105 VRC127 VRC174 VRC193 VRC197 101010 VRC42 VRC47 VRC50 VRC83 VRC101 VRC113 VRC104 VRC126 VRC173 VRC192 VRC196 101011 VRC43 VRC48 VRC51 VRC84 VRC102 VRC114 VRC103 VRC125 VRC172 VRC191 VRC195 101100 VRC44 VRC49 VRC52 VRC85 VRC103 VRC115 VRC102 VRC124 VRC171 VRC190 VRC194 101101 VRC45 VRC50 VRC53 VRC86 VRC104 VRC116 VRC101 VRC123 VRC170 VRC189 VRC193 101110 VRC46 VRC51 VRC54 VRC87 VRC105 VRC117 VRC100 VRC122 VRC169 VRC188 VRC192 101111 VRC47 VRC52 VRC55 VRC88 VRC106 VRC118 VRC99 VRC121 VRC168 VRC187 VRC191 110000 VRC48 VRC53 VRC56 VRC89 VRC107 VRC119 VRC98 VRC120 VRC167 VRC186 VRC190 110001 VRC49 VRC54 VRC57 VRC90 VRC108 VRC120 VRC97 VRC119 VRC166 VRC185 VRC189 110010 VRC50 VRC55 VRC58 VRC91 VRC109 VRC121 VRC96 VRC118 VRC165 VRC184 VRC188 110011 VRC51 VRC56 VRC59 VRC92 VRC110 VRC122 VRC95 VRC117 VRC164 VRC183 VRC187 110100 VRC52 VRC57 VRC60 VRC93 VRC111 VRC123 VRC94 VRC116 VRC163 VRC182 VRC186 110101 VRC53 VRC58 VRC61 VRC94 VRC112 VRC124 VRC93 VRC115 VRC162 VRC181 VRC185 110110 VRC54 VRC59 VRC62 VRC95 VRC113 VRC125 VRC92 VRC114 VRC161 VRC180 VRC184 110111 VRC55 VRC60 VRC63 VRC96 VRC114 VRC126 VRC91 VRC113 VRC160 VRC179 VRC183 111000 VRC56 VRC61 VRC64 VRC97 VRC115 VRC127 VRC90 VRC112 VRC159 VRC178 VRC182 111001 VRC57 VRC62 VRC65 VRC98 VRC116 VRC128 VRC89 VRC111 VRC158 VRC177 VRC181 111010 VRC58 VRC63 VRC66 VRC99 VRC117 VRC129 VRC88 VRC110 VRC157 VRC176 VRC180 Page 158/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 71. Relationship between micro-adjustment register and selected voltage(continued) Register value Selected voltage PKP(N) [5:0] VINP (N)1 VINP (N)2 VINP (N)3 VINP (N)4 VINP (N)5 VINP (N)6 VINP (N)7 VINP (N)8 VINP (N)9 VINP (N)10 VINP (N)11 111011 VRC59 VRC64 VRC67 VRC100 VRC118 VRC130 VRC87 VRC109 VRC156 VRC175 VRC179 111100 VRC60 VRC65 VRC68 VRC101 VRC119 VRC131 VRC86 VRC108 VRC155 VRC174 VRC178 111101 VRC61 VRC66 VRC69 VRC102 VRC120 VRC132 VRC85 VRC107 VRC154 VRC173 VRC177 111110 VRC62 VRC67 VRC70 VRC103 VRC121 VRC133 VRC84 VRC106 VRC153 VRC172 VRC176 111111 VRC63 VRC68 VRC71 VRC104 VRC122 VRC134 VRC83 VRC105 VRC152 VRC171 VRC175 The grayscale levels are determined by the following formulas listed in the following equations. Negative gamma voltages are calculated with the same equation of positive gamma voltages, but the gray scale is symmetric, which means negative V<0> is equal to positive V<255>. Rt and Ra in the below equations are determined by GL[1:0] Registers as follows. GLP/N[1:0]=00, Rt = 220R, Ra=0 GLP/N [1:0]=01, Rt = 270R, Ra=50R GLP/N [1:0]=10, Rt = 270R, Ra=0 GLP/N [1:0]=11, Rt = 320R, Ra=50R Page 159/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 4.2.7. Grayscale Levels Table 72. Formulas for calculating gamma adjusting voltage (positive polarity) 1 Pads Formula Micro-adjusting register value Reference voltage VRC0 ((219.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000000” VRC1 ((219R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000001” VRC2 ((218.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000010” VRC3 ((218R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000011” VRC4 ((217.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000100” VRC5 ((217R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000101” VRC6 ((216.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000110” VRC7 ((216R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “000111” VRC8 ((215.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001000” VRC9 ((215R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001001” VRC10 ((214.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001010” VRC11 ((214R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001011” VRC12 ((213.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001100” VRC13 ((213R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001101” VRC14 ((212.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001110” VRC15 ((212R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “001111” VRC16 ((211.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010000” VRC17 VRC18 ((211R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((210.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010001” PKP0[5:0] = “010010” VNP1 VRC19 ((210R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010011” VRC20 ((209R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010100” VRC21 ((208R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010101” VRC22 ((207R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010110” VRC23 ((206R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “010111” VRC24 ((205R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “011000” VRC25 ((204R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “011001” VRC26 ((203R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “011010” VRC27 ((202R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “011011” VRC28 VRC29 VRC30 VRC31 VRC32 VRC33 VRC34 VRC35 ((201R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((200R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((199R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((198R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((197R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((196R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((195R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((194R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “011100” PKP0[5:0] = “011101” PKP0[5:0] = “011110” PKP0[5:0] = “011111” PKP0[5:0] = “100000” PKP0[5:0] = “100001” PKP0[5:0] = “100010” PKP0[5:0] = “100011” Page 160/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 73. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC36 ((193R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “100100” VRC37 ((192R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “100101” VRC38 ((191R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “100110” VRC39 ((190R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “100111” VRC40 ((189R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101000” VRC41 ((188R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101001” VRC42 ((187R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101010” VRC43 ((186R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101011” VRC44 ((185R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101100” VRC45 ((184R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101101” VRC46 ((183R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101110” VRC47 ((182R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “101111” VRC48 ((181R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110000” VRC49 VRC50 ((180R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((179R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110001” PKP0[5:0] = “110010” VINP1 VRC51 ((178R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110011” VRC52 ((177R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110100” VRC53 ((176R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110101” VRC54 ((175R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110110” VRC55 ((174R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “110111” VRC56 ((173R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111000” VRC57 ((172R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111001” VRC58 ((171R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111010” VRC59 ((170R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111011” VRC60 ((169R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111100” VRC61 ((168R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111101” VRC62 ((167R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111110” VRC63 ((166R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP0[5:0] = “111111” VRC5 ((217R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000000” VRC6 ((216.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000001” VRC7 ((216R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000010” VRC8 VRC9 ((215.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((215R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000011” PKP1[5:0] = “000100” VINP2 VRC10 ((214.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000101” VRC11 ((214R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000110” VRC12 ((213.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “000111” Page 161/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 74. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC13 ((213R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001000” VRC14 ((212.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001001” VRC15 ((212R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001010” VRC16 ((211.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001011” VRC17 ((211R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001100” VRC18 ((210.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001101” VRC19 ((210R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001110” VRC20 ((209R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “001111” VRC21 ((208R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010000” VRC22 ((207R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010001” VRC23 ((206R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010010” VRC24 ((205R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010011” VRC25 ((204R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010100” VRC26 ((203R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010101” VRC27 ((202R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010110” VRC28 ((201R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “010111” VRC29 ((200R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011000” VRC30 VRC31 ((199R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((198R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011001” PKP1[5:0] = “011010” VINP2 VRC32 ((197R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011011” VRC33 ((196R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011100” VRC34 ((195R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011101” VRC35 ((194R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011110” VRC36 ((193R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “011111” VRC37 ((192R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100000” VRC38 ((191R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100001” VRC39 ((190R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100010” VRC40 ((189R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100011” VRC41 ((188R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100100” VRC42 ((187R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100101” VRC43 ((186R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100110” VRC44 ((185R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “100111” VRC45 ((184R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101000” VRC46 ((183R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101001” VRC47 ((182R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101010” VRC48 ((181R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101011” Page 162/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 75. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC49 ((180R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101100” VRC50 ((179R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101101” VRC51 ((178R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101110” VRC52 ((177R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “101111” VRC53 ((176R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110000” VRC54 ((175R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110001” VRC55 ((174R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110010” VRC56 ((173R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110011” VRC57 ((172R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110100” VRC58 VRC59 ((171R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((170R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110101” PKP1[5:0] = “110110” VINP2 VRC60 ((169R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “110111” VRC61 ((168R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111000” VRC62 ((167R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111001” VRC63 ((166R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111010” VRC64 ((165R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111011” VRC65 ((164R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111100” VRC66 ((163R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111101” VRC67 ((162R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111110” VRC68 ((161R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP1[5:0] = “111111” VRC8 ((215.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000000” VRC9 ((215R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000001” VRC10 ((214.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000010” VRC11 ((214R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000011” VRC12 ((213.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000100” VRC13 ((213R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000101” VRC14 ((212.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000110” VRC15 VRC16 ((212R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((211.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “000111” PKP2[5:0] = “001000” VINP3 VRC17 ((211R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001001” VRC18 ((210.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001010” VRC19 ((210R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001011” VRC20 ((209R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001100” VRC21 ((208R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001101” VRC22 ((207R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001110” VRC23 ((206R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “001111” Page 163/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 76. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC24 ((205R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010000” VRC25 ((204R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010001” VRC26 ((203R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010010” VRC27 ((202R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010011” VRC28 ((201R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010100” VRC29 ((200R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010101” VRC30 ((199R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010110” VRC31 ((198R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “010111” VRC32 ((197R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011000” VRC33 ((196R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011001” VRC34 ((195R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011010” VRC35 ((194R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011011” VRC36 ((193R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011100” VRC37 ((192R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011101” VRC38 ((191R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011110” VRC39 ((190R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “011111” VRC40 ((189R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100000” VRC41 VRC42 ((188R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((187R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100001” PKP2[5:0] = “100010” VINP3 VRC43 ((186R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100011” VRC44 ((185R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100100” VRC45 ((184R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100101” VRC46 ((183R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100110” VRC47 ((182R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “100111” VRC48 ((181R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101000” VRC49 ((180R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101001” VRC50 ((179R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101010” VRC51 ((178R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101011” VRC52 ((177R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101100” VRC53 ((176R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101101” VRC54 ((175R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101110” VRC55 ((174R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “101111” VRC56 ((173R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110000” VRC57 ((172R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110001” VRC58 ((171R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110010” VRC59 ((170R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110011” Page 164/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 77. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC60 ((169R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110100” VRC61 ((168R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110101” VRC62 ((167R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110110” VRC63 ((166R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “110111” VRC64 ((165R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111000” VRC65 VRC66 ((164R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((163R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111001” PKP2[5:0] = “111010” VINP3 VRC67 ((162R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111011” VRC68 ((161R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111100” VRC69 ((160R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111101” VRC70 ((159R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111110” VRC71 ((158R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP2[5:0] = “111111” VRC41 ((188R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000000” VRC42 ((187R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000001” VRC43 ((186R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000010” VRC44 ((185R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000011” VRC45 ((184R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000100” VRC46 ((183R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000101” VRC47 ((182R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000110” VRC48 ((181R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “000111” VRC49 ((180R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001000” VRC50 ((179R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001001” VRC51 ((178R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001010” VRC52 VRC53 ((177R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((176R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001011” PKP3[5:0] = “001100” VINP4 VRC54 ((175R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001101” VRC55 ((174R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001110” VRC56 ((173R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “001111” VRC57 ((172R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010000” VRC58 ((171R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010001” VRC59 ((170R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010010” VRC60 ((169R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010011” VRC61 ((168R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010100” VRC62 ((167R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010101” VRC63 ((166R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010110” VRC64 ((165R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “010111” Page 165/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 78. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC65 ((164R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011000” VRC66 ((163R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011001” VRC67 ((162R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011010” VRC68 ((161R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011011” VRC69 ((160R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011100” VRC70 ((159R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011101” VRC71 ((158R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011110” VRC72 ((157R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “011111” VRC73 ((156R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100000” VRC74 ((155R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100001” VRC75 ((154R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100010” VRC76 ((153R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100011” VRC77 ((152R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100100” VRC78 ((151R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100101” VRC79 ((150R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100110” VRC80 ((149R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “100111” VRC81 ((148R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101000” VRC82 VRC83 ((147R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((146R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101001” PKP3[5:0] = “101010” VINP4 VRC84 ((145R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101011” VRC85 ((144R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101100” VRC86 ((143R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101101” VRC87 ((142R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101110” VRC88 ((141R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “101111” VRC89 ((140R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110000” VRC90 ((139R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110001” VRC91 ((138R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110010” VRC92 ((137R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110011” VRC93 ((136R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110100” VRC94 ((135R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110101” VRC95 ((134R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110110” VRC96 ((133R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “110111” VRC97 ((132R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111000” VRC98 ((131R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111001” VRC99 ((130R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111010” VRC100 ((129R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111011” Page 166/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 79. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC101 ((128R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111100” VRC102 VRC103 ((127R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((126R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111101” PKP3[5:0] = “111110” VINP4 VRC104 ((125R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP3[5:0] = “111111” VRC59 ((170R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000000” VRC60 ((169R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000001” VRC61 ((168R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000010” VRC62 ((167R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000011” VRC63 ((166R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000100” VRC64 ((165R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000101” VRC65 ((164R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000110” VRC66 ((163R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “000111” VRC67 ((162R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001000” VRC68 ((161R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001001” VRC69 ((160R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001010” VRC70 ((159R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001011” VRC71 ((158R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001100” VRC72 ((157R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001101” VRC73 ((156R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001110” VRC74 VRC75 ((155R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((154R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “001111” PKP4[5:0] = “010000” VINP5 VRC76 ((153R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010001” VRC77 ((152R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010010” VRC78 ((151R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010011” VRC79 ((150R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010100” VRC80 ((149R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010101” VRC81 ((148R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010110” VRC82 ((147R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “010111” VRC83 ((146R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011000” VRC84 ((145R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011001” VRC85 ((144R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011010” VRC86 ((143R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011011” VRC87 ((142R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011100” VRC88 ((141R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011101” VRC89 ((140R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011110” VRC90 ((139R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “011111” Page 167/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 80. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC91 ((138R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100000” VRC92 ((137R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100001” VRC93 ((136R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100010” VRC94 ((135R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100011” VRC95 ((134R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100100” VRC96 ((133R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100101” VRC97 ((132R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100110” VRC98 ((131R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “100111” VRC99 ((130R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101000” VRC100 ((129R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101001” VRC101 ((128R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101010” VRC102 ((127R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101011” VRC103 ((126R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101100” VRC104 ((125R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101101” VRC105 ((124R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101110” VRC106 VRC107 ((123R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((122R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “101111” PKP4[5:0] = “110000” VINP5 VRC108 ((121R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110001” VRC109 ((120R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110010” VRC110 ((119R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110011” VRC111 ((118R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110100” VRC112 ((117R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110101” VRC113 ((116R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110110” VRC114 ((115R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “110111” VRC115 ((114R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111000” VRC116 ((113R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111001” VRC117 ((112R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111010” VRC118 ((111R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111011” VRC119 ((110R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111100” VRC120 ((109R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111101” VRC121 ((108R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111110” VRC122 ((107R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP4[5:0] = “111111” VRC71 ((158R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000000” VRC72 VRC73 ((157R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((156R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000001” PKP5[5:0] = “000010” VINP6 VRC74 ((155R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000011” Page 168/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 81. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC75 ((154R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000100” VRC76 ((153R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000101” VRC77 ((152R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000110” VRC78 ((151R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “000111” VRC79 ((150R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001000” VRC80 ((149R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001001” VRC81 ((148R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001010” VRC82 ((147R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001011” VRC83 ((146R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001100” VRC84 ((145R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001101” VRC85 ((144R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001110” VRC86 ((143R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “001111” VRC87 ((142R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010000” VRC88 ((141R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010001” VRC89 ((140R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010010” VRC90 ((139R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010011” VRC91 ((138R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010100” VRC92 VRC93 ((137R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((136R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010101” PKP5[5:0] = “010110” VINP6 VRC94 ((135R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “010111” VRC95 ((134R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011000” VRC96 ((133R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011001” VRC97 ((132R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011010” VRC98 ((131R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011011” VRC99 ((130R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011100” VRC100 ((129R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011101” VRC101 ((128R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011110” VRC102 ((127R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “011111” VRC103 ((126R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100000” VRC104 ((125R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100001” VRC105 ((124R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100010” VRC106 ((123R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100011” VRC107 ((122R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100100” VRC108 ((121R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100101” VRC109 ((120R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100110” VRC110 ((119R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “100111” Page 169/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 82. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC111 ((118R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101000” VRC112 ((117R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101001” VRC113 ((116R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101010” VRC114 ((115R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101011” VRC115 ((114R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101100” VRC116 ((113R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101101” VRC117 ((112R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101110” VRC118 ((111R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “101111” VRC119 ((110R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110000” VRC120 ((109R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110001” VRC121 ((108R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110010” VRC122 VRC123 ((107R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((106R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110011” PKP5[5:0] = “110100” VINP6 VRC124 ((105R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110101” VRC125 ((104R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110110” VRC126 ((103R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “110111” VRC127 ((102R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111000” VRC128 ((101R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111001” VRC129 ((100R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111010” VRC130 ((99R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111011” VRC131 ((98R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111100” VRC132 ((97R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111101” VRC133 ((96R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111110” VRC134 ((95R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP5[5:0] = “111111” VRC146 ((83R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000000” VRC145 ((84R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000001” VRC144 ((85R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000010” VRC143 ((86R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000011” VRC142 ((87R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000100” VRC141 VRC140 ((88R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((89R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000101” PKP6[5:0] = “000110” VINP7 VRC139 ((90R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “000111” VRC138 ((91R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001000” VRC137 ((92R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001001” VRC136 ((93R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001010” VRC135 ((94R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001011” Page 170/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 83. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC134 ((95R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001100” VRC133 ((96R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001101” VRC132 ((97R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001110” VRC131 ((98R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “001111” VRC130 ((99R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010000” VRC129 ((100R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010001” VRC128 ((101R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010010” VRC127 ((102R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010011” VRC126 ((103R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010100” VRC125 ((104R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010101” VRC124 ((105R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010110” VRC123 ((106R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “010111” VRC122 ((107R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011000” VRC121 ((108R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011001” VRC120 ((109R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011010” VRC119 ((110R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011011” VRC118 ((111R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011100” VRC117 VRC116 ((112R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((113R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011101” PKP6[5:0] = “011110” VINP7 VRC115 ((114R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “011111” VRC114 ((115R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100000” VRC113 ((116R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100001” VRC112 ((117R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100010” VRC111 ((118R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100011” VRC110 ((119R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100100” VRC109 ((120R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100101” VRC108 ((121R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100110” VRC107 ((122R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “100111” VRC106 ((123R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101000” VRC105 ((124R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101001” VRC104 ((125R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101010” VRC103 ((126R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101011” VRC102 ((127R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101100” VRC101 ((128R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101101” VRC100 ((129R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101110” VRC99 ((130R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “101111” Page 171/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 84. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC98 ((131R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110000” VRC97 ((132R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110001” VRC96 ((133R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110010” VRC95 ((134R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110011” VRC94 ((135R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110100” VRC93 ((136R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110101” VRC92 ((137R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110110” VRC91 VRC90 ((138R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((139R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “110111” PKP6[5:0] = “111000” VINP7 VRC89 ((140R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111001” VRC88 ((141R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111010” VRC87 ((142R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111011” VRC86 ((143R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111100” VRC85 ((144R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111101” VRC84 ((145R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111110” VRC83 ((146R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP6[5:0] = “111111” VRC168 ((61R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000000” VRC167 ((62R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000001” VRC166 ((63R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000010” VRC165 ((64R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000011” VRC164 ((65R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000100” VRC163 ((66R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000101” VRC162 ((67R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000110” VRC161 ((68R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “000111” VRC160 ((69R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001000” VRC159 VRC158 ((70R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((71R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001001” PKP7[5:0] = “001010” VINP8 VRC157 ((72R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001011” VRC156 ((73R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001100” VRC155 ((74R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001101” VRC154 ((75R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001110” VRC153 ((76R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “001111” VRC152 ((77R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010000” VRC151 ((78R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010001” VRC150 ((79R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010010” VRC149 ((80R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010011” Page 172/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 85. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC148 ((81R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010100” VRC147 ((82R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010101” VRC146 ((83R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010110” VRC145 ((84R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “010111” VRC144 ((85R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011000” VRC143 ((86R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011001” VRC142 ((87R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011010” VRC141 ((88R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011011” VRC140 ((89R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011100” VRC139 ((90R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011101” VRC138 ((91R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011110” VRC137 ((92R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “011111” VRC136 ((93R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100000” VRC135 ((94R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100001” VRC134 ((95R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100010” VRC133 ((96R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100011” VRC132 ((97R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100100” VRC131 VRC130 ((98R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((99R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100101” PKP7[5:0] = “100110” VINP8 VRC129 ((100R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “100111” VRC128 ((101R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101000” VRC127 ((102R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101001” VRC126 ((103R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101010” VRC125 ((104R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101011” VRC124 ((105R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101100” VRC123 ((106R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101101” VRC122 ((107R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101110” VRC121 ((108R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “101111” VRC120 ((109R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110000” VRC119 ((110R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110001” VRC118 ((111R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110010” VRC117 ((112R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110011” VRC116 ((113R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110100” VRC115 ((114R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110101” VRC114 ((115R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110110” VRC113 ((116R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “110111” Page 173/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 86. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC112 ((117R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111000” VRC111 ((118R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111001” VRC110 ((119R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111010” VRC109 VRC108 ((120R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((121R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111011” PKP7[5:0] = “111100” VINP8 VRC107 ((122R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111101” VRC106 ((123R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111110” VRC105 ((124R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP7[5:0] = “111111” VRC215 ((14R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000000” VRC214 ((15R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000001” VRC213 ((16R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000010” VRC212 ((17R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000011” VRC211 ((18R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000100” VRC210 ((19R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000101” VRC209 ((20R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000110” VRC208 ((21R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “000111” VRC207 ((22R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001000” VRC206 ((23R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001001” VRC205 ((24R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001010” VRC204 ((25R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001011” VRC203 ((26R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001100” VRC202 VRC201 ((27R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((28R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001101” PKP8[5:0] = “001110” VINP9 VRC200 ((29R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “001111” VRC199 ((30R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010000” VRC198 ((31R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010001” VRC197 ((32R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010010” VRC196 ((33R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010011” VRC195 ((34R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010100” VRC194 ((35R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010101” VRC193 ((36R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010110” VRC192 ((37R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “010111” VRC191 ((38R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011000” VRC190 ((39R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011001” VRC189 ((40R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011010” VRC188 ((41R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011011” Page 174/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 87. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC187 ((42R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011100” VRC186 ((43R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011101” VRC185 ((44R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011110” VRC184 ((45R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “011111” VRC183 ((46R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100000” VRC182 ((47R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100001” VRC181 ((48R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100010” VRC180 ((49R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100011” VRC179 ((50R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100100” VRC178 ((51R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100101” VRC177 ((52R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100110” VRC176 ((53R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “100111” VRC175 ((54R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101000” VRC174 ((55R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101001” VRC173 ((56R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101010” VRC172 ((57R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101011” VRC171 ((58R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101100” VRC170 VRC169 ((59R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((60R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101101” PKP8[5:0] = “101110” VINP9 VRC168 ((61R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “101111” VRC167 ((62R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110000” VRC166 ((63R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110001” VRC165 ((64R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110010” VRC164 ((65R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110011” VRC163 ((66R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110100” VRC162 ((67R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110101” VRC161 ((68R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110110” VRC160 ((69R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “110111” VRC159 ((70R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111000” VRC158 ((71R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111001” VRC157 ((72R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111010” VRC156 ((73R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111011” VRC155 ((74R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111100” VRC154 ((75R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111101” VRC153 ((76R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111110” VRC152 ((77R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP8[5:0] = “111111” Page 175/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 88. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC234 ((2.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000000” VRC233 ((3R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000001” VRC232 ((3.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000010” VRC231 ((4R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000011” VRC230 ((4.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000100” VRC229 ((5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000101” VRC228 ((5.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000110” VRC227 ((6R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “000111” VRC226 ((6.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001000” VRC225 ((7R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001001” VRC224 ((7.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001010” VRC223 ((8R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001011” VRC222 ((8.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001100” VRC221 ((9R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001101” VRC220 ((9.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001110” VRC219 ((10R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “001111” VRC218 ((11R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010000” VRC217 VRC216 ((12R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((13R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010001” PKP9[5:0] = “010010” VNP10 VRC215 ((14R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010011” VRC214 ((15R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010100” VRC213 ((16R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010101” VRC212 ((17R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010110” VRC211 ((18R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “010111” VRC210 ((19R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011000” VRC209 ((20R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011001” VRC208 ((21R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011010” VRC207 ((22R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011011” VRC206 ((23R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011100” VRC205 ((24R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011101” VRC204 ((25R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011110” VRC203 ((26R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “011111” VRC202 ((27R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100000” VRC201 ((28R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100001” VRC200 ((29R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100010” VRC199 ((30R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100011” Page 176/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 89. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC198 ((31R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100100” VRC197 ((32R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100101” VRC196 ((33R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100110” VRC195 ((34R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “100111” VRC194 ((35R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101000” VRC193 ((36R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101001” VRC192 ((37R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101010” VRC191 ((38R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101011” VRC190 ((39R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101100” VRC189 ((40R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101101” VRC188 ((41R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101110” VRC187 ((42R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “101111” VRC186 ((43R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110000” VRC185 VRC184 ((44R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((45R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110001” PKP9[5:0] = “110010” VINP10 VRC183 ((46R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110011” VRC182 ((47R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110100” VRC181 ((48R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110101” VRC180 ((49R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110110” VRC179 ((50R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “110111” VRC178 ((51R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111000” VRC177 ((52R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111001” VRC176 ((53R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111010” VRC175 ((54R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111011” VRC174 ((55R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111100” VRC173 ((56R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111101” VRC172 ((57R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111110” VRC171 ((58R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP9[5:0] = “111111” VRC238 ((0.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000000” VRC237 ((1R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000001” VRC236 ((1.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000010” VRC235 VRC234 ((2R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((2.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000011” PKP10[5:0] = “000100” VINP11 VRC233 ((3R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000101” VRC232 ((3.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000110” VRC231 ((4R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “000111” Page 177/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 90. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC230 ((4.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001000” VRC229 ((5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001001” VRC228 ((5.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001010” VRC227 ((6R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001011” VRC226 ((6.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001100” VRC225 ((7R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001101” VRC224 ((7.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001110” VRC223 ((8R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “001111” VRC222 ((8.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010000” VRC221 ((9R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010001” VRC220 ((9.5R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010010” VRC219 ((10R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010011” VRC218 ((11R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010100” VRC217 ((12R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010101” VRC216 ((13R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010110” VRC215 ((14R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “010111” VRC214 ((15R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011000” VRC213 VRC212 ((16R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((17R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011001” PKP10[5:0] = “011010” VINP11 VRC211 ((18R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011011” VRC210 ((19R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011100” VRC209 ((20R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011101” VRC208 ((21R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011110” VRC207 ((22R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “011111” VRC206 ((23R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100000” VRC205 ((24R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100001” VRC204 ((25R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100010” VRC203 ((26R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100011” VRC202 ((27R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100100” VRC201 ((28R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100101” VRC200 ((29R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100110” VRC199 ((30R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “100111” VRC198 ((31R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101000” VRC197 ((32R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101001” VRC196 ((33R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101010” VRC195 ((34R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101011” Page 178/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 91. Formulas for calculating gamma adjusting voltage (positive polarity) 1 (continued) Pads Formula Micro-adjusting register value Reference voltage VRC194 ((35R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101100” VRC193 ((36R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101101” VRC192 ((37R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101110” VRC191 ((38R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “101111” VRC190 ((39R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110000” VRC189 ((40R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110001” VRC188 ((41R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110010” VRC187 ((42R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110011” VRC186 ((43R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110100” VRC185 VRC184 ((44R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 ((45R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110101” PKP10[5:0] = “110110” VINP11 VRC183 ((46R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “110111” VRC182 ((47R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111000” VRC181 ((48R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111001” VRC180 ((49R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111010” VRC179 ((50R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111011” VRC178 ((51R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111100” VRC177 ((52R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111101” VRC176 ((53R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111110” VRC175 ((54R+Ra)/Rt) * (VINP0 - VINP12) + VINP12 PKP10[5:0] = “111111” Page 179/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 92. Formulas for calculating gamma adjusting voltage (positive polarity) 2 Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V0 VINP0 V1 VINP1 V2 V1-(V1-V4)*(2/6) V1-(V1-V5)*(2/8.5) V1-(V1-V6)*(2/9.5) V1-(V1-V7)*(2/10.5) V3 V1-(V1-V4)*(4/6) V1-(V1-V5)*(4/8.5) V1-(V1-V6)*(4/9.5) V1-(V1-V7)*(4/10.5) V4 VINP2 V1-(V1-V5)*(6/8.5) V1-(V1-V6)*(6/9.5) V1-(V1-V7)*(6/10.5) V5 V4-(V4-V11)*(2.5/9.5) VINP2 V1-(V1-V6)*(8.5/9.5) V1-(V1-V7)*(8.5/10.5) V6 V4-(V4-V11)*(3.5/9.5) V5-(V5-V11)*(1/7) VINP2 V1-(V1-V7)*(9.5/10.5) V7 V4-(V4-V11)*(4.5/9.5) V5-(V5-V11)*(2/7) V6-(V6-V11)*(1/6) VINP2 V8 V4-(V4-V11)*(6/9.5) V5-(V5-V11)*(3.5/7) V6-(V6-V11)*(2.5/6) V7-(V7-V11)*(1.5/5) V9 V4-(V4-V11)*(7/9.5) V5-(V5-V11)*(4.5/7) V6-(V6-V11)*(3.5/6) V7-(V7-V11)*(2.5/5) V10 V4-(V4-V11)*(8.5/9.5) V5-(V5-V11)*(6/7) V6-(V6-V11)*(5/6) V7-(V7-V11)*(4/5) V11 VINP3 V12 V11-(V11-V54)*(3/61) V11-(V11-V55)*(3/62) V11-(V11-V56)*(3/63) V11-(V11-V57)*(3/64.5) V13 V11-(V11-V54)*(6/61) V11-(V11-V55)*(6/62) V11-(V11-V56)*(6/63) V11-(V11-V57)*(6/64.5) V14 V11-(V11-V54)*(8/61) V11-(V11-V55)*(8/62) V11-(V11-V56)*(8/63) V11-(V11-V57)*(8/64.5) V15 V11-(V11-V54)*(10/61) V11-(V11-V55)*(10/62) V11-(V11-V56)*(10/63) V11-(V11-V57)*(10/64.5) V16 V11-(V11-V54)*(12/61) V11-(V11-V55)*(12/62) V11-(V11-V56)*(12/63) V11-(V11-V57)*(12/64.5) V17 V11-(V11-V54)*(14/61) V11-(V11-V55)*(14/62) V11-(V11-V56)*(14/63) V11-(V11-V57)*(14/64.5) V18 V11-(V11-V54)*(16/61) V11-(V11-V55)*(16/62) V11-(V11-V56)*(16/63) V11-(V11-V57)*(16/64.5) V19 V11-(V11-V54)*(17/61) V11-(V11-V55)*(17/62) V11-(V11-V56)*(17/63) V11-(V11-V57)*(17/64.5) V20 V11-(V11-V54)*(19/61) V11-(V11-V55)*(19/62) V11-(V11-V56)*(19/63) V11-(V11-V57)*(19/64.5) V21 V11-(V11-V54)*(21/61) V11-(V11-V55)*(21/62) V11-(V11-V56)*(21/63) V11-(V11-V57)*(21/64.5) V22 V11-(V11-V54)*(23/61) V11-(V11-V55)*(23/62) V11-(V11-V56)*(23/63) V11-(V11-V57)*(23/64.5) V23 V11-(V11-V54)*(24/61) V11-(V11-V55)*(24/62) V11-(V11-V56)*(24/63) V11-(V11-V57)*(24/64.5) V24 V11-(V11-V54)*(26/61) V11-(V11-V55)*(26/62) V11-(V11-V56)*(26/63) V11-(V11-V57)*(26/64.5) V25 V11-(V11-V54)*(27.5/61) V11-(V11-V55)*(27.5/62) V11-(V11-V56)*(27.5/63) V11-(V11-V57)*(27.5/64.5) V26 V11-(V11-V54)*(29.5/61) V11-(V11-V55)*(29.5/62) V11-(V11-V56)*(29.5/63) V11-(V11-V57)*(29.5/64.5) V27 V11-(V11-V54)*(31/61) V11-(V11-V55)*(31/62) V11-(V11-V56)*(31/63) V11-(V11-V57)*(31/64.5) V28 V11-(V11-V54)*(32/61) V11-(V11-V55)*(32/62) V11-(V11-V56)*(32/63) V11-(V11-V57)*(32/64.5) V29 V11-(V11-V54)*(34/61) V11-(V11-V55)*(34/62) V11-(V11-V56)*(34/63) V11-(V11-V57)*(34/64.5) V30 V11-(V11-V54)*(35/61) V11-(V11-V55)*(35/62) V11-(V11-V56)*(35/63) V11-(V11-V57)*(35/64.5) V31 V11-(V11-V54)*(37/61) V11-(V11-V55)*(37/62) V11-(V11-V56)*(37/63) V11-(V11-V57)*(37/64.5) V32 V11-(V11-V54)*(39/61) V11-(V11-V55)*(39/62) V11-(V11-V56)*(39/63) V11-(V11-V57)*(39/64.5) V33 V11-(V11-V54)*(40/61) V11-(V11-V55)*(40/62) V11-(V11-V56)*(40/63) V11-(V11-V57)*(40/64.5) Page 180/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 93. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V34 V11-(V11-V54)*(41/61) V11-(V11-V55)*(41/62) V11-(V11-V56)*(41/63) V11-(V11-V57)*(41/64.5) V35 V11-(V11-V54)*(42/61) V11-(V11-V55)*(42/62) V11-(V11-V56)*(42/63) V11-(V11-V57)*(42/64.5) V36 V11-(V11-V54)*(43/61) V11-(V11-V55)*(43/62) V11-(V11-V56)*(43/63) V11-(V11-V57)*(43/64.5) V37 V11-(V11-V54)*(44/61) V11-(V11-V55)*(44/62) V11-(V11-V56)*(44/63) V11-(V11-V57)*(44/64.5) V38 V11-(V11-V54)*(45/61) V11-(V11-V55)*(45/62) V11-(V11-V56)*(45/63) V11-(V11-V57)*(45/64.5) V39 V11-(V11-V54)*(46/61) V11-(V11-V55)*(46/62) V11-(V11-V56)*(46/63) V11-(V11-V57)*(46/64.5) V40 V11-(V11-V54)*(47/61) V11-(V11-V55)*(47/62) V11-(V11-V56)*(47/63) V11-(V11-V57)*(47/64.5) V41 V11-(V11-V54)*(48/61) V11-(V11-V55)*(48/62) V11-(V11-V56)*(48/63) V11-(V11-V57)*(48/64.5) V42 V11-(V11-V54)*(49/61) V11-(V11-V55)*(49/62) V11-(V11-V56)*(49/63) V11-(V11-V57)*(49/64.5) V43 V11-(V11-V54)*(50/61) V11-(V11-V55)*(50/62) V11-(V11-V56)*(50/63) V11-(V11-V57)*(50/64.5) V44 V11-(V11-V54)*(51/61) V11-(V11-V55)*(51/62) V11-(V11-V56)*(51/63) V11-(V11-V57)*(51/64.5) V45 V11-(V11-V54)*(52/61) V11-(V11-V55)*(52/62) V11-(V11-V56)*(52/63) V11-(V11-V57)*(52/64.5) V46 V11-(V11-V54)*(53/61) V11-(V11-V55)*(53/62) V11-(V11-V56)*(53/63) V11-(V11-V57)*(53/64.5) V47 V11-(V11-V54)*(54/61) V11-(V11-V55)*(54/62) V11-(V11-V56)*(54/63) V11-(V11-V57)*(54/64.5) V48 V11-(V11-V54)*(55/61) V11-(V11-V55)*(55/62) V11-(V11-V56)*(55/63) V11-(V11-V57)*(55/64.5) V49 V11-(V11-V54)*(56/61) V11-(V11-V55)*(56/62) V11-(V11-V56)*(56/63) V11-(V11-V57)*(56/64.5) V50 V11-(V11-V54)*(57/61) V11-(V11-V55)*(57/62) V11-(V11-V56)*(57/63) V11-(V11-V57)*(57/64.5) V51 V11-(V11-V54)*(58/61) V11-(V11-V55)*(58/62) V11-(V11-V56)*(58/63) V11-(V11-V57)*(58/64.5) V52 V11-(V11-V54)*(59/61) V11-(V11-V55)*(59/62) V11-(V11-V56)*(59/63) V11-(V11-V57)*(59/64.5) V53 V11-(V11-V54)*(60/61) V11-(V11-V55)*(60/62) V11-(V11-V56)*(60/63) V11-(V11-V57)*(60/64.5) V54 VINP4 V11-(V11-V55)*(61/62) V11-(V11-V56)*(61/63) V11-(V11-V57)*(61/64.5) V55 V54-(V54-V95)*(1/42) VINP4 V11-(V11-V56)*(62/63) V11-(V11-V57)*(62/64.5) V56 V54-(V54-V95)*(2/42) V55-(V55-V95)*(1/41) VINP4 V11-(V11-V57)*(63/64.5) V57 V54-(V54-V95)*(3.5/42) V55-(V55-V95)*(2.5/41) V56-(V56-V95)*(1.5/40) VINP4 V58 V54-(V54-V95)*(4.5/42) V55-(V55-V95)*(3.5/41) V56-(V56-V95)*(2.5/40) V57-(V57-V95)*(1/38.5) V59 V54-(V54-V95)*(5.5/42) V55-(V55-V95)*(4.5/41) V56-(V56-V95)*(3.5/40) V57-(V57-V95)*(2/38.5) V60 V54-(V54-V95)*(7/42) V55-(V55-V95)*(6/41) V56-(V56-V95)*(5/40) V57-(V57-V95)*(3.5/38.5) V61 V54-(V54-V95)*(8/42) V55-(V55-V95)*(7/41) V56-(V56-V95)*(6/40) V57-(V57-V95)*(4.5/38.5) V62 V54-(V54-V95)*(9/42) V55-(V55-V95)*(8/41) V56-(V56-V95)*(7/40) V57-(V57-V95)*(5.5/38.5) V63 V54-(V54-V95)*(10/42) V55-(V55-V95)*(9/41) V56-(V56-V95)*(8/40) V57-(V57-V95)*(6.5/38.5) V64 V54-(V54-V95)*(11/42) V55-(V55-V95)*(10/41) V56-(V56-V95)*(9/40) V57-(V57-V95)*(7.5/38.5) V65 V54-(V54-V95)*(12/42) V55-(V55-V95)*(11/41) V56-(V56-V95)*(10/40) V57-(V57-V95)*(8.5/38.5) V66 V54-(V54-V95)*(13/42) V55-(V55-V95)*(12/41) V56-(V56-V95)*(11/40) V57-(V57-V95)*(9.5/38.5) V67 V54-(V54-V95)*(14/42) V55-(V55-V95)*(13/41) V56-(V56-V95)*(12/40) V57-(V57-V95)*(10.5/38.5) Page 181/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 94. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V68 V54-(V54-V95)*(15/42) V55-(V55-V95)*(14/41) V56-(V56-V95)*(13/40) V57-(V57-V95)*(11.5/38.5) V69 V54-(V54-V95)*(16/42) V55-(V55-V95)*(15/41) V56-(V56-V95)*(14/40) V57-(V57-V95)*(12.5/38.5) V70 V54-(V54-V95)*(17/42) V55-(V55-V95)*(16/41) V56-(V56-V95)*(15/40) V57-(V57-V95)*(13.5/38.5) V71 V54-(V54-V95)*(18/42) V55-(V55-V95)*(17/41) V56-(V56-V95)*(16/40) V57-(V57-V95)*(14.5/38.5) V72 V54-(V54-V95)*(19/42) V55-(V55-V95)*(18/41) V56-(V56-V95)*(17/40) V57-(V57-V95)*(15.5/38.5) V73 V54-(V54-V95)*(20/42) V55-(V55-V95)*(19/41) V56-(V56-V95)*(18/40) V57-(V57-V95)*(16.5/38.5) V74 V54-(V54-V95)*(21/42) V55-(V55-V95)*(20/41) V56-(V56-V95)*(19/40) V57-(V57-V95)*(17.5/38.5) V75 V54-(V54-V95)*(22/42) V55-(V55-V95)*(21/41) V56-(V56-V95)*(20/40) V57-(V57-V95)*(18.5/38.5) V76 V54-(V54-V95)*(23/42) V55-(V55-V95)*(22/41) V56-(V56-V95)*(21/40) V57-(V57-V95)*(19.5/38.5) V77 V54-(V54-V95)*(24/42) V55-(V55-V95)*(23/41) V56-(V56-V95)*(22/40) V57-(V57-V95)*(20.5/38.5) V78 V54-(V54-V95)*(25/42) V55-(V55-V95)*(24/41) V56-(V56-V95)*(23/40) V57-(V57-V95)*(21.5/38.5) V79 V54-(V54-V95)*(26/42) V55-(V55-V95)*(25/41) V56-(V56-V95)*(24/40) V57-(V57-V95)*(22.5/38.5) V80 V54-(V54-V95)*(27/42) V55-(V55-V95)*(26/41) V56-(V56-V95)*(25/40) V57-(V57-V95)*(23.5/38.5) V81 V54-(V54-V95)*(28/42) V55-(V55-V95)*(27/41) V56-(V56-V95)*(26/40) V57-(V57-V95)*(24.5/38.5) V82 V54-(V54-V95)*(29/42) V55-(V55-V95)*(28/41) V56-(V56-V95)*(27/40) V57-(V57-V95)*(25.5/38.5) V83 V54-(V54-V95)*(30/42) V55-(V55-V95)*(29/41) V56-(V56-V95)*(28/40) V57-(V57-V95)*(26.5/38.5) V84 V54-(V54-V95)*(31/42) V55-(V55-V95)*(30/41) V56-(V56-V95)*(29/40) V57-(V57-V95)*(27.5/38.5) V85 V54-(V54-V95)*(32/42) V55-(V55-V95)*(31/41) V56-(V56-V95)*(30/40) V57-(V57-V95)*(28.5/38.5) V86 V54-(V54-V95)*(33/42) V55-(V55-V95)*(32/41) V56-(V56-V95)*(31/40) V57-(V57-V95)*(29.5/38.5) V87 V54-(V54-V95)*(34/42) V55-(V55-V95)*(33/41) V56-(V56-V95)*(32/40) V57-(V57-V95)*(30.5/38.5) V88 V54-(V54-V95)*(35/42) V55-(V55-V95)*(34/41) V56-(V56-V95)*(33/40) V57-(V57-V95)*(31.5/38.5) V89 V54-(V54-V95)*(36/42) V55-(V55-V95)*(35/41) V56-(V56-V95)*(34/40) V57-(V57-V95)*(32.5/38.5) V90 V54-(V54-V95)*(37/42) V55-(V55-V95)*(36/41) V56-(V56-V95)*(35/40) V57-(V57-V95)*(33.5/38.5) V91 V54-(V54-V95)*(38/42) V55-(V55-V95)*(37/41) V56-(V56-V95)*(36/40) V57-(V57-V95)*(34.5/38.5) V92 V54-(V54-V95)*(39/42) V55-(V55-V95)*(38/41) V56-(V56-V95)*(37/40) V57-(V57-V95)*(35.5/38.5) V93 V54-(V54-V95)*(40/42) V55-(V55-V95)*(39/41) V56-(V56-V95)*(38/40) V57-(V57-V95)*(36.5/38.5) V94 V54-(V54-V95)*(41/42) V55-(V55-V95)*(40/41) V56-(V56-V95)*(39/40) V57-(V57-V95)*(37.5/38.5) V95 VINP5 V96 V95-(V95-VC)*(1/33) V97 V95-(V95-VC)*(2/33) V98 V95-(V95-VC)*(3/33) V99 V95-(V95-VC)*(4/33) V100 V95-(V95-VC)*(5/33) V101 V95-(V95-VC)*(6/33) Page 182/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 95. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V102 V95-(V95-VC)*(7/33) V103 V95-(V95-VC)*(8/33) V104 V95-(V95-VC)*(9/33) V105 V95-(V95-VC)*(10/33) V106 V95-(V95-VC)*(11/33) V107 V95-(V95-VC)*(12/33) V108 V95-(V95-VC)*(13/33) V109 V95-(V95-VC)*(14/33) V110 V95-(V95-VC)*(15/33) V111 V95-(V95-VC)*(16/33) V112 V95-(V95-VC)*(17/33) V113 V95-(V95-VC)*(18/33) V114 V95-(V95-VC)*(19/33) V115 V95-(V95-VC)*(20/33) V116 V95-(V95-VC)*(21/33) V117 V95-(V95-VC)*(22/33) V118 V95-(V95-VC)*(23/33) V119 V95-(V95-VC)*(24.5/33) V120 V95-(V95-VC)*(25.5/33) V121 V95-(V95-VC)*(26.5/33) V122 V95-(V95-VC)*(27.5/33) V123 V95-(V95-VC)*(28.5/33) V124 V95-(V95-VC)*(29.5/33) V125 V95-(V95-VC)*(30.5/33) V126 V95-(V95-VC)*(31/33) V127 V95-(V95-VC)*(32/33) VC VINP6 V128 VC-(VC-V160)*(0.5/32) V129 VC-(VC-V160)*(1.5/32) V130 VC-(VC-V160)*(2.5/32) V131 VC-(VC-V160)*(3.5/32) V132 VC-(VC-V160)*(4.5/32) V133 VC-(VC-V160)*(5.5/32) V134 VC-(VC-V160)*(6.5/32) Page 183/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 96. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V135 VC-(VC-V160)*(7.5/32) V136 VC-(VC-V160)*(8.5/32) V137 VC-(VC-V160)*(9/32) V138 VC-(VC-V160)*(10/32) V139 VC-(VC-V160)*(11/32) V140 VC-(VC-V160)*(12/32) V141 VC-(VC-V160)*(13/32) V142 VC-(VC-V160)*(14/32) V143 VC-(VC-V160)*(15/32) V144 VC-(VC-V160)*(16/32) V145 VC-(VC-V160)*(17/32) V146 VC-(VC-V160)*(18/32) V147 VC-(VC-V160)*(19/32) V148 VC-(VC-V160)*(20/32) V149 VC-(VC-V160)*(21/32) V150 VC-(VC-V160)*(22/32) V151 VC-(VC-V160)*(23/32) V152 VC-(VC-V160)*(24.5/32) V153 VC-(VC-V160)*(25.5/32) V154 VC-(VC-V160)*(26.5/32) V155 VC-(VC-V160)*(27.5/32) V156 VC-(VC-V160)*(28.5/32) V157 VC-(VC-V160)*(29.5/32) V158 VC-(VC-V160)*(30/32) V159 VC-(VC-V160)*(31/32) V160 VINP7 V161 V160-(V160-V199)*(1/40.5) V160-(V160-V200)*(1/41.5) V160-(V160-V201)*(1/43) V160-(V160-V202)*(1/44) V162 V160-(V160-V199)*(2/40.5) V160-(V160-V200)*(2/41.5) V160-(V160-V201)*(2/43) V160-(V160-V202)*(2/44) V163 V160-(V160-V199)*(3/40.5) V160-(V160-V200)*(3/41.5) V160-(V160-V201)*(3/43) V160-(V160-V202)*(3/44) V164 V160-(V160-V199)*(3.5/40.5) V160-(V160-V200)*(3.5/41.5) V160-(V160-V201)*(3.5/43) V160-(V160-V202)*(3.5/44) V165 V160-(V160-V199)*(4.5/40.5) V160-(V160-V200)*(4.5/41.5) V160-(V160-V201)*(4.5/43) V160-(V160-V202)*(4.5/44) V166 V160-(V160-V199)*(5.5/40.5) V160-(V160-V200)*(5.5/41.5) V160-(V160-V201)*(5.5/43) V160-(V160-V202)*(5.5/44) V167 V160-(V160-V199)*(6.5/40.5) V160-(V160-V200)*(6.5/41.5) V160-(V160-V201)*(6.5/43) V160-(V160-V202)*(6.5/44) V168 V160-(V160-V199)*(7.5/40.5) V160-(V160-V200)*(7.5/41.5) V160-(V160-V201)*(7.5/43) V160-(V160-V202)*(7.5/44) Page 184/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 97. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V169 V160-(V160-V199)*(8.5/40.5) V160-(V160-V200)*(8.5/41.5) V160-(V160-V201)*(8.5/43) V160-(V160-V202)*(8.5/44) V170 V160-(V160-V199)*(9.5/40.5) V160-(V160-V200)*(9.5/41.5) V160-(V160-V201)*(9.5/43) V160-(V160-V202)*(9.5/44) V171 V160-(V160-V199)*(10.5/40.5) V160-(V160-V200)*(10.5/41.5) V160-(V160-V201)*(10.5/43) V160-(V160-V202)*(10.5/44) V172 V160-(V160-V199)*(11.5/40.5) V160-(V160-V200)*(11.5/41.5) V160-(V160-V201)*(11.5/43) V160-(V160-V202)*(11.5/44) V173 V160-(V160-V199)*(12.5/40.5) V160-(V160-V200)*(12.5/41.5) V160-(V160-V201)*(12.5/43) V160-(V160-V202)*(12.5/44) V174 V160-(V160-V199)*(13.5/40.5) V160-(V160-V200)*(13.5/41.5) V160-(V160-V201)*(13.5/43) V160-(V160-V202)*(13.5/44) V175 V160-(V160-V199)*(14.5/40.5) V160-(V160-V200)*(14.5/41.5) V160-(V160-V201)*(14.5/43) V160-(V160-V202)*(14.5/44) V176 V160-(V160-V199)*(15.5/40.5) V160-(V160-V200)*(15.5/41.5) V160-(V160-V201)*(15.5/43) V160-(V160-V202)*(15.5/44) V177 V160-(V160-V199)*(16.5/40.5) V160-(V160-V200)*(16.5/41.5) V160-(V160-V201)*(16.5/43) V160-(V160-V202)*(16.5/44) V178 V160-(V160-V199)*(17.5/40.5) V160-(V160-V200)*(17.5/41.5) V160-(V160-V201)*(17.5/43) V160-(V160-V202)*(17.5/44) V179 V160-(V160-V199)*(18.5/40.5) V160-(V160-V200)*(18.5/41.5) V160-(V160-V201)*(18.5/43) V160-(V160-V202)*(18.5/44) V180 V160-(V160-V199)*(19.5/40.5) V160-(V160-V200)*(19.5/41.5) V160-(V160-V201)*(19.5/43) V160-(V160-V202)*(19.5/44) V181 V160-(V160-V199)*(20.5/40.5) V160-(V160-V200)*(20.5/41.5) V160-(V160-V201)*(20.5/43) V160-(V160-V202)*(20.5/44) V182 V160-(V160-V199)*(21.5/40.5) V160-(V160-V200)*(21.5/41.5) V160-(V160-V201)*(21.5/43) V160-(V160-V202)*(21.5/44) V183 V160-(V160-V199)*(22.5/40.5) V160-(V160-V200)*(22.5/41.5) V160-(V160-V201)*(22.5/43) V160-(V160-V202)*(22.5/44) V184 V160-(V160-V199)*(23.5/40.5) V160-(V160-V200)*(23.5/41.5) V160-(V160-V201)*(23.5/43) V160-(V160-V202)*(23.5/44) V185 V160-(V160-V199)*(24.5/40.5) V160-(V160-V200)*(24.5/41.5) V160-(V160-V201)*(24.5/43) V160-(V160-V202)*(24.5/44) V186 V160-(V160-V199)*(25.5/40.5) V160-(V160-V200)*(25.5/41.5) V160-(V160-V201)*(25.5/43) V160-(V160-V202)*(25.5/44) V187 V160-(V160-V199)*(26.5/40.5) V160-(V160-V200)*(26.5/41.5) V160-(V160-V201)*(26.5/43) V160-(V160-V202)*(26.5/44) V188 V160-(V160-V199)*(27.5/40.5) V160-(V160-V200)*(27.5/41.5) V160-(V160-V201)*(27.5/43) V160-(V160-V202)*(27.5/44) V189 V160-(V160-V199)*(29.5/40.5) V160-(V160-V200)*(29.5/41.5) V160-(V160-V201)*(29.5/43) V160-(V160-V202)*(29.5/44) V190 V160-(V160-V199)*(30.5/40.5) V160-(V160-V200)*(30.5/41.5) V160-(V160-V201)*(30.5/43) V160-(V160-V202)*(30.5/44) V191 V160-(V160-V199)*(31.5/40.5) V160-(V160-V200)*(31.5/41.5) V160-(V160-V201)*(31.5/43) V160-(V160-V202)*(31.5/44) V192 V160-(V160-V199)*(32.5/40.5) V160-(V160-V200)*(32.5/41.5) V160-(V160-V201)*(32.5/43) V160-(V160-V202)*(32.5/44) V193 V160-(V160-V199)*(33.5/40.5) V160-(V160-V200)*(33.5/41.5) V160-(V160-V201)*(33.5/43) V160-(V160-V202)*(33.5/44) V194 V160-(V160-V199)*(35/40.5) V160-(V160-V200)*(35/41.5) V160-(V160-V201)*(35/43) V160-(V160-V202)*(35/44) V195 V160-(V160-V199)*(36/40.5) V160-(V160-V200)*(36/41.5) V160-(V160-V201)*(36/43) V160-(V160-V202)*(36/44) V196 V160-(V160-V199)*(37/40.5) V160-(V160-V200)*(37/41.5) V160-(V160-V201)*(37/43) V160-(V160-V202)*(37/44) V197 V160-(V160-V199)*(38/40.5) V160-(V160-V200)*(38/41.5) V160-(V160-V201)*(38/43) V160-(V160-V202)*(38/44) V198 V160-(V160-V199)*(39.5/40.5) V160-(V160-V200)*(39.5/41.5) V160-(V160-V201)*(39.5/43) V160-(V160-V202)*(39.5/44) V199 VINP8 V160-(V160-V200)*(40.5/41.5) V160-(V160-V201)*(40.5/43) V160-(V160-V202)*(40.5/44) V200 V199-(V199-V244)*(1/51) VINP8 V160-(V160-V201)*(41.5/43) V160-(V160-V202)*(41.5/44) V201 V199-(V199-V244)*(2.5/51) V200-(V200-V244)*(1.5/50) VINP8 V160-(V160-V202)*(43/44) V202 V199-(V199-V244)*(3.5/51) V200-(V200-V244)*(2.5/50) V201-(V201-V244)*(1/48.5) VINP8 Page 185/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 98. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V203 V199-(V199-V244)*(4/51) V200-(V200-V244)*(3/50) V201-(V201-V244)*(1.5/48.5) V202-(V202-V244)*(0.5/47.5) V204 V199-(V199-V244)*(5/51) V200-(V200-V244)*(4/50) V201-(V201-V244)*(2.5/48.5) V202-(V202-V244)*(1.5/47.5) V205 V199-(V199-V244)*(5.5/51) V200-(V200-V244)*(4.5/50) V201-(V201-V244)*(3/48.5) V202-(V202-V244)*(2/47.5) V206 V199-(V199-V244)*(6/51) V200-(V200-V244)*(5/50) V201-(V201-V244)*(3.5/48.5) V202-(V202-V244)*(2.5/47.5) V207 V199-(V199-V244)*(7/51) V200-(V200-V244)*(6/50) V201-(V201-V244)*(4.5/48.5) V202-(V202-V244)*(3.5/47.5) V208 V199-(V199-V244)*(8/51) V200-(V200-V244)*(7/50) V201-(V201-V244)*(5.5/48.5) V202-(V202-V244)*(4.5/47.5) V209 V199-(V199-V244)*(8.5/51) V200-(V200-V244)*(7.5/50) V201-(V201-V244)*(6/48.5) V202-(V202-V244)*(5/47.5) V210 V199-(V199-V244)*(9/51) V200-(V200-V244)*(8/50) V201-(V201-V244)*(6.5/48.5) V202-(V202-V244)*(5.5/47.5) V211 V199-(V199-V244)*(10/51) V200-(V200-V244)*(9/50) V201-(V201-V244)*(7.5/48.5) V202-(V202-V244)*(6.5/47.5) V212 V199-(V199-V244)*(11/51) V200-(V200-V244)*(10/50) V201-(V201-V244)*(8.5/48.5) V202-(V202-V244)*(7.5/47.5) V213 V199-(V199-V244)*(12/51) V200-(V200-V244)*(11/50) V201-(V201-V244)*(9.5/48.5) V202-(V202-V244)*(8.5/47.5) V214 V199-(V199-V244)*(13/51) V200-(V200-V244)*(12/50) V201-(V201-V244)*(10.5/48.5) V202-(V202-V244)*(9.5/47.5) V215 V199-(V199-V244)*(14/51) V200-(V200-V244)*(13/50) V201-(V201-V244)*(11.5/48.5) V202-(V202-V244)*(10.5/47.5) V216 V199-(V199-V244)*(15/51) V200-(V200-V244)*(14/50) V201-(V201-V244)*(12.5/48.5) V202-(V202-V244)*(11.5/47.5) V217 V199-(V199-V244)*(16/51) V200-(V200-V244)*(15/50) V201-(V201-V244)*(13.5/48.5) V202-(V202-V244)*(12.5/47.5) V218 V199-(V199-V244)*(17/51) V200-(V200-V244)*(16/50) V201-(V201-V244)*(14.5/48.5) V202-(V202-V244)*(13.5/47.5) V219 V199-(V199-V244)*(18/51) V200-(V200-V244)*(17/50) V201-(V201-V244)*(15.5/48.5) V202-(V202-V244)*(14.5/47.5) V220 V199-(V199-V244)*(19/51) V200-(V200-V244)*(18/50) V201-(V201-V244)*(16.5/48.5) V202-(V202-V244)*(15.5/47.5) V221 V199-(V199-V244)*(20/51) V200-(V200-V244)*(19/50) V201-(V201-V244)*(17.5/48.5) V202-(V202-V244)*(16.5/47.5) V222 V199-(V199-V244)*(21/51) V200-(V200-V244)*(20/50) V201-(V201-V244)*(18.5/48.5) V202-(V202-V244)*(17.5/47.5) V223 V199-(V199-V244)*(22/51) V200-(V200-V244)*(21/50) V201-(V201-V244)*(19.5/48.5) V202-(V202-V244)*(18.5/47.5) V224 V199-(V199-V244)*(23/51) V200-(V200-V244)*(22/50) V201-(V201-V244)*(20.5/48.5) V202-(V202-V244)*(19.5/47.5) V225 V199-(V199-V244)*(24/51) V200-(V200-V244)*(23/50) V201-(V201-V244)*(21.5/48.5) V202-(V202-V244)*(20.5/47.5) V226 V199-(V199-V244)*(25/51) V200-(V200-V244)*(24/50) V201-(V201-V244)*(22.5/48.5) V202-(V202-V244)*(21.5/47.5) V227 V199-(V199-V244)*(26/51) V200-(V200-V244)*(25/50) V201-(V201-V244)*(23.5/48.5) V202-(V202-V244)*(22.5/47.5) V228 V199-(V199-V244)*(27/51) V200-(V200-V244)*(26/50) V201-(V201-V244)*(24.5/48.5) V202-(V202-V244)*(23.5/47.5) V229 V199-(V199-V244)*(28/51) V200-(V200-V244)*(27/50) V201-(V201-V244)*(25.5/48.5) V202-(V202-V244)*(24.5/47.5) V230 V199-(V199-V244)*(29/51) V200-(V200-V244)*(28/50) V201-(V201-V244)*(26.5/48.5) V202-(V202-V244)*(25.5/47.5) V231 V199-(V199-V244)*(30/51) V200-(V200-V244)*(29/50) V201-(V201-V244)*(27.5/48.5) V202-(V202-V244)*(26.5/47.5) V232 V199-(V199-V244)*(31.5/51) V200-(V200-V244)*(30.5/50) V201-(V201-V244)*(29/48.5) V202-(V202-V244)*(28/47.5) V233 V199-(V199-V244)*(32.5/51) V200-(V200-V244)*(31.5/50) V201-(V201-V244)*(30/48.5) V202-(V202-V244)*(29/47.5) V234 V199-(V199-V244)*(34.5/51) V200-(V200-V244)*(33.5/50) V201-(V201-V244)*(32/48.5) V202-(V202-V244)*(31/47.5) V235 V199-(V199-V244)*(35.5/51) V200-(V200-V244)*(34.5/50) V201-(V201-V244)*(33/48.5) V202-(V202-V244)*(32/47.5) V236 V199-(V199-V244)*(37.5/51) V200-(V200-V244)*(36.5/50) V201-(V201-V244)*(35/48.5) V202-(V202-V244)*(34/47.5) Page 186/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 99. Formulas for calculating gamma adjusting voltage (positive polarity) 2 (continued) Grayscale Voltage 0001 0010 Formula GSRP[3:0] 0100 1000 V237 V199-(V199-V244)*(38.5/51) V200-(V200-V244)*(37.5/50) V201-(V201-V244)*(36/48.5) V202-(V202-V244)*(35/47.5) V238 V199-(V199-V244)*(39.5/51) V200-(V200-V244)*(38.5/50) V201-(V201-V244)*(37/48.5) V202-(V202-V244)*(36/47.5) V239 V199-(V199-V244)*(41.5/51) V200-(V200-V244)*(40.5/50) V201-(V201-V244)*(39/48.5) V202-(V202-V244)*(38/47.5) V240 V199-(V199-V244)*(43.5/51) V200-(V200-V244)*(42.5/50) V201-(V201-V244)*(41/48.5) V202-(V202-V244)*(40/47.5) V241 V199-(V199-V244)*(45/51) V200-(V200-V244)*(44/50) V201-(V201-V244)*(42.5/48.5) V202-(V202-V244)*(41.5/47.5) V242 V199-(V199-V244)*(47/51) V200-(V200-V244)*(46/50) V201-(V201-V244)*(44.5/48.5) V202-(V202-V244)*(43.5/47.5) V243 V199-(V199-V244)*(49/51) V200-(V200-V244)*(48/50) V201-(V201-V244)*(46.5/48.5) V202-(V202-V244)*(45.5/47.5) V244 VINP9 V245 V244-(V244-V249)*(2/12.5) V244-(V244-V250)*(2/15.5) V244-(V244-V251)*(2/17.5) V244-(V244-V252)*(2/19.5) V246 V244-(V244-V249)*(4/12.5) V244-(V244-V250)*(4/15.5) V244-(V244-V251)*(4/17.5) V244-(V244-V252)*(4/19.5) V247 V244-(V244-V249)*(6.5/12.5) V244-(V244-V250)*(6.5/15.5) V244-(V244-V251)*(6.5/17.5) V244-(V244-V252)*(6.5/19.5) V248 V244-(V244-V249)*(9.5/12.5) V244-(V244-V250)*(9.5/15.5) V244-(V244-V251)*(9.5/17.5) V244-(V244-V252)*(9.5/19.5) V249 VINP10 V244-(V244-V250)*(12.5/15.5) V244-(V244-V251)*(12.5/17.5) V244-(V244-V252)*(12.5/19.5) V250 V249-(V249-V254)*(3/11.5) VINP10 V244-(V244-V251)*(15.5/17.5) V244-(V244-V252)*(15.5/19.5) V251 V249-(V249-V254)*(5/11.5) V250-(V250-V254)*(2/8.5) VINP10 V244-(V244-V252)*(17.5/19.5) V252 V249-(V249-V254)*(7/11.5) V250-(V250-V254)*(4/8.5) V251-(V251-V254)*(2/6.5) VINP10 V253 V249-(V249-V254)*(9.5/11.5) V250-(V250-V254)*(6.5/8.5) V251-(V251-V254)*(4.5/4.5) V252-(V252-V254)*(2.5/4.5) V254 VINP11 V255 VINP12 Page 187/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 117. Relationship between RAM data and output voltage Page 188/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 118. Relationship between source output and VCOM Page 189/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.3. GATE DRIVER Mobile Display Driver IC 4.3.1. Gate Driver The gate driver block includes gate control outputs (G1 to G480) which should be connected directly to the TFT-LCD. Page 190/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.4. OSCILLATOR- SYSTEM CLOCK GENERATOR Mobile Display Driver IC S6D05A0 has an on-chip oscillator which does not require any external components. This oscillator output signal is used for the system clock generation for internal display operation. 4.4.1. Oscillator Circuit The S6D05A0 can provide R-C oscillation. S6D05A0 internal oscillator does not need to attach the external resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the oscillator frequency control register setting. Since R-C oscillation stops during the sleep mode, power consumption can be reduced. Figure 119. Application diagram for oscillator circuitry Page 191/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.4.2. Frame Frequency Adjusting Function Mobile Display Driver IC The S6D05A0 has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (RTN & CRTN) during the LCD driver operation as the oscillation frequency is always same. When a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. When high-speed screen switching for an animated display is required, the frame frequency can be set high. The relationship between the LCD driving duty and the frame frequency is calculated by the following expression. The frame frequency can be adjusted in the RTN (1H period adjusting bit) and CRTN (1 RTN period adjusting bit) . Calculation Example: Figure 120. Formula for the frame frequency * Frame frequency ? - Line: 480 - B: Blank period (BP + FP): 34 - RTN :22 - CRTN :22 = Frame frequency = 60.295 Hz Page 192/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5. DISPLAY DATA RAM Mobile Display Driver IC This Chapter is based on the assumption that the number of 320-RGB source channels. 4.5.1. Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 8-8-8-bit), according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=319 (13Fh) and Y=0 to Y=479 (1DFh). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined onto which it will be written. The window is programmable via the command registers SC, SP designating the start address and EC, EP designating the end address. For example, the whole display contents will be written, and the window will be defined by the following values: SC=0 (0h), SP=0 (0h) and EC=319 (13Fh), EP=479 (1DFh). In vertical addressing mode (D5=1), the Y-address increments after each byte. After the last Y-address (Y=EP), Y wraps around to SP and X increments to address the next column. In horizontal addressing mode (D5=0), the Xaddress increments after each byte. After the last X-address (X=EC), X wraps around to SC and Y increments to address the next page. After every last address (X=EC and Y=EP) the address pointers wrap around to address (X=SC and Y=SP). For flexibility in handling a wide variety of display architectures, the commands “CASET, PASET” and “MADCTL” (see section 5 command lists) define flags D6 and D7, which allows mirroring of the X-address and Yaddress. All combinations of flags are allowed. Following Figure shows the available combinations of writing to the display RAM. When D6, D7 and D5 will be changed the data must be rewritten to the display RAM. For each image condition, the controls for the column and page counters apply as below: Table 100. Control for column and page counter Condition Column counter When RAMWR/RAMRD command is accepted Return to “start column(SC)” Complete pixel read/write action Increment by 1 The column counter value is large than “End column (EC)” Return to “start column(SC)” The page counter value is large than “End page (EP)” Return to “start column(SC)” Page counter Return to “start page(SP)” No change Increment by 1 Return to “start page(SP)” Page 193/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Display Data direction MADCTL parameter D5 D6 D7 Image in the host(MPU) Normal 0 0 0 Mobile Display Driver IC Image in the driver (DDRAM) Y-mirror 0 0 1 X-mirror 0 1 0 X-mirror 0 1 1 Y-mirror X-Y exchange 1 0 0 X-Y exchange 1 0 1 Y-mirror X-Y exchange 1 1 0 X-mirror H/W position(0,0) E X-Y address(0,0) X : PASET, B Y : CASET X-Y exchange X-mirror 1 1 1 Y-mirror Figure 121. Frame data write direction according to the MADCTL parameters (D5, D6 and D7) Note.D5, D6 and D7 are parameters of MADCTL command. D5(MV), D6(MX), D7(MY) Page 194/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5.2. Memory to Display Address Mapping 4.5.2.1. When Using 320RGB x 480 Resolution (MX = MY = RGB = ‘0’) Mobile Display Driver IC Pixel1 Pixel2 -- - Pixel 319 Pixel320 Source out S1 S2 --- S 319 S 320 R GB=0 R GB=1 R GB=0 R GB=1 R GB=0 R GB=1 R GB=0 R GB=1 RA MY = 0 MY = 1 0 479 1 478 2 477 3 476 4 475 5 474 6 473 7 472 8 471 9 470 10 469 11 468 R07-0 G 07 -0 B07-0 R17-0 G 17-0 B17-0 RGB order ----------------------- R318 7 -0 G 3187-0 B 318 R319 7- 0 7 -0 G 3197-0 B319 7- 0 SA ML= 0 ML = 1 0 479 1 478 2 477 3 476 4 475 5 474 6 473 7 472 8 471 9 470 10 469 11 468 Display pattern data 472 7 473 6 474 5 475 4 476 3 477 2 478 1 479 0 MX = 0 0 CA MX = 1 319 --- --- --- --- --- --- --- --- 1 --- 318 --- 472 7 473 6 474 5 475 4 476 3 477 2 478 1 479 0 318 319 1 0 Figure 122. Memory to display address mapping Note. RA = Page Address, CA = Column Address, SA = Scan Address, MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Page address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 195/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5.3. Normal Display On or Partial Mode On Mobile Display Driver IC 4.5.3.1. When using 320RGB x 480 resolution In this mode, the content of the frame memory within an area where column pointer is 00h to 13Fh and page pointer is 000h to 1DFh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, page pointer) = (0, 0). 1). Example for Normal Display On (D6 = D7 = D4 = ‘0’) S1 S2 S3 S4 S318 S319 S320 Figure 123. Example for normal display On (D6 = D7 = D4 = ‘0’) 2). Partial Display On: SR [15:0] = 04h, ER [15:0] = 1DCh, MADCTL Figure 124. Partial display on: SR [15:0] = 04h, ER [15:0] = 1DCh, MADCTL Page 196/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5.4. Command Definition is Independent of the IC Mount Position Mobile Display Driver IC Depending on how the MADCTL command is set, the top-bottom / left-right definitions are changed in the driver IC to adapt to the mounted form. 4.5.4.1. Model of LCD Module for the S6D05A0 The LCD module for the S6D05A0 is shown below. The top-bottom / left-right positions, RGB filter and white/ black back ground defined in this development specification are in accordance with the diagram shown below. Figure 125. Model of LCD module for the S6D05A0 In the case of MADCTL set to “00h,” the result of memory access is controlled as show below. Figure 126. An example of MADCTL(00h) Refer to the top-bottom / left-right relationship. (The non-bump plane is the surface.) If the driver IC is left-mounted or right-mounted due to the device structure, the display data RAM to LCD display data readout and gate scan direction should be set left-right rather than top-bottom. Page 197/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Case of bottom-mounted IC Mobile Display Driver IC Case of top-mounted IC (Example) MADCTL(00h) RAM address (0,0) Position Left-top RAM Access Direction Column Direction Column X direction Page RAMÆLCD readout direction Y direction Top to Bottom Gate line scan Direction Top to Bottom (Example) MADCTL(D0h) RAM address (0,0) Position Left-top RAM Access Direction Column Direction Column X direction Page RAMÆLCD readout direction Y direction Top to Bottom Gate line scan Direction Top to Bottom Case of left-mounted IC Case of right-mounted IC (Example) MADCTL(A0h) RAM address (0,0) Position Left-top RAM Access Direction Column Direction Column X direction Page Y direction RAMÆLCD readout direction Right to Left Gate line scan Direction Right to Left (Example) MADCTL(60h) RAM address (0,0) Position Left-top RAM Access Direction Column Direction Column X direction Page Y direction RAMÆLCD readout direction Left to Right Gate line scan Direction Left to Right Figure 127. Cases of panel position mounted IC Page 198/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5.4.2. 0-Address Position and RAM Access Scan Direction Refer to MADCTL Mobile Display Driver IC Written image and direction from the host to the frame memory memory Location ( 0,0 ) Image position on the frame memory with D7 = 0/1, D6 = 0/1 and D5 = 0 FRAME MEMORY memory Location ( 0,0 ) FRAME MEMORY 4 32 1 0 479 memor y location page counter (D7=1) 4 32 1 0 memor y location 4 32 1 0 page counter (D7=0) 01 23 4 479 479 479 D7 = 0 D6 = 0 D5 = 0 01234 319 memory location 01234 319 column counter (D 6= 0 ) memory Location ( 0,0 ) FRAME MEMORY D7 = 1 D6 = 0 D5 = 0 01234 319 memory location 01234 319 column counter (D 6= 0 ) memory Location ( 0,0 ) FRAME MEMORY 4 32 1 0 479 memor y location page counter (D7=1) 4 32 1 0 memor y location 4 32 1 0 page counter (D7=0) 01 23 4 479 479 479 D7 = 0 D6 = 1 D5 = 0 01234 319 memory location 319 43210 column counter (D 6= 1 ) D7 = 1 D6 = 1 D5 = 0 01234 319 memory location 319 43210 column counter (D 6= 1 ) Figure 128. 0-Address position and RAM access scan direction(D5=0) Page 199/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Written image and direction from the host to the frame memory Mobile Display Driver IC memory Location ( 0,0 ) Image position on the frame memory with D7 = 0/1, D6 = 0/1 and D5 = 1 FRAME MEMORY memory Location ( 0,0 ) FRAME MEMORY 4 32 1 0 479 memor y location page counter (D7=1) 4 32 1 0 memor y location 4 32 1 0 page counter (D7=0) 01 23 4 479 479 479 D7 = 0 D6 = 0 D5 = 1 01234 319 memory location 01234 319 column counter (D 6= 0 ) memory Location ( 0,0 ) FRAME MEMORY D7 = 1 D6 = 0 D5 = 1 01234 319 memory location 01234 319 column counter (D 6= 0 ) 4 32 1 0 479 memor y location page counter (D7=1) 4 32 1 0 memor y location 4 32 1 0 page counter (D7=0) 01 23 4 479 479 479 D7 = 0 D6 = 1 D5 = 1 01234 319 memory location 319 43210 column counter (D 6= 1 ) Figure 129. 0-Address position and RAM access scan direction(D5=1) Page 200/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.5.4.3. LCD Read Scan Direction and Common Scan Direction Refer to MADCTL Mobile Display Driver IC 0 Top to Bottom D4 : Memory Scan Direction 1 Bottom to Top Figure 130. LCD read scan direction and common scan direction 4.5.4.4. Partial Area and Scan Direction Refer to MADCTL, PTLAR A. Partial Mode RAM Partial area D4=0 1 ~ 100 D4=1 Figure 131. Partial area and scan direction Page 201/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.6. RESET 4.6.1. Registers Table 101. The default value of the register set Item After Power On Frame memory Random Sleep In/Out In Display On/Off Off Display mode (normal/partial) Normal Display Inversion On/Off Off Column: Start Address (SC) 0000h After Hardware Reset No Change In Off Normal Off 0000h Column: End Address (EC) 013Fh 013Fh Page: Start Address (SP) 0000h 0000h Page: End Address (EP) 01DFh (479d) 01DFh (479d) Partial: Start Address (SR) Partial: End Address (ER) Color Pixel Fomat Tearing: On/Off Tearing Effect Mode Memory Data Access Control (MY/MX/MV/ML/RGB) Idle Mode RDDPM (0Ah) RDDMADCTL (0Bh) RDDCOLMOD(0Ch) RDDSM (0Eh) RDDSDR (0Fh) WRDISBV(51h) RDDISBV(52h) WRCTRLD(53h) 0000h 01DFh (77h) IFPF:24bit/pixel VFPF:24bit/pixel Off 00h (Mode1) 0/0/0/0/0 Off 08h 00h 77h 00h 00h 00h 00h 00h 0000h 01DFh (77h) FPF:24bit/pixel VFPF:24bit/pixel Off 00h (Mode1) 0/0/0/0/0 Off 08h 00h 77h 00h 00h 00h 00h 00h Page 202/389 Mobile Display Driver IC After Software Reset No Change In Off Normal Off 0000h 013Fh (319d) (when MADCTL’s D5=0) 01DFh (479d) (when MADCTL’s D5=1) 0000h 01DFh (479d) (when MADCTL’s D5=0) 013Fh (319d) (when MADCTL’s D5=1) 0000h 01DFh No change Off 00h (Mode1) No Change Off 08h No Change No change 00h 00h 00h 00h 00h 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Item After Power On After Hardware Reset RDCTRLD(54h) 00h 00h WRCABC(55h) 00h 00h RDCABC(56h) 00h 00h WRCABCMB(5Eh) 00h 00h RDCABCMB(5Fh) 00h 00h MIECTL1(CAh) 808010h 808010h BCMODE(CBh) 01h 01h RDID1 (DAh) (MTP values) (MTP values) RDID2 (DBh) (MTP values) (MTP values) RDID3 (DCh) (MTP values) (MTP values) Note. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Powered-On Reset finishes within 10µs after both VDD3 & VCI are applied. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Mobile Display Driver IC After Software Reset 00h 00h 00h 00h 00h 808010h 01h (MTP values) (MTP values) (MTP values) Page 203/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 102. The default value of the register set 1(level II) Item Default value(Software/Hardware Reset) DSTB(B0h) 00h MIECTL2(CCh) 80_07_7C_01_3Fh MIECTL3(CDh) 03_14h MTPCTL (D0h) 0C_05h WRVCMOC (D1h) 00h WRVMLOC (D2h) 00h WRGVDOC (D3h) 00h WRID (D4h) 00_00_00h RDOFFSETC (D5h) MTP Value MDDICTL(E0h) 00h MDDILINK(E1h) 00_00h D_CON(EFh) WRPWD (F0h) DISCTL (F2h) PWRCTL (F3h) VCMCTL (F4h) SRCCTL (F5h) IFCTL (F6h) RPGAMCTL(F7h) RNPGAMCTL(F8h) GPGAMCTL(F9h) GNPGAMCTL(FAh) BPGAMCTL(FBh) BNPGAMCTL(FCh) GATECTL(FDh) 00h 04_30h 16_16_03_11_11_11_11_10_00_16_16h 00_00_26_26_02_00_00_00_00h 00_00_00_00_44h 10_11_06_F1_41_1Fh 80_10_00h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 00_0D_01_08_15_1E_1F_21_1B_17_10_15_06_22_22h 11_3B_00h Page 204/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.6.2. Moduls Input/Output/Bi-direction (I/O) Pads Mobile Display Driver IC 4.6.2.1. Output or Bi-directional (I/O) Pads Table 103. Reset states of output pads Output or Bi-directional pads When RESX is Low TE Low DB23 to DB0 (Output driver) High-Z (Inactive) After Power On Low High-Z (Inactive) After Hardware Reset Low High-Z (Inactive) After Software Reset Low High-Z (Inactive) SDA (Output driver) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) BC BC_CTL Low High Low High Low High Low High Note. There will be no output from DB23-DB0 during Power On/Off sequence, Hardware Reset and Software Reset 4.6.2.2. Input Pads Table 104. Reset states of input pads Input pads When RESX is Low During Power On Process RESX See Section - 4.1.1 CSX Input invalid Input invalid DCX Input invalid Input invalid WRX Input invalid Input invalid RDX Input invalid Input invalid DB23 to DB0 (Input driver) Input invalid Input invalid SDA (Input driver) Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid HSYNC Input invalid Input invalid Input valid Input valid Input valid VSYNC Input invalid Input invalid Input valid Input valid Input valid DOTCLK Input invalid Input invalid Input valid Input valid Input valid ENABLE Input invalid Input invalid Input valid Input valid Input valid During Power Off Process See Section 4.4.1 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input valid (RGB IF) Input invalid (The other cases) Input valid (RGB IF) Input invalid (The other cases) Input valid (RGB IF) Input invalid (The other cases) Input invalid Page 205/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 4.7. SLEEP-OUT COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE 4.7.1. Register Loading Detection Sleep-out command is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. Data of the EEPROM and register values of driver IC are compared as shown in the figure below. If those both values (EEPROM and register values) are the same, there is an inverted (=increased by 1) bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D7). If both those values are not same, this bit (D7) is not inverted (= not increased by 1). The flowchart of the function described above is as follows. Figure 132. Flowchart of register loading detection Note1. There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh) by the display module. Note2. EEPROM Means Internal MTP Page 206/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.7.2. Functionality Detection Mobile Display Driver IC Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= not increased by 1). The flow chart for this internal function is following: Figure 133. Flowchart of functionality detection Note: There is needed 120msec after Sleep Out –command, when there is changing from Sleep In –mode to Sleep Out –mode, before there is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out –mode. Page 207/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.8. NVM MEMORY CONTROL 4.8.1. MTP Control 4.8.1.1. MTP Control Flow Mobile Display Driver IC Figure 134. Flow of MTP load / read Page 208/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.8.1.2. Internal Control a. Using VCI for MTP Mobile Display Driver IC Figure 135. MTP initialization, erase and program (internal mode using VCI) Page 209/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 b. Using VCI1 for MTP Mobile Display Driver IC Figure 136. MTP initialization, erase and program (internal mode using VCI1) Page 210/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.8.1.3. External Control Mobile Display Driver IC Figure 137. MTP initialization, erase and program (external mode) Page 211/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.8.1.4. Timing of MTP Control Mobile Display Driver IC Figure 138. Timing of MTP program Figure 139. Timing of MTP load Note: When SLPOUT above MTP Load Action is also Excused Page 212/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.9. 8-COLOR DISPLAY MODE Mobile Display Driver IC An 8-color display mode is also provided by the S6D05A0. In an 8-color mode of operation, gray scale voltage generation (V0-V255) is halted to conserve power and the values of gamma micro-adjustment registers (PKP and PKN) become invalid. Also, the only MSB of each R, G, and B in the Frame Memory are displayed. (Refer to 39h Command) GRAM MSB ------------------------------------------------------------------------------------------------------------------------- LSB R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 1 Binary driver 1 Binary driver < G> 1 Binary driver GVDD AVSS GVDD AVSS GVDD AVSS RGB LCD Figure 140. 8-color display control. Page 213/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.10. INSTRUCTION SETUP FLOW 4.10.1. Power OFF Sequence Mobile Display Driver IC APON=0 Normal Display GON = 1 D1-0 = 10 Wait (more than 2 frame) GON = 0 D1-0 = 00 Power off SAP = 0 AON = 0 PON3 = 0 PON2 = 0 PON1 = 0 PON0 = 0 PON = 0 SLPIN Stop the Power Supply : VDD3 and VCI stop (any order ) APON=1 Power OFF Start ( without H /W Reset: Sleep-In mode ) SLPIN Display whole blank screen Drain Charge From LCD Panel Stop Booster Internal operation Stop Internal Oscillator Stop the Power Supply: VDD3 and VCI stop ( any order ) Power OFF End Power OFF End RESX Power OFF Start ( with H/W Reset ) RESX =0 Wait for more than10 us RESX =1 Stop the Power Supply: VDD3 and VCI stop (any order ) Power OFF End Figure 141. Power OFF sequence Page 214/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.11. TEARING EFFECT OUTPUT LINE Mobile Display Driver IC The Tearing Effect output line supplies a Panel synchronization signal to the MPU. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 4.11.1. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: Figure 142. Tearing effect output signal consists of V-blanking information only tvdh = The LCD display is not updated from the Frame Memory tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 480H-sync pulses per field. Figure 143. Tearing effect output signal consists of V-blanking and H-blanking information Figure 144. Tearing effect output signal Note. During Sleep In Mode, The Tearing Output Pin is active Low Page 215/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.11.2. Tearing Effect Line Timings The Tearing effect signal is described below. Mobile Display Driver IC Figure 145. Tearing effect output signal timing Table 105. AC characteristics of tearing effect signal (Idle mode off) Symbol Parameter min max unit Description tvdl Vertical timing low duration - - ms tvdh Vertical timing high duration - - us thdl Horizontal timing low duration - - us thdh Horizontal timing high duration - 500 us Note1. The timings in above Table apply when MADCTL D4=0 and D4=1 Note2. When TE MODE1 tvdh = VBP+VFP-1, When TE MODE2 tvdh = VBP+VFP-thdl Note3. When TE mode 2 in MPU Interface, the high period of TE signal in horizontal timing can be controlled in HBP+2. The rise and fall time of TE signal is stipulated to be equal to or less than 15ns. Figure 146. Rise and fall time of TE signal The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect. Page 216/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.11.2.1. Example 1: MPU write is faster than panel read. Mobile Display Driver IC Figure 147. Method 1 to avoid tearing effect Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image. Figure 148. Panel image refreshment of method 1 Page 217/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.11.2.2. Example 2 : MPU write is slower than panel read. Mobile Display Driver IC Figure 149. Method 2 to avoid tearing effect The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and to finish downloading during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. Figure 150. Panel image refreshment of method 2 Page 218/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 4.12. MIE FUNCTION Mobile Display Driver IC S6D05A0 has a special image enhancement function. MIE (Mobile Image Enhancement) reduces power consumption of backlight unit by adaptive enhancement of luminance and contrast. According the brightness enhancement rate of input image, the power reduction of BLU is controlled automatically. Figure 151. Flowchart of MIE function When MIE is enabled, MIE dynamically changes the brightness of backlight unit by on-chip BC(Backlight Control) Generator. Host can control the rate of BLU power reduction by setting RRC value (Refer to CAh Command.) When MIE is enabled, the enhanced data is outputted to Source block. Host processor should select movie or stillImage mode (Refer to 55h Command). Page 219/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC CHAPTER 5 COMMAND 5.1 Command List 5.2 Description of Level 1 Command 5.3 Description of Level 2 Command Page 220/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5 COMMAND Mobile Display Driver IC 5.1. COMMAND LIST 5.1.1. Level 1: Function Command Table 106. Instruction code D23~ Instruction R/W DCX D7 D8 SWRESET W 0 - 0 0 - 0 1 - - RDDIDIF R 1 - ID17 1 - ID27 1 - ID37 0 - 0 1 - - RDDST 1 R 1 - D31 - 0 1 - 0 1 - 0 0 - 0 RDDPM R 1 - - 1 - D7 0 RDD R 1 MADCTL 1 - 0 - - - D7 0 - 0 RDD R 1 - - COLMOD 1 - 0 0 - 0 RDDSM R 1 - - 1 - D7 D6 0 0 ID16 ID26 ID36 0 D30 D22 0 0 0 D6 0 D6 0 D6 0 D6 D5 0 0 ID15 ID25 ID35 0 D29 D21 0 D5 0 D5 0 D5 0 D5 0 0 D4 0 0 ID14 ID24 ID34 0 D28 D20 0 0 0 D4 0 D4 0 D4 0 0 D3 0 0 ID13 ID23 ID33 1 D27 D19 0 0 1 D3 1 D3 1 0 1 0 D2 0 1 ID12 ID22 ID32 0 D26 D18 D10 0 0 D2 0 0 1 D2 1 0 D1 0 0 ID11 ID21 ID31 0 0 D17 D9 0 1 0 1 0 0 D1 1 0 D0 1 0 ID10 ID20 ID30 1 0 D16 0 0 0 0 1 0 0 D0 0 0 Hex 01h 04h 09h 0Ah 0Bh 0Ch 0Eh Reference Page 221/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 107. Instruction code - (0F ~ 2E) D23~ Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 Hex Reference D8 0 - 0 0 0 0 1 1 1 1 0Fh RDDSDR R 1 - - - - - - - - - 1 - D7 D6 0 0 0 0 0 0 SLPIN W 0 - 0 0 0 1 0 0 0 0 10h SLPOUT W 0 - 0 0 0 1 0 0 0 1 11h PTLON W 0 - 0 0 0 1 0 0 1 0 12h NORON W 0 - 0 0 0 1 0 0 1 1 13h DISPOFF W 0 - 0 0 1 0 1 0 0 0 28h DISPON W 0 - 0 0 1 0 1 0 0 1 29h 0 - 0 0 1 0 1 0 1 0 2Ah 1 - SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 CASET W 1 - SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 1 - EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 1 - EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 0 - 0 0 1 0 1 0 1 1 2Bh 1 - SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 PASET W 1 - SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 1 - EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 1 - EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0 - 0 0 1 0 1 1 0 0 2Ch RAMWR W D23 ~ 1 D7 D6 D5 D4 D3 D2 D1 D0 D8 0 - 0 0 1 0 1 1 1 0 2Eh RAMRD 1 - - - - - - - - - R D23 ~ 1 D7 D6 D5 D4 D3 D2 D1 D0 D8 Page 222/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 108. Instruction code – (30 ~ 56) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 0 0 1 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 PTLAR W 1 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 1 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 TEOFF W 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 TEON W 1 0 0 0 0 0 0 0 M 0 0 0 1 1 0 1 1 0 MADCTL W 1 D7 D6 D5 D4 D3 0 0 0 IDMOFF W 0 0 0 1 1 1 0 0 0 IDMON W 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 1 0 COLMOD W 1 0 D6 D5 D4 0 D2 D1 D0 0 0 1 0 1 0 0 0 1 WRDISBV W MANB MANB MANB MANB MANB MANB MANB MANB 1 R7 R6 R5 R4 R3 R2 R1 R0 0 0 1 0 1 0 0 1 0 1 - - - - - - - - RDDISBV R BROU BROU BROU BROU BROU BROU BROU BROU 1 T7 T6 T5 T4 T3 T2 T1 T0 0 0 1 0 1 0 0 1 1 WRCTRLD W 1 - - BCTRL - DD BL - - 0 0 1 0 1 0 1 0 0 RDCTRLD R 1 - - - - - - - - 1 - - BCTRL - DD BL - - 0 0 1 0 1 0 1 0 1 WRCABC W MIE_M MIE_M 1 - - - - - - ODE1 ODE0 0 0 1 0 1 0 1 1 0 1 - - - - - - - - RDCABC R MIE_M MIE_M 1 - - - - - - ODE1 ODE0 Hex 30h 34h 35h 36h 38h 39h 3Ah 51h 52h 53h 54h 55h 56h Reference Page 223/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 109. Instruction code - (5E ~ DC) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 1 1 0 WRCABCMB W BRMI BRMI BRMI BRMI BRMI BRMI BRMI BRMI 1 N7 N6 N5 N4 N3 N2 N1 N0 0 0 1 0 1 1 1 1 1 RDCABCMB R 1 - - - - - - - - BRMI BRMI BRMI BRMI BRMI BRMI BRMI BRMI 1 N7 N6 N5 N4 N3 N2 N1 N0 0 1 1 0 0 1 0 1 0 1 RRC7 RRC6 RRC5 RRC4 RRC3 RRC2 RRC1 RRC0 1 IERC7 IERC6 IERC5 IERC4 IERC3 IERC2 IERC1 IERC0 MIECTL1 W ONOF SERC SERC SERC SERC SERC 1 - - F_DIM 4 3 2 1 0 M_EN 0 1 1 0 0 1 0 1 1 BCMODE W BC_M BC_M 1 - - - - - - ODE1 ODE0 0 1 1 0 1 1 0 1 0 RDID1 R 1 - - - - - - - - 1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 0 1 1 0 1 1 0 1 1 RDID2 R 1 - - - - - - - - 1 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 0 1 1 0 1 1 1 0 0 RDID3 R 1 - - - - - - - - 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Hex 5Eh 5Fh CAh CBh DAh DBh DCh Reference Undefined Commands are for the factory use of the display supplier. Commands 10h, 12h, 13h, 28h, 29h, 30h, 36h (Bit 4 only), 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Self Diagnostic Result (0Fh) commands are updated immediately both in Sleep In mode and Sleep Out mode. Note1. Only Level 1 Registers are readable in SPI, Level2 Registers are not readable in SPI. Page 224/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.1.2. Level 2: Function Command Mobile Display Driver IC Table 110. Instruction code – (B0 ~ CD) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 0 0 DSTB W 1 - - - - - - - DSTB 0 1 1 0 0 1 1 0 0 WINV WINV WINV WINV CAT1 CAT0 CST1 CST0 ADDR ADDR ADDR ADDR 08 07 06 05 WINV WINV WINV WINV WINV WINV WINV WINV ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 04 03 02 01 00 18 17 16 WINV WINV WINV WINV WINV WINV WINH WINH MIECTL2 W 1 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 15 14 13 12 11 10 08 07 WINH WINH WINH WINH WINH WINH WINH WINH ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 06 05 04 03 02 01 00 18 WINH WINH WINH WINH WINH WINH WINH WINH ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 17 16 15 14 13 12 11 10 0 1 1 0 0 1 1 0 1 BC_F BC_F BC_F BC_F BC_F BC_F BC_F - RQ_S RQ_S RQ_S RQ_S RQ_S RQ_S RQ_S MIECTL3 W EL6 EL5 EL4 EL3 EL2 EL1 EL0 1 BL_M BL_DR BL_DI BL_DI ODE_ - DT2 DT1 DT0 V_EN_ MM_S MM_S INSLP PAD TEP1 TEP0 HEX B0h CCh CDh Reference Page 225/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 111. Instruction code – (D0 ~ D5) Instruction R/W DCX D7 D6 0 1 1 - - MTPCTL R/W 1 - - 0 1 1 WRVCMOC R/W 1 - - 0 1 1 WRVMLOC R/W 1 - - 0 1 1 WRGVDOC R/W 1 - - WRID 0 R/W 1 0 1 ID17 ID27 ID37 1 - 1 ID16 ID26 ID36 1 - - - RDOFFSETC R 1 - - - - D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 ID_ MTP_ MTP_ MTP_ - - SEL SEL MODE EX MTP_ MTP_ MTP_ - - - ERB LOAD WRB 0 1 0 0 0 1 VCMO VCMO VCMO VCMO VCMO VCMO C5 C4 C3 C2 C1 C0 0 1 0 0 1 0 VMLO VMLO VMLO VMLO VMLO - C4 C3 C2 C1 C0 0 1 0 0 1 1 GVDO GVDO GVDO GVDO - 0 C4 C3 C2 C1 0 1 0 1 0 0 ID15 ID14 ID13 ID12 ID11 ID10 ID25 ID24 ID23 ID22 ID21 ID20 ID35 ID34 ID33 ID32 ID31 ID30 0 1 0 1 0 1 - - - - - - VCMO VCMO VCMO VCMO VCMO VCMO C_MT C_MT C_MT C_MT C_MT C_MT P5 P4 P3 P2 P1 P0 VMLO VMLO VMLO VMLO VMPO - C_MT C_MT C_MT C_MT C_MT P4 P3 P2 P1 P0 GVDO GVDO GVDO GVDO - C_MT C_MT C_MT C_MT 0 P4 P3 P2 P1 HEX D0h D1h D2h D3h D4h D5h Reference Page 226/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 112. Instruction code – (E0 ~ F2) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 1 0 0 0 0 0 E0h MDDICTL W MDDI VWAK 1 - - - - - - _SLP E_EN 0 1 1 1 0 0 0 0 1 E1h MDILINK W 1 WKL9 WKL8 WKL7 WKL6 WKL5 WKL4 WKL3 WKL2 WKL1 WKL0 WKF3 WKF2 WKF1 WKF0 - - 0 1 1 1 0 1 1 1 1 EFh DCON R/W D_C D_C 1 - - - - - GON ON1 ON0 0 1 1 1 1 0 0 0 0 F0h TEST TEST TEST TEST TEST TEST TEST TEST _DST _DST _DST _DST _DST _DST _DST _DST WR_PWD R/W 1 B7 B6 B5 B4 B3 B2 B1 B0 TEST TEST TEST TEST TEST TEST TEST TEST 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 1 0 F2h NRTN NRTN NRTN NRTN NRTN - - - 4 3 2 1 0 IPRTN IPRTN IPRTN IPRTN IPRTN - - - 4 3 2 1 0 - - - - IPINV IINV PINV NINV NVBP NVBP NVBP NVBP NVBP NVBP NVBP NVBP 7 6 5 4 3 2 1 0 NVFP NVFP NVFP NVFP NVFP NVFP NVFP NVFP DISCTL 7 6 5 4 3 2 1 0 R/W 1 IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP 7 6 5 4 3 2 1 0 IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP 7 6 5 4 3 2 1 0 - HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 - - - - - SM GS REV NCRT NCRT NCRT NCRT NCRT - - - N4 N3 N2 N1 N0 IPCRT IPCRT IPCRT IPCRT IPCRT - - - N4 N3 N2 N1 N0 Reference Page 227/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 113. Instruction code – (F3 ~ F4) Instruction R/W DCX D7 D6 D5 D4 D3 D2 0 1 1 1 1 0 0 - - - - - - - AON PON3 PON2 PON1 PON0 PWRCTL R/W 1 NDC NDC NDC NDC - - 31 30 21 20 IPDC IPDC IPDC IPDC - - 31 30 21 20 - - - - VC3 VC2 - IPBT2 IPBT1 IPBT0 - NBT2 D1 D0 1 1 - APON PON VCI1_ EN NDC NDC 11 10 IPDC IPDC 11 10 VC1 VC0 NBT1 NBT0 HEX F3h Reference NGV NGV NGV NGV NGV NGV NGV - D6 D5 D4 D3 D2 D1 D0 IPGV IPGV IPGV IPGV IPGV IPGV IPGV - D6 D5 D4 D3 D2 D1 D0 AB_ NAB2 IPAB2 - - - - - VCI1 A A 0 1 1 1 1 0 1 0 0 F4h NVCM NVCM NVCM NVCM NVCM NVCM NVCM - 6 5 4 3 2 1 0 IPVC IPVC IPVC IPVC IPVC IPVC IPVC - M6 M5 M4 M3 M2 M1 M0 VCMCTL R/W VCOM NVML NVML NVML NVML NVML NVML NVML 1 G 6 5 4 3 2 1 0 IPVML IPVML IPVML IPVML IPVML IPVML IPVML - 6 5 4 3 2 1 0 VCIRA VCIRA VCIRA - 0 VCIR2 VCIR1 VCIR0 2 1 0 Page 228/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 114. Instruction code – (F5 ~ F6) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 0 1 0 1 SEL_ - 360 GS_ - - EN - NGF SG IPSDT IPSDT IPSDT NSDT NSDT NSDT - - 2 1 0 2 1 0 - - - - SAP3 SAP2 SAP1 SAP0 SRCCTL NBLK NBLK IPBLK IPBLK NDISP NDISP IPDIS IPDIS R/W 1 _ _ _ _ _ _ P_ P_ VCIR1 VCIR0 VCIR1 VCIR0 CON1 CON0 CON1 CON0 HEX F5h Reference VCOM - _BLK - _OFF NBLK NBLK IPBLK IPBLK - _ _ _ _ CON1 CON0 CON1 CON0 GOC GOC GOC - - - OCM1 OCM0 M2 M1 M0 0 1 1 1 1 0 1 1 0 F6h IPM2 IPM1 IPM0 MDT1 MDT0 - VSM - IFCTL R/W 1 ENDIA VPL HPL DPL EPL - N - RIM RGB_ RGB_ RGB_ RGB_ - - - - DIV3 DIV2 DIV1 DIV0 Page 229/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 115. Instruction code – (F7) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 0 1 1 1 RGLP RGLP RRFP RRFP RRFP RRFP RRFP RRFP 1 0 5 4 3 2 1 0 ROSP ROSP ROSP ROSP ROSP ROSP - - 5 4 3 2 1 0 RPKP RPKP RPKP RPKP RPKP RPKP - - 05 04 03 02 01 00 RPKP RPKP RPKP RPKP RPKP RPKP - - 15 14 13 12 11 10 RPKP RPKP RPKP RPKP RPKP RPKP - - 25 24 23 22 21 20 RPKP RPKP RPKP RPKP RPKP RPKP - - 35 34 33 32 31 30 RPKP RPKP RPKP RPKP RPKP RPKP - - 45 44 43 42 41 40 RPGAMCTL R/W 1 - RPKP RPKP RPKP RPKP RPKP RPKP - 55 54 53 52 51 50 RPKP RPKP RPKP RPKP RPKP RPKP - - 65 64 63 62 61 60 RPKP RPKP RPKP RPKP RPKP RPKP - - 75 74 73 72 71 70 RPKP RPKP RPKP RPKP RPKP RPKP - - 85 84 83 82 81 80 RPKP RPKP RPKP RPKP RPKP RPKP - 95 94 93 92 91 90 RPKP RPKP RPKP RPKP RPKP RPKP - 105 104 103 102 101 100 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR P03 P02 P01 P00 P13 P12 P11 P10 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR P23 P22 P21 P20 P33 P32 P31 P30 HEX F7h Reference Page 230/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 116. Instruction code – (F8) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 0 0 0 RGLN RGLN RRFN RRFN RRFN RRFN RRFN RRFN 1 0 5 4 3 2 1 0 ROSN ROSN ROSN ROSN ROSN ROSN - - 5 4 3 2 1 0 RPKN RPKN RPKN RPKN RPKN RPKN - - 05 04 03 02 01 00 RPKN RPKN RPKN RPKN RPKN RPKN - - 15 14 13 12 11 10 RPKN RPKN RPKN RPKN RPKN RPKN - - 25 24 23 22 21 20 RPKN RPKN RPKN RPKN RPKN RPKN - - 35 34 33 32 31 30 RPKN RPKN RPKN RPKN RPKN RPKN - - 45 44 43 42 41 40 RNGAMCTL R/W 1 - RPKN RPKN RPKN RPKN RPKN RPKN - 55 54 53 52 51 50 RPKN RPKN RPKN RPKN RPKN RPKN - - 65 64 63 62 61 60 RPKN RPKN RPKN RPKN RPKN RPKN - - 75 74 73 72 71 70 RPKN RPKN RPKN RPKN RPKN RPKN - - 85 84 83 82 81 80 RPKN RPKN RPKN RPKN RPKN RPKN - - 95 94 93 92 91 90 RPKN RPKN RPKN RPKN RPKN RPKN - - 105 104 103 102 101 100 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR N03 N02 N01 N00 N13 N12 N11 N10 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR N23 N22 N21 N20 N33 N32 N31 N30 HEX F8h Reference Page 231/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 117. Instruction code – (F9) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX Reference 0 1 1 1 1 1 0 0 1 F9h GGLP GGLP GRFP GRFP GRFP GRFP GRFP GRFP 1 0 5 4 3 2 1 0 GOSP GOSP GOSP GOSP GOSP GOSP - - 5 4 3 2 1 0 GPKP GPKP GPKP GPKP GPKP GPKP - - 05 04 03 02 01 00 GPKP GPKP GPKP GPKP GPKP GPKP - - 15 14 13 12 11 10 GPKP GPKP GPKP GPKP GPKP GPKP - - 25 24 23 22 21 20 GPKP GPKP GPKP GPKP GPKP GPKP - - 35 34 33 32 31 30 GPKP GPKP GPKP GPKP GPKP GPKP - - 45 44 43 42 41 40 GPGAMCTL R/W 1 - GPKP GPKP GPKP GPKP GPKP GPKP - 55 54 53 52 51 50 GPKP GPKP GPKP GPKP GPKP GPKP - - 65 64 63 62 61 60 GPKP GPKP GPKP GPKP GPKP GPKP - - 75 74 73 72 71 70 GPKP GPKP GPKP GPKP GPKP GPKP - - 85 84 83 82 81 80 GPKP GPKP GPKP GPKP GPKP GPKP - 95 94 93 92 91 90 GPKP GPKP GPKP GPKP GPKP GPKP - 105 104 103 102 101 100 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR P03 P02 P01 P00 P13 P12 P11 P10 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR P23 P22 P21 P20 P33 P32 P31 P30 Page 232/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 118. Instruction code – (FA) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 0 1 0 GGLN GGLN GRFN GRFN GRFN GRFN GRFN GRFN 1 0 5 4 3 2 1 0 GOSN GOSN GOSN GOSN GOSN GOSN - - 5 4 3 2 1 0 GPKN GPKN GPKN GPKN GPKN GPKN - - 05 04 03 02 01 00 GPKN GPKN GPKN GPKN GPKN GPKN - - 15 14 13 12 11 10 GPKN GPKN GPKN GPKN GPKN GPKN - - 25 24 23 22 21 20 GPKN GPKN GPKN GPKN GPKN GPKN - - 35 34 33 32 31 30 GPKN GPKN GPKN GPKN GPKN GPKN - - 45 44 43 42 41 40 GNGAMCTL R/W 1 - GPKN GPKN GPKN GPKN GPKN GPKN - 55 54 53 52 51 50 GPKN GPKN GPKN GPKN GPKN GPKN - - 65 64 63 62 61 60 GPKN GPKN GPKN GPKN GPKN GPKN - - 75 74 73 72 71 70 GPKN GPKN GPKN GPKN GPKN GPKN - - 85 84 83 82 81 80 GPKN GPKN GPKN GPKN GPKN GPKN - - 95 94 93 92 91 90 GPKN GPKN GPKN GPKN GPKN GPKN - - 105 104 103 102 101 100 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR N03 N02 N01 N00 N13 N12 N11 N10 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR N23 N22 N21 N20 N33 N32 N31 N30 HEX FAh Reference Page 233/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 119. Instruction code – (FB) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 0 1 1 BGLP BGLP BRFP BRFP BRFP BRFP BRFP BRFP 1 0 5 4 3 2 1 0 BOSP BOSP BOSP BOSP BOSP BOSP - - 5 4 3 2 1 0 BPKP BPKP BPKP BPKP BPKP BPKP - - 05 04 03 02 01 00 BPKP BPKP BPKP BPKP BPKP BPKP - - 15 14 13 12 11 10 BPKP BPKP BPKP BPKP BPKP BPKP - - 25 24 23 22 21 20 BPKP BPKP BPKP BPKP BPKP BPKP - - 35 34 33 32 31 30 BPKP BPKP BPKP BPKP BPKP BPKP - - 45 44 43 42 41 40 BPGAMCTL R/W 1 - BPKP BPKP BPKP BPKP BPKP BPKP - 55 54 53 52 51 50 BPKP BPKP BPKP BPKP BPKP BPKP - - 65 64 63 62 61 60 BPKP BPKP BPKP BPKP BPKP BPKP - - 75 74 73 72 71 70 BPKP BPKP BPKP BPKP BPKP BPKP - - 85 84 83 82 81 80 BPKP BPKP BPKP BPKP BPKP BPKP - 95 94 93 92 91 90 BPKP BPKP BPKP BPKP BPKP BPKP - 105 104 103 102 101 100 BGSR BGSR BGSR BGSR BGRS BGRS BGRS BGRS P03 P02 P01 P00 P13 P12 P11 P10 BGSR BGSR BGSR BGSR BGRS BGRS BGRS BGRS P23 P22 P21 P20 P33 P32 P31 P30 HEX FBh Reference Page 234/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 120. Instruction code – (FC) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 0 0 BGLN BGLN BRFN BRFN BRFN BRFN BRFN BRFN 1 0 5 4 3 2 1 0 BOSN BOSN BOSN BOSN BOSN BOSN - - 5 4 3 2 1 0 BPKN BPKN BPKN BPKN BPKN BPKN - - 05 04 03 02 01 00 BPKN BPKN BPKN BPKN BPKN BPKN - - 15 14 13 12 11 10 BPKN BPKN BPKN BPKN BPKN BPKN - - 25 24 23 22 21 20 BPKN BPKN BPKN BPKN BPKN BPKN - - 35 34 33 32 31 30 BPKN BPKN BPKN BPKN BPKN BPKN - - 45 44 43 42 41 40 BNGAMCTL R/W 1 - BPKN BPKN BPKN BPKN BPKN BPKN - 55 54 53 52 51 50 BPKN BPKN BPKN BPKN BPKN BPKN - - 65 64 63 62 61 60 BPKN BPKN BPKN BPKN BPKN BPKN - - 75 74 73 72 71 70 BPKN BPKN BPKN BPKN BPKN BPKN - - 85 84 83 82 81 80 BPKN BPKN BPKN BPKN BPKN BPKN - - 95 94 93 92 91 90 BPKN BPKN BPKN BPKN BPKN BPKN - - 105 104 103 102 101 100 BGRS BGRS BGRS BGRS BGRS BGRS BGRS BGRS N03 N02 N01 N00 N13 N12 N11 N10 BGRS BGRS BGRS BGRS BGRS BGRS BGRS BGSR N23 N22 N21 N20 N33 N32 N31 N30 HEX FCh Reference Page 235/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 121. Instruction code – (FD) Instruction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX Reference 0 1 1 1 1 1 1 0 1 FDh 1 GATECTL R/W 1 - IPNO2 IPNO1 IPNO0 - NNO2 NNO1 NNO0 - - NL5 NL4 NL3 NL2 NL1 NL0 1 - - - SCN4 SCN3 SCN2 SCN1 SCN0 Note1. In Level1 and Level 2 register read action, if Interface mode is 80 MPU, 1-byte Dummy Read will be needed, Note2. When TEST[7:0] is “8’h5A” , D0h, D1h, D2h, D3h, D4h Registers are updated. Page 236/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2. DESCRIPTION OF LEVEL1 COMMAND 5.2.1. SWRESET: Software Reset (01h) Mobile Display Driver IC Inst/Para SWRESET Parameter Description Restriction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 0 0 0 0 0 1 01h No Parameter The Software Reset command resets the commands and parameters to their S/W Reset default values, and all the source & gate outputs are set to VSS (display off). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command It is necessary to wait for 5msec before sending new commands following the software reset. The display module loads all of display supplier’s factory default values to the registers during 5msec. Case APON=1 (If Software Reset is applied during Sleep Out mode, it is necessary to wait 120msec before sending Sleep Out command. Software Reset command cannot be sent during Sleep Out sequence.) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value N/A N/A N/A Page 237/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Case APON=1 SWRESET Flow Chart Display whole blank screen Set Commands to S/W Default Value Sleep In Mode Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 238/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.2. RDDIDIF: Read Display ID (04h) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDIDIF 0 0 0 0 0 0 1 0 0 04h Dummy Read 2nd parameter R 3rd parameter 4th parameter 1 X X X X X X X X X 1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 xx 1 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 xx 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 xx This read command returns 24-bit display identification information. The 1st parameter is dummy data. The 2nd parameter identifies the LCD module’s manufacturers. It is specified by a user. The 3rd parameter has 2 purposes. Bit7 (MSB) defines the type of a panel. 0=Driver (STN B/W), 1=Module (Color). Bit 6..0 are used to track the LCD module/driver version. It is defined by a panel Description supplier and updated each time; a version of the display is updated. The 4th parameter identifies the LCD module/driver. It is specified by a user. Restriction Register Availability Note. Commands RDID1/2/3(DAh, DBh, DCh) reads data corresponding to the parameters 2, 3, 4 of the command 04h, respectively. “X“ denotes “Don’t care” - When ID_SEL=1, RDDIDIF Read Values are MTP ID1/2/3 Values - When ID_SEL=0, RDDIDIF Read Values are D4h’s Register Values Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value ID1 ID2 ID3 (MTP value) (MTP value) (MTP value) (MTP value) (MTP value) (MTP value) (MTP value) (MTP value) (MTP value) Page 239/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 240/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.3. RDDST: Read Display Status (09h) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDST 0 0 0 0 0 1 0 0 1 09h Dummy Read 2nd parameter R 3rd parameter 4th parameter 5th parameter 1 X X X X X X X X X 1 D31 D30 D29 D28 D27 D26 0 0 xx 1 0 D22 D21 D20 D19 D18 D17 D16 xx 1 0 0 0 0 0 D10 D9 0 xx 1 0 0 D5 0 0 0 0 0 xx This command indicates the current status of the display as described in the table below: Bit Description Value D31 Booster Voltage Status “1”=Booster on, “0”=off D30 Page Address Order (MY) “1”=Decrement, “0”=Increment D29 Column Address Order (MX) “1”=Decrement, “0”=Increment “1”= Page/column exchange (MV=1), D28 Page/Column Exchange (MV) “0”= Normal (MV=0) D27 Vertical Refresh Order (ML) “1”=Decrement, “0”=Increment D26 RGB/BGR Order (RGB) “1”=BGR, “0”=RGB D25 Not Used “0” D24 Not Used “0” D23 Not Used “0” D22 “101”=16-bits/pixel D21 Interface Color Pixel Format “110”=18-bits/pixel Description D20 Definition (IFPF) "111"= 24-bits/pixel The Others = not defined D19 Idle Mode On/Off “1” = On, “0” = Off D18 Partial Mode On/Off “1” = On, “0” = Off D17 Sleep In/Out “1” = Out, “0” = In D16 Display Normal Mode On/Off “1” = Normal Display, “0” = Partial Display D15 Not Used “0” D14 Not Used “0” D13 Not Used “0” D12 Not Used “0” D11 Not Used “0” D10 Display On/Off “1” = On, “0” = Off D9 Tearing effect line on/off “1” = On, “0” = Off D8~D6 Gamma Curve Selection Fixed “000” D5 Tearing effect line mode “0” = mode1, V_Blanking only Page 241/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Restriction “1” = mode2, Both H & V-Blanking. D4 Not Used “0” D3 Not Used “0” D2 Not Used “0” D1 Not Used “0” D0 Not Used “0” Note: “X“ denotes “Don’t care” -D10 Read bit is valid in APON=1, It is invalid in APON=0 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value (D31 to D0) 0000_0000_0111_0001_0000 0000_0000_0000 0xxx_xxx0_0 xxx _0001_0000 0000_0000_0000 0000_0000_0111_0001_0000 0000_0000_0000 Flow Chart Legend Command Parameter Display Action Mode Page 242/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.4. RDDPM: Read Display Power Mode (0Ah) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDPM 0 0 0 0 0 1 0 1 0 0Ah Dummy Read R 2nd parameter 1 X X X X X X X 1 D7 D6 D5 D4 D3 D2 0 X X 0 xx This command indicates the current status of the display as described in the table below: Bit Description Value D7 Booster Voltage Status “1”=Booster on, “0”=off D6 Idle Mode On/Off “1” = Idle Mode On, “0”= idle Mode Off D5 Description D4 Partial Mode On/Off Sleep In/Out “1” = Partial Mode On, “0” = Partial Mode Off “1” = Sleep Out, “0” = Sleep In D3 Display Normal Mode On/Off “1” = Normal Display, “0” = Partial Display D2 Display On/Off “1” = Display On, “0” = Display Off D1 Not Used “0” D0 Not Used “0” Note. “X“ denotes “Don’t care” Restriction - D2 Read bit is valid in APON=1, It is invalid in APON=0 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 0000_1000 (08h) 0000_1000 (08h) 0000_1000 (08h) Page 243/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 244/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.5. RDDMADCTL: Read Display MADCTL (0Bh) Mobile Display Driver IC Inst/Para RDDMADCTL Dummy Read 2nd parameter Description Restriction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 0 0 0 1 0 1 1 0Bh R 1 X X X X X X X X X 1 D7 D6 D5 D4 D3 0 0 0 xx This command indicates the current status of the display MADCTL(memory address control) as described in the table below: Bit Description Value D7 Page Address Order “1”=Decrement, “0”=Increment D6 Column Address Order “1”=Decrement, “0”=Increment “1”= Page/column exchange (MV=1) D5 Page/Column Order (MV) “0”= Normal (MV=0) D4 Vertical fresh Order (ML) “1”=Decrement, “0”=Increment D3 RGB/BGR Order(RGB) “1”=BGR, “0”=RGB D2 Not Used “0” D1 Not Used “0” D0 Not Used “0” Note: “X“ denotes “Don’t care” Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h) Page 245/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 246/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.6. RDDCOLMOD: Read Display Pixel Format (0Ch) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 RDDCOLMOD 0 0 0 0 0 1 1 0 0 Dummy Read R 1 X X X X X X X X 2nd parameter 1 0 D6 D5 D4 0 D2 D1 D0 This command indicates the current status of the display as described in the table below: Bit Description Value D7 - D6 RGB Interface Color Format D5 (VFPF) D4 “0” (Not Used) “101”=16-bits/pixel “110”=18-bits/pixel "111"= 24-bits/pixel Others = not defined Description Restriction D3 - D2 Control Interface Color Format D1 (MPU Interface : IFPF) D0 Bit D7: Set to’0’. Bit D6~4 : RGB Interface Color Pixel format Definition Bit D3 : Set to ‘0’ Bit D2~0 : Control Interface Color Pixel Format Definition Note: “X“ denotes “Don’t care” - “0” (Not Used) “101”=16-bits/pixel “110”=18-bits/pixel "111"= 24-bits/pixel Others = not defined Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes HEX 0Ch X xx Default Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 0111_0111 (77h) No Change 0111_0111 (77h) Page 247/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 248/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.7. RDDSM: Read Display Signal Mode (0Eh) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDSM 0 0 0 0 0 1 1 1 0 0Eh Dummy Read R 1 X X X X X X X X X 2nd parameter 1 D7 D6 0 0 0 0 0 0 xx This command indicates the current status of the display signal mode as described in the table below: Bit Description Value D7 Tearing Effect Line On/Off “1” = On, “0” = Off D6 Tearing effect line mode “0” = Mode1 “1” = Mode2 D5 Not Used “0” Description D4 Not Used “0” D3 Not Used “0” D2 Not Used “0” D1 Not Used “0” D0 Not Used “0” Note: “X“ denotes “Don’t care” Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) Page 249/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 250/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.8. RDDSDR: Read Display Self-Diagnostic Result (0Fh) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDSDR 0 0 0 0 0 1 1 1 1 0Fh Dummy Read R 1 X X X X X X X X X 2nd parameter 1 D7 D6 0 0 0 0 0 0 xx This command indicates the current status of the display self-diagnostics as described in the table below: Bit Description Value D7 Register Loading Detection D6 Functionality Detection See section 4.7 D5 Not Used “0” Description D4 Not Used “0” D3 Not Used “0” D2 Not Used “0” D1 Not Used “0” D0 Not Used “0” Note: “X“ denotes “Don’t care” Restriction - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) Page 251/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 252/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.9. SLPIN: Sleep In (10h) Mobile Display Driver IC Inst/Para SLPIN Parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 0 1 0 0 0 0 10h No Parameter A Case (APON=1) This command causes the LCD module to enter the power saving mode. During this mode, the Booster, Internal display oscillator and panel scanning are not in operation. Description A Case (APON=0) This command causes halting OSC Operation. Restriction Register Availability MPU interface and memory are still in normal operation and the memory keeps its contents. This command has no effect when module is already in sleep in mode. Sleep In Mode can only exit by the Sleep Out Command (11h). It is necessary to wait for 5msec after SLPIN command, to send next command, It is allowing time for the supply voltages and clock circuits to stabilize. A Case (APON=1) It is necessary to wait for 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Page 253/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Default Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode Flow Chart A Case (APON=1) It takes about 120msec before it goes into Sleep-in Mode (Booster off state) after SLPIN command. The Booster States can be checked by RDDST(09h) command Bit 31. SPLIN Display whole blank screen (Automatic No effect to DISP ON/ OFF Commands) Drain charge from LCD panel Stop Booster Stop Internal Oscillator Sleep In Mode Legend Command Parameter Display Action Mode Page 254/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.10. SLPOUT: Sleep Out (11h) Mobile Display Driver IC Inst/Para SLPOUT Parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 0 1 0 0 0 1 11h No Parameter A Case (APON=1) This command turns off the sleep mode. During this mode, the Booster, the Internal display oscillator, and panel scanning are in normal operation. Description A Case (APON=0) This command causes starting OSC Operation. Restriction This command has no effect when the module is already in sleep out mode. Sleep Out Mode can only exit by the Sleep In Command (10h). It is necessary to wait for 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. S6D05A0 loads the default values of extended and test commands to the registers during this 5msec duration. There cannot be any abnormal visual effect on the display image if those default and register values are the same when this loading is done and when the S6D05A0 is already in Sleep Out –mode. S6D05A0 performs self-diagnostic during this 5msec. See also section 4.7. A Case (APON=1) It is necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent. Page 255/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode A Case (APON=1) It takes 120msec to be in Sleep Out mode (booster on mode) after SLPOUT command is issued. The booster on status can be checked by RDDST (09h) command Bit31. Flow Chart SPLOUT Start Internal Oscillator Strat Booster Charge Offset voltage for LCD Panel Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Commands) Display Memory contents in accordance with the current command table settings Sleep Out Mode Legend Command Parameter Display Action Mode Page 256/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.11. PTLON: Partial Display Mode On (12h) Mobile Display Driver IC Inst/Para PTLON Parameter Description Restriction Register Availability R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 0 1 0 0 1 0 12h No Parameter This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H). To leave Partial mode, the Normal Display Mode On command (13H) should be written. There is no abnormal visual effect during mode change between Normal mode On and Partial mode On. This command has no effect when Partial mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset See Partial Area (30h) Default Value Normal Mode On Normal Mode On Normal Mode On Page 257/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.12. NORON: Normal Display Mode On (13h) Mobile Display Driver IC Inst/Para NORON Parameter Description Restriction R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 0 1 0 0 1 1 13h No Parameter This command returns the display to normal mode. Turning normal display mode on means Partial mode off. Exiting from NORON can be done by the Partial mode On command (12h). There is no abnormal visual effect during the mode change from Normal mode On to Partial mode On. This command has no effect when Normal Display mode is active. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Flow Chart Status Power On Sequence S/W Reset H/W Reset See Partial Area for details of when to use this command. Default Value Normal Mode On Normal Mode On Normal Mode On Page 258/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.13. DISPOFF: Display Off (28h) Mobile Display Driver IC Inst/Para DISPOFF Parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 1 0 1 0 0 0 28h No Parameter This command turns on DISPLAY OFF mode. During this mode, the output from the Frame Memory is disabled and blank page is inserted. This command makes no change to the contents of frame memory. This command does not alter any other status. There will be no abnormal visible effect on the display. Exiting from this command can be done by Display On (29h) Description (Example) Restriction Register Availability This command has no effect when module is already in Display Off mode. When APON is Low, DISPOFF Command is ignored, and Display Status is controled by D_CON[1:0] Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off Page 259/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Display ON Mode DISPOFF Display OFF Mode Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 260/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.14. DISPON: Display On (29h) Mobile Display Driver IC Inst/Para DISPON Parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 W 0 0 0 1 0 1 0 0 1 No Parameter This command enables DISPLAY ON mode. Output from the Frame Memory is enabled. This command makes no change to the contents of frame memory. This command does not alter any other status. HEX 29h Description (Example) Restriction Register Availability This command has no effect when the module is already in Display On mode. When APON is Low, DISPON Command is ignored, Display Status is controled by D_CON[1:0] Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off Page 261/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Display OFF Mode DISPON Display ON Mode Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 262/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.15. CASET: Column Address Set (2Ah) Mobile Display Driver IC Inst/Para CASET 1st para 2nd para 3rd para 4th para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 1 0 1 SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 W 1 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 1 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 This command is used to define the area of the frame memory where MPU can access. This command does not alter any other status. The value of SC [15:0] and EC [15:0] are referred when RAMWR command is issued. Each value represents one column line of the Frame Memory. HEX 2Ah *Note 1 *Note 1 (Example) Description Restriction SC [15:0] always must be equal to or less than EC [15:0]. Note1. When SC [15:0] or EC [15:0] is greater than maximum address like below, data of out of range will be ignored. (Parameter range: 0 ≤ SC [15:0] ≤ EC [15:0] ≤ 359 (0167h)): MV=”0” (Parameter range: 0 ≤ SC [15:0] ≤ EC [15:0] ≤ 479 (01DFh)): MV=”1” Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset SC[15:0] 0000h 0000h 0000h Default Value EC[15:0] EC[15:0] (MV=0) (MV=1) 013Fh (319d) 013Fh(319d) 01DFh(479d) 013Fh (319d) Page 263/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 264/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.16. PASET: Page Address Set (2Bh) Mobile Display Driver IC Inst/Para PASET 1st para 2nd para 3rd para 4th para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 1 1 1 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 W 1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 1 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 1 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 This command is used to define the area of the frame memory where MPU can access. This command makes no change on the other driver status. The value of SP [15:0] and EP [15:0] is referred when RAMWR command is issued. Each value represents one column line of the Frame Memory. HEX 2Bh *Note 1 *Note 1 (Example) Description Restriction SP [15:0] should be equal to or less than EP [15:0] Note. 1. When SP [15:0] or EP [15:0] are greater than maximum Page address like below, any data out of range will be ignored.(Parameter range: 0 ≤ SP [15:0] ≤ EP [15:0] ≤ 479 (01DFh)): MV=”0” (Parameter range: 0 ≤ SP [15:0] ≤ EP [15:0] ≤ 359 (0167h)): MV=”1” Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset SP[15:0] 0000h 0000h 0000h Default Value EP[15:0] EP[15:0] (MV=0) (MV=1) 01DFh (479d) 01DFh(479d) 013Fh (319d) 01DFh (479d) Page 265/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 266/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.17. RAMWR: Memory Write (2Ch) Mobile Display Driver IC Inst/Para RAMWR 1st para : Nth para D23~ R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 D8 HEX 0 X 0 0 1 0 1 1 0 0 2Ch D123 000000h~ 1 D17 D16 D15 D14 D13 D12 D11 D10 ~18 FFFFFFh W Dx 000000h~ 1 Dx Dx Dx Dx Dx Dx Dx Dx ~Dx FFFFFFh Dn23 000000h~ 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 ~n8 FFFFFFh This command is used to transfer data from MPU to the frame memory. This command makes no change to the other status of the driver. Description When this command is issued, the Column register and the Page register are programmed to the Start Column/Start Page positions. The Start Column/Start Page positions are different in accordance with MADCTL setting. (See section 4.5.2) Restriction Then D [23:0] is stored in the frame memory, the Column register and the Page register increments as in section 4.5.2 Sending any other command can stop the Frame Write. In all color modes, there is no restriction on the length of the parameters. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared Page 267/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter Display Action Mode Page 268/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.18. RAMRD: Memory Read (2Eh) Mobile Display Driver IC D23~ Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 D8 HEX RAMRD 0 X 0 0 1 0 1 1 1 0 2Eh Dummy read 1 X X X X X X X X X XX 2nd para D123 000000h~ 1 D17 D16 D15 D14 D13 D12 D11 D10 ~8 FFFFFFh R Dx 000000h~ : 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 ~Dx FFFFFFh (N+1)th para Dn23 000000h~ 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 ~8 FFFFFFh This command is used to transfer data from the frame memory to MPU. This command makes no change to the other driver status. Description With this command, the column register and the Page register are programmed to the Start Column/Start Page positions.The Start Column/Start Page positions are different in accordance with MADCTL setting. (See section 4.5.2) Then D[23:0] is read back from the frame memory, and the column register and the Page register increments as in section 4.5.2 Frame Read can be cancelled by sending any other command. Restriction See section 3.2 “Display Data Format” for color coding. Note: “X“ denotes “Don’t care" - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared Page 269/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Legend Command Parameter D is p la y Action Mode Page 270/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.19. PTLAR: Partial Area (30h) Mobile Display Driver IC Inst / Para R/W PLTAR 1st para 2nd para W 3rd parar 4th para DCX D7 D6 D5 D4 D3 D2 D1 0 0 0 1 1 0 0 0 1 SR15 SR14 SR13 SR12 SR11 SR10 SR9 1 SR7 SR6 SR5 SR4 SR3 SR2 SR1 1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 1 ER7 ER6 ER5 ER4 ER3 ER2 ER1 D0 HEX 0 30h SR8 0000h~ SR0 01DFh ER8 0000h~ 01DFh ER0 This command defines the display area of the partial display mode. There are 4 parameters associated with this command. The 1’st & 2’nd parameters define the Start Row (SR) and the 3’rd and 4’th parameters define the End Row (ER), as illustrated in the figures below. SR and ER refer to the Frame Memory Row address counter. If End Row > Start Row when MADCTL D4=0 If End Row > Start Row when MADCTL D4=1: Description If End Row < Start Row when MADCTL D4=0: If End Row = Start Row, then the Partial Area will be one Row. SR[15:0] and ER[15:0] should have the range below Restriction (Parameter range: 0 ≤ SR[15:0], ER[15:0] ≤ 479(01DFh) Page 271/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Mobile Display Driver IC Availability Yes Yes Yes Yes Yes Default Value SR[15:0] ER[15:0] 0000h 01DFh 0000h 01DFh 0000h 01DFh Flow Chart Page 272/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.20. TEOFF: Tearing Effect Line OFF (34h) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX TEOFF W 0 0 0 1 1 0 1 0 0 34h parameter No Parameter Description This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction This command has no effect when Tearing Effect output is already OFF. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Off Off Off Flow Chart Page 273/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.21. TEON: Tearing Effect Line ON (35h) Mobile Display Driver IC Inst / Para TEON parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 0 1 1 0 1 0 1 35h W 1 0 0 0 0 0 0 0 M xx This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit D4. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. When M=0: The Tearing Effect Output line consists of V-Blanking information only. Description When M=1: The Tearing Effect Output line consists of both V-Blanking and H-Blanking Information. Restriction See Section 4.11 for more information. Note. During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. This command has no effect when Tearing Effect output is already OFF. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Tearing effect off & M=0 Tearing effect off & M=0 Tearing effect off & M=0 Page 274/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Page 275/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.22. MADCTL: Memory Data Access Control (36h) Mobile Display Driver IC Inst / Para MADCTL parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 0 0 0 1 1 0 1 1 W 1 D7 D6 D5 D4 D3 0 0 This command defines the read/write scanning direction of the frame memory. This command makes no change on the other driver status. D0 HEX 0 36h 0 xx Description Bit Name Description D7 Page Address order(MY) These 3-bits control MPU for the memory D6 Column Address order(MX) write/read direction. D5 Page/Column exchange(MV) D4 Vertical refresh order(ML) LCD Vertical refresh direction control Color selector refresh direction control D3 RGB-BGR order(RGB) (0=RGB color filter panel, 1=BGR color filter panel) Note1. D3 setting is effective When display the panel, not Memory write action Restriction D2, D1 and D0 of the 1st parameter are set to ‘00’ internally. When GS=1, Do not set D4 to 1, When NL is not 480 line, Set D4 to 0. Page 276/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Mobile Display Driver IC Availability Yes Yes Yes Yes Yes Default Value D7=0, D6=0, D5=0, D4=0, D3=0, D2=0 No Change D7=0, D6=0, D5=0, D4=0, D3=0, D2=0 Flowchart Page 277/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.23. IDMOFF: Idle Mode Off (38h) Mobile Display Driver IC Inst / Para IDMOFF Parameter Description Restriction R/W DCX D7 D6 D5 D4 D3 D2 D1 W 0 0 0 1 1 1 0 0 No Parameter This command turns Idle mode off. There will be no abnormal visible effect during the mode transition of the display. During the idle off mode, 1. LCD can display maximum 16M-colors. 2. Normal frame frequency is applied. This command has no effect when module is already in idle off mode. D0 HEX 0 38h Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode Off Idle Mode Off Idle Mode Off Flowchart Page 278/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.24. IDMON: Idle Mode On (39h) Mobile Display Driver IC Inst / Para IDMON Parameter R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX W 0 0 0 1 1 1 0 0 1 39h No Parameter This command turns Idle mode on. (Refer to section 4.9 8-Color mode) There will be no abnormal visible effect during mode transition. During the idle on mode, 1. Color expression is reduced to 8-color. 8-color is displayed by MSB of each R, G, and B in the Frame Memory. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command (Example) Description Restriction Color Black R7R6R5R4R3R2R1R0 0XXXXXXX Blue 0XXXXXXX Red 1XXXXXXX Magenta 1XXXXXXX Green 0XXXXXXX Cyan 0XXXXXXX Yellow 1XXXXXXX White 1XXXXXXX Note: “X“ denotes “Don’t care” G7G6G5G4G3G2G1G0 0XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX 1XXXXXXX This command has no effect when module is already in idle off mode. B7B6B5B4B3B2B1B0 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 1XXXXXXX Page 279/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset Mobile Display Driver IC Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off Flow Chart Page 280/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.25. COLMOD: Interface Pixel Format (3Ah) Mobile Display Driver IC Inst / Para COLMOD Parameter Description Restrictions D/CX WRX RDX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 ↑ 1 0 0 1 1 1 0 1 0 3Ah 1 ↑ 1 0 D6 D5 D4 0 D2 D1 D0 XX This command is used to define the format of RGB picture data, which is to be transferred via the MPU interface. The formats are as shown in the table below. Bit Description Value D7 - “0” (Not Used) D6 “101”=16-bits/pixel D5 RGB Interface Color Format “110”=18-bits/pixel (VFPF) D4 "111"= 24-bits/pixel Others = not defined D3 - “0” (Not Used) D2 “101”=16-bits/pixel D1 Control Interface Color Format “110”=18-bits/pixel (IFPF) D0 "111"= 24-bits/pixel Others = not defined Note. In 16-bit/pixel or 18-bit/pixel mode, display data is expended to 24bit data. Refer to Section 3.2.1 12-bits/pixel (4096 color mode) is not supported. There is no visible effect until the frame memory is written. Register Availability Status Normal mode on, Idle mode off, Sleep out Normal mode on, Idle mode on, Sleep out Partial mode on, Idle mode off, Sleep out Partial mode on, Idle mode on, Sleep out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value 77h No change 77h Page 281/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Flow Chart Mobile Display Driver IC Page 282/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.26. WRDISBV: Write Manual Brightness (51h) Mobile Display Driver IC Inst/Para WRDISBV 1st para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 1 0 1 0 0 0 1 51 MAN MAN MAN MAN MAN MAN MAN MAN W 1 BR BR BR BR BR BR BR BR - [7] [6] [5] [4] [3] [2] [1] [0] This command is used to set the manual brightness value. If the manual brightness is used (BCMODE = “01” or “11”), the value of register “MANBR[7:0] is selected or merged with the MIE brightness to generate BC. Table 122. MANBR [7:0] MANBR[7:0] 0000_0000 0000_0001 0000_0010 0000_0011 … 1111_1100 1111_1101 1111_1110 1111_1111 Brightness Level 0 1 2 3 … 252 253 254 255 Status Initial Default Value MANBR[7:0] = 0000_0000 Figure 152. Manual brightness The display brightness level is calculated with the following formula. Figure 153. Calculation formula Page 283/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 The MIE brightness has transition time A and the manual brightness has transition time B. The maximum transition time is transition time C (C A + B). Mobile Display Driver IC Manual brightness MIE brightness Display brightness Figure 154. Example of manual brightness Table 123. Example of manual brightness Operation Mode Manual Brightness Case 1 85 % Case 2 60 % Case 3 85 % MIE Brightness 80 % 70 % 90 % Display Brightness 68 % 42 % 76.5 % Page 284/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.27. RDDISBV : Read Display Brightness (52h) Mobile Display Driver IC Inst/Para RDDISBV Dummy Read 1st para R/W R DCX 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 1 0 X X X X X X X X BROU BROU BROU BROU BROU BROU BROU BROU T7 T6 T5 T4 T3 T2 T1 T0 HEX 52 X xx This command is used to read the display brightness value. It is a real brightness value of BC output which is calculated with MIE brightness and manual brightness. The value of this register is updated after display V-sync and host can read exact value after display V-sync. Table 124. BROUT[7:0] BROUT[7:0] 0000_0000 0000_0001 0000_0010 0000_0011 … 1111_1100 1111_1101 1111_1110 1111_1111 Brightness Level 0 1 2 3 … 252 253 254 255 Status Initial Default Value BROUT[7:0] = 0000_0000 Page 285/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.28. WRCTRLD: Write BL Control (53h) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX WRCTRLD 0 0 1 0 1 0 0 1 1 53 W 1st para 1 0 0 BCTRL 0 DD BL 0 0 - 5.2.28.1. BCTRL This register is used to enable the backlight control block. If BCTRL is turned off, the BL control block is not working and BC output is fixed to low. Table 125. BCTRL BCTRL 0 1 BL Control Off On Status Initial Default Value BCTRL = 0 5.2.28.2. DD This register is used to enable the manual brightness dimming function. The manual brightness should be changed smoothly for preventing a visible artifact, e.g. flicker. So the dimming function is needed when the transition of input manual brightness is fast to make a visible artifact. When the manual dimming is enabled, the new manual brightness value has to be changed after former dimming transition is finished. The transition time is controlled by DT[2:0]. Table 126. DD DD 0 1 Manual Dimming Function Off On Status Initial Default Value DD = 0 “” “” Figure 155. Manual dimming function Page 286/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.28.3. BL Mobile Display Driver IC This register is used to enable the BC output. Even if the value of BL is “0”, the backlight control block is working when BCTRL is “1”. And the host can read the display brightness value (BROUT[7:0]) and control the BLU directly. BL register is valid in SLPOUT State. Table 127. BL BL 0 1 BC state Low Active Status Initial Default Value BL = 0 Page 287/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.2.29. Read BL Control (54h) Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDCTRLD 0 0 1 0 1 0 1 0 0 54 Dummy Read R 1 X X X X X X X X X 1st para 1 0 0 BCTRL 0 DD BL 0 0 - This command is used to read BL control register. For details, refer to Write BL Control (53h). Status Initial Default Value BCTRL=0 DD=0 BL=0 Page 288/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.30. WRCABC : Write MIE Mode (55h) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX WRCABC 0 0 1 0 1 0 1 0 1 55 1st para MIE_ MIE_ W 1 0 0 0 0 0 0 MODE MODE - [1] [0] This command is used to select the operation mode of MIE. If the MIE is off mode, the BLU brightness value of MIE is set to 255. Table 128. MIE_MODE[1:0] MIE_MODE[1:0] 00 01 10 11 Operation Mode Off UI (User Interface) Still Image Moving Image Status Initial Default Value MIE_MODE[1:0] = 00 Page 289/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.2.31. Read MIE Mode (56h) Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDCABC 0 0 1 0 1 0 1 1 0 56 Dummy Read 1 X X X X X X X X X 1st para R MIE_ MIE_ 1 0 0 0 0 0 0 MODE MODE - [1] [0] This command is used to read MIE mode register. For details, refer to Write MIE Mode (55h). Status Initial Default Value MIE_MODE[1:0] = 00 Page 290/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.32. WRCABCMB: Write Minimum Brightness (5Eh) Mobile Display Driver IC Inst/Para R/W WRCABCMB W 1st para DCX 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 BRMI N7 1 BRMI N6 0 BRMI N5 1 BRMI N4 1 BRMI N3 1 BRMI N2 1 BRMI N1 0 BRMI N0 HEX 5E - This command is used to set the minimum brightness value. The MIE function is automatically reduced the backlight brightness based on the content of image. In the case of the combination with the manual brightness setting, the display brightness can be too dark. It must affect to image quality degradation. So the minimum brightness setting is used to avoid too much brightness reduction. When the MIE is activated, the display brightness can not be reduced less than the value of minimum brightness setting. The image processing function is worked as normal, even if the display brightness can not be decreased by the minimum brightness setting. This function of the manual brightness setting does not affect to the other functions. The smooth transition and dimming function can be worked as normal. The manual brightness shouldn’t be set less than the minimum brightness. When the BL control block is turned off (BCTRL=0), the MIE minimum brightness setting is ignored. Manual brightness MIE brightness Minimum brightness Figure 156. Example of minimum brightness Table 129. Example of minimum brightness ( Minimum brightness = 20%) Operation Manual MIE Calculated Display Mode Brightness Brightness Brightness Case 1 50 % 70 % 35% Case 2 20 % 70 % 14% Case 3 50 % 70 % 35% Display Brightness 35 % 20 % 35 % Page 291/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 130. BRMIN[7:0] BRMIN[7:0] 0000_0000 0000_0001 0000_0010 0000_0011 … 1111_1100 1111_1101 1111_1110 1111_1111 Status Initial Mobile Display Driver IC Brightness Level 0 1 2 3 … 252 253 254 255 Default Value BRMIN[7:0] = 0000_0000 Page 292/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.33. Read Minimum Brightness (5Fh) Mobile Display Driver IC Inst/Para RDCABCMB Dummy Read 1st para R/W R DCX 0 1 1 D7 0 X BRMI N7 D6 1 X BRMI N6 D5 0 X BRMI N5 D4 1 X BRMI N4 D3 1 X BRMI N3 D2 1 X BRMI N2 D1 1 X BRMI N1 D0 1 X BRMI N0 HEX 5F X - This command is used to read Minimum Brightness register. For details, refer to Write Minimum Brightness (5Eh). Status Initial Default Value BRMIN[7:0] = 0000_0000 Page 293/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.34. MIECTRL1: Write MIE Control 1 (CAh) Mobile Display Driver IC Inst/Para MIECTL1 1st para 2nd para 3rd para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 0 1 0 1 0 CA RRC RRC RRC RRC RRC RRC RRC RRC 1 - [7] [6] [5] [4] [3] [2] [1] [0] IERC IERC IERC IERC IERC IERC IERC IERC W 1 - [7] [6] [5] [4] [3] [2] [1] [0] ONOF SERC SERC SERC SERC SERC 1 0 0 F_DIM - [4] [3] [2] [1] [0] M_EN 5.2.34.1. RRC[7:0] This register is used to adjust the reduction rate of the backlight power. Figure 157. Power reduction rate The Power Reduction Rate is the power reduction rate by the MIE algorithm. The Reduction range is from ‘0’ (no reduction) to two times of the contents adaptive backlight power. To increase the value of RRC, more backlight power can be reduced but the displayed image become darker. The other way, brighter image is obtained by decreasing the value of RRC. Figure 158. Example of RRC Page 294/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 131. RRC[7:0] RRC[7:0] 0000_0000 0000_0001 0000_0010 … 1000_0000 … 1111_1101 1111_1110 1111_1111 Status Initial 5.2.34.2. IERC[7:0] This register is used to adjust the image enhancement rate. Mobile Display Driver IC Adjusted Power Reduction Rate Power Reduction Rate x 0/128 Power Reduction Rate x 1/128 Power Reduction Rate x 2/128 … Power Reduction Rate x 128/128 … Power Reduction Rate x 253/128 Power Reduction Rate x 254/128 Power Reduction Rate x 255/128 Default Value RRC[7:0] = 1000_0000 Figure 159. Image enhancement rate If the value of IERC is ‘0’, there is no enhancement in output image. If its value is ‘255’, the enhancement rate is two times of Image Enhancement Rate. If the value of IERC is increased, brighter image is obtained but the quality of displayed image may be decreased. The other way, if the value of IERC register is decreased, the quality of image will be increased. Figure 160. Example of IERC Page 295/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 132. IERC[7:0] IERC[7:0] 0000_0000 0000_0001 0000_0010 … 1000_0000 … 1111_1101 1111_1110 1111_1111 Status Initial 5.2.34.3. ONOFF_DIMM_EN Mobile Display Driver IC Adjust Image Enhancement Rate Image Enhancement Rate x 0/128 Image Enhancement Rate x 1/128 Image Enhancement Rate x 2/128 … Image Enhancement Rate x 128/128 … Image Enhancement Rate x 253/128 Image Enhancement Rate x 254/128 Image Enhancement Rate x 255/128 Default Value IERC[7:0] = 1000_0000 This register is used to enable the on/off dimming function of MIE. The MIE has a dimming function for preventing abnormal visible artifacts when the MIE is turning on or off. If the ONOFF_DIMM_EN is “1”, the MIE is smoothly turning on or off. When the ONOFF_DIMM_EN is “0”, the MIE is turning on or off immediately. The transition time is controlled by CST[1:0]. If the MIE mode is changed during on/off dimming transition, it will be updated after finishing the dimming transition. Table 133. ONOFF_DIMM_EN ONOFF_DIMM_EN 0 1 Status Initial On / Off Dimming Function Disable Enable Default Value ONOFF_DIMM_EN = 0 Figure 161. Example of MIE on / off dimming transition control Page 296/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.34.4. SERC[4:0] This register is used to adjust the Image Saturation Enhancement Rate. Mobile Display Driver IC Figure 162. Saturation enhancement rate If the value of SERC is ‘0’, there is no saturation enhancement in output image. If the value of SERC is increased, the saturation enhancement rate will be increased and more vivid image is obtained. The other way, if the value of SERC is decreased, the saturation enhancement rate will be decreased. 0 16 31 SERC[5:0] Figure 163. Example of SERC Table 134. SERC[4:0] SERC[4:0] 00000 00001 00010 … 10000 … 11101 11110 11111 Adjust Saturation Enhancement Rate Saturation Enhancement Rate x 0/16 Saturation Enhancement Rate x 1/16 Saturation Enhancement Rate x 2/16 … Saturation Enhancement Rate x 16/16 … Saturation Enhancement Rate x 29/16 Saturation Enhancement Rate x 30/16 Saturation Enhancement Rate x 31/16 Status Initial Default Value SERC[4:0] = 10000 Page 297/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.35. BCMODE: Write BL Control Mode (CBh) Mobile Display Driver IC Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX BCMODE 0 1 1 0 0 1 0 1 1 CB W BC_M BC_M 1st para 1 0 0 0 0 0 0 - ODE1 ODE0 This command is used to select the source of brightness value for the display brightness calculation. Table 135. BC_MODE[1:0] BC_MODE[1:0] 00 01 10 11 Brightness Source Setting disabled Manual Brightness MIE Brightness Merged Brightness (MIE + Manual) Status Initial Default Value BC_MODE[1:0] = 01 Page 298/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.36. RDID1: Read ID1 Value (DAh) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 RDID1 0 1 1 0 1 1 0 Dummy read R 2nd Para 1 X X X X X X 1 ID17 ID16 ID15 ID14 ID13 ID12 Description This read byte identifies the LCD module’s manufacturer. Note. “X“ denotes “Don’t care” Restrictions - When ID_SEL=1, RDID1 Read Values are MTP ID1 Values - When ID_SEL=0, RDID1 Read Values are D4h’s 1st Parameter Values D1 1 X ID11 D0 0 X ID10 HEX DAh X xx Register Availability Status Normal mode on, Idle mode off, Sleep out Normal mode on, Idle mode on, Sleep out Partial mode on, Idle mode off, Sleep out Partial mode on, Idle mode on, Sleep out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value MTP[23:16] MTP[23:16] MTP[23:16] Flow Chart RDID1(DAh) Dummy Read Host Driver Send 2nd parameter Legend Command Parameter Display Action Mode Sequential transfer Page 299/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.37. RDID2 : Read ID2 Value (DBh) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX RDID2 0 1 1 0 1 1 0 1 1 DBh Dummy read R 1 X X X X X X X X X 2nd Para 1 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 xx Description This read byte is used to track the LCD module/driver version. It is provided by a display supplier and updated each time a revision is made to the display, material or construction specifications. Note. “X“ denotes “Don’t care” Restrictions - When ID_SEL=1, RDID2 Read Values are MTP ID2 Values - When ID_SEL=0, RDID2 Read Values are D4h’s 2nd Parameter Values Register Availability Status Normal mode on, Idle mode off, Sleep out Normal mode on, Idle mode on, Sleep out Partial mode on, Idle mode off, Sleep out Partial mode on, Idle mode on, Sleep out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value MTP[15:8] MTP[15:8] MTP[15:8] Flow Chart RDID2(DBh) Dummy Read Host Driver Send 2nd parameter Legend Command Parameter Display Action Mode Sequential transfer Page 300/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.2.38. RDID3 : Read ID3 Value (DCh) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 RDID3 0 1 1 0 1 1 1 Dummy read R 2nd Para 1 X X X X X X 1 ID37 ID36 ID35 ID34 ID33 ID32 Description This read byte identifies the LCD module/driver. It is specified by a user. Note. “X“ denotes “Don’t care” Restrictions - When ID_SEL=1, RDID3 Read Values are MTP ID3 Values - When ID_SEL=0, RDID3 Read Values are D4h’s 3rd Parameter Values D1 0 X ID31 D0 0 X ID30 HEX DC X xx Register Availability Status Normal mode on, Idle mode off, Sleep out Normal mode on, Idle mode on, Sleep out Partial mode on, Idle mode off, Sleep out Partial mode on, Idle mode on, Sleep out Sleep In Availability Yes Yes Yes Yes Yes Default Status Power On Sequence S/W Reset H/W Reset Default Value MTP[7:0] MTP[7:0] MTP[7:0] Flow Chart RDID3(DCh) Dummy Read Host Driver Send 2nd parameter Legend Command Parameter Display Action Mode Sequential transfer Page 301/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3. DESCRIPTION OF LEVEL2 COMMAND Command Description Tables are explained by 80mode Interface standard. Mobile Display Driver IC 5.3.1. DSTB: Deep Stand by mode Control (B0h) Inst/Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX DSTB 0 1 0 1 1 0 0 0 0 B0 W 1st para 1 0 0 0 0 0 0 0 DSTB - DSTB: When DSTB = 1, the S6D05A0 enters the deep standby mode, where the power supply for the internal logic is off to save more power than the sleep mode. The GRAM data and the instruction sets are prohibited during the deep standby mode and they must be reset after releasing from the deep standby mode. Status Initial Default Value DSTB = 0 5.3.2. MIECTL2: Write MIE Control 2 (CCh) Inst/Para MIECTL2 1st para 2nd para 3rd para 4th para 5th para R/W W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 0 1 1 0 0 CC WIN WIN WIN WIN CAT CAT CST CST 1 VADDR VADDR VADDR VADDR - 1 0 1 0 08 07 06 05 WIN WIN WIN WIN WIN WIN WIN WIN 1 VADDR VADDR VADDR VADDR VADDR VADDR VADDR VADDR - 04 03 02 01 00 18 17 16 WIN WIN WIN WIN WIN WIN WIN WIN 1 VADDR VADDR VADDR VADDR VADDR VADDR HADD HADD - 15 14 13 12 11 10 R08 R07 WIN WIN WIN WIN WIN WIN WIN WIN 1 HADD HADD HADD HADD HADD HADD HADD HADD - R06 R05 R04 R03 R02 R01 R00 R18 WIN WIN WIN WIN WIN WIN WIN WIN 1 HADD HADD HADD HADD HADD HADD HADD HADD - R17 R16 R15 R14 R13 R12 R11 R10 Page 302/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.2.1. CAT[1:0] Mobile Display Driver IC This register is used to select the abrupt transition time. The MIE has two transition times based on image contents for preventing abnormal visible artifacts (e.g. flicker). The MIE controls transition time between CAT and CST automatically in moving mode (MIE_MODE = “11”). - Abrupt transition time: If input image is changed abruptly, short transition time is needed. - Smooth transition time: If input image is changed smoothly, long transition time is needed. Table 136. CAT[1:0] CAT[1:0] 00 01 10 11 Abrupt Transition Time 1 frame 2 frames 4 frames 8 frames Status Initial Default Value CAT[1:0] = 10 5.3.2.2. CST [1:0] This register is used to select the smooth transition time Table 137. CST[1:0] CST[1:0] 00 01 10 11 Smooth Transition Time 32 frames 64 frames 96 frames 128 frames Status Initial Default Value CST[1:0] = 00 An example of MIE transition time is illustrated as below. If the input image is changed abruptly, the MIE has an abrupt transition time “case (1)” and if the input image is changed smoothly, the MIE has a smooth transition time “case (2)”. The display brightness changes to target brightness abruptly “case (4)” when the abrupt change of image is happened during the smooth transition “case (3)”. Page 303/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 164. Example of MIE transition control 5.3.2.3. WINVADDR0[8:0] This register is used to set the vertical start address of MIE window. Table 138. WINVADDR0[8:0] WINVADDR0[8:0] 0_0000_0000 0_0000_0001 0_0000_0010 0_0000_0011 … 1_1101_0111 1_1101_1000 … 1_1111_1111 Vertical Start Address of MIE Window 0 1 2 3 … 471 Setting disabled … Setting disabled Status Initial Note1: WINVADDR1 – WINVADDR0 ≥ 8 Note2: According to the MADCTL and SEL_360, Set WINVADDR0. Default Value WINVADDR0[8:0] = 0_0000_0000 Page 304/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.3.2.4. WINVADDR1[8:0] This register is used to set the vertical end address of MIE window. Table 139. WINVADDR1[8:0] WINVADDR1[8:0] 0_0000_0000 0_0000_0001 … 0_0000_0111 0_0000_1000 0_0000_1001 … 1_1101_1110 1_1101_1111 1_1110_0000 … 1_1111_1111 Vertical End Address of MIE Window Setting disabled Setting disabled … Setting disabled 8 9 … 478 479 Setting disabled … Setting disabled Status Initial Note1: WINVADDR1 – WINVADDR0 ≥ 8 Note2: According to the MADCTL and SEL_360, Set WINVADDR1. Default Value WINVADDR1[8:0] = 1_1101_1111 5.3.2.5. WINHADDR0[8:0] This register is used to set the horizontal start address of MIE window. Table 140. WINHADDR0[8:0] WINHADDR0[8:0] 0_0000_0000 0_0000_0001 ~ 1_1111_1111 Horizontal Start Address of MIE Window 0 Setting disabled Status Initial Default Value WINHADDR0[8:0] = 0_0000_0000 Page 305/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.2.6. WINHADDR1[8:0] This register is used to set the horizontal end address of MIE window. Mobile Display Driver IC Table 141. WINHADDR1[8:0] WINHADDR1[8:0] 0_0000_0000 ~ 1_0011_1110 1_0011_1111 1_0100_0000 ~ 1_0110_0110 1_0110_0111 1_0110_1000 ~ 1_1111_1111 Horizontal End Address of MIE Window Setting disabled 319 Setting disabled 359 Setting disabled Status Initial Note1: According to the SEL_360, Set WINHADDR1. Default Value WINHADDR1[8:0] = 1_0011_1111 The MIE can select the window area which is used to analysis and enhance input image. The outside area of the MIE window is not used to MIE analysis and there is no image enhancement. Figure 165. MIE window(A Case of 320RGB) Page 306/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.3. MIE Control3 (CDh) : Write BL Control Mobile Display Driver IC Inst/Para MIECTL3 1st para 2nd para R/W W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 0 1 1 0 1 CD BC_FR BC_FR BC_FR BC_FR BC_FR BC_FR BC_FR 1 0 Q_SEL Q_SEL Q_SEL Q_SEL Q_SEL Q_SEL Q_SEL - 6 5 4 3 2 1 0 BL_MO 1 DE_IN 0 _SLP BL_DR BL_DI BL_DI DT DT DT V_EN_ MM_S MM_S - 2 1 0 PAD TEP1 TEP0 5.3.3.1. BC_FRQ_SEL[6:0] This register is used to select the frequency of BC. To select the BC frequency, two registers are needed. Those register are BC_FRQ_SEL [6:0] and BL_DIMM_STEP [1:0]. For details, refer to the table of BC frequency. Status Initial Default Value BC_FRQ_SEL[6:0] = 000_0011 5.3.3.2. BL_MODE_IN_SLP This register is used to select the state of BC when driver IC is sleep in mode. When BL register is high, BL_MODE_IN_SLP reigster is valid. Table 142. BL_MODE_IN_SLP BL_MODE_IN_SLP 0 1 Status Initial State of BC Low High Default Value BL_MODE_IN_SLP = 0 Table 143. State of BC Pin Hard Reset SW Reset BC Low Low State SLPIN Display On Display Off Fixed as BL_MODE_IN_SLP Page 307/389 SPLOUT Display On Display Off Active Low 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.3.3. DT[2:0] This register is used to select the transition time of the manual dimming function. Table 144. DT[2:0] DT[2:0] 000 001 010 011 100 101 110 111 Transition Time 16 frames 24 frames 32 frames 40 frames 48 frames 56 frames 64 frames 72 frames Mobile Display Driver IC Dimming Step 16 24 32 40 48 56 64 72 Figure 166. Transition time of manual dimming function Status Initial Default Value DT[2:0] = 010 Figure 167. Example of dimming function (DT[2:0] = 000) Page 308/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.3.4. BL_DRV_EN_PAD Mobile Display Driver IC This register is used to enable the LED driver IC when the IC needs the chip enable signal. Table 145. BL_DRV_EN_PAD BL_DRV_EN_PAD 0 1 State of BC_CTL Pin Low High Status Initial Default Value BL_DRV_EN_PAD = 1 5.3.3.5. BL_DIMM_STEP[1:0] This register is used to select the dimming step of BC level. It is used to select the frequency of BC with BC_FRQ_SEL [6:0]. Table 146. BL_DIMM_STEP[1:0] BL_DIMM_STEP[1:0] 00 01 10 11 Dimming Steps of BC 256 128 64 32 Status Initial Default Value BL_DIMM_STEP[1:0] = 00 The PWM frequency is calculated with the following formula. Figure 168. Calculation formula of BC frequency Page 309/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 169. Example of BC frequency selection Page 310/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 147. BC frequency Mobile Display Driver IC Note. F.F. means Frame Frequency.When the display frame frequency is 60Hz, BC frequency is represented at the table below. Page 311/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 148. Example of BC frequency selection Mobile Display Driver IC Page 312/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.4. MTPCTL: MTP Control Command (D0h) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX MTPCTL 0 1 1 0 1 0 0 0 0 D0h 1st para ID_ MTP_ MTP_ MTP_ 1 0 0 0 0 R/W SEL SEL MODE EX 2nd para MTP_ MTP_ MTP_ 1 0 0 0 0 0 ERB LOAD WRB 5.3.4.1. ID_SEL/ MTP_SEL/ MTP_MODE/ MTP_EX ID_SEL: Select the ID register. Table 149. ID_SEL ID_SEL 0 1 ID2/ID3 Data ID1/ID2/ID3 Register MTP data MTP_SEL: Select the VCOMH voltage setting register. Table 150. MTP_SEL MTP_SEL 0 1 VCOMH Control Data VCMOC/VMLOC/GVDDOC Register MTP data MTP_MODE: Set the 2nd booster operating condition. When MTP_MODE = 0, the 2nd booster operates as a userspecified condition. VGH/VGL voltages are generated as a designated level by BT2-0 setting. If MTP_MODE = 1, available BT2-0 settings are limited only ‘010’ & ‘101’. Table 151. MTP_MODE MTP_MODE MTP operation mode 0 All BT2-0 settings are available (Normal operating condition) 1 Setting of BT2-0 is limited. (An MTP-programming / erasing condition) Note. Do not execute MTP programming / erasing operation when MTP_MODE = 0. MTP_EX: Select MTP power supply source. When MTP_EX = 0, Internally generated VGH voltage is used as a MTP-programming / erasing potential. If MTP_EX = 1, External power should be applied for programming / erasing MTP via VGH pad. Page 313/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 152. MTP_EX MTP_EX Erase / Initial / Program supply 0 Used internally generated VGH 1 Needed external power supply Note. MTP_EX register is valid only in case that MTP_MODE = 1. Do not access MTP_EX register when MTP_MODE = 0. Status Initial Default Value ID_SEL = 1 MTP_SEL = 1 MTP_MODE = 0 MTP_EX = 0 5.3.4.2. MTP_ERB/ MTP_LOAD/ MTP_WRB MTP_ERB: Enable bit for MTP initialization or erasure. When MTP_ERB = 0, MTP initialization or erasure is enabled. MTP_LOAD: When MTP_LOAD is High, MTP data is loaded into an internal register. MTP_WRB: MTP Write enable bit. If MTP cell is to be written, set MTP_WRB = 0 Status Initial Default Value MTP_ERB = 1 MTP_LOAD = 0 MTP_WRB = 1 Page 314/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.5. WRVCMOC: Set VCOM Offset Control (D1h) Mobile Display Driver IC Inst / Para WRVCMOC 1st param R/W DCX D7 0 1 R/W 1 0 D6 D5 D4 D3 D2 D1 D0 HEX 1 0 1 0 0 0 1 D1h VCM VCM VCM VCM VCM VCM 0 OC5 OC4 OC3 OC2 OC1 OC0 5.3.5.1. VCMOC[5:0] VCMOC5-0 contains VCM Offset data. This MTP data and VCM register determine VCOMH level. TOTAL_VCM [6:0] = VCM[6:0](NVCM or IPVCM) + VCMOC5-0 Table 153. VCMOC[5:0] VCMOC5-0 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 VCM_OFFSET 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 +24 VCMOC5-0 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 Page 315/389 VCM_OFFSET 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 VCMOC5-0 011001 011010 011011 011100 011101 011110 011111 VCM_OFFSET +25 +26 +27 +28 +29 +30 +31 VCMOC5-0 111001 111010 111011 111100 111101 111110 111111 Mobile Display Driver IC VCM_OFFSET -25 -26 -27 -28 -29 -30 -31 For example, if VCM [6:0] = 0101011 and VCMOC5-0 = 100001 are selected, then VCM_OFFSET is “-1,” and therefore TOTAL_VCM is “0101010,” which results in VCOMH voltage = 3.3268V from NVCM6-0/IPVCM6-0 table. Note1. TOTAL_VCM [6:0] cannot be set to the value above “1111111” or below “0011010,” that is, 127 ≥ VCM [6:0] + VCMOC5-0 ≥ 0. Note2. TOTAL_VCM [6:0] is VCM[6:0] + VCM_OFFSET_MTP[5:0] when MTP_SEL=1 and is VCM[6:0] + VCMOC5-0 when MTP_SEL=0. Status Initial Default Value VCMOC[5:0] = 000000 Page 316/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.6. WRVMLOC: Set VCOML Offset Control (D2h) Mobile Display Driver IC Inst / Para WRVMLOC 1st para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX R/W 0 1 1 0 1 0 0 1 0 D2h VMLO VMLO VMLO VMLO VMLO R/W 1 0 0 0 C4 C3 C2 C1 C0 5.3.6.1. VMLOC[4:0] VMLOC4-0 contain VCOM amplitude Offset data. This MTP data and VML register determine VCOML amplitude. TOTAL_VML [6:0] = VML [6:0](NVML or IPVML) + VMLOC4-0. Table 154. VMLOC[4:0] VMLOC4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VML_OFFSET 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 VMLOC4-0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VML_OFFSET 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 For example, if VML [6:0] = 0101011 and VMLOC4-0 = 10001 are selected, then VML_OFFSET is “-1,” and therefore TOTAL_VML is “0101010,” which results in VCOM amplitude voltage = 3.9921V from NVML6-0/IPVML6-0 table. Note1. TOTAL_VML[6:0] cannot be set to the value above “1111111” or below “0011010,” that is, 127 ≥ VML[6:0] + VMLOC4-0 ≥ 0. Note2. TOTAL_VML [6:0] is VML[6:0] + VML_OFFSET_MTP[4:0] when MTP_SEL=1 and is VML[6:0] + VMLOC4-0 when MTP_SEL=0 Status Initial Default Value VMLOC[4:0] = 00000 Page 317/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.7. WRGVDOC: Set GVDD Offset Control (D3h) Mobile Display Driver IC Inst / Para WRGVDOC 1st para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 1 0 0 1 1 D3h R/W GVDO GVDO GVDO GVDO 1 0 0 0 0 C4 C3 C2 C1 5.3.7.1. GVDOC[4:1] GVDOC4-1 contains GVD Offset data. This MTP data and GVD register determine GVDD level. TOTAL_GVD [6:0] = GVD [6:0](NGVD or IPGVD) + GVDOC[4:1]. Table 155. GVDOC[4:1] GVDOC4-1 0000 0001 0010 0011 0100 0101 0110 0111 GVD_OFFSET 0 +2 +4 +6 +8 +10 +12 +14 GVDOC4-1 1000 1001 1010 1011 1100 1101 1110 1111 GVD_OFFSET 0 -2 -4 -6 -8 -10 -12 -14 For example, if GVD [6:0] = 0101011 and GVDOC4-1 = 1001 are selected, then MTP_OFFSET is “-2,” and therefore TOTAL_GVD is “0101001,” which results in GVDD voltage = 3.3071V from NGVD6-0/IPGVD6-0 table. Note1. TOTAL_GVD [6:0] cannot be set to the value above “1111111” or below “0011010,” that is, 127 ≥ GVD [6:0] + GVDOC4-1 ≥ 0. Note2. TOTAL_GVD [6:0] is GVD [6:0] + GVD_OFFSET_MTP[4:1] when MTP_SEL=1 and is GVD[6:0] + GVDOC4-1 when MTP_SEL=0. Status Initial Default Value GVDOC[4:1] = 0000 Page 318/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.8. WRID: ID Definition (D4h) Mobile Display Driver IC Inst / Para WRID 1st para 2nd para 3rd para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 1 0 1 0 0 D4h 1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 R/W 1 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 5.3.8.1. ID1/ ID2/ ID3 WRID read register value which is not MTP value. ID1: LCD module/driver manufacturers ID (specified by user) ID2: LCD module/driver version ID(specified by module supplier) ID3: Project ID(specified by handset company) Status Intial Default Value ID1 = 00h ID2 = 00h ID3 = 00h Page 319/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.9. RDOFFSETC: Read Offset Control (D5h) Mobile Display Driver IC Inst / Para R/W DCX D7 RDOFFSETC 0 1 Dummy Read 1 X 1st para 1 0 2nd para R 1 0 3rd para 1 0 Note. “X“ denotes “Don’t care” D6 D5 D4 D3 D2 D1 D0 HEX 1 0 1 0 1 0 1 D5h X X X X X X X X VCMO VCMO VCMO VCMO VCMO VCMO 0 C_MT C_MT C_MT C_MT C_MT C_MT P5 P4 P3 P2 P1 P0 VMLO VMLO VMLO VMLO VMLO 0 0 C_MT C_MT C_MT C_MT C_MT P4 P3 P2 P1 P0 GVDO GVDO GVDO GVDO 0 0 C_MT C_MT C_MT C_MT 0 P4 P3 P2 P1 5.3.9.1. VCMOC_MTP/ VMLOC_MTP/ GVDOC_MTP VCMOC_MTP: Read VCMOC Values from MTP VMLOC_MTP: Read VMLOC Values from MTP GVDOC_MTP: Read GVDOC Values from MTP Status Initial Default Value VCMOC_MTP: MTP[38:33] VMLOC_MTP: MTP[32:28] GVDOC_MTP: MTP[27:24] Page 320/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.10. MDDICTL1 : MDDI Control 1 (E0h) Mobile Display Driver IC Inst / Para R/W RS D7 D6 D5 D4 D3 D2 D1 D0 HEX MDDICTL1 0 1 1 1 0 0 0 0 0 E0h W 1st para MDDI_ VWAK 1 0 0 0 0 0 0 SLP E_EN 5.3.10.1. MDDI_SLP/VWAKE_EN MDDI_SLP: When MDDI_SLP is high, MDDI Operating State is STOP state. To release STOP state, input reset(RESX) signal. VWAKE_EN: When VWAKE_EN is 1, client initiated wake-up is enabled Status Initial Default Value MDDI_SLP=0 VWAKE_EN=0 Page 321/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.11. MDDILIK: MDDI Link Wake-up Start Position (E1h) Mobile Display Driver IC Inst / Para R/W RS D7 D6 D5 D4 D3 D2 D1 D0 HEX MDDILIK 0 1 1 1 0 0 0 0 1 (E1h) 1st para W 1 WKL9 WKL8 WKL7 WKL6 WKL5 WKL4 WKL3 WKL2 2nd para 1 WKL1 WKL0 WKF3 WKF2 WKF1 WKF0 0 0 5.3.11.1. WKL[9:0]/WKF[3:0] WKL9-0: The registers for defining at which number of line the client-initiated wakeup would start. If WKL is updated to '000h', client-initiated wakeup starts automatically at the first line after vertical front porch. The range of WKL is from '000h' to '3DBh'. WKF3-0: The registers for defining after which number of frame the client-initiated wakeup would start. If WKF is updated to '0000' client-initiated wakeup starts at the start of next frame, and if '1111', wakeup starts after 16th frame. Setting of WKF and WKL works together for client-initiated wakeup. For example, If WKF is '0011' and WKL is '003h', VBP is ‘03h’, wakeup starts at the first display line of third frame. Status Initial Default Value WKL[9:0]=00_0000_0000 WKF[3:0]=0000 Page 322/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.12. DCON: Manual Display Control Register (EFh) Mobile Display Driver IC Inst / Para R/W RS D7 D6 D5 D4 D3 D2 D1 D0 HEX DCON 0 1 1 1 0 1 1 1 1 (EFh) R/W D_ D_ 1st para 1 0 0 0 0 0 GON CON1 CON0 5.3.12.1. GON/D_CON[1:0] GON: Gate on/off control bit. All gate outputs are set to be AVSS or VGL level when GON = 0. When GON = 1, gate driver is working: G1 to G480 output is either VGH or VGL level. See the Instruction set-up flow for further description on the display on/off flow. Table 156. GON GON 0 1 Gate Output All gates goes to AVSS or VGL Gate on(VGH / VGL) D_CON: When APON=0, Display Status is controled by D_CON[1:0], Please refer Following Table, When APON=1, D_CON[1:0] Setting is ignored. Table 157. D_CON[1:0] Register Chip Operation D_CON GON SOURCE VCOM 00 X AVSS AVSS 01 0 AVSS AVSS 01 1 AVSS AVSS Operate 10 0 Operate (Same Phase of VCOM) Operate 10 1 Operate (Same Phase of VCOM) 11 0 Operate (GRAM Data) Operate 11 1 Operate (GRAM Data) Operate GATE AVSS VGL Operate VGL Operate VGL Operate Display Status Halt Halt Blank Display Halt Blank Display Halt GRAM Display Status Initial When APON=1, Please refer Following Table for Display Control Page 323/389 Default Value GON=0 D_CON[1:0]=00 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 158. Display Control and Chip Operation, When APON is High, Register Chip Operation SLP DISP DISP SLPIN OUT ON OFF SOURCE VCOM GATE ON OFF X X AVSS AVSS AVSS Operate OFF ON OFF ON (Same Phase of Operate Operate VCOM) Operate OFF ON ON OFF (GRAM Data) Operate Operate Mobile Display Driver IC Display Status Boosting Status Halt OFF Blank ON Display GRAM ON Display Page 324/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.13. WRPWD: DSTB and MTP Control Test Key (F0h) Mobile Display Driver IC Inst / Para WRPWD 1st para 2nd para R/W R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 0 0 0 0 TEST_ TEST_ TEST_ TEST_ TEST_ TEST_ TEST_ TEST_ 1 DSTB7 DSTB6 DSTB5 DSTB4 DSTB3 DSTB2 DSTB1 DSTB0 1 TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 HEX F0h 5.3.13.1. TEST_DSTB[7:0]/TEST[7:0] TEST_DSTB7-0: DSTB Function Protection TEST_KEY. When Test Key Command =5Ah, DSTB(B0h) are writable TEST7-0: MTP Function Protection TEST_KEY. When Test Key Command =5Ah, MTP_WRB and MTP_ERB are valid. And D0h, D1h, D2h, D3h, D4h Registers are updated. Status Initial Default Value TEST_DSTB[7:0] = 04h TEST[7:0] = 30h Page 325/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.14. DISCTL: Display Control Register (F2h) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX DISCTL 0 1 1 1 1 0 0 1 0 F2h 1st para NRTN NRTN NRTN NRTN NRTN 1 0 0 0 4 3 2 1 0 2nd para IPRTN IPRTN IPRTN IPRTN IPRTN 1 0 0 0 4 3 2 1 0 3rd para 1 0 0 0 0 IPINV IINV PINV NINV 4th para 5th para 6th para 7th para 8th para 9th para NVBP NVBP NVBP NVBP NVBP NVBP NVBP NVBP 1 7 6 5 4 3 2 1 0 NVFP NVFP NVFP NVFP NVFP NVFP NVFP NVFP 1 7 6 5 4 3 2 1 0 R/W IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP IPVBP 1 7 6 5 4 3 2 1 0 IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP IPVFP 1 7 6 5 4 3 2 1 0 HBP HBP HBP HBP HBP HBP HBP 1 0 6 5 4 3 2 1 0 1 0 0 0 0 0 SM GS REV 10th para 11th para NCRTN NCRTN NCRTN NCRTN NCRTN 1 0 0 0 4 3 2 1 0 IPCRT IPCRT IPCRT IPCRT IPCRT 1 0 0 0 N4 N3 N2 N1 N0 5.3.14.1. NRTN[4:0] / IPRTN[4:0] Set the 1H period (1 raster-row) register. NRTN is valid in Normal mode, and IPRTN is applied in Idle Partial mode. Table 159. NRTN[4:0]/IPRTN[4:0] NRTN4 / NRTN3 / IPRTN4 IPRTN3 0 0 0 0 0 0 0 0 0 0 NRTN2 / IPRTN2 0 0 0 0 1 NRTN1 / IPRTN1 0 0 1 1 0 Page 326/389 NRTN0 / IPRTN0 0 1 0 1 0 1 Horizontal clock cycle (CL1) Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 NRTN4 / NRTN3 / NRTN2 / NRTN1 / NRTN0 / IPRTN4 IPRTN3 IPRTN2 IPRTN1 IPRTN0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Note1. RTN x CRTN must bigger than Horizontal Pixel + 30 (ex 320RGB : RTN x CRTN > 350) Note2. INCLK: Internal clock Note3. IPNO, IPSDT, VCIRA, VCIR register values must be smaller than the half of IPRTN values. NNO, NSDT, VCIRA, VCIR register values must be smaller than the half of NRTN values. Mobile Display Driver IC 1 Horizontal clock cycle (CL1) Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable 14 INCLK 15 INCLK 16 INCLK 17 INCLK 18 INCLK 19 INCLK 20 INCLK 21 INCLK 22 INCLK 23 INCLK 24 INCLK 25 INCLK 26 INCLK 27 INCLK 28 INCLK 29 INCLK 30 INCLK 31 INCLK Status Initial Default Value NRTN=16h IPRTN=16h Page 327/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.14.2. IPINV/IINV/PINV/INV Display inversion mode control register. IPINV: Inversion setting on partial idle mode (Partial mode on / Idle mode on) IINV: Inversion setting on Idle mode (Idle mode on) PINV: Inversion setting on partial mode (Partial mode on) NINV: Inversion setting on full color normal mode (Normal mode on) Mobile Display Driver IC Table 160. IPINV/IINV/PINV/NINV IPINV/IINV/PINV/NINV 0 1 Inversion Frame inversion Line inversion Status Initial Default Value IPINV = 0 IINV = 0 PINV = 1 NINV = 1 5.3.14.3. NVBP[7:0]/ IPVBP[7:0]/ NVFP[7:0]/ IPVFP[7:0] Control vertical back and front porch in MPU I/F or MDDI. And Control vertical back porch in or RGB I/F(Regardless of NVFP/IPVFP register values, External Physical front porch must be bigger than 3) In RGB I/F, It should be noted that NVBP/IPVBP Register and Externaly forsing Back Porch are same. NVBP/ IPVBP: The number of lines for the back porch of VS(Vertical Sync) register. IPVBP is applied in Idle Partial mode Table 161. NVBP[7:0]/IPVBP[7:0] NVBP[7:0] / IPVBP[7:0] 00d 01d 02d 03d 04d 05d 254d 255d … … No. of clock cycle of HS (horizontal Sync) Setting Disable Setting Disable 2 3 4 5 254 Setting Disable Page 328/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC NVFP/ IPVFP: The number of lines for the front porch of VS. NVFP/IPVFP must be bigger than 3. IPVFP is applied in Idle Partial mode. Table 162. NVFP[7:0]/IPVFP[7:0] NVFP[7:0] / IPVFP[7:0] 00d 01d 02d 03d 04d 05d No. of clock cycle of HS Setting Disable Setting Disable Setting Disable 3 4 5 … … 254d 255d Status Initial 5.3.14.4. HBP[6:0] The number of internal clocks for TE’s Horizontal timing high width 254 Setting Disable Default Value NVBP[7:0] = 11h IPVBP[7:0] = 11h NVFP[7:0] = 11h IPVFP[7:0] = 11h Table 163. HBP[6:0] HBP[6:0] 00d 01d 02d 03d 25d 26d 27d~127d Status Initial No. of clock cycle of INCLK 2 3 4 5 27 28 Setting Disable Default Value HBP[6:0] = 001_0000 Page 329/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.14.5. SM/ GS/ REV Mobile Display Driver IC SM: Select the division drive method of the gate driver. When SM=0, even/odd division is selected; SM =1, upper/lower division drive is selected by (total gate line)/2 and (total gate line)/2. Various connections between TFT panel and the IC can be supported with the combination of SM and GS bit. GS: Set the order of Gate Clock generation. When GS = 0 (NL=6’b111011, SCN=5’b00000, SM=0), the order of GATE_ON is from G1 to G480, and then GS = 1 (NL=6’b111011, SCN=5’b00000,SM=0), from G480 to G1. Gate start position and Gate scan order are changed by GS/NL/SCN/SM. Figure 170. Gate clock generation order selection using GS and SM (NL=6’b111011, SCN=5’b00000) Figure 171. Gate clock generation order selection using GS and SM (NL=6’b100111, SCN=5’b00000) REV: Display all character and graphics display sections with reversal when REV=1. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. Table 164. REV REV 0 1 GRAM Data 8’b000000 : 8’b111111 8’b000000 : 8’b111111 Positive V255 : V0 V0 : V255 Page 330/389 Display Area Negative V0 : V255 V255 : V0 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Status Initial Mobile Display Driver IC Default Value SM = 0 GS = 0 REV = 0 5.3.14.6. NCRTN[4:0] / IPCRTN[4:0] Set the 1 raster-row. IPCRTN is applied in Idle Partial mode. Table 165. NCRTN[4:0] / IPCRTN[4:0] NCRTN4/ NCRTN3/ NCRTN2/ IPCRTN4 IPCRTN3 IPCRTN2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 NCRTN1/ IPCRTN1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 NCRTN0/ IPCRTN0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Page 331/389 INCLK Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable Setting Disable 14 OSC_CLK 15 OSC_CLK 16 OSC_CLK 17 OSC_CLK 18 OSC_CLK 19 OSC_CLK 20 OSC_CLK 21 OSC_CLK 22 OSC_CLK 23 OSC_CLK 24 OSC_CLK 25 OSC_CLK 26 OSC_CLK 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 NCRTN4/ NCRTN3/ NCRTN2/ NCRTN1/ NCRTN0/ IPCRTN4 IPCRTN3 IPCRTN2 IPCRTN1 IPCRTN0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Note. RTN x CRTN must be bigger than Horizontal Pixel + 30 (ex 320RGB : RTN x CRTN > 350) Mobile Display Driver IC INCLK 27 OSC_CLK 28 OSC_CLK 29 OSC_CLK 30 OSC_CLK 31 OSC_CLK Status Initial Default Value NCRTN=16h IPCRTN=16h Page 332/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.15. PWRCTL: Power Control Register (F3h) Mobile Display Driver IC Inst / Para PWRCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para 9th para R/W DCX 0 1 1 1 1 R/W 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 HEX 1 1 1 1 0 0 1 1 F3h AP 0 0 0 0 0 0 0 ON PON PON PON PON VCI1_ 0 AON PON 3 2 1 0 EN NDC NDC NDC NDC NDC 0 0 NDC10 31 30 21 20 11 IPDC IPDC IPDC IPDC IPDC IPDC 0 0 31 30 21 20 11 10 VC VC VC VC 0 0 0 0 3 2 1 0 IPBT IPBT IPBT NBT NBT NBT 0 0 2 1 0 2 1 0 NGVD NGVD NGVD NGVD NGVD NGVD NGVD 0 6 5 4 3 2 1 0 IPGVD IPGV IPGVD IPGVD IPGVD IPGVD IPGVD 0 6 D5 4 3 2 1 0 AB_ NAB IPAB 0 0 0 0 0 VCI1 2A 2A 5.3.15.1. APON APON: This is an automatic-boosting-operation-starting bit for the booster circuits. In case of APON=0, the automatic boosting sequence starter is halted and the booster circuits are operated independently by PON, PON0, PON1, PON2 and PON3 bits. In case of APON=1, booster circuits are operated automatically and sequentially. For further information about timing, please refer to the Section 4.1.6, 4.1.7 Status Initial Default Value APON =0 5.3.15.2. AON/PON3/PON2/PON1/PON0/PON/VCI1_EN AON: This is an operation-starting bit for GVDD/VCOMH/VCOML amplifiers. In case of AON = 0, the amplifier circuits are stopped. On the other hand, the operation of the amplifiers is getting started when AON = 1. For further information about timing for adjusting to AON= 1, refer to the Section 4.1.6, 4.1.7 Page 333/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC PON3: This is an operation-starting bit for the booster circuit 3(VCL). In case of PON3 = 0, the circuit is stopped and vice versa. For further information about timing for adjusting to the PON3= 1, please refer to the Section 4.1.6, 4.1.7 PON2: This is an operation-starting bit for the booster circuit 2(VGL). In case of PON2 = 0, the circuit is stopped and vice versa. For further information about timing for adjusting to the PON2= 1, please refer to the Section 4.1.6, 4.1.7 PON1: This is an operation-starting bit for the booster circuit 2(VGH). In case of PON1 = 0, the circuit is stopped and vice versa. For further information about timing for adjusting to the PON1= 1, please refer to the Section 4.1.6, 4.1..7 PON0: This is an operation-starting bit for the booster circuit 1(AVDD2). In case of PON0 = 0, the circuit is stopped and vice versa. For further information about timing for adjusting to the PON0= 1, please refer to the Section 4.1.6, 4.1..7 PON: This is an operation-starting bit for the booster circuit 1(AVDD1). In case of PON = 0, the circuit is stopped and vice versa. For further information about timing for adjusting to the PON= 1, please refer to the Section 4.1.6, 4.1..7 VCI1_EN: Internal VCI1 generation amplifier operation control bit. When VCI1_EN=0, VCI1 voltage is not generated. Status Initial Default Value AON = 0 PON3 = 0 PON2 =0 PON1 = 0 PON0 = 0 PON = 0 VCI1_EN = 0 5.3.15.3. NDC3/IPDC3/NDC2/IPDC2/NDC1/IPDC1 NDC31-30/ IPDC31-30: The operating frequency in the booster circuit 3 is selected. IPDC3 is applied in Idle Partial mode. Table 166. NDC3[1:0]/ IPDC3[1:0] NDC31/ NDC30/ IPDC31 IPDC30 0 0 0 1 1 0 1 1 Note. DCCLK3 is pumping clock for booster circuit3 Internal Operation (synchronized with internal clock) f(CL1) : f(DCCLK3) 1:4 1:2 1:1 Setting disabled Page 334/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC NDC21-20/ IPDC21-20: The operating frequency in the booster circuit 2 is selected. IPDC2 is applied in Idle Partial mode. Table 167. NDC2[1:0]/ IPDC2[1:0] NDC21/ NDC20/ IPDC21 IPDC20 0 0 0 1 1 0 1 1 Internal Operation (synchronized with internal clock) f(CL1) : f(DCCLK2) 1:2 1:1 1:0.5 1:0.25 Note. DCCLK2 is pumping clock for booster circuit2 NDC11-10/IPDC11-10: The operating frequency in the booster circuit1 is selected. When the boosting operating frequency is high, the driving ability of the booster circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. IPDC1 is applied in Idle Partial mode. Table 168. NDC1[1:0]/ IPDC1[1:0] NDC11/ NDC10 Internal Operation (synchronized with internal clock) IPDC11 IPDC11 f(CL1) : f(DCCLK1) 0 0 1:4 0 1 1:2 1 0 1:1 1 1 Setting disabled Note. DCCLK1 is pumping clock for booster circuit1. f(1H) is horizontal frequency (1 raster-row) Status Initial Default Value NDC3[1 :0] = 10, NDC2[1 :0] = 01, NDC1[1 :0] = 10 IPDC3[1 :0] = 10,IPDC2[1 :0] = 01, IPDC1[1 :0] = 10 Page 335/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.15.4. VC[3:0] Mobile Display Driver IC VC3-0: Set the VCI1 voltage. These bits set the VCI1 voltage up to 3V as the nominal output (upper limit value may depend on VCI voltage) Table 169. VC[3:0] VC3 VC2 VC1 VC0 Setting Disable Setting Disable 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Note. 1.Do not set any higher VCI1 level than VCI -0.12V. 2) VC=1.35V (VC3-0=0000) should be set only in power-up sequence for latch-up immunity. VCI1 2.07 2.16 2.25 2.34 2.43 2.52 2.58 2.64 2.70 2.76 2.82 2.88 2.94 3 Status Initial Default Value VC[3:0] = 0010 5.3.15.5. NBT[2:0]/ IPBT[2:0] NBT/ IPBT: The output factor of booster is switched. Adjust scale factor of the booster circuit by the voltage used. When the boosting operating frequency is high, the driving ability of the booster circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. IPBT is applied in Idle Partial mode. Page 336/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Table 170. NBT[2:0]/IPBT[2:0] IPBT2/NBT2 IPBT1/NBT1 IPBT0/NBT0 VGH VGL Notes* 0 0 0 5 X VCI1 -3X VCI1 13.75V 0 0 1 5 X VCI1 -4X VCI1 13.75V 0 1 0 6 X VCI1 -3X VCI1 16.5V 0 1 1 6 X VCI1 -4X VCI1 16.5V 1 0 0 6 X VCI1 -5X VCI1 16.5V 1 0 1 7 X VCI1 -4X VCI1 19.25V 1 1 0 Setting disabled 1 1 1 Setting disabled Note. The values in table above are example of nominal upper-limit by register setting when VCI1=2.75V. .Status Default Value Initial NBT[2:0] = 000, IPBT[2:0] = 000 -8.25V -11V -8.25V -11V -13.75V -11V 5.3.15.6. NGVD[6:0]/IPGVD[6:0] NGVD6-0: Set the amplifying factor of the GVDD voltage on Normal Mode (the voltage for the Gamma voltage). It allows ranging from 3V to 5.0V. It allows ranging from 2.5V to 5.0V Table 171. NGVD[6:0] NGVD6-0 GVDD Voltage 0000000 2.5000 0000001 2.5197 0000010 2.5394 0000011 2.5591 0000100 2.5787 0000101 2.5984 0000110 2.6181 0000111 2.6378 0001000 2.6575 0001001 2.6772 0001010 2.6969 0001011 2.7165 0001100 2.7362 0001101 2.7559 0001110 2.7756 NGVD6-0 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 GVDD Voltage 3.1299 3.1496 3.1693 3.1890 3.2087 3.2283 3.2480 3.2677 3.2874 3.3071 3.3268 3.3465 3.3661 3.3858 3.4055 NGVD6-0 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 Page 337/389 GVDD Voltage 3.7598 3.7795 3.7992 3.8189 3.8386 3.8583 3.8780 3.8976 3.9173 3.9370 3.9567 3.9764 3.9961 4.0157 4.0354 NGVD6-0 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 GVDD Voltage 4.3898 4.4094 4.4291 4.4488 4.4685 4.4882 4.5079 4.5276 4.5472 4.5669 4.5866 4.6063 4.6260 4.6457 4.6654 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 NGVD6-0 GVDD Voltage NGVD6-0 GVDD Voltage 0001111 2.7953 0101111 3.4252 0010000 2.8150 0110000 3.4449 0010001 2.8346 0110001 3.4646 0010010 2.8543 0110010 3.4843 0010011 2.8740 0110011 3.5039 0010100 2.8937 0110100 3.5236 0010101 2.9134 0110101 3.5433 0010110 2.9331 0110110 3.5630 0010111 2.9528 0110111 3.5827 0011000 2.9724 0111000 3.6024 0011001 2.9921 0111001 3.6220 0011010 3.0118 0111010 3.6417 0011011 3.0315 0111011 3.6614 0011100 3.0512 0111100 3.6811 0011101 3.0709 0111101 3.7008 0011110 3.0906 0111110 3.7205 0011111 3.1102 0111111 3.7402 Note. Do not set any higher GVDD level than AVDD-0.3V NGVD6-0 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 GVDD Voltage 4.0551 4.0748 4.0945 4.1142 4.1339 4.1535 4.1732 4.1929 4.2126 4.2323 4.2520 4.2717 4.2913 4.3110 4.3307 4.3504 4.3701 Mobile Display Driver IC NGVD6-0 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 GVDD Voltage 4.6850 4.7047 4.7244 4.7441 4.7638 4.7835 4.8031 4.8228 4.8425 4.8622 4.8819 4.9016 4.9213 4.9409 4.9606 4.9803 5.0000 IPGVD6-0: Set the amplifying factor of the GVDD voltage on partial idle mode. Table 172. IPGVD[6:0] IPGVD6-0 GVDD Voltage 0000000 2.5000 0000001 2.5197 0000010 2.5394 0000011 2.5591 0000100 2.5787 0000101 2.5984 0000110 2.6181 0000111 2.6378 0001000 2.6575 0001001 2.6772 0001010 2.6969 0001011 2.7165 0001100 2.7362 IPGVD6-0 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 GVDD Voltage 3.1299 3.1496 3.1693 3.1890 3.2087 3.2283 3.2480 3.2677 3.2874 3.3071 3.3268 3.3465 3.3661 IPGVD6-0 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 Page 338/389 GVDD Voltage 3.7598 3.7795 3.7992 3.8189 3.8386 3.8583 3.8780 3.8976 3.9173 3.9370 3.9567 3.9764 3.9961 IPGVD6-0 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 GVDD Voltage 4.3898 4.4094 4.4291 4.4488 4.4685 4.4882 4.5079 4.5276 4.5472 4.5669 4.5866 4.6063 4.6260 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 IPGVD6-0 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 GVDD Voltage 2.7559 2.7756 2.7953 2.8150 2.8346 2.8543 2.8740 2.8937 2.9134 2.9331 2.9528 2.9724 2.9921 3.0118 3.0315 3.0512 3.0709 3.0906 3.1102 IPGVD6-0 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 GVDD Voltage 3.3858 3.4055 3.4252 3.4449 3.4646 3.4843 3.5039 3.5236 3.5433 3.5630 3.5827 3.6024 3.6220 3.6417 3.6614 3.6811 3.7008 3.7205 3.7402 IPGVD6-0 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 GVDD Voltage 4.0157 4.0354 4.0551 4.0748 4.0945 4.1142 4.1339 4.1535 4.1732 4.1929 4.2126 4.2323 4.2520 4.2717 4.2913 4.3110 4.3307 4.3504 4.3701 Mobile Display Driver IC IPGVD6-0 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 GVDD Voltage 4.6457 4.6654 4.6850 4.7047 4.7244 4.7441 4.7638 4.7835 4.8031 4.8228 4.8425 4.8622 4.8819 4.9016 4.9213 4.9409 4.9606 4.9803 5.0000 Status Initial Default Value NGVD=000_0000 IPGVP=000_0000 5.3.15.7. AB_VCI1 AB_VCI1: Set VCI1 output equal to VCI. VCI1 output is internally connected to VCI via switching circuit when AB_VCI1=”H.” Status Initial Default Value AB_VCI1 =0 Page 339/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.15.8. NAB2A/ IPAB2A NAB2A/ IPAB2A: VCOMH amplifier output stage selection register. IPAB2A is applied in Idle Partial mode. Mobile Display Driver IC NAB2A/ IPAB2A 0 1 Status Initial Description The output stage of VCOMH amplifier operates as a Class-AB type The output stage of VCOMH amplifier operates as a Class-A type Default Value NAB2A = 0, IPAB2A = 0 Page 340/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.3.16. VCMCTL : VCOM Control Register (F4h) Inst / Para VCMCTL 1st para 2nd para 3rd para 4th para 5th para R/W R/W DCX 0 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 0 0 NVCM NVCM NVCM NVCM NVCM NVCM NVCM 0 6 5 4 3 2 1 0 IPVCM IPVCM IPVCM IPVCM IPVCM IPVCM IPVCM 6 5 4 3 2 1 0 VCOM NVML NVML NVML NVML NVML NVML NVML G 6 5 4 3 2 1 0 IPVML IPVML IPVML IPVML IPVML IPVML IPVML 0 6 5 4 3 2 1 0 VCIRA VCIRA VCIRA 0 0 2 1 0 VCIR 2 VCIR 1 VCIR 0 HEX F4h 5.3.16.1. NVCM[6:0]/ IPVCM[6:0] NVCM6-0: Set the upper level of VCOM on Normal Mode (VCOMH) Table 173. NVCM[6:0] (Vref=2.0V, unit =V) NVCM[6:0] VCOMH Voltage NVCM[6:0] VCOMH Voltage 0000000 2.5000 0100000 3.1299 0000001 2.5197 0100001 3.1496 0000010 2.5394 0100010 3.1693 0000011 2.5591 0100011 3.1890 0000100 2.5787 0100100 3.2087 0000101 2.5984 0100101 3.2283 0000110 2.6181 0100110 3.2480 0000111 2.6378 0100111 3.2677 0001000 2.6575 0101000 3.2874 0001001 2.6772 0101001 3.3071 0001010 2.6969 0101010 3.3268 0001011 2.7165 0101011 3.3465 0001100 2.7362 0101100 3.3661 0001101 2.7559 0101101 3.3858 0001110 2.7756 0101110 3.4055 0001111 2.7953 0101111 3.4252 NVCM[6:0] 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Page 341/389 VCOMH Voltage 3.7598 3.7795 3.7992 3.8189 3.8386 3.8583 3.8780 3.8976 3.9173 3.9370 3.9567 3.9764 3.9961 4.0157 4.0354 4.0551 NVCM[6:0] 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 VCOMH Voltage 4.3898 4.4094 4.4291 4.4488 4.4685 4.4882 4.5079 4.5276 4.5472 4.5669 4.5866 4.6063 4.6260 4.6457 4.6654 4.6850 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 NVCM[6:0] VCOMH Voltage NVCM[6:0] VCOMH Voltage 0010000 2.8150 0110000 3.4449 0010001 2.8346 0110001 3.4646 0010010 2.8543 0110010 3.4843 0010011 2.8740 0110011 3.5039 0010100 2.8937 0110100 3.5236 0010101 2.9134 0110101 3.5433 0010110 2.9331 0110110 3.5630 0010111 2.9528 0110111 3.5827 0011000 2.9724 0111000 3.6024 0011001 2.9921 0111001 3.6220 0011010 3.0118 0111010 3.6417 0011011 3.0315 0111011 3.6614 0011100 3.0512 0111100 3.6811 0011101 3.0709 0111101 3.7008 0011110 3.0906 0111110 3.7205 0011111 3.1102 0111111 3.7402 Note. Don’t set any higher VCOMH level than AVDD-0.3V NVCM[6:0] 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 VCOMH Voltage 4.0748 4.0945 4.1142 4.1339 4.1535 4.1732 4.1929 4.2126 4.2323 4.2520 4.2717 4.2913 4.3110 4.3307 4.3504 4.3701 Mobile Display Driver IC NVCM[6:0] 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 VCOMH Voltage 4.7047 4.7244 4.7441 4.7638 4.7835 4.8031 4.8228 4.8425 4.8622 4.8819 4.9016 4.9213 4.9409 4.9606 4.9803 5.0000 IPVCM6-0: Set the upper level of VCOM (VCOMH) on partial idle mode. Table 174. IPVCM[6:0] (Vref=2.0V, unit =V) IPVCM[6:0] VCOMH Voltage IPVCM[6:0] VCOMH Voltage 0000000 2.5000 0100000 3.1299 0000001 2.5197 0100001 3.1496 0000010 2.5394 0100010 3.1693 0000011 2.5591 0100011 3.1890 0000100 2.5787 0100100 3.2087 0000101 2.5984 0100101 3.2283 0000110 2.6181 0100110 3.2480 0000111 2.6378 0100111 3.2677 0001000 2.6575 0101000 3.2874 0001001 2.6772 0101001 3.3071 0001010 2.6969 0101010 3.3268 0001011 2.7165 0101011 3.3465 0001100 2.7362 0101100 3.3661 0001101 2.7559 0101101 3.3858 IPVCM[6:0] 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 Page 342/389 VCOMH Voltage 3.7598 3.7795 3.7992 3.8189 3.8386 3.8583 3.8780 3.8976 3.9173 3.9370 3.9567 3.9764 3.9961 4.0157 IPVCM[6:0] 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 VCOMH Voltage 4.3898 4.4094 4.4291 4.4488 4.4685 4.4882 4.5079 4.5276 4.5472 4.5669 4.5866 4.6063 4.6260 4.6457 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC IPVCM[6:0] VCOMH Voltage IPVCM[6:0] VCOMH Voltage 0001110 2.7756 0101110 3.4055 0001111 2.7953 0101111 3.4252 0010000 2.8150 0110000 3.4449 0010001 2.8346 0110001 3.4646 0010010 2.8543 0110010 3.4843 0010011 2.8740 0110011 3.5039 0010100 2.8937 0110100 3.5236 0010101 2.9134 0110101 3.5433 0010110 2.9331 0110110 3.5630 0010111 2.9528 0110111 3.5827 0011000 2.9724 0111000 3.6024 0011001 2.9921 0111001 3.6220 0011010 3.0118 0111010 3.6417 0011011 3.0315 0111011 3.6614 0011100 3.0512 0111100 3.6811 0011101 3.0709 0111101 3.7008 0011110 3.0906 0111110 3.7205 0011111 3.1102 0111111 3.7402 Note. Don’t set any higher VCOMH level than AVDD-0.3V IPVCM[6:0] 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 VCOMH Voltage 4.0354 4.0551 4.0748 4.0945 4.1142 4.1339 4.1535 4.1732 4.1929 4.2126 4.2323 4.2520 4.2717 4.2913 4.3110 4.3307 4.3504 4.3701 IPVCM[6:0] 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 VCOMH Voltage 4.6654 4.6850 4.7047 4.7244 4.7441 4.7638 4.7835 4.8031 4.8228 4.8425 4.8622 4.8819 4.9016 4.9213 4.9409 4.9606 4.9803 5.0000 Status Initial Default Value NVCM=000_0000 IPVCM=000_0000 5.3.16.2. VCOMG/ NVML[6:0]/ IPVML[6:0] VCOMG: When VCOMG = 1, low level of VCOM signal is to be fixed at AVSS. Therefore, the amplitude of VCOM signal is determined as |VCOMH – AVSS| regardless of VML setting. When VCOMG=0, the amplitude of VCOM signal is determined as |VCOMH – VCOML| NVML6-0 : Set the Amplitude of the VCOM voltage on Normal Mode. VCOML is adjusted automatically by setting the Amplitude of VCOM voltage. Table 175. NVML[6:0] (Vref=2.0V, unit =V) NVML[6:0] Amplitude Voltage NVML[6:0] Amplitude Voltage 0000000 3.0000 0100000 3.7559 0000001 3.0236 0100001 3.7795 NVML[6:0] 1000000 1000001 Amplitude Voltage 4.5118 4.5354 NVML[6:0] 1100000 1100001 Amplitude Voltage 5.2677 5.2913 Page 343/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC NVML[6:0] Amplitude Voltage NVML[6:0] Amplitude Voltage NVML[6:0] Amplitude Voltage NVML[6:0] 0000010 3.0472 0100010 3.8031 1000010 4.5591 1100010 0000011 3.0709 0100011 3.8268 1000011 4.5827 1100011 0000100 3.0945 0100100 3.8504 1000100 4.6063 1100100 0000101 3.1181 0100101 3.8740 1000101 4.6299 1100101 0000110 3.1417 0100110 3.8976 1000110 4.6535 1100110 0000111 3.1654 0100111 3.9213 1000111 4.6772 1100111 0001000 3.1890 0101000 3.9449 1001000 4.7008 1101000 0001001 3.2126 0101001 3.9685 1001001 4.7244 1101001 0001010 3.2362 0101010 3.9921 1001010 4.7480 1101010 0001011 3.2598 0101011 4.0157 1001011 4.7717 1101011 0001100 3.2835 0101100 4.0394 1001100 4.7953 1101100 0001101 3.3071 0101101 4.0630 1001101 4.8189 1101101 0001110 3.3307 0101110 4.0866 1001110 4.8425 1101110 0001111 3.3543 0101111 4.1102 1001111 4.8661 1101111 0010000 3.3780 0110000 4.1339 1010000 4.8898 1110000 0010001 3.4016 0110001 4.1575 1010001 4.9134 1110001 0010010 3.4252 0110010 4.1811 1010010 4.9370 1110010 0010011 3.4488 0110011 4.2047 1010011 4.9606 1110011 0010100 3.4724 0110100 4.2283 1010100 4.9843 1110100 0010101 3.4961 0110101 4.2520 1010101 5.0079 1110101 0010110 3.5197 0110110 4.2756 1010110 5.0315 1110110 0010111 3.5433 0110111 4.2992 1010111 5.0551 1110111 0011000 3.5669 0111000 4.3228 1011000 5.0787 1111000 0011001 3.5906 0111001 4.3465 1011001 5.1024 1111001 0011010 3.6142 0111010 4.3701 1011010 5.1260 1111010 0011011 3.6378 0111011 4.3937 1011011 5.1496 1111011 0011100 3.6614 0111100 4.4173 1011100 5.1732 1111100 0011101 3.6850 0111101 4.4409 1011101 5.1969 1111101 0011110 3.7087 0111110 4.4646 1011110 5.2205 1111110 0011111 3.7323 0111111 4.4882 1011111 5.2441 1111111 Note. Available setting range of VCOML is from VCL+0.5V to 0V. The Amplitude of VCOM cannot exceed 6V. Amplitude Voltage 5.3150 5.3386 5.3622 5.3858 5.4094 5.4331 5.4567 5.4803 5.5039 5.5276 5.5512 5.5748 5.5984 5.6220 5.6457 5.6693 5.6929 5.7165 5.7402 5.7638 5.7874 5.8110 5.8346 5.8583 5.8819 5.9055 5.9291 5.9528 5.9764 6.0000 IPVML6-0: Set the Amplitude of the VCOM voltage on partial idle mode. Table 176. IPVML[6:0] (Vref=2.0V, unit =V) IPVML[6:0] Amplitude Voltage IPVML[6:0] Amplitude Voltage IPVML[6:0] Amplitude Voltage IPVML[6:0] Amplitude Voltage Page 344/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC IPVML[6:0] Amplitude Voltage IPVML[6:0] Amplitude Voltage IPVML[6:0] Amplitude Voltage IPVML[6:0] 0000000 3.0000 0100000 3.7559 1000000 4.5118 1100000 0000001 3.0236 0100001 3.7795 1000001 4.5354 1100001 0000010 3.0472 0100010 3.8031 1000010 4.5591 1100010 0000011 3.0709 0100011 3.8268 1000011 4.5827 1100011 0000100 3.0945 0100100 3.8504 1000100 4.6063 1100100 0000101 3.1181 0100101 3.8740 1000101 4.6299 1100101 0000110 3.1417 0100110 3.8976 1000110 4.6535 1100110 0000111 3.1654 0100111 3.9213 1000111 4.6772 1100111 0001000 3.1890 0101000 3.9449 1001000 4.7008 1101000 0001001 3.2126 0101001 3.9685 1001001 4.7244 1101001 0001010 3.2362 0101010 3.9921 1001010 4.7480 1101010 0001011 3.2598 0101011 4.0157 1001011 4.7717 1101011 0001100 3.2835 0101100 4.0394 1001100 4.7953 1101100 0001101 3.3071 0101101 4.0630 1001101 4.8189 1101101 0001110 3.3307 0101110 4.0866 1001110 4.8425 1101110 0001111 3.3543 0101111 4.1102 1001111 4.8661 1101111 0010000 3.3780 0110000 4.1339 1010000 4.8898 1110000 0010001 3.4016 0110001 4.1575 1010001 4.9134 1110001 0010010 3.4252 0110010 4.1811 1010010 4.9370 1110010 0010011 3.4488 0110011 4.2047 1010011 4.9606 1110011 0010100 3.4724 0110100 4.2283 1010100 4.9843 1110100 0010101 3.4961 0110101 4.2520 1010101 5.0079 1110101 0010110 3.5197 0110110 4.2756 1010110 5.0315 1110110 0010111 3.5433 0110111 4.2992 1010111 5.0551 1110111 0011000 3.5669 0111000 4.3228 1011000 5.0787 1111000 0011001 3.5906 0111001 4.3465 1011001 5.1024 1111001 0011010 3.6142 0111010 4.3701 1011010 5.1260 1111010 0011011 3.6378 0111011 4.3937 1011011 5.1496 1111011 0011100 3.6614 0111100 4.4173 1011100 5.1732 1111100 0011101 3.6850 0111101 4.4409 1011101 5.1969 1111101 0011110 3.7087 0111110 4.4646 1011110 5.2205 1111110 0011111 3.7323 0111111 4.4882 1011111 5.2441 1111111 Note. Available setting range of VCOML is from VCL+0.5V to 0V. The Amplitude of VCOM cannot exceed 6V. Amplitude Voltage 5.2677 5.2913 5.3150 5.3386 5.3622 5.3858 5.4094 5.4331 5.4567 5.4803 5.5039 5.5276 5.5512 5.5748 5.5984 5.6220 5.6457 5.6693 5.6929 5.7165 5.7402 5.7638 5.7874 5.8110 5.8346 5.8583 5.8819 5.9055 5.9291 5.9528 5.9764 6.0000 Status Initial Default Value VCOMG = 0 NVML[6:0] = 000_0000 Page 345/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC IPVML[6:0] = 000_0000 5.3.16.3. VCIRA[2:0]/ VCIR[2:0] VCIRA2-0: VCI recycling period of Source is sustained for the number of clock cycle which is set on VCIRA2-0. VCIR2-0: VCI recycling period of VCOM is sustained for the number of clock cycle which is set on VCIR2-0. Table 177. VCIRA[2:0]/ VCIR[2:0] VCIRA2/ VCIR2 0 VCIRA1/ VCIR1 0 VCIRA0/ VCIR0 0 VCIR / VCI recycling period (Synchronized with INCLK) Sn Vcom1 (a/b) Vcom2 (c/d) 0 0 0 0 0 1 1 0.5 / 1 1 / 0.5 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1/2 1.5 / 3 2/4 2.5 / 5 3/6 2/1 3 / 1.5 4/2 5 / 2.5 6/3 1 1 1 7 3.5 / 7 7 / 3.5 Note1. clock cycle Note2. When VCI Recycling is used, VCOMH level must be larger than VCI level. Note3. INCLK means internal clock for display. In MPU I/F, INCLK is decided by CRTN. In RGB I/F, INCLK is decided by RGB_DIV. Note4. When Frame inversion .It is recommended that Do not use Source VCIR Recycling for Saving Current Figure 172. Set delay from gate output to source output and VCIR signal Page 346/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 173. Source/Vcom operating example by releated registers Status Initial Default Value VCIRA[2:0] = 100 VCIR[2:0] = 100 Page 347/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.17. SRCCTL: Source Output Control Register (F5h) Mobile Display Driver IC Inst / Para SRCCTL 1st para 2nd para 3rd para 4th para 5th para 6th para R/W R/W DCX 0 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 0 1 SEL_ - 360 GS_ - - EN - NGF SG IPSDT IPSDT IPSDT NSDT NSDT NSDT - - 2 1 0 2 1 0 SAP SAP SAP SAP - - - - 3 2 1 0 NBLK_ NBLK_ IPBLK_ IPBLK_ NDISP NDISP IPDISP IPDISP VCIR1 VCIR0 VCIR1 VCIR0 _CON1 _CON0 _CON1 _CON0 VCOM - _BLK - _OFF NBLK_ NBLK_ IPBLK_ IPBLK_ - CON1 CON0 CON1 CON0 GOCM GOCM GOCM OCM OCM - - - 2 1 0 1 0 HEX F5h 5.3.17.1. SEL_360/GS_EN/ NGF/SG SEL_360: Set the number of active Source Channel Table 178. SEL_360 SEL_360 0 1 GS_EN: Set the separated Gamma mode. Source Channels S61~S1020 Channel enable S1~S1080 Channel enable Table 179. GS_EN GS_EN 0 1 (default) Gamma set Non- separated Gamma R/G/B Seperated Gamma Description Red Gamma apply to Green and Blue. Use R/G/B separated gamma. NGF: Set the negative polarity gamma register to positive polarity gamma register or user setting value. Pleae refer to the section 4.2 SG: Set the symmetric way of negative polarity gamma voltage to positive, X-axis or Y-axis. Pleae refer to the section 4.2 Page 348/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Status Initial Default Value SEL_360 = 0 GS_EN = 1 NGF = 0 SG = 0 Mobile Display Driver IC 5.3.17.2. IPSDT[2:0]/ NSDT[2:0] IPSDT/ NSDT: Set delay amount from gate edge (end) to source output IPSDT is applied in Idle Partial mode. Table 180. IPSDT[2:0]/NSDT[2:0] NSDT2/ IPSDT2 NSDT1/ IPSDT1 NSDT0/ IPSDT0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Note. INCLK means internal clock for display. In MPU I/F, INCLK is decided by CRTN. In RGB I/F, INCLK is decided by RGB_DIV. Status Initial Delay amount of the source output 1 INCLK 2 INCLK 3 INCLK 4 INCLK 5 INCLK 6 INCLK 7 INCLK Setting Disable Default Value NSDT=001 IPSDT=001 Page 349/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.17.3. SAP[3:0] Mobile Display Driver IC SAP: Adjust the slew-rate of the operational amplifier for the source driver. If higher SAP3-0 is set, LCD panel having higher resolution or higher frame frequency can be driven because the slew-rate of the operational amplifier is increased. But these bits must be set as adequate value because the amount of fixed current of the operational amplifier is also adjusted. During non-display, when SAP3-0 =”0000,” operational amplifiers are turned off, so current consumption can be reduced. Table 181. SAP[3:0] SAP3 SAP2 SAP1 SAP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Source Amp. Current Level Amp. Stop Slow 3 Medium Slow 1 Medium Slow 2 Medium Slow 3 Medium Slow 4 Medium Fast 1 Medium Fast 2 Medium Fast 3 Medium Fast 4 Fast1 Fast2 Fast3 Fast4 (the Fastest) Slew rate[us/V] SG=0 SG=1 - Setting Disable Setting Disable 5.56 4.3 3.5 2.98 2.98 2.62 2.98 2.34 2.98 2.12 2.98 1.92 2.98 1.76 2.98 1.60 2.98 1.48 2.98 1.34 2.98 1.24 Delay[us] SG=0 SG=1 - 27.8 21.5 17.5 14.9 14.9 13.1 14.9 11.7 14.9 10.6 14.9 9.6 14.9 8.8 14.9 8.0 14.9 7.4 14.9 6.7 14.9 6.2 Status Initial Note. Panel load: R=10.5 kohm, C=55pF. Default Value SAP=0110 Page 350/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.17.4. NBLK_VCIR[1:0]/ IPBLK_VCIR[1:0]/ NDISP_CON[1:0] / IPDISP_CON[1:0] Mobile Display Driver IC NBLK_VCIR/ IPBLK_VCIR: In porch period and non-display area VCOM/Source VCIR recycling control IPBLK_VCIR is applied in Idle Partial mode When Idle mode, Source VCIR recycling do not operate. When VCOM_BLK_OFF = 0, BLK_VCIR control is valid. Table 182. NBLK_VCIR[1:0]/ IPBLK_VCIR[1:0] NBLK_VCIR1/ NBLK_VCIR0/ IPBLK_VCIR1/ IPBLK_VCIR0/ 0 0 0 1 1 0 1 1 Porch period Disable Active Disable Active Non-display area Disable Disable Active Active NDISP_CON [1:0] / IPDISP_CON [1:0]: In non-display area, Source driver operation IPDISP_CON is applied in Idle Partial mode Table 183. NDISP_CON[1:0] NDISP_CON1 NDISP_CON0 0 0 0 1 1 0 1 1 Table 184. IPDISP_CON [1:0] IPDISP_CON1 IPDISP_CON0 0 0 0 1 1 0 1 1 Status Initial Operation AMP operation Binary operation Setting Disable Setting Disable Operation Setting Disable Binary operation Setting Disable Setting Disable Default Value NBLK_VCIR=11 IPBLK_VCIR=11 NDISP_CON=00 IPDISP_CON=01 Page 351/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.17.5. VCOM_BLK_OFF/ NBLK_CON/IPBLK_CON Mobile Display Driver IC VCOM_BLK_OFF: If the VCOM_BLK_OFF is high, then in porch period VCOM does not toggle. Else, VCOM is continuously toggled in porch period. This Command is Valid in Line Inversion mode, Table 185. VCOM_BLK_OFF VCOM_BLK_OFF Operation 0 Operating in porch period 1 Not operation in porch period NBLK_CON / IPBLK_CON: In porch period, Source driver operation method. IPBLK_CON is applied in Idle partial mode Table 186. NBLK_CON[1:0] NBLK_CON1 NBLK_CON0 0 0 0 1 1 0 1 1 Operation AMP operation(Same Phase of VCOM) Binary operation(Inverted Phase of VCOM) GND Hi-Z Table 187. IPBLK_CON[1:0] IPBLK_CON1 IPBLK_CON0 0 0 0 1 1 0 1 1 Operation Setting Disable Binary operation GND Hi-Z Status Initial Default Value VCOM_BLK_OFF=1 NBLK_CON=00 IPBLK_CON=01 5.3.17.6. OCM[1:0]/GOCM[2:0] GOCM2-0: The control bits to cancel the offset voltage of the gamma amp. This register supports the line and frame offset cancellation mode. Page 352/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 188. GOCM[2:0] GOCM2 GOCM1 GOCM0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Note. GPOL: The register bit for the Gamma amp polarity. Mobile Display Driver IC Gamma amp. Offset cancellation mode selection N/A N/A 8 frame offset cancellation mode 4 frame offset cancellation mode 4 frame offset cancellation mode 2 line and 4 frame offset cancellation mode 1 line and 4 frame offset cancellation mode GPOL=”L” fix OCM1-0: The control bits to cancel the offset voltage of the source amp. This register supports the line and frame offset cancellation mode. Table 189. OCM[1:0] OCM1 OCM0 0 0 0 1 1 0 1 1 Note. POL: The register bit for the source amp polarity. Status Initial Source amp. Offset cancellation mode selection 2 line and 4 frame offset cancellation mode 1 line and 4 frame offset cancellation mode 4 frame offset cancellation mode POL=”L” fix Default Value GOCM=111 OCM=11 Figure 174. Gamma & Source driver offset cancellation method Page 353/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 175. 4-frame offset cancellation mode Figure 176. 2-frame offset cancellation mode Figure 177. Line & 4-frame offset cancellation mode Figure 178. Line & 2-frame offset cancellation mode Figure 179. Halt offset cancellation mode Page 354/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 180. 8 Frame offset cancellation mode Frame Line 4(n)th Frame 1234 POL 4(n)+1th Frame 4(n)+2th Frame 4(n)+3th Frame 4(n+1)th Frame 4(n+1)+1th Frame 4(n+1)+2th Frame 4(n+1)+3th Frame 12 12 12 12 12 12 12 Figure 181. 2 Line and 4 Frame offset cancellation mode Page 355/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC 5.3.18. IFCTL : Interface Control Register (F6h) Inst / Para IFCTL 1st para 2nd para 3rd para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 1 1 0 1 1 0 F6h 1 IPM2 IPM1 IPM0 MDT1 MDT0 0 VSM 0 R/W 1 VPL HPL DPL EPL ENDIAN 0 0 RIM RGB_ RGB_ RGB_ RGB_ 1 0 0 0 0 DIV3 DIV2 DIV1 DIV0 5.3.18.1. IPM[2:0]/ MDT[1:0]/ VSM IPM: Select the method of display expansion (Default value = 100) Figure 182. Data expansion by IMP (example of red color) Table 190. IPM[2:0] IPM 000 001 010 011 100 101 110 111 6bit Æ 8bit R[1] R[0] 0 0 0 1 1 0 1 1 DB[5] DB[4] DB[5] 0 DB[5] 1 Not defined R[2] DB[4] DB[4] DB[4] DB[4] DB[4] DB[4] DB[4] 5bit Æ 8bit R[1] 0 0 1 1 DB[3] DB[3] DB[3] Not defined R[0] 0 1 0 1 DB[2] 0 1 MDT: Select the method of display data transferring. (Refer to the 3.2 Display Data Format section.) VSM : Select Vsync Interface mode. When VSM=”1”, VSYNC interface is available. In this interface the internal display operation is synchronized with VSYNC. Data for display is written to RAM via the system interface with higher speed than for internal display operation. This method enables flicker-free display of motion pictures with the conventional interface. Page 356/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC LCDC VSYNC CSX DCX WRX S6D05A0 24 DB23-0 Figure 183. VSYNC interface (example: 24bit interface) Figure 184. Motion picture data transfer via VSYNC interface Status Initial Default Value IPM[2:0] = 100 MDT[1:0] = 00 VSM = 0 5.3.18.2. VPL/HPL/DPL/EPL VPL: Reverses the polarity of the VSYNC signal. VPL= “0”: VSYNC is low active. VPL= “1”: VSYNC is high active. HPL: Reverses the polarity of the HSYNC signal. HPL= “0”: HSYNC is low active. HPL= “1”: HSYNC is high active. DPL: Reverses the polarity of the DOTCLK signal. DPL= “0”: Display data is fetched at DOTCLK’s rising edge. DPL= “1”: Display data is fetched at DOTCLK’s falling edge. EPL: Set the polarity of ENABLE pad while using RGB interface. - EPL = “0”: ENABLE =”Low” / write data of DB[23:0] ENABLE =”High” / do not write data of DB[23:0] - EPL = “1”: ENABLE =”High” / write data of DB[23:0] ENABLE =”Low” / do not write data of DB[23:0] Page 357/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 191. Relationship between EPL, ENABLE and RAM access EPL ENABLE RAM write 0 0 Valid 0 1 Invalid 1 1 1 0 Valid Invalid Mobile Display Driver IC RAM address Updated Held Updated Held Status Initial Default Value VPL = 0 HPL = 0 DPL = 0 EPL = 1 5.3.18.3. ENDIAN/RIM ENDIAN: Select Little Endian Interface bit. At Little Endian mode, the host sends LSB data first. Figure 185. Little Endian (When MPU 65K 8bit I/F) Table 192. ENDIAN ENDIAN Data transfer mode 0 Normal (MSB first) 1 Little Endian (LSB first) Note. Little Endian is valid on only MPU 260K 9bit I/F (MDT=00), 65K 8bit, 9bit I/F mode. RIM: Specify the RGB interface mode when the RGB interface is used. These bits should be set before display operation through the RGB interface and should not be set during operation. Page 358/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Table 193. RIM RIM 0 1 COLMOD[6:4] 111 (16M color) 110 (262k color) 101 (65k color) 111 (16M color) 110 (262k color) Mobile Display Driver IC RGB Interface Mode 24- bit RGB interface (1 transfer/pixel) 18- bit RGB interface (1 transfer/pixel) 16- bit RGB interface (1 transfer/pixel) 8- bit RGB interface (3 transfer/pixel) 6- bit RGB interface (3 transfer/pixel) Status Initial Default Value ENDIAN = 0 RIM = 0 5.3.18.4. RGB_DIV[3:0] RGB_DIV3-0: Select internal clock in RGB interface mode Table 194. RGB_DIV[3:0] RGB_DIV[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note. INCLK means Internal Clock. Status Initial 24/18/16- bit RGB 16 DOTCLK 15 DOTCLK 14 DOTCLK 13 DOTCLK 12 DOTCLK 11 DOTCLK 10 DOTCLK 9 DOTCLK 17 DOTCLK 18 DOTCLK 19 DOTCLK 20 DOTCLK 21 DOTCLK 22 DOTCLK 23 DOTCLK 24 DOTCLK INCLK 8/6- bit RGB 16 x 3 DOTCLK 15 x 3 DOTCLK 14 x 3 DOTCLK 13 x 3 DOTCLK 12 x 3 DOTCLK 11 x 3 DOTCLK 10 x 3 DOTCLK 9 x 3 DOTCLK 17 x 3 DOTCLK 18 x 3 DOTCLK 19 x 3 DOTCLK 20 x 3 DOTCLK 21 x 3 DOTCLK 22 x 3 DOTCLK 23 x 3 DOTCLK 24 x 3 DOTCLK Default Value RGB_DIV = 0000 Page 359/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.19. RGAMCTL: Positive Gamma Control Register for Red (F7h) Mobile Display Driver IC Inst / Para RPGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para 9th para 10th para 11th para 12th para 13th para 14th para 15th para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 1 1 0 1 1 1 F7h RGLP RGLP RRFP RRFP RRFP RRFP RRFP RRFP 1 1 0 5 4 3 2 1 0 ROSP ROSP ROSP ROSP ROSP ROSP 1 0 0 5 4 3 2 1 0 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 05 04 03 02 01 00 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 15 14 13 12 11 10 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 25 24 23 22 21 20 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 35 34 33 32 31 30 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 45 44 43 42 41 40 R/W RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 55 54 53 52 51 50 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 65 64 63 62 61 60 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 75 74 73 72 71 70 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 85 84 83 82 81 80 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 95 94 93 92 91 90 RPKP RPKP RPKP RPKP RPKP RPKP 1 0 0 105 104 103 102 101 100 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR 1 P03 P02 P01 P00 P13 P12 P11 P10 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR 1 P23 P22 P21 P20 P33 P32 P31 P30 RGLP: The positive voltage of red color grayscale number V1 or V254 is mainly adjusted. RRFP: The positive voltage of red color grayscale number from V0 is mainly adjusted. ROSP: The positive voltage of red color grayscale number from V255 is mainly adjusted. RPKP0~RPKP10: The positive voltage of red color grayscale number from V1 to V254 is finely adjusted. Page 360/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 RGSRP0: The positive voltage of red color grayscale V5 is finely adjusted. RGSRP1: The positive voltage of red color grayscale V55 is finely adjusted. RGSRP2: The positive voltage of red color grayscale V200 is finely adjusted. RGSRP3: The positive voltage of red color grayscale V250 is finely adjusted. Status Initial Default Value RGLP : 0000 RRFP : 0000 ROSP : 001101 RPKP0 : 000001 RPKP1 : 001000 RPKP2 : 010101 RPKP3 : 011110 RPKP4 : 011111 RPKP5 : 100001 RPKP6 : 011011 RPKP7 : 010111 RPKP8 : 010000 RPKP9 : 010101 RPKP10 : 000110 RGSRP0 : 0010 RGSRP1 : 0010 RGSRP2 : 0010 RGSRP3 : 0010 Mobile Display Driver IC Page 361/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.20. RNGAMCTL: Negative Gamma Control Register for Red (F8h) Mobile Display Driver IC Inst / Para RNGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para 9th para 10th para 11th para 12th para 13th para 14th para 15th para R/W R/W DCX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 0 0 RGLN RGLN RRFN RRFN RRFN RRFN RRFN RRFN 1 0 5 4 3 2 1 0 ROSN ROSN ROSN ROSN ROSN ROSN 0 0 5 4 3 2 1 0 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 05 04 03 02 01 00 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 15 14 13 12 11 10 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 25 24 23 22 21 20 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 35 34 33 32 31 30 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 45 44 43 42 41 40 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 55 54 53 52 51 50 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 65 64 63 62 61 60 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 75 74 73 72 71 70 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 85 84 83 82 81 80 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 95 94 93 92 91 90 RPKN RPKN RPKN RPKN RPKN RPKN 0 0 105 104 103 102 101 100 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR N03 N02 N01 N00 N13 N12 N11 N10 RGSR RGSR RGSR RGSR RGSR RGSR RGSR RGSR N23 N22 N21 N20 N33 N32 N31 N30 HEX F8h RGLN: The negative voltage of red color grayscale V1 or V254 is mainly adjusted. RRFN: The negative voltage of red color grayscale number from V0 is mainly adjusted. ROSN: The negative voltage of red color grayscale number from V255 is mainly adjusted. RPKN0~RPKN10: The negative red color voltage of grayscale number from V1 to V254 is finely adjusted. Page 362/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 RGSRN0: The negative voltage of red color grayscale V5 is finely adjusted. RGSRN1: The negative voltage of red color grayscale V55 is finely adjusted. RGSRN2: The negative voltage of red color grayscale V200 is finely adjusted. RGSRN3: The negative voltage of red color grayscale V250 is finely adjusted. Status Initial Default Value RGLN : 0000 RRFN : 0000 ROSN : 001101 RPKN0 : 000001 RPKN1 : 001000 RPKN2 : 010101 RPKN3 : 011110 RPKN4 : 011111 RPKN5 : 100001 RPKN6 : 011011 RPKN7 : 010111 RPKN8 : 010000 RPKN9 : 010101 RPKN10 : 000110 RGSRN0 : 0010 RGSRN1 : 0010 RGSRN2 : 0010 RGSRN3 : 0010 Mobile Display Driver IC Page 363/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.21. GGAMCTL: Positive Gamma Control Register for Green (F9h) Mobile Display Driver IC Inst / Para R/W GPGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para R/W 9th para 10th para 11th para 12th para 13th para 14th para 15th para DCX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 0 1 GGLP GGLP GRFP GRFP GRFP GRFP GRFP GRFP 1 0 5 4 3 2 1 0 GOSP GOSP GOSP GOSP GOSP GOSP 0 0 5 4 3 2 1 0 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 05 04 03 02 01 00 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 15 14 13 12 11 10 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 25 24 23 22 21 20 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 35 34 33 32 31 30 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 45 44 43 42 41 40 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 55 54 53 52 51 50 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 65 64 63 62 61 60 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 75 74 73 72 71 70 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 85 84 83 82 81 80 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 95 94 93 92 91 90 GPKP GPKP GPKP GPKP GPKP GPKP 0 0 105 104 103 102 101 100 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR P03 P02 P01 P00 P13 P12 P11 P10 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR P23 P22 P21 P20 P33 P32 P31 P30 HEX F9h GGLP: The positive voltage of green color grayscale V1 or V254 is mainly adjusted. GRFP: The positive voltage of green color grayscale number from V0 is mainly adjusted. GOSP: The positive voltage of green color grayscale number from V255 is mainly adjusted. GPKP0~GPKP10: The positive voltage of green color grayscale number from V1 to V254 is finely adjusted. Page 364/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 GGSRP0: The positive voltage of green color grayscale V5 is finely adjusted. GGSRP1: The positive voltage of green color grayscale V55 is finely adjusted. GGSRP2: The positive voltage of green color grayscale V200 is finely adjusted. GGSRP3: The positive voltage of green color grayscale V250 is finely adjusted. Status Initial Default Value GGLP : 0000 GRFP : 0000 GOSP : 001101 GPKP0 : 000001 GPKP1 : 001000 GPKP2 : 010101 GPKP3 : 011110 GPKP4 : 011111 GPKP5 : 100001 GPKP6 : 011011 GPKP7 : 010111 GPKP8 : 010000 GPKP9 : 010101 GPKP10 : 000110 GGSRP0 : 0010 GGSRP1 : 0010 GGSRP2 : 0010 GGSRP3 : 0010 Mobile Display Driver IC Page 365/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.22. GNGAMCTL: Negative Gamma Control Register for Green (FAh) Mobile Display Driver IC Inst / Para R/W GNGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para R/W 9th para 10th para 11th para 12th para 13th para 14th para 15th para DCX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 1 0 GGLN GGLN GRFN GRFN GRFN GRFN GRFN GRFN 1 0 5 4 3 2 1 0 GOSN GOSN GOSN GOSN GOSN GOSN 0 0 5 4 3 2 1 0 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 05 04 03 02 01 00 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 15 14 13 12 11 10 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 25 24 23 22 21 20 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 35 34 33 32 31 30 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 45 44 43 42 41 40 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 55 54 53 52 51 50 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 65 64 63 62 61 60 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 75 74 73 72 71 70 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 85 84 83 82 81 80 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 95 94 93 92 91 90 GPKN GPKN GPKN GPKN GPKN GPKN 0 0 105 104 103 102 101 100 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR N03 N02 N01 N00 N13 N12 N11 N10 GGSR GGSR GGSR GGSR GGSR GGSR GGSR GGSR N23 N22 N21 N20 N33 N32 N31 N30 HEX FAh GGLN: The negative voltage of green color grayscale V1 or V254 is mainly adjusted. GRFN: The negative voltage of green color grayscale number from V0 is mainly adjusted. GOSN: The negative voltage of green color grayscale number from V255 is mainly adjusted. GPKN0~GPKN10: The negative green color voltage of grayscale number from V1 to V254 is finely adjusted. Page 366/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 GGSRN0: The negative voltage of green color grayscale V5 is finely adjusted. GGSRN1: The negative voltage of green color grayscale V55 is finely adjusted. GGSRN2: The negative voltage of green color grayscale V200 is finely adjusted. GGSRN3: The negative voltage of green color grayscale V250 is finely adjusted. Status Initial Default Value GGLN : 0000 GRFN : 0000 GOSN : 001101 GPKN0 : 000001 GPKN1 : 001000 GPKN2 : 010101 GPKN3 : 011110 GPKN4 : 011111 GPKN5 : 100001 GPKN6 : 011011 GPKN7 : 010111 GPKN8 : 010000 GPKN9 : 010101 GPKN10 : 000110 GGSRN0 : 0010 GGSRN1 : 0010 GGSRN2 : 0010 GGSRN3 : 0010 Mobile Display Driver IC Page 367/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.23. BGAMCTL : Positive Gamma Control Register for Blue (FBh) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX BPGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para R/W 9th para 10th para 11th para 12th para 13th para 14th para 15th para 0 1 1 1 1 1 0 1 1 FBh BGLP BGLP BRFP BRFP BRFP BRFP BRFP BRFP 1 1 0 5 4 3 2 1 0 BOSP BOSP BOSP BOSP BOSP BOSP 1 0 0 5 4 3 2 1 0 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 05 04 03 02 01 00 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 15 14 13 12 11 10 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 25 24 23 22 21 20 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 35 34 33 32 31 30 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 45 44 43 42 41 40 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 55 54 53 52 51 50 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 65 64 63 62 61 60 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 75 74 73 72 71 70 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 85 84 83 82 81 80 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 95 94 93 92 91 90 BPKP BPKP BPKP BPKP BPKP BPKP 1 0 0 105 104 103 102 101 100 BGSR BGSR BGSR BGSR BGSR BGSR BGSR BGSR 1 P03 P02 P01 P00 P13 P12 P11 P10 BGSR BGSR BGSR BGSR BGSR BGSR BGSR BGSR 1 P23 P22 P21 P20 P33 P32 P31 P30 BGLP: The positive voltage of blue color grayscale V1 or V254 is mainly adjusted. BRFP: The positive voltage of blue color grayscale number from V0 is mainly adjusted. Page 368/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC BOSP: The positive voltage of blue color grayscale number from V255 is mainly adjusted. BPKP0~BPKP10: The positive voltage of blue color grayscale number from V1 to V254 is finely adjusted. BGSRP0: The positive voltage of blue color grayscale V5 is finely adjusted. BGSRP1: The positive voltage of blue color grayscale V55 is finely adjusted. BGSRP2: The positive voltage of blue color grayscale V200 is finely adjusted. BGSRP3: The positive voltage of blue color grayscale V250 is finely adjusted. Status Initial Default Value BGLP : 0000 BRFP : 0000 BOSP : 001101 BPKP0 : 000001 BPKP1 : 001000 BPKP2 : 010101 BPKP3 : 011110 BPKP4 : 011111 BPKP5 : 100001 BPKP6 : 011011 BPKP7 : 010111 BPKP8 : 010000 BPKP9 : 010101 BPKP10 : 000110 BGSRP0 : 0010 BGSRP1 : 0010 BGSRP2 : 0010 BGSRP3 : 0010 Page 369/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.24. BNGAMCTL: Negative Gamma Control Register for Blue(FCh) Mobile Display Driver IC Inst / Para R/W DCX D7 D6 D5 D4 D3 D2 D1 D0 HEX BNGAMCTL 1st para 2nd para 3rd para 4th para 5th para 6th para 7th para 8th para R/W 9th para 10th para 11th para 12th para 13th para 14th para 15th para 0 1 1 1 1 1 1 0 0 FCh BGLN BGLN BRFN BRFN BRFN BRFN BRFN BRFN 1 1 0 5 4 3 2 1 0 BOSN BOSN BOSN BOSN BOSN BOSN 1 0 0 5 4 3 2 1 0 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 05 04 03 02 01 00 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 15 14 13 12 11 10 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 25 24 23 22 21 20 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 35 34 33 32 31 30 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 45 44 43 42 41 40 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 55 54 53 52 51 50 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 65 64 63 62 61 60 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 75 74 73 72 71 70 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 85 84 83 82 81 80 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 95 94 93 92 91 90 BPKN BPKN BPKN BPKN BPKN BPKN 1 0 0 105 104 103 102 101 100 BGSR BGSR BGSR BGSR BGSR BGSR BGSR BGSR 1 N03 N02 N01 N00 N13 N12 N11 N10 BGSR BGSR BGSR BGSR BGSR BGSR BGSR BGSR 1 N23 N22 N21 N20 N33 N32 N31 N30 BGLN: The negative voltage of blue color grayscale number from V1 or V254 is mainly adjusted. BRFN: The negative voltage of blue color grayscale number from V0 is mainly adjusted. Page 370/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC BOSN: The negative voltage of blue color grayscale number from V255 is mainly adjusted. BPKN0~BPKN10: The negative blue color voltage of grayscale number from V1 to V254 is finely adjusted. BGSRN0: The negative voltage of blue color grayscale V5 is finely adjusted. BGSRN1: The negative voltage of blue color grayscale V55 is finely adjusted. BGSRN2: The negative voltage of blue color grayscale V200 is finely adjusted. BGSRN3: The negative voltage of blue color grayscale V250 is finely adjusted. Status Initial Default Value BGLN : 0000 BRFN : 0000 BOSN : 001101 BPKN0 : 000001 BPKN1 : 001000 BPKN2 : 010101 BPKN3 : 011110 BPKN4 : 011111 BPKN5 : 100001 BPKN6 : 011011 BPKN7 : 010111 BPKN8 : 010000 BPKN9 : 010101 BPKN10 : 000110 BGSRN0 : 0010 BGSRN1 : 0010 BGSRN2 : 0010 BGSRN3 : 0010 Page 371/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.25. GATECTL: Gate Control Register (FDh) Mobile Display Driver IC Inst / Para GATECTL 1st para 2nd para 3rd para R/W DCX 0 1 R/W 1 1 D7 D6 D5 D4 D3 D2 D1 D0 HEX 1 1 1 1 1 1 0 1 FDh 0 IPNO2 IPNO1 IPNO0 0 NNO2 NNO1 NNO0 0 0 NL5 NL4 NL3 NL2 NL1 NL0 0 0 0 SCN4 SCN3 SCN2 SCN1 SCN0 5.3.25.1. IPNO/NNO IPNO/NNO: Set amount of non-overlap for the gate output. IPNO is applied in Idle Partial mode. Table 195. IPNO[2:0]/ NNO[2:0] IPNO2 IPNO1 IPNO0 / NNO2 / NNO1 /NNO0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Note1. The amount of non-overlap time is defined from starting time of 1H. Note2. INCLK means internal clock for display. In MPU I/F, INCLK is decided by CRTN. In RGB I/F, INCLK is decided by RGB_DIV. Amount of non-overlap Setting disable 1 INCLK 2 INCLK 3 INCLK 4 INCLK 5 INCLK 6 INCLK 7 INCLK Status Initial Default Value IPNO[2:0] = 001 NNO[2:0] = 001 Page 372/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 5.3.25.2. NL Mobile Display Driver IC NL5–0: Specifies the number of horizontal lines to be driven. The number of lines can be adjusted in units of eight. Table 196. NL bits and drive duty(When SCN=”00000”) NL5-0 Display Size 000000 000001 011101 011110 011100 320RGB X 240 320RGB X 248 111011 320RGB X 480 111100 111111 LCD Raster Rows Settng Disable 240 248 480 Settng Disable Status Initial 5.3.25.3. SCN SCN4–0: Set the scanning start position of the gate driver Default Value NL[5:0] = 111011 Table 197. SCN bits and drive duty SCN4-0 00000 00001 00010 11101 11110 11111 Note1. Ensure that NL+SCN 480 Line GS=0 G1 G9 G17 Start Position GS=1 G480 G472 G464 233 241 Setting Disable 248 240 Setting Disable Page 373/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Figure 186. Gate Scan Position Control Status Initial Default Value SCN[4:0] = 00000 Page 374/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC CHAPTER 6 APPENDIX 6.1 Application Circuit 6.2 External Component 6.3 PAD Center Coordinates 6.4 Display Module Default Position Page 375/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 6 APPENDIX 6.1. APPLICATION CIRCUIT A typical application circuit is shown in following figure. Mobile Display Driver IC Figure 187. Application circuit Page 376/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 6.2. EXTERNAL COMPONENT Table 198. External components Name Device C1 Capacitor C2 Capacitor C3 Capacitor C4 Capacitor C5 Capacitor C6 Capacitor C7 Capacitor C8 Capacitor C9 Capacitor C10 Capacitor C11 Capacitor C12 Capacitor C13 Capacitor C14 Capacitor C15 Capacitor C16 Capacitor C17 Capacitor C18 Capacitor C19 Capacitor R1 Resistor R2 Resistor Value 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 100 Ohm 100 Ohm Connection VGH – GND VGL – GND C22M – C22P C21M – C21P VCI1 - GND C11M – C11P C12M – C12P C13M – C13P C14M – C14P C31M – C31P C32M – C32P VCL – GND AVDD1 – GND AVDD2 – GND VDD – GND VREF – GND GVDD – GND VCOMH - GND VCOML – GND MDP – MDN MSP - MSN D1 Diode - (+)VGL – GND(-) Note. Component C16 (described in gray-color) is optional for this application. Mobile Display Driver IC Note 25V 16V 25V 16V 6V 10V 10V 10V 10V Maximum 6V Ratings 6V Voltage 6V 10V 10V 6V 6V 6V 6V 6V 6V 6V VF < 0.4V (@ IF = 20mA, Ta = 25 ) VR ≥ max.25V Page 377/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 6.3. PAD CENTER COORDINATES Table 199. Pad center coordinates [Unit: µm] Mobile Display Driver IC Note. DUMMY_VSS3 pins show VSS3 potential during normal operating condition. Page 378/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Note. DUMMY_VGH and DUMMY_VGL pins show VGH, VGL potential during normal operating condition. These pins should be floated. DUMMY_VSS3 pins show VSS3 potential during normal operating condition. Page 379/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Note. DUMMY_VSS3 pins show VSS3 potential during normal operating condition. DUMMY_VSS pins show VSS potential during normal operating condition. Page 380/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Note. DUMMY pins between gate and source show floating state during normal operating condition. Page 381/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Page 382/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Page 383/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Page 384/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Page 385/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Page 386/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Note. DUMMY pins between gate and source show floating state during normal operating condition. Page 387/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 Mobile Display Driver IC Note. DUMMY_VSS pins show VSS potential during normal operating condition. Page 388/389 2008-12-29 S6D05A0 Data Sheet_ REV 1.10 6.4. DISPLAY MODULE DEFAULT POSITION Mobile Display Driver IC The default position (display driver, glass, filter order, etc) of the display module is always as follow, when MADCTL’s (36h) parameter is D0h. The color filter is always RGB (if color filters are used). Figure 188. Display module default position Page 389/389 2008-12-29

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